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-rw-r--r--arch/arm/cpu/arm926ejs/lpc32xx/clk.c10
-rw-r--r--arch/arm/cpu/armv7/ls102xa/cpu.c15
-rw-r--r--arch/arm/cpu/armv7/nonsec_virt.S14
-rw-r--r--arch/arm/cpu/armv7/sunxi/board.c8
4 files changed, 36 insertions, 11 deletions
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
index 1ef8a36..f5e2103 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
@@ -54,12 +54,12 @@ unsigned int get_hclk_pll_rate(void)
if (fref > 27000000ULL || fref < 1000000ULL)
return 0;
- fout = fref * m_div;
- if (val & CLK_HCLK_PLL_FEEDBACK) {
- fcco = fout;
+ fcco = fref * m_div;
+ fout = fcco;
+ if (val & CLK_HCLK_PLL_FEEDBACK)
+ fcco *= p_div;
+ else
do_div(fout, p_div);
- } else
- fcco = fout * p_div;
if (fcco > 320000000ULL || fcco < 156000000ULL)
return 0;
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 8dd95d9..e2eb5f3 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -13,6 +13,8 @@
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
+#include <config.h>
+#include <fsl_wdog.h>
#include "fsl_epu.h"
@@ -354,3 +356,16 @@ void smp_kick_all_cpus(void)
asm volatile("sev");
}
#endif
+
+void reset_cpu(ulong addr)
+{
+ struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+ clrbits_be16(&wdog->wcr, WCR_SRS);
+
+ while (1) {
+ /*
+ * Let the watchdog trigger
+ */
+ }
+}
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 30d81db..31d1c9e 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -53,6 +53,20 @@ _secure_monitor:
bl psci_arch_init
#endif
+#ifdef CONFIG_ARM_ERRATA_773022
+ mrc p15, 0, r5, c1, c0, 1
+ orr r5, r5, #(1 << 1)
+ mcr p15, 0, r5, c1, c0, 1
+ isb
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_774769
+ mrc p15, 0, r5, c1, c0, 1
+ orr r5, r5, #(1 << 25)
+ mcr p15, 0, r5, c1, c0, 1
+ isb
+#endif
+
mrc p15, 0, r5, c1, c1, 0 @ read SCR
bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
orr r5, r5, #0x31 @ enable NS, AW, FW bits
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index b40198b..d11365b 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -21,6 +21,7 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
+#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
#include <asm/arch/tzpc.h>
@@ -152,7 +153,7 @@ u32 spl_boot_device(void)
* binary over USB. If it is found, it determines where SPL was
* read from.
*/
- if (readl(4) != 0x4E4F4765 || readl(8) != 0x3054422E) /* eGON.BT0 */
+ if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
return BOOT_DEVICE_BOARD;
/* The BROM will try to boot from mmc0 first, so try that first. */
@@ -198,11 +199,6 @@ void board_init_f(ulong dummy)
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
sunxi_board_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- board_init_r(NULL, 0);
}
#endif