diff options
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/board.c | 12 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/clocks-common.c | 21 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/emif-common.c | 50 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/hwinit-common.c | 44 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/Kconfig | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/sdram.c | 183 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/u-boot-spl.lds | 2 |
8 files changed, 126 insertions, 196 deletions
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index b6db23e..399b07c 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -45,10 +45,10 @@ void lpc32xx_uart_init(unsigned int uart_id) #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_platdata lpc32xx_uart[] = { - { UART3_BASE, 2, CONFIG_SYS_NS16550_CLK }, - { UART4_BASE, 2, CONFIG_SYS_NS16550_CLK }, - { UART5_BASE, 2, CONFIG_SYS_NS16550_CLK }, - { UART6_BASE, 2, CONFIG_SYS_NS16550_CLK }, + { .base = UART3_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = UART4_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = UART5_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = UART6_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, }; #if defined(CONFIG_LPC32XX_HSUART) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index e8d5be3..a99cbf9 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -40,14 +40,14 @@ DECLARE_GLOBAL_DATA_PTR; #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_platdata am33xx_serial[] = { - { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, # ifdef CONFIG_SYS_NS16550_COM2 - { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, # ifdef CONFIG_SYS_NS16550_COM3 - { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK }, - { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK }, - { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK }, - { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, # endif # endif }; diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index e28b795..367d224 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -769,7 +769,7 @@ void lock_dpll(u32 const base) wait_for_lock(base); } -void setup_clocks_for_console(void) +static void setup_clocks_for_console(void) { /* Do not add any spl_debug prints in this function */ clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, @@ -853,14 +853,31 @@ void do_disable_clocks(u32 const *clk_domains, disable_clock_domain(clk_domains[i]); } -void prcm_init(void) +/** + * setup_early_clocks() - Setup early clocks needed for SoC + * + * Setup clocks for console, SPL basic initialization clocks and initialize + * the timer. This is invoked prior prcm_init. + */ +void setup_early_clocks(void) { switch (omap_hw_init_context()) { case OMAP_INIT_CONTEXT_SPL: case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: + setup_clocks_for_console(); enable_basic_clocks(); timer_init(); + /* Fall through */ + } +} + +void prcm_init(void) +{ + switch (omap_hw_init_context()) { + case OMAP_INIT_CONTEXT_SPL: + case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: + case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: scale_vcores(*omap_vcores); setup_dplls(); setup_warmreset_time(); diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index bf7bf26..697d6e0 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -163,7 +163,11 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); + if (!is_dra7xx()) + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); + else + writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw); + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); @@ -246,33 +250,39 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; - u32 reg, i; + u32 reg, i, phy; emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; + phy = readl(&emif->emif_ddr_phy_ctrl_1); /* Update PHY_REG_RDDQS_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7; - for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) { - reg = readl(emif_phy_status++); - writel(reg, emif_ext_phy_ctrl_reg++); - writel(reg, emif_ext_phy_ctrl_reg++); - } + if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)) + for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; - for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { - reg = readl(emif_phy_status++); - writel(reg, emif_ext_phy_ctrl_reg++); - writel(reg, emif_ext_phy_ctrl_reg++); - } + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12]; + if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)) + for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; - for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { - reg = readl(emif_phy_status++); - writel(reg, emif_ext_phy_ctrl_reg++); - writel(reg, emif_ext_phy_ctrl_reg++); - } + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17]; + if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)) + for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } /* Disable Leveling */ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); @@ -323,8 +333,10 @@ static void dra7_ddr3_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - if (warm_reset()) + if (warm_reset()) { emif_reset_phy(base); + writel(0x0, &emif->emif_pwr_mgmt_ctrl); + } do_ext_phy_settings(base, regs); writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK, @@ -1317,6 +1329,8 @@ void dmm_init(u32 base) &hw_lisa_map_regs->dmm_lisa_map_1); writel(lisa_map_regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); + + setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK); } /* diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 80794f9..99634fd 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -97,21 +97,36 @@ int arch_cpu_init(void) } #endif /* CONFIG_ARCH_CPU_INIT */ -/* - * Routine: s_init - * Description: Does early system init of watchdog, muxing, andclocks +/** + * do_board_detect() - Detect board description + * + * Function to detect board description. This is expected to be + * overridden in the SoC family board file where desired. + */ +void __weak do_board_detect(void) +{ +} + +void s_init(void) +{ +} + +/** + * early_system_init - Does Early system initialization. + * + * Does early system init of watchdog, muxing, andclocks * Watchdog disable is done always. For the rest what gets done - * depends on the boot mode in which this function is executed - * 1. s_init of SPL running from SRAM - * 2. s_init of U-Boot running from FLASH - * 3. s_init of U-Boot loaded to SDRAM by SPL - * 4. s_init of U-Boot loaded to SDRAM by ROM code using the + * depends on the boot mode in which this function is executed when + * 1. SPL running from SRAM + * 2. U-Boot running from FLASH + * 3. U-Boot loaded to SDRAM by SPL + * 4. U-Boot loaded to SDRAM by ROM code using the * Configuration Header feature * Please have a look at the respective functions to see what gets * done in each of these cases * This function is called with SRAM stack. */ -void s_init(void) +void early_system_init(void) { init_omap_revision(); hw_data_init(); @@ -125,16 +140,17 @@ void s_init(void) set_mux_conf_regs(); #ifdef CONFIG_SPL_BUILD srcomp_enable(); - setup_clocks_for_console(); - do_io_settings(); #endif + setup_early_clocks(); + do_board_detect(); prcm_init(); } #ifdef CONFIG_SPL_BUILD void board_init_f(ulong dummy) { + early_system_init(); #ifdef CONFIG_BOARD_EARLY_INIT_F board_early_init_f(); #endif @@ -143,6 +159,12 @@ void board_init_f(ulong dummy) } #endif +int arch_cpu_init_dm(void) +{ + early_system_init(); + return 0; +} + /* * Routine: wait_for_command_complete * Description: Wait for posting to finish on watchdog diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index bfa264e..026bf24 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -12,9 +12,11 @@ config TARGET_OMAP5_UEVM config TARGET_DRA7XX_EVM bool "TI DRA7XX" + select TI_I2C_BOARD_DETECT config TARGET_BEAGLE_X15 bool "BeagleBoard X15" + select TI_I2C_BOARD_DETECT endchoice diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index a8d63c2..7dc5bb7 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -137,81 +137,6 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { .emif_rd_wr_exec_thresh = 0x40000305 }; -const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { - .sdram_config_init = 0x61851ab2, - .sdram_config = 0x61851ab2, - .sdram_config2 = 0x08000000, - .ref_ctrl = 0x000040F1, - .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xCCCF36B3, - .sdram_tim2 = 0x308F7FDA, - .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190B, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400B, - .emif_ddr_phy_ctlr_1 = 0x0E24400B, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00910091, - .emif_ddr_ext_phy_ctrl_3 = 0x00950095, - .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, - .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 -}; - -const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { - .sdram_config_init = 0x61851B32, - .sdram_config = 0x61851B32, - .sdram_config2 = 0x08000000, - .ref_ctrl = 0x000040F1, - .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xCCCF36B3, - .sdram_tim2 = 0x308F7FDA, - .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190B, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400B, - .emif_ddr_phy_ctlr_1 = 0x0E24400B, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00910091, - .emif_ddr_ext_phy_ctrl_3 = 0x00950095, - .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, - .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 -}; - -const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { - .sdram_config_init = 0x61862B32, - .sdram_config = 0x61862B32, - .sdram_config2 = 0x08000000, - .ref_ctrl = 0x0000514C, - .ref_ctrl_final = 0x0000144A, - .sdram_tim1 = 0xD113781C, - .sdram_tim2 = 0x305A7FDA, - .sdram_tim3 = 0x409F86A8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x5007190B, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400D, - .emif_ddr_phy_ctlr_1 = 0x0E24400D, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, - .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9, - .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, - .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 -}; - const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, @@ -220,53 +145,6 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .is_ma_present = 0x1 }; -/* - * DRA752 EVM board has 1.5 GB of memory - * EMIF1 --> 2Gb * 2 = 512MB - * EMIF2 --> 2Gb * 4 = 1GB - * so mapping 1GB interleaved and 512MB non-interleaved - */ -const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = { - .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0x80640300, - .dmm_lisa_map_2 = 0xC0500220, - .dmm_lisa_map_3 = 0xFF020100, - .is_ma_present = 0x1 -}; - -/* - * DRA752 EVM EMIF1 ONLY CONFIGURATION - */ -const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { - .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0x0, - .dmm_lisa_map_2 = 0x80500100, - .dmm_lisa_map_3 = 0xFF020100, - .is_ma_present = 0x1 -}; - -/* - * DRA752 EVM EMIF2 ONLY CONFIGURATION - */ -const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { - .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0x0, - .dmm_lisa_map_2 = 0x80600200, - .dmm_lisa_map_3 = 0xFF020100, - .is_ma_present = 0x1 -}; - -/* - * DRA722 EVM EMIF1 CONFIGURATION - */ -const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { - .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0x0, - .dmm_lisa_map_2 = 0x80600100, - .dmm_lisa_map_3 = 0xFF020100, - .is_ma_present = 0x1 -}; - static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) { switch (omap_revision()) { @@ -280,25 +158,9 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_532_mhz_2cs_es2; break; case OMAP5432_ES2_0: + default: *regs = &emif_regs_ddr3_532_mhz_1cs_es2; break; - case DRA752_ES1_0: - case DRA752_ES1_1: - case DRA752_ES2_0: - switch (emif_nr) { - case 1: - *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; - break; - case 2: - *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1; - break; - } - break; - case DRA722_ES1_0: - *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; - break; - default: - *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; } } @@ -313,16 +175,9 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs case OMAP5430_ES2_0: case OMAP5432_ES1_0: case OMAP5432_ES2_0: + default: *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; break; - case DRA752_ES1_0: - case DRA752_ES1_1: - case DRA752_ES2_0: - *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2; - break; - case DRA722_ES1_0: - default: - *dmm_lisa_regs = &lisa_map_2G_x_2; } } @@ -643,11 +498,12 @@ static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs) u32 *emif_ext_phy_ctrl_base = 0; u32 emif_nr; const u32 *ext_phy_ctrl_const_regs; - u32 i, hw_leveling, size; + u32 i, hw_leveling, size, phy; emif_nr = (base == EMIF1_BASE) ? 1 : 2; hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT; + phy = regs->emif_ddr_phy_ctlr_1_init; emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1); @@ -657,18 +513,35 @@ static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs) writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]); writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]); - if (!hw_leveling) { - /* - * Copy the predefined PHY register values - * in case of sw leveling - */ - for (i = 1; i < 25; i++) { + /* + * Copy the predefined PHY register values + * if leveling is disabled. + */ + if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK) + for (i = 1; i < 6; i++) { writel(ext_phy_ctrl_const_regs[i], &emif_ext_phy_ctrl_base[i * 2]); writel(ext_phy_ctrl_const_regs[i], &emif_ext_phy_ctrl_base[i * 2 + 1]); } - } else { + + if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK) + for (i = 6; i < 11; i++) { + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2]); + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2 + 1]); + } + + if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK) + for (i = 11; i < 25; i++) { + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2]); + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2 + 1]); + } + + if (hw_leveling) { /* * Write the init value for HW levling to occur */ diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds index 4df339c..cc427c3 100644 --- a/arch/arm/cpu/armv8/u-boot-spl.lds +++ b/arch/arm/cpu/armv8/u-boot-spl.lds @@ -54,6 +54,8 @@ SECTIONS *(.__end) } >.sram + _image_binary_end = .; + .bss_start : { . = ALIGN(8); KEEP(*(.__bss_start)); |