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-rw-r--r--arch/arm/cpu/armv7/am33xx/clock_am43xx.c3
-rw-r--r--arch/arm/cpu/armv7/exynos/spl_boot.c1
-rw-r--r--arch/arm/cpu/armv7/keystone/ddr3.c5
-rw-r--r--arch/arm/cpu/armv7/omap-common/emif-common.c4
-rw-r--r--arch/arm/cpu/armv7/omap-common/lowlevel_init.S2
-rw-r--r--arch/arm/cpu/armv7/omap3/lowlevel_init.S2
-rw-r--r--arch/arm/cpu/armv7/omap5/sdram.c83
-rw-r--r--arch/arm/cpu/armv7/start.S7
-rw-r--r--arch/arm/cpu/armv7/sunxi/Makefile5
-rw-r--r--arch/arm/cpu/armv7/sunxi/board.c46
-rw-r--r--arch/arm/cpu/armv7/sunxi/config.mk2
-rw-r--r--arch/arm/cpu/armv7/sunxi/dram_helpers.c37
-rw-r--r--arch/arm/cpu/armv7/sunxi/fel_utils.S42
-rw-r--r--arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds82
14 files changed, 183 insertions, 138 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 31188c8..529a119 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -118,4 +118,7 @@ void enable_basic_clocks(void)
/* Select the Master osc clk as Timer2 clock source */
writel(0x1, &cmdpll->clktimer2clk);
+
+ /* For OPP100 the mac clock should be /5. */
+ writel(0x4, &cmdpll->clkselmacclk);
}
diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c
index bc237c9..c7f943e 100644
--- a/arch/arm/cpu/armv7/exynos/spl_boot.c
+++ b/arch/arm/cpu/armv7/exynos/spl_boot.c
@@ -309,4 +309,3 @@ void board_init_r(gd_t *id, ulong dest_addr)
while (1)
;
}
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
index 923906a..dfb27b5 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -263,17 +263,14 @@ static void ddr3_map_ecc_cic2_irq(u32 base)
}
#endif
-void ddr3_init_ecc(u32 base)
+void ddr3_init_ecc(u32 base, u32 ddr3_size)
{
- u32 ddr3_size;
-
if (!ddr3_ecc_support_rmw(base)) {
ddr3_disable_ecc(base);
return;
}
ddr3_ecc_init_range(base);
- ddr3_size = ddr3_get_size();
ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
/* mapping DDR3 ECC system interrupt from CIC2 to GIC */
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index e601ba1..c01a98f 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -252,6 +252,8 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+ writel(regs->sdram_config_init, &emif->emif_sdram_config);
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
* and RL =7. As the default values of the Mode Registers are not
@@ -265,7 +267,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
- writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
/*
@@ -274,6 +275,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
*/
if (is_dra7xx()) {
do_ext_phy_settings(base, regs);
+ writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
} else {
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 86c0e42..e19c7ae 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -19,7 +19,7 @@
ENTRY(save_boot_params)
ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
str r0, [r1]
- bx lr
+ b save_boot_params_ret
ENDPROC(save_boot_params)
ENTRY(set_pl310_ctrl_reg)
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index 78577b1..80cb263 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -23,7 +23,7 @@ ENTRY(save_boot_params)
ldr r5, [r0, #0x4]
and r5, r5, #0xff
str r5, [r4]
- bx lr
+ b save_boot_params_ret
ENDPROC(save_boot_params)
#endif
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 7d8cec0..5f8daa1 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -141,7 +141,8 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
@@ -151,10 +152,10 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@@ -165,7 +166,8 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
@@ -175,10 +177,10 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@@ -186,18 +188,19 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
};
const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
- .sdram_config_init = 0x61851AB2,
- .sdram_config = 0x61851AB2,
+ .sdram_config_init = 0x61862B32,
+ .sdram_config = 0x61862B32,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x027F88A8,
+ .ref_ctrl = 0x0000493E,
+ .ref_ctrl_final = 0x0000144A,
+ .sdram_tim1 = 0xD113781C,
+ .sdram_tim2 = 0x308F7FE3,
+ .sdram_tim3 = 0x009F86A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400A,
- .emif_ddr_phy_ctlr_1 = 0x0024400A,
+ .emif_ddr_phy_ctlr_1_init = 0x0E24400D,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400D,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
.emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
@@ -420,22 +423,22 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
- 0x00BB00BB,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
+ 0x00980098,
+ 0x00340034,
+ 0x00350035,
+ 0x00340034,
+ 0x00310031,
+ 0x00340034,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
+ 0x00480048,
+ 0x004A004A,
+ 0x00520052,
+ 0x00550055,
+ 0x00500050,
0x00000000,
0x00600020,
0x40010080,
@@ -449,22 +452,22 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
- 0x00BB00BB,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
+ 0x00980098,
+ 0x00330033,
+ 0x00330033,
+ 0x002F002F,
+ 0x00320032,
+ 0x00310031,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
+ 0x00520052,
+ 0x00520052,
+ 0x00470047,
+ 0x00490049,
+ 0x00500050,
0x00000000,
0x00600020,
0x40010080,
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 70048c1..9b49ece 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -31,9 +31,12 @@
*************************************************************************/
.globl reset
+ .globl save_boot_params_ret
reset:
- bl save_boot_params
+ /* Allow the board to save important registers */
+ b save_boot_params
+save_boot_params_ret:
/*
* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
* except if in HYP mode already
@@ -96,7 +99,7 @@ ENDPROC(c_runtime_cpu_setup)
*
*************************************************************************/
ENTRY(save_boot_params)
- bx lr @ back to my caller
+ b save_boot_params_ret @ back to my caller
ENDPROC(save_boot_params)
.weak save_boot_params
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 48db744..4bb12ad 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-y += timer.o
obj-y += board.o
obj-y += clock.o
obj-y += cpu_info.o
+obj-y += dram_helpers.o
obj-y += pinmux.o
obj-y += usbc.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
@@ -38,7 +39,5 @@ obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
-ifdef CONFIG_SPL_FEL
-obj-y += start.o
-endif
+obj-y += fel_utils.o
endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6e28bcd..c02c015 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -27,6 +27,17 @@
#include <linux/compiler.h>
+struct fel_stash {
+ uint32_t sp;
+ uint32_t lr;
+ uint32_t cpsr;
+ uint32_t sctlr;
+ uint32_t vbar;
+ uint32_t cr;
+};
+
+struct fel_stash fel_stash __attribute__((section(".data")));
+
static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
@@ -65,6 +76,12 @@ static int gpio_init(void)
return 0;
}
+void spl_board_load_image(void)
+{
+ debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
+ return_to_fel(fel_stash.sp, fel_stash.lr);
+}
+
void s_init(void)
{
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
@@ -95,7 +112,34 @@ void s_init(void)
*/
u32 spl_boot_device(void)
{
- return BOOT_DEVICE_MMC1;
+#ifdef CONFIG_SPL_FEL
+ /*
+ * This is the legacy compile time configuration for a special FEL
+ * enabled build. It has many restrictions and can only boot over USB.
+ */
+ return BOOT_DEVICE_BOARD;
+#else
+ /*
+ * When booting from the SD card, the "eGON.BT0" signature is expected
+ * to be found in memory at the address 0x0004 (see the "mksunxiboot"
+ * tool, which generates this header).
+ *
+ * When booting in the FEL mode over USB, this signature is patched in
+ * memory and replaced with something else by the 'fel' tool. This other
+ * signature is selected in such a way, that it can't be present in a
+ * valid bootable SD card image (because the BROM would refuse to
+ * execute the SPL in this case).
+ *
+ * This branch is just making a decision at runtime whether to load
+ * the main u-boot binary from the SD card (if the "eGON.BT0" signature
+ * is found) or return to the FEL code in the BROM to wait and receive
+ * the main u-boot binary over USB.
+ */
+ if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */
+ return BOOT_DEVICE_MMC1;
+ else
+ return BOOT_DEVICE_BOARD;
+#endif
}
/* No confirmation data available in SPL yet. Hardcode bootmode */
diff --git a/arch/arm/cpu/armv7/sunxi/config.mk b/arch/arm/cpu/armv7/sunxi/config.mk
index 00f5ffc..76ffec9 100644
--- a/arch/arm/cpu/armv7/sunxi/config.mk
+++ b/arch/arm/cpu/armv7/sunxi/config.mk
@@ -1,8 +1,6 @@
# Build a combined spl + u-boot image
ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
-ifndef CONFIG_SPL_FEL
ALL-y += u-boot-sunxi-with-spl.bin
endif
endif
-endif
diff --git a/arch/arm/cpu/armv7/sunxi/dram_helpers.c b/arch/arm/cpu/armv7/sunxi/dram_helpers.c
new file mode 100644
index 0000000..9a94e1b
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram_helpers.c
@@ -0,0 +1,37 @@
+/*
+ * DRAM init helper functions
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/dram.h>
+
+/*
+ * Wait up to 1s for value to be set in given part of reg.
+ */
+void mctl_await_completion(u32 *reg, u32 mask, u32 val)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ while ((readl(reg) & mask) != val) {
+ if (timer_get_us() > tmo)
+ panic("Timeout initialising DRAM\n");
+ }
+}
+
+/*
+ * Test if memory at offset offset matches memory at begin of DRAM
+ */
+bool mctl_mem_matches(u32 offset)
+{
+ /* Try to write different values to RAM at two addresses */
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+ writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset);
+ /* Check if the same value is actually observed when reading back */
+ return readl(CONFIG_SYS_SDRAM_BASE) ==
+ readl(CONFIG_SYS_SDRAM_BASE + offset);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/fel_utils.S b/arch/arm/cpu/armv7/sunxi/fel_utils.S
new file mode 100644
index 0000000..bf00335
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/fel_utils.S
@@ -0,0 +1,42 @@
+/*
+ * Utility functions for FEL mode.
+ *
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+ ldr r0, =fel_stash
+ str sp, [r0, #0]
+ str lr, [r0, #4]
+ mrs lr, cpsr @ Read CPSR
+ str lr, [r0, #8]
+ mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
+ str lr, [r0, #12]
+ mrc p15, 0, lr, c12, c0, 0 @ Read VBAR
+ str lr, [r0, #16]
+ mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
+ str lr, [r0, #20]
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
+
+ENTRY(return_to_fel)
+ mov sp, r0
+ mov lr, r1
+ ldr r0, =fel_stash
+ ldr r1, [r0, #20]
+ mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
+ ldr r1, [r0, #16]
+ mcr p15, 0, r1, c12, c0, 0 @ Write VBAR
+ ldr r1, [r0, #12]
+ mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
+ ldr r1, [r0, #8]
+ msr cpsr, r1 @ Write CPSR
+ bx lr
+ENDPROC(return_to_fel)
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
deleted file mode 100644
index 928b7c1..0000000
--- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2013
- * Henrik Nordstrom <henrik@henriknordstrom.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(s_init)
-SECTIONS
-{
- . = 0x00002000;
-
- . = ALIGN(4);
- .text :
- {
- *(.text.s_init)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
- . = .;
-
- . = ALIGN(4);
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- . = ALIGN(4);
- .note.gnu.build-id :
- {
- *(.note.gnu.build-id)
- }
- _end = .;
-
- . = ALIGN(4096);
- .mmutable : {
- *(.mmutable)
- }
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
- /DISCARD/ : { *(.note*) }
-}
generated by cgit v1.1 at 2024-10-13 11:26:20 +0000