diff options
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/kirkwood/Makefile | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 74 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/kirkwood/dram.c | 137 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/kirkwood/mpp.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/kirkwood/timer.c | 157 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/armada-xp/Makefile | 7 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/armada-xp/cpu.c | 193 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/pinmux.c | 5 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/Kconfig | 3 |
9 files changed, 210 insertions, 372 deletions
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile index c230ce8..df4756e 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile +++ b/arch/arm/cpu/arm926ejs/kirkwood/Makefile @@ -7,7 +7,5 @@ # obj-y = cpu.o -obj-y += dram.o -obj-y += mpp.o -obj-y += timer.o obj-y += cache.o +obj-y += mpp.o diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index 881e2de..9e412bb 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -9,14 +9,11 @@ #include <common.h> #include <netdev.h> #include <asm/cache.h> -#include <u-boot/md5.h> #include <asm/io.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <mvebu_mmc.h> -#define BUFLEN 16 - void reset_cpu(unsigned long ignored) { struct kwcpu_registers *cpureg = @@ -30,31 +27,6 @@ void reset_cpu(unsigned long ignored) } /* - * Generates Ramdom hex number reading some time varient system registers - * and using md5 algorithm - */ -unsigned char get_random_hex(void) -{ - int i; - u32 inbuf[BUFLEN]; - u8 outbuf[BUFLEN]; - - /* - * in case of 88F6281/88F6282/88F6192 A0, - * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470 - * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are - * reserved regs and does not have names at this moment - * (no errata available) - */ - writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478); - for (i = 0; i < BUFLEN; i++) { - inbuf[i] = readl(KW_REG_UNDOC_0x1470); - } - md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf); - return outbuf[outbuf[7] % 0x0f]; -} - -/* * Window Size * Used with the Base register to set the address window size and location. * Must be programmed from LSB to MSB as sequence of ones followed by @@ -140,50 +112,6 @@ int kw_config_adr_windows(void) } /* - * kw_config_gpio - GPIO configuration - */ -void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe) -{ - struct kwgpio_registers *gpio0reg = - (struct kwgpio_registers *)KW_GPIO0_BASE; - struct kwgpio_registers *gpio1reg = - (struct kwgpio_registers *)KW_GPIO1_BASE; - - /* Init GPIOS to default values as per board requirement */ - writel(gpp0_oe_val, &gpio0reg->dout); - writel(gpp1_oe_val, &gpio1reg->dout); - writel(gpp0_oe, &gpio0reg->oe); - writel(gpp1_oe, &gpio1reg->oe); -} - -/* - * kw_config_mpp - Multi-Purpose Pins Functionality configuration - * - * Each MPP can be configured to different functionality through - * MPP control register, ref (sec 6.1 of kirkwood h/w specification) - * - * There are maximum 64 Multi-Pourpose Pins on Kirkwood - * Each MPP functionality can be configuration by a 4bit value - * of MPP control reg, the value and associated functionality depends - * upon used SoC varient - */ -int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31, - u32 mpp32_39, u32 mpp40_47, u32 mpp48_55) -{ - u32 *mppreg = (u32 *) KW_MPP_BASE; - - /* program mpp registers */ - writel(mpp0_7, &mppreg[0]); - writel(mpp8_15, &mppreg[1]); - writel(mpp16_23, &mppreg[2]); - writel(mpp24_31, &mppreg[3]); - writel(mpp32_39, &mppreg[4]); - writel(mpp40_47, &mppreg[5]); - writel(mpp48_55, &mppreg[6]); - return 0; -} - -/* * SYSRSTn Duration Counter Support * * Kirkwood SoC implements a hardware-based SYSRSTn duration counter. diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c deleted file mode 100644 index d73ae47..0000000 --- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct kw_sdram_bank { - u32 win_bar; - u32 win_sz; -}; - -struct kw_sdram_addr_dec { - struct kw_sdram_bank sdram_bank[4]; -}; - -#define KW_REG_CPUCS_WIN_ENABLE (1 << 0) -#define KW_REG_CPUCS_WIN_WR_PROTECT (1 << 1) -#define KW_REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2) -#define KW_REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24) - -/* - * kw_sdram_bar - reads SDRAM Base Address Register - */ -u32 kw_sdram_bar(enum memory_bank bank) -{ - struct kw_sdram_addr_dec *base = - (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500); - u32 result = 0; - u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz); - - if ((!enable) || (bank > BANK3)) - return 0; - - result = readl(&base->sdram_bank[bank].win_bar); - return result; -} - -/* - * kw_sdram_bs_set - writes SDRAM Bank size - */ -static void kw_sdram_bs_set(enum memory_bank bank, u32 size) -{ - struct kw_sdram_addr_dec *base = - (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500); - /* Read current register value */ - u32 reg = readl(&base->sdram_bank[bank].win_sz); - - /* Clear window size */ - reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF); - - /* Set new window size */ - reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24); - - writel(reg, &base->sdram_bank[bank].win_sz); -} - -/* - * kw_sdram_bs - reads SDRAM Bank size - */ -u32 kw_sdram_bs(enum memory_bank bank) -{ - struct kw_sdram_addr_dec *base = - (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500); - u32 result = 0; - u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz); - - if ((!enable) || (bank > BANK3)) - return 0; - result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz); - result += 0x01000000; - return result; -} - -void kw_sdram_size_adjust(enum memory_bank bank) -{ - u32 size; - - /* probe currently equipped RAM size */ - size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank)); - - /* adjust SDRAM window size accordingly */ - kw_sdram_bs_set(bank, size); -} - -#ifndef CONFIG_SYS_BOARD_DRAM_INIT -int dram_init(void) -{ - int i; - - gd->ram_size = 0; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - /* - * It is assumed that all memory banks are consecutive - * and without gaps. - * If the gap is found, ram_size will be reported for - * consecutive memory only - */ - if (gd->bd->bi_dram[i].start != gd->ram_size) - break; - - gd->ram_size += gd->bd->bi_dram[i].size; - - } - - for (; i < CONFIG_NR_DRAM_BANKS; i++) { - /* If above loop terminated prematurely, we need to set - * remaining banks' start address & size as 0. Otherwise other - * u-boot functions and Linux kernel gets wrong values which - * could result in crash */ - gd->bd->bi_dram[i].start = 0; - gd->bd->bi_dram[i].size = 0; - } - - return 0; -} - -/* - * If this function is not defined here, - * board.c alters dram bank zero configuration defined above. - */ -void dram_init_banksize(void) -{ - dram_init(); -} -#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c index 0ba6f09..7222504 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c @@ -12,7 +12,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #include <asm/arch/mpp.h> static u32 kirkwood_variant(void) diff --git a/arch/arm/cpu/arm926ejs/kirkwood/timer.c b/arch/arm/cpu/arm926ejs/kirkwood/timer.c deleted file mode 100644 index a08f4a1..0000000 --- a/arch/arm/cpu/arm926ejs/kirkwood/timer.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (C) Marvell International Ltd. and its affiliates - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/kirkwood.h> - -#define UBOOT_CNTR 0 /* counter to use for uboot timer */ - -/* Timer reload and current value registers */ -struct kwtmr_val { - u32 reload; /* Timer reload reg */ - u32 val; /* Timer value reg */ -}; - -/* Timer registers */ -struct kwtmr_registers { - u32 ctrl; /* Timer control reg */ - u32 pad[3]; - struct kwtmr_val tmr[2]; - u32 wdt_reload; - u32 wdt_val; -}; - -struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE; - -/* - * ARM Timers Registers Map - */ -#define CNTMR_CTRL_REG &kwtmr_regs->ctrl -#define CNTMR_RELOAD_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].reload -#define CNTMR_VAL_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].val - -/* - * ARM Timers Control Register - * CPU_TIMERS_CTRL_REG (CTCR) - */ -#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) -#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) -#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) - -#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) -#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) - -/* - * ARM Timer\Watchdog Reload Register - * CNTMR_RELOAD_REG (TRR) - */ -#define TRG_ARM_TIMER_REL_OFFS 0 -#define TRG_ARM_TIMER_REL_MASK 0xffffffff - -/* - * ARM Timer\Watchdog Register - * CNTMR_VAL_REG (TVRG) - */ -#define TVR_ARM_TIMER_OFFS 0 -#define TVR_ARM_TIMER_MASK 0xffffffff -#define TVR_ARM_TIMER_MAX 0xffffffff -#define TIMER_LOAD_VAL 0xffffffff - -#define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \ - (CONFIG_SYS_TCLK / 1000)) - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc - -ulong get_timer_masked(void) -{ - ulong now = READ_TIMER; - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + - (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; - } - lastdec = now; - - return timestamp; -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void __udelay(unsigned long usec) -{ - uint current; - ulong delayticks; - - current = readl(CNTMR_VAL_REG(UBOOT_CNTR)); - delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); - - if (current < delayticks) { - delayticks -= current; - while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ; - while ((TIMER_LOAD_VAL - delayticks) < - readl(CNTMR_VAL_REG(UBOOT_CNTR))) ; - } else { - while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) > - (current - delayticks)) ; - } -} - -/* - * init the counter - */ -int timer_init(void) -{ - unsigned int cntmrctrl; - - /* load value into timer */ - writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); - writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); - - /* enable timer in auto reload mode */ - cntmrctrl = readl(CNTMR_CTRL_REG); - cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); - cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); - writel(cntmrctrl, CNTMR_CTRL_REG); - - /* init the timestamp and lastdec value */ - lastdec = READ_TIMER; - timestamp = 0; - - return 0; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - return (ulong)CONFIG_SYS_HZ; -} diff --git a/arch/arm/cpu/armv7/armada-xp/Makefile b/arch/arm/cpu/armv7/armada-xp/Makefile new file mode 100644 index 0000000..885dcee --- /dev/null +++ b/arch/arm/cpu/armv7/armada-xp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = cpu.o diff --git a/arch/arm/cpu/armv7/armada-xp/cpu.c b/arch/arm/cpu/armv7/armada-xp/cpu.c new file mode 100644 index 0000000..1cf70a9 --- /dev/null +++ b/arch/arm/cpu/armv7/armada-xp/cpu.c @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) +#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) + +static struct mbus_win windows[] = { + /* PCIE MEM address space */ + { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM }, + + /* PCIE IO address space */ + { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO }, + + /* SPI */ + { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, + CPU_ATTR_SPIFLASH }, + + /* NOR */ + { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, + CPU_ATTR_BOOTROM }, +}; + +void reset_cpu(unsigned long ignored) +{ + struct mvebu_system_registers *reg = + (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; + + writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask); + writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst); + while (1) + ; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; + u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; + + puts("SoC: "); + + switch (devid) { + case SOC_MV78460_ID: + puts("MV78460-"); + break; + default: + puts("Unknown-"); + break; + } + + switch (revid) { + case 1: + puts("A0\n"); + break; + case 2: + puts("B0\n"); + break; + default: + puts("??\n"); + break; + } + + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ + +/* + * This function initialize Controller DRAM Fastpath windows. + * It takes the CS size information from the 0x1500 scratch registers + * and sets the correct windows sizes and base addresses accordingly. + * + * These values are set in the scratch registers by the Marvell + * DDR3 training code, which is executed by the BootROM before the + * main payload (U-Boot) is executed. This training code is currently + * only available in the Marvell U-Boot version. It needs to be + * ported to mainline U-Boot SPL at some point. + */ +static void update_sdram_window_sizes(void) +{ + u64 base = 0; + u32 size, temp; + int i; + + for (i = 0; i < SDRAM_MAX_CS; i++) { + size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK; + if (size != 0) { + size |= ~(SDRAM_ADDR_MASK); + + /* Set Base Address */ + temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF); + writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); + + /* + * Check if out of max window size and resize + * the window + */ + temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) & + ~(SDRAM_ADDR_MASK)) | 1; + temp |= (size & SDRAM_ADDR_MASK); + writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)); + + base += ((u64)size + 1); + } else { + /* + * Disable window if not used, otherwise this + * leads to overlapping enabled windows with + * pretty strange results + */ + clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1); + } + } +} + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + /* Linux expects the internal registers to be at 0xf1000000 */ + writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); + + /* + * We need to call mvebu_mbus_probe() before calling + * update_sdram_window_sizes() as it disables all previously + * configured mbus windows and then configures them as + * required for U-Boot. Calling update_sdram_window_sizes() + * without this configuration will not work, as the internal + * registers can't be accessed reliably because of potenial + * double mapping. + * After updating the SDRAM access windows we need to call + * mvebu_mbus_probe() again, as this now correctly configures + * the SDRAM areas that are later used by the MVEBU drivers + * (e.g. USB, NETA). + */ + + /* + * First disable all windows + */ + mvebu_mbus_probe(NULL, 0); + + /* + * Now the SDRAM access windows can be reconfigured using + * the information in the SDRAM scratch pad registers + */ + update_sdram_window_sizes(); + + /* + * Finally the mbus windows can be configured with the + * updated SDRAM sizes + */ + mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); + + return 0; +} +#endif /* CONFIG_ARCH_CPU_INIT */ + +/* + * SOC specific misc init + */ +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + /* Nothing yet, perhaps we need something here later */ + return 0; +} +#endif /* CONFIG_ARCH_MISC_INIT */ + +#ifdef CONFIG_MVNETA +int cpu_eth_init(bd_t *bis) +{ + mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0); + mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1); + mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2); + mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3); + + return 0; +} +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index b929486..3d95dc3 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -7,7 +7,7 @@ #include <common.h> #include <fdtdec.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/sromc.h> @@ -172,6 +172,9 @@ static int exynos5420_mmc_config(int peripheral, int flags) * this same assumption. */ if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) { +#ifndef CONFIG_SPL_BUILD + gpio_request(i, "sdmmc0_vdden"); +#endif gpio_set_value(i, 1); gpio_cfg_pin(i, S5P_GPIO_OUTPUT); } else { diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig index bcae2d6..3ea6d76 100644 --- a/arch/arm/cpu/armv7/tegra-common/Kconfig +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig @@ -17,6 +17,9 @@ config TEGRA124 endchoice +config USE_PRIVATE_LIBGCC + default y if SPL_BUILD + config SYS_CPU default "arm720t" if SPL_BUILD default "armv7" if !SPL_BUILD |