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-rw-r--r--arch/arm/cpu/armv7/keystone/ddr3.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
index bb16551..b711b81 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -8,6 +8,7 @@
*/
#include <asm/io.h>
+#include <common.h>
#include <asm/arch/ddr3.h>
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
@@ -67,3 +68,21 @@ void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
__raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
__raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
}
+
+void ddr3_reset_ddrphy(void)
+{
+ u32 tmp;
+
+ /* Assert DDR3A PHY reset */
+ tmp = readl(K2HK_DDR3APLLCTL1);
+ tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
+ writel(tmp, K2HK_DDR3APLLCTL1);
+
+ /* wait 10us to catch the reset */
+ udelay(10);
+
+ /* Release DDR3A PHY reset */
+ tmp = readl(K2HK_DDR3APLLCTL1);
+ tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
+ __raw_writel(tmp, K2HK_DDR3APLLCTL1);
+}