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Diffstat (limited to 'arch/arm/cpu/pxa/pxafb.c')
-rw-r--r--arch/arm/cpu/pxa/pxafb.c76
1 files changed, 75 insertions, 1 deletions
diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c
index d56c5f0..524a03b 100644
--- a/arch/arm/cpu/pxa/pxafb.c
+++ b/arch/arm/cpu/pxa/pxafb.c
@@ -112,6 +112,39 @@ vidinfo_t panel_info = {
vl_efw: 0,
};
#endif /* CONFIG_SHARP_LM8V31 */
+/*----------------------------------------------------------------------*/
+#ifdef CONFIG_VOIPAC_LCD
+
+# define LCD_BPP LCD_COLOR8
+# define LCD_INVERT_COLORS
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x043008f8
+# define REG_LCCR3 0x0340FF08
+
+vidinfo_t panel_info = {
+ vl_col: 640,
+ vl_row: 480,
+ vl_width: 157,
+ vl_height: 118,
+ vl_clkp: CONFIG_SYS_HIGH,
+ vl_oep: CONFIG_SYS_HIGH,
+ vl_hsp: CONFIG_SYS_HIGH,
+ vl_vsp: CONFIG_SYS_HIGH,
+ vl_dp: CONFIG_SYS_HIGH,
+ vl_bpix: LCD_BPP,
+ vl_lbw: 0,
+ vl_splt: 1,
+ vl_clor: 1,
+ vl_tft: 1,
+ vl_hpw: 32,
+ vl_blw: 144,
+ vl_elw: 32,
+ vl_vpw: 2,
+ vl_bfw: 13,
+ vl_efw: 30,
+};
+#endif /* CONFIG_VOIPAC_LCD */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_HITACHI_SX14
@@ -147,6 +180,40 @@ vidinfo_t panel_info = {
#endif /* CONFIG_HITACHI_SX14 */
/*----------------------------------------------------------------------*/
+#ifdef CONFIG_LMS283GF05
+
+# define LCD_BPP LCD_COLOR8
+//# define LCD_INVERT_COLORS
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x043008f8
+# define REG_LCCR3 0x03b00009
+
+vidinfo_t panel_info = {
+ vl_col: 240,
+ vl_row: 320,
+ vl_width: 240,
+ vl_height: 320,
+ vl_clkp: CONFIG_SYS_HIGH,
+ vl_oep: CONFIG_SYS_LOW,
+ vl_hsp: CONFIG_SYS_LOW,
+ vl_vsp: CONFIG_SYS_LOW,
+ vl_dp: CONFIG_SYS_HIGH,
+ vl_bpix: LCD_BPP,
+ vl_lbw: 0,
+ vl_splt: 1,
+ vl_clor: 1,
+ vl_tft: 1,
+ vl_hpw: 4,
+ vl_blw: 4,
+ vl_elw: 8,
+ vl_vpw: 4,
+ vl_bfw: 4,
+ vl_efw: 8,
+};
+#endif /* CONFIG_LMS283GF05 */
+
+/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_COLOR8
void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
@@ -292,7 +359,9 @@ static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
return 0;
}
-
+#ifdef CONFIG_CPU_MONAHANS
+static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
+#else
static void pxafb_setup_gpio (vidinfo_t *vid)
{
u_long lccr0;
@@ -349,6 +418,7 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
}
}
+#endif
static void pxafb_enable_controller (vidinfo_t *vid)
{
@@ -363,7 +433,11 @@ static void pxafb_enable_controller (vidinfo_t *vid)
FDADR1 = vid->pxa.fdadr1;
LCCR0 |= LCCR0_ENB;
+#ifdef CONFIG_CPU_MONAHANS
+ CKENA |= CKENA_1_LCD;
+#else
CKEN |= CKEN16_LCD;
+#endif
debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);