diff options
Diffstat (limited to 'arch/arm/cpu/armv7')
24 files changed, 129 insertions, 78 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 2ce682f..781d83f 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -18,6 +18,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/clock.h> #include <power/tps65910.h> +#include <linux/compiler.h> struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE; @@ -51,11 +52,11 @@ u32 get_cpu_type(void) /** * get_board_rev() - setup to pass kernel board revision information - * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + * returns: 0 for the ATAG REVISION tag value. */ -u32 get_board_rev(void) +u32 __weak get_board_rev(void) { - return BOARD_REV_ID; + return 0; } /** diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index c215404..a029379 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -22,6 +22,9 @@ config TARGET_CM_T35 bool "CompuLab CM-T3530 and CM-T3730 boards" select SUPPORT_SPL +config TARGET_CM_T3517 + bool "CompuLab CM-T3517 boards" + config TARGET_DEVKIT8000 bool "TimLL OMAP3 Devkit8000" select SUPPORT_SPL @@ -98,6 +101,7 @@ source "board/teejet/mt_ventoux/Kconfig" source "board/ti/sdp3430/Kconfig" source "board/ti/beagle/Kconfig" source "board/compulab/cm_t35/Kconfig" +source "board/compulab/cm_t3517/Kconfig" source "board/timll/devkit8000/Kconfig" source "board/ti/evm/Kconfig" source "board/isee/igep00x0/Kconfig" diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index d869f47..fa3b93a 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -507,6 +507,19 @@ unsigned int cm_get_qspi_controller_clk_hz(void) return clock; } +unsigned int cm_get_spi_controller_clk_hz(void) +{ + uint32_t reg, clock = 0; + + clock = cm_get_per_vco_clk_hz(); + + /* get the clock prior L4 SP divider (periph_base_clk) */ + reg = readl(&clock_manager_base->per_pll.perbaseclk); + clock /= (reg + 1); + + return clock; +} + static void cm_print_clock_quick_summary(void) { printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); @@ -518,6 +531,7 @@ static void cm_print_clock_quick_summary(void) printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); + printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); } int set_cpu_clk_info(void) diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 8c3e5f7..73cffd3 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -202,6 +202,12 @@ int arch_early_init_r(void) /* Add device descriptor to FPGA device table */ socfpga_fpga_add(); + +#ifdef CONFIG_DESIGNWARE_SPI + /* Get Designware SPI controller out of reset */ + socfpga_spim_enable(); +#endif + return 0; } diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index 1d3a95d..af9db85 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -104,3 +104,12 @@ void socfpga_emac_reset(int enable) #endif } } + +/* SPI Master enable (its held in reset by the preloader) */ +void socfpga_spim_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB); + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB); +} diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig index 3ea6d76..1446452 100644 --- a/arch/arm/cpu/armv7/tegra-common/Kconfig +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig @@ -20,10 +20,6 @@ endchoice config USE_PRIVATE_LIBGCC default y if SPL_BUILD -config SYS_CPU - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - source "arch/arm/cpu/armv7/tegra20/Kconfig" source "arch/arm/cpu/armv7/tegra30/Kconfig" source "arch/arm/cpu/armv7/tegra114/Kconfig" diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index f013dc3..36b7f11 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -32,4 +32,31 @@ config CMD_PINMON The boot mode pins are latched when the system reset is deasserted and determine which device the system should load a boot image from. +config SOC_INIT + bool + default SPL_BUILD + +config DRAM_INIT + bool + default SPL_BUILD + +choice + prompt "DDR3 Frequency select" + depends on DRAM_INIT + +config DDR_FREQ_1600 + bool "DDR3 1600" + depends on MACH_PH1_PRO4 || MACH_PH1_LD4 + +config DDR_FREQ_1333 + bool "DDR3 1333" + depends on MACH_PH1_LD4 || MACH_PH1_SLD8 + +endchoice + +config DDR_FREQ + int + default 1333 if DDR_FREQ_1333 + default 1600 if DDR_FREQ_1600 + endmenu diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile index dd57469..0f64d25 100644 --- a/arch/arm/cpu/armv7/uniphier/Makefile +++ b/arch/arm/cpu/armv7/uniphier/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o obj-y += timer.o obj-y += reset.o obj-y += cache_uniphier.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o obj-y += dram_init.o obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c index 4302277..89e44bb 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c +++ b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c @@ -5,11 +5,13 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> +#include <linux/compiler.h> #include <asm/arch/led.h> #include <asm/arch/board.h> -void bcu_init(void); +void __weak bcu_init(void) +{ +}; void sbc_init(void); void sg_init(void); void pll_init(void); @@ -18,12 +20,15 @@ void clkrst_init(void); int board_postclk_init(void) { +#ifdef CONFIG_SOC_INIT bcu_init(); sbc_init(); sg_init(); + uniphier_board_reset(); + pll_init(); uniphier_board_init(); @@ -33,7 +38,7 @@ int board_postclk_init(void) clkrst_init(); led_write(B, 2, , ); - +#endif pin_init(); led_write(B, 3, , ); diff --git a/arch/arm/cpu/armv7/uniphier/dram_init.c b/arch/arm/cpu/armv7/uniphier/dram_init.c index 5465a0e..7de657b 100644 --- a/arch/arm/cpu/armv7/uniphier/dram_init.c +++ b/arch/arm/cpu/armv7/uniphier/dram_init.c @@ -16,7 +16,7 @@ int dram_init(void) DECLARE_GLOBAL_DATA_PTR; gd->ram_size = CONFIG_SYS_SDRAM_SIZE; -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_DRAM_INIT led_write(B, 4, , ); { diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile index 781b511..fba1cc7 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-y += platdevice.o obj-y += boot-mode.o -obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ - sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \ + clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c index 0047223..62f5b01 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c @@ -13,3 +13,16 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, + { + .base = 0x5a820100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c index 1344ac1..ebcbaab 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c @@ -149,10 +149,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600 -#error Unsupported DDR Frequency. -#endif - #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile index e11f4f6..74129bc 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile @@ -5,7 +5,6 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-y += platdevice.o obj-y += boot-mode.o -obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \ - sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c deleted file mode 100644 index 7198829..0000000 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/led.h> -#include <asm/arch/board.h> - -void sbc_init(void); -void sg_init(void); -void pll_init(void); -void pin_init(void); -void clkrst_init(void); - -int board_postclk_init(void) -{ - sbc_init(); - - sg_init(); - - pll_init(); - - uniphier_board_init(); - - led_write(B, 1, , ); - - clkrst_init(); - - led_write(B, 2, , ); - - pin_init(); - - led_write(B, 3, , ); - - return 0; -} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c index 503c247..4e3d476 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c @@ -41,5 +41,12 @@ void pin_init(void) sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */ #endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */ + sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */ + sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */ + sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */ +#endif + writel(1, SG_LOADPINCTRL); } diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c index 6da921e..1843d04 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c @@ -13,3 +13,13 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c index dd46287..328b2f4 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c @@ -122,10 +122,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1600 -#error Unsupported DDR frequency. -#endif - #if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \ (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \ ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \ diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile index 781b511..fba1cc7 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-y += platdevice.o obj-y += boot-mode.o -obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ - sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \ + clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c deleted file mode 100644 index 287b33c..0000000 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-ld4/board_postclk_init.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c index 59d054a..72ec599 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c @@ -13,3 +13,16 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, + { + .base = 0x5a820100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c index ff2dcb1..a44f999 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c @@ -129,10 +129,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1333 -#error Unsupported DDR frequency. -#endif - #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 diff --git a/arch/arm/cpu/armv7/uniphier/reset.c b/arch/arm/cpu/armv7/uniphier/reset.c index b0dc967..50d1fed 100644 --- a/arch/arm/cpu/armv7/uniphier/reset.c +++ b/arch/arm/cpu/armv7/uniphier/reset.c @@ -8,14 +8,11 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/sc-regs.h> -#include <asm/arch/board.h> void reset_cpu(unsigned long ignored) { u32 tmp; - uniphier_board_reset(); - writel(5, SC_IRQTIMSET); /* default value */ tmp = readl(SC_SLFRSTSEL); diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index 1ea086d..d74f8db 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -40,6 +40,7 @@ void zynq_ddrc_init(void) * first stage bootloader. To get ECC to work all memory has * been initialized by writing any value. */ + /* cppcheck-suppress nullPointer */ memset((void *)0, 0, 1 * 1024 * 1024); } else { puts("ECC disabled "); |