diff options
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/mx7ulp/clock.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c b/arch/arm/cpu/armv7/mx7ulp/clock.c index e6225bb..1c072b8 100644 --- a/arch/arm/cpu/armv7/mx7ulp/clock.c +++ b/arch/arm/cpu/armv7/mx7ulp/clock.c @@ -73,6 +73,46 @@ u32 get_lpuart_clk(void) return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]); } +#ifdef CONFIG_SYS_LPI2C_IMX +int enable_i2c_clk(unsigned char enable, unsigned i2c_num) +{ + /* Set parent to FIRC DIV2 clock */ + const enum pcc_clk lpi2c_pcc_clks[] = { + PER_CLK_LPI2C4, + PER_CLK_LPI2C5, + PER_CLK_LPI2C6, + PER_CLK_LPI2C7, + }; + + if (i2c_num < 4 || i2c_num > 7) + return -EINVAL; + + if (enable) { + pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false); + pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK); + pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true); + } else { + pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false); + } + return 0; +} + +u32 imx_get_i2cclk(unsigned i2c_num) +{ + const enum pcc_clk lpi2c_pcc_clks[] = { + PER_CLK_LPI2C4, + PER_CLK_LPI2C5, + PER_CLK_LPI2C6, + PER_CLK_LPI2C7, + }; + + if (i2c_num < 4 || i2c_num > 7) + return 0; + + return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]); +} +#endif + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { |