diff options
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/mx5/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx5/asm-offsets.c | 76 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx5/lowlevel_init.S | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx5/timer.c | 20 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/timer.c | 21 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/s5p-common/timer.c | 10 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/timer.c | 17 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/u8500/timer.c | 5 |
9 files changed, 95 insertions, 70 deletions
diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile index e8be9c9..6e13cc3 100644 --- a/arch/arm/cpu/armv7/mx5/Makefile +++ b/arch/arm/cpu/armv7/mx5/Makefile @@ -45,4 +45,6 @@ include $(SRCTREE)/rules.mk sinclude $(obj).depend +lowlevel_init.o : $(TOPDIR)/include/asm/arch/asm-offsets.h + ######################################################################### diff --git a/arch/arm/cpu/armv7/mx5/asm-offsets.c b/arch/arm/cpu/armv7/mx5/asm-offsets.c new file mode 100644 index 0000000..f972498 --- /dev/null +++ b/arch/arm/cpu/armv7/mx5/asm-offsets.c @@ -0,0 +1,76 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/arch/imx-regs.h> + +#include <linux/kbuild.h> + +int main(void) +{ + + /* Round up to make sure size gives nice stack alignment */ + DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); + DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr)); + DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr)); + DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr)); + DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr)); + DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr)); + DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr)); + DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1)); + DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2)); + DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1)); + DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr)); + DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr)); + DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr)); + DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr)); + DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2)); + DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3)); + DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4)); + DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr)); + DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr)); + DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr)); + DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor)); + DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr)); + DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr)); + DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr)); + DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr)); + DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr)); + DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0)); + DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1)); + DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2)); + DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3)); + DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4)); + DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5)); + DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6)); + DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor)); +#if defined(CONFIG_MX53) + DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7)); +#endif + + /* DPLL */ + DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); + DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); + DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); + DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); + DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); + DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); + DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); + DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); + + return 0; +} diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 96ebfe2..94de9f1 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -39,10 +39,14 @@ orr r0, r0, #(1 << 23) /* disable write allocate combine */ orr r0, r0, #(1 << 22) /* disable write allocate */ - cmp r3, #0x10 /* r3 contains the silicon rev */ +#if defined(CONFIG_MX51) + ldr r1, =0x0 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 /* disable write combine for TO 2 and lower revs */ orrls r0, r0, #(1 << 25) +#endif mcr 15, 1, r0, c9, c0, 2 .endm /* init_l2cc */ diff --git a/arch/arm/cpu/armv7/mx5/timer.c b/arch/arm/cpu/armv7/mx5/timer.c index 1972f64..2544b08 100644 --- a/arch/arm/cpu/armv7/mx5/timer.c +++ b/arch/arm/cpu/armv7/mx5/timer.c @@ -52,6 +52,7 @@ DECLARE_GLOBAL_DATA_PTR; int timer_init(void) { int i; + ulong val; /* setup GP Timer 1 */ __raw_writel(GPTCR_SWR, &cur_gpt->control); @@ -65,20 +66,12 @@ int timer_init(void) /* Freerun Mode, PERCLK1 input */ i = __raw_readl(&cur_gpt->control); __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control); - reset_timer_masked(); - return 0; -} - -void reset_timer(void) -{ - reset_timer_masked(); -} -void reset_timer_masked(void) -{ - ulong val = __raw_readl(&cur_gpt->counter); + val = __raw_readl(&cur_gpt->counter); lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ); timestamp = 0; + + return 0; } ulong get_timer_masked(void) @@ -99,11 +92,6 @@ ulong get_timer(ulong base) return get_timer_masked() - base; } -void set_timer(ulong t) -{ - timestamp = t; -} - /* delay x useconds AND preserve advance timestamp value */ void __udelay(unsigned long usec) { diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c index 59bbca8..9f8bc93 100644 --- a/arch/arm/cpu/armv7/omap-common/timer.c +++ b/arch/arm/cpu/armv7/omap-common/timer.c @@ -55,7 +55,9 @@ int timer_init(void) writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, &timer_base->tclr); - reset_timer_masked(); /* init the timestamp and lastinc value */ + /* reset time, capture current incrementer value time */ + gd->lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); + gd->tbl = 0; /* start "advancing" time stamp from 0 */ return 0; } @@ -63,21 +65,11 @@ int timer_init(void) /* * timer without interrupts */ -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer(ulong base) { return get_timer_masked() - base; } -void set_timer(ulong t) -{ - gd->tbl = t; -} - /* delay x useconds */ void __udelay(unsigned long usec) { @@ -94,13 +86,6 @@ void __udelay(unsigned long usec) } } -void reset_timer_masked(void) -{ - /* reset time, capture current incrementer value time */ - gd->lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); - gd->tbl = 0; /* start "advancing" time stamp from 0 */ -} - ulong get_timer_masked(void) { /* current tick value */ diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index b750d16..359c21f 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -50,21 +50,11 @@ int timer_init(void) /* * timer without interrupts */ -void reset_timer(void) -{ - reset_timer_masked(); -} - unsigned long get_timer(unsigned long base) { return get_timer_masked() - base; } -void set_timer(unsigned long t) -{ - gd->tbl = t; -} - /* delay x useconds */ void __udelay(unsigned long usec) { diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 0e698b6..5c87e9c 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -182,7 +182,7 @@ stack_setup: mov sp, r4 adr r0, _start -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD cmp r0, r6 beq clear_bss /* skip relocation */ #endif @@ -196,7 +196,7 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -248,7 +248,7 @@ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l -#endif /* #ifndef CONFIG_PRELOADER */ +#endif /* #ifndef CONFIG_SPL_BUILD */ /* * We are done. Do not return, instead branch to second part of board @@ -283,6 +283,7 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start +#ifndef CONFIG_SKIP_LOWLEVEL_INIT /************************************************************************* * * CPU_init_critical registers @@ -327,6 +328,7 @@ cpu_init_crit: bl lowlevel_init @ go setup pll,mux,memory mov lr, ip @ restore link mov pc, lr @ back to my caller +#endif /* ************************************************************************* * diff --git a/arch/arm/cpu/armv7/tegra2/timer.c b/arch/arm/cpu/armv7/tegra2/timer.c index fb061d0..0b9fa64 100644 --- a/arch/arm/cpu/armv7/tegra2/timer.c +++ b/arch/arm/cpu/armv7/tegra2/timer.c @@ -48,21 +48,11 @@ struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE; #define TIMER_LOAD_VAL 0xffffffff /* timer without interrupts */ -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer(ulong base) { return get_timer_masked() - base; } -void set_timer(ulong t) -{ - gd->tbl = t; -} - /* delay x useconds */ void __udelay(unsigned long usec) { @@ -79,13 +69,6 @@ void __udelay(unsigned long usec) } } -void reset_timer_masked(void) -{ - /* reset time, capture current incrementer value time */ - gd->lastinc = readl(&timer_base->cntr_1us) / (TIMER_CLK/CONFIG_SYS_HZ); - gd->tbl = 0; /* start "advancing" time stamp from 0 */ -} - ulong get_timer_masked(void) { ulong now; diff --git a/arch/arm/cpu/armv7/u8500/timer.c b/arch/arm/cpu/armv7/u8500/timer.c index 8e96eaa..79aad99 100644 --- a/arch/arm/cpu/armv7/u8500/timer.c +++ b/arch/arm/cpu/armv7/u8500/timer.c @@ -129,11 +129,6 @@ ulong get_timer(ulong base) return get_timer_masked() - base; } -void set_timer(ulong t) -{ - gd->tbl = t; -} - /* * Emulation of Power architecture long long timebase. * |