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-rw-r--r--arch/arm/cpu/armv7/Makefile1
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c4
-rw-r--r--arch/arm/cpu/armv7/am33xx/emif4.c2
-rw-r--r--arch/arm/cpu/armv7/arch_timer.c58
-rw-r--r--arch/arm/cpu/armv7/keystone/Makefile17
-rw-r--r--arch/arm/cpu/armv7/keystone/aemif.c71
-rw-r--r--arch/arm/cpu/armv7/keystone/clock.c318
-rw-r--r--arch/arm/cpu/armv7/keystone/cmd_clock.c124
-rw-r--r--arch/arm/cpu/armv7/keystone/cmd_mon.c131
-rw-r--r--arch/arm/cpu/armv7/keystone/ddr3.c69
-rw-r--r--arch/arm/cpu/armv7/keystone/init.c56
-rw-r--r--arch/arm/cpu/armv7/keystone/keystone_nav.c376
-rw-r--r--arch/arm/cpu/armv7/keystone/msmc.c68
-rw-r--r--arch/arm/cpu/armv7/keystone/psc.c237
-rw-r--r--arch/arm/cpu/armv7/keystone/spl.c45
-rw-r--r--arch/arm/cpu/armv7/omap-common/boot-common.c11
-rw-r--r--arch/arm/cpu/armv7/omap-common/utils.c21
-rw-r--r--arch/arm/cpu/armv7/omap3/board.c4
-rw-r--r--arch/arm/cpu/armv7/omap3/clock.c355
-rw-r--r--arch/arm/cpu/armv7/omap3/sys_info.c19
-rw-r--r--arch/arm/cpu/armv7/syslib.c13
21 files changed, 1826 insertions, 174 deletions
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 119ebb3..ab869b1 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -25,6 +25,7 @@ endif
obj-$(CONFIG_KONA) += kona-common/
obj-$(CONFIG_OMAP_COMMON) += omap-common/
+obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
obj-$(CONFIG_TEGRA) += tegra-common/
ifneq (,$(filter s5pc1xx exynos,$(SOC)))
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index fb44cc8..28c16f8 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -142,7 +142,7 @@ int arch_misc_init(void)
return 0;
}
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*
* This function is the place to do per-board things such as ramp up the
* MPU clock frequency.
@@ -200,9 +200,7 @@ static void watchdog_disable(void)
while (readl(&wdtimer->wdtwwps) != 0x0)
;
}
-#endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
void s_init(void)
{
/*
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 3e39752..2c67c32 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -35,7 +35,7 @@ void dram_init_banksize(void)
}
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_TI81XX
static struct dmm_lisa_map_regs *hw_lisa_map_regs =
(struct dmm_lisa_map_regs *)DMM_BASE;
diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
new file mode 100644
index 0000000..0588e2b
--- /dev/null
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int timer_init(void)
+{
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
+
+ return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+ ulong nowl, nowu;
+
+ asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (nowl), "=r" (nowu));
+
+ gd->arch.tbl = nowl;
+ gd->arch.tbu = nowu;
+
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+
+ulong get_timer(ulong base)
+{
+ return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned long long endtime;
+
+ endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
+ 1000UL);
+
+ endtime += get_ticks();
+
+ while (get_ticks() < endtime)
+ ;
+}
+
+ulong get_tbclk(void)
+{
+ return gd->arch.timer_rate_hz;
+}
diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile
new file mode 100644
index 0000000..b1bd022
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2012-2014
+# Texas Instruments Incorporated, <www.ti.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += aemif.o
+obj-y += init.o
+obj-y += psc.o
+obj-y += clock.o
+obj-y += cmd_clock.o
+obj-y += cmd_mon.o
+obj-y += keystone_nav.o
+obj-y += msmc.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-y += ddr3.o
diff --git a/arch/arm/cpu/armv7/keystone/aemif.c b/arch/arm/cpu/armv7/keystone/aemif.c
new file mode 100644
index 0000000..9b26886
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/aemif.c
@@ -0,0 +1,71 @@
+/*
+ * Keystone2: Asynchronous EMIF Configuration
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/emif_defs.h>
+
+#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
+#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
+#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26)
+#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20)
+#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17)
+#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13)
+#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7)
+#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4)
+#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2)
+#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0)
+
+#define set_config_field(reg, field, val) \
+ do { \
+ if (val != -1) { \
+ reg &= ~AEMIF_CFG_##field(0xffffffff); \
+ reg |= AEMIF_CFG_##field(val); \
+ } \
+ } while (0)
+
+void configure_async_emif(int cs, struct async_emif_config *cfg)
+{
+ unsigned long tmp;
+
+ if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
+ tmp = __raw_readl(&davinci_emif_regs->nandfcr);
+ tmp |= (1 << cs);
+ __raw_writel(tmp, &davinci_emif_regs->nandfcr);
+
+ } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
+ tmp = __raw_readl(&davinci_emif_regs->one_nand_cr);
+ tmp |= (1 << cs);
+ __raw_writel(tmp, &davinci_emif_regs->one_nand_cr);
+ }
+
+ tmp = __raw_readl(&davinci_emif_regs->abncr[cs]);
+
+ set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
+ set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
+ set_config_field(tmp, WR_SETUP, cfg->wr_setup);
+ set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
+ set_config_field(tmp, WR_HOLD, cfg->wr_hold);
+ set_config_field(tmp, RD_SETUP, cfg->rd_setup);
+ set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
+ set_config_field(tmp, RD_HOLD, cfg->rd_hold);
+ set_config_field(tmp, TURN_AROUND, cfg->turn_around);
+ set_config_field(tmp, WIDTH, cfg->width);
+
+ __raw_writel(tmp, &davinci_emif_regs->abncr[cs]);
+}
+
+void init_async_emif(int num_cs, struct async_emif_config *config)
+{
+ int cs;
+
+ for (cs = 0; cs < num_cs; cs++)
+ configure_async_emif(cs, config + cs);
+}
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
new file mode 100644
index 0000000..bfa4c9d
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock.c
@@ -0,0 +1,318 @@
+/*
+ * Keystone2: pll initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm-generic/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+static void wait_for_completion(const struct pll_init_data *data)
+{
+ int i;
+ for (i = 0; i < 100; i++) {
+ sdelay(450);
+ if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
+ break;
+ }
+}
+
+struct pll_regs {
+ u32 reg0, reg1;
+};
+
+static const struct pll_regs pll_regs[] = {
+ [CORE_PLL] = { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
+ [PASS_PLL] = { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
+ [TETRIS_PLL] = { K2HK_ARMPLLCTL0, K2HK_ARMPLLCTL1},
+ [DDR3A_PLL] = { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
+ [DDR3B_PLL] = { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
+};
+
+/* Fout = Fref * NF(mult) / NR(prediv) / OD */
+static unsigned long pll_freq_get(int pll)
+{
+ unsigned long mult = 1, prediv = 1, output_div = 2;
+ unsigned long ret;
+ u32 tmp, reg;
+
+ if (pll == CORE_PLL) {
+ ret = external_clk[sys_clk];
+ if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+ /* PLL mode */
+ tmp = __raw_readl(K2HK_MAINPLLCTL0);
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+ (pllctl_reg_read(pll, mult) &
+ PLLM_MULT_LO_MASK)) + 1;
+ output_div = ((pllctl_reg_read(pll, secctl) >>
+ PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+ ret = ret / prediv / output_div * mult;
+ }
+ } else {
+ switch (pll) {
+ case PASS_PLL:
+ ret = external_clk[pa_clk];
+ reg = K2HK_PASSPLLCTL0;
+ break;
+ case TETRIS_PLL:
+ ret = external_clk[tetris_clk];
+ reg = K2HK_ARMPLLCTL0;
+ break;
+ case DDR3A_PLL:
+ ret = external_clk[ddr3a_clk];
+ reg = K2HK_DDR3APLLCTL0;
+ break;
+ case DDR3B_PLL:
+ ret = external_clk[ddr3b_clk];
+ reg = K2HK_DDR3BPLLCTL0;
+ break;
+ default:
+ return 0;
+ }
+
+ tmp = __raw_readl(reg);
+
+ if (!(tmp & PLLCTL_BYPASS)) {
+ /* Bypass disabled */
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+ output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+ PLL_CLKOD_MASK) + 1;
+ ret = ((ret / prediv) * mult) / output_div;
+ }
+ }
+
+ return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ switch (clk) {
+ case core_pll_clk: return pll_freq_get(CORE_PLL);
+ case pass_pll_clk: return pll_freq_get(PASS_PLL);
+ case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
+ case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
+ case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
+ case sys_clk0_1_clk:
+ case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
+ case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
+ case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
+ case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
+ case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
+ case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
+ case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
+ case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
+ case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
+ case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
+ case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
+ case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
+ case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
+ case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
+ case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
+ default:
+ break;
+ }
+ return 0;
+}
+
+void init_pll(const struct pll_init_data *data)
+{
+ u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
+
+ pllm = data->pll_m - 1;
+ plld = (data->pll_d - 1) & PLL_DIV_MASK;
+ pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
+
+ if (data->pll == MAIN_PLL) {
+ /* The requered delay before main PLL configuration */
+ sdelay(210000);
+
+ tmp = pllctl_reg_read(data->pll, secctl);
+
+ if (tmp & (PLLCTL_BYPASS)) {
+ setbits_le32(pll_regs[data->pll].reg1,
+ BIT(MAIN_ENSAT_OFFSET));
+
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
+ PLLCTL_PLLENSRC);
+ sdelay(340);
+
+ pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
+ pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
+ sdelay(21000);
+
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
+ } else {
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
+ PLLCTL_PLLENSRC);
+ sdelay(340);
+ }
+
+ pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
+
+ clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
+ (pllm << 6));
+
+ /* Set the BWADJ (12 bit field) */
+ tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
+ clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
+ (tmp_ctl << PLL_BWADJ_LO_SHIFT));
+ clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
+ (tmp_ctl >> 8));
+
+ /*
+ * Set the pll divider (6 bit field) *
+ * PLLD[5:0] is located in MAINPLLCTL0
+ */
+ clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);
+
+ /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
+ pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
+ (pllod << PLL_CLKOD_SHIFT));
+ wait_for_completion(data);
+
+ pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
+ pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
+ pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
+ pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
+ pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
+
+ pllctl_reg_setbits(data->pll, alnctl, 0x1f);
+
+ /*
+ * Set GOSET bit in PLLCMD to initiate the GO operation
+ * to change the divide
+ */
+ pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
+ sdelay(1500); /* wait for the phase adj */
+ wait_for_completion(data);
+
+ /* Reset PLL */
+ pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
+ sdelay(21000); /* Wait for a minimum of 7 us*/
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
+ sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
+
+ pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
+
+ tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
+
+ } else if (data->pll == TETRIS_PLL) {
+ bwadj = pllm >> 1;
+ /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
+ setbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+ /*
+ * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
+ * only applicable for Kepler
+ */
+ clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+ /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
+ setbits_le32(pll_regs[data->pll].reg1 ,
+ PLL_PLLRST | PLLCTL_ENSAT);
+
+ /*
+ * 3 Program PLLM and PLLD in PLLCTL0 register
+ * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
+ * PLLCTL1 register. BWADJ value must be set
+ * to ((PLLM + 1) >> 1) – 1)
+ */
+ tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
+ (pllm << 6) |
+ (plld & PLL_DIV_MASK) |
+ (pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
+ __raw_writel(tmp, pll_regs[data->pll].reg0);
+
+ /* Set BWADJ[11:8] bits */
+ tmp = __raw_readl(pll_regs[data->pll].reg1);
+ tmp &= ~(PLL_BWADJ_HI_MASK);
+ tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
+ __raw_writel(tmp, pll_regs[data->pll].reg1);
+ /*
+ * 5 Wait for at least 5 us based on the reference
+ * clock (PLL reset time)
+ */
+ sdelay(21000); /* Wait for a minimum of 7 us*/
+
+ /* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
+ clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
+ /*
+ * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
+ * (PLL lock time)
+ */
+ sdelay(105000);
+ /* 8 disable bypass */
+ clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+ /*
+ * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
+ * only applicable for Kepler
+ */
+ setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+ } else {
+ setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
+ /*
+ * process keeps state of Bypass bit while programming
+ * all other DDR PLL settings
+ */
+ tmp = __raw_readl(pll_regs[data->pll].reg0);
+ tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
+
+ /*
+ * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
+ * bypass disabled
+ */
+ bwadj = pllm >> 1;
+ tmp |= ((bwadj & PLL_BWADJ_LO_SHIFT) << PLL_BWADJ_LO_SHIFT) |
+ (pllm << PLL_MULT_SHIFT) |
+ (plld & PLL_DIV_MASK) |
+ (pllod << PLL_CLKOD_SHIFT);
+ __raw_writel(tmp, pll_regs[data->pll].reg0);
+
+ /* Set BWADJ[11:8] bits */
+ tmp = __raw_readl(pll_regs[data->pll].reg1);
+ tmp &= ~(PLL_BWADJ_HI_MASK);
+ tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
+
+ /* set PLL Select (bit 13) for PASS PLL */
+ if (data->pll == PASS_PLL)
+ tmp |= PLLCTL_PAPLL;
+
+ __raw_writel(tmp, pll_regs[data->pll].reg1);
+
+ /* Reset bit: bit 14 for both DDR3 & PASS PLL */
+ tmp = PLL_PLLRST;
+ /* Set RESET bit = 1 */
+ setbits_le32(pll_regs[data->pll].reg1, tmp);
+ /* Wait for a minimum of 7 us*/
+ sdelay(21000);
+ /* Clear RESET bit */
+ clrbits_le32(pll_regs[data->pll].reg1, tmp);
+ sdelay(105000);
+
+ /* clear BYPASS (Enable PLL Mode) */
+ clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+ sdelay(21000); /* Wait for a minimum of 7 us*/
+ }
+
+ /*
+ * This is required to provide a delay between multiple
+ * consequent PPL configurations
+ */
+ sdelay(210000);
+}
+
+void init_plls(int num_pll, struct pll_init_data *config)
+{
+ int i;
+
+ for (i = 0; i < num_pll; i++)
+ init_pll(&config[i]);
+}
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
new file mode 100644
index 0000000..afd30f3
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
@@ -0,0 +1,124 @@
+/*
+ * keystone2: commands for clocks
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/psc_defs.h>
+
+struct pll_init_data cmd_pll_data = {
+ .pll = MAIN_PLL,
+ .pll_m = 16,
+ .pll_d = 1,
+ .pll_od = 2,
+};
+
+int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc != 5)
+ goto pll_cmd_usage;
+
+ if (strncmp(argv[1], "pa", 2) == 0)
+ cmd_pll_data.pll = PASS_PLL;
+ else if (strncmp(argv[1], "arm", 3) == 0)
+ cmd_pll_data.pll = TETRIS_PLL;
+ else if (strncmp(argv[1], "ddr3a", 5) == 0)
+ cmd_pll_data.pll = DDR3A_PLL;
+ else if (strncmp(argv[1], "ddr3b", 5) == 0)
+ cmd_pll_data.pll = DDR3B_PLL;
+ else
+ goto pll_cmd_usage;
+
+ cmd_pll_data.pll_m = simple_strtoul(argv[2], NULL, 10);
+ cmd_pll_data.pll_d = simple_strtoul(argv[3], NULL, 10);
+ cmd_pll_data.pll_od = simple_strtoul(argv[4], NULL, 10);
+
+ printf("Trying to set pll %d; mult %d; div %d; OD %d\n",
+ cmd_pll_data.pll, cmd_pll_data.pll_m,
+ cmd_pll_data.pll_d, cmd_pll_data.pll_od);
+ init_pll(&cmd_pll_data);
+
+ return 0;
+
+pll_cmd_usage:
+ return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+ pllset, 5, 0, do_pll_cmd,
+ "set pll multiplier and pre divider",
+ "<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
+);
+
+int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int clk;
+ unsigned int freq;
+
+ if (argc != 2)
+ goto getclk_cmd_usage;
+
+ clk = simple_strtoul(argv[1], NULL, 10);
+
+ freq = clk_get_rate(clk);
+ printf("clock index [%d] - frequency %u\n", clk, freq);
+ return 0;
+
+getclk_cmd_usage:
+ return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+ getclk, 2, 0, do_getclk_cmd,
+ "get clock rate",
+ "<clk index>\n"
+ "See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
+);
+
+int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int psc_module;
+ int res;
+
+ if (argc != 3)
+ goto psc_cmd_usage;
+
+ psc_module = simple_strtoul(argv[1], NULL, 10);
+ if (strcmp(argv[2], "en") == 0) {
+ res = psc_enable_module(psc_module);
+ printf("psc_enable_module(%d) - %s\n", psc_module,
+ (res) ? "ERROR" : "OK");
+ return 0;
+ }
+
+ if (strcmp(argv[2], "di") == 0) {
+ res = psc_disable_module(psc_module);
+ printf("psc_disable_module(%d) - %s\n", psc_module,
+ (res) ? "ERROR" : "OK");
+ return 0;
+ }
+
+ if (strcmp(argv[2], "domain") == 0) {
+ res = psc_disable_domain(psc_module);
+ printf("psc_disable_domain(%d) - %s\n", psc_module,
+ (res) ? "ERROR" : "OK");
+ return 0;
+ }
+
+psc_cmd_usage:
+ return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+ psc, 3, 0, do_psc_cmd,
+ "<enable/disable psc module os disable domain>",
+ "<mod/domain index> <en|di|domain>\n"
+ "See the hardware.h for Power and Sleep Controller (PSC) Domains\n"
+);
diff --git a/arch/arm/cpu/armv7/keystone/cmd_mon.c b/arch/arm/cpu/armv7/keystone/cmd_mon.c
new file mode 100644
index 0000000..f9f58a3
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/cmd_mon.c
@@ -0,0 +1,131 @@
+/*
+ * K2HK: secure kernel command file
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+asm(".arch_extension sec\n\t");
+
+static int mon_install(u32 addr, u32 dpsc, u32 freq)
+{
+ int result;
+
+ __asm__ __volatile__ (
+ "stmfd r13!, {lr}\n"
+ "mov r0, %1\n"
+ "mov r1, %2\n"
+ "mov r2, %3\n"
+ "blx r0\n"
+ "ldmfd r13!, {lr}\n"
+ : "=&r" (result)
+ : "r" (addr), "r" (dpsc), "r" (freq)
+ : "cc", "r0", "r1", "r2", "memory");
+ return result;
+}
+
+static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 addr, dpsc_base = 0x1E80000, freq;
+ int rcode = 0;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ freq = clk_get_rate(sys_clk0_6_clk);
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ rcode = mon_install(addr, dpsc_base, freq);
+ printf("## installed monitor, freq [%d], status %d\n",
+ freq, rcode);
+
+ return 0;
+}
+
+U_BOOT_CMD(mon_install, 2, 0, do_mon_install,
+ "Install boot kernel at 'addr'",
+ ""
+);
+
+static void core_spin(void)
+{
+ while (1)
+ ; /* forever */;
+}
+
+int mon_power_on(int core_id, void *ep)
+{
+ int result;
+
+ asm volatile (
+ "stmfd r13!, {lr}\n"
+ "mov r1, %1\n"
+ "mov r2, %2\n"
+ "mov r0, #0\n"
+ "smc #0\n"
+ "ldmfd r13!, {lr}\n"
+ : "=&r" (result)
+ : "r" (core_id), "r" (ep)
+ : "cc", "r0", "r1", "r2", "memory");
+ return result;
+}
+
+int mon_power_off(int core_id)
+{
+ int result;
+
+ asm volatile (
+ "stmfd r13!, {lr}\n"
+ "mov r1, %1\n"
+ "mov r0, #1\n"
+ "smc #1\n"
+ "ldmfd r13!, {lr}\n"
+ : "=&r" (result)
+ : "r" (core_id)
+ : "cc", "r0", "r1", "memory");
+ return result;
+}
+
+int do_mon_power(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int rcode = 0, core_id, on;
+ void (*fn)(void);
+
+ fn = core_spin;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ core_id = simple_strtoul(argv[1], NULL, 16);
+ on = simple_strtoul(argv[2], NULL, 16);
+
+ if (on)
+ rcode = mon_power_on(core_id, fn);
+ else
+ rcode = mon_power_off(core_id);
+
+ if (on) {
+ if (!rcode)
+ printf("core %d powered on successfully\n", core_id);
+ else
+ printf("core %d power on failure\n", core_id);
+ } else {
+ printf("core %d powered off successfully\n", core_id);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(mon_power, 3, 0, do_mon_power,
+ "Power On/Off secondary core",
+ "mon_power <coreid> <oper>\n"
+ "- coreid (1-3) and oper (1 - ON, 0 - OFF)\n"
+ ""
+);
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
new file mode 100644
index 0000000..4875db7
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -0,0 +1,69 @@
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
+{
+ unsigned int tmp;
+
+ while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
+ & 0x00000001) != 0x00000001)
+ ;
+
+ __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
+
+ tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
+ tmp &= ~(phy_cfg->pgcr1_mask);
+ tmp |= phy_cfg->pgcr1_val;
+ __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
+
+ __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET);
+ __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET);
+ __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET);
+ __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET);
+
+ tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
+ tmp &= ~(phy_cfg->dcr_mask);
+ tmp |= phy_cfg->dcr_val;
+ __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
+
+ __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
+ __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
+ __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
+ __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
+ __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
+ __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
+ __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
+ __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
+
+ __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
+ __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
+ __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
+
+ __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
+ while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
+ ;
+
+ __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
+ while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
+ ;
+}
+
+void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
+{
+ __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
+ __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
+ __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
+ __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
+ __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
+ __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
+ __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
+}
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
new file mode 100644
index 0000000..044015a
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -0,0 +1,56 @@
+/*
+ * Keystone2: Architecture initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+
+void chip_configuration_unlock(void)
+{
+ __raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
+ __raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
+}
+
+int arch_cpu_init(void)
+{
+ chip_configuration_unlock();
+ icache_enable();
+
+#ifdef CONFIG_SOC_K2HK
+ share_all_segments(8);
+ share_all_segments(9);
+ share_all_segments(10); /* QM PDSP */
+ share_all_segments(11); /* PCIE */
+#endif
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
+ u32 tmp;
+
+ tmp = *rstctrl & KS2_RSTCTRL_MASK;
+ *rstctrl = tmp | KS2_RSTCTRL_KEY;
+
+ *rstctrl &= KS2_RSTCTRL_SWRST;
+
+ for (;;)
+ ;
+}
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+#endif
+}
diff --git a/arch/arm/cpu/armv7/keystone/keystone_nav.c b/arch/arm/cpu/armv7/keystone/keystone_nav.c
new file mode 100644
index 0000000..39d6f99
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/keystone_nav.c
@@ -0,0 +1,376 @@
+/*
+ * Multicore Navigator driver for TI Keystone 2 devices.
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/keystone_nav.h>
+
+static int soc_type =
+#ifdef CONFIG_SOC_K2HK
+ k2hk;
+#endif
+
+struct qm_config k2hk_qm_memmap = {
+ .stat_cfg = 0x02a40000,
+ .queue = (struct qm_reg_queue *)0x02a80000,
+ .mngr_vbusm = 0x23a80000,
+ .i_lram = 0x00100000,
+ .proxy = (struct qm_reg_queue *)0x02ac0000,
+ .status_ram = 0x02a06000,
+ .mngr_cfg = (struct qm_cfg_reg *)0x02a02000,
+ .intd_cfg = 0x02a0c000,
+ .desc_mem = (struct descr_mem_setup_reg *)0x02a03000,
+ .region_num = 64,
+ .pdsp_cmd = 0x02a20000,
+ .pdsp_ctl = 0x02a0f000,
+ .pdsp_iram = 0x02a10000,
+ .qpool_num = 4000,
+};
+
+/*
+ * We are going to use only one type of descriptors - host packet
+ * descriptors. We staticaly allocate memory for them here
+ */
+struct qm_host_desc desc_pool[HDESC_NUM] __aligned(sizeof(struct qm_host_desc));
+
+static struct qm_config *qm_cfg;
+
+inline int num_of_desc_to_reg(int num_descr)
+{
+ int j, num;
+
+ for (j = 0, num = 32; j < 15; j++, num *= 2) {
+ if (num_descr <= num)
+ return j;
+ }
+
+ return 15;
+}
+
+static int _qm_init(struct qm_config *cfg)
+{
+ u32 j;
+
+ if (cfg == NULL)
+ return QM_ERR;
+
+ qm_cfg = cfg;
+
+ qm_cfg->mngr_cfg->link_ram_base0 = qm_cfg->i_lram;
+ qm_cfg->mngr_cfg->link_ram_size0 = HDESC_NUM * 8;
+ qm_cfg->mngr_cfg->link_ram_base1 = 0;
+ qm_cfg->mngr_cfg->link_ram_size1 = 0;
+ qm_cfg->mngr_cfg->link_ram_base2 = 0;
+
+ qm_cfg->desc_mem[0].base_addr = (u32)desc_pool;
+ qm_cfg->desc_mem[0].start_idx = 0;
+ qm_cfg->desc_mem[0].desc_reg_size =
+ (((sizeof(struct qm_host_desc) >> 4) - 1) << 16) |
+ num_of_desc_to_reg(HDESC_NUM);
+
+ memset(desc_pool, 0, sizeof(desc_pool));
+ for (j = 0; j < HDESC_NUM; j++)
+ qm_push(&desc_pool[j], qm_cfg->qpool_num);
+
+ return QM_OK;
+}
+
+int qm_init(void)
+{
+ switch (soc_type) {
+ case k2hk:
+ return _qm_init(&k2hk_qm_memmap);
+ }
+
+ return QM_ERR;
+}
+
+void qm_close(void)
+{
+ u32 j;
+
+ if (qm_cfg == NULL)
+ return;
+
+ queue_close(qm_cfg->qpool_num);
+
+ qm_cfg->mngr_cfg->link_ram_base0 = 0;
+ qm_cfg->mngr_cfg->link_ram_size0 = 0;
+ qm_cfg->mngr_cfg->link_ram_base1 = 0;
+ qm_cfg->mngr_cfg->link_ram_size1 = 0;
+ qm_cfg->mngr_cfg->link_ram_base2 = 0;
+
+ for (j = 0; j < qm_cfg->region_num; j++) {
+ qm_cfg->desc_mem[j].base_addr = 0;
+ qm_cfg->desc_mem[j].start_idx = 0;
+ qm_cfg->desc_mem[j].desc_reg_size = 0;
+ }
+
+ qm_cfg = NULL;
+}
+
+void qm_push(struct qm_host_desc *hd, u32 qnum)
+{
+ u32 regd;
+
+ if (!qm_cfg)
+ return;
+
+ cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4);
+ regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1);
+ writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh);
+}
+
+void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
+ void *buff_ptr, u32 buff_len)
+{
+ hd->orig_buff_len = buff_len;
+ hd->buff_len = buff_len;
+ hd->orig_buff_ptr = (u32)buff_ptr;
+ hd->buff_ptr = (u32)buff_ptr;
+ qm_push(hd, qnum);
+}
+
+struct qm_host_desc *qm_pop(u32 qnum)
+{
+ u32 uhd;
+
+ if (!qm_cfg)
+ return NULL;
+
+ uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf;
+ if (uhd)
+ cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4);
+
+ return (struct qm_host_desc *)uhd;
+}
+
+struct qm_host_desc *qm_pop_from_free_pool(void)
+{
+ if (!qm_cfg)
+ return NULL;
+
+ return qm_pop(qm_cfg->qpool_num);
+}
+
+void queue_close(u32 qnum)
+{
+ struct qm_host_desc *hd;
+
+ while ((hd = qm_pop(qnum)))
+ ;
+}
+
+/*
+ * DMA API
+ */
+
+struct pktdma_cfg k2hk_netcp_pktdma = {
+ .global = (struct global_ctl_regs *)0x02004000,
+ .tx_ch = (struct tx_chan_regs *)0x02004400,
+ .tx_ch_num = 9,
+ .rx_ch = (struct rx_chan_regs *)0x02004800,
+ .rx_ch_num = 26,
+ .tx_sched = (u32 *)0x02004c00,
+ .rx_flows = (struct rx_flow_regs *)0x02005000,
+ .rx_flow_num = 32,
+ .rx_free_q = 4001,
+ .rx_rcv_q = 4002,
+ .tx_snd_q = 648,
+};
+
+struct pktdma_cfg *netcp;
+
+static int netcp_rx_disable(void)
+{
+ u32 j, v, k;
+
+ for (j = 0; j < netcp->rx_ch_num; j++) {
+ v = readl(&netcp->rx_ch[j].cfg_a);
+ if (!(v & CPDMA_CHAN_A_ENABLE))
+ continue;
+
+ writel(v | CPDMA_CHAN_A_TDOWN, &netcp->rx_ch[j].cfg_a);
+ for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
+ udelay(100);
+ v = readl(&netcp->rx_ch[j].cfg_a);
+ if (!(v & CPDMA_CHAN_A_ENABLE))
+ continue;
+ }
+ /* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
+ }
+
+ /* Clear all of the flow registers */
+ for (j = 0; j < netcp->rx_flow_num; j++) {
+ writel(0, &netcp->rx_flows[j].control);
+ writel(0, &netcp->rx_flows[j].tags);
+ writel(0, &netcp->rx_flows[j].tag_sel);
+ writel(0, &netcp->rx_flows[j].fdq_sel[0]);
+ writel(0, &netcp->rx_flows[j].fdq_sel[1]);
+ writel(0, &netcp->rx_flows[j].thresh[0]);
+ writel(0, &netcp->rx_flows[j].thresh[1]);
+ writel(0, &netcp->rx_flows[j].thresh[2]);
+ }
+
+ return QM_OK;
+}
+
+static int netcp_tx_disable(void)
+{
+ u32 j, v, k;
+
+ for (j = 0; j < netcp->tx_ch_num; j++) {
+ v = readl(&netcp->tx_ch[j].cfg_a);
+ if (!(v & CPDMA_CHAN_A_ENABLE))
+ continue;
+
+ writel(v | CPDMA_CHAN_A_TDOWN, &netcp->tx_ch[j].cfg_a);
+ for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
+ udelay(100);
+ v = readl(&netcp->tx_ch[j].cfg_a);
+ if (!(v & CPDMA_CHAN_A_ENABLE))
+ continue;
+ }
+ /* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
+ }
+
+ return QM_OK;
+}
+
+static int _netcp_init(struct pktdma_cfg *netcp_cfg,
+ struct rx_buff_desc *rx_buffers)
+{
+ u32 j, v;
+ struct qm_host_desc *hd;
+ u8 *rx_ptr;
+
+ if (netcp_cfg == NULL || rx_buffers == NULL ||
+ rx_buffers->buff_ptr == NULL || qm_cfg == NULL)
+ return QM_ERR;
+
+ netcp = netcp_cfg;
+ netcp->rx_flow = rx_buffers->rx_flow;
+
+ /* init rx queue */
+ rx_ptr = rx_buffers->buff_ptr;
+
+ for (j = 0; j < rx_buffers->num_buffs; j++) {
+ hd = qm_pop(qm_cfg->qpool_num);
+ if (hd == NULL)
+ return QM_ERR;
+
+ qm_buff_push(hd, netcp->rx_free_q,
+ rx_ptr, rx_buffers->buff_len);
+
+ rx_ptr += rx_buffers->buff_len;
+ }
+
+ netcp_rx_disable();
+
+ /* configure rx channels */
+ v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, netcp->rx_rcv_q);
+ writel(v, &netcp->rx_flows[netcp->rx_flow].control);
+ writel(0, &netcp->rx_flows[netcp->rx_flow].tags);
+ writel(0, &netcp->rx_flows[netcp->rx_flow].tag_sel);
+
+ v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, netcp->rx_free_q, 0,
+ netcp->rx_free_q);
+
+ writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[0]);
+ writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[1]);
+ writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[0]);
+ writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[1]);
+ writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[2]);
+
+ for (j = 0; j < netcp->rx_ch_num; j++)
+ writel(CPDMA_CHAN_A_ENABLE, &netcp->rx_ch[j].cfg_a);
+
+ /* configure tx channels */
+ /* Disable loopback in the tx direction */
+ writel(0, &netcp->global->emulation_control);
+
+/* TODO: make it dependend on a soc type variable */
+#ifdef CONFIG_SOC_K2HK
+ /* Set QM base address, only for K2x devices */
+ writel(0x23a80000, &netcp->global->qm_base_addr[0]);
+#endif
+
+ /* Enable all channels. The current state isn't important */
+ for (j = 0; j < netcp->tx_ch_num; j++) {
+ writel(0, &netcp->tx_ch[j].cfg_b);
+ writel(CPDMA_CHAN_A_ENABLE, &netcp->tx_ch[j].cfg_a);
+ }
+
+ return QM_OK;
+}
+
+int netcp_init(struct rx_buff_desc *rx_buffers)
+{
+ switch (soc_type) {
+ case k2hk:
+ _netcp_init(&k2hk_netcp_pktdma, rx_buffers);
+ return QM_OK;
+ }
+ return QM_ERR;
+}
+
+int netcp_close(void)
+{
+ if (!netcp)
+ return QM_ERR;
+
+ netcp_tx_disable();
+ netcp_rx_disable();
+
+ queue_close(netcp->rx_free_q);
+ queue_close(netcp->rx_rcv_q);
+ queue_close(netcp->tx_snd_q);
+
+ return QM_OK;
+}
+
+int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2)
+{
+ struct qm_host_desc *hd;
+
+ hd = qm_pop(qm_cfg->qpool_num);
+ if (hd == NULL)
+ return QM_ERR;
+
+ hd->desc_info = num_bytes;
+ hd->swinfo[2] = swinfo2;
+ hd->packet_info = qm_cfg->qpool_num;
+
+ qm_buff_push(hd, netcp->tx_snd_q, pkt, num_bytes);
+
+ return QM_OK;
+}
+
+void *netcp_recv(u32 **pkt, int *num_bytes)
+{
+ struct qm_host_desc *hd;
+
+ hd = qm_pop(netcp->rx_rcv_q);
+ if (!hd)
+ return NULL;
+
+ *pkt = (u32 *)hd->buff_ptr;
+ *num_bytes = hd->desc_info & 0x3fffff;
+
+ return hd;
+}
+
+void netcp_release_rxhd(void *hd)
+{
+ struct qm_host_desc *_hd = (struct qm_host_desc *)hd;
+
+ _hd->buff_len = _hd->orig_buff_len;
+ _hd->buff_ptr = _hd->orig_buff_ptr;
+
+ qm_push(_hd, netcp->rx_free_q);
+}
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c
new file mode 100644
index 0000000..f3f1621
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/msmc.c
@@ -0,0 +1,68 @@
+/*
+ * MSMC controller utilities
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+struct mpax {
+ u32 mpaxl;
+ u32 mpaxh;
+};
+
+struct msms_regs {
+ u32 pid;
+ u32 _res_04;
+ u32 smcerrar;
+ u32 smcerrxr;
+ u32 smedcc;
+ u32 smcea;
+ u32 smsecc;
+ u32 smpfar;
+ u32 smpfxr;
+ u32 smpfr;
+ u32 smpfcr;
+ u32 _res_2c;
+ u32 sbndc[8];
+ u32 sbndm;
+ u32 sbnde;
+ u32 _res_58;
+ u32 cfglck;
+ u32 cfgulck;
+ u32 cfglckstat;
+ u32 sms_mpax_lck;
+ u32 sms_mpax_ulck;
+ u32 sms_mpax_lckstat;
+ u32 ses_mpax_lck;
+ u32 ses_mpax_ulck;
+ u32 ses_mpax_lckstat;
+ u32 smestat;
+ u32 smirstat;
+ u32 smirc;
+ u32 smiestat;
+ u32 smiec;
+ u32 _res_94_c0[12];
+ u32 smncerrar;
+ u32 smncerrxr;
+ u32 smncea;
+ u32 _res_d0_1fc[76];
+ struct mpax sms[16][8];
+ struct mpax ses[16][8];
+};
+
+
+void share_all_segments(int priv_id)
+{
+ struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE;
+ int j;
+
+ for (j = 0; j < 8; j++) {
+ msmc->sms[priv_id][j].mpaxh &= 0xffffff7ful;
+ msmc->ses[priv_id][j].mpaxh &= 0xffffff7ful;
+ }
+}
diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/cpu/armv7/keystone/psc.c
new file mode 100644
index 0000000..c844dc8
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/psc.c
@@ -0,0 +1,237 @@
+/*
+ * Keystone: PSC configuration module
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm-generic/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/psc_defs.h>
+
+#define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr))
+#define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr))
+
+#ifdef CONFIG_SOC_K2HK
+#define DEVICE_PSC_BASE K2HK_PSC_BASE
+#endif
+
+int psc_delay(void)
+{
+ udelay(10);
+ return 10;
+}
+
+/*
+ * FUNCTION PURPOSE: Wait for end of transitional state
+ *
+ * DESCRIPTION: Polls pstat for the selected domain and waits for transitions
+ * to be complete.
+ *
+ * Since this is boot loader code it is *ASSUMED* that interrupts
+ * are disabled and no other core is mucking around with the psc
+ * at the same time.
+ *
+ * Returns 0 when the domain is free. Returns -1 if a timeout
+ * occurred waiting for the completion.
+ */
+int psc_wait(u32 domain_num)
+{
+ u32 retry;
+ u32 ptstat;
+
+ /*
+ * Do nothing if the power domain is in transition. This should never
+ * happen since the boot code is the only software accesses psc.
+ * It's still remotely possible that the hardware state machines
+ * initiate transitions.
+ * Don't trap if the domain (or a module in this domain) is
+ * stuck in transition.
+ */
+ retry = 0;
+
+ do {
+ ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
+ ptstat = ptstat & (1 << domain_num);
+ } while ((ptstat != 0) && ((retry += psc_delay()) <
+ PSC_PTSTAT_TIMEOUT_LIMIT));
+
+ if (retry >= PSC_PTSTAT_TIMEOUT_LIMIT)
+ return -1;
+
+ return 0;
+}
+
+u32 psc_get_domain_num(u32 mod_num)
+{
+ u32 domain_num;
+
+ /* Get the power domain associated with the module number */
+ domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
+ PSC_REG_MDCFG(mod_num));
+ domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
+
+ return domain_num;
+}
+
+/*
+ * FUNCTION PURPOSE: Power up/down a module
+ *
+ * DESCRIPTION: Powers up/down the requested module and the associated power
+ * domain if required. No action is taken it the module is
+ * already powered up/down.
+ *
+ * This only controls modules. The domain in which the module
+ * resides will be left in the power on state. Multiple modules
+ * can exist in a power domain, so powering down the domain based
+ * on a single module is not done.
+ *
+ * Returns 0 on success, -1 if the module can't be powered up, or
+ * if there is a timeout waiting for the transition.
+ */
+int psc_set_state(u32 mod_num, u32 state)
+{
+ u32 domain_num;
+ u32 pdctl;
+ u32 mdctl;
+ u32 ptcmd;
+ u32 reset_iso;
+ u32 v;
+
+ /*
+ * Get the power domain associated with the module number, and reset
+ * isolation functionality
+ */
+ v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+ domain_num = PSC_REG_MDCFG_GET_PD(v);
+ reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
+
+ /* Wait for the status of the domain/module to be non-transitional */
+ if (psc_wait(domain_num) != 0)
+ return -1;
+
+ /*
+ * Perform configuration even if the current status matches the
+ * existing state
+ *
+ * Set the next state of the power domain to on. It's OK if the domain
+ * is always on. This code will not ever power down a domain, so no
+ * change is made if the new state is power down.
+ */
+ if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
+ pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
+ PSC_REG_PDCTL(domain_num));
+ pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
+ PSC_REG_VAL_PDCTL_NEXT_ON);
+ DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
+ pdctl);
+ }
+
+ /* Set the next state for the module to enabled/disabled */
+ mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
+ mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
+ DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+
+ /* Trigger the enable */
+ ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+ ptcmd |= (u32)(1<<domain_num);
+ DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+
+ /* Wait on the complete */
+ return psc_wait(domain_num);
+}
+
+/*
+ * FUNCTION PURPOSE: Power up a module
+ *
+ * DESCRIPTION: Powers up the requested module and the associated power domain
+ * if required. No action is taken it the module is already
+ * powered up.
+ *
+ * Returns 0 on success, -1 if the module can't be powered up, or
+ * if there is a timeout waiting for the transition.
+ */
+int psc_enable_module(u32 mod_num)
+{
+ u32 mdctl;
+
+ /* Set the bit to apply reset */
+ mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
+ return 0;
+
+ return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_ON);
+}
+
+/*
+ * FUNCTION PURPOSE: Power down a module
+ *
+ * DESCRIPTION: Powers down the requested module.
+ *
+ * Returns 0 on success, -1 on failure or timeout.
+ */
+int psc_disable_module(u32 mod_num)
+{
+ u32 mdctl;
+
+ /* Set the bit to apply reset */
+ mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ if ((mdctl & 0x3f) == 0)
+ return 0;
+ mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
+ DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+
+ return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
+}
+
+/*
+ * FUNCTION PURPOSE: Set the reset isolation bit in mdctl
+ *
+ * DESCRIPTION: The reset isolation enable bit is set. The state of the module
+ * is not changed. Returns 0 if the module config showed that
+ * reset isolation is supported. Returns 1 otherwise. This is not
+ * an error, but setting the bit in mdctl has no effect.
+ */
+int psc_set_reset_iso(u32 mod_num)
+{
+ u32 v;
+ u32 mdctl;
+
+ /* Set the reset isolation bit */
+ mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
+ DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+
+ v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+ if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
+ return 0;
+
+ return 1;
+}
+
+/*
+ * FUNCTION PURPOSE: Disable a power domain
+ *
+ * DESCRIPTION: The power domain is disabled
+ */
+int psc_disable_domain(u32 domain_num)
+{
+ u32 pdctl;
+ u32 ptcmd;
+
+ pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num));
+ pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
+ pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
+ DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
+
+ ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+ ptcmd |= (u32)(1 << domain_num);
+ DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+
+ return psc_wait(domain_num);
+}
diff --git a/arch/arm/cpu/armv7/keystone/spl.c b/arch/arm/cpu/armv7/keystone/spl.c
new file mode 100644
index 0000000..e07b64d
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/spl.c
@@ -0,0 +1,45 @@
+/*
+ * common spl init code
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <spl.h>
+#include <spi_flash.h>
+
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_799,
+ TETRIS_PLL_500,
+};
+
+void spl_init_keystone_plls(void)
+{
+ init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+
+void spl_board_init(void)
+{
+ spl_init_keystone_plls();
+ preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+#if defined(CONFIG_SPL_SPI_LOAD)
+ return BOOT_DEVICE_SPI;
+#else
+ puts("Unknown boot device\n");
+ hang();
+#endif
+}
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 52e0f4a..3033564 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -56,6 +56,17 @@ void save_omap_boot_params(void)
*((u32 *)(dev_data + BOOT_MODE_OFFSET));
}
}
+
+#ifdef CONFIG_DRA7XX
+ /*
+ * We get different values for QSPI_1 and QSPI_4 being used, but
+ * don't actually care about this difference. Rather than
+ * mangle the later code, if we're coming in as QSPI_4 just
+ * change to the QSPI_1 value.
+ */
+ if (gd->arch.omap_boot_params.omap_bootdevice == 11)
+ gd->arch.omap_boot_params.omap_bootdevice = BOOT_DEVICE_SPI;
+#endif
}
#ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c
index aabf2bd..1696c2d 100644
--- a/arch/arm/cpu/armv7/omap-common/utils.c
+++ b/arch/arm/cpu/armv7/omap-common/utils.c
@@ -5,6 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <asm/arch/sys_proto.h>
static void do_cancel_out(u32 *num, u32 *den, u32 factor)
{
while (1) {
@@ -39,3 +40,23 @@ void cancel_out(u32 *num, u32 *den, u32 den_limit)
*den = (*den + 1) / 2;
}
}
+
+void __weak usb_fake_mac_from_die_id(u32 *id)
+{
+ uint8_t device_mac[6];
+
+ if (!getenv("usbethaddr")) {
+ /*
+ * create a fake MAC address from the processor ID code.
+ * first byte is 0x02 to signify locally administered.
+ */
+ device_mac[0] = 0x02;
+ device_mac[1] = id[3] & 0xff;
+ device_mac[2] = id[2] & 0xff;
+ device_mac[3] = id[1] & 0xff;
+ device_mac[4] = id[0] & 0xff;
+ device_mac[5] = (id[0] >> 8) & 0xff;
+
+ eth_setenv_enetaddr("usbethaddr", device_mac);
+ }
+}
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 2922816..9bb1a1c 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -290,8 +290,8 @@ void watchdog_init(void)
* should not be running and does not generate a PRCM reset.
*/
- sr32(&prcm_base->fclken_wkup, 5, 1, 1);
- sr32(&prcm_base->iclken_wkup, 5, 1, 1);
+ setbits_le32(&prcm_base->fclken_wkup, 0x20);
+ setbits_le32(&prcm_base->iclken_wkup, 0x20);
wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
writel(WD_UNLOCK1, &wd2_base->wspr);
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 1bc27bd..529ad9a 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -132,9 +132,9 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
if (xip_safe) {
/*
* CORE DPLL
- * sr32(CM_CLKSEL2_EMU) set override to work when asleep
*/
- sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x00000007, PLL_FAST_RELOCK_BYPASS);
wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
LDELAY);
@@ -144,37 +144,50 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
*/
/* CM_CLKSEL1_EMU[DIV_DPLL3] */
- sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
- sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
+ clrsetbits_le32(&prcm_base->clksel1_emu,
+ 0x001F0000, (CORE_M3X2 + 1) << 16) ;
+ clrsetbits_le32(&prcm_base->clksel1_emu,
+ 0x001F0000, CORE_M3X2 << 16);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- sr32(&prcm_base->clksel1_pll, 6, 1, 0);
+ clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
/* SSI */
- sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
- sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
- sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x0000000C, CORE_L4_DIV << 2);
/* L3 */
- sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000003, CORE_L3_DIV);
/* GFX */
- sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
+ clrsetbits_le32(&prcm_base->clksel_gfx,
+ 0x00000007, GFX_DIV);
/* RESET MGR */
- sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
+ clrsetbits_le32(&prcm_base->clksel_wkup,
+ 0x00000006, WKUP_RSM << 1);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x000000F0, ptr->fsel << 4);
/* LOCK MODE */
- sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x00000007, PLL_LOCK);
wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
LDELAY);
@@ -186,29 +199,29 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
f_lock_pll = (void *) (SRAM_CLK_CODE);
p0 = readl(&prcm_base->clken_pll);
- sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- sr32(&p0, 4, 4, ptr->fsel);
+ clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
p1 = readl(&prcm_base->clksel1_pll);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- sr32(&p1, 27, 5, ptr->m2);
+ clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- sr32(&p1, 16, 11, ptr->m);
+ clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- sr32(&p1, 8, 7, ptr->n);
+ clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- sr32(&p1, 6, 1, 0);
+ clrbits_le32(&p1, 0x00000040);
p2 = readl(&prcm_base->clksel_core);
/* SSI */
- sr32(&p2, 8, 4, CORE_SSI_DIV);
+ clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
- sr32(&p2, 4, 2, CORE_FUSB_DIV);
+ clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
- sr32(&p2, 2, 2, CORE_L4_DIV);
+ clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
/* L3 */
- sr32(&p2, 0, 2, CORE_L3_DIV);
+ clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
p3 = (u32)&prcm_base->idlest_ckgen;
@@ -225,7 +238,7 @@ static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
ptr = ptr + clk_index;
/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
- sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
+ clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
/*
@@ -234,33 +247,38 @@ static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
* and then the actual divisor value
*/
/* M6 */
- sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1));
- sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2);
+ clrsetbits_le32(&prcm_base->clksel1_emu,
+ 0x1F000000, (PER_M6X2 + 1) << 24);
+ clrsetbits_le32(&prcm_base->clksel1_emu,
+ 0x1F000000, PER_M6X2 << 24);
/* M5 */
- sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1));
- sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2);
+ clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1));
+ clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2);
/* M4 */
- sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1));
- sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2);
+ clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1));
+ clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2);
/* M3 */
- sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1));
- sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2);
+ clrsetbits_le32(&prcm_base->clksel_dss,
+ 0x00001F00, (PER_M3X2 + 1) << 8);
+ clrsetbits_le32(&prcm_base->clksel_dss,
+ 0x00001F00, PER_M3X2 << 8);
/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
- sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1));
- sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1));
+ clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
/* Workaround end */
/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
- sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel2_pll,
+ 0x0007FF00, ptr->m << 8);
/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
- sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
/* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
- sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel);
+ clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20);
/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
- sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
}
@@ -273,13 +291,18 @@ static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
ptr = ptr + clk_index;
/* PER2 DPLL (DPLL5) */
- sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
+ clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
- sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
- sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
- sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
- sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); /* FREQSEL */
- sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
+ /* set M2 (usbtll_fck) */
+ clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
+ /* set m (11-bit multiplier) */
+ clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
+ /* set n (7-bit divider)*/
+ clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
+ /* FREQSEL */
+ clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4);
+ /* lock mode */
+ clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
}
@@ -294,16 +317,20 @@ static void mpu_init_34xx(u32 sil_index, u32 clk_index)
/* MPU DPLL (unlocked already) */
/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
- sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel2_pll_mpu,
+ 0x0000001F, ptr->m2);
/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
- sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
+ 0x0007FF00, ptr->m << 8);
/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
- sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
+ 0x0000007F, ptr->n);
/* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
- sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel);
+ clrsetbits_le32(&prcm_base->clken_pll_mpu,
+ 0x000000F0, ptr->fsel << 4);
}
static void iva_init_34xx(u32 sil_index, u32 clk_index)
@@ -316,23 +343,29 @@ static void iva_init_34xx(u32 sil_index, u32 clk_index)
/* IVA DPLL */
/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
- sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
+ clrsetbits_le32(&prcm_base->clken_pll_iva2,
+ 0x00000007, PLL_STOP);
wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
- sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel2_pll_iva2,
+ 0x0000001F, ptr->m2);
/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
- sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
+ 0x0007FF00, ptr->m << 8);
/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
- sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
+ 0x0000007F, ptr->n);
/* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
- sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel);
+ clrsetbits_le32(&prcm_base->clken_pll_iva2,
+ 0x000000F0, ptr->fsel << 4);
/* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
- sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll_iva2,
+ 0x00000007, PLL_LOCK);
wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
}
@@ -357,41 +390,54 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
/* CORE DPLL */
/* Select relock bypass: CM_CLKEN_PLL[0:2] */
- sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x00000007, PLL_FAST_RELOCK_BYPASS);
wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
LDELAY);
/* CM_CLKSEL1_EMU[DIV_DPLL3] */
- sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
+ clrsetbits_le32(&prcm_base->clksel1_emu,
+ 0x001F0000, CORE_M3X2 << 16);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel1_pll,
+ 0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- sr32(&prcm_base->clksel1_pll, 6, 1, 0);
+ clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
/* SSI */
- sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
- sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
- sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x0000000C, CORE_L4_DIV << 2);
/* L3 */
- sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
+ clrsetbits_le32(&prcm_base->clksel_core,
+ 0x00000003, CORE_L3_DIV);
/* GFX */
- sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X);
+ clrsetbits_le32(&prcm_base->clksel_gfx,
+ 0x00000007, GFX_DIV_36X);
/* RESET MGR */
- sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
+ clrsetbits_le32(&prcm_base->clksel_wkup,
+ 0x00000006, WKUP_RSM << 1);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x000000F0, ptr->fsel << 4);
/* LOCK MODE */
- sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll,
+ 0x00000007, PLL_LOCK);
wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
LDELAY);
@@ -403,29 +449,29 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
f_lock_pll = (void *) (SRAM_CLK_CODE);
p0 = readl(&prcm_base->clken_pll);
- sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- sr32(&p0, 4, 4, ptr->fsel);
+ clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
p1 = readl(&prcm_base->clksel1_pll);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- sr32(&p1, 27, 5, ptr->m2);
+ clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- sr32(&p1, 16, 11, ptr->m);
+ clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- sr32(&p1, 8, 7, ptr->n);
+ clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- sr32(&p1, 6, 1, 0);
+ clrbits_le32(&p1, 0x00000040);
p2 = readl(&prcm_base->clksel_core);
/* SSI */
- sr32(&p2, 8, 4, CORE_SSI_DIV);
+ clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
/* FSUSB */
- sr32(&p2, 4, 2, CORE_FUSB_DIV);
+ clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
/* L4 */
- sr32(&p2, 2, 2, CORE_L4_DIV);
+ clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
/* L3 */
- sr32(&p2, 0, 2, CORE_L3_DIV);
+ clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
p3 = (u32)&prcm_base->idlest_ckgen;
@@ -444,35 +490,35 @@ static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
ptr += clk_index;
/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
- sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
+ clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
/* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
- sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);
+ clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);
/* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
- sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);
+ clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);
/* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
- sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);
+ clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);
/* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
- sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);
+ clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);
/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
- sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
- sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);
/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
- sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
/* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
- sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);
+ clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);
/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
- sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
}
@@ -485,12 +531,16 @@ static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
ptr = ptr + clk_index;
/* PER2 DPLL (DPLL5) */
- sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
+ clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
- sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
- sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
- sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
- sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
+ /* set M2 (usbtll_fck) */
+ clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
+ /* set m (11-bit multiplier) */
+ clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
+ /* set n (7-bit divider)*/
+ clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
+ /* lock mode */
+ clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
}
@@ -505,13 +555,13 @@ static void mpu_init_36xx(u32 sil_index, u32 clk_index)
/* MPU DPLL (unlocked already */
/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
- sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2);
/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
- sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8);
/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
- sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n);
}
static void iva_init_36xx(u32 sil_index, u32 clk_index)
@@ -524,20 +574,20 @@ static void iva_init_36xx(u32 sil_index, u32 clk_index)
/* IVA DPLL */
/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
- sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
+ clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP);
wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
- sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
+ clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2);
/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
- sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
+ clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8);
/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
- sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
+ clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n);
/* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
- sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK);
wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
}
@@ -561,16 +611,16 @@ void prcm_init(void)
get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
/* set input crystal speed */
- sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
+ clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);
/* If the input clock is greater than 19.2M always divide/2 */
if (sys_clkin_sel > 2) {
/* input clock divider */
- sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
+ clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
clk_index = sys_clkin_sel / 2;
} else {
/* input clock divider */
- sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
+ clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
clk_index = sys_clkin_sel;
}
@@ -587,12 +637,14 @@ void prcm_init(void)
* input divider to /1 as it should never set to /6.5
* in this case.
*/
- if (sys_clkin_sel != 1) /* 13 MHz */
+ if (sys_clkin_sel != 1) { /* 13 MHz */
/* Bit 8: DPLL4_CLKINP_DIV */
- sr32(&prm_base->clksrc_ctrl, 8, 1, 0);
+ clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
+ }
/* Unlock MPU DPLL (slows things down, and needed later) */
- sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
+ clrsetbits_le32(&prcm_base->clken_pll_mpu,
+ 0x00000007, PLL_LOW_POWER_BYPASS);
wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
LDELAY);
@@ -603,7 +655,8 @@ void prcm_init(void)
mpu_init_36xx(0, clk_index);
/* Lock MPU DPLL to set frequency */
- sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll_mpu,
+ 0x00000007, PLL_LOCK);
wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
LDELAY);
} else {
@@ -620,7 +673,8 @@ void prcm_init(void)
sil_index = 1;
/* Unlock MPU DPLL (slows things down, and needed later) */
- sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
+ clrsetbits_le32(&prcm_base->clken_pll_mpu,
+ 0x00000007, PLL_LOW_POWER_BYPASS);
wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
LDELAY);
@@ -633,14 +687,15 @@ void prcm_init(void)
mpu_init_34xx(sil_index, clk_index);
/* Lock MPU DPLL to set frequency */
- sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
+ clrsetbits_le32(&prcm_base->clken_pll_mpu,
+ 0x00000007, PLL_LOCK);
wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
LDELAY);
}
/* Set up GPTimers to sys_clk source only */
- sr32(&prcm_base->clksel_per, 0, 8, 0xff);
- sr32(&prcm_base->clksel_wkup, 0, 1, 1);
+ setbits_le32(&prcm_base->clksel_per, 0x000000FF);
+ setbits_le32(&prcm_base->clksel_wkup, 1);
sdelay(5000);
}
@@ -653,16 +708,16 @@ void ehci_clocks_enable(void)
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
- sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
+ setbits_le32(&prcm_base->iclken_usbhost, 1);
/*
* Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
* and USBHOST_120M_FCLK (USBHOST_FCLK2)
*/
- sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
+ setbits_le32(&prcm_base->fclken_usbhost, 0x00000003);
/* Enable USBTTL_ICLK */
- sr32(&prcm_base->iclken3_core, 2, 1, 1);
+ setbits_le32(&prcm_base->iclken3_core, 0x00000004);
/* Enable USBTTL_FCLK */
- sr32(&prcm_base->fclken3_core, 2, 1, 1);
+ setbits_le32(&prcm_base->fclken3_core, 0x00000004);
}
/******************************************************************************
@@ -673,62 +728,62 @@ void per_clocks_enable(void)
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/* Enable GP2 timer. */
- sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
- sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */
- sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */
+ setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */
+ setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */
+ setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */
#ifdef CONFIG_SYS_NS16550
/* Enable UART1 clocks */
- sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
- sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
+ setbits_le32(&prcm_base->fclken1_core, 0x00002000);
+ setbits_le32(&prcm_base->iclken1_core, 0x00002000);
/* UART 3 Clocks */
- sr32(&prcm_base->fclken_per, 11, 1, 0x1);
- sr32(&prcm_base->iclken_per, 11, 1, 0x1);
+ setbits_le32(&prcm_base->fclken_per, 0x00000800);
+ setbits_le32(&prcm_base->iclken_per, 0x00000800);
#endif
#ifdef CONFIG_OMAP3_GPIO_2
- sr32(&prcm_base->fclken_per, 13, 1, 1);
- sr32(&prcm_base->iclken_per, 13, 1, 1);
+ setbits_le32(&prcm_base->fclken_per, 0x00002000);
+ setbits_le32(&prcm_base->iclken_per, 0x00002000);
#endif
#ifdef CONFIG_OMAP3_GPIO_3
- sr32(&prcm_base->fclken_per, 14, 1, 1);
- sr32(&prcm_base->iclken_per, 14, 1, 1);
+ setbits_le32(&prcm_base->fclken_per, 0x00004000);
+ setbits_le32(&prcm_base->iclken_per, 0x00004000);
#endif
#ifdef CONFIG_OMAP3_GPIO_4
- sr32(&prcm_base->fclken_per, 15, 1, 1);
- sr32(&prcm_base->iclken_per, 15, 1, 1);
+ setbits_le32(&prcm_base->fclken_per, 0x00008000);
+ setbits_le32(&prcm_base->iclken_per, 0x00008000);
#endif
#ifdef CONFIG_OMAP3_GPIO_5
- sr32(&prcm_base->fclken_per, 16, 1, 1);
- sr32(&prcm_base->iclken_per, 16, 1, 1);
+ setbits_le32(&prcm_base->fclken_per, 0x00010000);
+ setbits_le32(&prcm_base->iclken_per, 0x00010000);
#endif
#ifdef CONFIG_OMAP3_GPIO_6
- sr32(&prcm_base->fclken_per, 17, 1, 1);
- sr32(&prcm_base->iclken_per, 17, 1, 1);
+ setbits_le32(&prcm_base->fclken_per, 0x00020000);
+ setbits_le32(&prcm_base->iclken_per, 0x00020000);
#endif
#ifdef CONFIG_SYS_I2C_OMAP34XX
/* Turn on all 3 I2C clocks */
- sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
- sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
+ setbits_le32(&prcm_base->fclken1_core, 0x00038000);
+ setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */
#endif
/* Enable the ICLK for 32K Sync Timer as its used in udelay */
- sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
+ setbits_le32(&prcm_base->iclken_wkup, 0x00000004);
if (get_cpu_family() != CPU_AM35XX)
- sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
-
- sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
- sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
- sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
- sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
- sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
- sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
- sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
+ out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON);
+
+ out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON);
+ out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON);
+ out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON);
+ out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON);
+ out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON);
+ out_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
+ out_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
if (get_cpu_family() != CPU_AM35XX) {
- sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
- sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
+ out_le32(&prcm_base->fclken_cam, FCK_CAM_ON);
+ out_le32(&prcm_base->iclken_cam, ICK_CAM_ON);
}
sdelay(1000);
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
index 258786b..bef5f05 100644
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -41,11 +41,23 @@ static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
#endif /* CONFIG_DISPLAY_CPUINFO */
/*****************************************************************
+ * get_dieid(u32 *id) - read die ID
+ *****************************************************************/
+void get_dieid(u32 *id)
+{
+ struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
+
+ id[3] = readl(&id_base->die_id_0);
+ id[2] = readl(&id_base->die_id_1);
+ id[1] = readl(&id_base->die_id_2);
+ id[0] = readl(&id_base->die_id_3);
+}
+
+/*****************************************************************
* dieid_num_r(void) - read and set die ID
*****************************************************************/
void dieid_num_r(void)
{
- struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
char *uid_s, die_id[34];
u32 id[4];
@@ -54,10 +66,7 @@ void dieid_num_r(void)
uid_s = getenv("dieid#");
if (uid_s == NULL) {
- id[3] = readl(&id_base->die_id_0);
- id[2] = readl(&id_base->die_id_1);
- id[1] = readl(&id_base->die_id_2);
- id[0] = readl(&id_base->die_id_3);
+ get_dieid(id);
sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
setenv("dieid#", die_id);
uid_s = die_id;
diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/cpu/armv7/syslib.c
index caf9fbc..4ae2596 100644
--- a/arch/arm/cpu/armv7/syslib.c
+++ b/arch/arm/cpu/armv7/syslib.c
@@ -24,19 +24,6 @@ void sdelay(unsigned long loops)
"bne 1b":"=r" (loops):"0"(loops));
}
-/*****************************************************************
- * sr32 - clear & set a value in a bit range for a 32 bit address
- *****************************************************************/
-void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
-{
- u32 tmp, msk = 0;
- msk = 1 << num_bits;
- --msk;
- tmp = readl((u32)addr) & ~(msk << start_bit);
- tmp |= value << start_bit;
- writel(tmp, (u32)addr);
-}
-
/*********************************************************************
* wait_on_value() - common routine to allow waiting for changes in
* volatile regs.
generated by cgit v1.1 at 2024-11-09 19:34:06 +0000