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-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c32
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c10
2 files changed, 36 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index abe2d81..700d190 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -733,6 +733,15 @@ static void ungate_sata_clock(void)
/* Enable SATA clock. */
setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
}
+#else
+static void ungate_disp_axi_clock(void)
+{
+ struct mxc_ccm_reg *const imx_ccm =
+ (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* Enable display axi clock. */
+ setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_DISP_AXI_MASK);
+}
#endif
static void ungate_pcie_clock(void)
@@ -758,6 +767,9 @@ int enable_pcie_clock(void)
(struct anatop_regs *)ANATOP_BASE_ADDR;
struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ /* PCIe reference clock sourced from AXI. */
+ clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
+
/*
* Here be dragons!
*
@@ -773,22 +785,30 @@ int enable_pcie_clock(void)
#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
+#ifndef CONFIG_MX6SX
+ /* lvds_clk1 is sourced from sata ref on imx6q/dl/solo */
clrsetbits_le32(&anatop_regs->ana_misc1,
ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
- /* PCIe reference clock sourced from AXI. */
- clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
-
/* Party time! Ungate the clock to the PCIe. */
-#ifndef CONFIG_MX6SX
ungate_sata_clock();
-#endif
ungate_pcie_clock();
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
- BM_ANADIG_PLL_ENET_ENABLE_PCIE);
+ BM_ANADIG_PLL_ENET_ENABLE_PCIE);
+#else
+ /* lvds_clk1 is sourced from pcie ref on imx6sx */
+ clrsetbits_le32(&anatop_regs->ana_misc1,
+ ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
+ ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
+ ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xa);
+
+ ungate_disp_axi_clock();
+ ungate_pcie_clock();
+ return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_PCIE);
+#endif
}
#ifdef CONFIG_SECURE_BOOT
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index e4393b3..fa1d6e6 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -427,6 +427,16 @@ void vadc_power_down(void)
val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK,
writel(val, &iomux->gpr[5]);
}
+
+void pcie_power_up(void)
+{
+ set_ldo_voltage(LDO_PU, 1100); /* Set VDDPU to 1.1V */
+}
+
+void pcie_power_off(void)
+{
+ set_ldo_voltage(LDO_PU, 0); /* Set VDDPU to 1.1V */
+}
#endif
static void imx_set_vddpu_power_down(void)