diff options
Diffstat (limited to 'arch/arm/cpu/armv7/omap5')
-rw-r--r-- | arch/arm/cpu/armv7/omap5/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap5/clocks.c | 98 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 43 |
3 files changed, 43 insertions, 99 deletions
diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile index 81625f6..ce00e2c 100644 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o COBJS += hwinit.o -COBJS += clocks.o COBJS += emif.o COBJS += sdram.o COBJS += prcm-regs.o diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c deleted file mode 100644 index da5b3ac..0000000 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * - * Clock initialization for OMAP5 - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Aneesh V <aneesh@ti.com> - * Sricharan R <r.sricharan@ti.com> - * - * Based on previous work by: - * Santosh Shilimkar <santosh.shilimkar@ti.com> - * Rajendra Nayak <rnayak@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <asm/omap_common.h> -#include <asm/arch/clocks.h> -#include <asm/arch/sys_proto.h> -#include <asm/utils.h> -#include <asm/omap_gpio.h> -#include <asm/emif.h> - -#ifndef CONFIG_SPL_BUILD -/* - * printing to console doesn't work unless - * this code is executed from SPL - */ -#define printf(fmt, args...) -#define puts(s) -#endif - -/* - * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva - * We set the maximum voltages allowed here because Smart-Reflex is not - * enabled in bootloader. Voltage initialization in the kernel will set - * these to the nominal values after enabling Smart-Reflex - */ -void scale_vcores(void) -{ - u32 volt_core, volt_mpu, volt_mm; - - omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); - - /* Palmas settings */ - if (omap_revision() != OMAP5432_ES1_0) { - volt_core = VDD_CORE; - volt_mpu = VDD_MPU; - volt_mm = VDD_MM; - } else { - volt_core = VDD_CORE_5432; - volt_mpu = VDD_MPU_5432; - volt_mm = VDD_MM_5432; - } - - do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core); - do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu); - do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm); - - if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { - /* Configure LDO SRAM "magic" bits */ - writel(2, (*prcm)->prm_sldo_core_setup); - writel(2, (*prcm)->prm_sldo_mpu_setup); - writel(2, (*prcm)->prm_sldo_mm_setup); - } -} - -u32 get_offset_code(u32 volt_offset) -{ - u32 offset_code, step = 10000; /* 10 mV represented in uV */ - - volt_offset -= PALMAS_SMPS_BASE_VOLT_UV; - - offset_code = (volt_offset + step - 1) / step; - - /* - * Offset codes 1-6 all give the base voltage in Palmas - * Offset code 0 switches OFF the SMPS - */ - return offset_code + 6; -} diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index df375f9..13e618d 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -30,12 +30,15 @@ #include <asm/arch/sys_proto.h> #include <asm/omap_common.h> #include <asm/arch/clocks.h> +#include <asm/omap_gpio.h> #include <asm/io.h> struct prcm_regs const **prcm = (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; struct dplls const **dplls_data = (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; +struct vcores_data const **omap_vcores = + (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -179,6 +182,44 @@ struct dplls omap5_dplls_es1 = { .usb = usb_dpll_params_1920mhz }; +struct pmic_data palmas = { + .base_offset = PALMAS_SMPS_BASE_VOLT_UV, + .step = 10000, /* 10 mV represented in uV */ + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + .start_code = 6, +}; + +struct vcores_data omap5430_volts = { + .mpu.value = VDD_MPU, + .mpu.addr = SMPS_REG_ADDR_12_MPU, + .mpu.pmic = &palmas, + + .core.value = VDD_CORE, + .core.addr = SMPS_REG_ADDR_8_CORE, + .core.pmic = &palmas, + + .mm.value = VDD_MM, + .mm.addr = SMPS_REG_ADDR_45_IVA, + .mm.pmic = &palmas, +}; + +struct vcores_data omap5432_volts = { + .mpu.value = VDD_MPU_5432, + .mpu.addr = SMPS_REG_ADDR_12_MPU, + .mpu.pmic = &palmas, + + .core.value = VDD_CORE_5432, + .core.addr = SMPS_REG_ADDR_8_CORE, + .core.pmic = &palmas, + + .mm.value = VDD_MM_5432, + .mm.addr = SMPS_REG_ADDR_45_IVA, + .mm.pmic = &palmas, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -380,11 +421,13 @@ void hw_data_init(void) case OMAP5430_ES1_0: *prcm = &omap5_es1_prcm; *dplls_data = &omap5_dplls_es1; + *omap_vcores = &omap5430_volts; break; case OMAP5432_ES1_0: *prcm = &omap5_es1_prcm; *dplls_data = &omap5_dplls_es1; + *omap_vcores = &omap5432_volts; break; default: |