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Diffstat (limited to 'arch/arm/cpu/armv7/omap5/sdram.c')
-rw-r--r--arch/arm/cpu/armv7/omap5/sdram.c214
1 files changed, 153 insertions, 61 deletions
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index e65c116..2e18706 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -148,13 +148,13 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0E20400A,
- .emif_ddr_phy_ctlr_1 = 0x0E24400A,
- .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x009E009E,
- .emif_ddr_ext_phy_ctrl_3 = 0x009E009E,
- .emif_ddr_ext_phy_ctrl_4 = 0x009E009E,
- .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400A,
+ .emif_ddr_phy_ctlr_1 = 0x0024400A,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00B000B0,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00B000B0,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
+ .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@@ -172,13 +172,13 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0020400A,
- .emif_ddr_phy_ctlr_1 = 0x0E24400A,
- .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x009D009D,
- .emif_ddr_ext_phy_ctrl_3 = 0x009D009D,
- .emif_ddr_ext_phy_ctrl_4 = 0x009D009D,
- .emif_ddr_ext_phy_ctrl_5 = 0x009D009D,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400A,
+ .emif_ddr_phy_ctlr_1 = 0x0024400A,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00B000B0,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00B000B0,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
+ .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@@ -306,7 +306,7 @@ void emif_get_device_details(u32 emif_nr,
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
-const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ext_phy_ctrl_const_base[] = {
0x01004010,
0x00001004,
0x04010040,
@@ -329,7 +329,7 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x0
};
-const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
0x01004010,
0x00001004,
0x04010040,
@@ -352,7 +352,7 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x0
};
-const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
0x50D4350D,
0x00000D43,
0x04010040,
@@ -376,51 +376,61 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
};
const u32
-dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
- 0x009E009E,
- 0x002E002E,
- 0x002E002E,
- 0x002E002E,
- 0x002E002E,
- 0x002E002E,
- 0x004D004D,
- 0x004D004D,
- 0x004D004D,
- 0x004D004D,
- 0x004D004D,
- 0x004D004D,
- 0x004D004D,
- 0x004D004D,
- 0x004D004D,
- 0x004D004D,
- 0x0,
- 0x600020,
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
+ 0x00B000B0,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00800080,
+ 0x00600060,
+ 0x00600060,
+ 0x00600060,
+ 0x00600060,
+ 0x00600060,
+ 0x00800080,
+ 0x00800080,
0x40010080,
- 0x8102040
+ 0x08102040,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0
};
const u32
-dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
- 0x009D009D,
- 0x002D002D,
- 0x002D002D,
- 0x002D002D,
- 0x002D002D,
- 0x002D002D,
- 0x00570057,
- 0x00570057,
- 0x00570057,
- 0x00570057,
- 0x00570057,
- 0x00570057,
- 0x00570057,
- 0x00570057,
- 0x00570057,
- 0x00570057,
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
+ 0x00BB00BB,
+ 0x00440044,
+ 0x00440044,
+ 0x00440044,
+ 0x00440044,
+ 0x00440044,
+ 0x007F007F,
+ 0x007F007F,
+ 0x007F007F,
+ 0x007F007F,
+ 0x007F007F,
+ 0x00600060,
+ 0x00600060,
+ 0x00600060,
+ 0x00600060,
+ 0x00600060,
0x0,
- 0x600020,
+ 0x00600020,
0x40010080,
- 0x8102040
+ 0x08102040,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0
};
const struct lpddr2_mr_regs mr_regs = {
@@ -431,27 +441,38 @@ const struct lpddr2_mr_regs mr_regs = {
.mr16 = MR16_REF_FULL_ARRAY
};
-static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs)
+static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
+ const u32 **regs,
+ u32 *size)
{
switch (omap_revision()) {
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
*regs = ext_phy_ctrl_const_base;
+ *size = ARRAY_SIZE(ext_phy_ctrl_const_base);
break;
case OMAP5432_ES1_0:
*regs = ddr3_ext_phy_ctrl_const_base_es1;
+ *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
break;
case OMAP5432_ES2_0:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
+ *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
break;
case DRA752_ES1_0:
- if (emif_nr == 1)
+ if (emif_nr == 1) {
*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
- else
+ *size =
+ ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
+ } else {
*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
+ *size =
+ ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
+ }
break;
default:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
+ *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
}
}
@@ -468,6 +489,7 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
u32 emif_nr;
const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
+ u32 size;
emif_nr = (base == EMIF1_BASE) ? 1 : 2;
@@ -487,8 +509,10 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
* external phy 6-24 registers do not change with
* ddr frequency
*/
- emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs);
- for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
+ emif_get_ext_phy_ctrl_const_regs(emif_nr,
+ &ext_phy_ctrl_const_regs, &size);
+
+ for (i = 0; i < size; i++) {
writel(ext_phy_ctrl_const_regs[i],
emif_ext_phy_ctrl_base++);
/* Update shadow registers */
@@ -545,6 +569,74 @@ static const struct lpddr2_device_timings dev_4G_S4_timings = {
.min_tck = &min_tck,
};
+/*
+ * List of status registers to be controlled back to control registers
+ * after initial leveling
+ * readreg, writereg
+ */
+const struct read_write_regs omap5_bug_00339_regs[] = {
+ { 8, 5 },
+ { 9, 6 },
+ { 10, 7 },
+ { 14, 8 },
+ { 15, 9 },
+ { 16, 10 },
+ { 11, 2 },
+ { 12, 3 },
+ { 13, 4 },
+ { 17, 11 },
+ { 18, 12 },
+ { 19, 13 },
+};
+
+const struct read_write_regs dra_bug_00339_regs[] = {
+ { 7, 7 },
+ { 8, 8 },
+ { 9, 9 },
+ { 10, 10 },
+ { 11, 11 },
+ { 12, 2 },
+ { 13, 3 },
+ { 14, 4 },
+ { 15, 5 },
+ { 16, 6 },
+ { 17, 12 },
+ { 18, 13 },
+ { 19, 14 },
+ { 20, 15 },
+ { 21, 16 },
+ { 22, 17 },
+ { 23, 18 },
+ { 24, 19 },
+ { 25, 20 },
+ { 26, 21}
+};
+
+const struct read_write_regs *get_bug_regs(u32 *iterations)
+{
+ const struct read_write_regs *bug_00339_regs_ptr = NULL;
+
+ switch (omap_revision()) {
+ case OMAP5430_ES1_0:
+ case OMAP5430_ES2_0:
+ case OMAP5432_ES1_0:
+ case OMAP5432_ES2_0:
+ bug_00339_regs_ptr = omap5_bug_00339_regs;
+ *iterations = sizeof(omap5_bug_00339_regs)/
+ sizeof(omap5_bug_00339_regs[0]);
+ break;
+ case DRA752_ES1_0:
+ bug_00339_regs_ptr = dra_bug_00339_regs;
+ *iterations = sizeof(dra_bug_00339_regs)/
+ sizeof(dra_bug_00339_regs[0]);
+ break;
+ default:
+ printf("\n Error: UnKnown SOC");
+ }
+
+ return bug_00339_regs_ptr;
+}
+
void emif_get_device_timings_sdp(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings)
generated by cgit v1.1 at 2024-11-15 09:29:29 +0000