3 files changed, 20 insertions, 38 deletions

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index f3cd81a..89c587e 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -478,7 +478,7 @@ void omap3_outer_cache_disable(void)
 	 */
 	omap3_update_aux_cr(0, 0x2);
 }
-#endif
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
@@ -486,4 +486,4 @@ void enable_caches(void)
 	/* Enable D-cache. I-cache is already enabled in start.S */
 	dcache_enable();
 }
-#endif
+#endif /* !CONFIG_SYS_DCACHE_OFF */
diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
index 2fe5ac7..d04a5a1 100644
--- a/arch/arm/cpu/armv7/omap3/mem.c
+++ b/arch/arm/cpu/armv7/omap3/mem.c
@@ -42,14 +42,7 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
 	M_NAND_GPMC_CONFIG5,
 	M_NAND_GPMC_CONFIG6, 0
 };
-
-#if defined(CONFIG_ENV_IS_IN_NAND)
-#define GPMC_CS 0
-#else
-#define GPMC_CS 1
-#endif
-
-#endif
+#endif /* CONFIG_CMD_NAND */
 
 #if defined(CONFIG_CMD_ONENAND)
 static const u32 gpmc_onenand[GPMC_MAX_REG] = {
@@ -60,14 +53,7 @@ static const u32 gpmc_onenand[GPMC_MAX_REG] = {
 	ONENAND_GPMC_CONFIG5,
 	ONENAND_GPMC_CONFIG6, 0
 };
-
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
-#define GPMC_CS 0
-#else
-#define GPMC_CS 1
-#endif
-
-#endif
+#endif /* CONFIG_CMD_ONENAND */
 
 /********************************************************
  *  mem_ok() - test used to see if timings are correct
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index f6d9b97..e32bf11 100644
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -113,18 +113,18 @@ u32 get_sdr_cs_offset(u32 cs)
  *  - Test CS to make sure it's OK for use
  */
 static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
-		u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr)
+			struct board_sdrc_timings *timings)
 {
 	/* Setup timings we got from the board. */
-	writel(mcfg, &sdrc_base->cs[cs].mcfg);
-	writel(ctrla, &sdrc_actim_base->ctrla);
-	writel(ctrlb, &sdrc_actim_base->ctrlb);
-	writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
+	writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
+	writel(timings->ctrla, &sdrc_actim_base->ctrla);
+	writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
+	writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
 	writel(CMD_NOP, &sdrc_base->cs[cs].manual);
 	writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
 	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
 	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-	writel(mr, &sdrc_base->cs[cs].mr);
+	writel(timings->mr, &sdrc_base->cs[cs].mr);
 
 	/*
 	 * Test ram in this bank
@@ -143,7 +143,7 @@ static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
 void do_sdrc_init(u32 cs, u32 early)
 {
 	struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
-	u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr;
+	struct board_sdrc_timings timings;
 
 	sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
 	sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
@@ -158,7 +158,7 @@ void do_sdrc_init(u32 cs, u32 early)
 	 * setup CS1.
 	 */
 #ifdef CONFIG_SPL_BUILD
-	get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr);
+	get_board_mem_timings(&timings);
 #endif
 	if (early) {
 		/* reset sdrc controller */
@@ -177,11 +177,9 @@ void do_sdrc_init(u32 cs, u32 early)
 		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
 		sdelay(0x20000);
 #ifdef CONFIG_SPL_BUILD
-		write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
-				rfr_ctrl, mr);
+		write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
 		make_cs1_contiguous();
-		write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb,
-				rfr_ctrl, mr);
+		write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
 #endif
 
 	}
@@ -193,14 +191,12 @@ void do_sdrc_init(u32 cs, u32 early)
 	 * so we may be asked now to setup CS1.
 	 */
 	if (cs == CS1) {
-		mcfg = readl(&sdrc_base->cs[CS0].mcfg),
-		rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
-		ctrla = readl(&sdrc_actim_base0->ctrla),
-		ctrlb = readl(&sdrc_actim_base0->ctrlb);
-		mr = readl(&sdrc_base->cs[CS0].mr);
-		write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb,
-				rfr_ctrl, mr);
-
+		timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
+		timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
+		timings.ctrla = readl(&sdrc_actim_base0->ctrla);
+		timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
+		timings.mr = readl(&sdrc_base->cs[CS0].mr);
+		write_sdrc_timings(cs, sdrc_actim_base1, &timings);
 	}
 }