diff options
Diffstat (limited to 'arch/arm/cpu/armv7/omap-common/clocks-common.c')
-rw-r--r-- | arch/arm/cpu/armv7/omap-common/clocks-common.c | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 03674e6..c94a807 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -372,6 +372,7 @@ static void setup_dplls(void) { u32 temp; const struct dpll_params *params; + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; debug("setup_dplls\n"); @@ -382,7 +383,8 @@ static void setup_dplls(void) * Core DPLL will be locked after setting up EMIF * using the FREQ_UPDATE method(freq_update_core()) */ - if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) + if (emif_sdram_type(readl(&emif->emif_sdram_config)) == + EMIF_SDRAM_TYPE_LPDDR2) do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, DPLL_NO_LOCK, "core"); else @@ -508,6 +510,12 @@ static u32 optimize_vcore_voltage(struct volts const *v) return val; } +#ifdef CONFIG_IODELAY_RECALIBRATION +void __weak recalibrate_iodelay(void) +{ +} +#endif + /* * Setup the voltages for the main SoC core power domains. * We start with the maximum voltages allowed here, as set in the corresponding @@ -561,6 +569,16 @@ void scale_vcores(struct vcores_data const *vcores) debug("cor: %d\n", vcores->core.value); do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic); + /* + * IO delay recalibration should be done immediately after + * adjusting AVS voltages for VDD_CORE_L. + * Respective boards should call __recalibrate_iodelay() + * with proper mux, virtual and manual mode configurations. + */ +#ifdef CONFIG_IODELAY_RECALIBRATION + recalibrate_iodelay(); +#endif + debug("mpu: %d\n", vcores->mpu.value); do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic); /* Configure MPU ABB LDO after scale */ @@ -587,6 +605,16 @@ void scale_vcores(struct vcores_data const *vcores) val = optimize_vcore_voltage(&vcores->core); do_scale_vcore(vcores->core.addr, val, vcores->core.pmic); + /* + * IO delay recalibration should be done immediately after + * adjusting AVS voltages for VDD_CORE_L. + * Respective boards should call __recalibrate_iodelay() + * with proper mux, virtual and manual mode configurations. + */ +#ifdef CONFIG_IODELAY_RECALIBRATION + recalibrate_iodelay(); +#endif + val = optimize_vcore_voltage(&vcores->mpu); do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic); |