diff options
Diffstat (limited to 'arch/arm/cpu/armv7/mx6')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/Makefile | 48 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 366 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/iomux-v3.c | 71 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/lowlevel_init.S | 24 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 82 |
5 files changed, 591 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile new file mode 100644 index 0000000..b0da028 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS = soc.o clock.o iomux-v3.o +SOBJS = lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c new file mode 100644 index 0000000..b143535 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -0,0 +1,366 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/ccm_regs.h> +#include <asm/arch/clock.h> + +enum pll_clocks { + PLL_SYS, /* System PLL */ + PLL_BUS, /* System Bus PLL*/ + PLL_USBOTG, /* OTG USB PLL */ + PLL_ENET, /* ENET PLL */ +}; + +struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR; + +static u32 decode_pll(enum pll_clocks pll, u32 infreq) +{ + u32 div; + + switch (pll) { + case PLL_SYS: + div = __raw_readl(&imx_ccm->analog_pll_sys); + div &= BM_ANADIG_PLL_SYS_DIV_SELECT; + + return infreq * (div >> 1); + case PLL_BUS: + div = __raw_readl(&imx_ccm->analog_pll_528); + div &= BM_ANADIG_PLL_528_DIV_SELECT; + + return infreq * (20 + (div << 1)); + case PLL_USBOTG: + div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl); + div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT; + + return infreq * (20 + (div << 1)); + case PLL_ENET: + div = __raw_readl(&imx_ccm->analog_pll_enet); + div &= BM_ANADIG_PLL_ENET_DIV_SELECT; + + return (div == 3 ? 125000000 : 25000000 * (div << 1)); + default: + return 0; + } + /* NOTREACHED */ +} + +static u32 get_mcu_main_clk(void) +{ + u32 reg, freq; + + reg = __raw_readl(&imx_ccm->cacrr); + reg &= MXC_CCM_CACRR_ARM_PODF_MASK; + reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET; + freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK); + + return freq / (reg + 1); +} + +static u32 get_periph_clk(void) +{ + u32 reg, freq = 0; + + reg = __raw_readl(&imx_ccm->cbcdr); + if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { + reg = __raw_readl(&imx_ccm->cbcmr); + reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK; + reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET; + + switch (reg) { + case 0: + freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK); + break; + case 1: + case 2: + freq = CONFIG_SYS_MX6_HCLK; + break; + default: + break; + } + } else { + reg = __raw_readl(&imx_ccm->cbcmr); + reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK; + reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET; + + switch (reg) { + case 0: + freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK); + break; + case 1: + freq = PLL2_PFD2_FREQ; + break; + case 2: + freq = PLL2_PFD0_FREQ; + break; + case 3: + freq = PLL2_PFD2_DIV_FREQ; + break; + default: + break; + } + } + + return freq; +} + + +static u32 get_ahb_clk(void) +{ + u32 reg, ahb_podf; + + reg = __raw_readl(&imx_ccm->cbcdr); + reg &= MXC_CCM_CBCDR_AHB_PODF_MASK; + ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; + + return get_periph_clk() / (ahb_podf + 1); +} + +static u32 get_ipg_clk(void) +{ + u32 reg, ipg_podf; + + reg = __raw_readl(&imx_ccm->cbcdr); + reg &= MXC_CCM_CBCDR_IPG_PODF_MASK; + ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET; + + return get_ahb_clk() / (ipg_podf + 1); +} + +static u32 get_ipg_per_clk(void) +{ + u32 reg, perclk_podf; + + reg = __raw_readl(&imx_ccm->cscmr1); + perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK; + + return get_ipg_clk() / (perclk_podf + 1); +} + +static u32 get_uart_clk(void) +{ + u32 reg, uart_podf; + + reg = __raw_readl(&imx_ccm->cscdr1); + reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; + uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; + + return PLL3_80M / (uart_podf + 1); +} + +static u32 get_cspi_clk(void) +{ + u32 reg, cspi_podf; + + reg = __raw_readl(&imx_ccm->cscdr2); + reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK; + cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; + + return PLL3_60M / (cspi_podf + 1); +} + +static u32 get_axi_clk(void) +{ + u32 root_freq, axi_podf; + u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); + + axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK; + axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET; + + if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { + if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) + root_freq = PLL2_PFD2_FREQ; + else + root_freq = PLL3_PFD1_FREQ; + } else + root_freq = get_periph_clk(); + + return root_freq / (axi_podf + 1); +} + +static u32 get_emi_slow_clk(void) +{ + u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0; + + cscmr1 = __raw_readl(&imx_ccm->cscmr1); + emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK; + emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET; + emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK; + emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET; + + switch (emi_clk_sel) { + case 0: + root_freq = get_axi_clk(); + break; + case 1: + root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK); + break; + case 2: + root_freq = PLL2_PFD2_FREQ; + break; + case 3: + root_freq = PLL2_PFD0_FREQ; + break; + } + + return root_freq / (emi_slow_pof + 1); +} + +static u32 get_mmdc_ch0_clk(void) +{ + u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); + u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >> + MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET; + + return get_periph_clk() / (mmdc_ch0_podf + 1); +} + +static u32 get_usdhc_clk(u32 port) +{ + u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0; + u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1); + u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1); + + switch (port) { + case 0: + usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >> + MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET; + clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL; + + break; + case 1: + usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >> + MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET; + clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL; + + break; + case 2: + usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >> + MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET; + clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL; + + break; + case 3: + usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >> + MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET; + clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL; + + break; + default: + break; + } + + if (clk_sel) + root_freq = PLL2_PFD0_FREQ; + else + root_freq = PLL2_PFD2_FREQ; + + return root_freq / (usdhc_podf + 1); +} + +u32 imx_get_uartclk(void) +{ + return get_uart_clk(); +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return get_mcu_main_clk(); + case MXC_PER_CLK: + return get_periph_clk(); + case MXC_AHB_CLK: + return get_ahb_clk(); + case MXC_IPG_CLK: + return get_ipg_clk(); + case MXC_IPG_PERCLK: + return get_ipg_per_clk(); + case MXC_UART_CLK: + return get_uart_clk(); + case MXC_CSPI_CLK: + return get_cspi_clk(); + case MXC_AXI_CLK: + return get_axi_clk(); + case MXC_EMI_SLOW_CLK: + return get_emi_slow_clk(); + case MXC_DDR_CLK: + return get_mmdc_ch0_clk(); + case MXC_ESDHC_CLK: + return get_usdhc_clk(0); + case MXC_ESDHC2_CLK: + return get_usdhc_clk(1); + case MXC_ESDHC3_CLK: + return get_usdhc_clk(2); + case MXC_ESDHC4_CLK: + return get_usdhc_clk(3); + case MXC_SATA_CLK: + return get_ahb_clk(); + default: + break; + } + + return -1; +} + +/* + * Dump some core clockes. + */ +int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u32 freq; + freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK); + printf("PLL_SYS %8d MHz\n", freq / 1000000); + freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK); + printf("PLL_BUS %8d MHz\n", freq / 1000000); + freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK); + printf("PLL_OTG %8d MHz\n", freq / 1000000); + freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK); + printf("PLL_NET %8d MHz\n", freq / 1000000); + + printf("\n"); + printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); + printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); + printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); + printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); + printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); + printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); + printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); + printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); + printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); + printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000); + printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000); + printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); + + return 0; +} + +/***************************************************/ + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks, + "display clocks", + "" +); diff --git a/arch/arm/cpu/armv7/mx6/iomux-v3.c b/arch/arm/cpu/armv7/mx6/iomux-v3.c new file mode 100644 index 0000000..8785532 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/iomux-v3.c @@ -0,0 +1,71 @@ +/* + * Based on the iomux-v3.c from Linux kernel: + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * <armlinux@phytec.de> + * + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6x_pins.h> +#include <asm/arch/iomux-v3.h> + +static void *base = (void *)IOMUXC_BASE_ADDR; + +/* + * configures a single pad in the iomuxer + */ +int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) +{ + u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; + u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; + u32 sel_input_ofs = + (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; + u32 sel_input = + (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; + u32 pad_ctrl_ofs = + (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; + u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; + + if (mux_ctrl_ofs) + __raw_writel(mux_mode, base + mux_ctrl_ofs); + + if (sel_input_ofs) + __raw_writel(sel_input, base + sel_input_ofs); + + if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) + __raw_writel(pad_ctrl, base + pad_ctrl_ofs); + + return 0; +} + +int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) +{ + iomux_v3_cfg_t *p = pad_list; + int i; + int ret; + + for (i = 0; i < count; i++) { + ret = imx_iomux_v3_setup_pad(*p); + if (ret) + return ret; + p++; + } + return 0; +} diff --git a/arch/arm/cpu/armv7/mx6/lowlevel_init.S b/arch/arm/cpu/armv7/mx6/lowlevel_init.S new file mode 100644 index 0000000..1864356 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/lowlevel_init.S @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +.section ".text.init", "x" + +.globl lowlevel_init +lowlevel_init: + + mov pc, lr diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c new file mode 100644 index 0000000..dff5e4e --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +u32 get_cpu_rev(void) +{ + int system_rev = 0x61000 | CHIP_REV_1_0; + + return system_rev; +} + +#ifdef CONFIG_ARCH_CPU_INIT +void init_aips(void) +{ + u32 reg = AIPS1_BASE_ADDR; + + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, reg + 0x00); + writel(0x77777777, reg + 0x04); + + reg = AIPS2_BASE_ADDR; + writel(0x77777777, reg + 0x00); + writel(0x77777777, reg + 0x04); +} + +int arch_cpu_init(void) +{ + init_aips(); + + return 0; +} +#endif + +#if defined(CONFIG_FEC_MXC) +void imx_get_mac_from_fuse(unsigned char *mac) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[4]; + struct fuse_bank4_regs *fuse = + (struct fuse_bank4_regs *)bank->fuse_regs; + + u32 mac_lo = readl(&fuse->mac_addr_low); + u32 mac_hi = readl(&fuse->mac_addr_high); + + *(u32 *)mac = mac_lo; + + mac[4] = mac_hi & 0xff; + mac[5] = (mac_hi >> 8) & 0xff; + +} +#endif |