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Diffstat (limited to 'arch/arm/cpu/armv7/ls102xa/cpu.c')
-rw-r--r--arch/arm/cpu/armv7/ls102xa/cpu.c34
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index b7dde45..ce2d92f 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -12,6 +12,8 @@
#include <netdev.h>
#include <fsl_esdhc.h>
+#include "fsl_epu.h"
+
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_DISPLAY_CPUINFO)
@@ -101,3 +103,35 @@ int cpu_eth_init(bd_t *bis)
return 0;
}
+
+int arch_cpu_init(void)
+{
+ void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+
+ /*
+ * After wakeup from deep sleep, Clear EPU registers
+ * as early as possible to prevent from possible issue.
+ * It's also safe to clear at normal boot.
+ */
+ fsl_epu_clean(epu_base);
+
+ return 0;
+}
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+/* Set the address at which the secondary core starts from.*/
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ out_be32(&gur->scratchrw[0], addr);
+}
+
+/* Release the secondary core from holdoff state and kick it */
+void smp_kick_all_cpus(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ out_be32(&gur->brrl, 0x2);
+}
+#endif