diff options
Diffstat (limited to 'arch/arm/cpu/arm926ejs/davinci/cpu.c')
-rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/cpu.c | 76 |
1 files changed, 32 insertions, 44 deletions
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 9ea9785..b3c9fb7 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -25,6 +25,8 @@ #include <asm/arch/hardware.h> #include <asm/io.h> +DECLARE_GLOBAL_DATA_PTR; + /* offsets from PLL controller base */ #define PLLC_PLLCTL 0x100 #define PLLC_PLLM 0x110 @@ -115,21 +117,8 @@ int clk_get(enum davinci_clk_ids id) out: return pll_out; } -#ifdef CONFIG_DISPLAY_CPUINFO -int print_cpuinfo(void) -{ - printf("Cores: ARM %d MHz", - clk_get(DAVINCI_ARM_CLKID) / 1000000); - printf("\nDDR: %d MHz\n", - /* DDR PHY uses an x2 input clock */ - clk_get(0x10001) / 1000000); - return 0; -} -#endif #else /* CONFIG_SOC_DA8XX */ -#ifdef CONFIG_DISPLAY_CPUINFO - static unsigned pll_div(volatile void *pllbase, unsigned offset) { u32 div; @@ -185,36 +174,6 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); } -int print_cpuinfo(void) -{ - /* REVISIT fetch and display CPU ID and revision information - * too ... that will matter as more revisions appear. - */ -#if defined(CONFIG_SOC_DM365) - printf("Cores: ARM %d MHz", - pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV)); -#else - printf("Cores: ARM %d MHz", - pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV)); -#endif - -#ifdef DSP_PLLDIV - printf(", DSP %d MHz", - pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV)); -#endif - - printf("\nDDR: %d MHz\n", - /* DDR PHY uses an x2 input clock */ -#if defined(CONFIG_SOC_DM365) - pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV) - / 2); -#else - pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV) - / 2); -#endif - return 0; -} - #ifdef DAVINCI_DM6467EVM unsigned int davinci_arm_clk_get() { @@ -228,9 +187,38 @@ unsigned int davinci_clk_get(unsigned int div) return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000; } #endif -#endif /* CONFIG_DISPLAY_CPUINFO */ #endif /* !CONFIG_SOC_DA8XX */ +int set_cpu_clk_info(void) +{ +#ifdef CONFIG_SOC_DA8XX + gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; + /* DDR PHY uses an x2 input clock */ + gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000; +#else + + unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE; +#if defined(CONFIG_SOC_DM365) + pllbase = DAVINCI_PLL_CNTRL1_BASE; +#endif + gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV); + +#ifdef DSP_PLLDIV + gd->bd->bi_dsp_freq = + pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV); +#else + gd->bd->bi_dsp_freq = 0; +#endif + + pllbase = DAVINCI_PLL_CNTRL1_BASE; +#if defined(CONFIG_SOC_DM365) + pllbase = DAVINCI_PLL_CNTRL0_BASE; +#endif + gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2; +#endif + return 0; +} + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() |