diff options
Diffstat (limited to 'arch/arm/cpu/arm920t')
| -rw-r--r-- | arch/arm/cpu/arm920t/s3c24x0/speed.c | 30 | ||||
| -rw-r--r-- | arch/arm/cpu/arm920t/s3c24x0/timer.c | 23 | ||||
| -rw-r--r-- | arch/arm/cpu/arm920t/s3c24x0/usb.c | 10 | ||||
| -rw-r--r-- | arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c | 12 | ||||
| -rw-r--r-- | arch/arm/cpu/arm920t/start.S | 149 |
5 files changed, 50 insertions, 174 deletions
diff --git a/arch/arm/cpu/arm920t/s3c24x0/speed.c b/arch/arm/cpu/arm920t/s3c24x0/speed.c index b13283a..3ae558d 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/speed.c +++ b/arch/arm/cpu/arm920t/s3c24x0/speed.c @@ -54,9 +54,9 @@ static ulong get_PLLCLK(int pllreg) ulong r, m, p, s; if (pllreg == MPLL) - r = readl(&clk_power->MPLLCON); + r = readl(&clk_power->mpllcon); else if (pllreg == UPLL) - r = readl(&clk_power->UPLLCON); + r = readl(&clk_power->upllcon); else hang(); @@ -64,7 +64,12 @@ static ulong get_PLLCLK(int pllreg) p = ((r & 0x003F0) >> 4) + 2; s = r & 0x3; +#if defined(CONFIG_S3C2440) + if (pllreg == MPLL) + return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s)); +#endif return (CONFIG_SYS_CLK_FREQ * m) / (p << s); + } /* return FCLK frequency */ @@ -77,8 +82,23 @@ ulong get_FCLK(void) ulong get_HCLK(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - - return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK(); +#ifdef CONFIG_S3C2440 + switch (readl(&clk_power->clkdivn) & 0x6) { + default: + case 0: + return get_FCLK(); + case 2: + return get_FCLK() / 2; + case 4: + return (readl(&clk_power->camdivn) & (1 << 9)) ? + get_FCLK() / 8 : get_FCLK() / 4; + case 6: + return (readl(&clk_power->camdivn) & (1 << 8)) ? + get_FCLK() / 6 : get_FCLK() / 3; + } +#else + return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK(); +#endif } /* return PCLK frequency */ @@ -86,7 +106,7 @@ ulong get_PCLK(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK(); + return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK(); } /* return UCLK frequency */ diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c index 7d47354..8cf9ff6 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/timer.c +++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c @@ -43,7 +43,7 @@ static inline ulong READ_TIMER(void) { struct s3c24x0_timers *timers = s3c24x0_get_base_timers(); - return readl(&timers->TCNTO4) & 0xffff; + return readl(&timers->tcnto4) & 0xffff; } static ulong timestamp; @@ -56,7 +56,7 @@ int timer_init(void) /* use PWM Timer 4 because it has no output */ /* prescaler for Timer 4 is 16 */ - writel(0x0f00, &timers->TCFG0); + writel(0x0f00, &timers->tcfg0); if (timer_load_val == 0) { /* * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 @@ -68,13 +68,13 @@ int timer_init(void) } /* load value for 10 ms timeout */ lastdec = timer_load_val; - writel(timer_load_val, &timers->TCNTB4); - /* auto load, manual update of Timer 4 */ - tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000; - writel(tmr, &timers->TCON); - /* auto load, start Timer 4 */ + writel(timer_load_val, &timers->tcntb4); + /* auto load, manual update of timer 4 */ + tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000; + writel(tmr, &timers->tcon); + /* auto load, start timer 4 */ tmr = (tmr & ~0x0700000) | 0x0500000; - writel(tmr, &timers->TCON); + writel(tmr, &timers->tcon); timestamp = 0; return (0); @@ -181,6 +181,7 @@ ulong get_tbclk(void) tbclk = timer_load_val * 100; #elif defined(CONFIG_SBC2410X) || \ defined(CONFIG_SMDK2410) || \ + defined(CONFIG_S3C2440) || \ defined(CONFIG_VCMA9) tbclk = CONFIG_SYS_HZ; #else @@ -206,13 +207,13 @@ void reset_cpu(ulong ignored) watchdog = s3c24x0_get_base_watchdog(); /* Disable watchdog */ - writel(0x0000, &watchdog->WTCON); + writel(0x0000, &watchdog->wtcon); /* Initialize watchdog timer count register */ - writel(0x0001, &watchdog->WTCNT); + writel(0x0001, &watchdog->wtcnt); /* Enable watchdog timer; assert reset at timer timeout */ - writel(0x0021, &watchdog->WTCON); + writel(0x0021, &watchdog->wtcon); while (1) /* loop forever and wait for reset to happen */; diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb.c b/arch/arm/cpu/arm920t/s3c24x0/usb.c index e468ed0..226a3f6 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/usb.c +++ b/arch/arm/cpu/arm920t/s3c24x0/usb.c @@ -39,14 +39,14 @@ int usb_cpu_init(void) * Set the 48 MHz UPLL clocking. Values are taken from * "PLL value selection guide", 6-23, s3c2400_UM.pdf. */ - writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON); + writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon); /* 1 = use pads related USB for USB host */ - writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR); + writel(readl(&gpio->misccr) | 0x8, &gpio->misccr); /* * Enable USB host clock. */ - writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); return 0; } @@ -55,14 +55,14 @@ int usb_cpu_stop(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); /* may not want to do this */ - writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); return 0; } int usb_cpu_init_fail(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); return 0; } diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c index 5aa8d64..ccc9738 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c @@ -1666,13 +1666,13 @@ int usb_lowlevel_init(void) * Set the 48 MHz UPLL clocking. Values are taken from * "PLL value selection guide", 6-23, s3c2400_UM.pdf. */ - clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2); - gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */ + clk_power->upllcon = ((40 << 12) + (1 << 4) + 2); + gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */ /* * Enable USB host clock. */ - clk_power->CLKCON |= (1 << 4); + clk_power->clkcon |= (1 << 4); memset(&gohci, 0, sizeof(struct ohci)); memset(&urb_priv, 0, sizeof(struct urb_priv)); @@ -1709,7 +1709,7 @@ int usb_lowlevel_init(void) if (hc_reset(&gohci) < 0) { hc_release_ohci(&gohci); /* Initialization failed */ - clk_power->CLKCON &= ~(1 << 4); + clk_power->clkcon &= ~(1 << 4); return -1; } @@ -1722,7 +1722,7 @@ int usb_lowlevel_init(void) err("can't start usb-%s", gohci.slot_name); hc_release_ohci(&gohci); /* Initialization failed */ - clk_power->CLKCON &= ~(1 << 4); + clk_power->clkcon &= ~(1 << 4); return -1; } #ifdef DEBUG @@ -1748,7 +1748,7 @@ int usb_lowlevel_stop(void) /* call hc_release_ohci() here ? */ hc_reset(&gohci); /* may not want to do this */ - clk_power->CLKCON &= ~(1 << 4); + clk_power->clkcon &= ~(1 << 4); return 0; } diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 343a760..d4edde7 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -24,6 +24,7 @@ * MA 02111-1307 USA */ +#include <asm-offsets.h> #include <common.h> #include <config.h> @@ -74,12 +75,6 @@ _fiq: .word fiq _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE -#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) -.globl _armboot_start -_armboot_start: - .word _start -#endif - /* * These are defined in the board-specific linker script. */ @@ -103,7 +98,6 @@ FIQ_STACK_START: .word 0x0badc0de #endif -#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) /* IRQ stack memory (calculated at run-time) + 8 bytes */ .globl IRQ_STACK_START_IN IRQ_STACK_START_IN: @@ -242,7 +236,6 @@ stack_setup: cmp r0, r6 beq clear_bss -#ifndef CONFIG_SKIP_RELOCATE_UBOOT copy_loop: ldmia r0!, {r9-r10} /* copy from source address [r0] */ stmia r6!, {r9-r10} /* copy to target address [r1] */ @@ -267,9 +260,8 @@ fixloop: str r4, [r2] add r2, r2, #4 cmp r2, r3 - bne fixloop + blo fixloop #endif -#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ clear_bss: #ifndef CONFIG_PRELOADER @@ -315,127 +307,6 @@ _nand_boot: .word nand_boot _board_init_r: .word board_init_r #endif -#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ -/* - * the actual start code - */ - -start_code: - /* - * set the cpu to SVC32 mode - */ - mrs r0, cpsr - bic r0, r0, #0x1f - orr r0, r0, #0xd3 - msr cpsr, r0 - - bl coloured_LED_init - bl red_LED_on - -#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) - /* - * relocate exception table - */ - ldr r0, =_start - ldr r1, =0x0 - mov r2, #16 -copyex: - subs r2, r2, #1 - ldr r3, [r0], #4 - str r3, [r1], #4 - bne copyex -#endif - -#ifdef CONFIG_S3C24X0 - /* turn off the watchdog */ - -# if defined(CONFIG_S3C2400) -# define pWTCON 0x15300000 -# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ -# define CLKDIVN 0x14800014 /* clock divisor register */ -#else -# define pWTCON 0x53000000 -# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ -# define INTSUBMSK 0x4A00001C -# define CLKDIVN 0x4C000014 /* clock divisor register */ -# endif - - ldr r0, =pWTCON - mov r1, #0x0 - str r1, [r0] - - /* - * mask all IRQs by setting all bits in the INTMR - default - */ - mov r1, #0xffffffff - ldr r0, =INTMSK - str r1, [r0] -# if defined(CONFIG_S3C2410) - ldr r1, =0x3ff - ldr r0, =INTSUBMSK - str r1, [r0] -# endif - - /* FCLK:HCLK:PCLK = 1:2:4 */ - /* default FCLK is 120 MHz ! */ - ldr r0, =CLKDIVN - mov r1, #3 - str r1, [r0] -#endif /* CONFIG_S3C24X0 */ - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - -#ifndef CONFIG_SKIP_RELOCATE_UBOOT -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - blo copy_loop -#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ - sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ -#ifdef CONFIG_USE_IRQ - sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - blo clbss_l - - ldr pc, _start_armboot - -_start_armboot: .word start_armboot -#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ - /* ************************************************************************* * @@ -524,15 +395,7 @@ cpu_init_crit: .macro bad_save_user_regs sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0-r12 -#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) - ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE) - sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) - /* set base 2 words into abort stack */ - sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) -#else ldr r2, IRQ_STACK_START_IN -#endif ldmia r2, {r2 - r3} @ get pc, cpsr add r0, sp, #S_FRAME_SIZE @ restore sp_SVC @@ -564,15 +427,7 @@ cpu_init_crit: .endm .macro get_bad_stack -#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) - ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE) - sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) - /* reserve a couple spots in abort stack */ - sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) -#else ldr r13, IRQ_STACK_START_IN @ setup our mode stack -#endif str lr, [r13] @ save caller lr / spsr mrs lr, spsr |