diff options
162 files changed, 3153 insertions, 698 deletions
@@ -437,7 +437,7 @@ D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots mor N: Andre Schwarz E: andre.schwarz@matrix-vision.de -D: Support for Matrix Vision boards (MVBLM7/MVBC_P) +D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR) N: Robert Schwebel E: r.schwebel@pengutronix.de diff --git a/MAINTAINERS b/MAINTAINERS index b617953..04c8730 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -422,6 +422,7 @@ Andre Schwarz <andre.schwarz@matrix-vision.de> mvbc_p MPC5200 mvblm7 MPC8343 + mvsmr MPC5200 Jon Smirl <jonsmirl@gmail.com> @@ -616,6 +617,10 @@ Simon Kagstrom <simon.kagstrom@netinsight.net> openrd_base ARM926EJS (Kirkwood SoC) +Minkyu Kang <mk7.kang@samsung.com> + + SMDKC100 ARM CORTEX-A8 (S5PC100 SoC) + Nishant Kamat <nskamat@ti.com> omap1610h2 ARM926EJS @@ -630,17 +635,17 @@ Sergey Kubushyn <ksi@koi8.net> SONATA ARM926EJS SCHMOOGIE ARM926EJS -Sandeep Paulraj <s-paulraj@ti.com> - - davinci_dm355evm ARM926EJS - davinci_dm355leopard ARM926EJS - davinci_dm365evm ARM926EJS - davinci_dm6467evm ARM926EJS - Prakash Kumar <prakash@embedx.com> cerf250 xscale +Vipin Kumar <vipin.kumar@st.com> + + spear300 ARM926EJS (spear300 Soc) + spear310 ARM926EJS (spear310 Soc) + spear320 ARM926EJS (spear320 Soc) + spear600 ARM926EJS (spear600 Soc) + Sergey Lapin <slapin@ossfans.org> afeb9260 ARM926EJS (AT91SAM9260 SoC) @@ -673,6 +678,13 @@ Kyungmin Park <kyungmin.park@samsung.com> apollon ARM1136EJS +Sandeep Paulraj <s-paulraj@ti.com> + + davinci_dm355evm ARM926EJS + davinci_dm355leopard ARM926EJS + davinci_dm365evm ARM926EJS + davinci_dm6467evm ARM926EJS + Peter Pearse <peter.pearse@arm.com> integratorcp All current ARM supplied & supported core modules -see http://www.arm.com/products/DevTools/Hardware_Platforms.html @@ -773,10 +785,6 @@ Alex Züpke <azu@sysgo.de> lart SA1100 dnp1110 SA1110 -Minkyu Kang <mk7.kang@samsung.com> - - SMDKC100 ARM CORTEX-A8 (S5PC100 SoC) - ------------------------------------------------------------------------- Unknown / orphaned boards: @@ -70,6 +70,7 @@ LIST_5xxx=" \ motionpro \ munices \ MVBC_P \ + MVSMR \ o2dnt \ pcm030 \ pf5200 \ @@ -664,6 +664,11 @@ MVBC_P_config: unconfig { echo "#define CONFIG_MVBC_P" >>$(obj)include/config.h; } @$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p matrix_vision +MVSMR_config: unconfig + @mkdir -p $(obj)include + @mkdir -p $(obj)board/matrix_vision/mvsmr + @$(MKCONFIG) $(@:_config=) ppc mpc5xxx mvsmr matrix_vision + o2dnt_config: unconfig @$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt @@ -1133,6 +1133,12 @@ The following options need to be configured: images, gzipped BMP images can be displayed via the splashscreen support or the bmp command. +- Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8 + + If this option is set, 8-bit RLE compressed BMP images + can be displayed via the splashscreen support or the + bmp command. + - Compression support: CONFIG_BZIP2 diff --git a/board/altera/common/AMDLV065D.c b/board/altera/common/AMDLV065D.c index 0fcf354..7a1b4d3 100644 --- a/board/altera/common/AMDLV065D.c +++ b/board/altera/common/AMDLV065D.c @@ -122,12 +122,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ addr2 = (unsigned char *) info->start[sect]; - writeb (addr, 0xaa); - writeb (addr, 0x55); - writeb (addr, 0x80); - writeb (addr, 0xaa); - writeb (addr, 0x55); - writeb (addr2, 0x30); + writeb (0xaa, addr); + writeb (0x55, addr); + writeb (0x80, addr); + writeb (0xaa, addr); + writeb (0x55, addr); + writeb (0x30, addr2); /* Now just wait for 0xff & provide some user * feedback while we wait. */ @@ -169,10 +169,10 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) return (2); } - writeb (cmd, 0xaa); - writeb (cmd, 0x55); - writeb (cmd, 0xa0); - writeb (dst, b); + writeb (0xaa, cmd); + writeb (0x55, cmd); + writeb (0xa0, cmd); + writeb (b, dst); /* Verify write */ start = get_timer (0); diff --git a/board/altera/common/epled.c b/board/altera/common/epled.c index e5e7705..d019735 100644 --- a/board/altera/common/epled.c +++ b/board/altera/common/epled.c @@ -39,7 +39,7 @@ void __led_init (led_id_t mask, int state) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_set (led_id_t mask, int state) @@ -50,7 +50,7 @@ void __led_set (led_id_t mask, int state) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_toggle (led_id_t mask) @@ -58,5 +58,5 @@ void __led_toggle (led_id_t mask) nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; val ^= mask; - writel (&pio->data, val); + writel (val, &pio->data); } diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 518944e..9bb56b5 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -132,9 +132,7 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_SMC91111 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); #endif -#ifdef CONFIG_PCI rc += pci_eth_init(bis); -#endif return rc; } #endif diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 02a824d..620eb16 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -33,6 +33,7 @@ COBJS-${CONFIG_FSL_CADMUS} += cadmus.o COBJS-${CONFIG_FSL_VIA} += cds_via.o COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o COBJS-${CONFIG_FSL_PIXIS} += pixis.o +COBJS-${CONFIG_FSL_NGPIXIS} += ngpixis.o COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c new file mode 100644 index 0000000..bb6794e --- /dev/null +++ b/board/freescale/common/ngpixis.c @@ -0,0 +1,136 @@ +/** + * Copyright 2010 Freescale Semiconductor + * Author: Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + * + * A "switch" is black rectangular block on the motherboard. It contains + * eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that + * shadow the actual physical switches. There is also another set of + * registers (ENx) that tell the ngPIXIS which bits of SWx should actually be + * used to override the values of the bits in the physical switches. + * + * The following macros need to be defined: + * + * PIXIS_BASE - The virtual address of the base of the PIXIS register map + * + * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value + * is used in the PIXIS_SW() macro to determine which offset in + * the PIXIS register map corresponds to the physical switch that controls + * the boot bank. + * + * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use. + * + * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK. + * + * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to + * boot from the alternate bank. + */ + +#include <common.h> +#include <command.h> +#include <watchdog.h> +#include <asm/cache.h> +#include <asm/io.h> + +#include "ngpixis.h" + +/* + * Reset the board. This ignores the ENx registers. + */ +void pixis_reset(void) +{ + out_8(&pixis->rst, 0); + + while (1); +} + +/* + * Reset the board. Like pixis_reset(), but it honors the ENx registers. + */ +void pixis_bank_reset(void) +{ + out_8(&pixis->vctl, 0); + out_8(&pixis->vctl, 1); + + while (1); +} + +/** + * Set the boot bank to the power-on default bank + */ +void clear_altbank(void) +{ + /* Tell the ngPIXIS to use this the bits in the physical switch for the + * boot bank value, instead of the SWx register. We need to be careful + * only to set the bits in SWx that correspond to the boot bank. + */ + clrbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK); +} + +/** + * Set the boot bank to the alternate bank + */ +void set_altbank(void) +{ + /* Program the alternate bank number into the SWx register. + */ + clrsetbits_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK, + PIXIS_LBMAP_ALTBANK); + + /* Tell the ngPIXIS to use this the bits in the SWx register for the + * boot bank value, instead of the physical switch. We need to be + * careful only to set the bits in SWx that correspond to the boot bank. + */ + setbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK); +} + + +int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int i; + char *p_altbank = NULL; + char *unknown_param = NULL; + + /* No args is a simple reset request. + */ + if (argc <= 1) + pixis_reset(); + + for (i = 1; i < argc; i++) { + if (strcmp(argv[i], "altbank") == 0) { + p_altbank = argv[i]; + continue; + } + + unknown_param = argv[i]; + } + + if (unknown_param) { + printf("Invalid option: %s\n", unknown_param); + return 1; + } + + if (p_altbank) + set_altbank(); + else + clear_altbank(); + + pixis_bank_reset(); + + /* Shouldn't be reached. */ + return 0; +} + +U_BOOT_CMD( + pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd, + "Reset the board using the FPGA sequencer", + "- hard reset to default bank\n" + "pixis_reset altbank - reset to alternate bank\n" + ); diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h new file mode 100644 index 0000000..284d044 --- /dev/null +++ b/board/freescale/common/ngpixis.h @@ -0,0 +1,57 @@ +/** + * Copyright 2010 Freescale Semiconductor + * Author: Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* ngPIXIS register set. Hopefully, this won't change too much over time. + * Feel free to add board-specific #ifdefs where necessary. + */ +typedef struct ngpixis { + u8 id; + u8 arch; + u8 scver; + u8 csr; + u8 rst; + u8 res1; + u8 aux; + u8 spd; + u8 brdcfg0; + u8 dma; + u8 addr; + u8 res2[2]; + u8 data; + u8 led; + u8 res3; + u8 vctl; + u8 vstat; + u8 vcfgen0; + u8 res4; + u8 ocmcsr; + u8 ocmmsg; + u8 gmdbg; + u8 res5[2]; + u8 sclk[3]; + u8 dclk[3]; + u8 watch; + struct { + u8 sw; + u8 en; + } s[8]; +} ngpixis_t __attribute__ ((aligned(1))); + +/* Pointer to the PIXIS register set */ +#define pixis ((ngpixis_t *)PIXIS_BASE) + +/* The PIXIS SW register that corresponds to board switch X, where x >= 1 */ +#define PIXIS_SW(x) (pixis->s[(x) - 1].sw) + +/* The PIXIS EN register that corresponds to board switch X, where x >= 1 */ +#define PIXIS_EN(x) (pixis->s[(x) - 1].en) diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index 7210512..119eaf9 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -1,5 +1,5 @@ /* - * Copyright 2006 Freescale Semiconductor + * Copyright 2006,2010 Freescale Semiconductor * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -24,33 +24,26 @@ #include <common.h> #include <command.h> -#include <watchdog.h> -#include <asm/cache.h> #include <asm/io.h> -#include "pixis.h" - - -static ulong strfractoint(uchar *strptr); - +#define pixis_base (u8 *)PIXIS_BASE /* * Simple board reset. */ void pixis_reset(void) { - u8 *pixis_base = (u8 *)PIXIS_BASE; out_8(pixis_base + PIXIS_RST, 0); -} + while (1); +} /* * Per table 27, page 58 of MPC8641HPCN spec. */ -int set_px_sysclk(ulong sysclk) +static int set_px_sysclk(unsigned long sysclk) { u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux; - u8 *pixis_base = (u8 *)PIXIS_BASE; switch (sysclk) { case 33: @@ -117,13 +110,13 @@ int set_px_sysclk(ulong sysclk) return 1; } - -int set_px_mpxpll(ulong mpxpll) +/* Set the CFG_SYSPLL bits + * + * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if + * read_from_px_regs() is called. + */ +static int set_px_mpxpll(unsigned long mpxpll) { - u8 tmp; - u8 val; - u8 *pixis_base = (u8 *)PIXIS_BASE; - switch (mpxpll) { case 2: case 4: @@ -133,28 +126,19 @@ int set_px_mpxpll(ulong mpxpll) case 12: case 14: case 16: - val = (u8) mpxpll; - break; - default: - printf("Unsupported MPXPLL ratio.\n"); - return 0; + clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll); + return 1; } - tmp = in_8(pixis_base + PIXIS_VSPEED1); - tmp = (tmp & 0xF0) | (val & 0x0F); - out_8(pixis_base + PIXIS_VSPEED1, tmp); - - return 1; + printf("Unsupported MPXPLL ratio.\n"); + return 0; } - -int set_px_corepll(ulong corepll) +static int set_px_corepll(unsigned long corepll) { - u8 tmp; u8 val; - u8 *pixis_base = (u8 *)PIXIS_BASE; - switch ((int)corepll) { + switch (corepll) { case 20: val = 0x08; break; @@ -178,113 +162,132 @@ int set_px_corepll(ulong corepll) return 0; } - tmp = in_8(pixis_base + PIXIS_VSPEED0); - tmp = (tmp & 0xE0) | (val & 0x1F); - out_8(pixis_base + PIXIS_VSPEED0, tmp); - + clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val); return 1; } +#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE +#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C +#endif -void read_from_px_regs(int set) +/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values + * + * The PIXIS can be programmed to look at either the on-board dip switches + * or various other PIXIS registers to determine the values for COREPLL, + * MPXPLL, and SYSCLK. + * + * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0 + * register that tells the pixis to use the various PIXIS register. + */ +static void read_from_px_regs(int set) { - u8 *pixis_base = (u8 *)PIXIS_BASE; - u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */ u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0); if (set) - tmp = tmp | mask; + tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE; else - tmp = tmp & ~mask; + tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE; + out_8(pixis_base + PIXIS_VCFGEN0, tmp); } +/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1 + * register that tells the pixis to use the PX_VBOOT[LBMAP] register. + */ +#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE +#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04 +#endif -void read_from_px_regs_altbank(int set) +/* Configure the source of the boot location + * + * The PIXIS can be programmed to look at either the on-board dip switches + * or the PX_VBOOT[LBMAP] register to determine where we should boot. + * + * If we want to boot from the alternate boot bank, we need to tell the PIXIS + * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead. + */ +static void read_from_px_regs_altbank(int set) { - u8 *pixis_base = (u8 *)PIXIS_BASE; - u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */ u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1); if (set) - tmp = tmp | mask; + tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE; else - tmp = tmp & ~mask; + tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE; + out_8(pixis_base + PIXIS_VCFGEN1, tmp); } +/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that + * tells the PIXIS what the alternate flash bank is. + * + * Note that it's not really a mask. It contains the actual LBMAP bits that + * must be set to select the alternate bank. This code assumes that the + * primary bank has these bits set to 0, and the alternate bank has these + * bits set to 1. + */ #ifndef CONFIG_SYS_PIXIS_VBOOT_MASK #define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40) #endif -void clear_altbank(void) +/* Tell the PIXIS to boot from the default flash bank + * + * Program the default flash bank into the VBOOT register. This register is + * used only if PX_VCFGEN1[FLASH]=1. + */ +static void clear_altbank(void) { - u8 tmp; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - tmp = in_8(pixis_base + PIXIS_VBOOT); - tmp &= ~CONFIG_SYS_PIXIS_VBOOT_MASK; - - out_8(pixis_base + PIXIS_VBOOT, tmp); + clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK); } - -void set_altbank(void) +/* Tell the PIXIS to boot from the alternate flash bank + * + * Program the alternate flash bank into the VBOOT register. This register is + * used only if PX_VCFGEN1[FLASH]=1. + */ +static void set_altbank(void) { - u8 tmp; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - tmp = in_8(pixis_base + PIXIS_VBOOT); - tmp |= CONFIG_SYS_PIXIS_VBOOT_MASK; - - out_8(pixis_base + PIXIS_VBOOT, tmp); + setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK); } - -void set_px_go(void) +/* Reset the board with watchdog disabled. + * + * This respects the altbank setting. + */ +static void set_px_go(void) { - u8 tmp; - u8 *pixis_base = (u8 *)PIXIS_BASE; + /* Disable the VELA sequencer and watchdog */ + clrbits_8(pixis_base + PIXIS_VCTL, 9); - tmp = in_8(pixis_base + PIXIS_VCTL); - tmp = tmp & 0x1E; /* clear GO bit */ - out_8(pixis_base + PIXIS_VCTL, tmp); + /* Reboot by starting the VELA sequencer */ + setbits_8(pixis_base + PIXIS_VCTL, 0x1); - tmp = in_8(pixis_base + PIXIS_VCTL); - tmp = tmp | 0x01; /* set GO bit - start reset sequencer */ - out_8(pixis_base + PIXIS_VCTL, tmp); + while (1); } - -void set_px_go_with_watchdog(void) +/* Reset the board with watchdog enabled. + * + * This respects the altbank setting. + */ +static void set_px_go_with_watchdog(void) { - u8 tmp; - u8 *pixis_base = (u8 *)PIXIS_BASE; + /* Disable the VELA sequencer */ + clrbits_8(pixis_base + PIXIS_VCTL, 1); - tmp = in_8(pixis_base + PIXIS_VCTL); - tmp = tmp & 0x1E; - out_8(pixis_base + PIXIS_VCTL, tmp); + /* Enable the watchdog and reboot by starting the VELA sequencer */ + setbits_8(pixis_base + PIXIS_VCTL, 0x9); - tmp = in_8(pixis_base + PIXIS_VCTL); - tmp = tmp | 0x09; - out_8(pixis_base + PIXIS_VCTL, tmp); + while (1); } - -int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, - int flag, int argc, char *argv[]) +/* Disable the watchdog + * + */ +static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char *argv[]) { - u8 tmp; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - tmp = in_8(pixis_base + PIXIS_VCTL); - tmp = tmp & 0x1E; - out_8(pixis_base + PIXIS_VCTL, tmp); - - /* setting VCTL[WDEN] to 0 to disable watch dog */ - tmp = in_8(pixis_base + PIXIS_VCTL); - tmp &= ~0x08; - out_8(pixis_base + PIXIS_VCTL, tmp); + /* Disable the VELA sequencer and the watchdog */ + clrbits_8(pixis_base + PIXIS_VCTL, 9); return 0; } @@ -296,16 +299,17 @@ U_BOOT_CMD( ); #ifdef CONFIG_PIXIS_SGMII_CMD -int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) + +/* Enable or disable SGMII mode for a TSEC + */ +static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int which_tsec = -1; - u8 *pixis_base = (u8 *)PIXIS_BASE; - uchar mask; - uchar switch_mask; + unsigned char mask; + unsigned char switch_mask; - if (argc > 2) - if (strcmp(argv[1], "all") != 0) - which_tsec = simple_strtoul(argv[1], NULL, 0); + if ((argc > 2) && (strcmp(argv[1], "all") != 0)) + which_tsec = simple_strtoul(argv[1], NULL, 0); switch (which_tsec) { #ifdef CONFIG_TSEC1 @@ -363,6 +367,7 @@ U_BOOT_CMD( " off - disables SGMII\n" " switch - use switch settings" ); + #endif /* @@ -371,14 +376,13 @@ U_BOOT_CMD( * FPGA register values. * input: strptr i.e. argv[2] */ - -static ulong strfractoint(uchar *strptr) +static unsigned long strfractoint(char *strptr) { - int i, j, retval; + int i, j; int mulconst; - int intarr_len = 0, decarr_len = 0, no_dec = 0; - ulong intval = 0, decval = 0; - uchar intarr[3], decarr[3]; + int intarr_len, no_dec = 0; + unsigned long intval = 0, decval = 0; + char intarr[3], decarr[3]; /* Assign the integer part to intarr[] * If there is no decimal point i.e. @@ -412,26 +416,21 @@ static ulong strfractoint(uchar *strptr) j++; } - decarr_len = j; decarr[j] = '\0'; mulconst = 1; - for (i = 0; i < decarr_len; i++) + for (i = 0; i < j; i++) mulconst *= 10; - decval = simple_strtoul((char *)decarr, NULL, 10); + decval = simple_strtoul(decarr, NULL, 10); } - intval = simple_strtoul((char *)intarr, NULL, 10); + intval = simple_strtoul(intarr, NULL, 10); intval = intval * mulconst; - retval = intval + decval; - - return retval; + return intval + decval; } - -int -pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { unsigned int i; char *p_cf = NULL; @@ -440,7 +439,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *p_cf_mpxpll = NULL; char *p_altbank = NULL; char *p_wd = NULL; - unsigned int unknown_param = 0; + int unknown_param = 0; /* * No args is a simple reset request. @@ -493,9 +492,9 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ read_from_px_regs(0); - if (p_altbank) { + if (p_altbank) read_from_px_regs_altbank(0); - } + clear_altbank(); /* @@ -507,7 +506,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) unsigned long mpxpll; sysclk = simple_strtoul(p_cf_sysclk, NULL, 10); - corepll = strfractoint((uchar *) p_cf_corepll); + corepll = strfractoint(p_cf_corepll); mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10); if (!(set_px_sysclk(sysclk) @@ -536,11 +535,10 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * Reset with watchdog specified. */ - if (p_wd) { + if (p_wd) set_px_go_with_watchdog(); - } else { + else set_px_go(); - } /* * Shouldn't be reached. diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 81a56b5..253ed18 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -39,7 +39,6 @@ #include <netdev.h> #include <sata.h> -#include "../common/pixis.h" #include "../common/sgmii_riser.h" phys_size_t fixed_sdram(void); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index b35e02f..0be2d89 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -35,7 +35,6 @@ #include <tsec.h> #include <netdev.h> -#include "../common/pixis.h" #include "../common/sgmii_riser.h" int checkboard (void) diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 74085c3..6029a51 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -36,7 +36,6 @@ #include <tsec.h> #include <netdev.h> -#include "../common/pixis.h" #include "../common/sgmii_riser.h" long int fixed_sdram(void); diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index ab5f800..2ef7b23 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -34,8 +34,6 @@ #include <spd_sdram.h> #include <netdev.h> -#include "../common/pixis.h" - void sdram_init(void); phys_size_t fixed_sdram(void); void mpc8610hpcd_diu_init(void); diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c index 4186a2e..94fb1eb 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c @@ -29,7 +29,6 @@ #ifdef CONFIG_FSL_DIU_FB -#include "../common/pixis.h" #include "../common/fsl_diu_fb.h" #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 443c9fd..b352c33 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -31,8 +31,6 @@ #include <fdt_support.h> #include <netdev.h> -#include "../common/pixis.h" - phys_size_t fixed_sdram(void); int board_early_init_f(void) diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index f6eae55..f0ff209 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -38,7 +38,7 @@ #include <asm/mp.h> #include <netdev.h> -#include "../common/pixis.h" +#include "../common/ngpixis.h" #include "../common/sgmii_riser.h" DECLARE_GLOBAL_DATA_PTR; @@ -47,30 +47,24 @@ phys_size_t fixed_sdram(void); int checkboard(void) { - u8 sw7; - u8 *pixis_base = (u8 *)PIXIS_BASE; + u8 sw; puts("Board: P2020DS "); #ifdef CONFIG_PHYS_64BIT puts("(36-bit addrmap) "); #endif - printf("Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), - in_8(pixis_base + PIXIS_PVER)); + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); - sw7 = in_8(pixis_base + PIXIS_SW(7)); - switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) { - case 0: - case 1: - printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4)); - break; - case 2: - case 3: - puts ("Promjet\n"); - break; - } + sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); + sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + /* The lower two bits are the actual vbank number */ + printf("vBank: %d\n", sw & 3); + else + puts("Promjet\n"); return 0; } @@ -371,30 +365,22 @@ unsigned long get_board_ddr_clk(ulong dummy) return gd->mem_clk; } -unsigned long -calculate_board_sys_clk(ulong dummy) +unsigned long calculate_board_sys_clk(ulong dummy) { ulong val; - u8 *pixis_base = (u8 *)PIXIS_BASE; - val = ics307_clk_freq( - in_8(pixis_base + PIXIS_VSYSCLK0), - in_8(pixis_base + PIXIS_VSYSCLK1), - in_8(pixis_base + PIXIS_VSYSCLK2)); + val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]), + in_8(&pixis->sclk[2])); debug("sysclk val = %lu\n", val); return val; } -unsigned long -calculate_board_ddr_clk(ulong dummy) +unsigned long calculate_board_ddr_clk(ulong dummy) { ulong val; - u8 *pixis_base = (u8 *)PIXIS_BASE; - val = ics307_clk_freq( - in_8(pixis_base + PIXIS_VDDRCLK0), - in_8(pixis_base + PIXIS_VDDRCLK1), - in_8(pixis_base + PIXIS_VDDRCLK2)); + val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]), + in_8(&pixis->dclk[2])); debug("ddrclk val = %lu\n", val); return val; } @@ -403,9 +389,8 @@ unsigned long get_board_sys_clk(ulong dummy) { u8 i; ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - i = in_8(pixis_base + PIXIS_SPD); + i = in_8(&pixis->spd); i &= 0x07; switch (i) { @@ -442,9 +427,8 @@ unsigned long get_board_ddr_clk(ulong dummy) { u8 i; ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - i = in_8(pixis_base + PIXIS_SPD); + i = in_8(&pixis->spd); i &= 0x38; i >>= 3; diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile new file mode 100644 index 0000000..b179e6d --- /dev/null +++ b/board/matrix_vision/mvsmr/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2004-2008 +# Matrix-Vision GmbH, info@matrix-vision.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o fpga.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + @mkimage -T script -C none -n mvSMR_Script -d bootscript bootscript.img + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/matrix_vision/mvsmr/bootscript b/board/matrix_vision/mvsmr/bootscript new file mode 100644 index 0000000..02c802c --- /dev/null +++ b/board/matrix_vision/mvsmr/bootscript @@ -0,0 +1,42 @@ +echo +echo "==== running autoscript ====" +echo +setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}' +setenv ramkernel 'setenv kernel_boot ${loadaddr}' +setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}' +setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}' +setenv bootfromflash run flashkernel cpird addcons boot24 +setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel' +if test ${console} = yes; +then +setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8' +else +setenv addcons 'setenv bootargs ${bootargs} console=tty0' +fi +setenv set_static_ip 'setenv ipaddr ${static_ipaddr}' +setenv set_static_nm 'setenv netmask ${static_netmask}' +setenv set_static_gw 'setenv gatewayip ${static_gateway}' +setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}' +if test ${servicemode} != yes; +then + echo "=== forced flash mode ===" + run set_static_ip set_static_nm set_static_gw set_ip bootfromflash +fi +if test ${autoscript_boot} != no; +then + if test ${netboot} = yes; + then + bootp + if test $? = 0; + then + echo "=== bootp succeeded -> netboot ===" + run set_ip bootfromnet addcons boot24 + else + echo "=== netboot failed ===" + fi + fi + echo "=== bootfromflash ===" + run set_static_ip set_static_nm set_static_gw set_ip bootfromflash +else + echo "=== boot stopped with autoscript_boot no ===" +fi diff --git a/board/matrix_vision/mvsmr/config.mk b/board/matrix_vision/mvsmr/config.mk new file mode 100644 index 0000000..b1da812 --- /dev/null +++ b/board/matrix_vision/mvsmr/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0xFF800000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board +LDSCRIPT := $(SRCTREE)/board/matrix_vision/mvsmr/u-boot.lds diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c new file mode 100644 index 0000000..6320a69 --- /dev/null +++ b/board/matrix_vision/mvsmr/fpga.c @@ -0,0 +1,129 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * (C) Copyright 2010 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <spartan3.h> +#include <command.h> +#include <asm/io.h> +#include "fpga.h" +#include "mvsmr.h" + +Xilinx_Spartan3_Slave_Serial_fns fpga_fns = { + fpga_pre_config_fn, + fpga_pgm_fn, + fpga_clk_fn, + fpga_init_fn, + fpga_done_fn, + fpga_wr_fn, + 0 +}; + +Xilinx_desc spartan3 = { + Xilinx_Spartan2, + slave_serial, + XILINX_XC3S200_SIZE, + (void *) &fpga_fns, + 0, +}; + +DECLARE_GLOBAL_DATA_PTR; + +int mvsmr_init_fpga(void) +{ + fpga_init(); + fpga_add(fpga_xilinx, &spartan3); + + return 1; +} + +int fpga_init_fn(int cookie) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + + if (in_be32(&gpio->simple_ival) & FPGA_CONFIG) + return 0; + + return 1; +} + +int fpga_done_fn(int cookie) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + int result = 0; + + udelay(10); + if (in_be32(&gpio->simple_ival) & FPGA_DONE) + result = 1; + + return result; +} + +int fpga_pgm_fn(int assert, int flush, int cookie) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + + if (!assert) + setbits_8(&gpio->sint_dvo, FPGA_STATUS); + else + clrbits_8(&gpio->sint_dvo, FPGA_STATUS); + + return assert; +} + +int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + + if (assert_clk) + setbits_be32(&gpio->simple_dvo, FPGA_CCLK); + else + clrbits_be32(&gpio->simple_dvo, FPGA_CCLK); + + return assert_clk; +} + +int fpga_wr_fn(int assert_write, int flush, int cookie) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + + if (assert_write) + setbits_be32(&gpio->simple_dvo, FPGA_DIN); + else + clrbits_be32(&gpio->simple_dvo, FPGA_DIN); + + return assert_write; +} + +int fpga_pre_config_fn(int cookie) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + + setbits_8(&gpio->sint_dvo, FPGA_STATUS); + + return 0; +} diff --git a/board/freescale/common/pixis.h b/board/matrix_vision/mvsmr/fpga.h index ff62a62..ee690e6 100644 --- a/board/freescale/common/pixis.h +++ b/board/matrix_vision/mvsmr/fpga.h @@ -1,5 +1,6 @@ /* - * Copyright 2006 Freescale Semiconductor + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de * * See file CREDITS for list of people who contributed to this * project. @@ -18,14 +19,14 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * */ -extern void pixis_reset(void); -extern int set_px_sysclk(ulong sysclk); -extern int set_px_mpxpll(ulong mpxpll); -extern int set_px_corepll(ulong corepll); -extern void read_from_px_regs(int set); -extern void read_from_px_regs_altbank(int set); -extern void set_altbank(void); -extern void set_px_go(void); -extern void set_px_go_with_watchdog(void); +extern int mvsmr_init_fpga(void); + +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); +extern int fpga_init_fn(int cookie); +extern int fpga_clk_fn(int assert_clk, int flush, int cookie); +extern int fpga_wr_fn(int assert_write, int flush, int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_pre_config_fn(int cookie); diff --git a/board/matrix_vision/mvsmr/mvsmr.c b/board/matrix_vision/mvsmr/mvsmr.c new file mode 100644 index 0000000..69655c4 --- /dev/null +++ b/board/matrix_vision/mvsmr/mvsmr.c @@ -0,0 +1,264 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2005-2010 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <malloc.h> +#include <pci.h> +#include <i2c.h> +#include <fpga.h> +#include <environment.h> +#include <netdev.h> +#include <asm/io.h> +#include "fpga.h" +#include "mvsmr.h" +#include "../common/mv_common.h" + +#define SDRAM_DDR 1 +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x715f0f00 +#define SDRAM_CONFIG1 0xd3722930 +#define SDRAM_CONFIG2 0x46770000 + +DECLARE_GLOBAL_DATA_PTR; + +static void sdram_start(int hi_addr) +{ + long hi_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | + hi_bit); + + /* precharge all banks */ + out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | + hi_bit); + + /* set mode register: extended mode */ + out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE); + + /* set mode register: reset DLL */ + out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000); + + /* precharge all banks */ + out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | + hi_bit); + + /* auto refresh */ + out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | + hi_bit); + + /* set mode register */ + out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); + + /* normal operation */ + out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit); +} + +phys_addr_t initdram(int board_type) +{ + ulong dramsize = 0; + ulong test1, + test2; + + /* setup SDRAM chip selects */ + out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); + + /* setup config registers */ + out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); + out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else + dramsize = test2; + + if (dramsize < (1 << 20)) + dramsize = 0; + + if (dramsize > 0) + out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 + + __builtin_ffs(dramsize >> 20) - 1); + else + out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0); + + return dramsize; +} + +void mvsmr_init_gpio(void) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_wu_gpio *wu_gpio = + (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; + struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + printf("Ports : 0x%08x\n", gpio->port_config); + printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG)); + + out_be32(&gpio->simple_ddr, SIMPLE_DDR); + out_be32(&gpio->simple_dvo, SIMPLE_DVO); + out_be32(&gpio->simple_ode, SIMPLE_ODE); + out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN); + + out_8(&gpio->sint_ode, SINT_ODE); + out_8(&gpio->sint_ddr, SINT_DDR); + out_8(&gpio->sint_dvo, SINT_DVO); + out_8(&gpio->sint_inten, SINT_INTEN); + out_be16(&gpio->sint_itype, SINT_ITYPE); + out_8(&gpio->sint_gpioe, SINT_GPIOEN); + + out_8(&wu_gpio->ode, WKUP_ODE); + out_8(&wu_gpio->ddr, WKUP_DIR); + out_8(&wu_gpio->dvo, WKUP_DO); + out_8(&wu_gpio->enable, WKUP_EN); + + out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */ + out_be32(&timers->gpt1.emsr, 0x00000234); + out_be32(&timers->gpt2.emsr, 0x00000234); + out_be32(&timers->gpt3.emsr, 0x00000234); + out_be32(&timers->gpt4.emsr, 0x00000234); + out_be32(&timers->gpt5.emsr, 0x00000234); + out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */ + out_be32(&timers->gpt7.emsr, 0x00000024); +} + +int misc_init_r(void) +{ + char *s = getenv("reset_env"); + + if (s) { + printf(" === FACTORY RESET ===\n"); + mv_reset_environment(); + saveenv(); + } + + return -1; +} + +void mvsmr_get_dbg_present(void) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1; + + if (in_be32(&gpio->simple_ival) & COP_PRESENT) { + setenv("dbg_present", "no\0"); + setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0"); + } else { + setenv("dbg_present", "yes\0"); + setenv("bootstopkey", "s\0"); + setbits_8(&psc->command, PSC_RX_ENABLE); + } +} + +void mvsmr_get_service_mode(void) +{ + struct mpc5xxx_wu_gpio *wu_gpio = + (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; + + if (in_8(&wu_gpio->ival) & SERVICE_MODE) + setenv("servicemode", "no\0"); + else + setenv("servicemode", "yes\0"); +} + +int mvsmr_get_mac(void) +{ + unsigned char mac[6]; + struct mpc5xxx_wu_gpio *wu_gpio = + (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; + + if (in_8(&wu_gpio->ival) & LAN_PRSNT) { + setenv("lan_present", "no\0"); + return -1; + } else + setenv("lan_present", "yes\0"); + + i2c_read(0x50, 0, 1, mac, 6); + + eth_setenv_enetaddr("ethaddr", mac); + + return 0; +} + +int checkboard(void) +{ + mvsmr_init_gpio(); + printf("Board: Matrix Vision mvSMR\n"); + + return 0; +} + +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ + clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1); +} + +void flash_afterinit(ulong size) +{ + out_be32((u32 *)MPC5XXX_BOOTCS_START, + START_REG(CONFIG_SYS_BOOTCS_START | size)); + out_be32((u32 *)MPC5XXX_CS0_START, + START_REG(CONFIG_SYS_BOOTCS_START | size)); + out_be32((u32 *)MPC5XXX_BOOTCS_STOP, + STOP_REG(CONFIG_SYS_BOOTCS_START | size, size)); + out_be32((u32 *)MPC5XXX_CS0_STOP, + STOP_REG(CONFIG_SYS_BOOTCS_START | size, size)); +} + +struct pci_controller hose; + +void pci_init_board(void) +{ + mvsmr_get_dbg_present(); + mvsmr_get_service_mode(); + mvsmr_init_fpga(); + mv_load_fpga(); + pci_mpc5xxx_init(&hose); +} + +int board_eth_init(bd_t *bis) +{ + if (!mvsmr_get_mac()) + return cpu_eth_init(bis); + + return pci_eth_init(bis); +} diff --git a/board/matrix_vision/mvsmr/mvsmr.h b/board/matrix_vision/mvsmr/mvsmr.h new file mode 100644 index 0000000..b8320f1 --- /dev/null +++ b/board/matrix_vision/mvsmr/mvsmr.h @@ -0,0 +1,43 @@ +#include <pci.h> + +extern void pci_mpc5xxx_init(struct pci_controller *); + +#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0 +#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1 +#define FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2 +#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3 +#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4 +#define S_FPGA_DIN MPC5XXX_GPIO_SINT_PSC3_5 +#define S_FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_6 +#define S_FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_7 +#define S_FPGA_CONFIG MPC5XXX_GPIO_SINT_PSC3_8 +#define S_FPGA_STATUS MPC5XXX_GPIO_WKUP_PSC3_9 + +#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0 +#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1 +#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2 +#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3 +#define SERVICE_MODE MPC5XXX_GPIO_WKUP_6 +#define FLASH_RBY MPC5XXX_GPIO_WKUP_7 +#define UART_EN1 MPC5XXX_GPIO_WKUP_PSC1_4 +#define LAN_PRSNT MPC5XXX_GPIO_WKUP_PSC2_4 + +#define SIMPLE_DDR (FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\ + S_FPGA_CCLK) +#define SIMPLE_DVO (FPGA_CONFIG) +#define SIMPLE_ODE (FPGA_CONFIG) +#define SIMPLE_GPIOEN (FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\ + S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT) + +#define SINT_ODE 0x1 +#define SINT_DDR 0x3 +#define SINT_DVO 0x1 +#define SINT_INTEN 0 +#define SINT_ITYPE 0 +#define SINT_GPIOEN (FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG) + +#define WKUP_ODE (MAN_RST | S_FPGA_STATUS) +#define WKUP_DIR (MAN_RST | WD_TS | S_FPGA_STATUS) +#define WKUP_DO (MAN_RST | WD_TS | S_FPGA_STATUS) +#define WKUP_EN (MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\ + FLASH_RBY | UART_EN1 | LAN_PRSNT) diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds new file mode 100644 index 0000000..cfbb6ef --- /dev/null +++ b/board/matrix_vision/mvsmr/u-boot.lds @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright 2010 + * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the first two sectors (=8KB) of our S29GL flash chip */ + cpu/mpc5xxx/start.o (.text) + cpu/mpc5xxx/traps.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + /* This is only needed to force failure if size of above code will ever */ + /* increase and grow into reserved space. */ + . = ALIGN(0x2000); /* location counter has to be 0x4000 now */ + . += 0x4000; /* ->0x8000, i.e. move to env_offset */ + + . = env_offset; /* ld error as soon as above ALIGN misplaces lc */ + common/env_embedded.o (.ppcenv) + + *(.text) + *(.got1) + . = ALIGN(16); + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c index 0fcf354..72b0a9f 100644 --- a/board/psyent/common/AMDLV065D.c +++ b/board/psyent/common/AMDLV065D.c @@ -122,12 +122,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ addr2 = (unsigned char *) info->start[sect]; - writeb (addr, 0xaa); - writeb (addr, 0x55); - writeb (addr, 0x80); - writeb (addr, 0xaa); - writeb (addr, 0x55); - writeb (addr2, 0x30); + writeb (0xaa, addr); + writeb (0x55, addr); + writeb (0x80, addr); + writeb (0xaa, addr); + writeb (0x55, addr); + writeb (0x30, addr2); /* Now just wait for 0xff & provide some user * feedback while we wait. */ @@ -169,9 +169,9 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) return (2); } - writeb (cmd, 0xaa); - writeb (cmd, 0x55); - writeb (cmd, 0xa0); + writeb (0xaa, cmd); + writeb (0x55, cmd); + writeb (0xa0, cmd); writeb (dst, b); /* Verify write */ diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c index e5e7705..d019735 100644 --- a/board/psyent/pk1c20/led.c +++ b/board/psyent/pk1c20/led.c @@ -39,7 +39,7 @@ void __led_init (led_id_t mask, int state) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_set (led_id_t mask, int state) @@ -50,7 +50,7 @@ void __led_set (led_id_t mask, int state) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_toggle (led_id_t mask) @@ -58,5 +58,5 @@ void __led_toggle (led_id_t mask) nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; val ^= mask; - writel (&pio->data, val); + writel (val, &pio->data); } diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 15a1a27..fb466c6 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -23,10 +23,40 @@ */ #include <common.h> +#include <asm/io.h> +#include <asm/arch/smc.h> +#include <asm/arch/gpio.h> +#include <netdev.h> + DECLARE_GLOBAL_DATA_PTR; +/* + * Miscellaneous platform dependent initialisations + */ +static void smc9115_pre_init(void) +{ + u32 smc_bw_conf, smc_bc_conf; + + struct s5pc100_gpio *const gpio = + (struct s5pc100_gpio *)S5PC100_GPIO_BASE; + + /* gpio configuration GPK0CON */ + gpio_cfg_pin(&gpio->gpio_k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + + /* Ethernet needs bus width of 16 bits */ + smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); + smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe) + | SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4) + | SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0); + + /* Select and configure the SROMC bank */ + s5pc1xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); +} + int board_init(void) { + smc9115_pre_init(); + gd->bd->bi_arch_number = MACH_TYPE_SMDKC100; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; @@ -49,3 +79,12 @@ int checkboard(void) return 0; } #endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c index 74ab24c..583b009 100644 --- a/common/cmd_bmp.c +++ b/common/cmd_bmp.c @@ -90,46 +90,77 @@ bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp) } #endif +static int do_bmp_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; -/* - * Subroutine: do_bmp - * - * Description: Handler for 'bmp' command.. - * - * Inputs: argv[1] contains the subcommand - * - * Return: None - * - */ -int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) + switch (argc) { + case 1: /* use load_addr as default address */ + addr = load_addr; + break; + case 2: /* use argument */ + addr = simple_strtoul(argv[1], NULL, 16); + break; + default: + cmd_usage(cmdtp); + return 1; + } + + return (bmp_info(addr)); +} + +static int do_bmp_display(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { ulong addr; int x = 0, y = 0; switch (argc) { - case 2: /* use load_addr as default address */ + case 1: /* use load_addr as default address */ addr = load_addr; break; - case 3: /* use argument */ - addr = simple_strtoul(argv[2], NULL, 16); + case 2: /* use argument */ + addr = simple_strtoul(argv[1], NULL, 16); break; - case 5: - addr = simple_strtoul(argv[2], NULL, 16); - x = simple_strtoul(argv[3], NULL, 10); - y = simple_strtoul(argv[4], NULL, 10); + case 4: + addr = simple_strtoul(argv[1], NULL, 16); + x = simple_strtoul(argv[2], NULL, 10); + y = simple_strtoul(argv[3], NULL, 10); break; default: cmd_usage(cmdtp); return 1; } - /* Allow for short names - * Adjust length if more sub-commands get added - */ - if (strncmp(argv[1],"info",1) == 0) { - return (bmp_info(addr)); - } else if (strncmp(argv[1],"display",1) == 0) { - return (bmp_display(addr, x, y)); + return (bmp_display(addr, x, y)); +} + +static cmd_tbl_t cmd_bmp_sub[] = { + U_BOOT_CMD_MKENT(info, 3, 0, do_bmp_info, "", ""), + U_BOOT_CMD_MKENT(display, 5, 0, do_bmp_display, "", ""), +}; + +/* + * Subroutine: do_bmp + * + * Description: Handler for 'bmp' command.. + * + * Inputs: argv[1] contains the subcommand + * + * Return: None + * + */ +static int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + cmd_tbl_t *c; + + /* Strip off leading 'bmp' command argument */ + argc--; + argv++; + + c = find_cmd_tbl(argv[0], &cmd_bmp_sub[0], ARRAY_SIZE(cmd_bmp_sub)); + + if (c) { + return c->cmd(cmdtp, flag, argc, argv); } else { cmd_usage(cmdtp); return 1; diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c index 54faac1..2484b40 100644 --- a/common/cmd_ubi.c +++ b/common/cmd_ubi.c @@ -190,7 +190,7 @@ static int ubi_remove_vol(char *volume) { int i, err, reserved_pebs; int found = 0, vol_id = 0; - struct ubi_volume *vol; + struct ubi_volume *vol = NULL; for (i = 0; i < ubi->vtbl_slots; i++) { vol = ubi->volumes[i]; diff --git a/common/cmd_usb.c b/common/cmd_usb.c index 6b5c582..ee3755c 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -387,7 +387,7 @@ int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) dev = simple_strtoul(boot_device, &ep, 16); stor_dev = usb_stor_get_dev(dev); - if (stor_dev->type == DEV_TYPE_UNKNOWN) { + if (stor_dev == NULL || stor_dev->type == DEV_TYPE_UNKNOWN) { printf("\n** Device %d not available\n", dev); return 1; } @@ -595,8 +595,10 @@ int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (strncmp(argv[1], "part", 4) == 0) { int devno, ok = 0; if (argc == 2) { - for (devno = 0; devno < USB_MAX_STOR_DEV; ++devno) { + for (devno = 0; ; ++devno) { stor_dev = usb_stor_get_dev(devno); + if (stor_dev == NULL) + break; if (stor_dev->type != DEV_TYPE_UNKNOWN) { ok++; if (devno) @@ -608,7 +610,8 @@ int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else { devno = simple_strtoul(argv[2], NULL, 16); stor_dev = usb_stor_get_dev(devno); - if (stor_dev->type != DEV_TYPE_UNKNOWN) { + if (stor_dev != NULL && + stor_dev->type != DEV_TYPE_UNKNOWN) { ok++; debug("print_part of %x\n", devno); print_part(stor_dev); @@ -668,12 +671,12 @@ int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (argc == 3) { int dev = (int)simple_strtoul(argv[2], NULL, 10); printf("\nUSB device %d: ", dev); - if (dev >= USB_MAX_STOR_DEV) { + stor_dev = usb_stor_get_dev(dev); + if (stor_dev == NULL) { printf("unknown device\n"); return 1; } printf("\n Device %d: ", dev); - stor_dev = usb_stor_get_dev(dev); dev_print(stor_dev); if (stor_dev->type == DEV_TYPE_UNKNOWN) return 1; diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 205fc40..2276532 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1515,7 +1515,7 @@ void *sbrk(ptrdiff_t increment) ulong new = old + increment; if ((new < mem_malloc_start) || (new > mem_malloc_end)) - return NULL; + return (void *)MORECORE_FAILURE; mem_malloc_brk = new; diff --git a/common/fdt_support.c b/common/fdt_support.c index b7d4fe5..b6f252a 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -976,3 +976,16 @@ void fdt_fixup_mtdparts(void *blob, void *node_info, int node_info_size) } } #endif + +void fdt_del_node_and_alias(void *blob, const char *alias) +{ + int off = fdt_path_offset(blob, alias); + + if (off < 0) + return; + + fdt_del_node(blob, off); + + off = fdt_path_offset(blob, "/aliases"); + fdt_delprop(blob, off, alias); +} diff --git a/common/main.c b/common/main.c index 3949a5b..f7e7c1c 100644 --- a/common/main.c +++ b/common/main.c @@ -730,6 +730,7 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len) while (!tstc()) { /* while no incoming data */ if (retry_time >= 0 && get_ticks() > endtime) return (-2); /* timed out */ + WATCHDOG_RESET(); } #endif @@ -997,6 +998,7 @@ int readline_into_buffer (const char *const prompt, char * buffer) while (!tstc()) { /* while no incoming data */ if (retry_time >= 0 && get_ticks() > endtime) return (-2); /* timed out */ + WATCHDOG_RESET(); } #endif WATCHDOG_RESET(); /* Trigger watchdog, if needed */ @@ -1005,6 +1007,7 @@ int readline_into_buffer (const char *const prompt, char * buffer) while (!tstc()) { extern void show_activity(int arg); show_activity(0); + WATCHDOG_RESET(); } #endif c = getc(); diff --git a/common/usb_storage.c b/common/usb_storage.c index a8642c9..4fc01a2 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -175,7 +175,7 @@ void uhci_show_temp_int_td(void); block_dev_desc_t *usb_stor_get_dev(int index) { - return (index < USB_MAX_STOR_DEV) ? &usb_dev_desc[index] : NULL; + return (index < usb_max_devs) ? &usb_dev_desc[index] : NULL; } @@ -244,7 +244,7 @@ int usb_stor_scan(int mode) * get info and fill it in */ if (usb_stor_get_info(dev, &usb_stor[usb_max_devs], - &usb_dev_desc[usb_max_devs])) + &usb_dev_desc[usb_max_devs]) == 1) usb_max_devs++; } /* if storage device */ @@ -888,7 +888,7 @@ static int usb_inquiry(ccb *srb, struct us_data *ss) USB_STOR_PRINTF("inquiry returns %d\n", i); if (i == 0) break; - } while (retry--); + } while (--retry); if (!retry) { printf("error in inquiry\n"); diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c index 2c0014f..befa0cd 100644 --- a/cpu/arm1176/cpu.c +++ b/cpu/arm1176/cpu.c @@ -33,7 +33,9 @@ #include <common.h> #include <command.h> +#ifdef CONFIG_S3C64XX #include <asm/arch/s3c6400.h> +#endif #include <asm/system.h> static void cache_flush (void); diff --git a/cpu/arm1176/start.S b/cpu/arm1176/start.S index 68a356d..e2b6c9b 100644 --- a/cpu/arm1176/start.S +++ b/cpu/arm1176/start.S @@ -35,7 +35,9 @@ #ifdef CONFIG_ENABLE_MMU #include <asm/proc/domain.h> #endif +#ifdef CONFIG_S3C64XX #include <asm/arch/s3c6400.h> +#endif #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE @@ -190,10 +192,12 @@ mmu_disable: #endif mmu_disable_phys: +#ifdef CONFIG_S3C64XX /* Peri port setup */ ldr r0, =0x70000000 orr r0, r0, #0x13 mcr p15,0,r0,c15,c2,4 @ 256M (0x70000000 - 0x7fffffff) +#endif /* * Go setup Memory and board specific bits prior to relocation. diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c index 31304b7..4a0ce4d 100644 --- a/cpu/arm920t/ep93xx/timer.c +++ b/cpu/arm920t/ep93xx/timer.c @@ -1,8 +1,7 @@ /* * Cirrus Logic EP93xx timer support. * - * Copyright (C) 2009, 2010 - * Matthias Kaehlcke <matthias@kaehlcke.net> + * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net> * * Copyright (C) 2004, 2005 * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com> @@ -42,17 +41,9 @@ static struct ep93xx_timer { unsigned long long ticks; - unsigned long last_update; + unsigned long last_read; } timer; -static inline unsigned long clk_to_systicks(unsigned long long clk_ticks) -{ - unsigned long long sys_ticks = (clk_ticks * CONFIG_SYS_HZ); - do_div(sys_ticks, TIMER_FREQ); - - return (unsigned long)sys_ticks; -} - static inline unsigned long long usecs_to_ticks(unsigned long usecs) { unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ; @@ -61,11 +52,18 @@ static inline unsigned long long usecs_to_ticks(unsigned long usecs) return ticks; } -static inline unsigned long read_timer(void) +static inline void read_timer(void) { - struct timer_regs *timer = (struct timer_regs *)TIMER_BASE; + struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE; + const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value); + + if (now >= timer.last_read) + timer.ticks += now - timer.last_read; + else + /* an overflow occurred */ + timer.ticks += TIMER_MAX_VAL - timer.last_read + now; - return TIMER_MAX_VAL - readl(&timer->timer3.value); + timer.last_read = now; } /* @@ -73,17 +71,14 @@ static inline unsigned long read_timer(void) */ unsigned long long get_ticks(void) { - const unsigned long now = read_timer(); + unsigned long long sys_ticks; - if (now >= timer.last_update) - timer.ticks += now - timer.last_update; - else - /* an overflow occurred */ - timer.ticks += TIMER_MAX_VAL - timer.last_update + now; + read_timer(); - timer.last_update = now; + sys_ticks = timer.ticks * CONFIG_SYS_HZ; + do_div(sys_ticks, TIMER_FREQ); - return clk_to_systicks(timer.ticks); + return sys_ticks; } unsigned long get_timer_masked(void) @@ -98,7 +93,7 @@ unsigned long get_timer(unsigned long base) void reset_timer_masked(void) { - timer.last_update = read_timer(); + read_timer(); timer.ticks = 0; } @@ -109,28 +104,29 @@ void reset_timer(void) void __udelay(unsigned long usec) { - /* read the timer and update timer.ticks */ - get_ticks(); + unsigned long long target; + + read_timer(); - const unsigned long long target = timer.ticks + usecs_to_ticks(usec); + target = timer.ticks + usecs_to_ticks(usec); while (timer.ticks < target) - get_ticks(); + read_timer(); } int timer_init(void) { - struct timer_regs *timer = (struct timer_regs *)TIMER_BASE; + struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE; - /* use timer 3 with 508KHz and free running */ - writel(TIMER_CLKSEL, &timer->timer3.control); + /* use timer 3 with 508KHz and free running, not enabled now */ + writel(TIMER_CLKSEL, &timer_regs->timer3.control); - /* set initial timer value 3 */ - writel(TIMER_MAX_VAL, &timer->timer3.load); + /* set initial timer value */ + writel(TIMER_MAX_VAL, &timer_regs->timer3.load); /* Enable the timer */ writel(TIMER_ENABLE | TIMER_CLKSEL, - &timer->timer3.control); + &timer_regs->timer3.control); reset_timer_masked(); diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c index b06d760..ecf91f5 100644 --- a/cpu/arm926ejs/at91/clock.c +++ b/cpu/arm926ejs/at91/clock.c @@ -203,7 +203,8 @@ int at91_clock_init(unsigned long main_clock) if (mckr & AT91_PMC_MCKR_MDIV_MASK) freq /= 2; /* processor clock division */ #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) - mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == AT91SAM9_PMC_MDIV_3 + mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == + (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4) ? freq / 3 : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #else diff --git a/cpu/arm926ejs/nomadik/timer.c b/cpu/arm926ejs/nomadik/timer.c index 047b9e3..1d98ef3 100644 --- a/cpu/arm926ejs/nomadik/timer.c +++ b/cpu/arm926ejs/nomadik/timer.c @@ -34,8 +34,8 @@ #define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) #define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) -/* macro to read the 32 bit timer: since it decrements, we invert read value */ -#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0))) +/* macro to read the decrementing 32 bit timer as an increasing count */ +#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0))) /* Configure a free-running, auto-wrap counter with no prescaler */ int timer_init(void) @@ -49,7 +49,16 @@ int timer_init(void) /* Restart counting from 0 */ void reset_timer(void) { - writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); /* Immediate effect */ + ulong val; + writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); + /* + * The load-register isn't really immediate: it changes on clock + * edges, so we must wait for our newly-written value to appear. + * Since we might miss reading 0, wait for any change in value. + */ + val = READ_TIMER(); + while (READ_TIMER() == val) + ; } /* Return how many HZ passed since "base" */ diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile index 4f922e6..01c93fe 100644 --- a/cpu/arm_cortexa8/s5pc1xx/Makefile +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile @@ -33,6 +33,8 @@ SOBJS += reset.o COBJS += clock.o COBJS += cpu_info.o +COBJS += gpio.o +COBJS += sromc.o COBJS += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm_cortexa8/s5pc1xx/clock.c b/cpu/arm_cortexa8/s5pc1xx/clock.c index a9e78dd..19619f9 100644 --- a/cpu/arm_cortexa8/s5pc1xx/clock.c +++ b/cpu/arm_cortexa8/s5pc1xx/clock.c @@ -25,12 +25,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> - -#define APLL 0 -#define MPLL 1 -#define EPLL 2 -#define HPLL 3 -#define VPLL 4 +#include <asm/arch/clk.h> #define CLK_M 0 #define CLK_D 1 diff --git a/cpu/arm_cortexa8/s5pc1xx/gpio.c b/cpu/arm_cortexa8/s5pc1xx/gpio.c new file mode 100644 index 0000000..a97244b --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/gpio.c @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> + +#define CON_MASK(x) (0xf << ((x) << 2)) +#define CON_SFR(x, v) ((v) << ((x) << 2)) + +#define DAT_MASK(x) (0x1 << (x)) +#define DAT_SET(x) (0x1 << (x)) + +#define PULL_MASK(x) (0x3 << ((x) << 1)) +#define PULL_MODE(x, v) ((v) << ((x) << 1)) + +#define DRV_MASK(x) (0x3 << ((x) << 1)) +#define DRV_SET(x, m) ((m) << ((x) << 1)) +#define RATE_MASK(x) (0x1 << (x + 16)) +#define RATE_SET(x) (0x1 << (x + 16)) + +void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg) +{ + unsigned int value; + + value = readl(&bank->con); + value &= ~CON_MASK(gpio); + value |= CON_SFR(gpio, cfg); + writel(value, &bank->con); +} + +void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en) +{ + unsigned int value; + + gpio_cfg_pin(bank, gpio, GPIO_OUTPUT); + + value = readl(&bank->dat); + value &= ~DAT_MASK(gpio); + if (en) + value |= DAT_SET(gpio); + writel(value, &bank->dat); +} + +void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio) +{ + gpio_cfg_pin(bank, gpio, GPIO_INPUT); +} + +void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en) +{ + unsigned int value; + + value = readl(&bank->dat); + value &= ~DAT_MASK(gpio); + if (en) + value |= DAT_SET(gpio); + writel(value, &bank->dat); +} + +unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio) +{ + unsigned int value; + + value = readl(&bank->dat); + return !!(value & DAT_MASK(gpio)); +} + +void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->pull); + value &= ~PULL_MASK(gpio); + + switch (mode) { + case GPIO_PULL_DOWN: + case GPIO_PULL_UP: + value |= PULL_MODE(gpio, mode); + break; + default: + return; + } + + writel(value, &bank->pull); +} + +void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->drv); + value &= ~DRV_MASK(gpio); + + switch (mode) { + case GPIO_DRV_1X: + case GPIO_DRV_2X: + case GPIO_DRV_3X: + case GPIO_DRV_4X: + value |= DRV_SET(gpio, mode); + break; + default: + return; + } + + writel(value, &bank->drv); +} + +void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->drv); + value &= ~RATE_MASK(gpio); + + switch (mode) { + case GPIO_DRV_FAST: + case GPIO_DRV_SLOW: + value |= RATE_SET(gpio); + break; + default: + return; + } + + writel(value, &bank->drv); +} diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c b/cpu/arm_cortexa8/s5pc1xx/sromc.c new file mode 100644 index 0000000..380be81 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * Naveen Krishna Ch <ch.naveen@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/smc.h> + +/* + * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the + * band width control and bank control registers + * srom_bank - SROM Bank 0 to 5 + * smc_bw_conf - SMC Band witdh reg configuration value + * smc_bc_conf - SMC Bank Control reg configuration value + */ +void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf) +{ + u32 tmp; + struct s5pc1xx_smc *srom; + + if (cpu_is_s5pc100()) + srom = (struct s5pc1xx_smc *)S5PC100_SROMC_BASE; + else + srom = (struct s5pc1xx_smc *)S5PC110_SROMC_BASE; + + /* Configure SMC_BW register to handle proper SROMC bank */ + tmp = srom->bw; + tmp &= ~(0xF << (srom_bank * 4)); + tmp |= smc_bw_conf; + srom->bw = tmp; + + /* Configure SMC_BC register */ + srom->bc[srom_bank] = smc_bc_conf; +} diff --git a/cpu/mpc512x/diu.c b/cpu/mpc512x/diu.c index ca459a1..c2453c6 100644 --- a/cpu/mpc512x/diu.c +++ b/cpu/mpc512x/diu.c @@ -27,7 +27,6 @@ #include <command.h> #include <asm/io.h> -#include "../../board/freescale/common/pixis.h" #include "../../board/freescale/common/fsl_diu_fb.h" #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 56de7eb..f064fee 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -50,7 +50,11 @@ COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o COBJS-$(CONFIG_MPC8569) += ddr-gen3.o COBJS-$(CONFIG_P1011) += ddr-gen3.o +COBJS-$(CONFIG_P1012) += ddr-gen3.o +COBJS-$(CONFIG_P1013) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o +COBJS-$(CONFIG_P1021) += ddr-gen3.o +COBJS-$(CONFIG_P1022) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index dab784e..0b5b9da 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * Kumar Gala <kumar.gala@freescale.com> * * See file CREDITS for list of people who contributed to this @@ -57,11 +57,19 @@ __secondary_start_page: #ifndef CONFIG_E500MC li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mfspr r0,PVR + andi. r0,r0,0xff + cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */ + blt 1f + /* Set MBDD bit also */ + ori r3, r3, HID1_MBDD@l +1: mtspr SPRN_HID1,r3 #endif /* Enable branch prediction */ - li r3,0x201 + lis r3,BUCSR_ENABLE@h + ori r3,r3,BUCSR_ENABLE@l mtspr SPRN_BUCSR,r3 /* Ensure TB is 0 */ diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index af18c1c..b3cb56a 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -208,13 +208,21 @@ _start_e500: #ifndef CONFIG_E500MC li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mfspr r3,PVR + andi. r3,r3, 0xff + cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ + blt 1f + /* Set MBDD bit also */ + ori r0, r0, HID1_MBDD@l +1: mtspr HID1,r0 #endif /* Enable Branch Prediction */ #if defined(CONFIG_BTB) - li r0,0x201 /* BBFI = 1, BPEN = 1 */ - mtspr BUCSR,r0 + lis r0,BUCSR_ENABLE@h + ori r0,r0,BUCSR_ENABLE@l + mtspr SPRN_BUCSR,r0 #endif #if defined(CONFIG_SYS_INIT_DBCR) diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index d191263..47842e9 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c. * Basically this file contains cpu specific common code for 85xx/86xx @@ -66,8 +66,16 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(8572, 8572_E, 2), CPU_TYPE_ENTRY(P1011, P1011, 1), CPU_TYPE_ENTRY(P1011, P1011_E, 1), + CPU_TYPE_ENTRY(P1012, P1012, 1), + CPU_TYPE_ENTRY(P1012, P1012_E, 1), + CPU_TYPE_ENTRY(P1013, P1013, 1), + CPU_TYPE_ENTRY(P1013, P1013_E, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), CPU_TYPE_ENTRY(P1020, P1020_E, 2), + CPU_TYPE_ENTRY(P1021, P1021, 2), + CPU_TYPE_ENTRY(P1021, P1021_E, 2), + CPU_TYPE_ENTRY(P1022, P1022, 2), + CPU_TYPE_ENTRY(P1022, P1022_E, 2), CPU_TYPE_ENTRY(P2010, P2010, 1), CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index adc4f6e..03f9c43 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1,9 +1,10 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. */ /* @@ -934,7 +935,8 @@ static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) } /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */ -static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr) +static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) { unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ @@ -943,9 +945,15 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr) unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ #if defined(CONFIG_FSL_DDR3) - /* We need set BL/2 + 4 for BC4 or OTF */ - rrt = 4; /* BL/2 + 4 clocks */ - wwt = 4; /* BL/2 + 4 clocks */ + if (popts->burst_length == DDR_BL8) { + /* We set BL/2 for fixed BL8 */ + rrt = 0; /* BL/2 clocks */ + wwt = 0; /* BL/2 clocks */ + } else { + /* We need to set BL/2 + 2 to BC4 and OTF */ + rrt = 2; /* BL/2 + 2 clocks */ + wwt = 2; /* BL/2 + 2 clocks */ + } dll_lock = 1; /* tDLLK = 512 clocks from spec */ #endif ddr->timing_cfg_4 = (0 @@ -1343,7 +1351,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_sdram_clk_cntl(ddr, popts); set_ddr_init_addr(ddr); set_ddr_init_ext_addr(ddr); - set_timing_cfg_4(ddr); + set_timing_cfg_4(ddr, popts); set_timing_cfg_5(ddr); set_ddr_zq_cntl(ddr, zq_en); diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c index 3dcd33d..46731c8 100644 --- a/cpu/mpc8xxx/ddr/options.c +++ b/cpu/mpc8xxx/ddr/options.c @@ -1,9 +1,10 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008, 2010 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. */ #include <common.h> @@ -109,8 +110,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, /* Choose burst length. */ #if defined(CONFIG_FSL_DDR3) +#if defined(CONFIG_E500MC) + popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */ + popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ +#else popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ +#endif #else popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ #endif diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c index d53781b..9b7181d 100644 --- a/cpu/mpc8xxx/pci_cfg.c +++ b/cpu/mpc8xxx/pci_cfg.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -25,7 +25,7 @@ #include <pci.h> struct pci_info { - u16 cfg; + u32 cfg; }; /* The cfg field is a bit mask in which each bit represents the value of @@ -153,7 +153,8 @@ static struct pci_info pci_config_info[] = (1 << 7) | (1 << 0xe) | (1 << 0xf), }, }; -#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) +#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ + defined(CONFIG_P1012) || defined(CONFIG_P1021) static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCIE_1] = { @@ -163,6 +164,29 @@ static struct pci_info pci_config_info[] = .cfg = (1 << 0xe), }, }; +#elif defined(CONFIG_P1013) || defined(CONFIG_P1022) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xa) | + (1 << 0xb) | (1 << 0xd) | (1 << 0xe) | + (1 << 0xf) | (1 << 0x15) | (1 << 0x16) | + (1 << 0x17) | (1 << 0x18) | (1 << 0x19) | + (1 << 0x1a) | (1 << 0x1b) | (1 << 0x1c) | + (1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f), + }, + [LAW_TRGT_IF_PCIE_2] = { + .cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) | + (1 << 9) | (1 << 0xa) | (1 << 0xb) | (1 << 0xd) | + (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | + (1 << 0x18) | (1 << 0x1c), + }, + [LAW_TRGT_IF_PCIE_3] = { + .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xd) | + (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | (1 << 0x18) | + (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b), + }, +}; #elif defined(CONFIG_P2010) || defined(CONFIG_P2020) static struct pci_info pci_config_info[] = { diff --git a/cpu/nios2/Makefile b/cpu/nios2/Makefile index 75f30b4..3dfaa83 100644 --- a/cpu/nios2/Makefile +++ b/cpu/nios2/Makefile @@ -27,7 +27,7 @@ LIB = $(obj)lib$(CPU).a START = start.o SOBJS = exceptions.o -COBJS = cpu.o interrupts.o serial.o sysid.o traps.o epcs.o +COBJS = cpu.o interrupts.o sysid.o traps.o epcs.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/nios2/epcs.c b/cpu/nios2/epcs.c index 483b249..ab7d746 100644 --- a/cpu/nios2/epcs.c +++ b/cpu/nios2/epcs.c @@ -85,7 +85,7 @@ static int epcs_cs (int assert) if (assert) { tmp = readl (&epcs->control); - writel (&epcs->control, tmp | NIOS_SPI_SSO); + writel (tmp | NIOS_SPI_SSO, &epcs->control); } else { /* Let all bits shift out */ start = get_timer (0); @@ -93,7 +93,7 @@ static int epcs_cs (int assert) if (get_timer (start) > EPCS_TIMEOUT) return (-1); tmp = readl (&epcs->control); - writel (&epcs->control, tmp & ~NIOS_SPI_SSO); + writel (tmp & ~NIOS_SPI_SSO, &epcs->control); } return (0); } @@ -106,7 +106,7 @@ static int epcs_tx (unsigned char c) while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0) if (get_timer (start) > EPCS_TIMEOUT) return (-1); - writel (&epcs->txdata, c); + writel (c, &epcs->txdata); return (0); } @@ -207,6 +207,8 @@ static void epcs_status_wr (unsigned char status) static struct epcs_devinfo_t devinfo[] = { { "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c }, { "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c }, + { "EPCS16", 0x14, 21, 32, 16, 8, 0x1c }, + { "EPCS64", 0x16, 23,128, 16, 8, 0x1c }, { 0, 0, 0, 0, 0, 0 } }; @@ -501,15 +503,17 @@ void do_epcs_info (struct epcs_devinfo_t *dev, int argc, char *argv[]) } /* Sector info */ - for (i=0; i<dev->num_sects; i++) { + for (i=0; (i < dev->num_sects) && (argc > 1); i++) { erased = epcs_sect_erased (i, &tmp, dev); - printf (" %d: %06x ", + if ((i & 0x03) == 0) printf ("\n"); + printf ("%4d: %07x ", i, i*(1<<dev->sz_sect) ); if (erased) - printf ("erased\n"); + printf ("E "); else - printf ("data @ 0x%06x\n", tmp); + printf (" "); } + printf ("\n"); return; } diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c index 1c3566e..b552db4 100644 --- a/cpu/nios2/interrupts.c +++ b/cpu/nios2/interrupts.c @@ -56,7 +56,40 @@ volatile ulong timestamp = 0; void reset_timer (void) { + nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE; + + /* From Embedded Peripherals Handbook: + * + * "When the hardware is configured with Writeable period + * disabled, writing to one of the period_n registers causes + * the counter to reset to the fixed Timeout Period specified + * at system generation time." + * + * Here we force a reload to prevent early timeouts from + * get_timer() when the interrupt period is greater than + * than 1 msec. + * + * Simply write to periodl with its own value to force an + * internal counter reload, THEN reset the timestamp. + */ + writel (readl (&tmr->periodl), &tmr->periodl); timestamp = 0; + + /* From Embedded Peripherals Handbook: + * + * "Writing to one of the period_n registers stops the internal + * counter, except when the hardware is configured with Start/Stop + * control bits off. If Start/Stop control bits is off, writing + * either register does not stop the counter." + * + * In order to accomodate either configuration, the control + * register is re-written. If the counter is stopped, it will + * be restarted. If it is running, the write is essentially + * a nop. + */ + writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START, + &tmr->control); + } ulong get_timer (ulong base) @@ -81,7 +114,7 @@ void tmr_isr (void *arg) /* Interrupt is cleared by writing anything to the * status register. */ - writel (&tmr->status, 0); + writel (0, &tmr->status); timestamp += CONFIG_SYS_NIOS_TMRMS; #ifdef CONFIG_STATUS_LED status_led_tick(timestamp); @@ -92,16 +125,16 @@ static void tmr_init (void) { nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE; - writel (&tmr->status, 0); - writel (&tmr->control, 0); - writel (&tmr->control, NIOS_TIMER_STOP); + writel (0, &tmr->status); + writel (0, &tmr->control); + writel (NIOS_TIMER_STOP, &tmr->control); #if defined(CONFIG_SYS_NIOS_TMRCNT) - writel (&tmr->periodl, CONFIG_SYS_NIOS_TMRCNT & 0xffff); - writel (&tmr->periodh, (CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff); + writel (CONFIG_SYS_NIOS_TMRCNT & 0xffff, &tmr->periodl); + writel ((CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff, &tmr->periodh); #endif - writel (&tmr->control, NIOS_TIMER_ITO | NIOS_TIMER_CONT | - NIOS_TIMER_START ); + writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START, + &tmr->control); irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ, tmr_isr, (void *)tmr); } diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 365f966..88d53fb 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -52,7 +52,6 @@ COBJS += denali_data_eye.o COBJS += denali_spd_ddr2.o COBJS += ecc.o COBJS += fdt.o -COBJS += i2c.o COBJS += interrupts.o COBJS += iop480_uart.o ifdef CONFIG_CMD_REGINFO diff --git a/doc/README.mvsmr b/doc/README.mvsmr new file mode 100644 index 0000000..d729ea6 --- /dev/null +++ b/doc/README.mvsmr @@ -0,0 +1,55 @@ +Matrix Vision mvSMR +------------------- + +1. Board Description + + The mvSMR is a 75x130mm single image processing board used + in automation. Power Supply is 24VDC. + +2 System Components + +2.1 CPU + Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB. + 64MB DDR-I @ 133MHz. + 8 MByte Nor Flash on local bus. + 2 serial ports. Console running on ttyS0 @ 115200 8N1. + +2.2 PCI + PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core. + +2.3 FPGA + Xilinx Spartan-3 XC3S200 with PCI DMA engine. + Connects to Matrix Vision specific CCD/CMOS sensor interface. + +2.4 I2C + EEPROM @ 0xA0 for vendor specifics. + image sensor interface (slave adresses depend on sensor) + +3 Flash layout. + + reset vector is 0x00000100, i.e. "LOWBOOT". + + FF800000 u-boot + FF806000 u-boot script image + FF808000 u-boot environment + FF840000 FPGA raw bit file + FF880000 root FS + FFF00000 kernel + +4 Booting + + On startup the bootscript @ FF806000 is executed. This script can be + exchanged easily. Default boot mode is "boot from flash", i.e. system + works stand-alone. + + This behaviour depends on some environment variables : + + "netboot" : yes ->try dhcp/bootp and boot from network. + A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for + DHCP server configuration, e.g. to provide different images to + different devices. + + During netboot the system tries to get 3 image files: + 1. Kernel - name + data is given during BOOTP. + 2. Initrd - name is stored in "initrd_name" + Fallback files are the flash versions. diff --git a/doc/README.s5pc1xx b/doc/README.s5pc1xx index 5a0fe33..ab1f024 100644 --- a/doc/README.s5pc1xx +++ b/doc/README.s5pc1xx @@ -41,7 +41,23 @@ To check SoC: printf("cpu is s5pc110\n"); gpio - not supported yet. + + struct s5pc100_gpio *gpio = (struct s5pc100_gpio*)S5PC100_GPIO_BASE; + + /* GPA[0] pin set to irq */ + gpio_cfg_pin(&gpio->gpio_a, 0, GPIO_IRQ); + + /* GPA[0] pin set to input */ + gpio_direction_input(&gpio->gpio_a, 0); + + /* GPA[0] pin set to output/high */ + gpio_direction_output(&gpio->gpio_a, 0, 1); + + /* GPA[0] value set to low */ + gpio_set_value(&gpio->gpio_a, 0, 0); + + /* get GPA[0] value */ + value = gpio_get_value(&gpio->gpio_a, 0); Links ===== diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index 5f9bd10..dbb5e8c 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -173,7 +173,7 @@ Maps a pointer to the BIOS image on the graphics card on the PCI bus. ****************************************************************************/ void *PCI_mapBIOSImage(pci_dev_t pcidev) { - u32 BIOSImagePhys; + u32 BIOSImageBus; int BIOSImageBAR; u8 *BIOSImage; @@ -195,16 +195,18 @@ void *PCI_mapBIOSImage(pci_dev_t pcidev) specific programming for different cards to solve this problem. */ - if ((BIOSImagePhys = PCI_findBIOSAddr(pcidev, &BIOSImageBAR)) == 0) { + BIOSImageBus = PCI_findBIOSAddr(pcidev, &BIOSImageBAR); + if (BIOSImageBus == 0) { printf("Find bios addr error\n"); return NULL; } - BIOSImage = (u8 *) BIOSImagePhys; + BIOSImage = pci_bus_to_virt(pcidev, BIOSImageBus, + PCI_REGION_MEM, 0, MAP_NOCACHE); /*Change the PCI BAR registers to map it onto the bus.*/ pci_write_config_dword(pcidev, BIOSImageBAR, 0); - pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImagePhys | 0x1); + pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1); udelay(1); @@ -315,7 +317,8 @@ int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp) BE_init(0, 65536, VGAInfo, 0); /*Post all the display controller BIOS'es*/ - PCI_postController(pcidev, VGAInfo); + if (!PCI_postController(pcidev, VGAInfo)) + return false; /*Cleanup and exit the emulator if requested. If the BIOS emulator is needed after booting the card, we will not call BE_exit and diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 29bda85..d2c2515 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o +COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o diff --git a/cpu/ppc4xx/i2c.c b/drivers/i2c/ppc4xx_i2c.c index 9b86187..9b86187 100644 --- a/cpu/ppc4xx/i2c.c +++ b/drivers/i2c/ppc4xx_i2c.c diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 287e555..8255175 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -39,6 +39,8 @@ DECLARE_GLOBAL_DATA_PTR; #define FSL_HW_NUM_LAWS 10 #elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \ defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ + defined(CONFIG_P1012) || defined(CONFIG_P1021) || \ + defined(CONFIG_P1013) || defined(CONFIG_P1022) || \ defined(CONFIG_P2010) || defined(CONFIG_P2020) #define FSL_HW_NUM_LAWS 12 #elif defined(CONFIG_PPC_P4080) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index e665b5e..0f6f8b1 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, Freescale Semiconductor, Inc + * Copyright 2007,2010 Freescale Semiconductor, Inc * Andy Fleming * * Based vaguely on the pxa mmc code: @@ -110,8 +110,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) if (wml_value > 0x10) wml_value = 0x10; - wml_value = 0x100000 | wml_value; - + esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); esdhc_write32(®s->dsaddr, (u32)data->dest); } else { if (wml_value > 0x80) @@ -120,12 +119,12 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); return TIMEOUT; } - wml_value = wml_value << 16 | 0x10; + + esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, + wml_value << 16); esdhc_write32(®s->dsaddr, (u32)data->src); } - esdhc_write32(®s->wml, wml_value); - esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); /* Calculate the timeout period for data transactions */ @@ -265,18 +264,13 @@ void set_sysctl(struct mmc *mmc, uint clock) clk = (pre_div << 8) | (div << 4); - /* On imx the clock must be stopped before changing frequency */ - if (cfg->clk_enable) - esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); + esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); udelay(10000); - clk = SYSCTL_PEREN; - /* On imx systems the clock must be explicitely enabled */ - if (cfg->clk_enable) - clk |= SYSCTL_CKEN; + clk = SYSCTL_PEREN | SYSCTL_CKEN; esdhc_setbits32(®s->sysctl, clk); } @@ -349,6 +343,20 @@ static int esdhc_init(struct mmc *mmc) return ret; } +static void esdhc_reset(struct fsl_esdhc *regs) +{ + unsigned long timeout = 100; /* wait max 100 ms */ + + /* reset the controller */ + esdhc_write32(®s->sysctl, SYSCTL_RSTA); + + /* hardware clears the bit when it is done */ + while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) + udelay(1000); + if (!timeout) + printf("MMC/SD: Reset never completed.\n"); +} + int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) { struct fsl_esdhc *regs; @@ -363,6 +371,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) sprintf(mmc->name, "FSL_ESDHC"); regs = (struct fsl_esdhc *)cfg->esdhc_base; + /* First reset the eSDHC controller */ + esdhc_reset(regs); + mmc->priv = cfg; mmc->send_cmd = esdhc_send_cmd; mmc->set_ios = esdhc_set_ios; diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index d0240f5..3267c5d 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -544,6 +544,7 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector, #endif /* Wait for command completion */ + reset_timer(); start = get_timer (0); while (flash_is_busy (info, sector)) { if (get_timer (start) > tout) { @@ -630,6 +631,7 @@ static int flash_status_poll(flash_info_t *info, void *src, void *dst, #endif /* Wait for command completion */ + reset_timer(); start = get_timer(0); while (1) { switch (info->portwidth) { diff --git a/drivers/mtd/spi/eeprom_m95xxx.c b/drivers/mtd/spi/eeprom_m95xxx.c index 0148d00..632db4e 100644 --- a/drivers/mtd/spi/eeprom_m95xxx.c +++ b/drivers/mtd/spi/eeprom_m95xxx.c @@ -44,6 +44,9 @@ ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000, CONFIG_DEFAULT_SPI_MODE); + if(!slave) + return 0; + spi_claim_bus(slave); /* command */ @@ -75,6 +78,9 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000, CONFIG_DEFAULT_SPI_MODE); + if (!slave) + return 0; + spi_claim_bus(slave); buf[0] = SPI_EEPROM_WREN; diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index fe57926..5a63fa2 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -1,9 +1,10 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -513,10 +514,15 @@ void ft_fsl_pci_setup(void *blob, const char *pci_alias, struct pci_controller *hose) { int off = fdt_path_offset(blob, pci_alias); + u32 bus_range[2]; - if (off >= 0) { - u32 bus_range[2]; + if (off < 0) + return; + /* We assume a cfg_addr not being set means we didn't setup the controller */ + if ((hose == NULL) || (hose->cfg_addr == NULL)) { + fdt_del_node_and_alias(blob, pci_alias); + } else { bus_range[0] = 0; bus_range[1] = hose->last_busno - hose->first_busno; fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 3c77a7c..d2b4820 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,11 +25,14 @@ include $(TOPDIR)/config.mk LIB := $(obj)libserial.a +COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o +COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o COBJS-$(CONFIG_AT91RM9200_USART) += at91rm9200_usart.o COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o COBJS-$(CONFIG_MCFUART) += mcfuart.o COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o +COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o COBJS-$(CONFIG_SYS_NS16550) += ns16550.o COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o COBJS-$(CONFIG_S3C64XX) += s3c64xx.o diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c new file mode 100644 index 0000000..fb28aa9 --- /dev/null +++ b/drivers/serial/altera_jtag_uart.c @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/io.h> +#include <nios2-io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/*------------------------------------------------------------------ + * JTAG acts as the serial port + *-----------------------------------------------------------------*/ +static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE; + +void serial_setbrg( void ){ return; } +int serial_init( void ) { return(0);} + +void serial_putc (char c) +{ + while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0) + WATCHDOG_RESET (); + writel ((unsigned char)c, &jtag->data); +} + +void serial_puts (const char *s) +{ + while (*s != 0) + serial_putc (*s++); +} + +int serial_tstc (void) +{ + return ( readl (&jtag->control) & NIOS_JTAG_RRDY); +} + +int serial_getc (void) +{ + int c; + unsigned val; + + while (1) { + WATCHDOG_RESET (); + val = readl (&jtag->data); + if (val & NIOS_JTAG_RVALID) + break; + } + c = val & 0x0ff; + return (c); +} diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c new file mode 100644 index 0000000..045f119 --- /dev/null +++ b/drivers/serial/altera_uart.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#include <watchdog.h> +#include <asm/io.h> +#include <nios2-io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/*------------------------------------------------------------------ + * UART the serial port + *-----------------------------------------------------------------*/ + +static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE; + +#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) + +/* Everything's already setup for fixed-baud PTF + * assignment + */ +void serial_setbrg (void){ return; } +int serial_init (void) { return (0);} + +#else + +void serial_setbrg (void) +{ + unsigned div; + + div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1; + writel (div, &uart->divisor); + return; +} + +int serial_init (void) +{ + serial_setbrg (); + return (0); +} + +#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ + +/*----------------------------------------------------------------------- + * UART CONSOLE + *---------------------------------------------------------------------*/ +void serial_putc (char c) +{ + if (c == '\n') + serial_putc ('\r'); + while ((readl (&uart->status) & NIOS_UART_TRDY) == 0) + WATCHDOG_RESET (); + writel ((unsigned char)c, &uart->txdata); +} + +void serial_puts (const char *s) +{ + while (*s != 0) { + serial_putc (*s++); + } +} + +int serial_tstc (void) +{ + return (readl (&uart->status) & NIOS_UART_RRDY); +} + +int serial_getc (void) +{ + while (serial_tstc () == 0) + WATCHDOG_RESET (); + return (readl (&uart->rxdata) & 0x00ff ); +} diff --git a/cpu/nios2/serial.c b/drivers/serial/opencores_yanu.c index 6c835af..f18f7f4 100644 --- a/cpu/nios2/serial.c +++ b/drivers/serial/opencores_yanu.c @@ -1,8 +1,4 @@ /* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * YANU Support: * Copyright 2010, Renato Andreola <renato.andreola@imagos.it> * * See file CREDITS for list of people who contributed to this @@ -24,61 +20,13 @@ * MA 02111-1307 USA */ - #include <common.h> #include <watchdog.h> #include <asm/io.h> -#include <nios2-io.h> #include <nios2-yanu.h> DECLARE_GLOBAL_DATA_PTR; -/*------------------------------------------------------------------ - * JTAG acts as the serial port - *-----------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) - -static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE; - -void serial_setbrg( void ){ return; } -int serial_init( void ) { return(0);} - -void serial_putc (char c) -{ - unsigned val; - - while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0) - WATCHDOG_RESET (); - writel (&jtag->data, (unsigned char)c); -} - -void serial_puts (const char *s) -{ - while (*s != 0) - serial_putc (*s++); -} - -int serial_tstc (void) -{ - return ( readl (&jtag->control) & NIOS_JTAG_RRDY); -} - -int serial_getc (void) -{ - int c; - unsigned val; - - while (1) { - WATCHDOG_RESET (); - val = readl (&jtag->data); - if (val & NIOS_JTAG_RVALID) - break; - } - c = val & 0x0ff; - return (c); -} - -#elif defined(CONFIG_CONSOLE_YANU) /*-----------------------------------------------------------------*/ /* YANU Imagos serial port */ /*-----------------------------------------------------------------*/ @@ -113,7 +61,7 @@ void serial_setbrg (void) ((unsigned)CONFIG_SYS_CLK_FREQ >> k); baud = best_m + best_n * YANU_BAUDE; - writel(&uart->baud, baud); + writel(baud, &uart->baud); return; } @@ -144,7 +92,7 @@ void serial_setbrg (void) ((unsigned)CONFIG_SYS_CLK_FREQ >> k); baud = best_m + best_n * YANU_BAUDE; - writel(&uart->baud, baud); + writel(baud, &uart->baud); return; } @@ -165,7 +113,7 @@ int serial_init (void) YANU_ACTION_RPE | YANU_ACTION_RFE | YANU_ACTION_RFIFO_CLEAR | YANU_ACTION_TFIFO_CLEAR; - writel(&uart->action, action); + writel(action, &uart->action); /* control register cleanup */ /* no interrupts enabled */ @@ -179,7 +127,7 @@ int serial_init (void) control |= YANU_CONTROL_RDYDLY * YANU_RXFIFO_DLY; control |= YANU_CONTROL_TXTHR * YANU_TXFIFO_THR; - writel(&uart->control, control); + writel(control, &uart->control); /* to set baud rate */ serial_setbrg(); @@ -208,7 +156,7 @@ void serial_putc (char c) WATCHDOG_RESET (); } - writel(&uart->data, (unsigned char)c); + writel((unsigned char)c, &uart->data); } void serial_puts (const char *s) @@ -234,76 +182,7 @@ int serial_getc (void) WATCHDOG_RESET (); /* first we pull the char */ - writel(&uart->action, YANU_ACTION_RFIFO_PULL); + writel(YANU_ACTION_RFIFO_PULL, &uart->action); return(readl(&uart->data) & YANU_DATA_CHAR_MASK); } - -#else /*CONFIG_CONSOLE_YANU*/ - -/*------------------------------------------------------------------ - * UART the serial port - *-----------------------------------------------------------------*/ - -static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE; - -#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) - -/* Everything's already setup for fixed-baud PTF - * assignment - */ -void serial_setbrg (void){ return; } -int serial_init (void) { return (0);} - -#else - -void serial_setbrg (void) -{ - unsigned div; - - div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1; - writel (&uart->divisor,div); - return; -} - -int serial_init (void) -{ - serial_setbrg (); - return (0); -} - -#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ - - -/*----------------------------------------------------------------------- - * UART CONSOLE - *---------------------------------------------------------------------*/ -void serial_putc (char c) -{ - if (c == '\n') - serial_putc ('\r'); - while ((readl (&uart->status) & NIOS_UART_TRDY) == 0) - WATCHDOG_RESET (); - writel (&uart->txdata,(unsigned char)c); -} - -void serial_puts (const char *s) -{ - while (*s != 0) { - serial_putc (*s++); - } -} - -int serial_tstc (void) -{ - return (readl (&uart->status) & NIOS_UART_RRDY); -} - -int serial_getc (void) -{ - while (serial_tstc () == 0) - WATCHDOG_RESET (); - return (readl (&uart->rxdata) & 0x00ff ); -} - -#endif /* CONFIG_JTAG_CONSOLE */ diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 9ebeb4f..7784d92 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -55,14 +55,14 @@ static struct descriptor { { 0x12, /* bLength */ 1, /* bDescriptorType: UDESC_DEVICE */ - 0x0002, /* bcdUSB: v2.0 */ + cpu_to_le16(0x0200), /* bcdUSB: v2.0 */ 9, /* bDeviceClass: UDCLASS_HUB */ 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ 64, /* bMaxPacketSize: 64 bytes */ 0x0000, /* idVendor */ 0x0000, /* idProduct */ - 0x0001, /* bcdDevice */ + cpu_to_le16(0x0100), /* bcdDevice */ 1, /* iManufacturer */ 2, /* iProduct */ 0, /* iSerialNumber */ @@ -536,7 +536,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, uint32_t reg; uint32_t *status_reg; - if (le16_to_cpu(req->index) >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { + if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { printf("The request port(%d) is not configured\n", le16_to_cpu(req->index) - 1); return -1; @@ -630,19 +630,8 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, tmpbuf[0] |= USB_PORT_STAT_SUSPEND; if (reg & EHCI_PS_OCA) tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; - if (reg & EHCI_PS_PR && - (portreset & (1 << le16_to_cpu(req->index)))) { - int ret; - /* force reset to complete */ - reg = reg & ~(EHCI_PS_PR | EHCI_PS_CLEAR); - ehci_writel(status_reg, reg); - ret = handshake(status_reg, EHCI_PS_PR, 0, 2 * 1000); - if (!ret) - tmpbuf[0] |= USB_PORT_STAT_RESET; - else - printf("port(%d) reset error\n", - le16_to_cpu(req->index) - 1); - } + if (reg & EHCI_PS_PR) + tmpbuf[0] |= USB_PORT_STAT_RESET; if (reg & EHCI_PS_PP) tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; @@ -699,6 +688,8 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, ehci_writel(status_reg, reg); break; } else { + int ret; + reg |= EHCI_PS_PR; reg &= ~EHCI_PS_PE; ehci_writel(status_reg, reg); @@ -710,8 +701,19 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, wait_ms(50); /* terminate the reset */ ehci_writel(status_reg, reg & ~EHCI_PS_PR); - wait_ms(2); - portreset |= 1 << le16_to_cpu(req->index); + /* + * A host controller must terminate the reset + * and stabilize the state of the port within + * 2 milliseconds + */ + ret = handshake(status_reg, EHCI_PS_PR, 0, + 2 * 1000); + if (!ret) + portreset |= + 1 << le16_to_cpu(req->index); + else + printf("port(%d) reset error\n", + le16_to_cpu(req->index) - 1); } break; default: diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 441b1a2..047902a 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -28,6 +28,7 @@ #ifdef CONFIG_PCI_EHCI_DEVICE static struct pci_device_id ehci_pci_ids[] = { /* Please add supported PCI EHCI controller ids here */ + {0x1033, 0x00E0}, {0, 0} }; #endif diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 29f3ba1..b2e03bc 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -25,11 +25,6 @@ #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) -#ifndef CONFIG_AT91_LEGACY -#define CONFIG_AT91_LEGACY -#warning Please update to use C structur SoC access ! -#endif - #include <asm/arch/hardware.h> #include <asm/arch/io.h> #include <asm/arch/at91_pmc.h> @@ -37,22 +32,23 @@ int usb_cpu_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE; #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ defined(CONFIG_AT91SAM9261) /* Enable PLLB */ - at91_sys_write(AT91_CKGR_PLLBR, get_pllb_init()); - while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) + writel(get_pllb_init(), &pmc->pllbr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) ; #endif /* Enable USB host clock. */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP); + writel(1 << AT91_ID_UHP, &pmc->pcer); #ifdef CONFIG_AT91SAM9261 - at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP | AT91_PMC_HCK0); + writel(AT91_PMC_UHP | AT91_PMC_HCK0, &pmc->scer); #else - at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP); + writel(AT91_PMC_UHP, &pmc->scer); #endif return 0; @@ -60,19 +56,21 @@ int usb_cpu_init(void) int usb_cpu_stop(void) { + at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE; + /* Disable USB host clock. */ - at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP); + writel(1 << AT91_ID_UHP, &pmc->pcdr); #ifdef CONFIG_AT91SAM9261 - at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_HCK0); + writel(AT91_PMC_UHP | AT91_PMC_HCK0, &pmc->scdr); #else - at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP); + writel(AT91_PMC_UHP, &pmc->scdr); #endif #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) /* Disable PLLB */ - at91_sys_write(AT91_CKGR_PLLBR, 0); - while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != 0) + writel(0, &pmc->pllbr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) ; #endif diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c index 9ebb0b0..4a9bd07 100644 --- a/drivers/video/ati_radeon_fb.c +++ b/drivers/video/ati_radeon_fb.c @@ -210,7 +210,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo) * ToDo: identify these cases */ - DPRINT("radeonfb: Found %ldk of %s %d bits wide videoram\n", + DPRINT("radeonfb: Found %dk of %s %d bits wide videoram\n", rinfo->video_ram / 1024, rinfo->vram_ddr ? "DDR" : "SDRAM", rinfo->vram_width); @@ -586,18 +586,21 @@ int radeon_probe(struct radeonfb_info *rinfo) rinfo->pdev.device = did; rinfo->family = get_radeon_id_family(rinfo->pdev.device); pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, - &rinfo->fb_base_phys); + &rinfo->fb_base_bus); pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2, - &rinfo->mmio_base_phys); - rinfo->fb_base_phys &= 0xfffff000; - rinfo->mmio_base_phys &= ~0x04; - - rinfo->mmio_base = (void *)rinfo->mmio_base_phys; - DPRINT("rinfo->mmio_base = 0x%x\n",rinfo->mmio_base); + &rinfo->mmio_base_bus); + rinfo->fb_base_bus &= 0xfffff000; + rinfo->mmio_base_bus &= ~0x04; + + rinfo->mmio_base = pci_bus_to_virt(pdev, rinfo->mmio_base_bus, + PCI_REGION_MEM, 0, MAP_NOCACHE); + DPRINT("rinfo->mmio_base = 0x%p bus=0x%x\n", + rinfo->mmio_base, rinfo->mmio_base_bus); rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base); /* PostBIOS with x86 emulater */ - BootVideoCardBIOS(pdev, NULL, 0); + if (!BootVideoCardBIOS(pdev, NULL, 0)) + return -1; /* * Check for errata @@ -610,14 +613,15 @@ int radeon_probe(struct radeonfb_info *rinfo) rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram); - rinfo->fb_base = (void *)rinfo->fb_base_phys; - - DPRINT("Radeon: framebuffer base phy address 0x%08x," \ - "MMIO base phy address 0x%08x," \ - "framebuffer local base 0x%08x.\n ", - rinfo->fb_base_phys, rinfo->mmio_base_phys, - rinfo->fb_local_base); - + rinfo->fb_base = pci_bus_to_virt(pdev, rinfo->fb_base_bus, + PCI_REGION_MEM, 0, MAP_NOCACHE); + DPRINT("Radeon: framebuffer base address 0x%08x, " + "bus address 0x%08x\n" + "MMIO base address 0x%08x, bus address 0x%08x, " + "framebuffer local base 0x%08x.\n ", + (u32)rinfo->fb_base, rinfo->fb_base_bus, + (u32)rinfo->mmio_base, rinfo->mmio_base_bus, + rinfo->fb_local_base); return 0; } return -1; @@ -733,13 +737,13 @@ void *video_hw_init(void) } pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; - pGD->pciBase = rinfo->fb_base_phys; - pGD->frameAdrs = rinfo->fb_base_phys; + pGD->pciBase = (unsigned int)rinfo->fb_base; + pGD->frameAdrs = (unsigned int)rinfo->fb_base; pGD->memSize = 64 * 1024 * 1024; /* Cursor Start Address */ - pGD->dprBase = - (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + rinfo->fb_base_phys; + pGD->dprBase = (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + + (unsigned int)rinfo->fb_base; if ((pGD->dprBase & 0x0fff) != 0) { /* allign it */ pGD->dprBase &= 0xfffff000; @@ -747,8 +751,8 @@ void *video_hw_init(void) } DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase, PATTERN_ADR); - pGD->vprBase = rinfo->fb_base_phys; /* Dummy */ - pGD->cprBase = rinfo->fb_base_phys; /* Dummy */ + pGD->vprBase = (unsigned int)rinfo->fb_base; /* Dummy */ + pGD->cprBase = (unsigned int)rinfo->fb_base; /* Dummy */ /* set up Hardware */ /* Clear video memory (only visible screen area) */ diff --git a/drivers/video/ati_radeon_fb.h b/drivers/video/ati_radeon_fb.h index e981f95..0659045 100644 --- a/drivers/video/ati_radeon_fb.h +++ b/drivers/video/ati_radeon_fb.h @@ -49,8 +49,8 @@ struct radeonfb_info { struct pci_device_id pdev; u16 family; - u32 fb_base_phys; - u32 mmio_base_phys; + u32 fb_base_bus; + u32 mmio_base_bus; void *mmio_base; void *fb_base; diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 49f0a2e..d1f47c9 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -803,8 +803,193 @@ static void inline fill_555rgb_pswap(uchar *fb, int x, #endif /* + * RLE8 bitmap support + */ + +#ifdef CONFIG_VIDEO_BMP_RLE8 +/* Pre-calculated color table entry */ +struct palette { + union { + unsigned short w; /* word */ + unsigned int dw; /* double word */ + } ce; /* color entry */ +}; + +/* + * Helper to draw encoded/unencoded run. + */ +static void draw_bitmap (uchar **fb, uchar *bm, struct palette *p, + int cnt, int enc) +{ + ulong addr = (ulong)*fb; + int *off; + int enc_off = 1; + int i; + + /* + * Setup offset of the color index in the bitmap. + * Color index of encoded run is at offset 1. + */ + off = enc ? &enc_off : &i; + + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + for (i = 0; i < cnt; i++) + *(unsigned char *)addr++ = bm[*off]; + break; + case GDF_15BIT_555RGB: + case GDF_16BIT_565RGB: + /* differences handled while pre-calculating palette */ + for (i = 0; i < cnt; i++) { + *(unsigned short *)addr = p[bm[*off]].ce.w; + addr += 2; + } + break; + case GDF_32BIT_X888RGB: + for (i = 0; i < cnt; i++) { + *(unsigned long *)addr = p[bm[*off]].ce.dw; + addr += 4; + } + break; + } + *fb = (uchar *)addr; /* return modified address */ +} + +static int display_rle8_bitmap (bmp_image_t *img, int xoff, int yoff, + int width, int height) +{ + unsigned char *bm; + unsigned char *fbp; + unsigned int cnt, runlen; + int decode = 1; + int x, y, bpp, i, ncolors; + struct palette p[256]; + bmp_color_table_entry_t cte; + int green_shift, red_off; + + x = 0; + y = __le32_to_cpu(img->header.height) - 1; + ncolors = __le32_to_cpu(img->header.colors_used); + bpp = VIDEO_PIXEL_SIZE; + fbp = (unsigned char *)((unsigned int)video_fb_address + + (((y + yoff) * VIDEO_COLS) + xoff) * bpp); + + bm = (uchar *)img + __le32_to_cpu(img->header.data_offset); + + /* pre-calculate and setup palette */ + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + for (i = 0; i < ncolors; i++) { + cte = img->color_table[i]; + video_set_lut (i, cte.red, cte.green, cte.blue); + } + break; + case GDF_15BIT_555RGB: + case GDF_16BIT_565RGB: + if (VIDEO_DATA_FORMAT == GDF_15BIT_555RGB) { + green_shift = 3; + red_off = 10; + } else { + green_shift = 2; + red_off = 11; + } + for (i = 0; i < ncolors; i++) { + cte = img->color_table[i]; + p[i].ce.w = SWAP16((unsigned short) + (((cte.red >> 3) << red_off) | + ((cte.green >> green_shift) << 5) | + cte.blue >> 3)); + } + break; + case GDF_32BIT_X888RGB: + for (i = 0; i < ncolors; i++) { + cte = img->color_table[i]; + p[i].ce.dw = SWAP32((cte.red << 16) | (cte.green << 8) | + cte.blue); + } + break; + default: + printf("RLE Bitmap unsupported in video mode 0x%x\n", + VIDEO_DATA_FORMAT); + return -1; + } + + while (decode) { + switch (bm[0]) { + case 0: + switch (bm[1]) { + case 0: + /* scan line end marker */ + bm += 2; + x = 0; + y--; + fbp = (unsigned char *) + ((unsigned int)video_fb_address + + (((y + yoff) * VIDEO_COLS) + + xoff) * bpp); + continue; + case 1: + /* end of bitmap data marker */ + decode = 0; + break; + case 2: + /* run offset marker */ + x += bm[2]; + y -= bm[3]; + fbp = (unsigned char *) + ((unsigned int)video_fb_address + + (((y + yoff) * VIDEO_COLS) + + x + xoff) * bpp); + bm += 4; + break; + default: + /* unencoded run */ + cnt = bm[1]; + runlen = cnt; + bm += 2; + if (y < height) { + if (x >= width) { + x += runlen; + goto next_run; + } + if (x + runlen > width) + cnt = width - x; + + draw_bitmap (&fbp, bm, p, cnt, 0); + x += runlen; + } +next_run: + bm += runlen; + if (runlen & 1) + bm++; /* 0 padding if length is odd */ + } + break; + default: + /* encoded run */ + if (y < height) { /* only draw into visible area */ + cnt = bm[0]; + runlen = cnt; + if (x >= width) { + x += runlen; + bm += 2; + continue; + } + if (x + runlen > width) + cnt = width - x; + + draw_bitmap (&fbp, bm, p, cnt, 1); + x += runlen; + } + bm += 2; + break; + } + } + return 0; +} +#endif + +/* * Display the BMP file located at address bmp_image. - * Only uncompressed */ int video_display_bitmap (ulong bmp_image, int x, int y) { @@ -872,7 +1057,11 @@ int video_display_bitmap (ulong bmp_image, int x, int y) debug ("Display-bmp: %d x %d with %d colors\n", width, height, colors); - if (compression != BMP_BI_RGB) { + if (compression != BMP_BI_RGB +#ifdef CONFIG_VIDEO_BMP_RLE8 + && compression != BMP_BI_RLE8 +#endif + ) { printf ("Error: compression type %ld not supported\n", compression); #ifdef CONFIG_VIDEO_BMP_GZIP @@ -906,6 +1095,13 @@ int video_display_bitmap (ulong bmp_image, int x, int y) ((y + height - 1) * VIDEO_COLS * VIDEO_PIXEL_SIZE) + x * VIDEO_PIXEL_SIZE); +#ifdef CONFIG_VIDEO_BMP_RLE8 + if (compression == BMP_BI_RLE8) { + return display_rle8_bitmap(bmp, + x, y, width, height); + } +#endif + /* We handle only 8bpp or 24 bpp bitmap */ switch (le16_to_cpu (bmp->header.bit_count)) { case 8: diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index 5bb8b77..25afae7 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -42,11 +42,10 @@ static int at91_wdt_settimeout(unsigned int timeout) { unsigned int reg; - unsigned int mr; + at91_wdt_t *wd = (at91_wdt_t *) AT91_WDT_BASE; /* Check if disabled */ - mr = at91_sys_read(AT91_WDT_MR); - if (mr & AT91_WDT_WDDIS) { + if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) { printf("sorry, watchdog is disabled\n"); return -1; } @@ -57,19 +56,21 @@ static int at91_wdt_settimeout(unsigned int timeout) * Since WDV is a 12-bit counter, the maximum period is * 4096 / 256 = 16 seconds. */ - reg = AT91_WDT_WDRSTEN /* causes watchdog reset */ - /* | AT91_WDT_WDRPROC causes processor reset only */ - | AT91_WDT_WDDBGHLT /* disabled in debug mode */ - | AT91_WDT_WDD /* restart at any time */ - | (timeout & AT91_WDT_WDV); /* timer value */ - at91_sys_write(AT91_WDT_MR, reg); + + reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ + | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */ + | AT91_WDT_MR_WDD(0xfff) /* restart at any time */ + | AT91_WDT_MR_WDV(timeout); /* timer value */ + + writel(reg, &wd->mr); return 0; } void hw_watchdog_reset(void) { - at91_sys_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT); + at91_wdt_t *wd = (at91_wdt_t *) AT91_WDT_BASE; + writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr); } void hw_watchdog_init(void) diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index 680fe33..5b1a85d 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -108,11 +108,12 @@ typedef struct at91_pmc { #define AT91_PMC_IXR_PCKRDY3 0x00000800 #ifdef CONFIG_AT91_LEGACY - #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ +#endif + #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ @@ -128,27 +129,34 @@ typedef struct at91_pmc { #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ +#endif + #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ +#ifdef CONFIG_AT91_LEGACY #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ +#endif #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ - +#ifdef CONFIG_AT91_LEGACY #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ +#endif #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ - +#ifdef CONFIG_AT91_LEGACY #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ +#endif #define AT91_PMC_DIV (0xff << 0) /* Divider */ #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ @@ -160,7 +168,9 @@ typedef struct at91_pmc { #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ #define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ +#endif #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ #define AT91_PMC_CSS_SLOW (0 << 0) #define AT91_PMC_CSS_MAIN (1 << 0) @@ -188,11 +198,13 @@ typedef struct at91_pmc { #define AT91_PMC_PDIV_1 (0 << 12) #define AT91_PMC_PDIV_2 (1 << 12) +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ +#endif #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ @@ -203,12 +215,13 @@ typedef struct at91_pmc { #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ #define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ +#endif #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ - +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ - #endif /* CONFIG_AT91_LEGACY */ #endif diff --git a/include/asm-arm/arch-s5pc1xx/clk.h b/include/asm-arm/arch-s5pc1xx/clk.h index f1aa44f..3e59abe 100644 --- a/include/asm-arm/arch-s5pc1xx/clk.h +++ b/include/asm-arm/arch-s5pc1xx/clk.h @@ -23,6 +23,12 @@ #ifndef __ASM_ARM_ARCH_CLK_H_ #define __ASM_ARM_ARCH_CLK_H_ +#define APLL 0 +#define MPLL 1 +#define EPLL 2 +#define HPLL 3 +#define VPLL 4 + void s5pc1xx_clock_init(void); extern unsigned long (*get_pll_clk)(int pllreg); diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h index afbc7ea..8e4bb86 100644 --- a/include/asm-arm/arch-s5pc1xx/gpio.h +++ b/include/asm-arm/arch-s5pc1xx/gpio.h @@ -124,6 +124,35 @@ struct s5pc110_gpio { struct s5pc1xx_gpio_bank gpio_h2; struct s5pc1xx_gpio_bank gpio_h3; }; + +/* functions */ +void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg); +void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en); +void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio); +void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en); +unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio); +void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); +void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); +void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); #endif +/* Pin configurations */ +#define GPIO_INPUT 0x0 +#define GPIO_OUTPUT 0x1 +#define GPIO_IRQ 0xf +#define GPIO_FUNC(x) (x) + +/* Pull mode */ +#define GPIO_PULL_NONE 0x0 +#define GPIO_PULL_DOWN 0x1 +#define GPIO_PULL_UP 0x2 + +/* Drive Strength level */ +#define GPIO_DRV_1X 0x0 +#define GPIO_DRV_2X 0x1 +#define GPIO_DRV_3X 0x2 +#define GPIO_DRV_4X 0x3 +#define GPIO_DRV_FAST 0x0 +#define GPIO_DRV_SLOW 0x1 + #endif diff --git a/include/asm-arm/arch-s5pc1xx/smc.h b/include/asm-arm/arch-s5pc1xx/smc.h new file mode 100644 index 0000000..88f4ffe --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/smc.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Naveen Krishna Ch <ch.naveen@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: This file contains the register description for Memory subsystem + * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. + * + * Only SROMC is defined as of now + */ + +#ifndef __ASM_ARCH_SMC_H_ +#define __ASM_ARCH_SMC_H_ + +#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) +#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ + /* 1-> Byte base address*/ +#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) +#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) + +#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ +#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ +#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ +#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ +#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ +#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ +#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ + +#ifndef __ASSEMBLY__ +struct s5pc1xx_smc { + unsigned int bw; + unsigned int bc[6]; +}; +#endif /* __ASSEMBLY__ */ + +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ +void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf); + +#endif /* __ASM_ARCH_SMC_H_ */ diff --git a/include/asm-nios2/bitops.h b/include/asm-nios2/bitops.h index 5776bda..cf48ff7 100644 --- a/include/asm-nios2/bitops.h +++ b/include/asm-nios2/bitops.h @@ -24,15 +24,9 @@ #ifndef __ASM_NIOS2_BITOPS_H_ #define __ASM_NIOS2_BITOPS_H_ - -extern void set_bit(int nr, volatile void * a); -extern void clear_bit(int nr, volatile void * a); -extern int test_and_clear_bit(int nr, volatile void * a); -extern void change_bit(unsigned long nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void * a); -extern int test_and_change_bit(int nr, volatile void * addr); -extern int test_bit(int nr, volatile void * a); -extern int ffs(int i); -#define PLATFORM_FFS +/* copied from linux-2.6/include/asm-generic/bitops */ +#include <asm/bitops/atomic.h> +#include <asm/bitops/non-atomic.h> +#include <asm/bitops/ffs.h> #endif /* __ASM_NIOS2_BITOPS_H */ diff --git a/include/asm-nios2/bitops/atomic.h b/include/asm-nios2/bitops/atomic.h new file mode 100644 index 0000000..c894646 --- /dev/null +++ b/include/asm-nios2/bitops/atomic.h @@ -0,0 +1,189 @@ +#ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_ +#define _ASM_GENERIC_BITOPS_ATOMIC_H_ + +#include <asm/types.h> +#include <asm/system.h> + +#ifdef CONFIG_SMP +#include <asm/spinlock.h> +#include <asm/cache.h> /* we use L1_CACHE_BYTES */ + +/* Use an array of spinlocks for our atomic_ts. + * Hash function to index into a different SPINLOCK. + * Since "a" is usually an address, use one spinlock per cacheline. + */ +# define ATOMIC_HASH_SIZE 4 +# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ])) + +extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; + +/* Can't use raw_spin_lock_irq because of #include problems, so + * this is the substitute */ +#define _atomic_spin_lock_irqsave(l,f) do { \ + raw_spinlock_t *s = ATOMIC_HASH(l); \ + local_irq_save(f); \ + __raw_spin_lock(s); \ +} while(0) + +#define _atomic_spin_unlock_irqrestore(l,f) do { \ + raw_spinlock_t *s = ATOMIC_HASH(l); \ + __raw_spin_unlock(s); \ + local_irq_restore(f); \ +} while(0) + + +#else +# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0) +# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0) +#endif + +/* + * NMI events can occur at any time, including when interrupts have been + * disabled by *_irqsave(). So you can get NMI events occurring while a + * *_bit function is holding a spin lock. If the NMI handler also wants + * to do bit manipulation (and they do) then you can get a deadlock + * between the original caller of *_bit() and the NMI handler. + * + * by Keith Owens + */ + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * This function is atomic and may not be reordered. See __set_bit() + * if you do not require the atomic guarantees. + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p |= mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * clear_bit() is atomic and may not be reordered. However, it does + * not contain a memory barrier, so if it is used for locking purposes, + * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * in order to ensure changes are visible on other processors. + */ +static inline void clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p &= ~mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * change_bit - Toggle a bit in memory + * @nr: Bit to change + * @addr: Address to start counting from + * + * change_bit() is atomic and may not be reordered. It may be + * reordered on other architectures than x86. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p ^= mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It may be reordered on other architectures than x86. + * It also implies a memory barrier. + */ +static inline int test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old | mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +/** + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It can be reorderdered on other architectures other than x86. + * It also implies a memory barrier. + */ +static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old & ~mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +/** + * test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static inline int test_and_change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old ^ mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +#endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */ diff --git a/include/asm-nios2/bitops/ffs.h b/include/asm-nios2/bitops/ffs.h new file mode 100644 index 0000000..fbbb43a --- /dev/null +++ b/include/asm-nios2/bitops/ffs.h @@ -0,0 +1,41 @@ +#ifndef _ASM_GENERIC_BITOPS_FFS_H_ +#define _ASM_GENERIC_BITOPS_FFS_H_ + +/** + * ffs - find first bit set + * @x: the word to search + * + * This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ +static inline int ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} + +#endif /* _ASM_GENERIC_BITOPS_FFS_H_ */ diff --git a/include/asm-nios2/bitops/non-atomic.h b/include/asm-nios2/bitops/non-atomic.h new file mode 100644 index 0000000..697cc2b --- /dev/null +++ b/include/asm-nios2/bitops/non-atomic.h @@ -0,0 +1,108 @@ +#ifndef _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ +#define _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ + +#include <asm/types.h> + +/** + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p |= mask; +} + +static inline void __clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p &= ~mask; +} + +/** + * __change_bit - Toggle a bit in memory + * @nr: the bit to change + * @addr: the address to start counting from + * + * Unlike change_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p ^= mask; +} + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old | mask; + return (old & mask) != 0; +} + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old & ~mask; + return (old & mask) != 0; +} + +/* WARNING: non atomic and it can be reordered! */ +static inline int __test_and_change_bit(int nr, + volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old ^ mask; + return (old & mask) != 0; +} + +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static inline int test_bit(int nr, const volatile unsigned long *addr) +{ + return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); +} + +#endif /* _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ */ diff --git a/include/asm-nios2/errno.h b/include/asm-nios2/errno.h new file mode 100644 index 0000000..4c82b50 --- /dev/null +++ b/include/asm-nios2/errno.h @@ -0,0 +1 @@ +#include <asm-generic/errno.h> diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h index 01d11ef..121405c 100644 --- a/include/asm-nios2/io.h +++ b/include/asm-nios2/io.h @@ -80,19 +80,19 @@ extern unsigned inl (unsigned port); ({unsigned long val;\ asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) -#define writeb(addr,val)\ - asm volatile ("stbio %1, 0(%0)" : : "r" (addr), "r" (val)) -#define writew(addr,val)\ - asm volatile ("sthio %1, 0(%0)" : : "r" (addr), "r" (val)) -#define writel(addr,val)\ - asm volatile ("stwio %1, 0(%0)" : : "r" (addr), "r" (val)) +#define writeb(val,addr)\ + asm volatile ("stbio %0, 0(%1)" : : "r" (val), "r" (addr)) +#define writew(val,addr)\ + asm volatile ("sthio %0, 0(%1)" : : "r" (val), "r" (addr)) +#define writel(val,addr)\ + asm volatile ("stwio %0, 0(%1)" : : "r" (val), "r" (addr)) #define inb(addr) readb(addr) #define inw(addr) readw(addr) #define inl(addr) readl(addr) -#define outb(addr,val) writeb(addr,val) -#define outw(addr,val) writew(addr,val) -#define outl(addr,val) writel(addr,val) +#define outb(val, addr) writeb(val,addr) +#define outw(val, addr) writew(val,addr) +#define outl(val, addr) writel(val,addr) static inline void insb (unsigned long port, void *dst, unsigned long count) { diff --git a/include/asm-nios2/system.h b/include/asm-nios2/system.h index ec84f59..bb03ca5 100644 --- a/include/asm-nios2/system.h +++ b/include/asm-nios2/system.h @@ -23,4 +23,37 @@ #ifndef __ASM_NIOS2_SYSTEM_H_ #define __ASM_NIOS2_SYSTEM_H_ +#define local_irq_enable() __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "ori r8, r8, 1\n" \ + "wrctl status, r8\n" \ + : : : "r8") + +#define local_irq_disable() __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "andi r8, r8, 0xfffe\n" \ + "wrctl status, r8\n" \ + : : : "r8") + +#define local_save_flags(x) __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "mov %0, r8\n" \ + : "=r" (x) : : "r8", "memory") + +#define local_irq_restore(x) __asm__ __volatile__ ( \ + "mov r8, %0\n" \ + "wrctl status, r8\n" \ + : : "r" (x) : "r8", "memory") + +/* For spinlocks etc */ +#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } \ + while (0) + +#define irqs_disabled() \ +({ \ + unsigned long flags; \ + local_save_flags(flags); \ + ((flags & NIOS2_STATUS_PIE_MSK) == 0x0); \ +}) + #endif /* __ASM_NIOS2_SYSTEM_H */ diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index 0d78aa4..fc3facb 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -41,6 +41,7 @@ #endif #if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ + defined(CONFIG_P1021) || defined(CONFIG_P1022) || \ defined(CONFIG_P2020) || defined(CONFIG_MPC8641) #define CONFIG_MAX_CPUS 2 #elif defined(CONFIG_PPC_P4080) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 9b3d616..9ec319a 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -265,6 +265,7 @@ #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ #define HID1_ASTME (1<<13) /* Address bus streaming mode */ #define HID1_ABE (1<<12) /* Address broadcast enable */ +#define HID1_MBDD (1<<6) /* optimized sync instruction */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ @@ -533,6 +534,9 @@ #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ +#define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */ +#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */ +#define BUCSR_ENABLE (BUCSR_BBFI|BUCSR_BPEN) #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ #define SPRN_PID1 0x279 /* Process ID Register 1 */ @@ -1032,8 +1036,16 @@ #define SVR_8572_E 0x80E800 #define SVR_P1011 0x80E500 #define SVR_P1011_E 0x80ED00 +#define SVR_P1012 0x80E501 +#define SVR_P1012_E 0x80ED01 +#define SVR_P1013 0x80E700 +#define SVR_P1013_E 0x80EF00 #define SVR_P1020 0x80E400 #define SVR_P1020_E 0x80EC00 +#define SVR_P1021 0x80E401 +#define SVR_P1021_E 0x80EC01 +#define SVR_P1022 0x80E600 +#define SVR_P1022_E 0x80EE00 #define SVR_P2010 0x80E300 #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index 058fdf1..746bf18 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -15,6 +15,7 @@ #define CONFIG_CMD_AMBAPP /* AMBA Plug & Play Bus print utility */ #define CONFIG_CMD_ASKENV /* ask for env variable */ +#define CONFIG_CMD_AT91_SPIMUX /* AT91 MMC/SPI Mux Support */ #define CONFIG_CMD_BDI /* bdinfo */ #define CONFIG_CMD_BEDBUG /* Include BedBug Debugger */ #define CONFIG_CMD_BMP /* BMP support */ @@ -33,7 +34,6 @@ #define CONFIG_CMD_EDITENV /* editenv */ #define CONFIG_CMD_EEPROM /* EEPROM read/write support */ #define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */ -#define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_FDC /* Floppy Disk Support */ @@ -55,6 +55,7 @@ #define CONFIG_CMD_LOADS /* loads */ #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ #define CONFIG_CMD_MFSL /* FSL support for Microblaze */ +#define CONFIG_CMD_MG_DISK /* mGine m(g)flash IO node support */ #define CONFIG_CMD_MII /* MII support */ #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ #define CONFIG_CMD_MMC /* MMC support */ @@ -70,6 +71,7 @@ #define CONFIG_CMD_REGINFO /* Register dump */ #define CONFIG_CMD_REISER /* Reiserfs support */ #define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_SAVES /* save S record dump */ #define CONFIG_CMD_SCSI /* SCSI Support */ #define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */ @@ -79,12 +81,12 @@ #define CONFIG_CMD_SOURCE /* "source" command support */ #define CONFIG_CMD_SPI /* SPI utility */ #define CONFIG_CMD_TERMINAL /* built-in Serial Terminal */ +#define CONFIG_CMD_UBI /* UBI Support */ +#define CONFIG_CMD_UBIFS /* UBIFS Support */ #define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */ #define CONFIG_CMD_UNZIP /* unzip from memory to memory */ #define CONFIG_CMD_USB /* USB Support */ #define CONFIG_CMD_VFD /* VFD support (TRAB) */ #define CONFIG_CMD_XIMG /* Load part of Multi Image */ -#define CONFIG_CMD_AT91_SPIMUX /* AT91 MMC/SPI Mux Support */ -#define CONFIG_CMD_MG_DISK /* mGine m(g)flash IO node support */ #endif /* _CONFIG_CMD_ALL_H */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 5cb0f1e..4cb8052 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -244,6 +244,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index e3e6e75..cdba81d 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -173,6 +173,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index ae8494d..2b6786b 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -224,6 +224,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 5c88c47..9221211 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -207,6 +207,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index d131aea..3e7020d 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -256,6 +256,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 07c4e35..d3000f6 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -283,6 +283,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index c78552b..d376344 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -259,6 +259,7 @@ * I2C EEPROM (CAT24WC32) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 59e0778..07acab0 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -278,6 +278,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index b2679e5..5b50bcf 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -189,6 +189,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index 96bf161..9ab30ec 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -65,6 +65,7 @@ #define CONFIG_ETHADDR 00:40:a6:80:14:5 */ #define CONFIG_HARD_I2C 1 /* hardware support for i2c */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SDRAM_BANK0 1 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 49ecb6f..4423f2a 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -174,6 +174,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DU405.h b/include/configs/DU405.h index cfb3023..8f1fc78 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -212,6 +212,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 65dc235..830466f 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -169,6 +169,7 @@ */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_I2C_MULTI_BUS 1 diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h index 61d8e20..3920d35 100644 --- a/include/configs/EP1C20.h +++ b/include/configs/EP1C20.h @@ -94,7 +94,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ @@ -123,14 +124,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h index 41e64e6..bfbf8c1 100644 --- a/include/configs/EP1S10.h +++ b/include/configs/EP1S10.h @@ -92,7 +92,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ @@ -118,14 +119,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h index 5b332e4..4d905fe 100644 --- a/include/configs/EP1S40.h +++ b/include/configs/EP1S40.h @@ -92,7 +92,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ @@ -118,14 +119,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec) */ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index 023f33e..e07f9a1 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -54,6 +54,7 @@ #endif /* total size of a X1240 is 2048 bytes */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/G2000.h b/include/configs/G2000.h index 6819c3e..d2883eb 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -295,6 +295,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 9233523..01e0bc6 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -331,6 +331,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #if 0 /* test-only */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #else diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index ea502d4..8c6d5ed 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -244,6 +244,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 80c70e4..98f5661 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -217,6 +217,7 @@ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 4b67c94..49a7378 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -132,6 +132,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C hardware support */ #undef CONFIG_SOFT_I2C /* I2C !bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 518173a..e7429dd 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -194,6 +194,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C hardware support */ #undef CONFIG_SOFT_I2C /* I2C !bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 7ac9342..7e6484e 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -97,6 +97,7 @@ ***************************************************************/ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 87901b3..da4313a 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -413,6 +413,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 9b81703..0c43b2b 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -284,6 +284,9 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index fed441e..8382e3c 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -177,7 +177,7 @@ #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/ +#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h new file mode 100644 index 0000000..6492068 --- /dev/null +++ b/include/configs/MVSMR.h @@ -0,0 +1,295 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2010 + * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <version.h> + +#define CONFIG_MPC5xxx 1 +#define CONFIG_MPC5200 1 + +#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 + +#define BOOTFLAG_COLD 0x01 +#define BOOTFLAG_WARM 0x02 + +#define CONFIG_MISC_INIT_R 1 + +#define CONFIG_SYS_CACHELINE_SIZE 32 +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CACHELINE_SHIFT 5 +#endif + +#define CONFIG_PSC_CONSOLE 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200,\ + 230400} + +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#undef CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_SYS_XLB_PIPELINING 1 +#define CONFIG_HIGH_BATS 1 + +#define MV_CI mvSMR +#define MV_VCI mvSMR +#define MV_FPGA_DATA 0xff840000 +#define MV_FPGA_SIZE 0x1ff88 +#define MV_KERNEL_ADDR 0xfff00000 +#define MV_SCRIPT_ADDR 0xff806000 +#define MV_INITRD_ADDR 0xff880000 +#define MV_INITRD_LENGTH 0x00240000 +#define MV_SCRATCH_ADDR 0xffcc0000 +#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH + +#define CONFIG_SHOW_BOOT_PROGRESS 1 + +#define MV_KERNEL_ADDR_RAM 0x00100000 +#define MV_INITRD_ADDR_RAM 0x00400000 + +/* + * Supported commands + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SDRAM + +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_NTPSERVER +#define CONFIG_BOOTP_RANDOM_DELAY +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_VENDOREX + +/* + * Autoboot + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "abcdefg" +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_BOOTCOMMAND "source ${script_addr}" +#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \ + " allocate=6M" + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console_nr=0\0" \ + "console=no\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "fpga=0\0" \ + "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \ + "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \ + "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \ + "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \ + "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \ + "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \ + "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \ + "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \ + "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \ + "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \ + "mv_version=" U_BOOT_VERSION "\0" \ + "dhcp_client_id=" MK_STR(MV_CI) "\0" \ + "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \ + "netretry=no\0" \ + "use_static_ipaddr=no\0" \ + "static_ipaddr=192.168.0.101\0" \ + "static_netmask=255.255.255.0\0" \ + "static_gateway=0.0.0.0\0" \ + "initrd_name=uInitrd.mvsmr-rfs\0" \ + "zcip=yes\0" \ + "netboot=no\0" \ + "" + +#undef XMK_STR +#undef MK_STR + +/* + * IPB Bus clocking configuration. + */ +#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK + +/* + * Flash configuration + */ +#undef CONFIG_FLASH_16BIT +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#define CONFIG_SYS_FLASH_ERASE_TOUT 50000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_SYS_LOWBOOT +#define CONFIG_SYS_FLASH_BASE TEXT_BASE +#define CONFIG_SYS_FLASH_SIZE 0x00800000 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_IN_FLASH +#undef CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_HAS_UID +#define CONFIG_OVERWRITE_ETHADDR_ONCE + +#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x2000 + +/* used by linker script to wrap code around */ +#define CONFIG_SCRIPT_OFFSET 0x6000 +#define CONFIG_SCRIPT_SECT_SIZE 0x2000 + +/* + * Memory map + */ +#define CONFIG_SYS_MBAR 0xF0000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 + +#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM +#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE + +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT 1 +#endif + +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (512 << 10) +#define CONFIG_SYS_MALLOC_LEN (512 << 10) +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_MODULE 1 +#define CONFIG_SYS_I2C_SPEED 86000 +#define CONFIG_SYS_I2C_SLAVE 0x7F + +/* + * Ethernet configuration + */ +#define CONFIG_NET_RETRY_COUNT 5 + +#define CONFIG_MPC5xxx_FEC +#define CONFIG_MPC5xxx_FEC_MII100 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_NETDEV eth0 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#undef CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 +#else +#define CONFIG_SYS_CBSIZE 256 +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x00800000 +#define CONFIG_SYS_MEMTEST_END 0x02f00000 + +#define CONFIG_SYS_HZ 1000 + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x02000000 +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 0x00200000 + +/* + * Various low-level settings + */ +#define CONFIG_SYS_GPS_PORT_CONFIG 0x00050044 + +#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI) +#define CONFIG_SYS_HID0_FINAL HID0_ICE + +#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE +#define CONFIG_SYS_BOOTCS_CFG 0x00047800 +#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE + +#define CONFIG_SYS_CS_BURST 0x000000f0 +#define CONFIG_SYS_CS_DEADCYCLE 0x33333303 + +#define CONFIG_SYS_RESET_ADDRESS 0x00000100 + +#undef FPGA_DEBUG +#undef CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_FPGA CONFIG_SYS_XILINX_SPARTAN2 +#define CONFIG_FPGA_XILINX 1 +#define CONFIG_FPGA_SPARTAN2 1 +#define CONFIG_FPGA_COUNT 1 + +#endif diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 860ec52..55471af 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -210,6 +210,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index b2e2d41..1424713 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -208,6 +208,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 405e6d5..a9b4004 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -286,6 +286,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 30a5a31..66be725 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -238,7 +238,9 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ -#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#ifdef CONFIG_FSL_NGPIXIS #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ #ifdef CONFIG_PHYS_64BIT #define PIXIS_BASE_PHYS 0xfffdf0000ull @@ -249,59 +251,11 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ -#define PIXIS_ID 0x0 /* Board ID at offset 0 */ -#define PIXIS_VER 0x1 /* Board version at offset 1 */ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ -#define PIXIS_CSR 0x3 /* PIXIS General control/status register */ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ -#define PIXIS_PWR 0x5 /* PIXIS Power status register */ -#define PIXIS_AUX 0x6 /* Auxiliary 1 register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VSTAT 0x11 /* VELA Status Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ -#define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */ -#define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */ -#define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */ -#define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */ -#define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */ -#define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */ - -#define PIXIS_VWATCH 0x24 /* Watchdog Register */ -#define PIXIS_LED 0x25 /* LED Register */ - -#define PIXIS_SW(x) 0x20 + (x - 1) * 2 -#define PIXIS_EN(x) 0x21 + (x - 1) * 2 -#define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */ -#define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */ - -/* old pixis referenced names */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 -#define PIXIS_VSPEED2_TSEC1SER 0x8 -#define PIXIS_VSPEED2_TSEC2SER 0x4 -#define PIXIS_VSPEED2_TSEC3SER 0x2 -#define PIXIS_VSPEED2_TSEC4SER 0x1 -#define PIXIS_VCFGEN1_TSEC1SER 0x20 -#define PIXIS_VCFGEN1_TSEC2SER 0x20 -#define PIXIS_VCFGEN1_TSEC3SER 0x20 -#define PIXIS_VCFGEN1_TSEC4SER 0x20 -#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ - | PIXIS_VSPEED2_TSEC2SER \ - | PIXIS_VSPEED2_TSEC3SER \ - | PIXIS_VSPEED2_TSEC4SER) -#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ - | PIXIS_VCFGEN1_TSEC2SER \ - | PIXIS_VCFGEN1_TSEC3SER \ - | PIXIS_VCFGEN1_TSEC4SER) +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xf0 +#define PIXIS_LBMAP_SHIFT 4 +#define PIXIS_LBMAP_ALTBANK 0x20 +#endif #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 4e39799..0d443ea 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -204,6 +204,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h index 831a60d..c60a9f7 100644 --- a/include/configs/PCI5441.h +++ b/include/configs/PCI5441.h @@ -92,7 +92,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x009208a0 /* UART base addr */ @@ -113,14 +114,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /* diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 962b29e..3e57c0b 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -86,6 +86,7 @@ * The Atmel EEPROM uses 16Bit addressing. ***************************************************************/ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index cf6f7a9..874c20b 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -94,7 +94,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ @@ -123,14 +124,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period */ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 3d59454..f917eb5 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -278,6 +278,7 @@ * I2C EEPROM (24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 87ea7b6..00a12fb 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -235,6 +235,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 7198632..2c048dd 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -215,6 +215,7 @@ * I2C EEPROM (24W16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 89799af..c2fb56c 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -226,6 +226,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 8e9d928..44f03dc 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -414,6 +414,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 38a1d0d..9c91fcc 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -277,6 +277,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 4717869..871e4c3 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -203,6 +203,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index c017915..f06bfe5 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -273,6 +273,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 1d4ad13..be8c9f8 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -280,6 +280,7 @@ * I2C EEPROM (ATMEL 24C04N) */ #define CONFIG_HARD_I2C 1 /* Hardware assisted I2C */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 5c281a1..be9ac62 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -241,6 +241,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/XPEDITE1000.h b/include/configs/XPEDITE1000.h index 658e947..cf39aea 100644 --- a/include/configs/XPEDITE1000.h +++ b/include/configs/XPEDITE1000.h @@ -141,6 +141,7 @@ extern void out32(unsigned int, unsigned long); * I2C */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7f #define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 0fed9ad..f2392f6 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -118,6 +118,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 8cd97b8..13a941e 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -40,6 +40,7 @@ * I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* diff --git a/include/configs/csb272.h b/include/configs/csb272.h index aed6f50..9ded330 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -171,6 +171,7 @@ * */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 24b961f..71eb083 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -170,6 +170,7 @@ * */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ diff --git a/include/configs/korat.h b/include/configs/korat.h index 026dd08..f95df68 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -153,6 +153,7 @@ */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 011dd5c..6461124 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -258,6 +258,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/meesc.h b/include/configs/meesc.h index d002b97..e085f4a 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -82,7 +82,6 @@ */ #include <config_cmd_default.h> #undef CONFIG_CMD_BDI -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h index 4bed7ae..cb7efe7 100644 --- a/include/configs/netstal-common.h +++ b/include/configs/netstal-common.h @@ -42,6 +42,7 @@ * I2C */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/otc570.h b/include/configs/otc570.h index 4fde012..fb0f576 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -131,7 +131,6 @@ * Command line configuration. */ #include <config_cmd_default.h> -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 729ca6a..d6b9207 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -92,6 +92,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 000ae5c..1f744b8 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -138,6 +138,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index b08dcd4..403837e 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -150,6 +150,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index 242f42f..429b11c 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -166,6 +166,7 @@ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/sc3.h b/include/configs/sc3.h index a5eca39..d00f248 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -251,6 +251,7 @@ */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define I2C_INIT #define I2C_ACTIVE 0 diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index a8ba052..09bce6d 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -83,7 +83,6 @@ #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS #undef CONFIG_CMD_NAND -#undef CONFIG_CMD_NET #define CONFIG_CMD_CACHE #define CONFIG_CMD_REGINFO @@ -235,4 +234,15 @@ #define CONFIG_DOS_PARTITION 1 +/* + * Ethernet Contoller driver + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X 1 /* we have a SMC9115 on-board */ +#define CONFIG_SMC911X_16_BIT 1 /* SMC911X_16_BIT Mode */ +#define CONFIG_SMC911X_BASE 0x98800300 /* SMC911X Drive Base */ +#define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ +#endif /* CONFIG_CMD_NET */ + #endif /* __CONFIG_H */ diff --git a/include/configs/zeus.h b/include/configs/zeus.h index 1a77c71..3b2aede 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -167,6 +167,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/fdt_support.h b/include/fdt_support.h index a3d5f8c..9a453af 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -82,6 +82,7 @@ int fdt_resize(void *blob); int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size); void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size); +void fdt_del_node_and_alias(void *blob, const char *alias); #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 01b7dec..f9ae15a 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -2,7 +2,7 @@ * FSL SD/MMC Defines *------------------------------------------------------------------- * - * Copyright 2007-2008, Freescale Semiconductor, Inc + * Copyright 2007-2008,2010 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -39,6 +39,7 @@ #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 +#define SYSCTL_RSTA 0x01000000 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) @@ -132,6 +133,8 @@ #define WML 0x2e044 #define WML_WRITE 0x00010000 +#define WML_RD_WML_MASK 0xff +#define WML_WR_WML_MASK 0xff0000 #define BLKATTR 0x2e004 #define BLKATTR_CNT(x) ((x & 0xffff) << 16) @@ -148,7 +151,6 @@ struct fsl_esdhc_cfg { u32 esdhc_base; u32 no_snoop; - u32 clk_enable; }; /* Select the correct accessors depending on endianess */ diff --git a/include/linux/stat.h b/include/linux/stat.h index 2ce1c25..cef6369 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -68,7 +68,7 @@ struct stat { #endif /* __PPC__ */ #if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\ - defined (__microblaze__) + defined (__microblaze__) || defined (__nios2__) struct stat { unsigned short st_dev; diff --git a/lib_nios2/board.c b/lib_nios2/board.c index 41d3297..8ec66a3 100644 --- a/lib_nios2/board.c +++ b/lib_nios2/board.c @@ -139,6 +139,13 @@ void board_init (void) board_late_init (); #endif +#if defined(CONFIG_CMD_NET) +#if defined(CONFIG_NET_MULTI) + puts ("Net: "); +#endif + eth_initialize (bd); +#endif + /* main_loop */ for (;;) { WATCHDOG_RESET (); diff --git a/lib_nios2/bootm.c b/lib_nios2/bootm.c index 675bfac..5d25edf 100644 --- a/lib_nios2/bootm.c +++ b/lib_nios2/bootm.c @@ -26,21 +26,26 @@ #include <asm/byteorder.h> #include <asm/cache.h> +#define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */ + int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) { - void (*kernel)(void) = (void (*)(void))images->ep; + void (*kernel)(int, int, int, char *) = (void *)images->ep; + char *commandline = getenv("bootargs"); + ulong initrd_start = images->rd_start; + ulong initrd_end = images->rd_end; if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1; /* flushes data and instruction caches before calling the kernel */ - flush_dcache (0,CONFIG_SYS_DCACHE_SIZE); - flush_icache (0,CONFIG_SYS_ICACHE_SIZE); + disable_interrupts(); + flush_dcache((ulong)kernel, CONFIG_SYS_DCACHE_SIZE); + flush_icache((ulong)kernel, CONFIG_SYS_ICACHE_SIZE); - /* For now we assume the Microtronix linux ... which only - * needs to be called ;-) - */ - kernel (); + debug("bootargs=%s @ 0x%lx\n", commandline, (ulong)&commandline); + debug("initrd=0x%lx-0x%lx\n", (ulong)initrd_start, (ulong)initrd_end); + kernel(NIOS_MAGIC, initrd_start, initrd_end, commandline); /* does not return */ return 1; diff --git a/tools/mkimage.c b/tools/mkimage.c index 5c3e872..f5859d7 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -145,7 +145,7 @@ main (int argc, char **argv) { int ifd = -1; struct stat sbuf; - unsigned char *ptr; + char *ptr; int retval = 0; struct image_type_params *tparams = NULL; @@ -201,8 +201,7 @@ main (int argc, char **argv) case 'a': if (--argc <= 0) usage (); - params.addr = strtoul (*++argv, - (char **)&ptr, 16); + params.addr = strtoul (*++argv, &ptr, 16); if (*ptr) { fprintf (stderr, "%s: invalid load address %s\n", @@ -219,8 +218,7 @@ main (int argc, char **argv) case 'e': if (--argc <= 0) usage (); - params.ep = strtoul (*++argv, - (char **)&ptr, 16); + params.ep = strtoul (*++argv, &ptr, 16); if (*ptr) { fprintf (stderr, "%s: invalid entry point %s\n", |