diff options
1228 files changed, 45332 insertions, 7392 deletions
@@ -58,6 +58,14 @@ config CC_OPTIMIZE_FOR_SIZE endmenu # General setup +menuconfig EXPERT + bool "Configure standard U-Boot features (expert users)" + help + This option allows certain base U-Boot options and settings + to be disabled or tweaked. This is for specialized + environments which can tolerate a "non-standard" U-Boot. + Only use this if you really know what you are doing. + menu "Boot images" config SPL_BUILD @@ -93,6 +101,28 @@ config TPL help If you want to build TPL as well as the normal image and SPL, say Y. +config FIT + bool "Support Flattened Image Tree" + depends on !SPL_BUILD + help + This option allows to boot the new uImage structrure, + Flattened Image Tree. FIT is formally a FDT, which can include + images of various types (kernel, FDT blob, ramdisk, etc.) + in a single blob. To boot this new uImage structure, + pass the the address of the blob to the "bootm" command. + +config FIT_VERBOSE + bool "Display verbose messages on FIT boot" + depends on FIT + +config FIT_SIGNATURE + bool "Enabel signature verification of FIT uImages" + depends on FIT + help + This option enables signature verification of FIT uImages, + using a hash signed and verified using RSA. + See doc/uImage.FIT/signature.txt for more details. + config SYS_EXTRA_OPTIONS string "Extra Options (DEPRECATED)" depends on !SPL_BUILD diff --git a/MAINTAINERS b/MAINTAINERS index c8386ab..6041936 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -128,6 +128,12 @@ T: git git://git.denx.de/u-boot-stm.git F: arch/arm/cpu/arm926ejs/spear/ F: arch/arm/include/asm/arch-spear/ +ARM STM STV0991 +M: Vikas Manocha <vikas.manocha@st.com> +S: Maintained +F: arch/arm/cpu/armv7/stv0991/ +F: arch/arm/include/asm/arch-stv0991/ + ARM SUNXI M: Ian Campbell <ijc@hellion.org.uk> M: Hans De Goede <hdegoede@redhat.com> @@ -196,7 +202,8 @@ F: drivers/mtd/cfi_flash.c F: drivers/mtd/jedec_flash.c COLDFIRE -M: Jason Jin <jason.jin@freescale.com> +M: Huan Wang <alison.wang@freescale.com> +M: Angelo Dureghello <angelo@sysam.it> S: Maintained T: git git://git.denx.de/u-boot-coldfire.git F: arch/m68k/ @@ -390,6 +397,7 @@ T: git git://git.denx.de/u-boot-tq-group.git UBI M: Kyungmin Park <kmpark@infradead.org> +M: Heiko Schocher <hs@denx.de> S: Maintained T: git git://git.denx.de/u-boot-ubi.git F: drivers/mtd/ubi/ @@ -1,7 +1,7 @@ VERSION = 2015 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* @@ -503,6 +503,7 @@ autoconf_is_current := $(if $(wildcard $(KCONFIG_CONFIG)),$(shell find . \ -path ./include/config/auto.conf -newer $(KCONFIG_CONFIG))) ifneq ($(autoconf_is_current),) include $(srctree)/config.mk +include $(srctree)/arch/$(ARCH)/Makefile endif # If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use @@ -601,20 +602,11 @@ c_flags := $(KBUILD_CFLAGS) $(cpp_flags) ######################################################################### # U-Boot objects....order is important (i.e. start must be first) -head-y := $(CPUDIR)/start.o -head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o -head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o - HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n) libs-y += lib/ libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ -libs-y += $(CPUDIR)/ -ifdef SOC -libs-y += $(CPUDIR)/$(SOC)/ -endif libs-$(CONFIG_OF_EMBED) += dts/ -libs-y += arch/$(ARCH)/lib/ libs-y += fs/ libs-y += net/ libs-y += disk/ @@ -648,23 +640,11 @@ libs-y += drivers/usb/musb-new/ libs-y += drivers/usb/phy/ libs-y += drivers/usb/ulpi/ libs-y += common/ -libs-y += lib/libfdt/ libs-$(CONFIG_API) += api/ libs-$(CONFIG_HAS_POST) += post/ libs-y += test/ libs-y += test/dm/ -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610)) -libs-y += arch/$(ARCH)/imx-common/ -endif - -ifneq (,$(filter $(SOC), armada-xp kirkwood)) -libs-y += arch/$(ARCH)/mvebu-common/ -endif - -libs-$(CONFIG_ARM) += arch/arm/cpu/ -libs-$(CONFIG_PPC) += arch/powerpc/cpu/ - libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/) libs-y := $(sort $(libs-y)) @@ -749,6 +729,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) endif ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf +# We can't do this yet due to the need for binary blobs +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom + # enable combined SPL/u-boot/dtb rules for tegra ifneq ($(CONFIG_TEGRA),) ifeq ($(CONFIG_SPL),y) @@ -817,7 +800,8 @@ OBJCOPYFLAGS_u-boot.srec := -O srec u-boot.hex u-boot.srec: u-boot FORCE $(call if_changed,objcopy) -OBJCOPYFLAGS_u-boot.bin := -O binary +OBJCOPYFLAGS_u-boot.bin := -O binary \ + $(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec) binary_size_check: u-boot.bin FORCE @file_size=$(shell wc -c u-boot.bin | awk '{print $$1}') ; \ @@ -956,6 +940,39 @@ u-boot-nand.gph: u-boot.bin FORCE $(call if_changed,mkimage) @dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@ +# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including +# reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in +# the middle. +ifneq ($(CONFIG_X86_RESET_VECTOR),) +rom: u-boot.rom FORCE + +u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \ + $(srctree)/board/$(BOARDDIR)/mrc.bin + $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) u-boot.tmp + if [ -n "$(CONFIG_HAVE_INTEL_ME)" ]; then \ + $(objtree)/tools/ifdtool -D \ + $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp; \ + $(objtree)/tools/ifdtool \ + -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp; \ + fi + $(objtree)/tools/ifdtool -w \ + $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp + $(objtree)/tools/ifdtool -w \ + $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \ + u-boot.tmp + $(objtree)/tools/ifdtool -w \ + $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \ + u-boot.tmp + $(objtree)/tools/ifdtool -w \ + $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME) \ + u-boot.tmp + mv u-boot.tmp $@ + +OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec +u-boot-x86-16bit.bin: u-boot FORCE + $(call if_changed,objcopy) +endif + ifneq ($(CONFIG_SUNXI),) OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \ --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff @@ -982,15 +999,22 @@ u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE #concatenated with u-boot binary. It is need by PowerPC SoC having #internal SRAM <= 512KB. MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ - -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage + -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage \ + -A $(ARCH) -a $(CONFIG_SPL_TEXT_BASE) spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) +ifeq ($(ARCH),arm) +UBOOT_BINLOAD := u-boot.img +else +UBOOT_BINLOAD := u-boot.bin +endif + OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ --gap-fill=0xff -u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl u-boot.bin FORCE +u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl $(UBOOT_BINLOAD) FORCE $(call if_changed,pad_cat) # PPC4xx needs the SPL at the end of the image, since the reset vector @@ -409,6 +409,10 @@ The following options need to be configured: Enables a workaround for IFC erratum A003399. It is only requred during NOR boot. + CONFIG_A008044_WORKAROUND + Enables a workaround for T1040/T1042 erratum A008044. It is only + requred during NAND boot and valid for Rev 1.0 SoC revision + CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY This is the value to write into CCSR offset 0x18600 @@ -623,6 +627,120 @@ The following options need to be configured: exists, unlike the similar options in the Linux kernel. Do not set these options unless they apply! +- Driver Model + Driver model is a new framework for devices in U-Boot + introduced in early 2014. U-Boot is being progressively + moved over to this. It offers a consistent device structure, + supports grouping devices into classes and has built-in + handling of platform data and device tree. + + To enable transition to driver model in a relatively + painful fashion, each subsystem can be independently + switched between the legacy/ad-hoc approach and the new + driver model using the options below. Also, many uclass + interfaces include compatibility features which may be + removed once the conversion of that subsystem is complete. + As a result, the API provided by the subsystem may in fact + not change with driver model. + + See doc/driver-model/README.txt for more information. + + CONFIG_DM + + Enable driver model. This brings in the core support, + including scanning of platform data on start-up. If + CONFIG_OF_CONTROL is enabled, the device tree will be + scanned also when available. + + CONFIG_CMD_DM + + Enable driver model test commands. These allow you to print + out the driver model tree and the uclasses. + + CONFIG_DM_DEMO + + Enable some demo devices and the 'demo' command. These are + really only useful for playing around while trying to + understand driver model in sandbox. + + CONFIG_SPL_DM + + Enable driver model in SPL. You will need to provide a + suitable malloc() implementation. If you are not using the + full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, + consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you + must provide CONFIG_SYS_MALLOC_F_LEN to set the size. + In most cases driver model will only allocate a few uclasses + and devices in SPL, so 1KB should be enable. See + CONFIG_SYS_MALLOC_F_LEN for more details on how to enable + it. + + CONFIG_DM_SERIAL + + Enable driver model for serial. This replaces + drivers/serial/serial.c with the serial uclass, which + implements serial_putc() etc. The uclass interface is + defined in include/serial.h. + + CONFIG_DM_GPIO + + Enable driver model for GPIO access. The standard GPIO + interface (gpio_get_value(), etc.) is then implemented by + the GPIO uclass. Drivers provide methods to query the + particular GPIOs that they provide. The uclass interface + is defined in include/asm-generic/gpio.h. + + CONFIG_DM_SPI + + Enable driver model for SPI. The SPI slave interface + (spi_setup_slave(), spi_xfer(), etc.) is then implemented by + the SPI uclass. Drivers provide methods to access the SPI + buses that they control. The uclass interface is defined in + include/spi.h. The existing spi_slave structure is attached + as 'parent data' to every slave on each bus. Slaves + typically use driver-private data instead of extending the + spi_slave structure. + + CONFIG_DM_SPI_FLASH + + Enable driver model for SPI flash. This SPI flash interface + (spi_flash_probe(), spi_flash_write(), etc.) is then + implemented by the SPI flash uclass. There is one standard + SPI flash driver which knows how to probe most chips + supported by U-Boot. The uclass interface is defined in + include/spi_flash.h, but is currently fully compatible + with the old interface to avoid confusion and duplication + during the transition parent. SPI and SPI flash must be + enabled together (it is not possible to use driver model + for one and not the other). + + CONFIG_DM_CROS_EC + + Enable driver model for the Chrome OS EC interface. This + allows the cros_ec SPI driver to operate with CONFIG_DM_SPI + but otherwise makes few changes. Since cros_ec also supports + I2C and LPC (which don't support driver model yet), a full + conversion is not yet possible. + + + ** Code size options: The following options are enabled by + default except in SPL. Enable them explicitly to get these + features in SPL. + + CONFIG_DM_WARN + + Enable the dm_warn() function. This can use up quite a bit + of space for its strings. + + CONFIG_DM_STDIO + + Enable registering a serial device with the stdio library. + + CONFIG_DM_DEVICE_REMOVE + + Enable removing of devices. + + - Linux Kernel Interface: CONFIG_CLOCKS_IN_MHZ @@ -669,6 +787,13 @@ The following options need to be configured: Board code has addition modification that it wants to make to the flat device tree before handing it off to the kernel + CONFIG_OF_SYSTEM_SETUP + + Other code has addition modification that it wants to make + to the flat device tree before handing it off to the kernel. + This causes ft_system_setup() to be called before booting + the kernel. + CONFIG_OF_BOOT_CPU This define fills in the correct boot CPU in the boot @@ -989,6 +1114,7 @@ The following options need to be configured: CONFIG_CMD_EXT4 * ext4 command support CONFIG_CMD_FS_GENERIC * filesystem commands (e.g. load, ls) that work for multiple fs types + CONFIG_CMD_FS_UUID * Look up a filesystem UUID CONFIG_CMD_SAVEENV saveenv CONFIG_CMD_FDC * Floppy Disk Support CONFIG_CMD_FAT * FAT command support @@ -2834,18 +2960,6 @@ CBFS (Coreboot Filesystem) support Enable auto completion of commands using TAB. - CONFIG_SYS_HUSH_PARSER - - Define this variable to enable the "hush" shell (from - Busybox) as command line interpreter, thus enabling - powerful command line syntax like - if...then...else...fi conditionals or `&&' and '||' - constructs ("shell scripts"). - - If undefined, you get the old, much simpler behaviour - with a somewhat smaller memory footprint. - - CONFIG_SYS_PROMPT_HUSH_PS2 This defines the secondary prompt string, which is @@ -3407,7 +3521,7 @@ FIT uImage format: to 128 or 256, although it does not have to be power of 2). default: 4096 - + CONFIG_MTD_UBI_BEB_LIMIT This option specifies the maximum bad physical eraseblocks UBI expects on the MTD device (per 1024 eraseblocks). If the @@ -3547,10 +3661,13 @@ FIT uImage format: CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS, - CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION - Address, size and partition on the MMC to load U-Boot from + Address and partition on the MMC to load U-Boot from when the MMC is being used in raw mode. + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION + Partition on the MMC to load U-Boot from when the MMC is being + used in raw mode + CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR Sector to load kernel uImage from when MMC is being used in raw mode (for Falcon mode) @@ -3561,6 +3678,10 @@ FIT uImage format: parameters from when MMC is being used in raw mode (for falcon mode) + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION + Partition on the MMC to load U-Boot from when the MMC is being + used in fs mode + CONFIG_SPL_FAT_SUPPORT Support for fs/fat/libfat.o in SPL binary @@ -3605,6 +3726,10 @@ FIT uImage format: Support for the MTD subsystem within SPL. Useful for environment on NAND support within SPL. + CONFIG_SPL_NAND_RAW_ONLY + Support to boot only raw u-boot.bin images. Use this only + if you need to save space. + CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT Set for the SPL on PPC mpc8xxx targets, support for drivers/ddr/fsl/libddr.o in SPL binary. @@ -3877,6 +4002,11 @@ Configuration Settings: Pre-relocation malloc() is only supported on ARM and sandbox at present but is fairly easy to enable for other archs. +- CONFIG_SYS_MALLOC_SIMPLE + Provides a simple and small malloc() and calloc() for those + boards which do not use the full malloc in SPL (which is + enabled with CONFIG_SYS_SPL_MALLOC_START). + - CONFIG_SYS_BOOTM_LEN: Normally compressed uImages are limited to an uncompressed size of 8 MBytes. If this is not enough, diff --git a/arch/arc/Makefile b/arch/arc/Makefile new file mode 100644 index 0000000..de25cc9 --- /dev/null +++ b/arch/arc/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/arc/cpu/$(CPU)/start.o + +libs-y += arch/arc/cpu/$(CPU)/ +libs-y += arch/arc/lib/ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3955978..2b0d2c9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -203,10 +203,12 @@ config TARGET_PM9G45 select CPU_ARM926EJS config TARGET_CORVUS + select SUPPORT_SPL bool "Support corvus" select CPU_ARM926EJS config TARGET_TAURUS + select SUPPORT_SPL bool "Support taurus" select CPU_ARM926EJS @@ -339,6 +341,10 @@ config TARGET_SPEAR600 bool "Support spear600" select CPU_ARM926EJS +config TARGET_STV0991 + bool "Support stv0991" + select CPU_V7 + config TARGET_X600 bool "Support x600" select CPU_ARM926EJS @@ -394,8 +400,8 @@ config TARGET_MX35PDK bool "Support mx35pdk" select CPU_ARM1136 -config TARGET_RPI_B - bool "Support rpi_b" +config TARGET_RPI + bool "Support rpi" select CPU_ARM1176 config TARGET_TNETV107X_EVM @@ -413,6 +419,8 @@ config TARGET_INTEGRATORCP_CM946ES config TARGET_VEXPRESS_CA15_TC2 bool "Support vexpress_ca15_tc2" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT config TARGET_VEXPRESS_CA5X2 bool "Support vexpress_ca5x2" @@ -507,16 +515,24 @@ config TARGET_SAMA5D3XEK select CPU_V7 select SUPPORT_SPL +config TARGET_SAMA5D4_XPLAINED + bool "Support sama5d4_xplained" + select CPU_V7 + +config TARGET_SAMA5D4EK + bool "Support sama5d4ek" + select CPU_V7 + config TARGET_BCM28155_AP bool "Support bcm28155_ap" select CPU_V7 -config TARGET_BCM958300K - bool "Support bcm958300k" +config TARGET_BCMCYGNUS + bool "Support bcmcygnus" select CPU_V7 -config TARGET_BCM958622HR - bool "Support bcm958622hr" +config TARGET_BCMNSP + bool "Support bcmnsp" select CPU_V7 config ARCH_EXYNOS @@ -612,6 +628,7 @@ config TARGET_MX6QSABREAUTO config TARGET_MX6SABRESD bool "Support mx6sabresd" select CPU_V7 + select SUPPORT_SPL config TARGET_MX6SLEVK bool "Support mx6slevk" @@ -635,6 +652,10 @@ config TARGET_KOSAGI_NOVENA select CPU_V7 select SUPPORT_SPL +config TARGET_TBS2910 + bool "Support tbs2910" + select CPU_V7 + config TARGET_TQMA6 bool "TQ Systems TQMa6 board" select CPU_V7 @@ -712,12 +733,14 @@ config TARGET_LS2085A_SIMU select ARM64 config TARGET_LS1021AQDS - bool "Support ls1021aqds_nor" + bool "Support ls1021aqds" select CPU_V7 + select SUPPORT_SPL config TARGET_LS1021ATWR - bool "Support ls1021atwr_nor" + bool "Support ls1021atwr" select CPU_V7 + select SUPPORT_SPL config TARGET_BALLOON3 bool "Support balloon3" @@ -777,6 +800,7 @@ config ARCH_UNIPHIER bool "Panasonic UniPhier platform" select CPU_V7 select SUPPORT_SPL + select OF_CONTROL if !SPL_BUILD endchoice @@ -812,6 +836,8 @@ source "arch/arm/cpu/arm926ejs/versatile/Kconfig" source "arch/arm/cpu/armv7/zynq/Kconfig" +source "arch/arm/cpu/armv7/Kconfig" + source "board/aristainetos/Kconfig" source "board/BuR/kwb/Kconfig" source "board/BuR/tseries/Kconfig" @@ -838,6 +864,8 @@ source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" +source "board/atmel/sama5d4_xplained/Kconfig" +source "board/atmel/sama5d4ek/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/balloon3/Kconfig" source "board/barco/titanium/Kconfig" @@ -845,8 +873,8 @@ source "board/bluegiga/apx4devkit/Kconfig" source "board/bluewater/snapper9260/Kconfig" source "board/boundary/nitrogen6x/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" -source "board/broadcom/bcm958300k/Kconfig" -source "board/broadcom/bcm958622hr/Kconfig" +source "board/broadcom/bcmcygnus/Kconfig" +source "board/broadcom/bcmnsp/Kconfig" source "board/calao/sbc35_a9g20/Kconfig" source "board/calao/tny_a9260/Kconfig" source "board/calao/usb_a9263/Kconfig" @@ -910,7 +938,7 @@ source "board/palmtreo680/Kconfig" source "board/phytec/pcm051/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/pxa255_idp/Kconfig" -source "board/raspberrypi/rpi_b/Kconfig" +source "board/raspberrypi/rpi/Kconfig" source "board/ronetix/pm9261/Kconfig" source "board/ronetix/pm9263/Kconfig" source "board/ronetix/pm9g45/Kconfig" @@ -932,10 +960,12 @@ source "board/spear/spear600/Kconfig" source "board/spear/x600/Kconfig" source "board/st-ericsson/snowball/Kconfig" source "board/st-ericsson/u8500/Kconfig" +source "board/st/stv0991/Kconfig" source "board/sunxi/Kconfig" source "board/syteco/jadecpu/Kconfig" source "board/syteco/zmx25/Kconfig" source "board/taskit/stamp9g20/Kconfig" +source "board/tbs/tbs2910/Kconfig" source "board/ti/am335x/Kconfig" source "board/ti/am43xx/Kconfig" source "board/ti/ti814x/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile new file mode 100644 index 0000000..ebb7dc3 --- /dev/null +++ b/arch/arm/Makefile @@ -0,0 +1,29 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/arm/cpu/$(CPU)/start.o + +ifeq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_SPL_START_S_PATH),) +head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o +endif +endif + +libs-y += arch/arm/cpu/$(CPU)/ +libs-y += arch/arm/cpu/ +libs-y += arch/arm/lib/ + +ifeq ($(CONFIG_SPL_BUILD),y) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) +libs-y += arch/arm/imx-common/ +endif +else +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610)) +libs-y += arch/arm/imx-common/ +endif +endif + +ifneq (,$(filter $(SOC), armada-xp kirkwood)) +libs-y += arch/arm/mvebu-common/ +endif diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile index 3279f12..56a9390 100644 --- a/arch/arm/cpu/arm1136/Makefile +++ b/arch/arm/cpu/arm1136/Makefile @@ -7,3 +7,6 @@ extra-y = start.o obj-y = cpu.o + +obj-$(CONFIG_MX31) += mx31/ +obj-$(CONFIG_MX35) += mx35/ diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile index deec427..ead2303 100644 --- a/arch/arm/cpu/arm1176/Makefile +++ b/arch/arm/cpu/arm1176/Makefile @@ -10,3 +10,6 @@ extra-y = start.o obj-y = cpu.o + +obj-$(CONFIG_BCM2835) += bcm2835/ +obj-$(CONFIG_TNETV107X) += tnetv107x/ diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c index 47c23bb..7ba28d3 100644 --- a/arch/arm/cpu/arm1176/tnetv107x/clock.c +++ b/arch/arm/cpu/arm1176/tnetv107x/clock.c @@ -16,7 +16,7 @@ #define BIT(x) (1 << (x)) #define MAX_PREDIV 64 -#define MAX_POSTDIV 8 +#define MAX_POSTDIV 8UL #define MAX_MULT 512 #define MAX_DIV (MAX_PREDIV * MAX_POSTDIV) @@ -362,7 +362,7 @@ static void init_pll(const struct pll_init_data *data) pllctl_reg_write(data->pll, ctl, tmp); mult = data->pll_freq / fpll; - for (mult = max(mult, 1); mult <= MAX_MULT; mult++) { + for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) { div = (fpll * mult) / data->pll_freq; if (div < 1 || div > MAX_DIV) continue; diff --git a/arch/arm/cpu/arm720t/Makefile b/arch/arm/cpu/arm720t/Makefile index 6badb3b..9f61ea2 100644 --- a/arch/arm/cpu/arm720t/Makefile +++ b/arch/arm/cpu/arm720t/Makefile @@ -9,3 +9,7 @@ extra-y = start.o obj-y = interrupts.o cpu.o obj-$(CONFIG_TEGRA) += tegra-common/ +obj-$(CONFIG_TEGRA20) += tegra20/ +obj-$(CONFIG_TEGRA30) += tegra30/ +obj-$(CONFIG_TEGRA114) += tegra114/ +obj-$(CONFIG_TEGRA124) += tegra124/ diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index aac8043..a72e5de 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -9,3 +9,10 @@ extra-y = start.o obj-y += cpu.o obj-$(CONFIG_USE_IRQ) += interrupts.o + +obj-$(if $(filter a320,$(SOC)),y) += a320/ +obj-$(CONFIG_AT91FAMILY) += at91/ +obj-$(CONFIG_EP93XX) += ep93xx/ +obj-$(CONFIG_IMX) += imx/ +obj-$(CONFIG_KS8695) += ks8695/ +obj-$(CONFIG_S3C24X0) += s3c24x0/ diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 1252995..adcea9f 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -13,3 +13,18 @@ ifdef CONFIG_SPL_NO_CPU_SUPPORT_CODE extra-y := endif endif + +obj-$(CONFIG_ARMADA100) += armada100/ +obj-$(CONFIG_AT91FAMILY) += at91/ +obj-$(CONFIG_ARCH_DAVINCI) += davinci/ +obj-$(CONFIG_KIRKWOOD) += kirkwood/ +obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/ +obj-$(CONFIG_MB86R0x) += mb86r0x/ +obj-$(CONFIG_MX25) += mx25/ +obj-$(CONFIG_MX27) += mx27/ +obj-$(if $(filter mxs,$(SOC)),y) += mxs/ +obj-$(CONFIG_ARCH_NOMADIK) += nomadik/ +obj-$(CONFIG_ORION5X) += orion5x/ +obj-$(CONFIG_PANTHEON) += pantheon/ +obj-$(if $(filter spear,$(SOC)),y) += spear/ +obj-$(CONFIG_ARCH_VERSATILE) += versatile/ diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c index cae4abc..efb53d6 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -7,9 +7,12 @@ */ #include <common.h> +#include <dm.h> #include <asm/io.h> +#include <asm/arch/at91sam9260_matrix.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91sam9_sdramc.h> #include <asm/arch/gpio.h> /* @@ -207,3 +210,36 @@ void at91_mci_hw_init(void) #endif } #endif + +void at91_sdram_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); + at91_set_a_periph(AT91_PIO_PORTC, 17, 0); + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); + at91_set_a_periph(AT91_PIO_PORTC, 20, 0); + at91_set_a_periph(AT91_PIO_PORTC, 21, 0); + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); + at91_set_a_periph(AT91_PIO_PORTC, 25, 0); + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); + at91_set_a_periph(AT91_PIO_PORTC, 28, 0); + at91_set_a_periph(AT91_PIO_PORTC, 29, 0); + at91_set_a_periph(AT91_PIO_PORTC, 30, 0); + at91_set_a_periph(AT91_PIO_PORTC, 31, 0); +} + +/* Platform data for the GPIOs */ +static const struct at91_port_platdata at91sam9260_plat[] = { + { ATMEL_BASE_PIOA, "PA" }, + { ATMEL_BASE_PIOB, "PB" }, + { ATMEL_BASE_PIOC, "PC" }, +}; + +U_BOOT_DEVICES(at91sam9260_gpios) = { + { "gpio_at91", &at91sam9260_plat[0] }, + { "gpio_at91", &at91sam9260_plat[1] }, + { "gpio_at91", &at91sam9260_plat[2] }, +}; diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c index 31315b5..f363982 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -187,3 +187,63 @@ int at91_clock_init(unsigned long main_clock) return 0; } + +#if !defined(AT91_PLL_LOCK_TIMEOUT) +#define AT91_PLL_LOCK_TIMEOUT 1000000 +#endif + +void at91_plla_init(u32 pllar) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + int timeout = AT91_PLL_LOCK_TIMEOUT; + + writel(pllar, &pmc->pllar); + while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) { + timeout--; + if (timeout == 0) + break; + } +} +void at91_pllb_init(u32 pllbr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + int timeout = AT91_PLL_LOCK_TIMEOUT; + + writel(pllbr, &pmc->pllbr); + while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) { + timeout--; + if (timeout == 0) + break; + } +} + +void at91_mck_init(u32 mckr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + int timeout = AT91_PLL_LOCK_TIMEOUT; + u32 tmp; + + tmp = readl(&pmc->mckr); + tmp &= ~(AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_MASK | + AT91_PMC_MCKR_CSS_MASK); + tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_MASK | + AT91_PMC_MCKR_CSS_MASK); + writel(tmp, &pmc->mckr); + + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) { + timeout--; + if (timeout == 0) + break; + } +} + +void at91_periph_clk_enable(int id) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(1 << id, &pmc->pcer); +} diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile index 4976bbb..0edf144 100644 --- a/arch/arm/cpu/arm926ejs/mx27/Makefile +++ b/arch/arm/cpu/arm926ejs/mx27/Makefile @@ -5,3 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y = generic.o reset.o timer.o + +ifndef CONFIG_SPL_BUILD +obj-y += relocate.o +endif diff --git a/arch/arm/cpu/arm926ejs/mx27/relocate.S b/arch/arm/cpu/arm926ejs/mx27/relocate.S new file mode 100644 index 0000000..0c4b272 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx27/relocate.S @@ -0,0 +1,51 @@ +/* + * relocate - i.MX27-specific vector relocation + * + * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> + +/* + * The i.MX27 SoC is very specific with respect to exceptions: it + * does not provide RAM at the high vectors address (0xFFFF0000), + * thus only the low address (0x00000000) is useable; but that is + * in ROM. Therefore, vectors cannot be changed at all. + * + * However, these ROM-based vectors actually just perform indirect + * calls through pointers located in RAM at SoC-specific addresses, + * as follows: + * + * Offset Exception Use by ROM code + * 0x00000000 reset indirect branch to [0x00000014] + * 0x00000004 undefined instruction indirect branch to [0xfffffef0] + * 0x00000008 software interrupt indirect branch to [0xfffffef4] + * 0x0000000c prefetch abort indirect branch to [0xfffffef8] + * 0x00000010 data abort indirect branch to [0xfffffefc] + * 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000 + * 0x00000018 IRQ indirect branch to [0xffffff00] + * 0x0000001c FIQ indirect branch to [0xffffff04] + * + * In order to initialize exceptions on i.MX27, we must copy U-Boot's + * indirect (not exception!) vector table into 0xfffffef0..0xffffff04 + * taking care not to copy vectors number 5 (reserved exception). + */ + + .section .text.relocate_vectors,"ax",%progbits + +ENTRY(relocate_vectors) + + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ + ldr r1, =32 /* size of vector table */ + add r0, r0, r1 /* skip to indirect table */ + ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */ + ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */ + stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */ + + bx lr + +ENDPROC(relocate_vectors) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg index 1520bba..83953da 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg @@ -1,3 +1,4 @@ +DISPLAYPROGRESS SECTION 0x0 BOOTABLE TAG LAST LOAD 0x1000 spl/u-boot-spl.bin diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg index 55510e9..e702809 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -1,3 +1,4 @@ +DISPLAYPROGRESS SECTION 0x0 BOOTABLE TAG LAST LOAD 0x1000 spl/u-boot-spl.bin diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg index bb78cb0..3f7bf59 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -1,3 +1,4 @@ +DISPLAYPROGRESS SECTION 0x0 BOOTABLE TAG LAST LOAD 0x1000 spl/u-boot-spl.bin diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index d25019a..1c54ab7 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -1002,7 +1002,8 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, uint32_t powered_by_linreg = 0; int adjust_up, tmp; - new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV); + new_brownout = DIV_ROUND_CLOSEST(new_target - new_brownout, + cfg->step_mV); cur_target = readl(cfg->reg); cur_target &= cfg->trg_mask; diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig new file mode 100644 index 0000000..61e7c82 --- /dev/null +++ b/arch/arm/cpu/armv7/Kconfig @@ -0,0 +1,34 @@ +if CPU_V7 + +config CPU_V7_HAS_NONSEC + bool + +config CPU_V7_HAS_VIRT + bool + +config ARMV7_NONSEC + boolean "Enable support for booting in non-secure mode" if EXPERT + depends on CPU_V7_HAS_NONSEC + default y + ---help--- + Say Y here to enable support for booting in non-secure / SVC mode. + +config ARMV7_BOOT_SEC_DEFAULT + boolean "Boot in secure mode by default" if EXPERT + depends on ARMV7_NONSEC + default n + ---help--- + Say Y here to boot in secure mode by default even if non-secure mode + is supported. This option is useful to boot kernels which do not + suppport booting in non-secure mode. Only set this if you need it. + This can be overriden at run-time by setting the bootm_boot_mode env. + variable to "sec" or "nonsec". + +config ARMV7_VIRT + boolean "Enable support for hardware virtualization" if EXPERT + depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC + default y + ---help--- + Say Y here to boot in hypervisor (HYP) mode when booting non-secure. + +endif diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index afeed4d..409e6f5 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -37,3 +37,29 @@ obj-$(CONFIG_TEGRA) += tegra-common/ ifneq (,$(filter s5pc1xx exynos,$(SOC))) obj-y += s5p-common/ endif + +obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/ +obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/ +obj-$(CONFIG_AT91FAMILY) += at91/ +obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/ +obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/ +obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/ +obj-$(CONFIG_ARCH_EXYNOS) += exynos/ +obj-$(CONFIG_ARCH_HIGHBANK) += highbank/ +obj-$(CONFIG_ARCH_KEYSTONE) += keystone/ +obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/ +obj-$(if $(filter mx5,$(SOC)),y) += mx5/ +obj-$(CONFIG_MX6) += mx6/ +obj-$(CONFIG_OMAP34XX) += omap3/ +obj-$(CONFIG_OMAP44XX) += omap4/ +obj-$(CONFIG_OMAP54XX) += omap5/ +obj-$(CONFIG_RMOBILE) += rmobile/ +obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/ +obj-$(CONFIG_SOCFPGA) += socfpga/ +obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ +obj-$(CONFIG_ARCH_SUNXI) += sunxi/ +obj-$(CONFIG_TEGRA20) += tegra20/ +obj-$(CONFIG_U8500) += u8500/ +obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/ +obj-$(CONFIG_VF610) += vf610/ +obj-$(CONFIG_ZYNQ) += zynq/ diff --git a/arch/arm/cpu/armv7/at91/Makefile b/arch/arm/cpu/armv7/at91/Makefile index 0a2e48d..f4f35a4 100644 --- a/arch/arm/cpu/armv7/at91/Makefile +++ b/arch/arm/cpu/armv7/at91/Makefile @@ -9,6 +9,7 @@ # obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o +obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o obj-y += clock.o obj-y += cpu.o obj-y += reset.o diff --git a/arch/arm/cpu/armv7/at91/clock.c b/arch/arm/cpu/armv7/at91/clock.c index 36ed4a6..2cdddb2 100644 --- a/arch/arm/cpu/armv7/at91/clock.c +++ b/arch/arm/cpu/armv7/at91/clock.c @@ -111,6 +111,35 @@ int at91_clock_init(unsigned long main_clock) return 0; } +void at91_plla_init(u32 pllar) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(pllar, &pmc->pllar); + while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) + ; +} + +void at91_mck_init(u32 mckr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = readl(&pmc->mckr); + tmp &= ~(AT91_PMC_MCKR_CSS_MASK | + AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_2); + tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK | + AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_2); + writel(tmp, &pmc->mckr); + + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; +} + void at91_periph_clk_enable(int id) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; diff --git a/arch/arm/cpu/armv7/at91/config.mk b/arch/arm/cpu/armv7/at91/config.mk index 09eab70..db60308 100644 --- a/arch/arm/cpu/armv7/at91/config.mk +++ b/arch/arm/cpu/armv7/at91/config.mk @@ -3,8 +3,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD -ALL-y += boot.bin -else +ifndef CONFIG_SPL_BUILD ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/at91/sama5d4_devices.c b/arch/arm/cpu/armv7/at91/sama5d4_devices.c new file mode 100644 index 0000000..2708097 --- /dev/null +++ b/arch/arm/cpu/armv7/at91/sama5d4_devices.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2014 Atmel + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/sama5d4.h> + +char *get_cpu_name() +{ + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_sama5d4()) + switch (extension_id) { + case ARCH_EXID_SAMA5D41: + return "SAMA5D41"; + case ARCH_EXID_SAMA5D42: + return "SAMA5D42"; + case ARCH_EXID_SAMA5D43: + return "SAMA5D43"; + case ARCH_EXID_SAMA5D44: + return "SAMA5D44"; + default: + return "Unknown CPU type"; + } + else + return "Unknown CPU type"; +} diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c index e3ebfe0..19bf80b 100644 --- a/arch/arm/cpu/armv7/at91/timer.c +++ b/arch/arm/cpu/armv7/at91/timer.c @@ -65,7 +65,8 @@ int timer_init(void) /* Enable PITC */ writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); - gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16; + gd->arch.timer_rate_hz = get_pit_clk_rate() / 16; + gd->arch.tbu = 0; gd->arch.tbl = 0; diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.h b/arch/arm/cpu/armv7/bcm281xx/clk-core.h index 882a297..4a694d7 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-core.h +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.h @@ -73,10 +73,6 @@ struct clk { struct refclk *refclk_str_to_clk(const char *name); -#define U8_MAX ((u8)~0U) -#define U32_MAX ((u32)~0U) -#define U64_MAX ((u64)~0U) - /* The common clock framework uses u8 to represent a parent index */ #define PARENT_COUNT_MAX ((u32)U8_MAX) diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 090be93..f3eadb4 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -26,6 +26,8 @@ config TARGET_ODROID config TARGET_ARNDALE bool "Exynos5250 Arndale board" + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUPPORT_SPL select OF_CONTROL if !SPL_BUILD @@ -44,11 +46,16 @@ config TARGET_SMDK5420 select SUPPORT_SPL select OF_CONTROL if !SPL_BUILD -config TARGET_PEACH_PIT +config TARGET_PEACH_PI bool "Peach Pi board" select SUPPORT_SPL select OF_CONTROL if !SPL_BUILD +config TARGET_PEACH_PIT + bool "Peach Pit board" + select SUPPORT_SPL + select OF_CONTROL if !SPL_BUILD + endchoice config SYS_SOC diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 7558eff..8fab135 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -118,7 +118,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) div = PLL_DIV_1024; else if (proid_is_exynos4412()) div = PLL_DIV_65535; - else if (proid_is_exynos5250() || proid_is_exynos5420()) + else if (proid_is_exynos5250() || proid_is_exynos5420() + || proid_is_exynos5800()) div = PLL_DIV_65536; else return 0; @@ -1422,8 +1423,8 @@ static int clock_calc_best_scalar(unsigned int main_scaler_bits, return 1; for (i = 1; i <= loops; i++) { - const unsigned int effective_div = max(min(input_rate / i / - target_rate, cap), 1); + const unsigned int effective_div = + max(min(input_rate / i / target_rate, cap), 1U); const unsigned int effective_rate = input_rate / i / effective_div; const int error = target_rate - effective_rate; @@ -1581,7 +1582,7 @@ static unsigned long exynos4_get_i2c_clk(void) unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); } else { @@ -1617,7 +1618,7 @@ unsigned long get_i2c_clk(void) unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_pwm_clk(); return clock_get_periph_rate(PERIPH_ID_PWM0); } else { @@ -1630,7 +1631,7 @@ unsigned long get_pwm_clk(void) unsigned long get_uart_clk(int dev_index) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_uart_clk(dev_index); return exynos5_get_uart_clk(dev_index); } else { @@ -1643,7 +1644,7 @@ unsigned long get_uart_clk(int dev_index) unsigned long get_mmc_clk(int dev_index) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_mmc_clk(dev_index); return exynos5_get_mmc_clk(dev_index); } else { @@ -1654,7 +1655,7 @@ unsigned long get_mmc_clk(int dev_index) void set_mmc_clk(int dev_index, unsigned int div) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_set_mmc_clk(dev_index, div); else exynos5_set_mmc_clk(dev_index, div); @@ -1668,7 +1669,7 @@ unsigned long get_lcd_clk(void) if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_lcd_clk(); else return exynos5_get_lcd_clk(); @@ -1682,7 +1683,7 @@ void set_lcd_clk(void) else { if (proid_is_exynos5250()) exynos5_set_lcd_clk(); - else if (proid_is_exynos5420()) + else if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_set_lcd_clk(); } } @@ -1696,7 +1697,7 @@ void set_mipi_clk(void) int set_spi_clk(int periph_id, unsigned int rate) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_set_spi_clk(periph_id, rate); return exynos5_set_spi_clk(periph_id, rate); } else { diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index b6a9bc1..0aff3d0 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void) void system_clock_init(void) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_system_clock_init(); else exynos5250_system_clock_init(); diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index b86dd2d..7c0b12a 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -464,6 +464,16 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) + DMC_OFFSET); pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE; + if (CONFIG_NR_DRAM_BANKS > 4) { + /* Need both controllers. */ + mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2; + mem->chips_per_channel = 2; + mem->chips_to_configure = 2; + } else { + /* 2GB requires a single controller */ + mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1; + } + /* Enable PAUSE for DREX */ setbits_le32(&clk->pause, ENABLE_BIT); @@ -832,6 +842,25 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG); setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG); + /* + * As per Exynos5800 UM ver 0.00 section 17.13.2.1 + * CONCONTROL register bit 3 [update_mode], Exynos5800 does not + * support the PHY initiated update. And it is recommended to set + * this field to 1'b1 during initialization + * + * When we apply PHY-initiated mode, DLL lock value is determined + * once at DMC init time and not updated later when we change the MIF + * voltage based on ASV group in kernel. Applying MC-initiated mode + * makes sure that DLL tracing is ON so that silicon is able to + * compensate the voltage variation. + */ + val = readl(&drex0->concontrol); + val |= CONCONTROL_UPDATE_MODE; + writel(val , &drex0->concontrol); + val = readl(&drex1->concontrol); + val |= CONCONTROL_UPDATE_MODE; + writel(val , &drex1->concontrol); + return 0; } #endif diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 3d95dc3..94d0297 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -837,7 +837,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags) int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_pinmux_config(peripheral, flags); else if (proid_is_exynos5250()) return exynos5_pinmux_config(peripheral, flags); diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index e1ab3d6..1520d64 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -53,10 +53,37 @@ void exynos5_set_usbhost_phy_ctrl(unsigned int enable) } } +void exynos4412_set_usbhost_phy_ctrl(unsigned int enable) +{ + struct exynos4412_power *power = + (struct exynos4412_power *)samsung_get_base_power(); + + if (enable) { + /* Enabling USBHOST_PHY */ + setbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + setbits_le32(&power->hsic1_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + setbits_le32(&power->hsic2_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } else { + /* Disabling USBHOST_PHY */ + clrbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + clrbits_le32(&power->hsic1_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + clrbits_le32(&power->hsic2_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } +} + void set_usbhost_phy_ctrl(unsigned int enable) { if (cpu_is_exynos5()) exynos5_set_usbhost_phy_ctrl(enable); + else if (cpu_is_exynos4()) + if (proid_is_exynos4412()) + exynos4412_set_usbhost_phy_ctrl(enable); } static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable) diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c index 658e4cb..bc237c9 100644 --- a/arch/arm/cpu/armv7/exynos/spl_boot.c +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c @@ -151,7 +151,7 @@ static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) } for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) { - todo = min(uboot_size - upto, (1 << 15)); + todo = min(uboot_size - upto, (unsigned int)(1 << 15)); spi_rx_tx(regs, todo, (void *)(uboot_addr), (void *)(SPI_FLASH_UBOOT_POS), i); } @@ -195,10 +195,16 @@ void copy_uboot_to_ram(void) void (*end_bootop_from_emmc)(void); #endif #ifdef CONFIG_USB_BOOTING - u32 (*usb_copy)(void); int is_cr_z_set; unsigned int sec_boot_check; + /* + * Note that older hardware (before Exynos5800) does not expect any + * arguments, but it does not hurt to pass them, so a common function + * prototype is used. + */ + u32 (*usb_copy)(u32 num_of_block, u32 *dst); + /* Read iRAM location to check for secondary USB boot mode */ sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE); if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT) @@ -240,7 +246,7 @@ void copy_uboot_to_ram(void) */ is_cr_z_set = config_branch_prediction(0); usb_copy = get_irom_func(USB_INDEX); - usb_copy(); + usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE); config_branch_prediction(is_cr_z_set); break; #endif diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index d82ce8d..2e6a207 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -7,6 +7,8 @@ obj-y += cpu.o obj-y += clock.o obj-y += timer.o +obj-y += fsl_epu.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o +obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index b7dde45..ce2d92f 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -12,6 +12,8 @@ #include <netdev.h> #include <fsl_esdhc.h> +#include "fsl_epu.h" + DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_DISPLAY_CPUINFO) @@ -101,3 +103,35 @@ int cpu_eth_init(bd_t *bis) return 0; } + +int arch_cpu_init(void) +{ + void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + + /* + * After wakeup from deep sleep, Clear EPU registers + * as early as possible to prevent from possible issue. + * It's also safe to clear at normal boot. + */ + fsl_epu_clean(epu_base); + + return 0; +} + +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +/* Set the address at which the secondary core starts from.*/ +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + out_be32(&gur->scratchrw[0], addr); +} + +/* Release the secondary core from holdoff state and kick it */ +void smp_kick_all_cpus(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + out_be32(&gur->brrl, 0x2); +} +#endif diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 4ce3808..989780d 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -91,7 +91,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) } do_fixup_by_prop_u32(blob, "device_type", "soc", - 4, "bus-frequency", busclk / 2, 1); + 4, "bus-frequency", busclk, 1); ft_fixup_enet_phy_connect_type(blob); diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c new file mode 100644 index 0000000..6212640 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c @@ -0,0 +1,57 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> + +#include "fsl_epu.h" + +/** + * fsl_epu_clean - Clear EPU registers + */ +void fsl_epu_clean(void *epu_base) +{ + u32 offset; + + /* follow the exact sequence to clear the registers */ + /* Clear EPACRn */ + for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPEVTCRn */ + for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPGCR */ + out_be32(epu_base + EPGCR, 0); + + /* Clear EPSMCRn */ + for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCCRn */ + for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCMPRn */ + for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCTRn */ + for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPIMCRn */ + for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPXTRIGCRn */ + out_be32(epu_base + EPXTRIGCR, 0); + + /* Clear EPECRn */ + for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE) + out_be32(epu_base + offset, 0); +} diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h new file mode 100644 index 0000000..d658aad --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h @@ -0,0 +1,68 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_EPU_H +#define __FSL_EPU_H + +#include <asm/types.h> + +#define FSL_STRIDE_4B 4 +#define FSL_STRIDE_8B 8 + +/* Block offsets */ +#define EPU_BLOCK_OFFSET 0x00000000 + +/* EPGCR (Event Processor Global Control Register) */ +#define EPGCR 0x000 + +/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */ +#define EPEVTCR0 0x050 +#define EPEVTCR9 0x074 +#define EPEVTCR_STRIDE FSL_STRIDE_4B + +/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */ +#define EPXTRIGCR 0x090 + +/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */ +#define EPIMCR0 0x100 +#define EPIMCR31 0x17C +#define EPIMCR_STRIDE FSL_STRIDE_4B + +/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */ +#define EPSMCR0 0x200 +#define EPSMCR15 0x278 +#define EPSMCR_STRIDE FSL_STRIDE_8B + +/* EPECR0-15 (Event Processor Event Control Registers) */ +#define EPECR0 0x300 +#define EPECR15 0x33C +#define EPECR_STRIDE FSL_STRIDE_4B + +/* EPACR0-15 (Event Processor Action Control Registers) */ +#define EPACR0 0x400 +#define EPACR15 0x43C +#define EPACR_STRIDE FSL_STRIDE_4B + +/* EPCCRi0-15 (Event Processor Counter Control Registers) */ +#define EPCCR0 0x800 +#define EPCCR15 0x83C +#define EPCCR31 0x87C +#define EPCCR_STRIDE FSL_STRIDE_4B + +/* EPCMPR0-15 (Event Processor Counter Compare Registers) */ +#define EPCMPR0 0x900 +#define EPCMPR15 0x93C +#define EPCMPR31 0x97C +#define EPCMPR_STRIDE FSL_STRIDE_4B + +/* EPCTR0-31 (Event Processor Counter Register) */ +#define EPCTR0 0xA00 +#define EPCTR31 0xA7C +#define EPCTR_STRIDE FSL_STRIDE_4B + +void fsl_epu_clean(void *epu_base); + +#endif diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c new file mode 100644 index 0000000..1dfbf54 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/spl.c @@ -0,0 +1,33 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SPL_MMC_SUPPORT + return BOOT_DEVICE_MMC1; +#endif + return BOOT_DEVICE_NAND; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: +#ifdef CONFIG_SPL_FAT_SUPPORT + return MMCSD_MODE_FAT; +#else + return MMCSD_MODE_RAW; +#endif + case BOOT_DEVICE_NAND: + return 0; + default: + puts("spl: error: unsupported device\n"); + hang(); + } +} diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 2d53669..3753c14 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -85,37 +85,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) } #endif -void set_chipselect_size(int const cs_size) -{ - unsigned int reg; - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - reg = readl(&iomuxc_regs->gpr1); - - switch (cs_size) { - case CS0_128: - reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */ - reg |= 0x5; - break; - case CS0_64M_CS1_64M: - reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */ - reg |= 0x1B; - break; - case CS0_64M_CS1_32M_CS2_32M: - reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */ - reg |= 0x4B; - break; - case CS0_32M_CS1_32M_CS2_32M_CS3_32M: - reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */ - reg |= 0x249; - break; - default: - printf("Unknown chip select size: %d\n", cs_size); - break; - } - - writel(reg, &iomuxc_regs->gpr1); -} - #ifdef CONFIG_MX53 void boot_mode_apply(unsigned cfg_val) { diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 6c9c78c..93a02ad 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -443,7 +443,7 @@ int enable_fec_anatop_clock(enum enet_freq freq) struct anatop_regs __iomem *anatop = (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; - if (freq < ENET_25MHz || freq > ENET_125MHz) + if (freq < ENET_25MHZ || freq > ENET_125MHZ) return -EINVAL; reg = readl(&anatop->pll_enet); @@ -596,6 +596,14 @@ int enable_sata_clock(void) ungate_sata_clock(); return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); } + +void disable_sata_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); +} #endif int enable_pcie_clock(void) @@ -673,6 +681,36 @@ void hab_caam_clock_enable(unsigned char enable) } #endif +static void enable_pll3(void) +{ + struct anatop_regs __iomem *anatop = + (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; + + /* make sure pll3 is enabled */ + if ((readl(&anatop->usb1_pll_480_ctrl) & + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) { + /* enable pll's power */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER, + &anatop->usb1_pll_480_ctrl_set); + writel(0x80, &anatop->ana_misc2_clr); + /* wait for pll lock */ + while ((readl(&anatop->usb1_pll_480_ctrl) & + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) + ; + /* disable bypass */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS, + &anatop->usb1_pll_480_ctrl_clr); + /* enable pll output */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE, + &anatop->usb1_pll_480_ctrl_set); + } +} + +void enable_thermal_clk(void) +{ + enable_pll3(); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index affbf7f..5f5f497 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -22,6 +22,8 @@ #include <asm/arch/mxc_hdmi.h> #include <asm/arch/crm_regs.h> #include <asm/bootm.h> +#include <dm.h> +#include <imx_thermal.h> enum ldo_reg { LDO_ARM, @@ -37,6 +39,19 @@ struct scu_regs { u32 fpga_rev; }; +#if defined(CONFIG_IMX6_THERMAL) +static const struct imx_thermal_plat imx6_thermal_plat = { + .regs = (void *)ANATOP_BASE_ADDR, + .fuse_bank = 1, + .fuse_word = 6, +}; + +U_BOOT_DEVICE(imx6_thermal) = { + .name = "imx_thermal", + .platdata = &imx6_thermal_plat, +}; +#endif + u32 get_nr_cpus(void) { struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; @@ -350,8 +365,8 @@ void boot_mode_apply(unsigned cfg_val) /* * cfg_val will be used for * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] - * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] - * to SBMR1, which will determine the boot device. + * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0] + * instead of SBMR1 to determine the boot device. */ const struct boot_mode soc_boot_modes[] = { {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 745670e..30d81db 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -169,11 +169,11 @@ ENTRY(_nonsec_init) * we do this here instead. * But first check if we have the generic timer. */ -#ifdef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_TIMER_CLK_FREQ mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT) - ldreq r1, =CONFIG_SYS_CLK_FREQ + ldreq r1, =CONFIG_TIMER_CLK_FREQ mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ #endif @@ -191,6 +191,9 @@ ENTRY(smp_waitloop) wfi ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address ldr r1, [r1] +#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN + rev r1, r1 +#endif cmp r0, r1 @ make sure we dont execute this code beq smp_waitloop @ again (due to a spurious wakeup) mov r0, r1 diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/cpu/armv7/omap-common/abb.c index 423aeb9..a0add66 100644 --- a/arch/arm/cpu/armv7/omap-common/abb.c +++ b/arch/arm/cpu/armv7/omap-common/abb.c @@ -48,9 +48,9 @@ static void abb_setup_timings(u32 setup) */ /* calculate SR2_WTCNT_VALUE */ - sys_rate = DIV_ROUND(V_OSCK, 1000000); - clk_cycles = DIV_ROUND(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate); - sr2_cnt = DIV_ROUND(OMAP_ABB_SETTLING_TIME * 10, clk_cycles); + sys_rate = DIV_ROUND_CLOSEST(V_OSCK, 1000000); + clk_cycles = DIV_ROUND_CLOSEST(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate); + sr2_cnt = DIV_ROUND_CLOSEST(OMAP_ABB_SETTLING_TIME * 10, clk_cycles); setbits_le32(setup, sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1)); diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index fb535eb..cb18908 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -33,8 +33,19 @@ void save_omap_boot_params(void) * used. But it not correct to assume that romcode structure * encoding would be same as u-boot. So use the defined offsets. */ - gd->arch.omap_boot_params.omap_bootdevice = boot_device = - *((u8 *)(rom_params + BOOT_DEVICE_OFFSET)); + boot_device = *((u8 *)(rom_params + BOOT_DEVICE_OFFSET)); + +#if defined(BOOT_DEVICE_NAND_I2C) + /* + * Re-map NAND&I2C boot-device to the "normal" NAND boot-device. + * Otherwise the SPL boot IF can't handle this device correctly. + * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens + * Draco leads to this boot-device passed to SPL from the BootROM. + */ + if (boot_device == BOOT_DEVICE_NAND_I2C) + boot_device = BOOT_DEVICE_NAND; +#endif + gd->arch.omap_boot_params.omap_bootdevice = boot_device; gd->arch.omap_boot_params.ch_flags = *((u8 *)(rom_params + CH_FLAGS_OFFSET)); @@ -57,7 +68,7 @@ void save_omap_boot_params(void) } } -#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) /* * We get different values for QSPI_1 and QSPI_4 being used, but * don't actually care about this difference. Rather than diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index c8e9bc8..e601ba1 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1226,13 +1226,14 @@ void dmm_init(u32 base) emif1_enabled = 1; emif2_enabled = 1; break; - } else if (valid == 1) { + } + + if (valid == 1) emif1_enabled = 1; - } else if (valid == 2) { + + if (valid == 2) emif2_enabled = 1; - } } - } static void do_bug0039_workaround(u32 base) diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c index 3b4dd3f..a24baa1 100644 --- a/arch/arm/cpu/armv7/omap-common/sata.c +++ b/arch/arm/cpu/armv7/omap-common/sata.c @@ -74,6 +74,11 @@ int init_sata(int dev) return ret; } +int reset_sata(int dev) +{ + return 0; +} + /* On OMAP platforms SATA provides the SCSI subsystem */ void scsi_init(void) { diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index 129982c..aca862d 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -12,6 +12,9 @@ config TARGET_OMAP5_UEVM config TARGET_DRA7XX_EVM bool "TI DRA7XX" +config TARGET_BEAGLE_X15 + bool "BeagleBoard X15" + endchoice config SYS_SOC @@ -20,5 +23,6 @@ config SYS_SOC source "board/compulab/cm_t54/Kconfig" source "board/ti/omap5_uevm/Kconfig" source "board/ti/dra7xx/Kconfig" +source "board/ti/beagle_x15/Kconfig" endif diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 0257383..95f1686 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -365,31 +365,31 @@ struct vcores_data dra752_volts = { .mpu.value = VDD_MPU_DRA752, .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, .mpu.pmic = &tps659038, .eve.value = VDD_EVE_DRA752, .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE, + .eve.addr = TPS659038_REG_ADDR_SMPS45, .eve.pmic = &tps659038, .gpu.value = VDD_GPU_DRA752, .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU, + .gpu.addr = TPS659038_REG_ADDR_SMPS6, .gpu.pmic = &tps659038, .core.value = VDD_CORE_DRA752, .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .core.addr = TPS659038_REG_ADDR_SMPS7_CORE, + .core.addr = TPS659038_REG_ADDR_SMPS7, .core.pmic = &tps659038, .iva.value = VDD_IVA_DRA752, .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA, + .iva.addr = TPS659038_REG_ADDR_SMPS8, .iva.pmic = &tps659038, }; @@ -593,7 +593,7 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = { .ctrl_ddr_ctrl_ext_0 = 0xA2000000, }; -void hw_data_init(void) +void __weak hw_data_init(void) { u32 omap_rev = omap_revision(); diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index ff08ef4..0745d42 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -376,6 +376,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_status = 0x4A002134, + .control_phy_power_usb = 0x4A002370, .control_phy_power_sata = 0x4A002374, .control_core_mac_id_0_lo = 0x4A002514, .control_core_mac_id_0_hi = 0x4A002518, @@ -800,6 +801,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_clkmode_dpll_dsp = 0x4a005234, .cm_shadow_freq_config1 = 0x4a005260, .cm_clkmode_dpll_gmac = 0x4a0052a8, + .cm_coreaon_usb_phy_core_clkctrl = 0x4a008640, .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, /* cm1.mpu */ @@ -906,6 +908,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_gmac_gmac_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, + .cm_l3init_usb_otg_ss_clkctrl = 0x4a0093f0, /* cm2.l4per */ .cm_l4per_clkstctrl = 0x4a009700, diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 065199b..7d8cec0 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -513,7 +513,7 @@ const struct lpddr2_mr_regs mr_regs = { .mr16 = MR16_REF_FULL_ARRAY }; -static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, +void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) { diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig index 8444d42..6d94199 100644 --- a/arch/arm/cpu/armv7/rmobile/Kconfig +++ b/arch/arm/cpu/armv7/rmobile/Kconfig @@ -6,6 +6,9 @@ choice config TARGET_ARMADILLO_800EVA bool "armadillo 800 eva board" +config TARGET_GOSE + bool "Gose board" + config TARGET_KOELSCH bool "Koelsch board" @@ -29,6 +32,7 @@ config RMOBILE_EXTRAM_BOOT default n source "board/atmark-techno/armadillo-800eva/Kconfig" +source "board/renesas/gose/Kconfig" source "board/renesas/koelsch/Kconfig" source "board/renesas/lager/Kconfig" source "board/kmc/kzm9g/Kconfig" diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile index dd7de41..647e426 100644 --- a/arch/arm/cpu/armv7/rmobile/Makefile +++ b/arch/arm/cpu/armv7/rmobile/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o +obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c index b98137e..d47c47c 100644 --- a/arch/arm/cpu/armv7/rmobile/cpu_info.c +++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c @@ -53,6 +53,7 @@ static const struct { { 0x40, "R8A7740" }, { 0x45, "R8A7790" }, { 0x47, "R8A7791" }, + { 0x4B, "R8A7793" }, { 0x4C, "R8A7794" }, { 0x0, "CPU" }, }; diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c new file mode 100644 index 0000000..03c27ad --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c @@ -0,0 +1,1926 @@ +/* + * arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <sh_pfc.h> +#include <asm/gpio.h> + +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define CPU_32_PORT1(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx) + +/* + * GP_0_0_DATA -> GP_7_25_DATA + * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31] + * GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31]) + */ +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_32_PORT1(fn, pfx##_1_, sfx), \ + CPU_32_PORT(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_32_PORT(fn, pfx##_5_, sfx), \ + CPU_32_PORT(fn, pfx##_6_, sfx), \ + CPU_32_PORT1(fn, pfx##_7_, sfx) + +#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) + +#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +#define _GP_INDT(pfx, sfx) GP##pfx##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + + +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) + +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5, + FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11, + FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19, + FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29, + FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8, + FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20, + + /* GPSR1 */ + FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3, + FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16, + FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25, + FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N, + FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18, + FN_IP3_21_20, + + /* GPSR2 */ + FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, + FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19, + FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26, + FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9, + FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22, + FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0, + FN_IP6_5_3, FN_IP6_7_6, + + /* GPSR3 */ + FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13, + FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24, + FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9, + FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24, + FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7, + FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16, + FN_IP9_18_17, + + /* GPSR4 */ + FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25, + FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2, + FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5, + FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0, + FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15, + FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25, + FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, + FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4, + + /* GPSR5 */ + FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19, + FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24, + FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30, + FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10, + FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20, + FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3, + FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22, + + /* GPSR6 */ + FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14, + FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23, + FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0, + FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7, + FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17, + FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29, + + /* GPSR7 */ + FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24, + FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8, + FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, + FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27, + FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12, + FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, + + /* IPSR 0 -5 */ + + /* IPSR6 */ + FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, + FN_SCIF_CLK, FN_BPFCLK_E, + FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, + FN_SCIFA2_RXD, FN_FMIN_E, + FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, + FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, + FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, + FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, + FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, + FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, + FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E, + FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E, + FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D, + FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D, + + /* IPSR7 - IPSR10 */ + + /* IPSR11 */ + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, + FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, + FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, + FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B, + FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B, + FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, + FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, + FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5, + FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7, + FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO, + FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC, + FN_VI1_DATA7, FN_AVB_MDC, + FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, + FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, + + /* IPSR12 */ + FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, + FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, + FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, + FN_SCL2_D, FN_MSIOF1_RXD_E, + FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E, + FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, + FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, + FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, + FN_CAN1_TX_C, FN_MSIOF1_TXD_E, + FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, + FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, + FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, + FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, + FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, + FN_ADIDATA_B, FN_MSIOF0_SYNC_C, + FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, + FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, + + /* IPSR13 */ + FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, + FN_ADICLK_B, FN_MSIOF0_SS1_C, + FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, + FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, + FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, + FN_ADICHS2_B, FN_MSIOF0_TXD_C, + FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B, + FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B, + FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B, + FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, + FN_SCIFA5_TXD_B, FN_TX3_C, + FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, + FN_SCIFA5_RXD_B, FN_RX3_C, + FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B, + FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B, + FN_SD1_DATA3, FN_IERX_B, + FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C, + + /* IPSR14 */ + FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, + FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD, + FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1, + FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3, + FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C, + FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C, + FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B, + FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B, + FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B, + FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B, + FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, + FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, + FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, + FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, + + /* IPSR15 */ + FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, + FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, + FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, + FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, + FN_PWM5_B, FN_SCIFA3_TXD_C, + FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, + FN_VI1_G6_B, FN_SCIFA3_RXD_C, + FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, + FN_VI1_G7_B, FN_SCIFA3_SCK_C, + FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C, + FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C, + FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK, + FN_TCLK2, FN_VI1_DATA3_C, + FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C, + FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C, + + /* IPSR16 */ + FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C, + FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C, + FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C, + FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, + FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, + + /* MOD_SEL */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + FN_SEL_QSP_0, FN_SEL_QSP_1, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3, + FN_SEL_HSCIF1_4, + FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, + + /* MOD_SEL2 */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + FN_SEL_SCIF0_4, + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CAN0_4, FN_SEL_CAN0_5, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, + FN_SEL_ADG_0, FN_SEL_ADG_1, + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4, + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, + FN_SEL_SIM_0, FN_SEL_SIM_1, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, + + /* MOD_SEL3 */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, + FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, + FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, + FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, + FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_MMC_0, FN_SEL_MMC_1, + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, + FN_SEL_IIC1_4, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, + + /* MOD_SEL4 */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, + FN_SEL_SOF1_4, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, + FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, + FN_SEL_RAD_0, FN_SEL_RAD_1, + FN_SEL_RCN_0, FN_SEL_RCN_1, + FN_SEL_RSP_0, FN_SEL_RSP_1, + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, + FN_SEL_SCIF2_4, + FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, + FN_SEL_SOF2_4, + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + EX_CS0_N_MARK, RD_N_MARK, + + AUDIO_CLKA_MARK, + + VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK, + VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK, + VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK, + + USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, + + /* IPSR0 - 5 */ + + /* IPSR6 */ + AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK, + SCIF_CLK_MARK, BPFCLK_E_MARK, + AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, + SCIFA2_RXD_MARK, FMIN_E_MARK, + AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, + IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK, + IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK, + IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK, + IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK, + IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK, + MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK, + IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK, + IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK, + SDA1_E_MARK, MSIOF2_SYNC_E_MARK, + IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK, + GPS_CLK_C_MARK, GPS_CLK_D_MARK, + IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK, + GPS_SIGN_C_MARK, GPS_SIGN_D_MARK, + + /* IPSR7 - 10 */ + + /* IPSR11 */ + VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK, + VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK, + VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK, + SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, + VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK, + TX4_B_MARK, SCIFA4_TXD_B_MARK, + VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK, + RX4_B_MARK, SCIFA4_RXD_B_MARK, + VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK, + VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK, + VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK, + VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK, + VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK, + VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK, + VI1_DATA7_MARK, AVB_MDC_MARK, + ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK, + ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK, + + /* IPSR12 */ + ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK, + ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK, + ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK, + SCL2_D_MARK, MSIOF1_RXD_E_MARK, + ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK, + SDA2_D_MARK, MSIOF1_SCK_E_MARK, + ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK, + CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK, + ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK, + CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK, + ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK, + ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK, + ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK, + ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK, + STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK, + ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK, + STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK, + ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK, + + /* IPSR13 */ + STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK, + ADICLK_B_MARK, MSIOF0_SS1_C_MARK, + STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK, + STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK, + STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK, + ADICHS2_B_MARK, MSIOF0_TXD_C_MARK, + SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK, + SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK, + SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK, + SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK, + SCIFA5_TXD_B_MARK, TX3_C_MARK, + SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK, + SCIFA5_RXD_B_MARK, RX3_C_MARK, + SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK, + SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK, + SD1_DATA3_MARK, IERX_B_MARK, + SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK, + + /* IPSR14 */ + SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK, + SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK, + SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK, + SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK, + SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK, + SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK, + MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK, + VI1_CLK_C_MARK, VI1_G0_B_MARK, + MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK, + VI1_CLKENB_C_MARK, VI1_G1_B_MARK, + MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK, + MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK, + MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK, + VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK, + MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK, + VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK, + + /* IPSR15 */ + SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK, + SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK, + SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK, + GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK, + PWM5_B_MARK, SCIFA3_TXD_C_MARK, + GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK, + VI1_G6_B_MARK, SCIFA3_RXD_C_MARK, + GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK, + VI1_G7_B_MARK, SCIFA3_SCK_C_MARK, + HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK, + TCLK1_MARK, VI1_DATA1_C_MARK, + HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK, + HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK, + TCLK2_MARK, VI1_DATA3_C_MARK, + HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK, + CAN0_RX_B_MARK, VI1_DATA4_C_MARK, + HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK, + CAN0_TX_B_MARK, VI1_DATA5_C_MARK, + + /* IPSR16 */ + HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK, + GLO_SDATA_C_MARK, VI1_DATA6_C_MARK, + HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK, + GLO_SS_C_MARK, VI1_DATA7_C_MARK, + HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK, + HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK, + HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK, + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N), + PINMUX_DATA(RD_N_MARK, FN_RD_N), + PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA), + PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK), + PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0), + PINMUX_DATA(VI0_DATA0_VI0_B1_MARK, FN_VI0_DATA0_VI0_B1), + PINMUX_DATA(VI0_DATA0_VI0_B2_MARK, FN_VI0_DATA0_VI0_B2), + PINMUX_DATA(VI0_DATA0_VI0_B4_MARK, FN_VI0_DATA0_VI0_B4), + PINMUX_DATA(VI0_DATA0_VI0_B5_MARK, FN_VI0_DATA0_VI0_B5), + PINMUX_DATA(VI0_DATA0_VI0_B6_MARK, FN_VI0_DATA0_VI0_B6), + PINMUX_DATA(VI0_DATA0_VI0_B7_MARK, FN_VI0_DATA0_VI0_B7), + PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), + PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC), + PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN), + + /* IPSR0 - 5 */ + + /* IPSR6 */ + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4), + PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4), + PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT), + PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_DATA(IP6_9_8, IRQ0), + PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N), + PINMUX_IPSR_DATA(IP6_11_10, IRQ1), + PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), + PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N), + PINMUX_IPSR_DATA(IP6_13_12, IRQ2), + PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N), + PINMUX_IPSR_DATA(IP6_15_14, IRQ3), + PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2), + PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), + PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N), + PINMUX_IPSR_DATA(IP6_18_16, IRQ4), + PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2), + PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), + PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N), + PINMUX_IPSR_DATA(IP6_20_19, IRQ5), + PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4), + PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4), + PINMUX_IPSR_DATA(IP6_23_21, IRQ6), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4), + PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4), + PINMUX_IPSR_DATA(IP6_26_24, IRQ7), + PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3), + PINMUX_IPSR_DATA(IP6_29_27, IRQ8), + PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), + + /* IPSR7 - 10 */ + + /* IPSR11 */ + PINMUX_IPSR_DATA(IP11_2_0, VI0_R5), + PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3), + PINMUX_IPSR_DATA(IP11_5_3, VI0_R6), + PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1), + PINMUX_IPSR_DATA(IP11_8_6, VI0_R7), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2), + PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3), + PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_19, AVB_RXD4), + PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_20, AVB_RXD5), + PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_21, AVB_RXD6), + PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_22, AVB_RXD7), + PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_24, AVB_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV), + PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_27, AVB_MDC), + PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO), + PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2), + PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK), + PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2), + + /* IPSR12 */ + PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER), + PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0), + PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0), + PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0), + PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1), + PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK), + PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK), + PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1), + PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN), + PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC), + PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4), + PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0), + PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5), + PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC), + PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6), + PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), + + /* IPSR13 */ + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP13_6_5, AVB_COL), + PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK), + PINMUX_IPSR_DATA(IP13_9_7, PWM0_B), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2), + PINMUX_IPSR_DATA(IP13_10, SD0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_11, SD0_CMD), + PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_12, SD0_DATA0), + PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_13, SD0_DATA1), + PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_14, SD0_DATA2), + PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_15, SD0_DATA3), + PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1), + PINMUX_IPSR_DATA(IP13_18_16, SD0_CD), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2), + PINMUX_IPSR_DATA(IP13_21_19, SD0_WP), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2), + PINMUX_IPSR_DATA(IP13_22, SD1_CMD), + PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1), + PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0), + PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1), + PINMUX_IPSR_DATA(IP13_25, SD1_DATA1), + PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP13_26, SD1_DATA2), + PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP13_27, SD1_DATA3), + PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP13_30_28, SD1_CD), + PINMUX_IPSR_DATA(IP13_30_28, PWM0), + PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0), + PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2), + + /* IPSR14 */ + PINMUX_IPSR_DATA(IP14_1_0, SD1_WP), + PINMUX_IPSR_DATA(IP14_1_0, PWM1_B), + PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2), + PINMUX_IPSR_DATA(IP14_2, SD2_CLK), + PINMUX_IPSR_DATA(IP14_2, MMC_CLK), + PINMUX_IPSR_DATA(IP14_3, SD2_CMD), + PINMUX_IPSR_DATA(IP14_3, MMC_CMD), + PINMUX_IPSR_DATA(IP14_4, SD2_DATA0), + PINMUX_IPSR_DATA(IP14_4, MMC_D0), + PINMUX_IPSR_DATA(IP14_5, SD2_DATA1), + PINMUX_IPSR_DATA(IP14_5, MMC_D1), + PINMUX_IPSR_DATA(IP14_6, SD2_DATA2), + PINMUX_IPSR_DATA(IP14_6, MMC_D2), + PINMUX_IPSR_DATA(IP14_7, SD2_DATA3), + PINMUX_IPSR_DATA(IP14_7, MMC_D3), + PINMUX_IPSR_DATA(IP14_10_8, SD2_CD), + PINMUX_IPSR_DATA(IP14_10_8, MMC_D4), + PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2), + PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_DATA(IP14_13_11, SD2_WP), + PINMUX_IPSR_DATA(IP14_13_11, MMC_D5), + PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2), + PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2), + PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B), + PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2), + PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B), + PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2), + PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B), + PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2), + PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2), + PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2), + PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B), + + /* IPSR15 */ + PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3), + PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2), + PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP15_8_6, PWM5_B), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_DATA(IP15_11_9, PWM5), + PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2), + PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_DATA(IP15_14_12, PWM6), + PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B), + PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0), + PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0), + PINMUX_IPSR_DATA(IP15_23_21, TCLK2), + PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2), + + /* IPSR16 */ + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0), + PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0), + PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), + PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), + PINMUX_IPSR_DATA(IP16_7_6, MLB_CK), + PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N), + PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG), + PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N), + PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT), + PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + + GPIO_FN(EX_CS0_N), GPIO_FN(RD_N), GPIO_FN(AUDIO_CLKA), + GPIO_FN(VI0_CLK), GPIO_FN(VI0_DATA0_VI0_B0), + GPIO_FN(VI0_DATA0_VI0_B1), GPIO_FN(VI0_DATA0_VI0_B2), + GPIO_FN(VI0_DATA0_VI0_B4), GPIO_FN(VI0_DATA0_VI0_B5), + GPIO_FN(VI0_DATA0_VI0_B6), GPIO_FN(VI0_DATA0_VI0_B7), + GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN), + + /* IPSR0 - 5 */ + + /* IPSR6 */ + GPIO_FN(AUDIO_CLKB), GPIO_FN(STP_OPWM_0_B), GPIO_FN(MSIOF1_SCK_B), + GPIO_FN(SCIF_CLK), GPIO_FN(BPFCLK_E), + GPIO_FN(AUDIO_CLKC), GPIO_FN(SCIFB0_SCK_C), + GPIO_FN(MSIOF1_SYNC_B), GPIO_FN(RX2), + GPIO_FN(SCIFA2_RXD), GPIO_FN(FMIN_E), + GPIO_FN(AUDIO_CLKOUT), GPIO_FN(MSIOF1_SS1_B), + GPIO_FN(TX2), GPIO_FN(SCIFA2_TXD), + GPIO_FN(IRQ0), GPIO_FN(SCIFB1_RXD_D), GPIO_FN(INTC_IRQ0_N), + GPIO_FN(IRQ1), GPIO_FN(SCIFB1_SCK_C), GPIO_FN(INTC_IRQ1_N), + GPIO_FN(IRQ2), GPIO_FN(SCIFB1_TXD_D), GPIO_FN(INTC_IRQ2_N), + GPIO_FN(IRQ3), GPIO_FN(SCL4_C), + GPIO_FN(MSIOF2_TXD_E), GPIO_FN(INTC_IRQ3_N), + GPIO_FN(IRQ4), GPIO_FN(HRX1_C), GPIO_FN(SDA4_C), + GPIO_FN(MSIOF2_RXD_E), GPIO_FN(INTC_IRQ4_N), + GPIO_FN(IRQ5), GPIO_FN(HTX1_C), GPIO_FN(SCL1_E), GPIO_FN(MSIOF2_SCK_E), + GPIO_FN(IRQ6), GPIO_FN(HSCK1_C), GPIO_FN(MSIOF1_SS2_B), + GPIO_FN(SDA1_E), GPIO_FN(MSIOF2_SYNC_E), + GPIO_FN(IRQ7), GPIO_FN(HCTS1_N_C), GPIO_FN(MSIOF1_TXD_B), + GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), + GPIO_FN(IRQ8), GPIO_FN(HRTS1_N_C), GPIO_FN(MSIOF1_RXD_B), + GPIO_FN(GPS_SIGN_C), GPIO_FN(GPS_SIGN_D), + + /* IPSR7 - 10 */ + + /* IPSR11 */ + GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B), + GPIO_FN(RX0_C), GPIO_FN(SDA1_D), + GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7), + GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B), + GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B), + GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E), + GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D), + GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B), + GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B), + GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B), + GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B), + GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B), + GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B), + GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4), + GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5), + GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6), + GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7), + GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER), + GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO), + GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV), + GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC), + GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC), + GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C), + GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C), + + /* IPSR12 */ + GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7), + GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7), + GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C), + GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E), + GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C), + GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E), + GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B), + GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E), + GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B), + GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E), + GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3), + GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B), + GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C), + GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C), + GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C), + GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D), + GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C), + GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D), + GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C), + + /* IPSR13 */ + GPIO_FN(STP_ISD_0), GPIO_FN(AVB_TX_ER), GPIO_FN(SCIFB2_SCK_C), + GPIO_FN(ADICLK_B), GPIO_FN(MSIOF0_SS1_C), + GPIO_FN(STP_ISEN_0), GPIO_FN(AVB_TX_CLK), + GPIO_FN(ADICHS0_B), GPIO_FN(MSIOF0_SS2_C), + GPIO_FN(STP_ISSYNC_0), GPIO_FN(AVB_COL), + GPIO_FN(ADICHS1_B), GPIO_FN(MSIOF0_RXD_C), + GPIO_FN(STP_OPWM_0), GPIO_FN(AVB_GTX_CLK), GPIO_FN(PWM0_B), + GPIO_FN(ADICHS2_B), GPIO_FN(MSIOF0_TXD_C), + GPIO_FN(SD0_CLK), GPIO_FN(SPCLK_B), + GPIO_FN(SD0_CMD), GPIO_FN(MOSI_IO0_B), + GPIO_FN(SD0_DATA0), GPIO_FN(MISO_IO1_B), + GPIO_FN(SD0_DATA1), GPIO_FN(IO2_B), + GPIO_FN(SD0_DATA2), GPIO_FN(IO3_B), GPIO_FN(SD0_DATA3), GPIO_FN(SSL_B), + GPIO_FN(SD0_CD), GPIO_FN(MMC_D6_B), + GPIO_FN(SIM0_RST_B), GPIO_FN(CAN0_RX_F), + GPIO_FN(SCIFA5_TXD_B), GPIO_FN(TX3_C), + GPIO_FN(SD0_WP), GPIO_FN(MMC_D7_B), + GPIO_FN(SIM0_D_B), GPIO_FN(CAN0_TX_F), + GPIO_FN(SCIFA5_RXD_B), GPIO_FN(RX3_C), + GPIO_FN(SD1_CMD), GPIO_FN(REMOCON_B), + GPIO_FN(SD1_DATA0), GPIO_FN(SPEEDIN_B), + GPIO_FN(SD1_DATA1), GPIO_FN(IETX_B), + GPIO_FN(SD1_DATA2), GPIO_FN(IECLK_B), + GPIO_FN(SD1_DATA3), GPIO_FN(IERX_B), + GPIO_FN(SD1_CD), GPIO_FN(PWM0), GPIO_FN(TPU_TO0), GPIO_FN(SCL1_C), + + /* IPSR14 */ + GPIO_FN(SD1_WP), GPIO_FN(PWM1_B), GPIO_FN(SDA1_C), + GPIO_FN(SD2_CLK), GPIO_FN(MMC_CLK), GPIO_FN(SD2_CMD), GPIO_FN(MMC_CMD), + GPIO_FN(SD2_DATA0), GPIO_FN(MMC_D0), + GPIO_FN(SD2_DATA1), GPIO_FN(MMC_D1), + GPIO_FN(SD2_DATA2), GPIO_FN(MMC_D2), + GPIO_FN(SD2_DATA3), GPIO_FN(MMC_D3), + GPIO_FN(SD2_CD), GPIO_FN(MMC_D4), GPIO_FN(SCL8_C), + GPIO_FN(TX5_B), GPIO_FN(SCIFA5_TXD_C), + GPIO_FN(SD2_WP), GPIO_FN(MMC_D5), GPIO_FN(SDA8_C), + GPIO_FN(RX5_B), GPIO_FN(SCIFA5_RXD_C), + GPIO_FN(MSIOF0_SCK), GPIO_FN(RX2_C), GPIO_FN(ADIDATA), + GPIO_FN(VI1_CLK_C), GPIO_FN(VI1_G0_B), + GPIO_FN(MSIOF0_SYNC), GPIO_FN(TX2_C), GPIO_FN(ADICS_SAMP), + GPIO_FN(VI1_CLKENB_C), GPIO_FN(VI1_G1_B), + GPIO_FN(MSIOF0_TXD), GPIO_FN(ADICLK), + GPIO_FN(VI1_FIELD_C), GPIO_FN(VI1_G2_B), + GPIO_FN(MSIOF0_RXD), GPIO_FN(ADICHS0), + GPIO_FN(VI1_DATA0_C), GPIO_FN(VI1_G3_B), + GPIO_FN(MSIOF0_SS1), GPIO_FN(MMC_D6), GPIO_FN(ADICHS1), GPIO_FN(TX0_E), + GPIO_FN(VI1_HSYNC_N_C), GPIO_FN(SCL7_C), GPIO_FN(VI1_G4_B), + GPIO_FN(MSIOF0_SS2), GPIO_FN(MMC_D7), GPIO_FN(ADICHS2), GPIO_FN(RX0_E), + GPIO_FN(VI1_VSYNC_N_C), GPIO_FN(SDA7_C), GPIO_FN(VI1_G5_B), + + /* IPSR15 */ + GPIO_FN(SIM0_RST), GPIO_FN(IETX), GPIO_FN(CAN1_TX_D), + GPIO_FN(SIM0_CLK), GPIO_FN(IECLK), GPIO_FN(CAN_CLK_C), + GPIO_FN(SIM0_D), GPIO_FN(IERX), GPIO_FN(CAN1_RX_D), + GPIO_FN(GPS_CLK), GPIO_FN(DU1_DOTCLKIN_C), GPIO_FN(AUDIO_CLKB_B), + GPIO_FN(PWM5_B), GPIO_FN(SCIFA3_TXD_C), + GPIO_FN(GPS_SIGN), GPIO_FN(TX4_C), + GPIO_FN(SCIFA4_TXD_C), GPIO_FN(PWM5), + GPIO_FN(VI1_G6_B), GPIO_FN(SCIFA3_RXD_C), + GPIO_FN(GPS_MAG), GPIO_FN(RX4_C), GPIO_FN(SCIFA4_RXD_C), GPIO_FN(PWM6), + GPIO_FN(VI1_G7_B), GPIO_FN(SCIFA3_SCK_C), + GPIO_FN(HCTS0_N), GPIO_FN(SCIFB0_CTS_N), GPIO_FN(GLO_I0_C), + GPIO_FN(TCLK1), GPIO_FN(VI1_DATA1_C), + GPIO_FN(HRTS0_N), GPIO_FN(SCIFB0_RTS_N), + GPIO_FN(GLO_I1_C), GPIO_FN(VI1_DATA2_C), + GPIO_FN(HSCK0), GPIO_FN(SCIFB0_SCK), + GPIO_FN(GLO_Q0_C), GPIO_FN(CAN_CLK), + GPIO_FN(TCLK2), GPIO_FN(VI1_DATA3_C), + GPIO_FN(HRX0), GPIO_FN(SCIFB0_RXD), GPIO_FN(GLO_Q1_C), + GPIO_FN(CAN0_RX_B), GPIO_FN(VI1_DATA4_C), + GPIO_FN(HTX0), GPIO_FN(SCIFB0_TXD), GPIO_FN(GLO_SCLK_C), + GPIO_FN(CAN0_TX_B), GPIO_FN(VI1_DATA5_C), + + /* IPSR16 */ + GPIO_FN(HRX1), GPIO_FN(SCIFB1_RXD), GPIO_FN(VI1_R0_B), + GPIO_FN(GLO_SDATA_C), GPIO_FN(VI1_DATA6_C), + GPIO_FN(HTX1), GPIO_FN(SCIFB1_TXD), GPIO_FN(VI1_R1_B), + GPIO_FN(GLO_SS_C), GPIO_FN(VI1_DATA7_C), + GPIO_FN(HSCK1), GPIO_FN(SCIFB1_SCK), + GPIO_FN(MLB_CK), GPIO_FN(GLO_RFON_C), + GPIO_FN(HCTS1_N), GPIO_FN(SCIFB1_CTS_N), + GPIO_FN(MLB_SIG), GPIO_FN(CAN1_TX_B), + GPIO_FN(HRTS1_N), GPIO_FN(SCIFB1_RTS_N), + GPIO_FN(MLB_DAT), GPIO_FN(CAN1_RX_B), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP1_22_20, + GP_0_30_FN, FN_IP1_19_17, + GP_0_29_FN, FN_IP1_16_14, + GP_0_28_FN, FN_IP1_13_11, + GP_0_27_FN, FN_IP1_10_8, + GP_0_26_FN, FN_IP1_7_6, + GP_0_25_FN, FN_IP1_5_4, + GP_0_24_FN, FN_IP1_3_2, + GP_0_23_FN, FN_IP1_1_0, + GP_0_22_FN, FN_IP0_30_29, + GP_0_21_FN, FN_IP0_28_27, + GP_0_20_FN, FN_IP0_26_25, + GP_0_19_FN, FN_IP0_24_23, + GP_0_18_FN, FN_IP0_22_21, + GP_0_17_FN, FN_IP0_20_19, + GP_0_16_FN, FN_IP0_18_16, + GP_0_15_FN, FN_IP0_15, + GP_0_14_FN, FN_IP0_14, + GP_0_13_FN, FN_IP0_13, + GP_0_12_FN, FN_IP0_12, + GP_0_11_FN, FN_IP0_11, + GP_0_10_FN, FN_IP0_10, + GP_0_9_FN, FN_IP0_9, + GP_0_8_FN, FN_IP0_8, + GP_0_7_FN, FN_IP0_7, + GP_0_6_FN, FN_IP0_6, + GP_0_5_FN, FN_IP0_5, + GP_0_4_FN, FN_IP0_4, + GP_0_3_FN, FN_IP0_3, + GP_0_2_FN, FN_IP0_2, + GP_0_1_FN, FN_IP0_1, + GP_0_0_FN, FN_IP0_0, } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_FN, FN_IP3_21_20, + GP_1_24_FN, FN_IP3_19_18, + GP_1_23_FN, FN_IP3_17_16, + GP_1_22_FN, FN_IP3_15_14, + GP_1_21_FN, FN_IP3_13_12, + GP_1_20_FN, FN_IP3_11_9, + GP_1_19_FN, FN_RD_N, + GP_1_18_FN, FN_IP3_8_6, + GP_1_17_FN, FN_IP3_5_3, + GP_1_16_FN, FN_IP3_2_0, + GP_1_15_FN, FN_IP2_29_27, + GP_1_14_FN, FN_IP2_26_25, + GP_1_13_FN, FN_IP2_24_23, + GP_1_12_FN, FN_EX_CS0_N, + GP_1_11_FN, FN_IP2_22_21, + GP_1_10_FN, FN_IP2_20_19, + GP_1_9_FN, FN_IP2_18_16, + GP_1_8_FN, FN_IP2_15_13, + GP_1_7_FN, FN_IP2_12_10, + GP_1_6_FN, FN_IP2_9_7, + GP_1_5_FN, FN_IP2_6_5, + GP_1_4_FN, FN_IP2_4_3, + GP_1_3_FN, FN_IP2_2_0, + GP_1_2_FN, FN_IP1_31_29, + GP_1_1_FN, FN_IP1_28_26, + GP_1_0_FN, FN_IP1_25_23, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + GP_2_31_FN, FN_IP6_7_6, + GP_2_30_FN, FN_IP6_5_3, + GP_2_29_FN, FN_IP6_2_0, + GP_2_28_FN, FN_AUDIO_CLKA, + GP_2_27_FN, FN_IP5_31_29, + GP_2_26_FN, FN_IP5_28_26, + GP_2_25_FN, FN_IP5_25_24, + GP_2_24_FN, FN_IP5_23_22, + GP_2_23_FN, FN_IP5_21_20, + GP_2_22_FN, FN_IP5_19_17, + GP_2_21_FN, FN_IP5_16_15, + GP_2_20_FN, FN_IP5_14_12, + GP_2_19_FN, FN_IP5_11_9, + GP_2_18_FN, FN_IP5_8_6, + GP_2_17_FN, FN_IP5_5_3, + GP_2_16_FN, FN_IP5_2_0, + GP_2_15_FN, FN_IP4_30_28, + GP_2_14_FN, FN_IP4_27_26, + GP_2_13_FN, FN_IP4_25_24, + GP_2_12_FN, FN_IP4_23_22, + GP_2_11_FN, FN_IP4_21, + GP_2_10_FN, FN_IP4_20, + GP_2_9_FN, FN_IP4_19, + GP_2_8_FN, FN_IP4_18_16, + GP_2_7_FN, FN_IP4_15_13, + GP_2_6_FN, FN_IP4_12_10, + GP_2_5_FN, FN_IP4_9_8, + GP_2_4_FN, FN_IP4_7_5, + GP_2_3_FN, FN_IP4_4_2, + GP_2_2_FN, FN_IP4_1_0, + GP_2_1_FN, FN_IP3_30_28, + GP_2_0_FN, FN_IP3_27_25 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP9_18_17, + GP_3_30_FN, FN_IP9_16, + GP_3_29_FN, FN_IP9_15_13, + GP_3_28_FN, FN_IP9_12, + GP_3_27_FN, FN_IP9_11, + GP_3_26_FN, FN_IP9_10_8, + GP_3_25_FN, FN_IP9_7, + GP_3_24_FN, FN_IP9_6, + GP_3_23_FN, FN_IP9_5_3, + GP_3_22_FN, FN_IP9_2_0, + GP_3_21_FN, FN_IP8_30_28, + GP_3_20_FN, FN_IP8_27_26, + GP_3_19_FN, FN_IP8_25_24, + GP_3_18_FN, FN_IP8_23_21, + GP_3_17_FN, FN_IP8_20_18, + GP_3_16_FN, FN_IP8_17_15, + GP_3_15_FN, FN_IP8_14_12, + GP_3_14_FN, FN_IP8_11_9, + GP_3_13_FN, FN_IP8_8_6, + GP_3_12_FN, FN_IP8_5_3, + GP_3_11_FN, FN_IP8_2_0, + GP_3_10_FN, FN_IP7_29_27, + GP_3_9_FN, FN_IP7_26_24, + GP_3_8_FN, FN_IP7_23_21, + GP_3_7_FN, FN_IP7_20_19, + GP_3_6_FN, FN_IP7_18_17, + GP_3_5_FN, FN_IP7_16_15, + GP_3_4_FN, FN_IP7_14_13, + GP_3_3_FN, FN_IP7_12_11, + GP_3_2_FN, FN_IP7_10_9, + GP_3_1_FN, FN_IP7_8_6, + GP_3_0_FN, FN_IP7_5_3 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP15_5_4, + GP_4_30_FN, FN_IP15_3_2, + GP_4_29_FN, FN_IP15_1_0, + GP_4_28_FN, FN_IP11_8_6, + GP_4_27_FN, FN_IP11_5_3, + GP_4_26_FN, FN_IP11_2_0, + GP_4_25_FN, FN_IP10_31_29, + GP_4_24_FN, FN_IP10_28_27, + GP_4_23_FN, FN_IP10_26_25, + GP_4_22_FN, FN_IP10_24_22, + GP_4_21_FN, FN_IP10_21_19, + GP_4_20_FN, FN_IP10_18_17, + GP_4_19_FN, FN_IP10_16_15, + GP_4_18_FN, FN_IP10_14_12, + GP_4_17_FN, FN_IP10_11_9, + GP_4_16_FN, FN_IP10_8_6, + GP_4_15_FN, FN_IP10_5_3, + GP_4_14_FN, FN_IP10_2_0, + GP_4_13_FN, FN_IP9_31_29, + GP_4_12_FN, FN_VI0_DATA0_VI0_B7, + GP_4_11_FN, FN_VI0_DATA0_VI0_B6, + GP_4_10_FN, FN_VI0_DATA0_VI0_B5, + GP_4_9_FN, FN_VI0_DATA0_VI0_B4, + GP_4_8_FN, FN_IP9_28_27, + GP_4_7_FN, FN_VI0_DATA0_VI0_B2, + GP_4_6_FN, FN_VI0_DATA0_VI0_B1, + GP_4_5_FN, FN_VI0_DATA0_VI0_B0, + GP_4_4_FN, FN_IP9_26_25, + GP_4_3_FN, FN_IP9_24_23, + GP_4_2_FN, FN_IP9_22_21, + GP_4_1_FN, FN_IP9_20_19, + GP_4_0_FN, FN_VI0_CLK } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + GP_5_31_FN, FN_IP3_24_22, + GP_5_30_FN, FN_IP13_9_7, + GP_5_29_FN, FN_IP13_6_5, + GP_5_28_FN, FN_IP13_4_3, + GP_5_27_FN, FN_IP13_2_0, + GP_5_26_FN, FN_IP12_29_27, + GP_5_25_FN, FN_IP12_26_24, + GP_5_24_FN, FN_IP12_23_22, + GP_5_23_FN, FN_IP12_21_20, + GP_5_22_FN, FN_IP12_19_18, + GP_5_21_FN, FN_IP12_17_16, + GP_5_20_FN, FN_IP12_15_13, + GP_5_19_FN, FN_IP12_12_10, + GP_5_18_FN, FN_IP12_9_7, + GP_5_17_FN, FN_IP12_6_4, + GP_5_16_FN, FN_IP12_3_2, + GP_5_15_FN, FN_IP12_1_0, + GP_5_14_FN, FN_IP11_31_30, + GP_5_13_FN, FN_IP11_29_28, + GP_5_12_FN, FN_IP11_27, + GP_5_11_FN, FN_IP11_26, + GP_5_10_FN, FN_IP11_25, + GP_5_9_FN, FN_IP11_24, + GP_5_8_FN, FN_IP11_23, + GP_5_7_FN, FN_IP11_22, + GP_5_6_FN, FN_IP11_21, + GP_5_5_FN, FN_IP11_20, + GP_5_4_FN, FN_IP11_19, + GP_5_3_FN, FN_IP11_18_17, + GP_5_2_FN, FN_IP11_16_15, + GP_5_1_FN, FN_IP11_14_12, + GP_5_0_FN, FN_IP11_11_9 } + }, + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + 0, 0, + 0, 0, + GP_6_29_FN, FN_IP14_31_29, + GP_6_28_FN, FN_IP14_28_26, + GP_6_27_FN, FN_IP14_25_23, + GP_6_26_FN, FN_IP14_22_20, + GP_6_25_FN, FN_IP14_19_17, + GP_6_24_FN, FN_IP14_16_14, + GP_6_23_FN, FN_IP14_13_11, + GP_6_22_FN, FN_IP14_10_8, + GP_6_21_FN, FN_IP14_7, + GP_6_20_FN, FN_IP14_6, + GP_6_19_FN, FN_IP14_5, + GP_6_18_FN, FN_IP14_4, + GP_6_17_FN, FN_IP14_3, + GP_6_16_FN, FN_IP14_2, + GP_6_15_FN, FN_IP14_1_0, + GP_6_14_FN, FN_IP13_30_28, + GP_6_13_FN, FN_IP13_27, + GP_6_12_FN, FN_IP13_26, + GP_6_11_FN, FN_IP13_25, + GP_6_10_FN, FN_IP13_24_23, + GP_6_9_FN, FN_IP13_22, + 0, 0, + GP_6_7_FN, FN_IP13_21_19, + GP_6_6_FN, FN_IP13_18_16, + GP_6_5_FN, FN_IP13_15, + GP_6_4_FN, FN_IP13_14, + GP_6_3_FN, FN_IP13_13, + GP_6_2_FN, FN_IP13_12, + GP_6_1_FN, FN_IP13_11, + GP_6_0_FN, FN_IP13_10 } + }, + { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_25_FN, FN_USB1_PWEN, + GP_7_24_FN, FN_USB0_OVC, + GP_7_23_FN, FN_USB0_PWEN, + GP_7_22_FN, FN_IP15_14_12, + GP_7_21_FN, FN_IP15_11_9, + GP_7_20_FN, FN_IP15_8_6, + GP_7_19_FN, FN_IP7_2_0, + GP_7_18_FN, FN_IP6_29_27, + GP_7_17_FN, FN_IP6_26_24, + GP_7_16_FN, FN_IP6_23_21, + GP_7_15_FN, FN_IP6_20_19, + GP_7_14_FN, FN_IP6_18_16, + GP_7_13_FN, FN_IP6_15_14, + GP_7_12_FN, FN_IP6_13_12, + GP_7_11_FN, FN_IP6_11_10, + GP_7_10_FN, FN_IP6_9_8, + GP_7_9_FN, FN_IP16_11_10, + GP_7_8_FN, FN_IP16_9_8, + GP_7_7_FN, FN_IP16_7_6, + GP_7_6_FN, FN_IP16_5_3, + GP_7_5_FN, FN_IP16_2_0, + GP_7_4_FN, FN_IP15_29_27, + GP_7_3_FN, FN_IP15_26_24, + GP_7_2_FN, FN_IP15_23_21, + GP_7_1_FN, FN_IP15_20_18, + GP_7_0_FN, FN_IP15_17_15 } + }, + + /* IPSR0 - 5 */ + + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) { + /* IP6_31_30 [2] */ + 0, 0, 0, 0, + /* IP6_29_27 [3] */ + FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, + FN_GPS_SIGN_C, FN_GPS_SIGN_D, + 0, 0, 0, + /* IP6_26_24 [3] */ + FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, + FN_GPS_CLK_C, FN_GPS_CLK_D, + 0, 0, 0, + /* IP6_23_21 [3] */ + FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, + FN_SDA1_E, FN_MSIOF2_SYNC_E, + 0, 0, 0, + /* IP6_20_19 [2] */ + FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E, + /* IP6_18_16 [3] */ + FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, + 0, 0, 0, + /* IP6_15_14 [2] */ + FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, + /* IP6_13_12 [2] */ + FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0, + /* IP6_11_10 [2] */ + FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0, + /* IP6_9_8 [2] */ + FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0, + /* IP6_7_6 [2] */ + FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, + /* IP6_5_3 [3] */ + FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, + FN_SCIFA2_RXD, FN_FMIN_E, + 0, 0, + /* IP6_2_0 [3] */ + FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, + FN_SCIF_CLK, 0, FN_BPFCLK_E, + 0, 0, } + }, + + /* IPSR7 - 10 */ + + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, + 3, 3, 3, 3, 3) { + /* IP11_31_30 [2] */ + FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0, + /* IP11_29_28 [2] */ + FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0, + /* IP11_27 [1] */ + FN_VI1_DATA7, FN_AVB_MDC, + /* IP11_26 [1] */ + FN_VI1_DATA6, FN_AVB_MAGIC, + /* IP11_25 [1] */ + FN_VI1_DATA5, FN_AVB_RX_DV, + /* IP11_24 [1] */ + FN_VI1_DATA4, FN_AVB_MDIO, + /* IP11_23 [1] */ + FN_VI1_DATA3, FN_AVB_RX_ER, + /* IP11_22 [1] */ + FN_VI1_DATA2, FN_AVB_RXD7, + /* IP11_21 [1] */ + FN_VI1_DATA1, FN_AVB_RXD6, + /* IP11_20 [1] */ + FN_VI1_DATA0, FN_AVB_RXD5, + /* IP11_19 [1] */ + FN_VI1_CLK, FN_AVB_RXD4, + /* IP11_18_17 [2] */ + FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0, + /* IP11_16_15 [2] */ + FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0, + /* IP11_14_12 [3] */ + FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, + FN_RX4_B, FN_SCIFA4_RXD_B, + 0, 0, 0, + /* IP11_11_9 [3] */ + FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, + FN_TX4_B, FN_SCIFA4_TXD_B, + 0, 0, 0, + /* IP11_8_6 [3] */ + FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, + FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0, + /* IP11_5_3 [3] */ + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, + 0, 0, 0, + /* IP11_2_0 [3] */ + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, + 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) { + /* IP12_31_30 [2] */ + 0, 0, 0, 0, + /* IP12_29_27 [3] */ + FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, + FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, + 0, 0, 0, + /* IP12_26_24 [3] */ + FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, + FN_ADIDATA_B, FN_MSIOF0_SYNC_C, + 0, 0, 0, + /* IP12_23_22 [2] */ + FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0, + /* IP12_21_20 [2] */ + FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0, + /* IP12_19_18 [2] */ + FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0, + /* IP12_17_16 [2] */ + FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, + /* IP12_15_13 [3] */ + FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, + FN_CAN1_TX_C, FN_MSIOF1_TXD_E, + 0, 0, 0, + /* IP12_12_10 [3] */ + FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, + FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, + 0, 0, 0, + /* IP12_9_7 [3] */ + FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, + FN_SDA2_D, FN_MSIOF1_SCK_E, + 0, 0, 0, + /* IP12_6_4 [3] */ + FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, + FN_SCL2_D, FN_MSIOF1_RXD_E, + 0, 0, 0, + /* IP12_3_2 [2] */ + FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, + /* IP12_1_0 [2] */ + FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, } + }, + { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, + 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1, + 3, 2, 2, 3) { + /* IP13_31 [1] */ + 0, 0, + /* IP13_30_28 [3] */ + FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C, + 0, 0, 0, 0, + /* IP13_27 [1] */ + FN_SD1_DATA3, FN_IERX_B, + /* IP13_26 [1] */ + FN_SD1_DATA2, FN_IECLK_B, + /* IP13_25 [1] */ + FN_SD1_DATA1, FN_IETX_B, + /* IP13_24_23 [2] */ + FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0, + /* IP13_22 [1] */ + FN_SD1_CMD, FN_REMOCON_B, + /* IP13_21_19 [3] */ + FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, + FN_SCIFA5_RXD_B, FN_RX3_C, + 0, 0, + /* IP13_18_16 [3] */ + FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, + FN_SCIFA5_TXD_B, FN_TX3_C, + 0, 0, + /* IP13_15 [1] */ + FN_SD0_DATA3, FN_SSL_B, + /* IP13_14 [1] */ + FN_SD0_DATA2, FN_IO3_B, + /* IP13_13 [1] */ + FN_SD0_DATA1, FN_IO2_B, + /* IP13_12 [1] */ + FN_SD0_DATA0, FN_MISO_IO1_B, + /* IP13_11 [1] */ + FN_SD0_CMD, FN_MOSI_IO0_B, + /* IP13_10 [1] */ + FN_SD0_CLK, FN_SPCLK_B, + /* IP13_9_7 [3] */ + FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, + FN_ADICHS2_B, FN_MSIOF0_TXD_C, + 0, 0, 0, + /* IP13_6_5 [2] */ + FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, + /* IP13_4_3 [2] */ + FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, + /* IP13_2_0 [3] */ + FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, + FN_ADICLK_B, FN_MSIOF0_SS1_C, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, + 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) { + /* IP14_31_29 [3] */ + FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, + FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0, + /* IP14_28_26 [3] */ + FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, + FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0, + /* IP14_25_23 [3] */ + FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B, + 0, 0, 0, + /* IP14_22_20 [3] */ + FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B, + 0, 0, 0, + /* IP14_19_17 [3] */ + FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0, + FN_VI1_CLKENB_C, FN_VI1_G1_B, + 0, 0, + /* IP14_16_14 [3] */ + FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0, + FN_VI1_CLK_C, FN_VI1_G0_B, + 0, 0, + /* IP14_13_11 [3] */ + FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C, + 0, 0, 0, + /* IP14_10_8 [3] */ + FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C, + 0, 0, 0, + /* IP14_7 [1] */ + FN_SD2_DATA3, FN_MMC_D3, + /* IP14_6 [1] */ + FN_SD2_DATA2, FN_MMC_D2, + /* IP14_5 [1] */ + FN_SD2_DATA1, FN_MMC_D1, + /* IP14_4 [1] */ + FN_SD2_DATA0, FN_MMC_D0, + /* IP14_3 [1] */ + FN_SD2_CMD, FN_MMC_CMD, + /* IP14_2 [1] */ + FN_SD2_CLK, FN_MMC_CLK, + /* IP14_1_0 [2] */ + FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, + 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) { + /* IP15_31_30 [2] */ + 0, 0, 0, 0, + /* IP15_29_27 [3] */ + FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C, + FN_CAN0_TX_B, FN_VI1_DATA5_C, + 0, 0, + /* IP15_26_24 [3] */ + FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C, + FN_CAN0_RX_B, FN_VI1_DATA4_C, + 0, 0, + /* IP15_23_21 [3] */ + FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK, + FN_TCLK2, FN_VI1_DATA3_C, 0, + /* IP15_20_18 [3] */ + FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C, + 0, 0, 0, + /* IP15_17_15 [3] */ + FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C, + FN_TCLK1, FN_VI1_DATA1_C, + 0, 0, + /* IP15_14_12 [3] */ + FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, + FN_VI1_G7_B, FN_SCIFA3_SCK_C, + 0, 0, + /* IP15_11_9 [3] */ + FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, + FN_VI1_G6_B, FN_SCIFA3_RXD_C, + 0, 0, + /* IP15_8_6 [3] */ + FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, + FN_PWM5_B, FN_SCIFA3_TXD_C, + 0, 0, 0, + /* IP15_5_4 [2] */ + FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0, + /* IP15_3_2 [2] */ + FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0, + /* IP15_1_0 [2] */ + FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, + 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) { + /* IP16_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_27_24 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_23_20 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_19_16 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_15_12 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_11_10 [2] */ + FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, + /* IP16_9_8 [2] */ + FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, + /* IP16_7_6 [2] */ + FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C, + /* IP16_5_3 [3] */ + FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, + FN_GLO_SS_C, FN_VI1_DATA7_C, + 0, 0, 0, + /* IP16_2_0 [3] */ + FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, + FN_GLO_SDATA_C, FN_VI1_DATA6_C, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, + 3, 2, 2, 2, 1, 2, 2, 2) { + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIF1 [2] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + /* SEL_SCIFB [2] */ + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, + /* SEL_SCIFB2 [2] */ + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, + FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, + /* SEL_SCIFB1 [3] */ + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, + FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + 0, 0, 0, 0, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, + /* SEL_SSI9 [1] */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + /* SEL_SCFA [1] */ + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + /* SEL_QSP [1] */ + FN_SEL_QSP_0, FN_SEL_QSP_1, + /* SEL_SSI7 [1] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + /* SEL_HSCIF1 [3] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, + FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, + 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_VI1 [2] */ + FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_TMU [1] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + /* SEL_LBS [2] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_SOF0 [2] */ + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 3, 1, 1, 3, 2, 1, 1, 2, 2, + 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) { + /* SEL_SCIF0 [3] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, + FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, + 0, 0, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIF [1] */ + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + /* SEL_CAN0 [3] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CAN0_4, FN_SEL_CAN0_5, + 0, 0, + /* SEL_CAN1 [2] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIFA2 [1] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + /* SEL_SCIF4 [2] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_ADG [1] */ + FN_SEL_ADG_0, FN_SEL_ADG_1, + /* SEL_FM [3] */ + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, + FN_SEL_FM_3, FN_SEL_FM_4, + 0, 0, 0, + /* SEL_SCIFA5 [2] */ + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_GPS [2] */ + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + /* SEL_SCIFA4 [2] */ + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0, + /* SEL_SCIFA3 [2] */ + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, + /* SEL_SIM [1] */ + FN_SEL_SIM_0, FN_SEL_SIM_1, + /* RESEVED [1] */ + 0, 0, + /* SEL_SSI8 [1] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 2, 2, 2, 2, 2, 2, 2, 2, + 1, 1, 2, 2, 3, 2, 2, 2, 1) { + /* SEL_HSCIF2 [2] */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, + FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, + /* SEL_CANCLK [2] */ + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, + /* SEL_IIC8 [2] */ + FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0, + /* SEL_IIC7 [2] */ + FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0, + /* SEL_IIC4 [2] */ + FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0, + /* SEL_IIC3 [2] */ + FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, + /* SEL_SCIF3 [2] */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, + /* SEL_MMC [1] */ + FN_SEL_MMC_0, FN_SEL_MMC_1, + /* SEL_SCIF5 [1] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_IIC2 [2] */ + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + /* SEL_IIC1 [3] */ + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, + FN_SEL_IIC1_4, + 0, 0, 0, + /* SEL_IIC0 [2] */ + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [1] */ + 0, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, + 3, 2, 2, 1, 1, 1, 1, 3, 2, + 2, 3, 1, 1, 1, 2, 2, 2, 2) { + /* SEL_SOF1 [3] */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, + FN_SEL_SOF1_4, + 0, 0, 0, + /* SEL_HSCIF0 [2] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, + /* SEL_DIS [2] */ + FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_RAD [1] */ + FN_SEL_RAD_0, FN_SEL_RAD_1, + /* SEL_RCN [1] */ + FN_SEL_RCN_0, FN_SEL_RCN_1, + /* SEL_RSP [1] */ + FN_SEL_RSP_0, FN_SEL_RSP_1, + /* SEL_SCIF2 [3] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, + FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, + 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_SOF2 [3] */ + FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, + FN_SEL_SOF2_3, FN_SEL_SOF2_4, + 0, 0, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_SSI1 [1] */ + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + /* SEL_SSI0 [1] */ + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + /* SEL_SSP [2] */ + FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, + { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_IN, GP_1_25_OUT, + GP_1_24_IN, GP_1_24_OUT, + GP_1_23_IN, GP_1_23_OUT, + GP_1_22_IN, GP_1_22_OUT, + GP_1_21_IN, GP_1_21_OUT, + GP_1_20_IN, GP_1_20_OUT, + GP_1_19_IN, GP_1_19_OUT, + GP_1_18_IN, GP_1_18_OUT, + GP_1_17_IN, GP_1_17_OUT, + GP_1_16_IN, GP_1_16_OUT, + GP_1_15_IN, GP_1_15_OUT, + GP_1_14_IN, GP_1_14_OUT, + GP_1_13_IN, GP_1_13_OUT, + GP_1_12_IN, GP_1_12_OUT, + GP_1_11_IN, GP_1_11_OUT, + GP_1_10_IN, GP_1_10_OUT, + GP_1_9_IN, GP_1_9_OUT, + GP_1_8_IN, GP_1_8_OUT, + GP_1_7_IN, GP_1_7_OUT, + GP_1_6_IN, GP_1_6_OUT, + GP_1_5_IN, GP_1_5_OUT, + GP_1_4_IN, GP_1_4_OUT, + GP_1_3_IN, GP_1_3_OUT, + GP_1_2_IN, GP_1_2_OUT, + GP_1_1_IN, GP_1_1_OUT, + GP_1_0_IN, GP_1_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } }, + { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, + { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, + { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } }, + { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } }, + { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_25_IN, GP_7_25_OUT, + GP_7_24_IN, GP_7_24_OUT, + GP_7_23_IN, GP_7_23_OUT, + GP_7_22_IN, GP_7_22_OUT, + GP_7_21_IN, GP_7_21_OUT, + GP_7_20_IN, GP_7_20_OUT, + GP_7_19_IN, GP_7_19_OUT, + GP_7_18_IN, GP_7_18_OUT, + GP_7_17_IN, GP_7_17_OUT, + GP_7_16_IN, GP_7_16_OUT, + GP_7_15_IN, GP_7_15_OUT, + GP_7_14_IN, GP_7_14_OUT, + GP_7_13_IN, GP_7_13_OUT, + GP_7_12_IN, GP_7_12_OUT, + GP_7_11_IN, GP_7_11_OUT, + GP_7_10_IN, GP_7_10_OUT, + GP_7_9_IN, GP_7_9_OUT, + GP_7_8_IN, GP_7_8_OUT, + GP_7_7_IN, GP_7_7_OUT, + GP_7_6_IN, GP_7_6_OUT, + GP_7_5_IN, GP_7_5_OUT, + GP_7_4_IN, GP_7_4_OUT, + GP_7_3_IN, GP_7_3_OUT, + GP_7_2_IN, GP_7_2_OUT, + GP_7_1_IN, GP_7_1_OUT, + GP_7_0_IN, GP_7_0_OUT, } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } }, + { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { + 0, 0, 0, 0, + 0, 0, GP_1_25_DATA, GP_1_24_DATA, + GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, + GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, + GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, + GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, + GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, + GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } + }, + { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } }, + { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } }, + { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } }, + { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } }, + { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } }, + { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) { + 0, 0, 0, 0, + 0, 0, GP_7_25_DATA, GP_7_24_DATA, + GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA, + GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA, + GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA, + GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA, + GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA, + GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA } + }, + { }, +}; + +static struct pinmux_info r8a7793_pinmux_info = { + .name = "r8a7793_pfc", + + .unlock_reg = 0xe6060000, /* PMMR */ + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_CAN1_RX_B, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7793_pinmux_init(void) +{ + register_pinmux(&r8a7793_pinmux_info); +} diff --git a/arch/arm/cpu/armv7/stv0991/Makefile b/arch/arm/cpu/armv7/stv0991/Makefile new file mode 100644 index 0000000..95641d3 --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 +# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := timer.o clock.o pinmux.o reset.o +obj-y += lowlevel.o diff --git a/arch/arm/cpu/armv7/stv0991/clock.c b/arch/arm/cpu/armv7/stv0991/clock.c new file mode 100644 index 0000000..70b8a8d --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/clock.c @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/stv0991_cgu.h> +#include<asm/arch/stv0991_periph.h> + +static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ + (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); + +void enable_pll1(void) +{ + /* pll1 already configured for 1000Mhz, just need to enable it */ + writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01), + &stv0991_cgu_regs->pll1_ctrl); +} + +void clock_setup(int peripheral) +{ + switch (peripheral) { + case UART_CLOCK_CFG: + writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq); + break; + case ETH_CLOCK_CFG: + enable_pll1(); + writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq); + + /* Clock selection for ethernet tx_clk & rx_clk*/ + writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK) + | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl); + + break; + default: + break; + } +} diff --git a/arch/arm/cpu/armv7/stv0991/lowlevel.S b/arch/arm/cpu/armv7/stv0991/lowlevel.S new file mode 100644 index 0000000..6dafba3 --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/lowlevel.S @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2014 stmicroelectronics + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + mov pc, lr +ENDPROC(lowlevel_init) diff --git a/arch/arm/cpu/armv7/stv0991/pinmux.c b/arch/arm/cpu/armv7/stv0991/pinmux.c new file mode 100644 index 0000000..1d086a2 --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/pinmux.c @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <asm/arch/stv0991_creg.h> +#include <asm/arch/stv0991_periph.h> +#include <asm/arch/hardware.h> + +static struct stv0991_creg *const stv0991_creg = \ + (struct stv0991_creg *)CREG_BASE_ADDR; + +int stv0991_pinmux_config(int peripheral) +{ + switch (peripheral) { + case UART_GPIOC_30_31: + /* SSDA/SSCL pad muxing to UART Rx/Dx */ + writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) | + CFG_GPIOC_31_UART_RX, + &stv0991_creg->mux12); + writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) | + CFG_GPIOC_30_UART_TX, + &stv0991_creg->mux12); + /* SSDA/SSCL pad config to push pull*/ + writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) | + CFG_GPIOC_31_MODE_PP, + &stv0991_creg->cfg_pad6); + writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) | + CFG_GPIOC_30_MODE_HIGH, + &stv0991_creg->cfg_pad6); + break; + case UART_GPIOB_16_17: + /* ethernet rx_6/7 to UART Rx/Dx */ + writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) | + CFG_GPIOB_17_UART_RX, + &stv0991_creg->mux7); + writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) | + CFG_GPIOB_16_UART_TX, + &stv0991_creg->mux7); + break; + case ETH_GPIOB_10_31_C_0_4: + writel(readl(&stv0991_creg->mux6) & 0x000000FF, + &stv0991_creg->mux6); + writel(0x00000000, &stv0991_creg->mux7); + writel(0x00000000, &stv0991_creg->mux8); + writel(readl(&stv0991_creg->mux9) & 0xFFF00000, + &stv0991_creg->mux9); + /* Ethernet Voltage configuration to 1.8V*/ + writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | + ETH_VDD_CFG, &stv0991_creg->vdd_pad1); + writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | + ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1); + + break; + default: + break; + } + return 0; +} diff --git a/arch/arm/cpu/armv7/stv0991/reset.c b/arch/arm/cpu/armv7/stv0991/reset.c new file mode 100644 index 0000000..3384b32 --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/reset.c @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/stv0991_wdru.h> +void reset_cpu(ulong ignored) +{ + puts("System is going to reboot ...\n"); + /* + * This 1 second delay will allow the above message + * to be printed before reset + */ + udelay((1000 * 1000)); + + /* Setting bit 1 of the WDRU unit will reset the SoC */ + writel(WDRU_RST_SYS, &stv0991_wd_ru_ptr->wdru_ctrl1); + + /* system will restart */ + while (1) + ; +} diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c new file mode 100644 index 0000000..8654b8b --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/timer.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch-stv0991/hardware.h> +#include <asm/arch-stv0991/stv0991_cgu.h> +#include <asm/arch-stv0991/stv0991_gpt.h> + +static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ + (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); + +#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) +#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ) + +DECLARE_GLOBAL_DATA_PTR; + +#define timestamp gd->arch.tbl +#define lastdec gd->arch.lastinc + +int timer_init(void) +{ + /* Timer1 clock configuration */ + writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq); + writel(readl(&stv0991_cgu_regs->cgu_enable_2) | + TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2); + + /* Stop the timer */ + writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1); + writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc); + /* Configure timer for auto-reload */ + writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD, + &gpt1_regs_ptr->cr1); + + /* load value for free running */ + writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr); + + /* start timer */ + writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN, + &gpt1_regs_ptr->cr1); + + /* Reset the timer */ + lastdec = READ_TIMER(); + timestamp = 0; + + return 0; +} + +/* + * timer without interrupts + */ +ulong get_timer(ulong base) +{ + return (get_timer_masked() / GPT_RESOLUTION) - base; +} + +void __udelay(unsigned long usec) +{ + ulong tmo; + ulong start = get_timer_masked(); + ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100); + ulong rndoff; + + rndoff = (usec % 10) ? 1 : 0; + + /* tenudelcnt timer tick gives 10 microsecconds delay */ + tmo = ((usec / 10) + rndoff) * tenudelcnt; + + while ((ulong) (get_timer_masked() - start) < tmo) + ; +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER(); + + if (now >= lastdec) { + /* normal mode */ + timestamp += now - lastdec; + } else { + /* we have an overflow ... */ + timestamp += now + GPT_FREE_RUNNING - lastdec; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked(unsigned long usec) +{ + return udelay(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_STV0991_HZ; +} diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index a0e49d1..49f4032 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -180,6 +180,21 @@ void clock_set_pll1(unsigned int hz) } #endif +void clock_set_pll3(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (clk == 0) { + clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); + return; + } + + /* PLL3 rate = 3000000 * m */ + writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | + CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg); +} + unsigned int clock_get_pll5p(void) { struct sunxi_ccm_reg *const ccm = @@ -200,3 +215,15 @@ unsigned int clock_get_pll6(void) int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; return 24000000 * n * k / 2; } + +void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) +{ + int pll = clock_get_pll5p(); + int div = 1; + + while ((pll / div) > hz) + div++; + + writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_RST | CCM_DE_CTRL_PLL5P | + CCM_DE_CTRL_M(div), clk_cfg); +} diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 16ab6f3..8e949c6 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -127,6 +127,23 @@ void clock_set_pll1(unsigned int clk) } #endif +void clock_set_pll3(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */ + + if (clk == 0) { + clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); + return; + } + + /* PLL3 rate = 24000000 * n / m */ + writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | + CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m), + &ccm->pll3_cfg); +} + void clock_set_pll5(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -151,3 +168,15 @@ unsigned int clock_get_pll6(void) int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; return 24000000 * n * k / 2; } + +void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) +{ + int pll = clock_get_pll6() * 2; + int div = 1; + + while ((pll / div) > hz) + div++; + + writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div), + clk_cfg); +} diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c index dc9fdb9..ec8aaa7 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c @@ -428,9 +428,9 @@ static void dramc_clock_output_en(u32 on) #ifdef CONFIG_MACH_SUN4I struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; if (on) - setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT); + setbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT); else - clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT); + clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT); #endif } diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c index 10a6241..699173c 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c @@ -142,9 +142,6 @@ static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para) writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST, &mctl_phy->ptr0); - /* Unknown magic performed by boot0 */ - if ((readl(SUNXI_RTC_BASE + 0x20c) & 3) == 2) - setbits_le32(&mctl_phy->ptr0, 1 << 18); writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1); writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2); diff --git a/arch/arm/cpu/armv7/tegra114/Makefile b/arch/arm/cpu/armv7/tegra114/Makefile deleted file mode 100644 index 77e2319..0000000 --- a/arch/arm/cpu/armv7/tegra114/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see <http://www.gnu.org/licenses/>. -# - -# necessary to create built-in.o -obj- := __dummy__.o diff --git a/arch/arm/cpu/armv7/tegra124/Makefile b/arch/arm/cpu/armv7/tegra124/Makefile deleted file mode 100644 index 9478d44..0000000 --- a/arch/arm/cpu/armv7/tegra124/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2013-2014 -# NVIDIA Corporation <www.nvidia.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# necessary to create built-in.o -obj- := __dummy__.o diff --git a/arch/arm/cpu/armv7/tegra20/display.c b/arch/arm/cpu/armv7/tegra20/display.c index d98cec9..61efed6 100644 --- a/arch/arm/cpu/armv7/tegra20/display.c +++ b/arch/arm/cpu/armv7/tegra20/display.c @@ -45,8 +45,8 @@ static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win) writel(0, &dc->win.h_initial_dda); writel(0, &dc->win.v_initial_dda); - h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1); - v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1); + h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U); + v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U); val = h_dda << H_DDA_INC_SHIFT; val |= v_dda << V_DDA_INC_SHIFT; diff --git a/arch/arm/cpu/armv7/tegra30/Makefile b/arch/arm/cpu/armv7/tegra30/Makefile deleted file mode 100644 index 413eba1..0000000 --- a/arch/arm/cpu/armv7/tegra30/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see <http://www.gnu.org/licenses/>. -# - -# necessary to create built-in.o -obj- := __dummy__.o diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 36b7f11..9760299 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -5,15 +5,17 @@ config SYS_SOC default "uniphier" config SYS_CONFIG_NAME - default "ph1_pro4" if MACH_PH1_PRO4 - default "ph1_ld4" if MACH_PH1_LD4 - default "ph1_sld8" if MACH_PH1_SLD8 + default "uniphier" + +config UNIPHIER_SMP + bool choice prompt "UniPhier SoC select" config MACH_PH1_PRO4 bool "PH1-Pro4" + select UNIPHIER_SMP config MACH_PH1_LD4 bool "PH1-LD4" @@ -23,6 +25,29 @@ config MACH_PH1_SLD8 endchoice +choice + prompt "UniPhier Support Card select" + optional + +config PFC_MICRO_SUPPORT_CARD + bool "Support card with PFC CPLD" + help + This option provides support for the expansion board with PFC + original address mapping. + + Say Y to use the on-board UART, Ether, LED devices. + +config DCC_MICRO_SUPPORT_CARD + bool "Support card with DCC CPLD" + help + This option provides support for the expansion board with DCC- + arranged address mapping that is compatible with legacy UniPhier + reference boards. + + Say Y to use the on-board UART, Ether, LED devices. + +endchoice + config CMD_PINMON bool "Enable boot mode pins monitor command" depends on !SPL_BUILD diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile index 0f64d25..4a7b8a9 100644 --- a/arch/arm/cpu/armv7/uniphier/Makefile +++ b/arch/arm/cpu/armv7/uniphier/Makefile @@ -11,6 +11,7 @@ obj-y += cache_uniphier.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o obj-y += dram_init.o obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o +obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o obj-$(CONFIG_UNIPHIER_SMP) += smp.o obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o diff --git a/arch/arm/cpu/armv7/uniphier/board_early_init_r.c b/arch/arm/cpu/armv7/uniphier/board_early_init_r.c new file mode 100644 index 0000000..cb7e04f --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/board_early_init_r.c @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/board.h> + +int board_early_init_r(void) +{ + uniphier_board_late_init(); + return 0; +} diff --git a/arch/arm/cpu/armv7/uniphier/board_late_init.c b/arch/arm/cpu/armv7/uniphier/board_late_init.c index 3730020..0622a1e 100644 --- a/arch/arm/cpu/armv7/uniphier/board_late_init.c +++ b/arch/arm/cpu/armv7/uniphier/board_late_init.c @@ -26,42 +26,6 @@ static void nand_denali_wp_disable(void) #endif } -static void nand_denali_fixup(void) -{ -#if defined(CONFIG_NAND_DENALI) && \ - (defined(CONFIG_MACH_PH1_SLD8) || defined(CONFIG_MACH_PH1_PRO4)) - /* - * The Denali NAND controller on some of UniPhier SoCs does not - * automatically query the device parameters. For those SoCs, - * some registers must be set after the device is probed. - */ - void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; - struct mtd_info *mtd; - struct nand_chip *chip; - - if (nand_curr_device < 0 || - nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE) { - /* NAND was not detected. Just return. */ - return; - } - - mtd = &nand_info[nand_curr_device]; - chip = mtd->priv; - - writel(mtd->erasesize / mtd->writesize, denali_reg + PAGES_PER_BLOCK); - writel(0, denali_reg + DEVICE_WIDTH); - writel(mtd->writesize, denali_reg + DEVICE_MAIN_AREA_SIZE); - writel(mtd->oobsize, denali_reg + DEVICE_SPARE_AREA_SIZE); - writel(1, denali_reg + DEVICES_CONNECTED); - - /* - * chip->scan_bbt in nand_scan_tail() has been skipped. - * It should be done in here. - */ - chip->scan_bbt(mtd); -#endif -} - int board_late_init(void) { puts("MODE: "); @@ -70,7 +34,6 @@ int board_late_init(void) case BOOT_DEVICE_MMC1: printf("eMMC Boot\n"); setenv("bootmode", "emmcboot"); - nand_denali_fixup(); break; case BOOT_DEVICE_NAND: printf("NAND Boot\n"); @@ -80,7 +43,6 @@ int board_late_init(void) case BOOT_DEVICE_NOR: printf("NOR Boot\n"); setenv("bootmode", "norboot"); - nand_denali_fixup(); break; default: printf("Unsupported Boot Mode\n"); diff --git a/arch/arm/cpu/armv7/uniphier/init_page_table.c b/arch/arm/cpu/armv7/uniphier/init_page_table.c index d273835..a0d10a9 100644 --- a/arch/arm/cpu/armv7/uniphier/init_page_table.c +++ b/arch/arm/cpu/armv7/uniphier/init_page_table.c @@ -28,7 +28,12 @@ #define IS_SSC(x) ((IS_SPL_TEXT_AREA(x)) || \ (IS_INIT_STACK_AREA(x))) #define IS_EXT(x) ((x) < 0x100) -#define IS_REG(x) (0x500 <= (x) && (x) < 0x700) + +/* 0x20000000-0x2fffffff, 0xf0000000-0xffffffff are only used by PH1-sLD3 */ +#define IS_REG(x) (0x200 <= (x) && (x) < 0x300) || \ + (0x500 <= (x) && (x) < 0x700) || \ + (0xf00 <= (x)) + #define IS_DDR(x) (0x800 <= (x) && (x) < 0xf00) #define MMU_FLAGS(x) (IS_SSC(x)) ? SSC : \ diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile index fba1cc7..5d682d3 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile @@ -3,7 +3,7 @@ # obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o -obj-y += platdevice.o +obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o obj-y += boot-mode.o obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \ clkrst_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c index 62f5b01..9d51299 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c @@ -14,7 +14,6 @@ SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) -/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { { .base = 0x5a800100, diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile index 74129bc..fd1c432 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile @@ -3,7 +3,7 @@ # obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o -obj-y += platdevice.o +obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o obj-y += boot-mode.o obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c index 1843d04..31ee2a2 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c @@ -14,7 +14,6 @@ SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) -/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { { .base = 0x5a800100, diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c index f113db5..3c82a1a 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c @@ -22,16 +22,7 @@ void sbc_init(void) writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); - if (readl(SBBASE0) & 0x1) { - /* - * Boot Swap Off: boot from mask ROM - * 0x00000000-0x01ffffff: mask ROM - * 0x02000000-0x3effffff: memory bank (31MB) - * 0x03f00000-0x3fffffff: peripherals (1MB) - */ - writel(0x0000be01, SBBASE0); /* dummy */ - writel(0x0200be01, SBBASE1); - } else { + if (boot_is_swapped()) { /* * Boot Swap On: boot from external NOR/SRAM * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. @@ -40,6 +31,15 @@ void sbc_init(void) * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals */ writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x00000000-0x01ffffff: mask ROM + * 0x02000000-0x3effffff: memory bank (31MB) + * 0x03f00000-0x3fffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); } #elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD) #if !defined(CONFIG_SPL_BUILD) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile index fba1cc7..5d682d3 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile @@ -3,7 +3,7 @@ # obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o -obj-y += platdevice.o +obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o obj-y += boot-mode.o obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \ clkrst_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c index 72ec599..ea0691d 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c @@ -14,7 +14,6 @@ SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) -/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { { .base = 0x5a800100, diff --git a/arch/arm/cpu/armv7/uniphier/support_card.c b/arch/arm/cpu/armv7/uniphier/support_card.c index 40d4940..419012e 100644 --- a/arch/arm/cpu/armv7/uniphier/support_card.c +++ b/arch/arm/cpu/armv7/uniphier/support_card.c @@ -83,6 +83,12 @@ static int support_card_show_revision(void) } #endif +int check_support_card(void) +{ + printf("SC: Micro Support Card "); + return support_card_show_revision(); +} + void support_card_init(void) { /* @@ -94,12 +100,6 @@ void support_card_init(void) support_card_reset_deassert(); } -int check_support_card(void) -{ - printf("SC: Micro Support Card "); - return support_card_show_revision(); -} - #if defined(CONFIG_SMC911X) #include <netdev.h> @@ -112,18 +112,14 @@ int board_eth_init(bd_t *bis) #if !defined(CONFIG_SYS_NO_FLASH) #include <mtd/cfi_flash.h> +#include <asm/arch/sbc-regs.h> -#if CONFIG_SYS_MAX_FLASH_BANKS > 1 -static phys_addr_t flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS] = - CONFIG_SYS_FLASH_BANKS_LIST; +struct memory_bank { + phys_addr_t base; + unsigned long size; +}; -phys_addr_t cfi_flash_bank_addr(int i) -{ - return flash_banks_list[i]; -} -#endif - -int mem_is_flash(phys_addr_t base) +static int mem_is_flash(const struct memory_bank *mem) { const int loop = 128; u32 *scratch_addr; @@ -131,8 +127,9 @@ int mem_is_flash(phys_addr_t base) int ret = 1; int i; - scratch_addr = map_physmem(base + 0x01e00000, - sizeof(u32) * loop, MAP_NOCACHE); + /* just in case, use the tail of the memory bank */ + scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop, + sizeof(u32) * loop, MAP_NOCACHE); for (i = 0; i < loop; i++, scratch_addr++) { saved_value = readl(scratch_addr); @@ -150,31 +147,79 @@ int mem_is_flash(phys_addr_t base) return ret; } -int board_flash_wp_on(void) +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) + /* {address, size} */ +static const struct memory_bank memory_banks_boot_swap_off[] = { + {0x02000000, 0x01f00000}, +}; + +static const struct memory_bank memory_banks_boot_swap_on[] = { + {0x00000000, 0x01f00000}, +}; +#endif + +#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) +static const struct memory_bank memory_banks_boot_swap_off[] = { + {0x04000000, 0x04000000}, +}; + +static const struct memory_bank memory_banks_boot_swap_on[] = { + {0x00000000, 0x04000000}, + {0x04000000, 0x04000000}, +}; +#endif + +static const struct memory_bank +*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT]; + +phys_addr_t cfi_flash_bank_addr(int i) { - int i; - int ret = 1; + return flash_banks_list[i]->base; +} - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - if (mem_is_flash(cfi_flash_bank_addr(i))) { - /* - * We found at least one flash. - * We need to return 0 and call flash_init(). - */ - ret = 0; - } -#if CONFIG_SYS_MAX_FLASH_BANKS > 1 - else { - /* - * We might have a SRAM here. - * To prevent SRAM data from being destroyed, - * we set dummy address (SDRAM). - */ - flash_banks_list[i] = 0x80000000 + 0x10000 * i; +unsigned long cfi_flash_bank_size(int i) +{ + return flash_banks_list[i]->size; +} + +static void detect_num_flash_banks(void) +{ + const struct memory_bank *memory_bank, *end; + + cfi_flash_num_flash_banks = 0; + + if (boot_is_swapped()) { + memory_bank = memory_banks_boot_swap_on; + end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on); + } else { + memory_bank = memory_banks_boot_swap_off; + end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off); + } + + for (; memory_bank < end; memory_bank++) { + if (cfi_flash_num_flash_banks >= + CONFIG_SYS_MAX_FLASH_BANKS_DETECT) + break; + + if (mem_is_flash(memory_bank)) { + flash_banks_list[cfi_flash_num_flash_banks] = + memory_bank; + + debug("flash bank found: base = 0x%lx, size = 0x%lx\n", + memory_bank->base, memory_bank->size); + cfi_flash_num_flash_banks++; } -#endif } - return ret; + debug("number of flash banks: %d\n", cfi_flash_num_flash_banks); +} +#else /* ONFIG_SYS_NO_FLASH */ +void detect_num_flash_banks(void) +{ +}; +#endif /* ONFIG_SYS_NO_FLASH */ + +void support_card_late_init(void) +{ + detect_num_flash_banks(); } -#endif diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index a26d63e..92aaad9 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -265,20 +265,21 @@ static char *get_reset_cause(void) cause = readl(&src_regs->srsr); writel(cause, &src_regs->srsr); - cause &= 0xff; - switch (cause) { - case 0x08: - return "WDOG"; - case 0x20: + if (cause & SRC_SRSR_POR_RST) + return "POWER ON RESET"; + else if (cause & SRC_SRSR_WDOG_A5) + return "WDOG A5"; + else if (cause & SRC_SRSR_WDOG_M4) + return "WDOG M4"; + else if (cause & SRC_SRSR_JTAG_RST) return "JTAG HIGH-Z"; - case 0x80: + else if (cause & SRC_SRSR_SW_RST) + return "SW RESET"; + else if (cause & SRC_SRSR_RESETB) return "EXTERNAL RESET"; - case 0xfd: - return "POR"; - default: + else return "unknown reset"; - } } int print_cpuinfo(void) diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 7d93f59..0c10223 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -14,3 +14,5 @@ obj-y += exceptions.o obj-y += cache.o obj-y += tlb.o obj-y += transition.o + +obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/ diff --git a/arch/arm/cpu/at91-common/Makefile b/arch/arm/cpu/at91-common/Makefile index 5b97838..89e1577 100644 --- a/arch/arm/cpu/at91-common/Makefile +++ b/arch/arm/cpu/at91-common/Makefile @@ -9,4 +9,9 @@ # obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o -obj-$(CONFIG_SPL_BUILD) += mpddrc.o spl.o +ifneq ($(CONFIG_SPL_BUILD),) +obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o +obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o +obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o +obj-y += spl.o +endif diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c index 8136396..44798e6 100644 --- a/arch/arm/cpu/at91-common/mpddrc.c +++ b/arch/arm/cpu/at91-common/mpddrc.c @@ -17,6 +17,15 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address) writel(0, ram_address); } +static int ddr2_decodtype_is_seq(u32 cr) +{ +#if defined(CONFIG_SAMA5D3) + if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED) + return 0; +#endif + return 1; +} + int ddr2_init(const unsigned int ram_address, const struct atmel_mpddr *mpddr_value) { @@ -25,8 +34,8 @@ int ddr2_init(const unsigned int ram_address, /* Compute bank offset according to NC in configuration register */ ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; - if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)) - ba_off += ((mpddr->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; + if (ddr2_decodtype_is_seq(mpddr_value->cr)) + ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2; diff --git a/arch/arm/cpu/at91-common/sdram.c b/arch/arm/cpu/at91-common/sdram.c new file mode 100644 index 0000000..5758b06 --- /dev/null +++ b/arch/arm/cpu/at91-common/sdram.c @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2014 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91sam9_sdramc.h> +#include <asm/arch/gpio.h> + +int sdramc_initialize(unsigned int sdram_address, const struct sdramc_reg *p) +{ + struct sdramc_reg *reg = (struct sdramc_reg *)ATMEL_BASE_SDRAMC; + unsigned int i; + + /* SDRAM feature must be in the configuration register */ + writel(p->cr, ®->cr); + + /* The SDRAM memory type must be set in the Memory Device Register */ + writel(p->mdr, ®->mdr); + + /* + * The minimum pause of 200 us is provided to precede any single + * toggle + */ + for (i = 0; i < 1000; i++) + ; + + /* A NOP command is issued to the SDRAM devices */ + writel(AT91_SDRAMC_MODE_NOP, ®->mr); + writel(0x00000000, sdram_address); + + /* An All Banks Precharge command is issued to the SDRAM devices */ + writel(AT91_SDRAMC_MODE_PRECHARGE, ®->mr); + writel(0x00000000, sdram_address); + + for (i = 0; i < 10000; i++) + ; + + /* Eight auto-refresh cycles are provided */ + for (i = 0; i < 8; i++) { + writel(AT91_SDRAMC_MODE_REFRESH, ®->mr); + writel(0x00000001 + i, sdram_address + 4 + 4 * i); + } + + /* + * A Mode Register set (MRS) cyscle is issued to program the + * SDRAM parameters(TCSR, PASR, DS) + */ + writel(AT91_SDRAMC_MODE_LMR, ®->mr); + writel(0xcafedede, sdram_address + 0x24); + + /* + * The application must go into Normal Mode, setting Mode + * to 0 in the Mode Register and perform a write access at + * any location in the SDRAM. + */ + writel(AT91_SDRAMC_MODE_NORMAL, ®->mr); + writel(0x00000000, sdram_address); /* Perform Normal mode */ + + /* + * Write the refresh rate into the count field in the SDRAMC + * Refresh Timer Rgister. + */ + writel(p->tr, ®->tr); + + return 0; +} diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c index 674a470..6473320 100644 --- a/arch/arm/cpu/at91-common/spl.c +++ b/arch/arm/cpu/at91-common/spl.c @@ -8,83 +8,17 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> #include <asm/arch/at91_wdt.h> #include <asm/arch/clk.h> #include <spl.h> -static void at91_disable_wdt(void) +void at91_disable_wdt(void) { struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT; writel(AT91_WDT_MR_WDDIS, &wdt->mr); } -static void switch_to_main_crystal_osc(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - u32 tmp; - - tmp = readl(&pmc->mor); - tmp &= ~AT91_PMC_MOR_OSCOUNT(0xff); - tmp &= ~AT91_PMC_MOR_KEY(0xff); - tmp |= AT91_PMC_MOR_MOSCEN; - tmp |= AT91_PMC_MOR_OSCOUNT(8); - tmp |= AT91_PMC_MOR_KEY(0x37); - writel(tmp, &pmc->mor); - while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS)) - ; - - tmp = readl(&pmc->mor); - tmp &= ~AT91_PMC_MOR_OSCBYPASS; - tmp &= ~AT91_PMC_MOR_KEY(0xff); - tmp |= AT91_PMC_MOR_KEY(0x37); - writel(tmp, &pmc->mor); - - tmp = readl(&pmc->mor); - tmp |= AT91_PMC_MOR_MOSCSEL; - tmp &= ~AT91_PMC_MOR_KEY(0xff); - tmp |= AT91_PMC_MOR_KEY(0x37); - writel(tmp, &pmc->mor); - - while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCSELS)) - ; - - tmp = readl(&pmc->mor); - tmp &= ~AT91_PMC_MOR_MOSCRCEN; - tmp &= ~AT91_PMC_MOR_KEY(0xff); - tmp |= AT91_PMC_MOR_KEY(0x37); - writel(tmp, &pmc->mor); -} - -void at91_plla_init(u32 pllar) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - writel(pllar, &pmc->pllar); - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) - ; -} - -void at91_mck_init(u32 mckr) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - u32 tmp; - - tmp = readl(&pmc->mckr); - tmp &= ~(AT91_PMC_MCKR_PRES_MASK | - AT91_PMC_MCKR_MDIV_MASK | - AT91_PMC_MCKR_PLLADIV_2); - tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK | - AT91_PMC_MCKR_MDIV_MASK | - AT91_PMC_MCKR_PLLADIV_2); - writel(tmp, &pmc->mckr); - - while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) - ; -} - - u32 spl_boot_device(void) { #ifdef CONFIG_SYS_USE_MMC @@ -110,24 +44,3 @@ u32 spl_boot_mode(void) hang(); } } - -void s_init(void) -{ - switch_to_main_crystal_osc(); - - /* disable watchdog */ - at91_disable_wdt(); - - /* PMC configuration */ - at91_pmc_init(); - - at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); - - timer_init(); - - board_early_init_f(); - - preloader_console_init(); - - mem_init(); -} diff --git a/arch/arm/cpu/at91-common/spl_at91.c b/arch/arm/cpu/at91-common/spl_at91.c new file mode 100644 index 0000000..89f588b --- /dev/null +++ b/arch/arm/cpu/at91-common/spl_at91.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2014 DENX Software Engineering + * Heiko Schocher <hs@denx.de> + * + * Based on: + * Copyright (C) 2013 Atmel Corporation + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91sam9_matrix.h> +#include <asm/arch/at91_pit.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_wdt.h> +#include <asm/arch/clk.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void enable_ext_reset(void) +{ + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + + writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr); +} + +void lowlevel_clock_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) { + /* Enable Main Oscillator */ + writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor); + + /* Wait until Main Oscillator is stable */ + while (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) + ; + } + + /* After stabilization, switch to Main Oscillator */ + if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { + unsigned long tmp; + + tmp = readl(&pmc->mckr); + tmp &= ~AT91_PMC_CSS; + tmp |= AT91_PMC_CSS_MAIN; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + + tmp &= ~AT91_PMC_PRES; + tmp |= AT91_PMC_PRES_1; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + } + + return; +} + +void __weak matrix_init(void) +{ +} + +void __weak at91_spl_board_init(void) +{ +} + +void spl_board_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + lowlevel_clock_init(); + at91_disable_wdt(); + + /* + * At this stage the main oscillator is supposed to be enabled + * PCK = MCK = MOSC + */ + writel(0x00, &pmc->pllicpr); + + /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ + at91_plla_init(CONFIG_SYS_AT91_PLLA); + + /* PCK = PLLA = 2 * MCK */ + at91_mck_init(CONFIG_SYS_MCKR); + + /* Switch MCK on PLLA output */ + at91_mck_init(CONFIG_SYS_MCKR_CSS); + +#if defined(CONFIG_SYS_AT91_PLLB) + /* Configure PLLB */ + at91_pllb_init(CONFIG_SYS_AT91_PLLB); +#endif + + /* Enable External Reset */ + enable_ext_reset(); + + /* Initialize matrix */ + matrix_init(); + + gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; + /* + * init timer long enough for using in spl. + */ + timer_init(); + + /* enable clocks for all PIOs */ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + /* init console */ + at91_seriald_hw_init(); + preloader_console_init(); + + mem_init(); + + at91_spl_board_init(); +} diff --git a/arch/arm/cpu/at91-common/spl_atmel.c b/arch/arm/cpu/at91-common/spl_atmel.c new file mode 100644 index 0000000..7297530 --- /dev/null +++ b/arch/arm/cpu/at91-common/spl_atmel.c @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2013 Atmel Corporation + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pit.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_wdt.h> +#include <asm/arch/clk.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void switch_to_main_crystal_osc(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = readl(&pmc->mor); + tmp &= ~AT91_PMC_MOR_OSCOUNT(0xff); + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_MOSCEN; + tmp |= AT91_PMC_MOR_OSCOUNT(8); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); + while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS)) + ; + + tmp = readl(&pmc->mor); + tmp &= ~AT91_PMC_MOR_OSCBYPASS; + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); + + tmp = readl(&pmc->mor); + tmp |= AT91_PMC_MOR_MOSCSEL; + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); + + while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCSELS)) + ; + + /* Wait until MAINRDY field is set to make sure main clock is stable */ + while (!(readl(&pmc->mcfr) & AT91_PMC_MAINRDY)) + ; + + tmp = readl(&pmc->mor); + tmp &= ~AT91_PMC_MOR_MOSCRCEN; + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); +} + +void s_init(void) +{ + switch_to_main_crystal_osc(); + + /* disable watchdog */ + at91_disable_wdt(); + + /* PMC configuration */ + at91_pmc_init(); + + at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + + timer_init(); + + board_early_init_f(); + + preloader_console_init(); + + mem_init(); +} diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 4beddf0..a8be204 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -32,8 +32,18 @@ SECTIONS } . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*_i2c_*))); + } . = .; +#ifdef CONFIG_SPL_DM + .u_boot_list : { + KEEP(*(SORT(.u_boot_list_*_driver_*))); + KEEP(*(SORT(.u_boot_list_*_uclass_*))); + } +#endif + . = ALIGN(4); __image_copy_end = .; diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ba6dec9..187d58c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-snow.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ - exynos5420-peach-pit.dtb + exynos5420-peach-pit.dtb \ + exynos5800-peach-pi.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ @@ -31,6 +32,11 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra114-dalmore.dtb \ tegra124-jetson-tk1.dtb \ tegra124-venice2.dtb +dtb-$(CONFIG_ARCH_UNIPHIER) += \ + uniphier-ph1-sld3-ref.dtb \ + uniphier-ph1-pro4-ref.dtb \ + uniphier-ph1-ld4-ref.dtb \ + uniphier-ph1-sld8-ref.dtb dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ zynq-zc706.dtb \ zynq-zed.dtb \ diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts index 2a1f1dd..c78efec 100644 --- a/arch/arm/dts/exynos4412-odroid.dts +++ b/arch/arm/dts/exynos4412-odroid.dts @@ -67,4 +67,15 @@ div = <0x3>; index = <4>; }; + + ehci@12580000 { + compatible = "samsung,exynos-ehci"; + reg = <0x12580000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + phy { + compatible = "samsung,exynos-usb-phy"; + reg = <0x125B0000 0x100>; + }; + }; }; diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts index 6fd9275..95af025 100644 --- a/arch/arm/dts/exynos5250-snow.dts +++ b/arch/arm/dts/exynos5250-snow.dts @@ -131,11 +131,11 @@ }; ehci@12110000 { - samsung,vbus-gpio = <&gpio 0x309 0>; /* X11 */ + samsung,vbus-gpio = <&gpio 0xb1 0>; /* X11 */ }; xhci@12000000 { - samsung,vbus-gpio = <&gpio 0x317 0>; /* X27 */ + samsung,vbus-gpio = <&gpio 0xbf 0>; /* X27 */ }; tmu@10060000 { diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts new file mode 100644 index 0000000..8aedf8e --- /dev/null +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -0,0 +1,157 @@ +/* + * SAMSUNG/GOOGLE Peach-Pit board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "exynos54xx.dtsi" + +/ { + model = "Samsung/Google Peach Pi board based on Exynos5800"; + + compatible = "google,pit-rev#", "google,pit", + "google,peach", "samsung,exynos5800", "samsung,exynos5"; + + config { + google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */ + hwid = "PIT TEST A-A 7848"; + lazy-init = <1>; + }; + + aliases { + serial0 = "/serial@12C30000"; + console = "/serial@12C30000"; + pmic = "/i2c@12ca0000"; + }; + + dmc { + mem-manuf = "samsung"; + mem-type = "ddr3"; + clock-frequency = <800000000>; + arm-frequency = <1700000000>; + }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + /* MAX77802 is on i2c bus 4 */ + i2c@12ca0000 { + clock-frequency = <400000>; + power-regulator@9 { + compatible = "maxim,max77802-pmic"; + reg = <0x9>; + }; + }; + + i2c@12cd0000 { /* i2c7 */ + clock-frequency = <100000>; + soundcodec@20 { + reg = <0x20>; + compatible = "maxim,max98090-codec"; + }; + + edp-lvds-bridge@48 { + compatible = "parade,ps8625"; + reg = <0x48>; + }; + }; + + sound@3830000 { + samsung,codec-type = "max98090"; + }; + + i2c@12e10000 { /* i2c9 */ + clock-frequency = <400000>; + tpm@20 { + compatible = "infineon,slb9645-tpm"; + reg = <0x20>; + }; + }; + + spi@12d30000 { /* spi1 */ + spi-max-frequency = <50000000>; + firmware_storage_spi: flash@0 { + reg = <0>; + + /* + * A region for the kernel to store a panic event + * which the firmware will add to the log. + */ + elog-panic-event-offset = <0x01e00000 0x100000>; + + elog-shrink-size = <0x400>; + elog-full-threshold = <0xc00>; + }; + }; + + spi@12d40000 { /* spi2 */ + spi-max-frequency = <4000000>; + spi-deactivate-delay = <200>; + cros-ec@0 { + reg = <0>; + compatible = "google,cros-ec"; + spi-half-duplex; + spi-max-timeout-ms = <1100>; + spi-frame-header = <0xec>; + ec-interrupt = <&gpio 93 1>; /* GPX1_5 */ + + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; + }; + }; + }; + + xhci@12000000 { + samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */ + }; + + xhci@12400000 { + samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */ + }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <1920>; + samsung,vl-row = <1080>; + samsung,vl-width = <1920>; + samsung,vl-height = <1080>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <80>; + samsung,vl-hbpd = <172>; + samsung,vl-hfpd = <60>; + samsung,vl-vspw = <10>; + samsung,vl-vbpd = <25>; + samsung,vl-vfpd = <10>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; +}; diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts new file mode 100644 index 0000000..08bbd03 --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts @@ -0,0 +1,61 @@ +/* + * Device Tree Source for UniPhier PH1-LD4 Reference Board + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "uniphier-ph1-ld4.dtsi" + +/ { + model = "Panasonic UniPhier PH1-LD4 Reference Board"; + compatible = "panasonic,ph1-ld4-ref", "panasonic,ph1-ld4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyPS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + aliases { + uart0 = &uart0; + uart1 = &uart1; + uart2 = &uart2; + uart3 = &uart3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + eeprom { + compatible = "i2c-eeprom"; + reg = <0x50>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi new file mode 100644 index 0000000..2a3dd73 --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -0,0 +1,120 @@ +/* + * Device Tree Source for UniPhier PH1-LD4 SoC + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "panasonic,ph1-ld4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart0: serial@54006800 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x20>; + clock-frequency = <36864000>; + }; + + uart1: serial@54006900 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x20>; + clock-frequency = <36864000>; + }; + + uart2: serial@54006a00 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x20>; + clock-frequency = <36864000>; + }; + + uart3: serial@54006b00 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x20>; + clock-frequency = <36864000>; + }; + + i2c0: i2c@58400000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58400000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@58480000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58480000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@58500000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58500000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c3: i2c@58580000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58580000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + usb0: usb@5a800100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + }; + + usb1: usb@5a810100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + }; + + usb2: usb@5a820100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + }; + + nand: nand@68000000 { + compatible = "denali,denali-nand-dt"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + reg-names = "nand_data", "denali_reg"; + }; + }; +}; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts new file mode 100644 index 0000000..23add7c --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts @@ -0,0 +1,63 @@ +/* + * Device Tree Source for UniPhier PH1-Pro4 Reference Board + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "uniphier-ph1-pro4.dtsi" + +/ { + model = "Panasonic UniPhier PH1-Pro4 Reference Board"; + compatible = "panasonic,ph1-pro4-ref", "panasonic,ph1-pro4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyPS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + aliases { + uart0 = &uart0; + uart1 = &uart1; + uart2 = &uart2; + uart3 = &uart3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + eeprom { + compatible = "i2c-eeprom"; + reg = <0x50>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi new file mode 100644 index 0000000..49e375e --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -0,0 +1,140 @@ +/* + * Device Tree Source for UniPhier PH1-Pro4 SoC + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "panasonic,ph1-pro4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart0: serial@54006800 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x20>; + clock-frequency = <73728000>; + }; + + uart1: serial@54006900 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x20>; + clock-frequency = <73728000>; + }; + + uart2: serial@54006a00 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x20>; + clock-frequency = <73728000>; + }; + + uart3: serial@54006b00 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x20>; + clock-frequency = <73728000>; + }; + + i2c0: i2c@58780000 { + compatible = "panasonic,uniphier-fi2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58780000 0x80>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@58781000 { + compatible = "panasonic,uniphier-fi2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58781000 0x80>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@58782000 { + compatible = "panasonic,uniphier-fi2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58782000 0x80>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c3: i2c@58783000 { + compatible = "panasonic,uniphier-fi2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58783000 0x80>; + clock-frequency = <100000>; + status = "disabled"; + }; + + /* i2c4 does not exist */ + + i2c5: i2c@58785000 { + compatible = "panasonic,uniphier-fi2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58785000 0x80>; + clock-frequency = <400000>; + status = "ok"; + }; + + i2c6: i2c@58786000 { + compatible = "panasonic,uniphier-fi2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58786000 0x80>; + clock-frequency = <400000>; + status = "ok"; + }; + + usb0: usb@5a800100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + }; + + usb1: usb@5a810100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + }; + + nand: nand@68000000 { + compatible = "denali,denali-nand-dt"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + reg-names = "nand_data", "denali_reg"; + }; + }; +}; diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts new file mode 100644 index 0000000..91b4dbe --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts @@ -0,0 +1,60 @@ +/* + * Device Tree Source for UniPhier PH1-sLD3 Reference Board + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "uniphier-ph1-sld3.dtsi" + +/ { + model = "Panasonic UniPhier PH1-sLD3 Reference Board"; + compatible = "panasonic,ph1-sld3-ref", "panasonic,ph1-sld3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyPS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + aliases { + uart0 = &uart0; + uart1 = &uart1; + uart2 = &uart2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + eeprom { + compatible = "i2c-eeprom"; + reg = <0x50>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi new file mode 100644 index 0000000..f5529d2 --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -0,0 +1,125 @@ +/* + * Device Tree Source for UniPhier PH1-sLD3 SoC + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "panasonic,ph1-sld3"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart0: serial@54006800 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x20>; + clock-frequency = <36864000>; + }; + + uart1: serial@54006900 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x20>; + clock-frequency = <36864000>; + }; + + uart2: serial@54006a00 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x20>; + clock-frequency = <36864000>; + }; + + i2c0: i2c@58400000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58400000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@58480000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58480000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@58500000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58500000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c3: i2c@58580000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58580000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + usb0: usb@5a800100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + }; + + usb1: usb@5a810100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + }; + + usb2: usb@5a820100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + }; + + usb3: usb@5a830100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a830100 0x100>; + }; + + nand: nand@f8000000 { + compatible = "denali,denali-nand-dt"; + reg = <0xf8000000 0x20>, <0xf8100000 0x1000>; + reg-names = "nand_data", "denali_reg"; + }; + }; +}; diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts new file mode 100644 index 0000000..a8ce049 --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts @@ -0,0 +1,61 @@ +/* + * Device Tree Source for UniPhier PH1-sLD8 Reference Board + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "uniphier-ph1-sld8.dtsi" + +/ { + model = "Panasonic UniPhier PH1-sLD8 Reference Board"; + compatible = "panasonic,ph1-sld8-ref", "panasonic,ph1-sld8"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyPS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + aliases { + uart0 = &uart0; + uart1 = &uart1; + uart2 = &uart2; + uart3 = &uart3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + eeprom { + compatible = "i2c-eeprom"; + reg = <0x50>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi new file mode 100644 index 0000000..0ea76e5 --- /dev/null +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -0,0 +1,120 @@ +/* + * Device Tree Source for UniPhier PH1-sLD8 SoC + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "panasonic,ph1-sld8"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart0: serial@54006800 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x20>; + clock-frequency = <80000000>; + }; + + uart1: serial@54006900 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x20>; + clock-frequency = <80000000>; + }; + + uart2: serial@54006a00 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x20>; + clock-frequency = <80000000>; + }; + + uart3: serial@54006b00 { + compatible = "panasonic,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x20>; + clock-frequency = <80000000>; + }; + + i2c0: i2c@58400000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58400000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@58480000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58480000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@58500000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58500000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c3: i2c@58580000 { + compatible = "panasonic,uniphier-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58580000 0x40>; + clock-frequency = <100000>; + status = "disabled"; + }; + + usb0: usb@5a800100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + }; + + usb1: usb@5a810100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + }; + + usb2: usb@5a820100 { + compatible = "panasonic,uniphier-ehci", "usb-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + }; + + nand: nand@68000000 { + compatible = "denali,denali-nand-dt"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + reg-names = "nand_data", "denali_reg"; + }; + }; +}; diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 09fc227..28ccd29 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -17,6 +17,8 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/crm_regs.h> #include <ipu_pixfmt.h> +#include <thermal.h> +#include <sata.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> @@ -134,6 +136,11 @@ int print_cpuinfo(void) { u32 cpurev; +#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL) + struct udevice *thermal_dev; + int cpu_tmp, ret; +#endif + cpurev = get_cpu_rev(); printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", @@ -141,6 +148,21 @@ int print_cpuinfo(void) (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); + +#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL) + ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev); + if (!ret) { + ret = thermal_get_temp(thermal_dev, &cpu_tmp); + + if (!ret) + printf("CPU: Temperature %d C\n", cpu_tmp); + else + printf("CPU: Temperature: invalid sensor data\n"); + } else { + printf("CPU: Temperature: Can't find sensor device\n"); + } +#endif + printf("Reset cause: %s\n", get_reset_cause()); return 0; } @@ -180,10 +202,47 @@ u32 get_ahb_clk(void) return get_periph_clk() / (ahb_podf + 1); } -#if defined(CONFIG_VIDEO_IPUV3) void arch_preboot_os(void) { +#if defined(CONFIG_CMD_SATA) + sata_stop(); +#if defined(CONFIG_MX6) + disable_sata_clock(); +#endif +#endif +#if defined(CONFIG_VIDEO_IPUV3) /* disable video before launching O/S */ ipuv3_fb_shutdown(); -} #endif +} + +void set_chipselect_size(int const cs_size) +{ + unsigned int reg; + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + reg = readl(&iomuxc_regs->gpr[1]); + + switch (cs_size) { + case CS0_128: + reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */ + reg |= 0x5; + break; + case CS0_64M_CS1_64M: + reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */ + reg |= 0x1B; + break; + case CS0_64M_CS1_32M_CS2_32M: + reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */ + reg |= 0x4B; + break; + case CS0_32M_CS1_32M_CS2_32M_CS3_32M: + reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */ + reg |= 0x249; + break; + default: + printf("Unknown chip select size: %d\n", cs_size); + break; + } + + writel(reg, &iomuxc_regs->gpr[1]); +} diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c index 9d3c31a..477c38c 100644 --- a/arch/arm/imx-common/spl.c +++ b/arch/arm/imx-common/spl.c @@ -14,11 +14,12 @@ #include <spl.h> #if defined(CONFIG_MX6) -/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */ +/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */ u32 spl_boot_device(void) { struct src *psrc = (struct src *)SRC_BASE_ADDR; - unsigned reg = readl(&psrc->sbmr1); + unsigned int gpr10_boot = readl(&psrc->gpr10) & (1 << 28); + unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1); /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */ switch ((reg & 0x000000FF) >> 4) { diff --git a/board/compulab/cm_fx6/imximage.cfg b/arch/arm/imx-common/spl_sd.cfg index 420947e..5fc3e8a 100644 --- a/board/compulab/cm_fx6/imximage.cfg +++ b/arch/arm/imx-common/spl_sd.cfg @@ -4,5 +4,5 @@ * SPDX-License-Identifier: GPL-2.0+ */ -IMAGE_VERSION 2 +IMAGE_VERSION 2 BOOT_FROM sd diff --git a/arch/arm/imx-common/video.c b/arch/arm/imx-common/video.c index 8651b80..46f8a1e 100644 --- a/arch/arm/imx-common/video.c +++ b/arch/arm/imx-common/video.c @@ -11,6 +11,7 @@ int board_video_skip(void) int i; int ret; char const *panel = getenv("panel"); + if (!panel) { for (i = 0; i < display_count; i++) { struct display_info_t const *dev = displays+i; @@ -31,11 +32,14 @@ int board_video_skip(void) break; } } + if (i < display_count) { ret = ipuv3_fb_init(&displays[i].mode, 0, displays[i].pixfmt); if (!ret) { - displays[i].enable(displays+i); + if (displays[i].enable) + displays[i].enable(displays + i); + printf("Display: %s (%ux%u)\n", displays[i].mode.name, displays[i].mode.xres, diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 8543f43..e756418 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -25,6 +25,7 @@ #else #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 +#define BOOT_DEVICE_NAND_I2C 6 #if defined(CONFIG_AM33XX) #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h index 532411e..e062da1 100644 --- a/arch/arm/include/asm/arch-armada100/config.h +++ b/arch/arm/include/asm/arch-armada100/config.h @@ -16,7 +16,6 @@ #define _ARMD1_CONFIG_H #include <asm/arch/armada100.h> -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ /* default Dcache Line length for armada100 */ #define CONFIG_SYS_CACHELINE_SIZE 32 diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h index 59e2f43..912e55c 100644 --- a/arch/arm/include/asm/arch-at91/at91_common.h +++ b/arch/arm/include/asm/arch-at91/at91_common.h @@ -23,9 +23,15 @@ void at91_udp_hw_init(void); void at91_uhp_hw_init(void); void at91_lcd_hw_init(void); void at91_plla_init(u32 pllar); +void at91_pllb_init(u32 pllar); void at91_mck_init(u32 mckr); void at91_pmc_init(void); void mem_init(void); void at91_phy_reset(void); +void at91_sdram_hw_init(void); +void at91_mck_init(u32 mckr); +void at91_spl_board_init(void); +void at91_disable_wdt(void); +void matrix_init(void); #endif /* AT91_COMMON_H */ diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h index 27331ff..53b5b2e 100644 --- a/arch/arm/include/asm/arch-at91/at91_pmc.h +++ b/arch/arm/include/asm/arch-at91/at91_pmc.h @@ -78,7 +78,7 @@ typedef struct at91_pmc { #define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) #define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) #define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14) -#ifdef CONFIG_SAMA5D3 +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) #define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18) #else #define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16) @@ -97,7 +97,7 @@ typedef struct at91_pmc { #define AT91_PMC_MCKR_CSS_PLLB 0x00000003 #define AT91_PMC_MCKR_CSS_MASK 0x00000003 -#ifdef CONFIG_SAMA5D3 +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) #define AT91_PMC_MCKR_PRES_1 0x00000000 #define AT91_PMC_MCKR_PRES_2 0x00000010 #define AT91_PMC_MCKR_PRES_4 0x00000020 @@ -126,16 +126,19 @@ typedef struct at91_pmc { #else #define AT91_PMC_MCKR_MDIV_1 0x00000000 #define AT91_PMC_MCKR_MDIV_2 0x00000100 -#ifdef CONFIG_SAMA5D3 +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) #define AT91_PMC_MCKR_MDIV_3 0x00000300 #endif #define AT91_PMC_MCKR_MDIV_4 0x00000200 #define AT91_PMC_MCKR_MDIV_MASK 0x00000300 #endif +#define AT91_PMC_MCKR_PLLADIV_MASK 0x00003000 #define AT91_PMC_MCKR_PLLADIV_1 0x00000000 #define AT91_PMC_MCKR_PLLADIV_2 0x00001000 +#define AT91_PMC_MCKR_H32MXDIV 0x01000000 + #define AT91_PMC_IXR_MOSCS 0x00000001 #define AT91_PMC_IXR_LOCKA 0x00000002 #define AT91_PMC_IXR_LOCKB 0x00000004 diff --git a/arch/arm/include/asm/arch-at91/at91rm9200.h b/arch/arm/include/asm/arch-at91/at91rm9200.h index 25bb071..d177bdc 100644 --- a/arch/arm/include/asm/arch-at91/at91rm9200.h +++ b/arch/arm/include/asm/arch-at91/at91rm9200.h @@ -7,7 +7,6 @@ #define __AT91RM9200_H__ #define CONFIG_AT91FAMILY /* it's a member of AT91 family */ -#define CONFIG_ARM920T /* it's an ARM920T Core */ #define CONFIG_ARCH_CPU_INIT /* we need arch_cpu_init() for hw timers */ #define CONFIG_AT91_GPIO /* and require always gpio features */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h index 2e902ee..8950d67 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260.h @@ -21,7 +21,6 @@ /* * defines to be used in other places */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ #define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* @@ -95,6 +94,7 @@ #define ATMEL_BASE_SDRAMC 0xffffea00 #define ATMEL_BASE_SMC 0xffffec00 #define ATMEL_BASE_MATRIX 0xffffee00 +#define ATMEL_BASE_CCFG 0xffffef14 #define ATMEL_BASE_AIC 0xfffff000 #define ATMEL_BASE_DBGU 0xfffff200 #define ATMEL_BASE_PIOA 0xfffff400 @@ -136,9 +136,11 @@ /* * Other misc defines */ +#ifndef CONFIG_DM_GPIO #define ATMEL_PIO_PORTS 3 /* these SoCs have 3 PIO */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP #define ATMEL_BASE_PIO ATMEL_BASE_PIOA +#endif +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP /* * SoC specific defines diff --git a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h index 4755fa1..dc61f48 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h @@ -61,5 +61,10 @@ struct at91_matrix { #define AT91_MATRIX_DBPUC (1 << 8) #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_EBI_IOSR_SEL (1 << 17) + +/* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) +#define AT91_MATRIX_SLOT_CYCLE_(x) (x << 0) #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h index f7ad113..6dfcf4c 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9261.h +++ b/arch/arm/include/asm/arch-at91/at91sam9261.h @@ -21,7 +21,6 @@ /* * defines to be used in other places */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ #define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h index 3206af8..64a3888 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9263.h +++ b/arch/arm/include/asm/arch-at91/at91sam9263.h @@ -17,7 +17,6 @@ /* * defines to be used in other places */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ #define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* diff --git a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h index 5c98cc7..3a076c6 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h +++ b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h @@ -25,6 +25,21 @@ #define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) #define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) +#else +struct sdramc_reg { + u32 mr; + u32 tr; + u32 cr; + u32 lpr; + u32 ier; + u32 idr; + u32 imr; + u32 isr; + u32 mdr; +}; + +int sdramc_initialize(unsigned int sdram_address, + const struct sdramc_reg *p); #endif /* SDRAM Controller (SDRAMC) registers */ @@ -62,11 +77,17 @@ #define AT91_SDRAMC_DBW_32 (0 << 7) #define AT91_SDRAMC_DBW_16 (1 << 7) #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ +#define AT91_SDRAMC_TWR_VAL(x) (x << 8) #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ +#define AT91_SDRAMC_TRC_VAL(x) (x << 12) #define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ +#define AT91_SDRAMC_TRP_VAL(x) (x << 16) #define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ +#define AT91_SDRAMC_TRCD_VAL(x) (x << 20) #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ +#define AT91_SDRAMC_TRAS_VAL(x) (x << 24) #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ +#define AT91_SDRAMC_TXSR_VAL(x) (x << 28) #define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ @@ -93,5 +114,4 @@ #define AT91_SDRAMC_MD_SDRAM 0 #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 - #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/include/asm/arch-at91/at91sam9g45.h index 9cbfc27..6df8cdb 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45.h +++ b/arch/arm/include/asm/arch-at91/at91sam9g45.h @@ -15,7 +15,6 @@ /* * defines to be used in other places */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ #define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h b/arch/arm/include/asm/arch-at91/at91sam9rl.h index 00b6aa4..3a8e6d6 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9rl.h +++ b/arch/arm/include/asm/arch-at91/at91sam9rl.h @@ -17,7 +17,6 @@ /* * defines to be used in other places */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ #define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h index d49c184..36a5cdf 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9x5.h +++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h @@ -12,7 +12,6 @@ #ifndef __AT91SAM9X5_H__ #define __AT91SAM9X5_H__ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ #define CONFIG_AT91FAMILY /* it's a member of AT91 family */ /* diff --git a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h index 5741f6e..130a85a 100644 --- a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h +++ b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h @@ -57,6 +57,7 @@ int ddr2_init(const unsigned int ram_address, #define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) #define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) #define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) +#define ATMEL_MPDDRC_CR_DQMS_SHARED (0x1 << 16) #define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17) #define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) #define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21) diff --git a/arch/arm/include/asm/arch-at91/atmel_serial.h b/arch/arm/include/asm/arch-at91/atmel_serial.h new file mode 100644 index 0000000..5bc094b --- /dev/null +++ b/arch/arm/include/asm/arch-at91/atmel_serial.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ATMEL_SERIAL_H +#define _ATMEL_SERIAL_H + +/* Information about a serial port */ +struct atmel_serial_platdata { + uint32_t base_addr; +}; + +#endif diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h index 4076a78..1d45e2d 100644 --- a/arch/arm/include/asm/arch-at91/clk.h +++ b/arch/arm/include/asm/arch-at91/clk.h @@ -10,6 +10,7 @@ #define __ASM_ARM_ARCH_CLK_H__ #include <asm/arch/hardware.h> +#include <asm/arch/at91_pmc.h> #include <asm/global_data.h> static inline unsigned long get_cpu_clk_rate(void) @@ -48,14 +49,34 @@ static inline u32 get_pllb_init(void) return gd->arch.at91_pllb_usb_init; } +#ifdef CPU_HAS_H32MXDIV +static inline unsigned int get_h32mxdiv(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV; +} +#else +static inline unsigned int get_h32mxdiv(void) +{ + return 0; +} +#endif + static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) { - return get_mck_clk_rate(); + if (get_h32mxdiv()) + return get_mck_clk_rate() / 2; + else + return get_mck_clk_rate(); } static inline unsigned long get_usart_clk_rate(unsigned int dev_id) { - return get_mck_clk_rate(); + if (get_h32mxdiv()) + return get_mck_clk_rate() / 2; + else + return get_mck_clk_rate(); } static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) @@ -65,17 +86,34 @@ static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) static inline unsigned long get_spi_clk_rate(unsigned int dev_id) { - return get_mck_clk_rate(); + if (get_h32mxdiv()) + return get_mck_clk_rate() / 2; + else + return get_mck_clk_rate(); } static inline unsigned long get_twi_clk_rate(unsigned int dev_id) { - return get_mck_clk_rate(); + if (get_h32mxdiv()) + return get_mck_clk_rate() / 2; + else + return get_mck_clk_rate(); } static inline unsigned long get_mci_clk_rate(void) { - return get_mck_clk_rate(); + if (get_h32mxdiv()) + return get_mck_clk_rate() / 2; + else + return get_mck_clk_rate(); +} + +static inline unsigned long get_pit_clk_rate(void) +{ + if (get_h32mxdiv()) + return get_mck_clk_rate() / 2; + else + return get_mck_clk_rate(); } int at91_clock_init(unsigned long main_clock); diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h index 7121388..6d2a7b7 100644 --- a/arch/arm/include/asm/arch-at91/gpio.h +++ b/arch/arm/include/asm/arch-at91/gpio.h @@ -253,4 +253,10 @@ static inline unsigned at91_gpio_to_pin(unsigned gpio) return gpio % 32; } +/* Platform data for each GPIO port */ +struct at91_port_platdata { + uint32_t base_addr; + const char *bank_name; +}; + #endif /* __ASM_ARCH_AT91_GPIO_H */ diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h index d712a0d..bf0a1bd 100644 --- a/arch/arm/include/asm/arch-at91/hardware.h +++ b/arch/arm/include/asm/arch-at91/hardware.h @@ -27,6 +27,8 @@ # include <asm/arch/at91cap9.h> #elif defined(CONFIG_SAMA5D3) # include <asm/arch/sama5d3.h> +#elif defined(CONFIG_SAMA5D4) +# include <asm/arch/sama5d4.h> #else # error "Unsupported AT91 processor" #endif diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/include/asm/arch-at91/sama5d3.h index f7bc4ad..227ba80 100644 --- a/arch/arm/include/asm/arch-at91/sama5d3.h +++ b/arch/arm/include/asm/arch-at91/sama5d3.h @@ -16,7 +16,6 @@ /* * defines to be used in other places */ -#define CONFIG_ARMV7 /* ARM A5 Core */ #define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* diff --git a/arch/arm/include/asm/arch-at91/sama5d4.h b/arch/arm/include/asm/arch-at91/sama5d4.h new file mode 100644 index 0000000..d851568 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/sama5d4.h @@ -0,0 +1,206 @@ +/* + * Chip-specific header file for the SAMA5D4 SoC + * + * Copyright (C) 2014 Atmel + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SAMA5D4_H +#define __SAMA5D4_H + +/* + * defines to be used in other places + */ +#define CONFIG_AT91FAMILY /* It's a member of AT91 */ + +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FIQ 0 /* FIQ Interrupt */ +#define ATMEL_ID_SYS 1 /* System Controller */ +#define ATMEL_ID_ARM 2 /* Performance Monitor Unit */ +#define ATMEL_ID_PIT 3 /* Periodic Interval Timer */ +#define ATMEL_ID_WDT 4 /* Watchdog timer */ +#define ATMEL_ID_PIOD 5 /* Parallel I/O Controller D */ +#define ATMEL_ID_USART0 6 /* USART 0 */ +#define ATMEL_ID_USART1 7 /* USART 1 */ +#define ATMEL_ID_DMA0 8 /* DMA Controller 0 */ +#define ATMEL_ID_ICM 9 /* Integrity Check Monitor */ +#define ATMEL_ID_PKCC 10 /* Public Key Crypto Controller */ +#define ATMEL_ID_AES 12 /* Advanced Encryption Standard */ +#define ATMEL_ID_AESB 13 /* AES Bridge*/ +#define ATMEL_ID_TDES 14 /* Triple Data Encryption Standard */ +#define ATMEL_ID_SHA 15 /* SHA Signature */ +#define ATMEL_ID_MPDDRC 16 /* MPDDR controller */ +#define ATMEL_ID_MATRIX1 17 /* H32MX, 32-bit AHB Matrix */ +#define ATMEL_ID_MATRIX0 18 /* H64MX, 64-bit AHB Matrix */ +#define ATMEL_ID_VDEC 19 /* Video Decoder */ +#define ATMEL_ID_SBM 20 /* Secure Box Module */ +#define ATMEL_ID_SMC 22 /* Multi-bit ECC interrupt */ +#define ATMEL_ID_PIOA 23 /* Parallel I/O Controller A */ +#define ATMEL_ID_PIOB 24 /* Parallel I/O Controller B */ +#define ATMEL_ID_PIOC 25 /* Parallel I/O Controller C */ +#define ATMEL_ID_PIOE 26 /* Parallel I/O Controller E */ +#define ATMEL_ID_UART0 27 /* UART 0 */ +#define ATMEL_ID_UART1 28 /* UART 1 */ +#define ATMEL_ID_USART2 29 /* USART 2 */ +#define ATMEL_ID_USART3 30 /* USART 3 */ +#define ATMEL_ID_USART4 31 /* USART 4 */ +#define ATMEL_ID_TWI0 32 /* Two-Wire Interface 0 */ +#define ATMEL_ID_TWI1 33 /* Two-Wire Interface 1 */ +#define ATMEL_ID_TWI2 34 /* Two-Wire Interface 2 */ +#define ATMEL_ID_MCI0 35 /* High Speed Multimedia Card Interface 0 */ +#define ATMEL_ID_MCI1 36 /* High Speed Multimedia Card Interface 1 */ +#define ATMEL_ID_SPI0 37 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 38 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_SPI2 39 /* Serial Peripheral Interface 2 */ +#define ATMEL_ID_TC0 40 /* Timer Counter 0 (ch. 0, 1, 2) */ +#define ATMEL_ID_TC1 41 /* Timer Counter 1 (ch. 3, 4, 5) */ +#define ATMEL_ID_TC2 42 /* Timer Counter 2 (ch. 6, 7, 8) */ +#define ATMEL_ID_PWMC 43 /* Pulse Width Modulation Controller */ +#define ATMEL_ID_ADC 44 /* Touch Screen ADC Controller */ +#define ATMEL_ID_DBGU 45 /* Debug Unit Interrupt */ +#define ATMEL_ID_UHPHS 46 /* USB Host High Speed */ +#define ATMEL_ID_UDPHS 47 /* USB Device High Speed */ +#define ATMEL_ID_SSC0 48 /* Synchronous Serial Controller 0 */ +#define ATMEL_ID_SSC1 49 /* Synchronous Serial Controller 1 */ +#define ATMEL_ID_XDMAC1 50 /* DMA Controller 1 */ +#define ATMEL_ID_LCDC 51 /* LCD Controller */ +#define ATMEL_ID_ISI 52 /* Image Sensor Interface */ +#define ATMEL_ID_TRNG 53 /* True Random Number Generator */ +#define ATMEL_ID_GMAC0 54 /* Ethernet MAC 0 */ +#define ATMEL_ID_GMAC1 55 /* Ethernet MAC 1 */ +#define ATMEL_ID_IRQ 56 /* IRQ Interrupt ID */ +#define ATMEL_ID_SFC 57 /* Fuse Controller */ +#define ATMEL_ID_SECURAM 59 /* Secured RAM */ +#define ATMEL_ID_SMD 61 /* SMD Soft Modem */ +#define ATMEL_ID_TWI3 62 /* Two-Wire Interface 3 */ +#define ATMEL_ID_CATB 63 /* Capacitive Touch Controller */ +#define ATMEL_ID_SFR 64 /* Special Funcion Register */ +#define ATMEL_ID_AIC 65 /* Advanced Interrupt Controller */ +#define ATMEL_ID_SAIC 66 /* Secured Advanced Interrupt Controller */ +#define ATMEL_ID_L2CC 67 /* L2 Cache Controller */ + +/* + * User Peripherals physical base addresses. + */ +#define ATMEL_BASE_LCDC 0xf0000000 +#define ATMEL_BASE_DMAC1 0xf0004000 +#define ATMEL_BASE_ISI 0xf0008000 +#define ATMEL_BASE_PKCC 0xf000C000 +#define ATMEL_BASE_MPDDRC 0xf0010000 +#define ATMEL_BASE_DMAC0 0xf0014000 +#define ATMEL_BASE_PMC 0xf0018000 +#define ATMEL_BASE_MATRIX0 0xf001c000 +#define ATMEL_BASE_AESB 0xf0020000 +/* Reserved: 0xf0024000 - 0xf8000000 */ +#define ATMEL_BASE_MCI0 0xf8000000 +#define ATMEL_BASE_UART0 0xf8004000 +#define ATMEL_BASE_SSC0 0xf8008000 +#define ATMEL_BASE_PWMC 0xf800c000 +#define ATMEL_BASE_SPI0 0xf8010000 +#define ATMEL_BASE_TWI0 0xf8014000 +#define ATMEL_BASE_TWI1 0xf8018000 +#define ATMEL_BASE_TC0 0xf801c000 +#define ATMEL_BASE_GMAC0 0xf8020000 +#define ATMEL_BASE_TWI2 0xf8024000 +#define ATMEL_BASE_SFR 0xf8028000 +#define ATMEL_BASE_USART0 0xf802c000 +#define ATMEL_BASE_USART1 0xf8030000 +/* Reserved: 0xf8034000 - 0xfc000000 */ +#define ATMEL_BASE_MCI1 0xfc000000 +#define ATMEL_BASE_UART1 0xfc004000 +#define ATMEL_BASE_USART2 0xfc008000 +#define ATMEL_BASE_USART3 0xfc00c000 +#define ATMEL_BASE_USART4 0xfc010000 +#define ATMEL_BASE_SSC1 0xfc014000 +#define ATMEL_BASE_SPI1 0xfc018000 +#define ATMEL_BASE_SPI2 0xfc01c000 +#define ATMEL_BASE_TC1 0xfc020000 +#define ATMEL_BASE_TC2 0xfc024000 +#define ATMEL_BASE_GMAC1 0xfc028000 +#define ATMEL_BASE_UDPHS 0xfc02c000 +#define ATMEL_BASE_TRNG 0xfc030000 +#define ATMEL_BASE_ADC 0xfc034000 +#define ATMEL_BASE_TWI3 0xfc038000 + +#define ATMEL_BASE_SMC 0xfc05c000 +#define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070) +#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500) + +#define ATMEL_BASE_PIOD 0xfc068000 +#define ATMEL_BASE_RSTC 0xfc068600 +#define ATMEL_BASE_PIT 0xfc068630 +#define ATMEL_BASE_WDT 0xfc068640 + +#define ATMEL_BASE_DBGU 0xfc069000 +#define ATMEL_BASE_PIOA 0xfc06a000 +#define ATMEL_BASE_PIOB 0xfc06b000 +#define ATMEL_BASE_PIOC 0xfc06c000 +#define ATMEL_BASE_PIOE 0xfc06d000 +#define ATMEL_BASE_AIC 0xfc06e000 + +/* + * Internal Memory. + */ +#define ATMEL_BASE_ROM 0x00000000 /* Internal ROM base address */ +#define ATMEL_BASE_NFC 0x00100000 /* NFC SRAM */ +#define ATMEL_BASE_SRAM 0x00200000 /* Internal ROM base address */ +#define ATMEL_BASE_VDEC 0x00300000 /* Video Decoder Controller */ +#define ATMEL_BASE_UDPHS_FIFO 0x00400000 /* USB Device HS controller */ +#define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller (OHCI) */ +#define ATMEL_BASE_EHCI 0x00600000 /* USB Host controller (EHCI) */ +#define ATMEL_BASE_AXI 0x00700000 +#define ATMEL_BASE_DAP 0x00800000 +#define ATMEL_BASE_SMD 0x00900000 + +/* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 +#define ATMEL_BASE_DDRCS 0x20000000 +#define ATMEL_BASE_CS1 0x60000000 +#define ATMEL_BASE_CS2 0x70000000 +#define ATMEL_BASE_CS3 0x80000000 + +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 5 +#define CPU_HAS_PIO3 +#define PIO_SCDR_DIV 0x3fff +#define CPU_HAS_PCR +#define CPU_HAS_H32MXDIV + +/* sama5d4 series chip id definitions */ +#define ARCH_ID_SAMA5D4 0x8a5c07c0 +#define ARCH_EXID_SAMA5D41 0x00000001 +#define ARCH_EXID_SAMA5D42 0x00000002 +#define ARCH_EXID_SAMA5D43 0x00000003 +#define ARCH_EXID_SAMA5D44 0x00000004 + +#define cpu_is_sama5d4() (get_chip_id() == ARCH_ID_SAMA5D4) +#define cpu_is_sama5d41() (cpu_is_sama5d4() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D41)) +#define cpu_is_sama5d42() (cpu_is_sama5d4() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D42)) +#define cpu_is_sama5d43() (cpu_is_sama5d4() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D43)) +#define cpu_is_sama5d44() (cpu_is_sama5d4() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D44)) + +/* + * No PMECC Galois table in ROM + */ +#define NO_GALOIS_TABLE_IN_ROM + +#ifndef __ASSEMBLY__ +unsigned int get_chip_id(void); +unsigned int get_extension_chip_id(void); +unsigned int has_lcdc(void); +char *get_cpu_name(void); +#endif + +#endif diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h index 61f427d..0289ba6 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/include/asm/arch-bcm2835/mbox.h @@ -119,6 +119,39 @@ struct bcm2835_mbox_tag_hdr { * }; */ +#define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002 + +/* + * 0x2..0xf from: + * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/ + * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733 + * 0x10, 0x11 from swarren's testing + */ +#define BCM2835_BOARD_REV_B_I2C0_2 0x2 +#define BCM2835_BOARD_REV_B_I2C0_3 0x3 +#define BCM2835_BOARD_REV_B_I2C1_4 0x4 +#define BCM2835_BOARD_REV_B_I2C1_5 0x5 +#define BCM2835_BOARD_REV_B_I2C1_6 0x6 +#define BCM2835_BOARD_REV_A_7 0x7 +#define BCM2835_BOARD_REV_A_8 0x8 +#define BCM2835_BOARD_REV_A_9 0x9 +#define BCM2835_BOARD_REV_B_REV2_d 0xd +#define BCM2835_BOARD_REV_B_REV2_e 0xe +#define BCM2835_BOARD_REV_B_REV2_f 0xf +#define BCM2835_BOARD_REV_B_PLUS 0x10 +#define BCM2835_BOARD_REV_CM 0x11 + +struct bcm2835_mbox_tag_get_board_rev { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + } req; + struct { + u32 rev; + } resp; + } body; +}; + #define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003 struct bcm2835_mbox_tag_get_mac_address { diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 78aceef..29674ad 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -227,6 +227,13 @@ static inline void s5p_set_cpu_id(void) /* Exynos5420 */ s5p_cpu_id = 0x5420; break; + case 0x422: + /* + * Exynos5800 is a variant of Exynos5420 + * and has product id 0x5422 + */ + s5p_cpu_id = 0x5800; + break; } } @@ -255,6 +262,7 @@ IS_EXYNOS_TYPE(exynos4210, 0x4210) IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250) IS_EXYNOS_TYPE(exynos5420, 0x5420) +IS_EXYNOS_TYPE(exynos5800, 0x5800) #define SAMSUNG_BASE(device, base) \ static inline unsigned int __attribute__((no_instrument_function)) \ @@ -265,7 +273,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \ return EXYNOS4X12_##base; \ return EXYNOS4_##base; \ } else if (cpu_is_exynos5()) { \ - if (proid_is_exynos5420()) \ + if (proid_is_exynos5420() || proid_is_exynos5800()) \ return EXYNOS5420_##base; \ return EXYNOS5_##base; \ } \ diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index ec3f9b6..4990a1a 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -450,6 +450,7 @@ enum mem_manuf { #define CONCONTROL_RD_FETCH_SHIFT 12 #define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT) #define CONCONTROL_AREF_EN_SHIFT 5 +#define CONCONTROL_UPDATE_MODE (1 << 3) /* PRECHCONFIG register field */ #define PRECHCONFIG_TP_CNT_SHIFT 24 diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h index d2d70bd..3800fa9 100644 --- a/arch/arm/include/asm/arch-exynos/ehci.h +++ b/arch/arm/include/asm/arch-exynos/ehci.h @@ -12,6 +12,13 @@ #define CLK_24MHZ 5 +#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0) +#define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6) +#define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9) +#define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12) +#define RSTCON_HOSTPHY_SWRST (0xf << 3) +#define RSTCON_SWRST (0x1 << 0) + #define HOST_CTRL0_PHYSWRSTALL (1 << 31) #define HOST_CTRL0_COMMONON_N (1 << 9) #define HOST_CTRL0_SIDDQ (1 << 6) @@ -61,6 +68,12 @@ struct exynos_usb_phy { unsigned int usbotgtune; }; +struct exynos4412_usb_phy { + unsigned int usbphyctrl; + unsigned int usbphyclk; + unsigned int usbphyrstcon; +}; + /* Switch on the VBUS power. */ int board_usb_vbus_init(void); diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 02287de..9699954 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -1398,7 +1398,7 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { static inline struct gpio_info *get_gpio_data(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_gpio_data; else return exynos5_gpio_data; @@ -1415,7 +1415,7 @@ static inline struct gpio_info *get_gpio_data(void) static inline unsigned int get_bank_num(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return EXYNOS5420_GPIO_NUM_PARTS; else return EXYNOS5_GPIO_NUM_PARTS; diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index e8a98a5..3f97b31 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -210,6 +210,13 @@ struct exynos4_power { unsigned int gps_alive_option; }; +struct exynos4412_power { + unsigned char res1[0x0704]; + unsigned int usbhost_phy_control; + unsigned int hsic1_phy_control; + unsigned int hsic2_phy_control; +}; + struct exynos5_power { unsigned int om_stat; unsigned char res1[0x18]; diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index a3cc96f..254136e 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -12,3 +12,8 @@ #define MXC_CPU_MX6Q 0x63 #define MXC_CPU_MX6D 0x64 #define MXC_CPU_MX6SOLO 0x65 /* dummy ID */ + +#define CS0_128 0 +#define CS0_64M_CS1_64M 1 +#define CS0_64M_CS1_32M_CS2_32M 2 +#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index ccc8e4e..e77ac40 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -24,7 +24,6 @@ #endif /* CONFIG_KW88F6281 */ #include <asm/arch/soc.h> -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_SYS_CACHELINE_SIZE 32 /* default Dcache Line length for kirkwood */ #define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index c985401..8f6426b 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -10,7 +10,6 @@ #define _LPC32XX_CONFIG_H /* Basic CPU architecture */ -#define CONFIG_ARM926EJS #define CONFIG_ARCH_CPU_INIT #define CONFIG_NR_DRAM_BANKS_MAX 2 diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index f2c9687..5e934da 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -11,11 +11,17 @@ #define OCRAM_BASE_ADDR 0x10000000 #define OCRAM_SIZE 0x00020000 +#define OCRAM_BASE_S_ADDR 0x10010000 +#define OCRAM_S_SIZE 0x00010000 #define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_DCSRBAR 0x20000000 + +#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) +#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) @@ -27,7 +33,10 @@ #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) +#define CONFIG_SYS_LS102XA_USB1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET) +#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 #define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 @@ -49,6 +58,9 @@ #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) + #ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM @@ -72,6 +84,10 @@ #define DCU_LAYER_MAX_NUM 16 +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 + #define CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_LS102XA @@ -80,6 +96,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_SEC_COMPAT 5 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 7995fe2..697d4ca 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -17,6 +17,9 @@ #define SOC_VER_LS1021 0x11 #define SOC_VER_LS1022 0x12 +#define CCSR_BRR_OFFSET 0xe4 +#define CCSR_SCRATCHRW1_OFFSET 0x200 + #define RCWSR0_SYS_PLL_RAT_SHIFT 25 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f #define RCWSR0_MEM_PLL_RAT_SHIFT 16 @@ -29,6 +32,11 @@ #define ARCH_TIMER_CTRL_ENABLE (1 << 0) #define SYS_COUNTER_CTRL_ENABLE (1 << 24) +#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 +#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 + +#define DCFG_DCSR_PORCR1 0 + struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; @@ -95,11 +103,10 @@ struct ccsr_gur { u32 sdhcpcr; }; -#define SCFG_SCFGREVCR_REV 0xffffffff -#define SCFG_SCFGREVCR_NOREV 0 #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 +#define SCFG_QSPI_CLKSEL 0xc0100000 /* Supplemental Configuration Unit */ struct ccsr_scfg { @@ -182,7 +189,7 @@ struct ccsr_scfg { u32 etsecmcr; u32 sdhciovserlcr; u32 resv14[61]; - u32 sparecr; + u32 sparecr[8]; }; /* Clocking */ @@ -448,6 +455,7 @@ struct ccsr_ddr { #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 #define CCI400_CTRLORD_EN_BARRIER 0 +#define CCI400_SHAORD_NON_SHAREABLE 0x00000002 /* CCI-400 registers */ struct ccsr_cci400 { diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h new file mode 100644 index 0000000..abd70fc --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h @@ -0,0 +1,17 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS102XA_STREAM_ID_H_ +#define __FSL_LS102XA_STREAM_ID_H_ + +struct smmu_stream_id { + uint16_t offset; + uint16_t stream_id; + char dev_name[32]; +}; + +void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num); +#endif diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h new file mode 100644 index 0000000..b53f699 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h @@ -0,0 +1,118 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_NS_ACCESS_H_ +#define __FSL_NS_ACCESS_H_ + +enum csu_cslx_access { + CSU_NS_SUP_R = 0x08, + CSU_NS_SUP_W = 0x80, + CSU_NS_SUP_RW = 0x88, + CSU_NS_USER_R = 0x04, + CSU_NS_USER_W = 0x40, + CSU_NS_USER_RW = 0x44, + CSU_S_SUP_R = 0x02, + CSU_S_SUP_W = 0x20, + CSU_S_SUP_RW = 0x22, + CSU_S_USER_R = 0x01, + CSU_S_USER_W = 0x10, + CSU_S_USER_RW = 0x11, + CSU_ALL_RW = 0xff, +}; + +enum csu_cslx_ind { + CSU_CSLX_PCIE2_IO = 0, + CSU_CSLX_PCIE1_IO, + CSU_CSLX_MG2TPR_IP, + CSU_CSLX_IFC_MEM, + CSU_CSLX_OCRAM, + CSU_CSLX_GIC, + CSU_CSLX_PCIE1, + CSU_CSLX_OCRAM2, + CSU_CSLX_QSPI_MEM, + CSU_CSLX_PCIE2, + CSU_CSLX_SATA, + CSU_CSLX_USB3, + CSU_CSLX_SERDES = 32, + CSU_CSLX_QDMA, + CSU_CSLX_LPUART2, + CSU_CSLX_LPUART1, + CSU_CSLX_LPUART4, + CSU_CSLX_LPUART3, + CSU_CSLX_LPUART6, + CSU_CSLX_LPUART5, + CSU_CSLX_DSPI2 = 40, + CSU_CSLX_DSPI1, + CSU_CSLX_QSPI, + CSU_CSLX_ESDHC, + CSU_CSLX_2D_ACE, + CSU_CSLX_IFC, + CSU_CSLX_I2C1, + CSU_CSLX_USB2, + CSU_CSLX_I2C3, + CSU_CSLX_I2C2, + CSU_CSLX_DUART2 = 50, + CSU_CSLX_DUART1, + CSU_CSLX_WDT2, + CSU_CSLX_WDT1, + CSU_CSLX_EDMA, + CSU_CSLX_SYS_CNT, + CSU_CSLX_DMA_MUX2, + CSU_CSLX_DMA_MUX1, + CSU_CSLX_DDR, + CSU_CSLX_QUICC, + CSU_CSLX_DCFG_CCU_RCPM = 60, + CSU_CSLX_SECURE_BOOTROM, + CSU_CSLX_SFP, + CSU_CSLX_TMU, + CSU_CSLX_SECURE_MONITOR, + CSU_CSLX_RESERVED0, + CSU_CSLX_ETSEC1, + CSU_CSLX_SEC5_5, + CSU_CSLX_ETSEC3, + CSU_CSLX_ETSEC2, + CSU_CSLX_GPIO2 = 70, + CSU_CSLX_GPIO1, + CSU_CSLX_GPIO4, + CSU_CSLX_GPIO3, + CSU_CSLX_PLATFORM_CONT, + CSU_CSLX_CSU, + CSU_CSLX_ASRC, + CSU_CSLX_SPDIF, + CSU_CSLX_FLEXCAN2, + CSU_CSLX_FLEXCAN1, + CSU_CSLX_FLEXCAN4 = 80, + CSU_CSLX_FLEXCAN3, + CSU_CSLX_SAI2, + CSU_CSLX_SAI1, + CSU_CSLX_SAI4, + CSU_CSLX_SAI3, + CSU_CSLX_FTM2, + CSU_CSLX_FTM1, + CSU_CSLX_FTM4, + CSU_CSLX_FTM3, + CSU_CSLX_FTM6 = 90, + CSU_CSLX_FTM5, + CSU_CSLX_FTM8, + CSU_CSLX_FTM7, + CSU_CSLX_COP_DCSR, + CSU_CSLX_EPU, + CSU_CSLX_GDI, + CSU_CSLX_DDI, + CSU_CSLX_RESERVED1, + CSU_CSLX_USB3_PHY = 117, + CSU_CSLX_RESERVED2, + CSU_CSLX_MAX, +}; + +struct csu_ns_dev { + unsigned long ind; + uint32_t val; +}; + +void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num); + +#endif diff --git a/arch/arm/include/asm/arch-ls102xa/spl.h b/arch/arm/include/asm/arch-ls102xa/spl.h new file mode 100644 index 0000000..26e4ea1 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/spl.h @@ -0,0 +1,20 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_SPL_H__ +#define __ASM_ARCH_SPL_H__ + +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_XIP 1 +#define BOOT_DEVICE_XIPWAIT 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_ONENAND 4 +#define BOOT_DEVICE_MMC1 5 +#define BOOT_DEVICE_MMC2 6 +#define BOOT_DEVICE_MMC2_2 7 +#define BOOT_DEVICE_SPI 10 + +#endif /* __ASM_ARCH_SPL_H__ */ diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 054c680..f059d0f 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -202,11 +202,6 @@ */ #define WBED 1 -#define CS0_128 0 -#define CS0_64M_CS1_64M 1 -#define CS0_64M_CS1_32M_CS2_32M 2 -#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 - /* * CSPI register definitions */ @@ -414,8 +409,7 @@ struct weim { #if defined(CONFIG_MX51) struct iomuxc { - u32 gpr0; - u32 gpr1; + u32 gpr[2]; u32 omux0; u32 omux1; u32 omux2; @@ -424,9 +418,7 @@ struct iomuxc { }; #elif defined(CONFIG_MX53) struct iomuxc { - u32 gpr0; - u32 gpr1; - u32 gpr2; + u32 gpr[3]; u32 omux0; u32 omux1; u32 omux2; diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 3c58a0a..226a4cd 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -43,10 +43,10 @@ enum mxc_clock { }; enum enet_freq { - ENET_25MHz, - ENET_50MHz, - ENET_100MHz, - ENET_125MHz, + ENET_25MHZ, + ENET_50MHZ, + ENET_100MHZ, + ENET_125MHZ, }; u32 imx_get_uartclk(void); @@ -60,10 +60,12 @@ void enable_uart_clk(unsigned char enable); int enable_cspi_clock(unsigned char enable, unsigned spi_num); int enable_usdhc_clk(unsigned char enable, unsigned bus_num); int enable_sata_clock(void); +void disable_sata_clock(void); int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(enum enet_freq freq); void enable_enet_clk(unsigned char enable); +void enable_thermal_clk(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index a159309..5314298 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -332,6 +332,43 @@ extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); #define SRC_SCR_CORE_3_ENABLE_OFFSET 24 #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET) +/* WEIM registers */ +struct weim { + u32 cs0gcr1; + u32 cs0gcr2; + u32 cs0rcr1; + u32 cs0rcr2; + u32 cs0wcr1; + u32 cs0wcr2; + + u32 cs1gcr1; + u32 cs1gcr2; + u32 cs1rcr1; + u32 cs1rcr2; + u32 cs1wcr1; + u32 cs1wcr2; + + u32 cs2gcr1; + u32 cs2gcr2; + u32 cs2rcr1; + u32 cs2rcr2; + u32 cs2wcr1; + u32 cs2wcr2; + + u32 cs3gcr1; + u32 cs3gcr2; + u32 cs3rcr1; + u32 cs3rcr2; + u32 cs3wcr1; + u32 cs3wcr2; + + u32 unused[12]; + + u32 wcr; + u32 wiar; + u32 ear; +}; + /* System Reset Controller (SRC) */ struct src { u32 scr; diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index c35a9051..28ba844 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -26,6 +26,7 @@ u32 get_cpu_rev(void); const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); +void set_chipselect_size(int const); /* * Initializes on-chip ethernet controllers. diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 30d9de2..0dc584b 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -278,11 +278,11 @@ /* TPS659038 */ #define TPS659038_I2C_SLAVE_ADDR 0x58 -#define TPS659038_REG_ADDR_SMPS12_MPU 0x23 -#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B -#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F -#define TPS659038_REG_ADDR_SMPS7_CORE 0x33 -#define TPS659038_REG_ADDR_SMPS8_IVA 0x37 +#define TPS659038_REG_ADDR_SMPS12 0x23 +#define TPS659038_REG_ADDR_SMPS45 0x2B +#define TPS659038_REG_ADDR_SMPS6 0x2F +#define TPS659038_REG_ADDR_SMPS7 0x33 +#define TPS659038_REG_ADDR_SMPS8 0x37 /* TPS */ #define TPS62361_I2C_SLAVE_ADDR 0x60 @@ -314,7 +314,7 @@ */ #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 -#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) #define V_OSCK 20000000 /* Clock output from T2 */ #else #define V_OSCK 19200000 /* Clock output from T2 */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index b9600cf..e218159 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -27,7 +27,7 @@ #define CONTROL_CORE_ID_CODE 0x4A002204 #define CONTROL_WKUP_ID_CODE 0x4AE0C204 -#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE #else #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE @@ -163,7 +163,7 @@ struct s32ktimer { * much larger) and do not, at this time, make use of the additional * space. */ -#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ #else diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h index fdccd22..1eed7b1 100644 --- a/arch/arm/include/asm/arch-pantheon/config.h +++ b/arch/arm/include/asm/arch-pantheon/config.h @@ -11,7 +11,6 @@ #include <asm/arch/pantheon.h> -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ /* default Dcache Line length for pantheon */ #define CONFIG_SYS_CACHELINE_SIZE 32 diff --git a/arch/arm/include/asm/arch-rmobile/gpio.h b/arch/arm/include/asm/arch-rmobile/gpio.h index d25ea61..93b20af 100644 --- a/arch/arm/include/asm/arch-rmobile/gpio.h +++ b/arch/arm/include/asm/arch-rmobile/gpio.h @@ -13,6 +13,9 @@ void r8a7790_pinmux_init(void); #elif defined(CONFIG_R8A7791) #include "r8a7791-gpio.h" void r8a7791_pinmux_init(void); +#elif defined(CONFIG_R8A7793) +#include "r8a7793-gpio.h" +void r8a7793_pinmux_init(void); #elif defined(CONFIG_R8A7794) #include "r8a7794-gpio.h" void r8a7794_pinmux_init(void); diff --git a/arch/arm/include/asm/arch-rmobile/mmc.h b/arch/arm/include/asm/arch-rmobile/mmc.h new file mode 100644 index 0000000..4e0fef1 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/mmc.h @@ -0,0 +1,14 @@ +/* + * Renesas SuperH MMCIF driver. + * + * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef _RMOBILE_MMC_H_ +#define _RMOBILE_MMC_H_ + +int mmcif_mmc_init(void); + +#endif /* _RMOBILE_MMC_H_ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h index 6ef665d..132d58c 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7790.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h @@ -11,6 +11,23 @@ #include "rcar-base.h" +/* SH-I2C */ +#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000 +#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000 + +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00640801 +#define MSTP1_BITS 0xDB6E9BDF +#define MSTP2_BITS 0x300DA1FC +#define MSTP3_BITS 0xF08CF831 +#define MSTP4_BITS 0x80000184 +#define MSTP5_BITS 0x44C00046 +#define MSTP7_BITS 0x07F30718 +#define MSTP8_BITS 0x01F0FF84 +#define MSTP9_BITS 0xF5979FCF +#define MSTP10_BITS 0xFFFEFFE0 +#define MSTP11_BITS 0x00000000 + #define R8A7790_CUT_ES2X 2 #define IS_R8A7790_ES2() \ (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X) diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h index 592c524..d2cbcd7 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7791.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h @@ -13,6 +13,10 @@ /* * R-Car (R8A7791) I/O Addresses */ + +/* SH-I2C */ +#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 + #define DBSC3_1_QOS_R0_BASE 0xE67A1000 #define DBSC3_1_QOS_R1_BASE 0xE67A1100 #define DBSC3_1_QOS_R2_BASE 0xE67A1200 @@ -47,6 +51,19 @@ #define DBSC3_1_QOS_W15_BASE 0xE67A2F00 #define DBSC3_1_DBADJ2 0xE67A00C8 +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00640801 +#define MSTP1_BITS 0x9B6C9B5A +#define MSTP2_BITS 0x100D21FC +#define MSTP3_BITS 0xF08CD810 +#define MSTP4_BITS 0x800001C4 +#define MSTP5_BITS 0x44C00046 +#define MSTP7_BITS 0x05BFE618 +#define MSTP8_BITS 0x40C0FE85 +#define MSTP9_BITS 0xFF979FFF +#define MSTP10_BITS 0xFFFEFFE0 +#define MSTP11_BITS 0x000001C0 + #define R8A7791_CUT_ES2X 2 #define IS_R8A7791_ES2() \ (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X) diff --git a/arch/arm/include/asm/arch-rmobile/r8a7793-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7793-gpio.h new file mode 100644 index 0000000..f9a29fc --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7793-gpio.h @@ -0,0 +1,438 @@ +#ifndef __ASM_R8A7793_H__ +#define __ASM_R8A7793_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU + */ +enum { + GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, + GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, + GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, + GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, + GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, + GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, + GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, + GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, + + GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, + GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, + GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, + GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, + GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, + GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, + GPIO_GP_1_24, GPIO_GP_1_25, + + GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, + GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, + GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, + GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, + GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, + GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, + GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, + GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31, + + GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, + GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, + GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, + GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, + GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, + GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, + GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, + GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, + + GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, + GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, + GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, + GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, + GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, + GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, + GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, + GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, + + GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, + GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, + GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, + GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, + GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, + GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, + GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, + GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31, + + GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, + GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, + GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, + GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, + GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, + GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, + GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27, + GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31, + + GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3, + GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7, + GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11, + GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15, + GPIO_GP_7_16, GPIO_GP_7_17, GPIO_GP_7_18, GPIO_GP_7_19, + GPIO_GP_7_20, GPIO_GP_7_21, GPIO_GP_7_22, GPIO_GP_7_23, + GPIO_GP_7_24, GPIO_GP_7_25, + + GPIO_FN_EX_CS0_N, GPIO_FN_RD_N, GPIO_FN_AUDIO_CLKA, + GPIO_FN_VI0_CLK, GPIO_FN_VI0_DATA0_VI0_B0, + GPIO_FN_VI0_DATA0_VI0_B1, GPIO_FN_VI0_DATA0_VI0_B2, + GPIO_FN_VI0_DATA0_VI0_B4, GPIO_FN_VI0_DATA0_VI0_B5, + GPIO_FN_VI0_DATA0_VI0_B6, GPIO_FN_VI0_DATA0_VI0_B7, + GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN, + + /* IPSR0 */ + GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5, + GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10, + GPIO_FN_D11, GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15, + GPIO_FN_A0, GPIO_FN_ATAWR0_N_C, GPIO_FN_MSIOF0_SCK_B, + GPIO_FN_SCL0_C, GPIO_FN_PWM2_B, + GPIO_FN_A1, GPIO_FN_MSIOF0_SYNC_B, GPIO_FN_A2, GPIO_FN_MSIOF0_SS1_B, + GPIO_FN_A3, GPIO_FN_MSIOF0_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF0_TXD_B, + GPIO_FN_A5, GPIO_FN_MSIOF0_RXD_B, GPIO_FN_A6, GPIO_FN_MSIOF1_SCK, + + /* IPSR1 */ + GPIO_FN_A7, GPIO_FN_MSIOF1_SYNC, GPIO_FN_A8, + GPIO_FN_MSIOF1_SS1, GPIO_FN_SCL0, + GPIO_FN_A9, GPIO_FN_MSIOF1_SS2, GPIO_FN_SDA0, + GPIO_FN_A10, GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_TXD_D, + GPIO_FN_A11, GPIO_FN_MSIOF1_RXD, GPIO_FN_SCL3_D, GPIO_FN_MSIOF1_RXD_D, + GPIO_FN_A12, GPIO_FN_FMCLK, GPIO_FN_SDA3_D, GPIO_FN_MSIOF1_SCK_D, + GPIO_FN_A13, GPIO_FN_ATAG0_N_C, GPIO_FN_BPFCLK, GPIO_FN_MSIOF1_SS1_D, + GPIO_FN_A14, GPIO_FN_ATADIR0_N_C, GPIO_FN_FMIN, + GPIO_FN_FMIN_C, GPIO_FN_MSIOF1_SYNC_D, + GPIO_FN_A15, GPIO_FN_BPFCLK_C, + GPIO_FN_A16, GPIO_FN_DREQ2_B, GPIO_FN_FMCLK_C, GPIO_FN_SCIFA1_SCK_B, + GPIO_FN_A17, GPIO_FN_DACK2_B, GPIO_FN_SDA0_C, + GPIO_FN_A18, GPIO_FN_DREQ1, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_SCIFB1_RXD_C, + + /* IPSR2 */ + GPIO_FN_A19, GPIO_FN_DACK1, GPIO_FN_SCIFA1_TXD_C, + GPIO_FN_SCIFB1_TXD_C, GPIO_FN_SCIFB1_SCK_B, + GPIO_FN_A20, GPIO_FN_SPCLK, + GPIO_FN_A21, GPIO_FN_ATAWR0_N_B, GPIO_FN_MOSI_IO0, + GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_FMCLK_B, + GPIO_FN_TX0, GPIO_FN_SCIFA0_TXD, + GPIO_FN_A23, GPIO_FN_IO2, GPIO_FN_BPFCLK_B, + GPIO_FN_RX0, GPIO_FN_SCIFA0_RXD, + GPIO_FN_A24, GPIO_FN_DREQ2, GPIO_FN_IO3, + GPIO_FN_TX1, GPIO_FN_SCIFA1_TXD, + GPIO_FN_A25, GPIO_FN_DACK2, GPIO_FN_SSL, GPIO_FN_DREQ1_C, + GPIO_FN_RX1, GPIO_FN_SCIFA1_RXD, + GPIO_FN_CS0_N, GPIO_FN_ATAG0_N_B, GPIO_FN_SCL1, + GPIO_FN_CS1_N_A26, GPIO_FN_ATADIR0_N_B, GPIO_FN_SDA1, + GPIO_FN_EX_CS1_N, GPIO_FN_MSIOF2_SCK, + GPIO_FN_EX_CS2_N, GPIO_FN_ATAWR0_N, GPIO_FN_MSIOF2_SYNC, + GPIO_FN_EX_CS3_N, GPIO_FN_ATADIR0_N, GPIO_FN_MSIOF2_TXD, + GPIO_FN_ATAG0_N, GPIO_FN_EX_WAIT1, + + /* IPSR3 */ + GPIO_FN_EX_CS4_N, GPIO_FN_ATARD0_N, + GPIO_FN_MSIOF2_RXD, GPIO_FN_EX_WAIT2, + GPIO_FN_EX_CS5_N, GPIO_FN_ATACS00_N, GPIO_FN_MSIOF2_SS1, + GPIO_FN_HRX1_B, GPIO_FN_SCIFB1_RXD_B, + GPIO_FN_PWM1, GPIO_FN_TPU_TO1, + GPIO_FN_BS_N, GPIO_FN_ATACS10_N, GPIO_FN_MSIOF2_SS2, + GPIO_FN_HTX1_B, GPIO_FN_SCIFB1_TXD_B, + GPIO_FN_PWM2, GPIO_FN_TPU_TO2, + GPIO_FN_RD_WR_N, GPIO_FN_HRX2_B, GPIO_FN_FMIN_B, + GPIO_FN_SCIFB0_RXD_B, GPIO_FN_DREQ1_D, + GPIO_FN_WE0_N, GPIO_FN_HCTS2_N_B, GPIO_FN_SCIFB0_TXD_B, + GPIO_FN_WE1_N, GPIO_FN_ATARD0_N_B, + GPIO_FN_HTX2_B, GPIO_FN_SCIFB0_RTS_N_B, + GPIO_FN_EX_WAIT0, GPIO_FN_HRTS2_N_B, GPIO_FN_SCIFB0_CTS_N_B, + GPIO_FN_DREQ0, GPIO_FN_PWM3, GPIO_FN_TPU_TO3, + GPIO_FN_DACK0, GPIO_FN_DRACK0, GPIO_FN_REMOCON, + GPIO_FN_SPEEDIN, GPIO_FN_HSCK0_C, GPIO_FN_HSCK2_C, + GPIO_FN_SCIFB0_SCK_B, GPIO_FN_SCIFB2_SCK_B, + GPIO_FN_DREQ2_C, GPIO_FN_HTX2_D, + GPIO_FN_SSI_SCK0129, GPIO_FN_HRX0_C, GPIO_FN_HRX2_C, + GPIO_FN_SCIFB0_RXD_C, GPIO_FN_SCIFB2_RXD_C, + GPIO_FN_SSI_WS0129, GPIO_FN_HTX0_C, GPIO_FN_HTX2_C, + GPIO_FN_SCIFB0_TXD_C, GPIO_FN_SCIFB2_TXD_C, + + /* IPSR4 */ + GPIO_FN_SSI_SDATA0, GPIO_FN_SCL0_B, + GPIO_FN_SCL7_B, GPIO_FN_MSIOF2_SCK_C, + GPIO_FN_SSI_SCK1, GPIO_FN_SDA0_B, GPIO_FN_SDA7_B, + GPIO_FN_MSIOF2_SYNC_C, GPIO_FN_GLO_I0_D, + GPIO_FN_SSI_WS1, GPIO_FN_SCL1_B, GPIO_FN_SCL8_B, + GPIO_FN_MSIOF2_TXD_C, GPIO_FN_GLO_I1_D, + GPIO_FN_SSI_SDATA1, GPIO_FN_SDA1_B, + GPIO_FN_SDA8_B, GPIO_FN_MSIOF2_RXD_C, + GPIO_FN_SSI_SCK2, GPIO_FN_SCL2, GPIO_FN_GPS_CLK_B, + GPIO_FN_GLO_Q0_D, GPIO_FN_HSCK1_E, + GPIO_FN_SSI_WS2, GPIO_FN_SDA2, GPIO_FN_GPS_SIGN_B, + GPIO_FN_RX2_E, GPIO_FN_GLO_Q1_D, GPIO_FN_HCTS1_N_E, + GPIO_FN_SSI_SDATA2, GPIO_FN_GPS_MAG_B, + GPIO_FN_TX2_E, GPIO_FN_HRTS1_N_E, + GPIO_FN_SSI_SCK34, GPIO_FN_SSI_WS34, GPIO_FN_SSI_SDATA3, + GPIO_FN_SSI_SCK4, GPIO_FN_GLO_SS_D, + GPIO_FN_SSI_WS4, GPIO_FN_GLO_RFON_D, + GPIO_FN_SSI_SDATA4, GPIO_FN_MSIOF2_SCK_D, + GPIO_FN_SSI_SCK5, GPIO_FN_MSIOF1_SCK_C, + GPIO_FN_TS_SDATA0, GPIO_FN_GLO_I0, + GPIO_FN_MSIOF2_SYNC_D, GPIO_FN_VI1_R2_B, + + /* IPSR5 */ + GPIO_FN_SSI_WS5, GPIO_FN_MSIOF1_SYNC_C, GPIO_FN_TS_SCK0, + GPIO_FN_GLO_I1, GPIO_FN_MSIOF2_TXD_D, GPIO_FN_VI1_R3_B, + GPIO_FN_SSI_SDATA5, GPIO_FN_MSIOF1_TXD_C, GPIO_FN_TS_SDEN0, + GPIO_FN_GLO_Q0, GPIO_FN_MSIOF2_SS1_D, GPIO_FN_VI1_R4_B, + GPIO_FN_SSI_SCK6, GPIO_FN_MSIOF1_RXD_C, GPIO_FN_TS_SPSYNC0, + GPIO_FN_GLO_Q1, GPIO_FN_MSIOF2_RXD_D, GPIO_FN_VI1_R5_B, + GPIO_FN_SSI_WS6, GPIO_FN_GLO_SCLK, + GPIO_FN_MSIOF2_SS2_D, GPIO_FN_VI1_R6_B, + GPIO_FN_SSI_SDATA6, GPIO_FN_STP_IVCXO27_0_B, + GPIO_FN_GLO_SDATA, GPIO_FN_VI1_R7_B, + GPIO_FN_SSI_SCK78, GPIO_FN_STP_ISCLK_0_B, GPIO_FN_GLO_SS, + GPIO_FN_SSI_WS78, GPIO_FN_TX0_D, GPIO_FN_STP_ISD_0_B, GPIO_FN_GLO_RFON, + GPIO_FN_SSI_SDATA7, GPIO_FN_RX0_D, GPIO_FN_STP_ISEN_0_B, + GPIO_FN_SSI_SDATA8, GPIO_FN_TX1_D, GPIO_FN_STP_ISSYNC_0_B, + GPIO_FN_SSI_SCK9, GPIO_FN_RX1_D, GPIO_FN_GLO_SCLK_D, + GPIO_FN_SSI_WS9, GPIO_FN_TX3_D, GPIO_FN_CAN0_TX_D, GPIO_FN_GLO_SDATA_D, + GPIO_FN_SSI_SDATA9, GPIO_FN_RX3_D, GPIO_FN_CAN0_RX_D, + + /* IPSR6 */ + GPIO_FN_AUDIO_CLKB, GPIO_FN_STP_OPWM_0_B, GPIO_FN_MSIOF1_SCK_B, + GPIO_FN_SCIF_CLK, GPIO_FN_BPFCLK_E, + GPIO_FN_AUDIO_CLKC, GPIO_FN_SCIFB0_SCK_C, GPIO_FN_MSIOF1_SYNC_B, + GPIO_FN_RX2, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN_E, + GPIO_FN_AUDIO_CLKOUT, GPIO_FN_MSIOF1_SS1_B, + GPIO_FN_TX2, GPIO_FN_SCIFA2_TXD, + GPIO_FN_IRQ0, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_INTC_IRQ0_N, + GPIO_FN_IRQ1, GPIO_FN_SCIFB1_SCK_C, GPIO_FN_INTC_IRQ1_N, + GPIO_FN_IRQ2, GPIO_FN_SCIFB1_TXD_D, GPIO_FN_INTC_IRQ2_N, + GPIO_FN_IRQ3, GPIO_FN_SCL4_C, + GPIO_FN_MSIOF2_TXD_E, GPIO_FN_INTC_IRQ3_N, + GPIO_FN_IRQ4, GPIO_FN_HRX1_C, GPIO_FN_SDA4_C, + GPIO_FN_MSIOF2_RXD_E, GPIO_FN_INTC_IRQ4_N, + GPIO_FN_IRQ5, GPIO_FN_HTX1_C, GPIO_FN_SCL1_E, GPIO_FN_MSIOF2_SCK_E, + GPIO_FN_IRQ6, GPIO_FN_HSCK1_C, GPIO_FN_MSIOF1_SS2_B, + GPIO_FN_SDA1_E, GPIO_FN_MSIOF2_SYNC_E, + GPIO_FN_IRQ7, GPIO_FN_HCTS1_N_C, GPIO_FN_MSIOF1_TXD_B, + GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D, + GPIO_FN_IRQ8, GPIO_FN_HRTS1_N_C, GPIO_FN_MSIOF1_RXD_B, + GPIO_FN_GPS_SIGN_C, GPIO_FN_GPS_SIGN_D, + + /* IPSR7 */ + GPIO_FN_IRQ9, GPIO_FN_DU1_DOTCLKIN_B, GPIO_FN_CAN_CLK_D, + GPIO_FN_GPS_MAG_C, GPIO_FN_SCIF_CLK_B, GPIO_FN_GPS_MAG_D, + GPIO_FN_DU1_DR0, GPIO_FN_LCDOUT0, GPIO_FN_VI1_DATA0_B, GPIO_FN_TX0_B, + GPIO_FN_SCIFA0_TXD_B, GPIO_FN_MSIOF2_SCK_B, + GPIO_FN_DU1_DR1, GPIO_FN_LCDOUT1, GPIO_FN_VI1_DATA1_B, GPIO_FN_RX0_B, + GPIO_FN_SCIFA0_RXD_B, GPIO_FN_MSIOF2_SYNC_B, + GPIO_FN_DU1_DR2, GPIO_FN_LCDOUT2, GPIO_FN_SSI_SCK0129_B, + GPIO_FN_DU1_DR3, GPIO_FN_LCDOUT3, GPIO_FN_SSI_WS0129_B, + GPIO_FN_DU1_DR4, GPIO_FN_LCDOUT4, GPIO_FN_SSI_SDATA0_B, + GPIO_FN_DU1_DR5, GPIO_FN_LCDOUT5, GPIO_FN_SSI_SCK1_B, + GPIO_FN_DU1_DR6, GPIO_FN_LCDOUT6, GPIO_FN_SSI_WS1_B, + GPIO_FN_DU1_DR7, GPIO_FN_LCDOUT7, GPIO_FN_SSI_SDATA1_B, + GPIO_FN_DU1_DG0, GPIO_FN_LCDOUT8, GPIO_FN_VI1_DATA2_B, GPIO_FN_TX1_B, + GPIO_FN_SCIFA1_TXD_B, GPIO_FN_MSIOF2_SS1_B, + GPIO_FN_DU1_DG1, GPIO_FN_LCDOUT9, GPIO_FN_VI1_DATA3_B, GPIO_FN_RX1_B, + GPIO_FN_SCIFA1_RXD_B, GPIO_FN_MSIOF2_SS2_B, + GPIO_FN_DU1_DG2, GPIO_FN_LCDOUT10, GPIO_FN_VI1_DATA4_B, + GPIO_FN_SCIF1_SCK_B, GPIO_FN_SCIFA1_SCK, GPIO_FN_SSI_SCK78_B, + + /* IPSR8 */ + GPIO_FN_DU1_DG3, GPIO_FN_LCDOUT11, + GPIO_FN_VI1_DATA5_B, GPIO_FN_SSI_WS78_B, + GPIO_FN_DU1_DG4, GPIO_FN_LCDOUT12, GPIO_FN_VI1_DATA6_B, + GPIO_FN_HRX0_B, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_SSI_SDATA7_B, + GPIO_FN_DU1_DG5, GPIO_FN_LCDOUT13, GPIO_FN_VI1_DATA7_B, + GPIO_FN_HCTS0_N_B, GPIO_FN_SCIFB2_TXD_B, GPIO_FN_SSI_SDATA8_B, + GPIO_FN_DU1_DG6, GPIO_FN_LCDOUT14, GPIO_FN_HRTS0_N_B, + GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_SSI_SCK9_B, + GPIO_FN_DU1_DG7, GPIO_FN_LCDOUT15, GPIO_FN_HTX0_B, + GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_SSI_WS9_B, + GPIO_FN_DU1_DB0, GPIO_FN_LCDOUT16, GPIO_FN_VI1_CLK_B, GPIO_FN_TX2_B, + GPIO_FN_SCIFA2_TXD_B, GPIO_FN_MSIOF2_TXD_B, + GPIO_FN_DU1_DB1, GPIO_FN_LCDOUT17, GPIO_FN_VI1_HSYNC_N_B, + GPIO_FN_RX2_B, GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF2_RXD_B, + GPIO_FN_DU1_DB2, GPIO_FN_LCDOUT18, GPIO_FN_VI1_VSYNC_N_B, + GPIO_FN_SCIF2_SCK_B, GPIO_FN_SCIFA2_SCK, GPIO_FN_SSI_SDATA9_B, + GPIO_FN_DU1_DB3, GPIO_FN_LCDOUT19, GPIO_FN_VI1_CLKENB_B, + GPIO_FN_DU1_DB4, GPIO_FN_LCDOUT20, + GPIO_FN_VI1_FIELD_B, GPIO_FN_CAN1_RX, + GPIO_FN_DU1_DB5, GPIO_FN_LCDOUT21, GPIO_FN_TX3, + GPIO_FN_SCIFA3_TXD, GPIO_FN_CAN1_TX, + + /* IPSR9 */ + GPIO_FN_DU1_DB6, GPIO_FN_LCDOUT22, GPIO_FN_SCL3_C, + GPIO_FN_RX3, GPIO_FN_SCIFA3_RXD, + GPIO_FN_DU1_DB7, GPIO_FN_LCDOUT23, GPIO_FN_SDA3_C, + GPIO_FN_SCIF3_SCK, GPIO_FN_SCIFA3_SCK, + GPIO_FN_DU1_DOTCLKIN, GPIO_FN_QSTVA_QVS, + GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_QCLK, + GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_QSTVB_QVE, GPIO_FN_CAN0_TX, + GPIO_FN_TX3_B, GPIO_FN_SCL2_B, GPIO_FN_PWM4, + GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_QSTH_QHS, + GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_QSTB_QHE, + GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, + GPIO_FN_CAN0_RX, GPIO_FN_RX3_B, GPIO_FN_SDA2_B, + GPIO_FN_DU1_DISP, GPIO_FN_QPOLA, + GPIO_FN_DU1_CDE, GPIO_FN_QPOLB, GPIO_FN_PWM4_B, + GPIO_FN_VI0_CLKENB, GPIO_FN_TX4, + GPIO_FN_SCIFA4_TXD, GPIO_FN_TS_SDATA0_D, + GPIO_FN_VI0_FIELD, GPIO_FN_RX4, GPIO_FN_SCIFA4_RXD, GPIO_FN_TS_SCK0_D, + GPIO_FN_VI0_HSYNC_N, GPIO_FN_TX5, + GPIO_FN_SCIFA5_TXD, GPIO_FN_TS_SDEN0_D, + GPIO_FN_VI0_VSYNC_N, GPIO_FN_RX5, + GPIO_FN_SCIFA5_RXD, GPIO_FN_TS_SPSYNC0_D, + GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_SCIF3_SCK_B, GPIO_FN_SCIFA3_SCK_B, + GPIO_FN_VI0_G0, GPIO_FN_SCL8, GPIO_FN_STP_IVCXO27_0_C, GPIO_FN_SCL4, + GPIO_FN_HCTS2_N, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_ATAWR1_N, + + /* IPSR10 */ + GPIO_FN_VI0_G1, GPIO_FN_SDA8, GPIO_FN_STP_ISCLK_0_C, GPIO_FN_SDA4, + GPIO_FN_HRTS2_N, GPIO_FN_SCIFB2_RTS_N, GPIO_FN_ATADIR1_N, + GPIO_FN_VI0_G2, GPIO_FN_VI2_HSYNC_N, GPIO_FN_STP_ISD_0_C, + GPIO_FN_SCL3_B, GPIO_FN_HSCK2, GPIO_FN_SCIFB2_SCK, GPIO_FN_ATARD1_N, + GPIO_FN_VI0_G3, GPIO_FN_VI2_VSYNC_N, GPIO_FN_STP_ISEN_0_C, + GPIO_FN_SDA3_B, GPIO_FN_HRX2, GPIO_FN_SCIFB2_RXD, GPIO_FN_ATACS01_N, + GPIO_FN_VI0_G4, GPIO_FN_VI2_CLKENB, GPIO_FN_STP_ISSYNC_0_C, + GPIO_FN_HTX2, GPIO_FN_SCIFB2_TXD, GPIO_FN_SCIFB0_SCK_D, + GPIO_FN_VI0_G5, GPIO_FN_VI2_FIELD, GPIO_FN_STP_OPWM_0_C, + GPIO_FN_FMCLK_D, GPIO_FN_CAN0_TX_E, + GPIO_FN_HTX1_D, GPIO_FN_SCIFB0_TXD_D, + GPIO_FN_VI0_G6, GPIO_FN_VI2_CLK, GPIO_FN_BPFCLK_D, + GPIO_FN_VI0_G7, GPIO_FN_VI2_DATA0, GPIO_FN_FMIN_D, + GPIO_FN_VI0_R0, GPIO_FN_VI2_DATA1, GPIO_FN_GLO_I0_B, + GPIO_FN_TS_SDATA0_C, GPIO_FN_ATACS11_N, + GPIO_FN_VI0_R1, GPIO_FN_VI2_DATA2, GPIO_FN_GLO_I1_B, + GPIO_FN_TS_SCK0_C, GPIO_FN_ATAG1_N, + GPIO_FN_VI0_R2, GPIO_FN_VI2_DATA3, + GPIO_FN_GLO_Q0_B, GPIO_FN_TS_SDEN0_C, + GPIO_FN_VI0_R3, GPIO_FN_VI2_DATA4, + GPIO_FN_GLO_Q1_B, GPIO_FN_TS_SPSYNC0_C, + GPIO_FN_VI0_R4, GPIO_FN_VI2_DATA5, GPIO_FN_GLO_SCLK_B, + GPIO_FN_TX0_C, GPIO_FN_SCL1_D, + + /* IPSR11 */ + GPIO_FN_VI0_R5, GPIO_FN_VI2_DATA6, GPIO_FN_GLO_SDATA_B, + GPIO_FN_RX0_C, GPIO_FN_SDA1_D, + GPIO_FN_VI0_R6, GPIO_FN_VI2_DATA7, GPIO_FN_GLO_SS_B, + GPIO_FN_TX1_C, GPIO_FN_SCL4_B, + GPIO_FN_VI0_R7, GPIO_FN_GLO_RFON_B, GPIO_FN_RX1_C, GPIO_FN_CAN0_RX_E, + GPIO_FN_SDA4_B, GPIO_FN_HRX1_D, GPIO_FN_SCIFB0_RXD_D, + GPIO_FN_VI1_HSYNC_N, GPIO_FN_AVB_RXD0, GPIO_FN_TS_SDATA0_B, + GPIO_FN_TX4_B, GPIO_FN_SCIFA4_TXD_B, + GPIO_FN_VI1_VSYNC_N, GPIO_FN_AVB_RXD1, GPIO_FN_TS_SCK0_B, + GPIO_FN_RX4_B, GPIO_FN_SCIFA4_RXD_B, + GPIO_FN_VI1_CLKENB, GPIO_FN_AVB_RXD2, GPIO_FN_TS_SDEN0_B, + GPIO_FN_VI1_FIELD, GPIO_FN_AVB_RXD3, GPIO_FN_TS_SPSYNC0_B, + GPIO_FN_VI1_CLK, GPIO_FN_AVB_RXD4, GPIO_FN_VI1_DATA0, GPIO_FN_AVB_RXD5, + GPIO_FN_VI1_DATA1, GPIO_FN_AVB_RXD6, + GPIO_FN_VI1_DATA2, GPIO_FN_AVB_RXD7, + GPIO_FN_VI1_DATA3, GPIO_FN_AVB_RX_ER, + GPIO_FN_VI1_DATA4, GPIO_FN_AVB_MDIO, + GPIO_FN_VI1_DATA5, GPIO_FN_AVB_RX_DV, + GPIO_FN_VI1_DATA6, GPIO_FN_AVB_MAGIC, + GPIO_FN_VI1_DATA7, GPIO_FN_AVB_MDC, + GPIO_FN_ETH_MDIO, GPIO_FN_AVB_RX_CLK, GPIO_FN_SCL2_C, + GPIO_FN_ETH_CRS_DV, GPIO_FN_AVB_LINK, GPIO_FN_SDA2_C, + + /* IPSR12 */ + GPIO_FN_ETH_RX_ER, GPIO_FN_AVB_CRS, GPIO_FN_SCL3, GPIO_FN_SCL7, + GPIO_FN_ETH_RXD0, GPIO_FN_AVB_PHY_INT, GPIO_FN_SDA3, GPIO_FN_SDA7, + GPIO_FN_ETH_RXD1, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN0_TX_C, + GPIO_FN_SCL2_D, GPIO_FN_MSIOF1_RXD_E, + GPIO_FN_ETH_LINK, GPIO_FN_AVB_TXD0, GPIO_FN_CAN0_RX_C, + GPIO_FN_SDA2_D, GPIO_FN_MSIOF1_SCK_E, + GPIO_FN_ETH_REFCLK, GPIO_FN_AVB_TXD1, GPIO_FN_SCIFA3_RXD_B, + GPIO_FN_CAN1_RX_C, GPIO_FN_MSIOF1_SYNC_E, + GPIO_FN_ETH_TXD1, GPIO_FN_AVB_TXD2, GPIO_FN_SCIFA3_TXD_B, + GPIO_FN_CAN1_TX_C, GPIO_FN_MSIOF1_TXD_E, + GPIO_FN_ETH_TX_EN, GPIO_FN_AVB_TXD3, + GPIO_FN_TCLK1_B, GPIO_FN_CAN_CLK_B, + GPIO_FN_ETH_MAGIC, GPIO_FN_AVB_TXD4, GPIO_FN_IETX_C, + GPIO_FN_ETH_TXD0, GPIO_FN_AVB_TXD5, GPIO_FN_IECLK_C, + GPIO_FN_ETH_MDC, GPIO_FN_AVB_TXD6, GPIO_FN_IERX_C, + GPIO_FN_STP_IVCXO27_0, GPIO_FN_AVB_TXD7, GPIO_FN_SCIFB2_TXD_D, + GPIO_FN_ADIDATA_B, GPIO_FN_MSIOF0_SYNC_C, + GPIO_FN_STP_ISCLK_0, GPIO_FN_AVB_TX_EN, GPIO_FN_SCIFB2_RXD_D, + GPIO_FN_ADICS_SAMP_B, GPIO_FN_MSIOF0_SCK_C, + + /* IPSR13 */ + GPIO_FN_STP_ISD_0, GPIO_FN_AVB_TX_ER, GPIO_FN_SCIFB2_SCK_C, + GPIO_FN_ADICLK_B, GPIO_FN_MSIOF0_SS1_C, + GPIO_FN_STP_ISEN_0, GPIO_FN_AVB_TX_CLK, + GPIO_FN_ADICHS0_B, GPIO_FN_MSIOF0_SS2_C, + GPIO_FN_STP_ISSYNC_0, GPIO_FN_AVB_COL, + GPIO_FN_ADICHS1_B, GPIO_FN_MSIOF0_RXD_C, + GPIO_FN_STP_OPWM_0, GPIO_FN_AVB_GTX_CLK, GPIO_FN_PWM0_B, + GPIO_FN_ADICHS2_B, GPIO_FN_MSIOF0_TXD_C, + GPIO_FN_SD0_CLK, GPIO_FN_SPCLK_B, GPIO_FN_SD0_CMD, GPIO_FN_MOSI_IO0_B, + GPIO_FN_SD0_DATA0, GPIO_FN_MISO_IO1_B, + GPIO_FN_SD0_DATA1, GPIO_FN_IO2_B, + GPIO_FN_SD0_DATA2, GPIO_FN_IO3_B, GPIO_FN_SD0_DATA3, GPIO_FN_SSL_B, + GPIO_FN_SD0_CD, GPIO_FN_MMC_D6_B, + GPIO_FN_SIM0_RST_B, GPIO_FN_CAN0_RX_F, + GPIO_FN_SCIFA5_TXD_B, GPIO_FN_TX3_C, + GPIO_FN_SD0_WP, GPIO_FN_MMC_D7_B, GPIO_FN_SIM0_D_B, GPIO_FN_CAN0_TX_F, + GPIO_FN_SCIFA5_RXD_B, GPIO_FN_RX3_C, + GPIO_FN_SD1_CMD, GPIO_FN_REMOCON_B, + GPIO_FN_SD1_DATA0, GPIO_FN_SPEEDIN_B, + GPIO_FN_SD1_DATA1, GPIO_FN_IETX_B, GPIO_FN_SD1_DATA2, GPIO_FN_IECLK_B, + GPIO_FN_SD1_DATA3, GPIO_FN_IERX_B, + GPIO_FN_SD1_CD, GPIO_FN_PWM0, GPIO_FN_TPU_TO0, GPIO_FN_SCL1_C, + + /* IPSR14 */ + GPIO_FN_SD1_WP, GPIO_FN_PWM1_B, GPIO_FN_SDA1_C, + GPIO_FN_SD2_CLK, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CMD, GPIO_FN_MMC_CMD, + GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D1, + GPIO_FN_SD2_DATA2, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D3, + GPIO_FN_SD2_CD, GPIO_FN_MMC_D4, GPIO_FN_SCL8_C, + GPIO_FN_TX5_B, GPIO_FN_SCIFA5_TXD_C, + GPIO_FN_SD2_WP, GPIO_FN_MMC_D5, GPIO_FN_SDA8_C, + GPIO_FN_RX5_B, GPIO_FN_SCIFA5_RXD_C, + GPIO_FN_MSIOF0_SCK, GPIO_FN_RX2_C, GPIO_FN_ADIDATA, + GPIO_FN_VI1_CLK_C, GPIO_FN_VI1_G0_B, + GPIO_FN_MSIOF0_SYNC, GPIO_FN_TX2_C, GPIO_FN_ADICS_SAMP, + GPIO_FN_VI1_CLKENB_C, GPIO_FN_VI1_G1_B, + GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICLK, + GPIO_FN_VI1_FIELD_C, GPIO_FN_VI1_G2_B, + GPIO_FN_MSIOF0_RXD, GPIO_FN_ADICHS0, + GPIO_FN_VI1_DATA0_C, GPIO_FN_VI1_G3_B, + GPIO_FN_MSIOF0_SS1, GPIO_FN_MMC_D6, GPIO_FN_ADICHS1, GPIO_FN_TX0_E, + GPIO_FN_VI1_HSYNC_N_C, GPIO_FN_SCL7_C, GPIO_FN_VI1_G4_B, + GPIO_FN_MSIOF0_SS2, GPIO_FN_MMC_D7, GPIO_FN_ADICHS2, GPIO_FN_RX0_E, + GPIO_FN_VI1_VSYNC_N_C, GPIO_FN_SDA7_C, GPIO_FN_VI1_G5_B, + + /* IPSR15 */ + GPIO_FN_SIM0_RST, GPIO_FN_IETX, GPIO_FN_CAN1_TX_D, + GPIO_FN_SIM0_CLK, GPIO_FN_IECLK, GPIO_FN_CAN_CLK_C, + GPIO_FN_SIM0_D, GPIO_FN_IERX, GPIO_FN_CAN1_RX_D, + GPIO_FN_GPS_CLK, GPIO_FN_DU1_DOTCLKIN_C, GPIO_FN_AUDIO_CLKB_B, + GPIO_FN_PWM5_B, GPIO_FN_SCIFA3_TXD_C, + GPIO_FN_GPS_SIGN, GPIO_FN_TX4_C, GPIO_FN_SCIFA4_TXD_C, GPIO_FN_PWM5, + GPIO_FN_VI1_G6_B, GPIO_FN_SCIFA3_RXD_C, + GPIO_FN_GPS_MAG, GPIO_FN_RX4_C, GPIO_FN_SCIFA4_RXD_C, GPIO_FN_PWM6, + GPIO_FN_VI1_G7_B, GPIO_FN_SCIFA3_SCK_C, + GPIO_FN_HCTS0_N, GPIO_FN_SCIFB0_CTS_N, GPIO_FN_GLO_I0_C, + GPIO_FN_TCLK1, GPIO_FN_VI1_DATA1_C, + GPIO_FN_HRTS0_N, GPIO_FN_SCIFB0_RTS_N, + GPIO_FN_GLO_I1_C, GPIO_FN_VI1_DATA2_C, + GPIO_FN_HSCK0, GPIO_FN_SCIFB0_SCK, GPIO_FN_GLO_Q0_C, GPIO_FN_CAN_CLK, + GPIO_FN_TCLK2, GPIO_FN_VI1_DATA3_C, + GPIO_FN_HRX0, GPIO_FN_SCIFB0_RXD, GPIO_FN_GLO_Q1_C, + GPIO_FN_CAN0_RX_B, GPIO_FN_VI1_DATA4_C, + GPIO_FN_HTX0, GPIO_FN_SCIFB0_TXD, GPIO_FN_GLO_SCLK_C, + GPIO_FN_CAN0_TX_B, GPIO_FN_VI1_DATA5_C, + + /* IPSR16 */ + GPIO_FN_HRX1, GPIO_FN_SCIFB1_RXD, GPIO_FN_VI1_R0_B, + GPIO_FN_GLO_SDATA_C, GPIO_FN_VI1_DATA6_C, + GPIO_FN_HTX1, GPIO_FN_SCIFB1_TXD, GPIO_FN_VI1_R1_B, + GPIO_FN_GLO_SS_C, GPIO_FN_VI1_DATA7_C, + GPIO_FN_HSCK1, GPIO_FN_SCIFB1_SCK, GPIO_FN_MLB_CK, GPIO_FN_GLO_RFON_C, + GPIO_FN_HCTS1_N, GPIO_FN_SCIFB1_CTS_N, + GPIO_FN_MLB_SIG, GPIO_FN_CAN1_TX_B, + GPIO_FN_HRTS1_N, GPIO_FN_SCIFB1_RTS_N, + GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B, +}; + +#endif /* __ASM_R8A7793_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7793.h b/arch/arm/include/asm/arch-rmobile/r8a7793.h new file mode 100644 index 0000000..1abdeb7 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7793.h @@ -0,0 +1,77 @@ +/* + * arch/arm/include/asm/arch-rmobile/r8a7793.h + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARCH_R8A7793_H +#define __ASM_ARCH_R8A7793_H + +#include "rcar-base.h" + +/* + * R8A7793 I/O Addresses + */ + +/* SH-I2C */ +#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 + +#define DBSC3_1_QOS_R0_BASE 0xE67A1000 +#define DBSC3_1_QOS_R1_BASE 0xE67A1100 +#define DBSC3_1_QOS_R2_BASE 0xE67A1200 +#define DBSC3_1_QOS_R3_BASE 0xE67A1300 +#define DBSC3_1_QOS_R4_BASE 0xE67A1400 +#define DBSC3_1_QOS_R5_BASE 0xE67A1500 +#define DBSC3_1_QOS_R6_BASE 0xE67A1600 +#define DBSC3_1_QOS_R7_BASE 0xE67A1700 +#define DBSC3_1_QOS_R8_BASE 0xE67A1800 +#define DBSC3_1_QOS_R9_BASE 0xE67A1900 +#define DBSC3_1_QOS_R10_BASE 0xE67A1A00 +#define DBSC3_1_QOS_R11_BASE 0xE67A1B00 +#define DBSC3_1_QOS_R12_BASE 0xE67A1C00 +#define DBSC3_1_QOS_R13_BASE 0xE67A1D00 +#define DBSC3_1_QOS_R14_BASE 0xE67A1E00 +#define DBSC3_1_QOS_R15_BASE 0xE67A1F00 +#define DBSC3_1_QOS_W0_BASE 0xE67A2000 +#define DBSC3_1_QOS_W1_BASE 0xE67A2100 +#define DBSC3_1_QOS_W2_BASE 0xE67A2200 +#define DBSC3_1_QOS_W3_BASE 0xE67A2300 +#define DBSC3_1_QOS_W4_BASE 0xE67A2400 +#define DBSC3_1_QOS_W5_BASE 0xE67A2500 +#define DBSC3_1_QOS_W6_BASE 0xE67A2600 +#define DBSC3_1_QOS_W7_BASE 0xE67A2700 +#define DBSC3_1_QOS_W8_BASE 0xE67A2800 +#define DBSC3_1_QOS_W9_BASE 0xE67A2900 +#define DBSC3_1_QOS_W10_BASE 0xE67A2A00 +#define DBSC3_1_QOS_W11_BASE 0xE67A2B00 +#define DBSC3_1_QOS_W12_BASE 0xE67A2C00 +#define DBSC3_1_QOS_W13_BASE 0xE67A2D00 +#define DBSC3_1_QOS_W14_BASE 0xE67A2E00 +#define DBSC3_1_QOS_W15_BASE 0xE67A2F00 + +#define DBSC3_1_DBADJ2 0xE67A00C8 + +/* + * R8A7793 I/O Product Information + */ + +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00640801 +#define MSTP1_BITS 0x9B6C9B5A +#define MSTP2_BITS 0x100D21FC +#define MSTP3_BITS 0xF08CD810 +#define MSTP4_BITS 0x800001C4 +#define MSTP5_BITS 0x44C00046 +#define MSTP7_BITS 0x05BFE618 +#define MSTP8_BITS 0x40C0FE85 +#define MSTP9_BITS 0xFF979FFF +#define MSTP10_BITS 0xFFFEFFE0 +#define MSTP11_BITS 0x000001C0 + +#define R8A7793_CUT_ES2X 2 +#define IS_R8A7793_ES2() \ + (rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X) + +#endif /* __ASM_ARCH_R8A7793_H */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794.h b/arch/arm/include/asm/arch-rmobile/r8a7794.h index 94276dd..d7c9004 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7794.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7794.h @@ -11,4 +11,20 @@ #include "rcar-base.h" +/* SH-I2C */ +#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 + +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00440801 +#define MSTP1_BITS 0x936899DA +#define MSTP2_BITS 0x100D21FC +#define MSTP3_BITS 0xE084D810 +#define MSTP4_BITS 0x800001C4 +#define MSTP5_BITS 0x40C00044 +#define MSTP7_BITS 0x013FE618 +#define MSTP8_BITS 0x40803C05 +#define MSTP9_BITS 0xFB879FEE +#define MSTP10_BITS 0xFFFEFFE0 +#define MSTP11_BITS 0x000001C0 + #endif /* __ASM_ARCH_R8A7794_H */ diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h index 9c1439b..23c4bba 100644 --- a/arch/arm/include/asm/arch-rmobile/rcar-base.h +++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h @@ -10,7 +10,7 @@ #define __ASM_ARCH_RCAR_BASE_H /* - * R-Car (R8A7790/R8A7791/R8A7794) I/O Addresses + * R-Car (R8A7790/R8A7791/R8A7793/R8A7794) I/O Addresses */ #define RWDT_BASE 0xE6020000 #define SWDT_BASE 0xE6030000 @@ -29,6 +29,59 @@ #define SCIF4_BASE 0xE6EE0000 #define SCIF5_BASE 0xE6EE8000 +/* Module stop status register */ +#define MSTPSR0 0xE6150030 +#define MSTPSR1 0xE6150038 +#define MSTPSR2 0xE6150040 +#define MSTPSR3 0xE6150048 +#define MSTPSR4 0xE615004C +#define MSTPSR5 0xE615003C +#define MSTPSR7 0xE61501C4 +#define MSTPSR8 0xE61509A0 +#define MSTPSR9 0xE61509A4 +#define MSTPSR10 0xE61509A8 +#define MSTPSR11 0xE61509AC + +/* Realtime module stop control register */ +#define RMSTPCR0 0xE6150110 +#define RMSTPCR1 0xE6150114 +#define RMSTPCR2 0xE6150118 +#define RMSTPCR3 0xE615011C +#define RMSTPCR4 0xE6150120 +#define RMSTPCR5 0xE6150124 +#define RMSTPCR7 0xE615012C +#define RMSTPCR8 0xE6150980 +#define RMSTPCR9 0xE6150984 +#define RMSTPCR10 0xE6150988 +#define RMSTPCR11 0xE615098C + +/* System module stop control register */ +#define SMSTPCR0 0xE6150130 +#define SMSTPCR1 0xE6150134 +#define SMSTPCR2 0xE6150138 +#define SMSTPCR3 0xE615013C +#define SMSTPCR4 0xE6150140 +#define SMSTPCR5 0xE6150144 +#define SMSTPCR7 0xE615014C +#define SMSTPCR8 0xE6150990 +#define SMSTPCR9 0xE6150994 +#define SMSTPCR10 0xE6150998 +#define SMSTPCR11 0xE615099C + +/* + * SH-I2C + * Ch2 and ch3 are different address. These are defined + * in the header of each SoCs. + */ +#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 +#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 + +/* RCAR-I2C */ +#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 +#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 +#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000 +#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000 + #define S3C_BASE 0xE6784000 #define S3C_INT_BASE 0xE6784A00 #define S3C_MEDIA_BASE 0xE6784B00 diff --git a/arch/arm/include/asm/arch-rmobile/rcar-mstp.h b/arch/arm/include/asm/arch-rmobile/rcar-mstp.h new file mode 100644 index 0000000..9a564f8 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/rcar-mstp.h @@ -0,0 +1,109 @@ +/* + * arch/arm/include/asm/arch-rmobile/rcar-mstp.h + * + * Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * Copyright (C) 2013, 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARCH_RCAR_MSTP_H +#define __ASM_ARCH_RCAR_MSTP_H + +#define mstp_setbits(type, addr, saddr, set) \ + out_##type((saddr), in_##type(addr) | (set)) +#define mstp_clrbits(type, addr, saddr, clear) \ + out_##type((saddr), in_##type(addr) & ~(clear)) +#define mstp_setclrbits(type, addr, set, clear) \ + out_##type((addr), (in_##type(addr) | (set)) & ~(clear)) +#define mstp_setbits_le32(addr, saddr, set) \ + mstp_setbits(le32, addr, saddr, set) +#define mstp_clrbits_le32(addr, saddr, clear) \ + mstp_clrbits(le32, addr, saddr, clear) +#define mstp_setclrbits_le32(addr, set, clear) \ + mstp_setclrbits(le32, addr, set, clear) + +#ifndef CONFIG_SMSTP0_ENA +#define CONFIG_SMSTP0_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP1_ENA +#define CONFIG_SMSTP1_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP2_ENA +#define CONFIG_SMSTP2_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP3_ENA +#define CONFIG_SMSTP3_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP4_ENA +#define CONFIG_SMSTP4_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP5_ENA +#define CONFIG_SMSTP5_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP6_ENA +#define CONFIG_SMSTP6_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP7_ENA +#define CONFIG_SMSTP7_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP8_ENA +#define CONFIG_SMSTP8_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP9_ENA +#define CONFIG_SMSTP9_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP10_ENA +#define CONFIG_SMSTP10_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP11_ENA +#define CONFIG_SMSTP11_ENA 0x00 +#endif + +#ifndef CONFIG_RMSTP0_ENA +#define CONFIG_RMSTP0_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP1_ENA +#define CONFIG_RMSTP1_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP2_ENA +#define CONFIG_RMSTP2_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP3_ENA +#define CONFIG_RMSTP3_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP4_ENA +#define CONFIG_RMSTP4_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP5_ENA +#define CONFIG_RMSTP5_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP6_ENA +#define CONFIG_RMSTP6_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP7_ENA +#define CONFIG_RMSTP7_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP8_ENA +#define CONFIG_RMSTP8_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP9_ENA +#define CONFIG_RMSTP9_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP10_ENA +#define CONFIG_RMSTP10_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP11_ENA +#define CONFIG_RMSTP11_ENA 0x00 +#endif + +struct mstp_ctl { + u32 s_addr; + u32 s_dis; + u32 s_ena; + u32 r_addr; + u32 r_dis; + u32 r_ena; +}; + +#endif /* __ASM_ARCH_RCAR_MSTP_H */ diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h index 2cc38e1..65ee9eb 100644 --- a/arch/arm/include/asm/arch-rmobile/rmobile.h +++ b/arch/arm/include/asm/arch-rmobile/rmobile.h @@ -10,6 +10,8 @@ #include <asm/arch/r8a7790.h> #elif defined(CONFIG_R8A7791) #include <asm/arch/r8a7791.h> +#elif defined(CONFIG_R8A7793) +#include <asm/arch/r8a7793.h> #elif defined(CONFIG_R8A7794) #include <asm/arch/r8a7794.h> #else diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h index ce4186f..8773ce3 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h @@ -83,9 +83,9 @@ static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; } -static inline struct s3c2410_nand *s3c2410_get_base_nand(void) +static inline struct s3c24x0_nand *s3c24x0_get_base_nand(void) { - return (struct s3c2410_nand *)S3C2410_NAND_BASE; + return (struct s3c24x0_nand *)S3C2410_NAND_BASE; } static inline struct s3c24x0_uart diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h index 3f44bdc..7a525f2 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h @@ -81,9 +81,9 @@ static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; } -static inline struct s3c2440_nand *s3c2440_get_base_nand(void) +static inline struct s3c24x0_nand *s3c24x0_get_base_nand(void) { - return (struct s3c2440_nand *)S3C2440_NAND_BASE; + return (struct s3c24x0_nand *)S3C2440_NAND_BASE; } static inline struct s3c24x0_uart diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h index ed9df34..2dae9fc 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h @@ -135,34 +135,33 @@ struct s3c24x0_lcd { }; -#ifdef CONFIG_S3C2410 -/* NAND FLASH (see S3C2410 manual chapter 6) */ -struct s3c2410_nand { - u32 nfconf; - u32 nfcmd; - u32 nfaddr; - u32 nfdata; - u32 nfstat; - u32 nfecc; -}; -#endif -#ifdef CONFIG_S3C2440 -/* NAND FLASH (see S3C2440 manual chapter 6) */ -struct s3c2440_nand { +/* NAND FLASH (see manual chapter 6) */ +struct s3c24x0_nand { u32 nfconf; +#ifndef CONFIG_S3C2410 u32 nfcont; +#endif u32 nfcmd; u32 nfaddr; u32 nfdata; +#ifndef CONFIG_S3C2410 u32 nfeccd0; u32 nfeccd1; u32 nfeccd; +#endif u32 nfstat; +#ifdef CONFIG_S3C2410 + u32 nfecc; +#else u32 nfstat0; u32 nfstat1; -}; + u32 nfmecc0; + u32 nfmecc1; + u32 nfsecc; + u32 nfsblk; + u32 nfeblk; #endif - +}; /* UART (see manual chapter 11) */ struct s3c24x0_uart { diff --git a/arch/arm/include/asm/arch-stv0991/gpio.h b/arch/arm/include/asm/arch-stv0991/gpio.h new file mode 100644 index 0000000..9131ded --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/gpio.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_STV0991_GPIO_H +#define __ASM_ARCH_STV0991_GPIO_H + +enum gpio_direction { + GPIO_DIRECTION_IN, + GPIO_DIRECTION_OUT, +}; + +struct gpio_regs { + u32 data; /* offset 0x0 */ + u32 reserved[0xff]; /* 0x4--0x3fc */ + u32 dir; /* offset 0x400 */ +}; + +#endif /* __ASM_ARCH_STV0991_GPIO_H */ diff --git a/arch/arm/include/asm/arch-stv0991/hardware.h b/arch/arm/include/asm/arch-stv0991/hardware.h new file mode 100644 index 0000000..3f6bcaf --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/hardware.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +/* STV0991 */ +#define SRAM0_BASE_ADDR 0x00000000UL +#define SRAM1_BASE_ADDR 0x00068000UL +#define SRAM2_BASE_ADDR 0x000D0000UL +#define SRAM3_BASE_ADDR 0x00138000UL +#define CFS_SRAM0_BASE_ADDR 0x00198000UL +#define CFS_SRAM1_BASE_ADDR 0x001B8000UL +#define FAST_SRAM_BASE_ADDR 0x001D8000UL +#define FLASH_BASE_ADDR 0x40000000UL +#define PL310_BASE_ADDR 0x70000000UL +#define HSAXIM_BASE_ADDR 0x70100000UL +#define IMGSS_BASE_ADDR 0x70200000UL +#define ADC_BASE_ADDR 0x80000000UL +#define GPIOA_BASE_ADDR 0x80001000UL +#define GPIOB_BASE_ADDR 0x80002000UL +#define GPIOC_BASE_ADDR 0x80003000UL +#define HDM_BASE_ADDR 0x80004000UL +#define THSENS_BASE_ADDR 0x80200000UL +#define GPTIMER2_BASE_ADDR 0x80201000UL +#define GPTIMER1_BASE_ADDR 0x80202000UL +#define QSPI_BASE_ADDR 0x80203000UL +#define CGU_BASE_ADDR 0x80204000UL +#define CREG_BASE_ADDR 0x80205000UL +#define PEC_BASE_ADDR 0x80206000UL +#define WDRU_BASE_ADDR 0x80207000UL +#define BSEC_BASE_ADDR 0x80208000UL +#define DAP_ROM_BASE_ADDR 0x80210000UL +#define SOC_CTI_BASE_ADDR 0x80211000UL +#define TPIU_BASE_ADDR 0x80212000UL +#define TMC_ETF_BASE_ADDR 0x80213000UL +#define R4_ETM_BASE_ADDR 0x80214000UL +#define R4_CTI_BASE_ADDR 0x80215000UL +#define R4_DBG_BASE_ADDR 0x80216000UL +#define GMAC_BASE_ADDR 0x80300000UL +#define RNSS_BASE_ADDR 0x80302000UL +#define CRYP_BASE_ADDR 0x80303000UL +#define HASH_BASE_ADDR 0x80304000UL +#define GPDMA_BASE_ADDR 0x80305000UL +#define ISA_BASE_ADDR 0x8032A000UL +#define HCI_BASE_ADDR 0x80400000UL +#define I2C1_BASE_ADDR 0x80401000UL +#define I2C2_BASE_ADDR 0x80402000UL +#define SAI_BASE_ADDR 0x80403000UL +#define USI_BASE_ADDR 0x80404000UL +#define SPI1_BASE_ADDR 0x80405000UL +#define UART_BASE_ADDR 0x80406000UL +#define SPI2_BASE_ADDR 0x80500000UL +#define CAN_BASE_ADDR 0x80501000UL +#define USART1_BASE_ADDR 0x80502000UL +#define USART2_BASE_ADDR 0x80503000UL +#define USART3_BASE_ADDR 0x80504000UL +#define USART4_BASE_ADDR 0x80505000UL +#define USART5_BASE_ADDR 0x80506000UL +#define USART6_BASE_ADDR 0x80507000UL +#define SDI2_BASE_ADDR 0x80600000UL +#define SDI1_BASE_ADDR 0x80601000UL +#define VICA_BASE_ADDR 0x81000000UL +#define VICB_BASE_ADDR 0x81001000UL +#define STM_CHANNELS_BASE_ADDR 0x81100000UL +#define STM_BASE_ADDR 0x81110000UL +#define SROM_BASE_ADDR 0xFFFF0000UL + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h new file mode 100644 index 0000000..ddcbb57 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STV0991_CGU_H +#define _STV0991_CGU_H + +struct stv0991_cgu_regs { + u32 cpu_freq; /* offset 0x0 */ + u32 icn2_freq; /* offset 0x4 */ + u32 dma_freq; /* offset 0x8 */ + u32 isp_freq; /* offset 0xc */ + u32 h264_freq; /* offset 0x10 */ + u32 osif_freq; /* offset 0x14 */ + u32 ren_freq; /* offset 0x18 */ + u32 tim_freq; /* offset 0x1c */ + u32 sai_freq; /* offset 0x20 */ + u32 eth_freq; /* offset 0x24 */ + u32 i2c_freq; /* offset 0x28 */ + u32 spi_freq; /* offset 0x2c */ + u32 uart_freq; /* offset 0x30 */ + u32 qspi_freq; /* offset 0x34 */ + u32 sdio_freq; /* offset 0x38 */ + u32 usi_freq; /* offset 0x3c */ + u32 can_line_freq; /* offset 0x40 */ + u32 debug_freq; /* offset 0x44 */ + u32 trace_freq; /* offset 0x48 */ + u32 stm_freq; /* offset 0x4c */ + u32 eth_ctrl; /* offset 0x50 */ + u32 reserved[3]; /* offset 0x54 */ + u32 osc_ctrl; /* offset 0x60 */ + u32 pll1_ctrl; /* offset 0x64 */ + u32 pll1_freq; /* offset 0x68 */ + u32 pll1_fract; /* offset 0x6c */ + u32 pll1_spread; /* offset 0x70 */ + u32 pll1_status; /* offset 0x74 */ + u32 pll2_ctrl; /* offset 0x78 */ + u32 pll2_freq; /* offset 0x7c */ + u32 pll2_fract; /* offset 0x80 */ + u32 pll2_spread; /* offset 0x84 */ + u32 pll2_status; /* offset 0x88 */ + u32 cgu_enable_1; /* offset 0x8c */ + u32 cgu_enable_2; /* offset 0x90 */ + u32 cgu_isp_pulse; /* offset 0x94 */ + u32 cgu_h264_pulse; /* offset 0x98 */ + u32 cgu_osif_pulse; /* offset 0x9c */ + u32 cgu_ren_pulse; /* offset 0xa0 */ + +}; + +/* CGU Timer */ +#define CLK_TMR_OSC 0 +#define CLK_TMR_MCLK 1 +#define CLK_TMR_PLL1 2 +#define CLK_TMR_PLL2 3 +#define MDIV_SHIFT_TMR 3 +#define DIV_SHIFT_TMR 6 + +#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \ + | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK) + +/* Clock Enable/Disable */ + +#define TIMER1_CLK_EN (1 << 15) + +/* CGU Uart config */ +#define CLK_UART_MCLK 0 +#define CLK_UART_PLL1 1 +#define CLK_UART_PLL2 2 + +#define MDIV_SHIFT_UART 3 +#define DIV_SHIFT_UART 6 + +#define UART_CLK_CFG (4 << DIV_SHIFT_UART \ + | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK) + +/* CGU Ethernet clock config */ +#define CLK_ETH_MCLK 0 +#define CLK_ETH_PLL1 1 +#define CLK_ETH_PLL2 2 + +#define MDIV_SHIFT_ETH 3 +#define DIV_SHIFT_ETH 6 +#define DIV_ETH_125 9 +#define DIV_ETH_50 12 +#define DIV_ETH_P2P 15 + +#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \ + | 1 << DIV_ETH_125 \ + | 0 << DIV_SHIFT_ETH \ + | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1) + /* CGU Ethernet control */ + +#define ETH_CLK_TX_EXT_PHY 0 +#define ETH_CLK_TX_125M 1 +#define ETH_CLK_TX_25M 2 +#define ETH_CLK_TX_2M5 3 +#define ETH_CLK_TX_DIS 7 + +#define ETH_CLK_RX_EXT_PHY 0 +#define ETH_CLK_RX_25M 1 +#define ETH_CLK_RX_2M5 2 +#define ETH_CLK_RX_DIS 3 +#define RX_CLK_SHIFT 3 +#define ETH_CLK_MASK ~(0x1F) + +#define ETH_PHY_MODE_GMII 0 +#define ETH_PHY_MODE_RMII 1 +#define ETH_PHY_CLK_DIS 1 + +#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \ + | ETH_CLK_TX_EXT_PHY) +#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h new file mode 100644 index 0000000..c804eb5 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STV0991_CREG_H +#define _STV0991_CREG_H + +struct stv0991_creg { + u32 version; /* offset 0x0 */ + u32 hdpctl; /* offset 0x4 */ + u32 hdpval; /* offset 0x8 */ + u32 hdpgposet; /* offset 0xc */ + u32 hdpgpoclr; /* offset 0x10 */ + u32 hdpgpoval; /* offset 0x14 */ + u32 stm_mux; /* offset 0x18 */ + u32 sysctrl_1; /* offset 0x1c */ + u32 sysctrl_2; /* offset 0x20 */ + u32 sysctrl_3; /* offset 0x24 */ + u32 sysctrl_4; /* offset 0x28 */ + u32 reserved_1[0x35]; /* offset 0x2C-0xFC */ + u32 mux1; /* offset 0x100 */ + u32 mux2; /* offset 0x104 */ + u32 mux3; /* offset 0x108 */ + u32 mux4; /* offset 0x10c */ + u32 mux5; /* offset 0x110 */ + u32 mux6; /* offset 0x114 */ + u32 mux7; /* offset 0x118 */ + u32 mux8; /* offset 0x11c */ + u32 mux9; /* offset 0x120 */ + u32 mux10; /* offset 0x124 */ + u32 mux11; /* offset 0x128 */ + u32 mux12; /* offset 0x12c */ + u32 mux13; /* offset 0x130 */ + u32 reserved_2[0x33]; /* offset 0x134-0x1FC */ + u32 cfg_pad1; /* offset 0x200 */ + u32 cfg_pad2; /* offset 0x204 */ + u32 cfg_pad3; /* offset 0x208 */ + u32 cfg_pad4; /* offset 0x20c */ + u32 cfg_pad5; /* offset 0x210 */ + u32 cfg_pad6; /* offset 0x214 */ + u32 cfg_pad7; /* offset 0x218 */ + u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */ + u32 vdd_pad1; /* offset 0x300 */ + u32 vdd_pad2; /* offset 0x304 */ + u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */ + u32 vdd_comp1; /* offset 0x400 */ +}; + +/* CREG MUX 12 register */ +#define GPIOC_30_MUX_SHIFT 24 +#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT) +#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT) + +#define GPIOC_31_MUX_SHIFT 28 +#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT) +#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT) + +/* CREG MUX 7 register */ +#define GPIOB_16_MUX_SHIFT 0 +#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT) +#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT) + +#define GPIOB_17_MUX_SHIFT 4 +#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT) +#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT) + +/* CREG CFG_PAD6 register */ + +#define GPIOC_31_MODE_SHIFT 30 +#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT) +#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT) +#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT) + +#define GPIOC_30_MODE_SHIFT 28 +#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT) +#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT) +#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT) + +/* CREG Ethernet pad config */ + +#define VDD_ETH_PS_1V8 0 +#define VDD_ETH_PS_2V5 2 +#define VDD_ETH_PS_3V3 3 +#define VDD_ETH_PS_MASK 0x3 + +#define VDD_ETH_PS_SHIFT 12 +#define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT) + +#define VDD_ETH_M_PS_SHIFT 28 +#define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT) + +#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h new file mode 100644 index 0000000..1151378 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STV0991_DEFS_H__ +#define __STV0991_DEFS_H__ +#include <asm/arch/stv0991_periph.h> + +extern int stv0991_pinmux_config(enum periph_id); +extern int clock_setup(enum periph_clock); + +#endif + diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h new file mode 100644 index 0000000..abd7257 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STV0991_GPT_H +#define _STV0991_GPT_H + +#include <asm/arch-stv0991/hardware.h> + +struct gpt_regs { + u32 cr1; + u32 cr2; + u32 reserved_1; + u32 dier; /* dma_int_en */ + u32 sr; /* status reg */ + u32 egr; /* event gen */ + u32 reserved_2[3]; /* offset 0x18--0x20*/ + u32 cnt; + u32 psc; + u32 arr; +}; + +struct gpt_regs *const gpt1_regs_ptr = + (struct gpt_regs *) GPTIMER1_BASE_ADDR; + +/* Timer control1 register */ +#define GPT_CR1_CEN 0x0001 +#define GPT_MODE_AUTO_RELOAD (1 << 7) + +/* Timer prescalar reg */ +#define GPT_PRESCALER_128 0x128 + +/* Auto reload register for free running config */ +#define GPT_FREE_RUNNING 0xFFFF + +/* Timer, HZ specific defines */ +#define CONFIG_STV0991_HZ 1000 +#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128 + +#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h new file mode 100644 index 0000000..f728c83 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals required for pinmux configuration. List will + * grow with support for more devices getting added. + * Numbering based on interrupt table. + * + */ +enum periph_id { + UART_GPIOC_30_31 = 0, + UART_GPIOB_16_17, + ETH_GPIOB_10_31_C_0_4, + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, + PERIPH_ID_SPI0, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SDMMC0, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_SDMMC3, + PERIPH_ID_I2S1, +}; + +enum periph_clock { + UART_CLOCK_CFG = 0, + ETH_CLOCK_CFG, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h new file mode 100644 index 0000000..7e555a2 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STV0991_WD_RST_H +#define _STV0991_WD_RST_H +#include <asm/arch-stv0991/hardware.h> + +struct stv0991_wd_ru { + u32 wdru_config; + u32 wdru_ctrl1; + u32 wdru_ctrl2; + u32 wdru_tim; + u32 wdru_count; + u32 wdru_stat; + u32 wdru_wrlock; +}; + +struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \ + (struct stv0991_wd_ru *)WDRU_BASE_ADDR; + +/* Watchdog control register */ +#define WDRU_RST_SYS 0x1 + +#endif diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index b40c16b..64acff3 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -25,9 +25,11 @@ int clock_init(void); int clock_twi_onoff(int port, int state); void clock_set_pll1(unsigned int hz); +void clock_set_pll3(unsigned int hz); void clock_set_pll5(unsigned int hz); unsigned int clock_get_pll5p(void); unsigned int clock_get_pll6(void); +void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz); void clock_init_safe(void); void clock_init_uart(void); #endif diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 9dca800..eb88969 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -62,7 +62,7 @@ struct sunxi_ccm_reg { u32 gps_clk_cfg; /* 0xd0 */ u32 spi3_clk_cfg; /* 0xd4 */ u8 res5[0x28]; - u32 dram_clk_cfg; /* 0x100 */ + u32 dram_clk_gate; /* 0x100 */ u32 be0_clk_cfg; /* 0x104 */ u32 be1_clk_cfg; /* 0x108 */ u32 fe0_clk_cfg; /* 0x10c */ @@ -186,12 +186,20 @@ struct sunxi_ccm_reg { /* ahb clock gate bit offset (second register) */ #define AHB_GATE_OFFSET_GMAC 17 +#define AHB_GATE_OFFSET_DE_BE0 12 +#define AHB_GATE_OFFSET_HDMI 11 +#define AHB_GATE_OFFSET_LCD1 5 +#define AHB_GATE_OFFSET_LCD0 4 #define CCM_AHB_GATE_GPS (0x1 << 26) #define CCM_AHB_GATE_SDRAM (0x1 << 14) #define CCM_AHB_GATE_DLL (0x1 << 15) #define CCM_AHB_GATE_ACE (0x1 << 16) +#define CCM_PLL3_CTRL_M(n) (((n) & 0x7f) << 0) +#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 15) +#define CCM_PLL3_CTRL_EN (0x1 << 31) + #define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0) #define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3) #define CCM_PLL5_CTRL_M_X(n) ((n) - 1) @@ -253,6 +261,34 @@ struct sunxi_ccm_reg { #define CCM_MMC_CTRL_ENABLE (0x1 << 31) +#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 + +#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24) +#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) +#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) +#define CCM_LCD_CH0_CTRL_RST (0x1 << 30) +#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31) + +#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +/* We leave bit 11 set to 0, so sclk1 == sclk2 */ +#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24) +#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24) +#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24) +/* Enable / disable both ch1 sclk1 and sclk2 at the same time */ +#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31 | 0x1 << 15) + +#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_HDMI_CTRL_PLL_MASK (3 << 24) +#define CCM_HDMI_CTRL_PLL3 (0 << 24) +#define CCM_HDMI_CTRL_PLL7 (1 << 24) +#define CCM_HDMI_CTRL_PLL3_2X (2 << 24) +#define CCM_HDMI_CTRL_PLL7_2X (3 << 24) +/* No separate ddc gate on sun4i, sun5i and sun7i */ +#define CCM_HDMI_CTRL_DDC_GATE 0 +#define CCM_HDMI_CTRL_GATE (0x1 << 31) + #define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 #define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 #define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 @@ -266,4 +302,13 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY1_CLK 0 #define CCM_USB_CTRL_PHY2_CLK 0 +/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */ +#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_DE_CTRL_PLL_MASK (3 << 24) +#define CCM_DE_CTRL_PLL3 (0 << 24) +#define CCM_DE_CTRL_PLL7 (1 << 24) +#define CCM_DE_CTRL_PLL5P (2 << 24) +#define CCM_DE_CTRL_RST (1 << 30) +#define CCM_DE_CTRL_GATE (1 << 31) + #endif /* _SUNXI_CLOCK_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index e16a764..3599054 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -176,13 +176,18 @@ struct sunxi_ccm_reg { #define CCM_PLL1_CTRL_MAGIC (0x1 << 16) #define CCM_PLL1_CTRL_EN (0x1 << 31) +#define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8) +#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24) +#define CCM_PLL3_CTRL_EN (0x1 << 31) + #define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0) #define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4) #define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) #define CCM_PLL5_CTRL_UPD (0x1 << 20) #define CCM_PLL5_CTRL_EN (0x1 << 31) -#define PLL6_CFG_DEFAULT 0x90041811 +#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */ #define CCM_PLL6_CTRL_N_SHIFT 8 #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) @@ -193,17 +198,26 @@ struct sunxi_ccm_reg { #define AXI_GATE_OFFSET_DRAM 0 +/* ahb_gate0 offsets */ #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 #define AHB_GATE_OFFSET_MCTL 14 +#define AHB_GATE_OFFSET_GMAC 17 #define AHB_GATE_OFFSET_MMC3 11 #define AHB_GATE_OFFSET_MMC2 10 #define AHB_GATE_OFFSET_MMC1 9 #define AHB_GATE_OFFSET_MMC0 8 #define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) +/* ahb_gate1 offsets */ +#define AHB_GATE_OFFSET_DRC0 25 +#define AHB_GATE_OFFSET_DE_BE0 12 +#define AHB_GATE_OFFSET_HDMI 11 +#define AHB_GATE_OFFSET_LCD1 5 +#define AHB_GATE_OFFSET_LCD0 4 + #define CCM_MMC_CTRL_OSCM24 (0x0 << 24) #define CCM_MMC_CTRL_PLL6 (0x1 << 24) @@ -216,6 +230,12 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) + #define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */ #define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) @@ -223,8 +243,35 @@ struct sunxi_ccm_reg { #define CCM_DRAMCLK_CFG_UPD (0x1 << 16) #define CCM_DRAMCLK_CFG_RST (0x1 << 31) +#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 + +#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24) +#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) +#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) +#define CCM_LCD_CH0_CTRL_MIPI_PLL (4 << 24) +#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31) + +#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24) +#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24) +#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24) +#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31) + +#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_HDMI_CTRL_PLL_MASK (3 << 24) +#define CCM_HDMI_CTRL_PLL3 (0 << 24) +#define CCM_HDMI_CTRL_PLL7 (1 << 24) +#define CCM_HDMI_CTRL_PLL3_2X (2 << 24) +#define CCM_HDMI_CTRL_PLL7_2X (3 << 24) +#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30) +#define CCM_HDMI_CTRL_GATE (0x1 << 31) + #define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */ +/* ahb_reset0 offsets */ +#define AHB_RESET_OFFSET_GMAC 17 #define AHB_RESET_OFFSET_MCTL 14 #define AHB_RESET_OFFSET_MMC3 11 #define AHB_RESET_OFFSET_MMC2 10 @@ -232,10 +279,28 @@ struct sunxi_ccm_reg { #define AHB_RESET_OFFSET_MMC0 8 #define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n)) +/* ahb_reset0 offsets */ +#define AHB_RESET_OFFSET_DRC0 25 +#define AHB_RESET_OFFSET_DE_BE0 12 +#define AHB_RESET_OFFSET_HDMI 11 +#define AHB_RESET_OFFSET_LCD1 5 +#define AHB_RESET_OFFSET_LCD0 4 + /* apb2 reset */ #define APB2_RESET_UART_SHIFT (16) #define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) #define APB2_RESET_TWI_SHIFT (0) #define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) +/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */ +#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_DE_CTRL_PLL_MASK (0xf << 24) +#define CCM_DE_CTRL_PLL3 (0 << 24) +#define CCM_DE_CTRL_PLL7 (1 << 24) +#define CCM_DE_CTRL_PLL6_2X (2 << 24) +#define CCM_DE_CTRL_PLL8 (3 << 24) +#define CCM_DE_CTRL_PLL9 (4 << 24) +#define CCM_DE_CTRL_PLL10 (5 << 24) +#define CCM_DE_CTRL_GATE (1 << 31) + #endif /* _SUNXI_CLOCK_SUN6I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index bdee89e..2c92b5c 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -99,9 +99,13 @@ #define SUNXI_SCR_BASE 0x01c2c400 +#ifndef CONFIG_MACH_SUN6I #define SUNXI_GPS_BASE 0x01c30000 #define SUNXI_MALI400_BASE 0x01c40000 #define SUNXI_GMAC_BASE 0x01c50000 +#else +#define SUNXI_GMAC_BASE 0x01c30000 +#endif #define SUNXI_DRAM_COM_BASE 0x01c62000 #define SUNXI_DRAM_CTL0_BASE 0x01c63000 diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h new file mode 100644 index 0000000..ddb71c1 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/display.h @@ -0,0 +1,187 @@ +/* + * Sunxi platform display controller register and constant defines + * + * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DISPLAY_H +#define _SUNXI_DISPLAY_H + +struct sunxi_de_be_reg { + u8 res0[0x800]; /* 0x000 */ + u32 mode; /* 0x800 */ + u32 backcolor; /* 0x804 */ + u32 disp_size; /* 0x808 */ + u8 res1[0x4]; /* 0x80c */ + u32 layer0_size; /* 0x810 */ + u32 layer1_size; /* 0x814 */ + u32 layer2_size; /* 0x818 */ + u32 layer3_size; /* 0x81c */ + u32 layer0_pos; /* 0x820 */ + u32 layer1_pos; /* 0x824 */ + u32 layer2_pos; /* 0x828 */ + u32 layer3_pos; /* 0x82c */ + u8 res2[0x10]; /* 0x830 */ + u32 layer0_stride; /* 0x840 */ + u32 layer1_stride; /* 0x844 */ + u32 layer2_stride; /* 0x848 */ + u32 layer3_stride; /* 0x84c */ + u32 layer0_addr_low32b; /* 0x850 */ + u32 layer1_addr_low32b; /* 0x854 */ + u32 layer2_addr_low32b; /* 0x858 */ + u32 layer3_addr_low32b; /* 0x85c */ + u32 layer0_addr_high4b; /* 0x860 */ + u32 layer1_addr_high4b; /* 0x864 */ + u32 layer2_addr_high4b; /* 0x868 */ + u32 layer3_addr_high4b; /* 0x86c */ + u32 reg_ctrl; /* 0x870 */ + u8 res3[0xc]; /* 0x874 */ + u32 color_key_max; /* 0x880 */ + u32 color_key_min; /* 0x884 */ + u32 color_key_config; /* 0x888 */ + u8 res4[0x4]; /* 0x88c */ + u32 layer0_attr0_ctrl; /* 0x890 */ + u32 layer1_attr0_ctrl; /* 0x894 */ + u32 layer2_attr0_ctrl; /* 0x898 */ + u32 layer3_attr0_ctrl; /* 0x89c */ + u32 layer0_attr1_ctrl; /* 0x8a0 */ + u32 layer1_attr1_ctrl; /* 0x8a4 */ + u32 layer2_attr1_ctrl; /* 0x8a8 */ + u32 layer3_attr1_ctrl; /* 0x8ac */ +}; + +struct sunxi_lcdc_reg { + u32 ctrl; /* 0x00 */ + u32 int0; /* 0x04 */ + u32 int1; /* 0x08 */ + u8 res0[0x04]; /* 0x0c */ + u32 frame_ctrl; /* 0x10 */ + u8 res1[0x2c]; /* 0x14 */ + u32 tcon0_ctrl; /* 0x40 */ + u32 tcon0_dclk; /* 0x44 */ + u32 tcon0_basic_timing0; /* 0x48 */ + u32 tcon0_basic_timing1; /* 0x4c */ + u32 tcon0_basic_timing2; /* 0x50 */ + u32 tcon0_basic_timing3; /* 0x54 */ + u32 tcon0_hv_intf; /* 0x58 */ + u8 res2[0x04]; /* 0x5c */ + u32 tcon0_cpu_intf; /* 0x60 */ + u32 tcon0_cpu_wr_dat; /* 0x64 */ + u32 tcon0_cpu_rd_dat0; /* 0x68 */ + u32 tcon0_cpu_rd_dat1; /* 0x6c */ + u32 tcon0_ttl_timing0; /* 0x70 */ + u32 tcon0_ttl_timing1; /* 0x74 */ + u32 tcon0_ttl_timing2; /* 0x78 */ + u32 tcon0_ttl_timing3; /* 0x7c */ + u32 tcon0_ttl_timing4; /* 0x80 */ + u32 tcon0_lvds_intf; /* 0x84 */ + u32 tcon0_io_polarity; /* 0x88 */ + u32 tcon0_io_tristate; /* 0x8c */ + u32 tcon1_ctrl; /* 0x90 */ + u32 tcon1_timing_source; /* 0x94 */ + u32 tcon1_timing_scale; /* 0x98 */ + u32 tcon1_timing_out; /* 0x9c */ + u32 tcon1_timing_h; /* 0xa0 */ + u32 tcon1_timing_v; /* 0xa4 */ + u32 tcon1_timing_sync; /* 0xa8 */ + u8 res3[0x44]; /* 0xac */ + u32 tcon1_io_polarity; /* 0xf0 */ + u32 tcon1_io_tristate; /* 0xf4 */ +}; + +struct sunxi_hdmi_reg { + u32 version_id; /* 0x000 */ + u32 ctrl; /* 0x004 */ + u32 irq; /* 0x008 */ + u32 hpd; /* 0x00c */ + u32 video_ctrl; /* 0x010 */ + u32 video_size; /* 0x014 */ + u32 video_bp; /* 0x018 */ + u32 video_fp; /* 0x01c */ + u32 video_spw; /* 0x020 */ + u32 video_polarity; /* 0x024 */ + u8 res0[0x1d8]; /* 0x028 */ + u32 pad_ctrl0; /* 0x200 */ + u32 pad_ctrl1; /* 0x204 */ + u32 pll_ctrl; /* 0x208 */ + u32 pll_dbg0; /* 0x20c */ +}; + +/* + * DE-BE register constants. + */ +#define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0) +#define SUNXI_DE_BE_HEIGHT(y) (((y) - 1) << 16) +#define SUNXI_DE_BE_MODE_ENABLE (1 << 0) +#define SUNXI_DE_BE_MODE_START (1 << 1) +#define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8) +#define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5) +#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0) +#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8) + +/* + * LCDC register constants. + */ +#define SUNXI_LCDC_X(x) (((x) - 1) << 16) +#define SUNXI_LCDC_Y(y) (((y) - 1) << 0) +#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0) +#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0) +#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0) +#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31) +#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28) +#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) +#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31) +#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) +#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) +#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) +#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) (((n) * 2) << 16) + +/* + * HDMI register constants. + */ +#define SUNXI_HDMI_X(x) (((x) - 1) << 0) +#define SUNXI_HDMI_Y(y) (((y) - 1) << 16) +#define SUNXI_HDMI_CTRL_ENABLE (1 << 31) +#define SUNXI_HDMI_IRQ_STATUS_FIFO_UF (1 << 0) +#define SUNXI_HDMI_IRQ_STATUS_FIFO_OF (1 << 1) +#define SUNXI_HDMI_IRQ_STATUS_BITS 0x73 +#define SUNXI_HDMI_HPD_DETECT (1 << 0) +#define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31) +#define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0) +#define SUNXI_HDMI_VIDEO_POL_VER (1 << 1) +#define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16) + +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_HDMI_PAD_CTRL0_HDP 0x7e80000f +#define SUNXI_HDMI_PAD_CTRL0_RUN 0x7e8000ff +#else +#define SUNXI_HDMI_PAD_CTRL0_HDP 0xfe800000 +#define SUNXI_HDMI_PAD_CTRL0_RUN 0xfe800000 +#endif + +#ifdef CONFIG_MACH_SUN4I +#define SUNXI_HDMI_PAD_CTRL1 0x00d8c820 +#elif defined CONFIG_MACH_SUN6I +#define SUNXI_HDMI_PAD_CTRL1 0x01ded030 +#else +#define SUNXI_HDMI_PAD_CTRL1 0x00d8c830 +#endif +#define SUNXI_HDMI_PAD_CTRL1_HALVE (1 << 6) + +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_HDMI_PLL_CTRL 0xba48a308 +#define SUNXI_HDMI_PLL_CTRL_DIV(n) (((n) - 1) << 4) +#else +#define SUNXI_HDMI_PLL_CTRL 0xfa4ef708 +#define SUNXI_HDMI_PLL_CTRL_DIV(n) ((n) << 4) +#endif +#define SUNXI_HDMI_PLL_CTRL_DIV_MASK (0xf << 4) + +#define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21) +#define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21) + +int sunxi_simplefb_setup(void *blob); + +#endif /* _SUNXI_DISPLAY_H */ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index c734cf0..366c0dc 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -134,6 +134,7 @@ enum sunxi_gpio_number { #define SUNXI_GPIO_OUTPUT 1 #define SUNXI_GPA0_EMAC 2 +#define SUN6I_GPA0_GMAC 2 #define SUN7I_GPA0_GMAC 5 #define SUNXI_GPB0_TWI0 2 diff --git a/arch/arm/include/asm/arch-uniphier/board.h b/arch/arm/include/asm/arch-uniphier/board.h index e6ba4e4..e3cba5b 100644 --- a/arch/arm/include/asm/arch-uniphier/board.h +++ b/arch/arm/include/asm/arch-uniphier/board.h @@ -12,10 +12,12 @@ defined(CONFIG_DCC_MICRO_SUPPORT_CARD) void support_card_reset(void); void support_card_init(void); +void support_card_late_init(void); int check_support_card(void); #else #define support_card_reset() do {} while (0) #define support_card_init() do {} while (0) +#define support_card_late_init() do {} while (0) static inline int check_support_card(void) { return 0; @@ -32,4 +34,9 @@ static inline void uniphier_board_init(void) support_card_init(); } +static inline void uniphier_board_late_init(void) +{ + support_card_late_init(); +} + #endif /* ARCH_BOARD_H */ diff --git a/arch/arm/include/asm/arch-uniphier/gpio.h b/arch/arm/include/asm/arch-uniphier/gpio.h new file mode 100644 index 0000000..1fc4e19 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/gpio.h @@ -0,0 +1,6 @@ +/* + * Dummy header file to enable CONFIG_OF_CONTROL. + * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. + * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable + * OF_CONTROL must have arch/gpio.h even if GPIO is not supported. + */ diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 9d797db..6b10bdf 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -256,6 +256,14 @@ #define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8) #define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf) +/* System Reset Controller (SRC) */ +#define SRC_SRSR_SW_RST (0x1 << 18) +#define SRC_SRSR_RESETB (0x1 << 7) +#define SRC_SRSR_JTAG_RST (0x1 << 5) +#define SRC_SRSR_WDOG_M4 (0x1 << 4) +#define SRC_SRSR_WDOG_A5 (0x1 << 3) +#define SRC_SRSR_POR_RST (0x1 << 0) + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index c69d064..438f128 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -17,6 +17,14 @@ struct arch_global_data { #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; #endif + +#if defined(CONFIG_U_QE) + u32 qe_clk; + u32 brg_clk; + uint mp_alloc_base; + uint mp_alloc_top; +#endif /* CONFIG_U_QE */ + #ifdef CONFIG_AT91FAMILY /* "static data" needed by at91's clock.c */ unsigned long cpu_clk_rate_hz; diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 1838234..323952f 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -540,6 +540,7 @@ extern struct prcm_regs const omap5_es2_prcm; extern struct prcm_regs const omap4_prcm; extern struct prcm_regs const dra7xx_prcm; extern struct dplls const **dplls_data; +extern struct dplls dra7xx_dplls; extern struct vcores_data const **omap_vcores; extern const u32 sys_clk_array[8]; extern struct omap_sys_ctrl_regs const **ctrl; @@ -547,6 +548,8 @@ extern struct omap_sys_ctrl_regs const omap4_ctrl; extern struct omap_sys_ctrl_regs const omap5_ctrl; extern struct omap_sys_ctrl_regs const dra7xx_ctrl; +extern struct pmic_data tps659038; + void hw_data_init(void); const struct dpll_params *get_mpu_dpll_params(struct dplls const *); diff --git a/arch/arm/include/asm/pcie_layerscape.h b/arch/arm/include/asm/pcie_layerscape.h new file mode 100644 index 0000000..fb08578 --- /dev/null +++ b/arch/arm/include/asm/pcie_layerscape.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PCIE_LAYERSCAPE_H_ +#define __PCIE_LAYERSCAPE_H_ + +void pci_init_board(void); +void ft_pcie_setup(void *blob, bd_t *bd); + +#endif diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 4949d57..a7f7c67 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -237,6 +237,26 @@ static void boot_prep_linux(bootm_headers_t *images) } } +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +static bool boot_nonsec(void) +{ + char *s = getenv("bootm_boot_mode"); +#ifdef CONFIG_ARMV7_BOOT_SEC_DEFAULT + bool nonsec = false; +#else + bool nonsec = true; +#endif + + if (s && !strcmp(s, "sec")) + nonsec = false; + + if (s && !strcmp(s, "nonsec")) + nonsec = true; + + return nonsec; +} +#endif + /* Subcommand: GO */ static void boot_jump_linux(bootm_headers_t *images, int flag) { @@ -285,12 +305,13 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) if (!fake) { #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) - armv7_init_nonsec(); - secure_ram_addr(_do_nonsec_entry)(kernel_entry, - 0, machid, r2); -#else - kernel_entry(0, machid, r2); + if (boot_nonsec()) { + armv7_init_nonsec(); + secure_ram_addr(_do_nonsec_entry)(kernel_entry, + 0, machid, r2); + } else #endif + kernel_entry(0, machid, r2); } #endif } diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 4e597a4..f1c0792 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -11,7 +11,7 @@ __weak void flush_cache(unsigned long start, unsigned long size) { -#if defined(CONFIG_ARM1136) +#if defined(CONFIG_CPU_ARM1136) #if !defined(CONFIG_SYS_ICACHE_OFF) asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */ @@ -21,14 +21,14 @@ __weak void flush_cache(unsigned long start, unsigned long size) asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */ #endif -#endif /* CONFIG_ARM1136 */ +#endif /* CONFIG_CPU_ARM1136 */ -#ifdef CONFIG_ARM926EJS +#ifdef CONFIG_CPU_ARM926EJS /* test and clean, page 2-23 of arm926ejs manual */ asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); -#endif /* CONFIG_ARM926EJS */ +#endif /* CONFIG_CPU_ARM926EJS */ return; } diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 29cdad0..22df3e5 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -78,7 +78,7 @@ clr_gd: strlo r0, [r1] /* clear 32-bit GD word */ addlo r1, r1, #4 /* move to next */ blo clr_gd -#if defined(CONFIG_SYS_MALLOC_F_LEN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_MALLOC_F_LEN) sub sp, sp, #CONFIG_SYS_MALLOC_F_LEN str sp, [r9, #GD_MALLOC_BASE] #endif @@ -104,6 +104,11 @@ clr_gd: ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ b relocate_code here: +/* + * now relocate vectors + */ + + bl relocate_vectors /* Set up final (full) environment */ diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index b4a258c..92f5314 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -11,6 +11,47 @@ #include <linux/linkage.h> /* + * Default/weak exception vectors relocation routine + * + * This routine covers the standard ARM cases: normal (0x00000000), + * high (0xffff0000) and VBAR. SoCs which do not comply with any of + * the standard cases must provide their own, strong, version. + */ + + .section .text.relocate_vectors,"ax",%progbits + .weak relocate_vectors + +ENTRY(relocate_vectors) + +#ifdef CONFIG_HAS_VBAR + /* + * If the ARM processor has the security extensions, + * use VBAR to relocate the exception vectors. + */ + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ + mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */ +#else + /* + * Copy the relocated exception vectors to the + * correct address + * CP15 c1 V bit gives us the location of the vectors: + * 0x00000000 or 0xFFFF0000. + */ + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ + mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */ + ands r2, r2, #(1 << 13) + ldreq r1, =0x00000000 /* If V=0 */ + ldrne r1, =0xFFFF0000 /* If V=1 */ + ldmia r0!, {r2-r8,r10} + stmia r1!, {r2-r8,r10} + ldmia r0!, {r2-r8,r10} + stmia r1!, {r2-r8,r10} +#endif + bx lr + +ENDPROC(relocate_vectors) + +/* * void relocate_code(addr_moni) * * This function relocates the monitor code. @@ -54,34 +95,6 @@ fixnext: cmp r2, r3 blo fixloop - /* - * Relocate the exception vectors - */ -#ifdef CONFIG_HAS_VBAR - /* - * If the ARM processor has the security extensions, - * use VBAR to relocate the exception vectors. - */ - ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ - mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */ -#else - /* - * Copy the relocated exception vectors to the - * correct address - * CP15 c1 V bit gives us the location of the vectors: - * 0x00000000 or 0xFFFF0000. - */ - ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ - mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */ - ands r2, r2, #(1 << 13) - ldreq r1, =0x00000000 /* If V=0 */ - ldrne r1, =0xFFFF0000 /* If V=1 */ - ldmia r0!, {r2-r8,r10} - stmia r1!, {r2-r8,r10} - ldmia r0!, {r2-r8,r10} - stmia r1!, {r2-r8,r10} -#endif - relocate_done: #ifdef __XSCALE__ @@ -96,9 +109,9 @@ relocate_done: /* ARMv4- don't know bx lr but the assembler fails to see that */ #ifdef __ARM_ARCH_4__ - mov pc, lr + mov pc, lr #else - bx lr + bx lr #endif ENDPROC(relocate_code) diff --git a/arch/avr32/Makefile b/arch/avr32/Makefile new file mode 100644 index 0000000..e9b3184 --- /dev/null +++ b/arch/avr32/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/avr32/cpu/start.o + +libs-y += arch/avr32/cpu/ +libs-y += arch/avr32/lib/ diff --git a/arch/avr32/cpu/Makefile b/arch/avr32/cpu/Makefile index 5e11721..00cede3 100644 --- a/arch/avr32/cpu/Makefile +++ b/arch/avr32/cpu/Makefile @@ -16,3 +16,5 @@ obj-y += cache.o obj-y += interrupts.o obj-$(CONFIG_PORTMUX_PIO) += portmux-pio.o obj-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o + +obj-$(if $(filter at32ap700x,$(SOC)),y) += at32ap700x/ diff --git a/arch/avr32/cpu/at32ap700x/clk.c b/arch/avr32/cpu/at32ap700x/clk.c index d5dbe3b..0fc6088 100644 --- a/arch/avr32/cpu/at32ap700x/clk.c +++ b/arch/avr32/cpu/at32ap700x/clk.c @@ -72,7 +72,7 @@ unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent, sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN)); rate = parent_rate; } else { - divider = min(255, divider / 2 - 1); + divider = min(255UL, divider / 2 - 1); sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN) | SM_BF(DIV, divider)); rate = parent_rate / (2 * (divider + 1)); diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile new file mode 100644 index 0000000..787475e --- /dev/null +++ b/arch/blackfin/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/blackfin/cpu/start.o + +libs-y += arch/blackfin/cpu/ +libs-y += arch/blackfin/lib/ diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c index b8be318..b0abeda 100644 --- a/arch/blackfin/cpu/jtag-console.c +++ b/arch/blackfin/cpu/jtag-console.c @@ -168,7 +168,7 @@ static int jtag_getc(struct stdio_dev *dev) inbound_len = emudat; } else { /* store the bytes */ - leftovers_len = min(4, inbound_len); + leftovers_len = min((size_t)4, inbound_len); inbound_len -= leftovers_len; leftovers = emudat; } diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h index 69f08bc..aadb0d2 100644 --- a/arch/blackfin/include/asm/io.h +++ b/arch/blackfin/include/asm/io.h @@ -11,10 +11,9 @@ #ifdef __KERNEL__ +#include <linux/compiler.h> #include <asm/blackfin.h> -#define __iomem - static inline void sync(void) { SSYNC(); diff --git a/arch/blackfin/lib/string.c b/arch/blackfin/lib/string.c index f0a061b..211df7b 100644 --- a/arch/blackfin/lib/string.c +++ b/arch/blackfin/lib/string.c @@ -121,7 +121,7 @@ static void dma_calc_size(unsigned long ldst, unsigned long lsrc, size_t count, *dshift = WDSIZE_P; #endif - *bpos = min(limit, ffs(ldst | lsrc | count)) - 1; + *bpos = min(limit, (unsigned long)ffs(ldst | lsrc | count)) - 1; } /* This version misbehaves for count values of 0 and 2^16+. @@ -157,7 +157,7 @@ void dma_memcpy_nocache(void *dst, const void *src, size_t count) #ifdef PSIZE /* The max memory DMA peripheral transfer size is 4 bytes. */ - dsize |= min(2, bpos) << PSIZE_P; + dsize |= min(2UL, bpos) << PSIZE_P; #endif /* Copy sram functions from sdram to sram */ diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile new file mode 100644 index 0000000..aa3d2fa --- /dev/null +++ b/arch/m68k/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/m68k/cpu/$(CPU)/start.o + +libs-y += arch/m68k/cpu/$(CPU)/ +libs-y += arch/m68k/lib/ diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile new file mode 100644 index 0000000..ae4adc2 --- /dev/null +++ b/arch/microblaze/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/microblaze/cpu/start.o + +libs-y += arch/microblaze/cpu/ +libs-y += arch/microblaze/lib/ diff --git a/arch/mips/Makefile b/arch/mips/Makefile new file mode 100644 index 0000000..1907b57 --- /dev/null +++ b/arch/mips/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/mips/cpu/$(CPU)/start.o + +libs-y += arch/mips/cpu/$(CPU)/ +libs-y += arch/mips/lib/ diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile index e0e6309..fa82dd3 100644 --- a/arch/mips/cpu/mips32/Makefile +++ b/arch/mips/cpu/mips32/Makefile @@ -8,3 +8,5 @@ extra-y = start.o obj-y = cache.o obj-y += cpu.o interrupts.o time.o + +obj-$(CONFIG_SOC_AU1X00) += au1x00/ diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c index a3dac70..74bdb77 100644 --- a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c +++ b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c @@ -54,8 +54,6 @@ #define readl(a) au_readl((long)(a)) #define writel(v,a) au_writel((v),(int)(a)) -#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - #define DEBUG #ifdef DEBUG #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 68e59b5..384ea26 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -136,10 +136,11 @@ reset: /* Set up temporary stack */ li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET + move fp, sp la t9, board_init_f jr t9 - nop + move ra, zero /* * void relocate_code (addr_sp, gd, addr_moni) @@ -155,6 +156,7 @@ reset: .ent relocate_code relocate_code: move sp, a0 # set new stack pointer + move fp, sp move s0, a1 # save gd in s0 move s2, a2 # save destination address in s2 @@ -260,8 +262,9 @@ in_ram: addi t1, 4 move a0, s0 # a0 <-- gd + move a1, s2 la t9, board_init_r jr t9 - move a1, s2 + move ra, zero .end relocate_code diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S index 92954e1..6ff714e 100644 --- a/arch/mips/cpu/mips64/start.S +++ b/arch/mips/cpu/mips64/start.S @@ -130,10 +130,11 @@ reset: /* Set up temporary stack */ dli sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET + move fp, sp dla t9, board_init_f jr t9 - nop + move ra, zero /* * void relocate_code (addr_sp, gd, addr_moni) @@ -149,6 +150,7 @@ reset: .ent relocate_code relocate_code: move sp, a0 # set new stack pointer + move fp, sp move s0, a1 # save gd in s0 move s2, a2 # save destination address in s2 @@ -254,8 +256,9 @@ in_ram: daddi t1, 8 move a0, s0 # a0 <-- gd + move a1, s2 dla t9, board_init_r jr t9 - move a1, s2 + move ra, zero .end relocate_code diff --git a/arch/mips/include/asm/unaligned.h b/arch/mips/include/asm/unaligned.h index 1d5112e..c25a846 100644 --- a/arch/mips/include/asm/unaligned.h +++ b/arch/mips/include/asm/unaligned.h @@ -8,7 +8,7 @@ #ifndef _ASM_MIPS_UNALIGNED_H #define _ASM_MIPS_UNALIGNED_H -#include <compiler.h> +#include <linux/compiler.h> #if defined(__MIPSEB__) #define get_unaligned __get_unaligned_be #define put_unaligned __put_unaligned_be diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index e483e86..7f9b653 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -5,9 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifndef CONFIG_SYS_GENERIC_BOARD -obj-y += board.o -endif obj-y += io.o obj-$(CONFIG_CMD_BOOTM) += bootm.o diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c deleted file mode 100644 index 3feb020..0000000 --- a/arch/mips/lib/board.c +++ /dev/null @@ -1,320 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <malloc.h> -#include <serial.h> -#include <stdio_dev.h> -#include <version.h> -#include <net.h> -#include <environment.h> -#include <nand.h> -#include <onenand_uboot.h> -#include <spi.h> - -#ifdef CONFIG_BITBANGMII -#include <miiphy.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -ulong monitor_flash_len; - -static char *failed = "*** failed ***\n"; - -int __board_early_init_f(void) -{ - /* - * Nothing to do in this dummy implementation - */ - return 0; -} -int board_early_init_f(void) - __attribute__((weak, alias("__board_early_init_f"))); - -static int init_func_ram(void) -{ -#ifdef CONFIG_BOARD_TYPES - int board_type = gd->board_type; -#else - int board_type = 0; /* use dummy arg */ -#endif - puts("DRAM: "); - - gd->ram_size = initdram(board_type); - if (gd->ram_size > 0) { - print_size(gd->ram_size, "\n"); - return 0; - } - puts(failed); - return 1; -} - -static int display_banner(void) -{ - - printf("\n\n%s\n\n", version_string); - return 0; -} - -#ifndef CONFIG_SYS_NO_FLASH -static void display_flash_config(ulong size) -{ - puts("Flash: "); - print_size(size, "\n"); -} -#endif - -static int init_baudrate(void) -{ - gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); - return 0; -} - - -/* - * Breath some life into the board... - * - * The first part of initialization is running from Flash memory; - * its main purpose is to initialize the RAM so that we - * can relocate the monitor code to RAM. - */ - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ -typedef int (init_fnc_t)(void); - -init_fnc_t *init_sequence[] = { - board_early_init_f, - timer_init, - env_init, /* initialize environment */ - init_baudrate, /* initialize baudrate settings */ - serial_init, /* serial communications setup */ - console_init_f, - display_banner, /* say that we are here */ - checkboard, - init_func_ram, - NULL, -}; - - -void board_init_f(ulong bootflag) -{ - gd_t gd_data, *id; - bd_t *bd; - init_fnc_t **init_fnc_ptr; - ulong addr, addr_sp, len; - ulong *s; - - /* Pointer is writable since we allocated a register for it. - */ - gd = &gd_data; - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("" : : : "memory"); - - memset((void *)gd, 0, sizeof(gd_t)); - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - if ((*init_fnc_ptr)() != 0) - hang(); - } - - /* - * Now that we have DRAM mapped and working, we can - * relocate the code and continue running from DRAM. - */ - addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; - - /* We can reserve some RAM "on top" here. - */ - - /* round down to next 4 kB limit. - */ - addr &= ~(4096 - 1); - debug("Top of RAM usable for U-Boot at: %08lx\n", addr); - - /* Reserve memory for U-Boot code, data & bss - * round down to next 16 kB limit - */ - len = bss_end() - CONFIG_SYS_MONITOR_BASE; - addr -= len; - addr &= ~(16 * 1024 - 1); - - debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); - - /* Reserve memory for malloc() arena. - */ - addr_sp = addr - TOTAL_MALLOC_LEN; - debug("Reserving %dk for malloc() at: %08lx\n", - TOTAL_MALLOC_LEN >> 10, addr_sp); - - /* - * (permanently) allocate a Board Info struct - * and a permanent copy of the "global" data - */ - addr_sp -= sizeof(bd_t); - bd = (bd_t *)addr_sp; - gd->bd = bd; - debug("Reserving %zu Bytes for Board Info at: %08lx\n", - sizeof(bd_t), addr_sp); - - addr_sp -= sizeof(gd_t); - id = (gd_t *)addr_sp; - debug("Reserving %zu Bytes for Global Data at: %08lx\n", - sizeof(gd_t), addr_sp); - - /* Reserve memory for boot params. - */ - addr_sp -= CONFIG_SYS_BOOTPARAMS_LEN; - bd->bi_boot_params = addr_sp; - debug("Reserving %dk for boot params() at: %08lx\n", - CONFIG_SYS_BOOTPARAMS_LEN >> 10, addr_sp); - - /* - * Finally, we set up a new (bigger) stack. - * - * Leave some safety gap for SP, force alignment on 16 byte boundary - * Clear initial stack frame - */ - addr_sp -= 16; - addr_sp &= ~0xF; - s = (ulong *)addr_sp; - *s-- = 0; - *s-- = 0; - addr_sp = (ulong)s; - debug("Stack Pointer at: %08lx\n", addr_sp); - - /* - * Save local variables to board info struct - */ - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM */ - bd->bi_memsize = gd->ram_size; /* size of DRAM in bytes */ - - memcpy(id, (void *)gd, sizeof(gd_t)); - - relocate_code(addr_sp, id, addr); - - /* NOTREACHED - relocate_code() does not return */ -} - -/* - * This is the next part if the initialization sequence: we are now - * running from RAM and have a "normal" C environment, i. e. global - * data can be written, BSS has been cleared, the stack size in not - * that critical any more, etc. - */ - -void board_init_r(gd_t *id, ulong dest_addr) -{ -#ifndef CONFIG_SYS_NO_FLASH - ulong size; -#endif - bd_t *bd; - - gd = id; - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - - debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr); - - gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE; - - monitor_flash_len = image_copy_end() - dest_addr; - - serial_initialize(); - - bd = gd->bd; - - /* The Malloc area is immediately below the monitor copy in DRAM */ - mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off - - TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN); - -#ifndef CONFIG_SYS_NO_FLASH - /* configure available FLASH banks */ - size = flash_init(); - display_flash_config(size); - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; - bd->bi_flashsize = size; - -#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE - bd->bi_flashoffset = monitor_flash_len; /* reserved area for U-Boot */ -#else - bd->bi_flashoffset = 0; -#endif -#else - bd->bi_flashstart = 0; - bd->bi_flashsize = 0; - bd->bi_flashoffset = 0; -#endif - -#ifdef CONFIG_CMD_NAND - puts("NAND: "); - nand_init(); /* go init the NAND */ -#endif - -#if defined(CONFIG_CMD_ONENAND) - onenand_init(); -#endif - - /* relocate environment function pointers etc. */ - env_relocate(); - -#if defined(CONFIG_PCI) - /* - * Do pci configuration - */ - pci_init(); -#endif - -/** leave this here (after malloc(), environment and PCI are working) **/ - /* Initialize stdio devices */ - stdio_init(); - - jumptable_init(); - - /* Initialize the console (after the relocation and devices init) */ - console_init_r(); -/** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **/ - - /* Initialize from environment */ - load_addr = getenv_ulong("loadaddr", 16, load_addr); - -#ifdef CONFIG_CMD_SPI - puts("SPI: "); - spi_init(); /* go init the SPI */ - puts("ready\n"); -#endif - -#if defined(CONFIG_MISC_INIT_R) - /* miscellaneous platform dependent initialisations */ - misc_init_r(); -#endif - -#ifdef CONFIG_BITBANGMII - bb_miiphy_init(); -#endif -#if defined(CONFIG_CMD_NET) - puts("Net: "); - eth_initialize(gd->bd); -#endif - - /* main_loop() can return to retry autoboot, if so just run it again. */ - for (;;) - main_loop(); - - /* NOTREACHED - no way out of command loop except booting */ -} diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 71bb0d2..e0722d2 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -6,10 +6,7 @@ */ #include <common.h> -#include <command.h> #include <image.h> -#include <u-boot/zlib.h> -#include <asm/byteorder.h> #include <asm/addrspace.h> DECLARE_GLOBAL_DATA_PTR; @@ -52,6 +49,20 @@ void arch_lmb_reserve(struct lmb *lmb) lmb_reserve(lmb, sp, CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp); } +static int boot_setup_linux(bootm_headers_t *images) +{ + int ret; + ulong rd_len; + + rd_len = images->rd_end - images->rd_start; + ret = boot_ramdisk_high(&images->lmb, images->rd_start, + rd_len, &images->initrd_start, &images->initrd_end); + if (ret) + return ret; + + return 0; +} + static void linux_cmdline_init(void) { linux_argc = 1; @@ -224,6 +235,8 @@ static void boot_jump_linux(bootm_headers_t *images) int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images) { + int ret; + /* No need for those on MIPS */ if (flag & BOOTM_STATE_OS_BD_T) return -1; @@ -243,6 +256,10 @@ int do_bootm_linux(int flag, int argc, char * const argv[], return 0; } + ret = boot_setup_linux(images); + if (ret) + return ret; + boot_cmdline_linux(images); boot_prep_linux(images); boot_jump_linux(images); diff --git a/arch/nds32/Makefile b/arch/nds32/Makefile new file mode 100644 index 0000000..e1eccba --- /dev/null +++ b/arch/nds32/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/nds32/cpu/$(CPU)/start.o + +libs-y += arch/nds32/cpu/$(CPU)/ +libs-y += arch/nds32/lib/ diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile index 206d304..8ab1fce 100644 --- a/arch/nds32/cpu/n1213/Makefile +++ b/arch/nds32/cpu/n1213/Makefile @@ -9,7 +9,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# necessary to create built-in.o -obj- := __dummy__.o - extra-y = start.o + +obj-$(if $(filter ag101,$(SOC)),y) += ag101/ +obj-$(if $(filter ag102,$(SOC)),y) += ag102/ diff --git a/arch/nios2/Makefile b/arch/nios2/Makefile new file mode 100644 index 0000000..18685a9 --- /dev/null +++ b/arch/nios2/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/nios2/cpu/start.o + +libs-y += arch/nios2/cpu/ +libs-y += arch/nios2/lib/ diff --git a/arch/nios2/cpu/fdt.c b/arch/nios2/cpu/fdt.c index 4d88f16..5024682 100644 --- a/arch/nios2/cpu/fdt.c +++ b/arch/nios2/cpu/fdt.c @@ -18,11 +18,13 @@ DECLARE_GLOBAL_DATA_PTR; -void __ft_board_setup(void *blob, bd_t *bd) +int __ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } -void ft_board_setup(void *blob, bd_t *bd) \ +int ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup"))); void ft_cpu_setup(void *blob, bd_t *bd) @@ -32,5 +34,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) * Note: aliases in the dts are required for this */ fdt_fixup_ethernet(blob); + + return 0; } #endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */ diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile new file mode 100644 index 0000000..c4da3ce --- /dev/null +++ b/arch/openrisc/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/openrisc/cpu/start.o + +libs-y += arch/openrisc/cpu/ +libs-y += arch/openrisc/lib/ diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile new file mode 100644 index 0000000..8aa1d60 --- /dev/null +++ b/arch/powerpc/Makefile @@ -0,0 +1,11 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/powerpc/cpu/$(CPU)/start.o +head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o +head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o + +libs-y += arch/powerpc/cpu/$(CPU)/ +libs-y += arch/powerpc/cpu/ +libs-y += arch/powerpc/lib/ diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S index 02c706e..94eb0d3 100644 --- a/arch/powerpc/cpu/mpc5xxx/start.S +++ b/arch/powerpc/cpu/mpc5xxx/start.S @@ -76,6 +76,21 @@ _start: * been done in the SPL u-boot version. */ GET_GOT /* initialize GOT access */ + + /* + * The GD (global data) struct needs to get cleared. Lets do + * this by calling memset(). + * This function is called when the platform is build with SPL + * support from the main (full-blown) U-Boot. And the GD needs + * to get cleared (again) so that the following generic + * board support code, defined via CONFIG_SYS_GENERIC_BOARD, + * initializes all variables correctly. + */ + mr r3, r2 /* parameter 1: GD pointer */ + li r4,0 /* parameter 2: value to fill */ + li r5,GD_SIZE /* parameter 3: count */ + bl memset + bl board_init_f /* run 1st part of board init code (in Flash)*/ /* NOTREACHED - board_init_f() does not return */ #else diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c index 3c8b2d9..b7c1b55 100644 --- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c +++ b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c @@ -42,8 +42,6 @@ #define readl(a) (*((volatile u32 *)(a))) #define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) -#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - #ifdef DEBUG #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) #else diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 2a1abe0..69a600c 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -68,6 +68,9 @@ config TARGET_TUXX1 config TARGET_TQM834X bool "Support TQM834x" +config TARGET_HRCON + bool "Support hrcon" + endchoice source "board/esd/vme8349/Kconfig" @@ -88,5 +91,6 @@ source "board/mpc8308_p1m/Kconfig" source "board/sbc8349/Kconfig" source "board/tqc/tqm834x/Kconfig" source "board/ve8313/Kconfig" +source "board/gdsys/mpc8308/Kconfig" endmenu diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index af75c63..9bd86d8 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -283,6 +283,7 @@ in_flash: bl cpu_init_f /* run 1st part of board init code (in Flash)*/ + li r3, 0 /* clear boot_flag for calling board_init_f */ bl board_init_f /* NOTREACHED - board_init_f() does not return */ diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 7b42d06..7501eb4 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -110,6 +110,14 @@ config TARGET_P2041RDB config TARGET_QEMU_PPCE500 bool "Support qemu-ppce500" +config TARGET_T102XQDS + bool "Support T102xQDS" + select SUPPORT_SPL + +config TARGET_T102XRDB + bool "Support T102xRDB" + select SUPPORT_SPL + config TARGET_T1040QDS bool "Support T1040QDS" @@ -183,6 +191,8 @@ source "board/freescale/p2020come/Kconfig" source "board/freescale/p2020ds/Kconfig" source "board/freescale/p2041rdb/Kconfig" source "board/freescale/qemu-ppce500/Kconfig" +source "board/freescale/t102xqds/Kconfig" +source "board/freescale/t102xrdb/Kconfig" source "board/freescale/t1040qds/Kconfig" source "board/freescale/t104xrdb/Kconfig" source "board/freescale/t208xqds/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index ad26b43..b93158b 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -51,6 +51,8 @@ obj-$(CONFIG_PPC_T1040) += t1040_ids.o obj-$(CONFIG_PPC_T1042) += t1040_ids.o obj-$(CONFIG_PPC_T1020) += t1040_ids.o obj-$(CONFIG_PPC_T1022) += t1040_ids.o +obj-$(CONFIG_PPC_T1023) += t1024_ids.o +obj-$(CONFIG_PPC_T1024) += t1024_ids.o obj-$(CONFIG_PPC_T2080) += t2080_ids.o obj-$(CONFIG_PPC_T2081) += t2080_ids.o @@ -97,6 +99,8 @@ obj-$(CONFIG_PPC_T1040) += t1040_serdes.o obj-$(CONFIG_PPC_T1042) += t1040_serdes.o obj-$(CONFIG_PPC_T1020) += t1040_serdes.o obj-$(CONFIG_PPC_T1022) += t1040_serdes.o +obj-$(CONFIG_PPC_T1023) += t1024_serdes.o +obj-$(CONFIG_PPC_T1024) += t1024_serdes.o obj-$(CONFIG_PPC_T2080) += t2080_serdes.o obj-$(CONFIG_PPC_T2081) += t2080_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 39b8e3e..598f7bd 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -55,12 +55,12 @@ struct liodn_id_table liodn_tbl[] = { SET_SDHC_LIODN(1, 552), - SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(1, "fsl-usb2-dr", 553), SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), - SET_DMA_LIODN(1, 147), - SET_DMA_LIODN(2, 227), + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), #ifndef CONFIG_PPC_B4420 SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c index cf18be5..63172de 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -18,6 +18,8 @@ struct serdes_config { #ifdef CONFIG_PPC_B4860 static struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ + {0x01, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x02, {AURORA, AURORA, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, {0x04, {AURORA, AURORA, CPRI6, CPRI5, @@ -26,6 +28,8 @@ static struct serdes_config serdes1_cfg_tbl[] = { CPRI4, CPRI3, CPRI2, CPRI1} }, {0x06, {AURORA, AURORA, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x07, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x08, {AURORA, AURORA, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, {0x09, {AURORA, AURORA, CPRI6, CPRI5, @@ -184,12 +188,17 @@ static struct serdes_config serdes1_cfg_tbl[] = { CPRI4, CPRI3, NONE, NONE} }, {0x0F, {NONE, NONE, CPRI6, CPRI5, CPRI4, CPRI3, NONE, NONE} }, + {0x17, {NONE, NONE, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, {0x18, {NONE, NONE, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, {0x1B, {NONE, NONE, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, + {0x1D, {NONE, NONE, AURORA, AURORA, + NONE, NONE, NONE, NONE} }, {0x1E, {NONE, NONE, AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x21, {NONE, NONE, AURORA, AURORA, @@ -199,19 +208,29 @@ static struct serdes_config serdes1_cfg_tbl[] = { {} }; static struct serdes_config serdes2_cfg_tbl[] = { + {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + NONE, NONE, NONE, NONE} }, {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, NONE, NONE, NONE, NONE} }, {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, NONE, NONE, NONE, NONE} }, + {0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, AURORA, AURORA, NONE, NONE, NONE, NONE} }, + {0x99, {PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, {0x9A, {PCIE1, PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, + {0x9D, {PCIE1, PCIE1, PCIE1, PCIE1, + NONE, NONE, NONE, NONE} }, {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE} }, {} diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 3a04a89..2d5ddf0 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -9,6 +9,7 @@ #include <linux/compiler.h> #include <asm/fsl_errata.h> #include <asm/processor.h> +#include <fsl_usb.h> #include "fsl_corenet_serdes.h" #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 @@ -270,7 +271,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("Work-around for Erratum USB14 enabled\n"); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 - puts("Work-around for Erratum A007186 enabled\n"); + if (has_erratum_a007186()) + puts("Work-around for Erratum A007186 enabled\n"); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 puts("Work-around for Erratum A006593 enabled\n"); @@ -293,6 +295,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (has_erratum_a007075()) puts("Work-around for Erratum A007075 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007798 + if (has_erratum_a007798()) + puts("Work-around for Erratum A007798 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) @@ -308,6 +314,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A005434 puts("Work-around for Erratum A-005434 enabled\n"); #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_A008044) && \ + defined(CONFIG_A008044_WORKAROUND) + if (IS_SVR_REV(svr, 1, 0)) + puts("Work-around for Erratum A-008044 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS) + puts("Work-around for Erratum XFI on B4860QDS enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 072387a..5ca9bf5 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -70,9 +70,9 @@ void setup_ifc(void) #endif /* Change flash's physical address */ - out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); - out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); - out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); + ifc_out32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); + ifc_out32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); + ifc_out32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); return ; } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 8edf5bb..5cfae47 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -11,6 +11,7 @@ #include <asm/processor.h> #include <asm/fsl_law.h> #include <asm/errno.h> +#include <asm/fsl_errata.h> #include "fsl_corenet2_serdes.h" #ifdef CONFIG_SYS_FSL_SRDS_1 @@ -203,7 +204,7 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK; - if (sel == 0x01 || sel == 0x02) { + if (has_erratum_a007186() && (sel == 0x01 || sel == 0x02)) { for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) { pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); debug("A007186: pll_num=%x pllcr0=%x\n", diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 488e078..6e3cddd 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -50,8 +50,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), - SET_DMA_LIODN(1, 197), - SET_DMA_LIODN(2, 198), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 197), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 198), SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 7d98870..2b57703 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -51,8 +51,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), - SET_DMA_LIODN(1, 197), - SET_DMA_LIODN(2, 198), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 197), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 198), SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index b2a23c0..94a5143 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -40,8 +40,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), - SET_DMA_LIODN(1, 196), - SET_DMA_LIODN(2, 197), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 196), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 197), SET_GUTS_LIODN("fsl,srio-rmu", 200, rmuliodnr, 0xd3000), diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index b5d787c..0f292cf 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -51,8 +51,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), - SET_DMA_LIODN(1, 197), - SET_DMA_LIODN(2, 198), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 197), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 198), SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index 990f179..d4343ef 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -42,8 +42,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 196), SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 197), - SET_DMA_LIODN(1, 193), - SET_DMA_LIODN(2, 194), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 193), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 194), }; int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 3236f6a..7e69873 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -37,6 +37,7 @@ void get_sys_info(sys_info_t *sys_info) #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; #endif + __maybe_unused u32 svr; const u8 core_cplx_PLL[16] = { [ 0] = 0, /* CC1 PPL / 1 */ @@ -122,11 +123,27 @@ void get_sys_info(sys_info_t *sys_info) /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 * it uses 6. + * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 */ #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) - if (SVR_MAJ(get_svr()) >= 2) - mem_pll_rat *= 2; + defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) + svr = get_svr(); + switch (SVR_SOC_VER(svr)) { + case SVR_T4240: + case SVR_T4160: + case SVR_T4120: + case SVR_T4080: + if (SVR_MAJ(svr) >= 2) + mem_pll_rat *= 2; + break; + case SVR_T2080: + case SVR_T2081: + if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1)) + mem_pll_rat *= 2; + break; + default: + break; + } #endif if (mem_pll_rat > 2) sys_info->freq_ddrbus *= mem_pll_rat; @@ -168,6 +185,9 @@ void get_sys_info(sys_info_t *sys_info) defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define FM1_CLK_SEL 0xe0000000 #define FM1_CLK_SHIFT 29 +#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) +#define FM1_CLK_SEL 0x00000007 +#define FM1_CLK_SHIFT 0 #else #define PME_CLK_SEL 0xe0000000 #define PME_CLK_SHIFT 29 @@ -175,8 +195,12 @@ void get_sys_info(sys_info_t *sys_info) #define FM1_CLK_SHIFT 26 #endif #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) + rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; +#else rcw_tmp = in_be32(&gur->rcwsr[7]); #endif +#endif #ifdef CONFIG_SYS_DPAA_PME #ifndef CONFIG_PME_PLAT_CLK_DIV @@ -213,7 +237,10 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_SYS_DPAA_QBMAN - sys_info->freq_qman = sys_info->freq_systembus / 2; +#ifndef CONFIG_QBMAN_CLK_DIV +#define CONFIG_QBMAN_CLK_DIV 2 +#endif + sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV; #endif #ifdef CONFIG_SYS_DPAA_FMAN @@ -430,7 +457,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #if defined(CONFIG_FSL_IFC) - ccr = in_be32(&ifc_regs->ifc_ccr); + ccr = ifc_in32(&ifc_regs->ifc_ccr); ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; sys_info->freq_localbus = sys_info->freq_systembus / ccr; diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c new file mode 100644 index 0000000..132689b --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c @@ -0,0 +1,82 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 27, 1, 0), + SET_QP_INFO(2, 28, 1, 0), + SET_QP_INFO(3, 29, 1, 1), + SET_QP_INFO(4, 30, 1, 1), + SET_QP_INFO(5, 31, 1, 2), + SET_QP_INFO(6, 32, 1, 2), + SET_QP_INFO(7, 33, 1, 3), + SET_QP_INFO(8, 34, 1, 3), + SET_QP_INFO(9, 35, 1, 0), + SET_QP_INFO(10, 36, 1, 0), +}; +#endif + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(62), + SET_BMAN_LIODN(63), +#endif + + SET_SDHC_LIODN(1, 552), + + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(2, "fsl-usb2-dr", 554), + + SET_SATA_LIODN(1, 555), + + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), + /* SET_NEXUS_LIODN(557), -- not yet implemented */ + SET_QE_LIODN(559), + SET_TDM_LIODN(560), +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_1G_LIODN(1, 1, 89), + SET_FMAN_RX_1G_LIODN(1, 2, 90), + SET_FMAN_RX_1G_LIODN(1, 3, 91), + SET_FMAN_RX_10G_LIODN(1, 0, 94), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 454, 458), + SET_SEC_JR_LIODN_ENTRY(1, 455, 459), + SET_SEC_JR_LIODN_ENTRY(2, 456, 460), + SET_SEC_JR_LIODN_ENTRY(3, 457, 461), + SET_SEC_RTIC_LIODN_ENTRY(a, 453), + SET_SEC_RTIC_LIODN_ENTRY(b, 549), + SET_SEC_RTIC_LIODN_ENTRY(c, 550), + SET_SEC_RTIC_LIODN_ENTRY(d, 551), + SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), + SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), +#endif +}; diff --git a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c new file mode 100644 index 0000000..7dc8385 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c @@ -0,0 +1,52 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> + + +static u8 serdes_cfg_tbl[][4] = { + [0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1}, + [0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1}, + [0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1}, + [0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1}, + [0x46] = {PCIE1, PCIE1, PCIE2, SATA1}, + [0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1}, + [0x56] = {PCIE1, PCIE3, PCIE2, SATA1}, + [0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1}, + [0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1}, + [0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1}, + [0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1}, + [0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC1}, + [0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1}, + [0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC1}, + [0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1}, + [0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1}, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + + if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < 4; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index a5dfb81..8091722 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -24,12 +24,6 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { }; #endif -struct srio_liodn_id_table srio_liodn_tbl[] = { - SET_SRIO_LIODN_1(1, 307), - SET_SRIO_LIODN_1(2, 387), -}; -int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); - struct liodn_id_table liodn_tbl[] = { #ifdef CONFIG_SYS_DPAA_QBMAN SET_QMAN_LIODN(62), @@ -38,12 +32,21 @@ struct liodn_id_table liodn_tbl[] = { SET_SDHC_LIODN(1, 552), + SET_PME_LIODN(117), + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(2, "fsl-usb2-dr", 554), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 148), + SET_SATA_LIODN(1, 555), + SET_SATA_LIODN(2, 556), - SET_DMA_LIODN(1, 147), - SET_DMA_LIODN(2, 227), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), + + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), /* SET_NEXUS_LIODN(557), -- not yet implemented */ SET_QE_LIODN(559), @@ -74,6 +77,12 @@ struct liodn_id_table sec_liodn_tbl[] = { SET_SEC_RTIC_LIODN_ENTRY(d, 551), SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), + SET_SEC_DECO_LIODN_ENTRY(2, 543, 612), + SET_SEC_DECO_LIODN_ENTRY(3, 544, 613), + SET_SEC_DECO_LIODN_ENTRY(4, 545, 614), + SET_SEC_DECO_LIODN_ENTRY(5, 546, 615), + SET_SEC_DECO_LIODN_ENTRY(6, 547, 616), + SET_SEC_DECO_LIODN_ENTRY(7, 548, 617), }; int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); @@ -82,4 +91,7 @@ struct liodn_id_table liodn_bases[] = { #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), #endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846), +#endif }; diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c index 0bfd447..eda7f59 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -63,9 +63,9 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), - SET_DMA_LIODN(1, 147), - SET_DMA_LIODN(2, 227), - SET_DMA_LIODN(3, 226), + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), + SET_DMA_LIODN(3, "fsl,elo3-dma", 226), SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c index 7138bb4..c65f41d 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c @@ -169,6 +169,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = { {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, + {0x2E, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, {0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SATA1, SATA2} }, {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} }, diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 1a3cb33..470b080 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -93,8 +93,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), - SET_DMA_LIODN(1, 147), - SET_DMA_LIODN(2, 227), + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 129ec66..4adba95 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -300,7 +300,7 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; u64 memsize = (u64)memsize_in_meg << 20; - memsize = min(memsize, CONFIG_MAX_MEM_MAPPED); + memsize = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED); memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM); if (memsize) diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index e447748e..99420ab 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -13,9 +13,6 @@ config TARGET_COGENT_MPC8XX config TARGET_ESTEEM192E bool "Support ESTEEM192E" -config TARGET_HERMES - bool "Support hermes" - config TARGET_IP860 bool "Support IP860" @@ -112,7 +109,6 @@ source "board/LEOX/elpt860/Kconfig" source "board/RRvision/Kconfig" source "board/cogent/Kconfig" source "board/esteem192e/Kconfig" -source "board/hermes/Kconfig" source "board/ip860/Kconfig" source "board/ivm/Kconfig" source "board/kup/kup4k/Kconfig" diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 60c401e..6a1cd46 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -125,8 +125,7 @@ void cpu_init_f (volatile immap_t * immr) * I owe him a free beer. - wd] */ -#if defined(CONFIG_HERMES) || \ - defined(CONFIG_IP860) || \ +#if defined(CONFIG_IP860) || \ defined(CONFIG_IVML24) || \ defined(CONFIG_IVMS8) || \ defined(CONFIG_LWMON) || \ diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 84fec5e..2d28eb2 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -76,6 +76,10 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(T1020, T1020, 0), CPU_TYPE_ENTRY(T1021, T1021, 0), CPU_TYPE_ENTRY(T1022, T1022, 0), + CPU_TYPE_ENTRY(T1024, T1024, 0), + CPU_TYPE_ENTRY(T1023, T1023, 0), + CPU_TYPE_ENTRY(T1014, T1014, 0), + CPU_TYPE_ENTRY(T1013, T1013, 0), CPU_TYPE_ENTRY(T2080, T2080, 0), CPU_TYPE_ENTRY(T2081, T2081, 0), CPU_TYPE_ENTRY(BSC9130, 9130, 1), diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index c6b4d95..1c63f93 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -73,110 +73,6 @@ void ft_fixup_num_cores(void *blob) { } #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */ -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, - const char *phy_type, int start_offset) -{ - const char *compat_dr = "fsl-usb2-dr"; - const char *compat_mph = "fsl-usb2-mph"; - const char *prop_mode = "dr_mode"; - const char *prop_type = "phy_type"; - const char *node_type = NULL; - int node_offset; - int err; - - node_offset = fdt_node_offset_by_compatible(blob, - start_offset, compat_mph); - if (node_offset < 0) { - node_offset = fdt_node_offset_by_compatible(blob, - start_offset, compat_dr); - if (node_offset < 0) { - printf("WARNING: could not find compatible" - " node %s or %s: %s.\n", compat_mph, - compat_dr, fdt_strerror(node_offset)); - return -1; - } else - node_type = compat_dr; - } else - node_type = compat_mph; - - if (mode) { - err = fdt_setprop(blob, node_offset, prop_mode, mode, - strlen(mode) + 1); - if (err < 0) - printf("WARNING: could not set %s for %s: %s.\n", - prop_mode, node_type, fdt_strerror(err)); - } - - if (phy_type) { - err = fdt_setprop(blob, node_offset, prop_type, phy_type, - strlen(phy_type) + 1); - if (err < 0) - printf("WARNING: could not set %s for %s: %s.\n", - prop_type, node_type, fdt_strerror(err)); - } - - return node_offset; -} - -void fdt_fixup_dr_usb(void *blob, bd_t *bd) -{ - const char *modes[] = { "host", "peripheral", "otg" }; - const char *phys[] = { "ulpi", "utmi" }; - int usb_mode_off = -1; - int usb_phy_off = -1; - char str[5]; - int i, j; - - for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) { - const char *dr_mode_type = NULL; - const char *dr_phy_type = NULL; - int mode_idx = -1, phy_idx = -1; - snprintf(str, 5, "%s%d", "usb", i); - if (hwconfig(str)) { - for (j = 0; j < ARRAY_SIZE(modes); j++) { - if (hwconfig_subarg_cmp(str, "dr_mode", - modes[j])) { - mode_idx = j; - break; - } - } - - for (j = 0; j < ARRAY_SIZE(phys); j++) { - if (hwconfig_subarg_cmp(str, "phy_type", - phys[j])) { - phy_idx = j; - break; - } - } - - if (mode_idx < 0 && phy_idx < 0) { - printf("WARNING: invalid phy or mode\n"); - return; - } - - if (mode_idx > -1) - dr_mode_type = modes[mode_idx]; - - if (phy_idx > -1) - dr_phy_type = phys[phy_idx]; - } - - usb_mode_off = fdt_fixup_usb_mode_phy_type(blob, - dr_mode_type, NULL, usb_mode_off); - - if (usb_mode_off < 0) - return; - - usb_phy_off = fdt_fixup_usb_mode_phy_type(blob, - NULL, dr_phy_type, usb_phy_off); - - if (usb_phy_off < 0) - return; - } -} -#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */ - /* * update crypto node properties to a specified revision of the SEC * called with sec_rev == 0 if not on an E processor diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index f8d03cb..71bb9d7 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -1661,7 +1661,7 @@ static void program_mode(unsigned long *dimm_populated, for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_populated[dimm_num] != SDRAM_NONE) - t_wr_ns = max(t_wr_ns, + t_wr_ns = max(t_wr_ns, (unsigned long) spd_read(iic0_dimm_addr[dimm_num], 36) >> 2); } @@ -1838,12 +1838,18 @@ static void program_tr(unsigned long *dimm_populated, else sdram_ddr1 = false; - t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2); - t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2); - t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2); - t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30)); - t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41)); - t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42)); + t_rcd_ns = max(t_rcd_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 29) >> 2); + t_rrd_ns = max(t_rrd_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 28) >> 2); + t_rp_ns = max(t_rp_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 27) >> 2); + t_ras_ns = max(t_ras_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 30)); + t_rc_ns = max(t_rc_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 41)); + t_rfc_ns = max(t_rfc_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 42)); } } @@ -1916,9 +1922,12 @@ static void program_tr(unsigned long *dimm_populated, for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_populated[dimm_num] != SDRAM_NONE) { - t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2); - t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2); - t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2); + t_wpc_ns = max(t_wtr_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 36) >> 2); + t_wtr_ns = max(t_wtr_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 37) >> 2); + t_rpc_ns = max(t_rpc_ns, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 38) >> 2); } } @@ -2314,7 +2323,8 @@ static void program_ecc(unsigned long *dimm_populated, for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_populated[dimm_num] != SDRAM_NONE) - ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11)); + ecc = max(ecc, + (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11)); } if (ecc == 0) return; diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c index bd905d1..eef9c5a 100644 --- a/arch/powerpc/cpu/ppc4xx/fdt.c +++ b/arch/powerpc/cpu/ppc4xx/fdt.c @@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; -void __ft_board_setup(void *blob, bd_t *bd) +int __ft_board_setup(void *blob, bd_t *bd) { int rc; int i; @@ -60,8 +60,11 @@ void __ft_board_setup(void *blob, bd_t *bd) printf("Unable to update property EBC mappings, err=%s\n", fdt_strerror(rc)); } + + return 0; } -void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup"))); +int ft_board_setup(void *blob, bd_t *bd) + __attribute__((weak, alias("__ft_board_setup"))); /* * Fixup all PCIe nodes by setting the device_type property diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c index d1e78f6..65a0675 100644 --- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c +++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c @@ -40,8 +40,6 @@ #define readl(a) (*((volatile u32 *)(a))) #define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) -#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - #ifdef DEBUG #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) #else diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 4c1774f..01b0905 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -678,6 +678,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A007798 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_PCI_VER_3_X @@ -768,6 +769,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_FSL_ERRATUM_A008044 #define CONFIG_SYS_FMAN_V3 #define CONFIG_FM_PLAT_CLK_DIV 1 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV @@ -785,6 +787,52 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ +defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) +#define CONFIG_E5500 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 +#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#define CONFIG_SYS_FMAN_V3 +#ifdef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDRC_GEN4 +#endif +#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) +#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) +#define CONFIG_MAX_CPUS 1 +#endif +#define CONFIG_SYS_FSL_NUM_CC_PLL 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } +#define CONFIG_SYS_SDHC_CLOCK 0 +#define CONFIG_SYS_FSL_NUM_LAWS 16 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_FM1_CLK 0 +#define CONFIG_QBMAN_CLK_DIV 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" +#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_SFP_VER_3_0 + #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index 64da4bb..61c6d70 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -26,59 +26,28 @@ static inline bool has_erratum_a006379(void) return false; } #endif +#endif -#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 -static inline bool has_erratum_a006261(void) +#ifdef CONFIG_SYS_FSL_ERRATUM_A007186 +static inline bool has_erratum_a007186(void) { u32 svr = get_svr(); u32 soc = SVR_SOC_VER(svr); switch (soc) { - case SVR_P1010: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); - case SVR_P2041: - case SVR_P2040: - return IS_SVR_REV(svr, 1, 0) || - IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1); - case SVR_P3041: - return IS_SVR_REV(svr, 1, 0) || - IS_SVR_REV(svr, 1, 1) || - IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1); - case SVR_P5010: - case SVR_P5020: - case SVR_P5021: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); case SVR_T4240: + return IS_SVR_REV(svr, 2, 0); case SVR_T4160: - case SVR_T4080: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); - case SVR_T1040: - return IS_SVR_REV(svr, 1, 0); - case SVR_T2080: - case SVR_T2081: - return IS_SVR_REV(svr, 1, 0); - case SVR_P5040: - return IS_SVR_REV(svr, 1, 0); - } - - return false; -} -#endif - -static inline bool has_erratum_a007075(void) -{ - u32 svr = get_svr(); - u32 soc = SVR_SOC_VER(svr); - - switch (soc) { + return IS_SVR_REV(svr, 2, 0); case SVR_B4860: + return IS_SVR_REV(svr, 2, 0); case SVR_B4420: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); - case SVR_P1010: + return IS_SVR_REV(svr, 2, 0); + case SVR_T2081: + case SVR_T2080: return IS_SVR_REV(svr, 1, 0); - case SVR_P4080: - return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0); } + return false; } #endif diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index adfbb66..811f034 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -91,8 +91,8 @@ extern void fdt_fixup_liodn(void *blob); CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) /* reg nodes for DMA start @ 0x300 */ -#define SET_DMA_LIODN(dmaNum, liodn) \ - SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\ +#define SET_DMA_LIODN(dmaNum, compat, liodn) \ + SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\ CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300) #define SET_SDHC_LIODN(sdhcNum, liodn) \ diff --git a/arch/powerpc/include/asm/fsl_memac.h b/arch/powerpc/include/asm/fsl_memac.h index 4640e33..bed2a40 100644 --- a/arch/powerpc/include/asm/fsl_memac.h +++ b/arch/powerpc/include/asm/fsl_memac.h @@ -159,6 +159,7 @@ struct memac { #define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */ #define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */ #define MEMAC_CMD_CFG_RXTX_EN (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN) +#define MEMAC_CMD_CFG_NO_LEN_CHK 0x20000 /* Payload length check disable */ /* HASHTABLE_CTRL - Hashtable control register */ #define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */ @@ -243,6 +244,7 @@ struct memac_mdio_controller { #define MDIO_STAT_PRE (1 << 5) #define MDIO_STAT_ENC (1 << 6) #define MDIO_STAT_HOLD_15_CLK (7 << 2) +#define MDIO_STAT_NEG (1 << 23) #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 74c5d8f..14c6fc3 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -22,7 +22,9 @@ defined(CONFIG_T2080QDS) || \ defined(CONFIG_T2080RDB) || \ defined(CONFIG_T1040QDS) || \ - defined(CONFIG_T104xRDB) + defined(CONFIG_T104xRDB) || \ + defined(CONFIG_PPC_T1023) || \ + defined(CONFIG_PPC_T1024) #define CONFIG_SYS_CPC_REINIT_F #undef CONFIG_SYS_INIT_L3_ADDR #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index f60cb0a..8e0e190 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -71,6 +71,22 @@ enum srds_prtcl { INTERLAKEN, QSGMII_SW1_A, /* Indicates ports on L2 Switch */ QSGMII_SW1_B, + SGMII_2500_FM1_DTSEC1, + SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC3, + SGMII_2500_FM1_DTSEC4, + SGMII_2500_FM1_DTSEC5, + SGMII_2500_FM1_DTSEC6, + SGMII_2500_FM1_DTSEC9, + SGMII_2500_FM1_DTSEC10, + SGMII_2500_FM2_DTSEC1, + SGMII_2500_FM2_DTSEC2, + SGMII_2500_FM2_DTSEC3, + SGMII_2500_FM2_DTSEC4, + SGMII_2500_FM2_DTSEC5, + SGMII_2500_FM2_DTSEC6, + SGMII_2500_FM2_DTSEC9, + SGMII_2500_FM2_DTSEC10, }; enum srds { diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 0264523..ace1d12 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1626,10 +1626,15 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000 #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000 +#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION +#define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000 +#define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000 +#else #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000 #define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000 #define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000 +#endif #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000 @@ -1787,6 +1792,21 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 +#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \ + defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000 +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23 +#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 +#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */ +#define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000 +#define FSL_CORENET_RCWSR13_EC2 0x0c000000 +#define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000 +#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 +#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00 +#define PXCKEN_MASK 0x80000000 +#define PXCK_MASK 0x00FF0000 +#define PXCK_BITS_START 16 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 @@ -2971,6 +2991,8 @@ struct ccsr_sfp_regs { (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET) #define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \ (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET) +#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \ + (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET) #define CONFIG_SYS_FSL_QMAN_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) #define CONFIG_SYS_FSL_BMAN_ADDR \ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 1b98e0f..2ed51b1 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1133,6 +1133,10 @@ #define SVR_T1020 0x852100 #define SVR_T1021 0x852101 #define SVR_T1022 0x852102 +#define SVR_T1024 0x854000 +#define SVR_T1023 0x854100 +#define SVR_T1014 0x854400 +#define SVR_T1013 0x854500 #define SVR_T2080 0x853000 #define SVR_T2081 0x853100 diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 6eaab88..e6d5355 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -820,13 +820,6 @@ void board_init_r(gd_t *id, ulong dest_addr) mac_read_from_eeprom(); #endif -#ifdef CONFIG_HERMES - if ((gd->board_type >> 16) == 2) - bd->bi_ethspeed = gd->board_type & 0xFFFF; - else - bd->bi_ethspeed = 0xFFFF; -#endif - #ifdef CONFIG_CMD_NET /* kept around for legacy kernels only ... ignore the next section */ eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr); @@ -876,11 +869,6 @@ void board_init_r(gd_t *id, ulong dest_addr) misc_init_r(); #endif -#ifdef CONFIG_HERMES - if (bd->bi_ethspeed != 0xFFFF) - hermes_start_lxt980((int) bd->bi_ethspeed); -#endif - #if defined(CONFIG_CMD_KGDB) WATCHDOG_RESET(); puts("KGDB: "); diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 33099a4..ef15e7a 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -126,7 +126,7 @@ void arch_lmb_reserve(struct lmb *lmb) #endif size = min(bootm_size, get_effective_memsize()); - size = min(size, CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE); + size = min(size, (ulong)CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE); if (size < bootm_size) { ulong base = bootmap_base + size; diff --git a/arch/sandbox/Makefile b/arch/sandbox/Makefile new file mode 100644 index 0000000..23fdcdb --- /dev/null +++ b/arch/sandbox/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/sandbox/cpu/start.o + +libs-y += arch/sandbox/cpu/ +libs-y += arch/sandbox/lib/ diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 1c4aa3f..4d5f805 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -367,6 +367,7 @@ int os_dirent_ls(const char *dirname, struct os_dirent_node **headp) done: closedir(dir); + free(fname); return ret; } @@ -385,7 +386,7 @@ const char *os_dirent_get_typename(enum os_dirent_t type) return os_dirent_typename[OS_FILET_UNKNOWN]; } -ssize_t os_get_filesize(const char *fname) +int os_get_filesize(const char *fname, loff_t *size) { struct stat buf; int ret; @@ -393,7 +394,8 @@ ssize_t os_get_filesize(const char *fname) ret = stat(fname, &buf); if (ret) return ret; - return buf.st_size; + *size = buf.st_size; + return 0; } void os_putc(int ch) @@ -427,11 +429,11 @@ int os_read_ram_buf(const char *fname) { struct sandbox_state *state = state_get_current(); int fd, ret; - int size; + loff_t size; - size = os_get_filesize(fname); - if (size < 0) - return -ENOENT; + ret = os_get_filesize(fname, &size); + if (ret < 0) + return ret; if (size != state->ram_size) return -ENOSPC; fd = open(fname, O_RDONLY); diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 53a99ae..42353d8 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -39,7 +39,7 @@ int sandbox_early_getopt_check(void) max_arg_len = 0; for (i = 0; i < num_options; ++i) - max_arg_len = max(strlen(sb_opt[i]->flag), max_arg_len); + max_arg_len = max((int)strlen(sb_opt[i]->flag), max_arg_len); max_noarg_len = max_arg_len + 7; for (i = 0; i < num_options; ++i) { @@ -130,7 +130,8 @@ static int sandbox_cmdline_cb_memory(struct sandbox_state *state, state->write_ram_buf = true; state->ram_buf_fname = arg; - if (os_read_ram_buf(arg)) { + err = os_read_ram_buf(arg); + if (err) { printf("Failed to read RAM buffer\n"); return err; } diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index 59adad6..ba73b7e 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -49,14 +49,14 @@ static int state_ensure_space(int extra_size) static int state_read_file(struct sandbox_state *state, const char *fname) { - int size; + loff_t size; int ret; int fd; - size = os_get_filesize(fname); - if (size < 0) { + ret = os_get_filesize(fname, &size); + if (ret < 0) { printf("Cannot find sandbox state file '%s'\n", fname); - return -ENOENT; + return ret; } state->state_fdt = os_malloc(size); if (!state->state_fdt) { diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 4bf9afc..ff8f5b5 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -1,77 +1,129 @@ menu "SuperH architecture" depends on SH -config SYS_ARCH - default "sh" +config CPU_SH2 + bool + +config CPU_SH2A + bool + select CPU_SH2 + +config CPU_SH3 + bool + +config CPU_SH4 + bool + +config CPU_SH4A + bool + select CPU_SH4 + +config SH_32BIT + bool "32bit mode" + depends on CPU_SH4A + default n + help + SH4A has 2 physical memory maps. This use 32bit mode. + And this is board specific. Please check your board if you + want to use this. choice prompt "Target select" config TARGET_RSK7203 - bool "Support rsk7203" + bool "RSK+ 7203" + select CPU_SH2A config TARGET_RSK7264 - bool "Support rsk7264" + bool "RSK2+SH7264" + select CPU_SH2A config TARGET_RSK7269 - bool "Support rsk7269" + bool "RSK2+SH7269" + select CPU_SH2A config TARGET_MPR2 - bool "Support mpr2" + bool "Magic Panel Release 2 board" + select CPU_SH3 config TARGET_MS7720SE bool "Support ms7720se" + select CPU_SH3 config TARGET_SHMIN - bool "Support shmin" + bool "SHMIN" + select CPU_SH3 config TARGET_ESPT - bool "Support espt" + bool "Data Technology ESPT-GIGA board" + select CPU_SH4 config TARGET_MS7722SE - bool "Support ms7722se" + bool "SolutionEngine 7722" + select CPU_SH4 config TARGET_MS7750SE - bool "Support ms7750se" + bool "SolutionEngine 7750" + select CPU_SH4 config TARGET_AP_SH4A_4A - bool "Support ap_sh4a_4a" + bool "ALPHAPROJECT AP-SH4A-4A" + select CPU_SH4A config TARGET_AP325RXA - bool "Support ap325rxa" + bool "Renesas AP-325RXA" + select CPU_SH4 config TARGET_ECOVEC - bool "Support ecovec" + bool "EcoVec" + select CPU_SH4A config TARGET_MIGOR - bool "Support MigoR" + bool "Migo-R" + select CPU_SH4 config TARGET_R0P7734 bool "Support r0p7734" + select CPU_SH4A config TARGET_R2DPLUS - bool "Support r2dplus" + bool "Renesas R2D-PLUS" + select CPU_SH4 config TARGET_R7780MP - bool "Support r7780mp" + bool "R7780MP board" + select CPU_SH4A config TARGET_SH7752EVB - bool "Support sh7752evb" + bool "SH7752EVB" + select CPU_SH4A config TARGET_SH7753EVB - bool "Support sh7753evb" + bool "SH7753EVB" + select CPU_SH4 config TARGET_SH7757LCR - bool "Support sh7757lcr" + bool "SH7757LCR" + select CPU_SH4A config TARGET_SH7763RDP - bool "Support sh7763rdp" + bool "SH7763RDP" + select CPU_SH4 config TARGET_SH7785LCR - bool "Support sh7785lcr" + bool "SH7785LCR" + select CPU_SH4A endchoice +config SYS_ARCH + default "sh" + +config SYS_CPU + default "sh2" if CPU_SH2 + default "sh3" if CPU_SH3 + default "sh4" if CPU_SH4 + source "board/alphaproject/ap_sh4a_4a/Kconfig" source "board/espt/Kconfig" source "board/mpr2/Kconfig" diff --git a/arch/sh/Makefile b/arch/sh/Makefile new file mode 100644 index 0000000..ca55fac --- /dev/null +++ b/arch/sh/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/sh/cpu/$(CPU)/start.o + +libs-y += arch/sh/cpu/$(CPU)/ +libs-y += arch/sh/lib/ diff --git a/arch/sh/cpu/sh2/config.mk b/arch/sh/cpu/sh2/config.mk index 4904d76..12e202d 100644 --- a/arch/sh/cpu/sh2/config.mk +++ b/arch/sh/cpu/sh2/config.mk @@ -7,11 +7,11 @@ # ENDIANNESS += -EB -ifdef CONFIG_SH2A +ifdef CONFIG_CPU_SH2A PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb else # SH2 PLATFORM_CPPFLAGS += -m3e -mb endif -PLATFORM_CPPFLAGS += -DCONFIG_SH2 $(call cc-option,-mno-fdpic) +PLATFORM_CPPFLAGS += $(call cc-option,-mno-fdpic) PLATFORM_LDFLAGS += $(ENDIANNESS) diff --git a/arch/sh/cpu/sh3/config.mk b/arch/sh/cpu/sh3/config.mk index 24b5c47..dcafd19 100644 --- a/arch/sh/cpu/sh3/config.mk +++ b/arch/sh/cpu/sh3/config.mk @@ -11,4 +11,4 @@ # SPDX-License-Identifier: GPL-2.0+ # # -PLATFORM_CPPFLAGS += -DCONFIG_SH3 -m3 +PLATFORM_CPPFLAGS += -m3 diff --git a/arch/sh/cpu/sh4/config.mk b/arch/sh/cpu/sh4/config.mk index 5773d4f..4fb2dc2 100644 --- a/arch/sh/cpu/sh4/config.mk +++ b/arch/sh/cpu/sh4/config.mk @@ -8,4 +8,4 @@ # SPDX-License-Identifier: GPL-2.0+ # # -PLATFORM_CPPFLAGS += -DCONFIG_SH4 -m4-nofpu +PLATFORM_CPPFLAGS += -m4-nofpu diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h index 0698a37..abaf405 100644 --- a/arch/sh/include/asm/cache.h +++ b/arch/sh/include/asm/cache.h @@ -1,7 +1,7 @@ #ifndef __ASM_SH_CACHE_H #define __ASM_SH_CACHE_H -#if defined(CONFIG_SH4) +#if defined(CONFIG_CPU_SH4) int cache_control(unsigned int cmd); @@ -18,7 +18,7 @@ struct __large_struct { unsigned long buf[100]; }; */ #define ARCH_DMA_MINALIGN 32 -#endif /* CONFIG_SH4 */ +#endif /* CONFIG_CPU_SH4 */ /* * Use the L1 data cache line size value for the minimum DMA buffer alignment diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h index b8677da..b07fe54 100644 --- a/arch/sh/include/asm/processor.h +++ b/arch/sh/include/asm/processor.h @@ -1,10 +1,10 @@ #ifndef _ASM_SH_PROCESSOR_H_ #define _ASM_SH_PROCESSOR_H_ -#if defined(CONFIG_SH2) +#if defined(CONFIG_CPU_SH2) # include <asm/cpu_sh2.h> -#elif defined(CONFIG_SH3) +#elif defined(CONFIG_CPU_SH3) # include <asm/cpu_sh3.h> -#elif defined(CONFIG_SH4) +#elif defined(CONFIG_CPU_SH4) # include <asm/cpu_sh4.h> #endif #endif diff --git a/arch/sh/include/asm/unaligned.h b/arch/sh/include/asm/unaligned.h index 2e0d164..06096ee 100644 --- a/arch/sh/include/asm/unaligned.h +++ b/arch/sh/include/asm/unaligned.h @@ -8,7 +8,7 @@ #include <asm/unaligned-sh4a.h> #else /* Otherwise, SH can't handle unaligned accesses. */ -#include <compiler.h> +#include <linux/compiler.h> #if defined(__BIG_ENDIAN__) #define get_unaligned __get_unaligned_be #define put_unaligned __put_unaligned_be diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index 8a84b24..1304f4e 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -8,7 +8,7 @@ obj-y += board.o obj-$(CONFIG_CMD_BOOTM) += bootm.o -ifeq ($(CONFIG_SH2),y) +ifeq ($(CONFIG_CPU_SH2),y) obj-y += time_sh2.o else obj-y += time.o diff --git a/arch/sparc/Makefile b/arch/sparc/Makefile new file mode 100644 index 0000000..2d4c971 --- /dev/null +++ b/arch/sparc/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/sparc/cpu/$(CPU)/start.o + +libs-y += arch/sparc/cpu/$(CPU)/ +libs-y += arch/sparc/lib/ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 0dba8ac..4f5ce38 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -12,9 +12,230 @@ choice config TARGET_COREBOOT bool "Support coreboot" + help + This target is used for running U-Boot on top of Coreboot. In + this case Coreboot does the early inititalisation, and U-Boot + takes over once the RAM, video and CPU are fully running. + U-Boot is loaded as a fallback payload from Coreboot, in + Coreboot terminology. This method was used for the Chromebook + Pixel when launched. + +config TARGET_CHROMEBOOK_LINK + bool "Support Chromebook link" + help + This is the Chromebook Pixel released in 2013. It uses an Intel + i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of + SDRAM. It has a Panther Point platform controller hub, PCIe + WiFi and Bluetooth. It also includes a 720p webcam, USB SD + reader, microphone and speakers, display port and 32GB SATA + solid state drive. There is a Chrome OS EC connected on LPC, + and it provides a 2560x1700 high resolution touch-enabled LCD + display. + +endchoice + +config RAMBASE + hex + default 0x100000 + +config RAMTOP + hex + default 0x200000 + +config XIP_ROM_SIZE + hex + default 0x10000 + +config CPU_ADDR_BITS + int + default 36 + +config HPET_ADDRESS + hex + default 0xfed00000 if !HPET_ADDRESS_OVERRIDE + +config SMM_TSEG + bool + default n + +config SMM_TSEG_SIZE + hex + +config ROM_SIZE + hex + default 0x800000 + +config HAVE_INTEL_ME + bool "Platform requires Intel Management Engine" + help + Newer higher-end devices have an Intel Management Engine (ME) + which is a very large binary blob (typically 1.5MB) which is + required for the platform to work. This enforces a particular + SPI flash format. You will need to supply the me.bin file in + your board directory. + +config X86_RAMTEST + bool "Perform a simple RAM test after SDRAM initialisation" + help + If there is something wrong with SDRAM then the platform will + often crash within U-Boot or the kernel. This option enables a + very simple RAM test that quickly checks whether the SDRAM seems + to work correctly. It is not exhaustive but can save time by + detecting obvious failures. + +config MARK_GRAPHICS_MEM_WRCOMB + bool "Mark graphics memory as write-combining." + default n + help + The graphics performance may increase if the graphics + memory is set as write-combining cache type. This option + enables marking the graphics memory as write-combining. + +menu "Display" + +config FRAMEBUFFER_SET_VESA_MODE + prompt "Set framebuffer graphics resolution" + bool + help + Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console) + +choice + prompt "framebuffer graphics resolution" + default FRAMEBUFFER_VESA_MODE_117 + depends on FRAMEBUFFER_SET_VESA_MODE + help + This option sets the resolution used for the coreboot framebuffer (and + bootsplash screen). + +config FRAMEBUFFER_VESA_MODE_100 + bool "640x400 256-color" + +config FRAMEBUFFER_VESA_MODE_101 + bool "640x480 256-color" + +config FRAMEBUFFER_VESA_MODE_102 + bool "800x600 16-color" + +config FRAMEBUFFER_VESA_MODE_103 + bool "800x600 256-color" + +config FRAMEBUFFER_VESA_MODE_104 + bool "1024x768 16-color" + +config FRAMEBUFFER_VESA_MODE_105 + bool "1024x7686 256-color" + +config FRAMEBUFFER_VESA_MODE_106 + bool "1280x1024 16-color" + +config FRAMEBUFFER_VESA_MODE_107 + bool "1280x1024 256-color" + +config FRAMEBUFFER_VESA_MODE_108 + bool "80x60 text" + +config FRAMEBUFFER_VESA_MODE_109 + bool "132x25 text" + +config FRAMEBUFFER_VESA_MODE_10A + bool "132x43 text" + +config FRAMEBUFFER_VESA_MODE_10B + bool "132x50 text" + +config FRAMEBUFFER_VESA_MODE_10C + bool "132x60 text" + +config FRAMEBUFFER_VESA_MODE_10D + bool "320x200 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_10E + bool "320x200 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_10F + bool "320x200 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_110 + bool "640x480 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_111 + bool "640x480 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_112 + bool "640x480 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_113 + bool "800x600 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_114 + bool "800x600 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_115 + bool "800x600 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_116 + bool "1024x768 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_117 + bool "1024x768 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_118 + bool "1024x768 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_119 + bool "1280x1024 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_11A + bool "1280x1024 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_11B + bool "1280x1024 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_USER + bool "Manually select VESA mode" endchoice -source "board/chromebook-x86/coreboot/Kconfig" +# Map the config names to an integer (KB). +config FRAMEBUFFER_VESA_MODE + prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER + hex + default 0x100 if FRAMEBUFFER_VESA_MODE_100 + default 0x101 if FRAMEBUFFER_VESA_MODE_101 + default 0x102 if FRAMEBUFFER_VESA_MODE_102 + default 0x103 if FRAMEBUFFER_VESA_MODE_103 + default 0x104 if FRAMEBUFFER_VESA_MODE_104 + default 0x105 if FRAMEBUFFER_VESA_MODE_105 + default 0x106 if FRAMEBUFFER_VESA_MODE_106 + default 0x107 if FRAMEBUFFER_VESA_MODE_107 + default 0x108 if FRAMEBUFFER_VESA_MODE_108 + default 0x109 if FRAMEBUFFER_VESA_MODE_109 + default 0x10A if FRAMEBUFFER_VESA_MODE_10A + default 0x10B if FRAMEBUFFER_VESA_MODE_10B + default 0x10C if FRAMEBUFFER_VESA_MODE_10C + default 0x10D if FRAMEBUFFER_VESA_MODE_10D + default 0x10E if FRAMEBUFFER_VESA_MODE_10E + default 0x10F if FRAMEBUFFER_VESA_MODE_10F + default 0x110 if FRAMEBUFFER_VESA_MODE_110 + default 0x111 if FRAMEBUFFER_VESA_MODE_111 + default 0x112 if FRAMEBUFFER_VESA_MODE_112 + default 0x113 if FRAMEBUFFER_VESA_MODE_113 + default 0x114 if FRAMEBUFFER_VESA_MODE_114 + default 0x115 if FRAMEBUFFER_VESA_MODE_115 + default 0x116 if FRAMEBUFFER_VESA_MODE_116 + default 0x117 if FRAMEBUFFER_VESA_MODE_117 + default 0x118 if FRAMEBUFFER_VESA_MODE_118 + default 0x119 if FRAMEBUFFER_VESA_MODE_119 + default 0x11A if FRAMEBUFFER_VESA_MODE_11A + default 0x11B if FRAMEBUFFER_VESA_MODE_11B + default 0x117 if FRAMEBUFFER_VESA_MODE_USER + +endmenu + +source "arch/x86/cpu/ivybridge/Kconfig" + +source "board/coreboot/coreboot/Kconfig" + +source "board/google/chromebook_link/Kconfig" endmenu diff --git a/arch/x86/Makefile b/arch/x86/Makefile new file mode 100644 index 0000000..36a6018 --- /dev/null +++ b/arch/x86/Makefile @@ -0,0 +1,12 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/x86/cpu/start.o +ifeq ($(CONFIG_SPL_BUILD),y) +head-y += arch/x86/cpu/start16.o +head-y += arch/x86/cpu/resetvec.o +endif + +libs-y += arch/x86/cpu/ +libs-y += arch/x86/lib/ diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 3e7fedb..bb2da46 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -15,7 +15,6 @@ PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \ $(call cc-option, -mpreferred-stack-boundary=2) PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm -PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0 PLATFORM_CPPFLAGS += -march=i386 -m32 # Support generic board on x86 diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 9d38ef7..7f09db5 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -11,3 +11,10 @@ extra-y = start.o obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o obj-y += interrupts.o cpu.o call64.o + +obj-$(CONFIG_SYS_COREBOOT) += coreboot/ +obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ +obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ +obj-y += lapic.o +obj-$(CONFIG_PCI) += pci.o +obj-y += turbo.o diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk index f7b01d3..84aeaf3 100644 --- a/arch/x86/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -12,5 +12,6 @@ PLATFORM_CPPFLAGS += -D__I386__ -Werror # DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! LDPPFLAGS += -DRESET_SEG_START=0xffff0000 LDPPFLAGS += -DRESET_SEG_SIZE=0x10000 -LDPPFLAGS += -DRESET_VEC_LOC=0xfff0 -LDPPFLAGS += -DSTART_16=0xf800 +LDPPFLAGS += -DRESET_VEC_LOC=0xfffffff0 +LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16) +LDPPFLAGS += -DRESET_BASE="CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE)" diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index cd0bf4e..35e6cdd 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -13,10 +13,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_SYS_COREBOOT) += car.o -obj-$(CONFIG_SYS_COREBOOT) += coreboot.o -obj-$(CONFIG_SYS_COREBOOT) += tables.o -obj-$(CONFIG_SYS_COREBOOT) += ipchecksum.o -obj-$(CONFIG_SYS_COREBOOT) += sdram.o -obj-$(CONFIG_SYS_COREBOOT) += timestamp.o +obj-y += car.o +obj-y += coreboot.o +obj-y += tables.o +obj-y += ipchecksum.o +obj-y += sdram.o +obj-y += timestamp.o obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index e24f13a..cfacc05 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -13,25 +13,25 @@ #include <ns16550.h> #include <asm/msr.h> #include <asm/cache.h> +#include <asm/cpu.h> #include <asm/io.h> -#include <asm/arch-coreboot/tables.h> -#include <asm/arch-coreboot/sysinfo.h> +#include <asm/arch/tables.h> +#include <asm/arch/sysinfo.h> #include <asm/arch/timestamp.h> DECLARE_GLOBAL_DATA_PTR; -/* - * Miscellaneous platform dependent initializations - */ -int cpu_init_f(void) +int arch_cpu_init(void) { int ret = get_coreboot_info(&lib_sysinfo); - if (ret != 0) + if (ret != 0) { printf("Failed to parse coreboot tables.\n"); + return ret; + } timestamp_init(); - return ret; + return x86_cpu_init_f(); } int board_early_init_f(void) @@ -39,38 +39,9 @@ int board_early_init_f(void) return 0; } -int board_early_init_r(void) -{ - /* CPU Speed to 100MHz */ - gd->cpu_clk = 100000000; - - /* Crystal is 33.000MHz */ - gd->bus_clk = 33000000; - - return 0; -} - -void show_boot_progress(int val) +int print_cpuinfo(void) { -#if MIN_PORT80_KCLOCKS_DELAY - /* - * Scale the time counter reading to avoid using 64 bit arithmetics. - * Can't use get_timer() here becuase it could be not yet - * initialized or even implemented. - */ - if (!gd->arch.tsc_prev) { - gd->arch.tsc_base_kclocks = rdtsc() / 1000; - gd->arch.tsc_prev = 0; - } else { - uint32_t now; - - do { - now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; - } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); - gd->arch.tsc_prev = now; - } -#endif - outb(val, 0x80); + return default_print_cpuinfo(); } int last_stage_init(void) @@ -98,7 +69,7 @@ int board_eth_init(bd_t *bis) #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) -int board_final_cleanup(void) +void board_final_cleanup(void) { /* Un-cache the ROM so the kernel has one * more MTRR available. @@ -120,8 +91,6 @@ int board_final_cleanup(void) /* Issue SMI to Coreboot to lock down ME and registers */ printf("Finalizing Coreboot\n"); outb(0xcb, 0xb2); - - return 0; } void panic_puts(const char *str) diff --git a/arch/x86/cpu/coreboot/ipchecksum.c b/arch/x86/cpu/coreboot/ipchecksum.c index 57733d8..3340872 100644 --- a/arch/x86/cpu/coreboot/ipchecksum.c +++ b/arch/x86/cpu/coreboot/ipchecksum.c @@ -29,8 +29,9 @@ * SUCH DAMAGE. */ -#include <compiler.h> -#include <asm/arch-coreboot/ipchecksum.h> +#include <linux/types.h> +#include <linux/compiler.h> +#include <asm/arch/ipchecksum.h> unsigned short ipchksum(const void *vptr, unsigned long nbytes) { diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index 33f16a3..6a3dd93 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -13,14 +13,12 @@ #include <pci.h> #include <asm/pci.h> -static struct pci_controller coreboot_hose; - static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *table) { u8 secondary; hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); - hose->last_busno = max(hose->last_busno, secondary); + hose->last_busno = max(hose->last_busno, (int)secondary); pci_hose_scan_bus(hose, secondary); } @@ -31,19 +29,13 @@ static struct pci_config_table pci_coreboot_config_table[] = { {} }; -void pci_init_board(void) +void board_pci_setup_hose(struct pci_controller *hose) { - coreboot_hose.config_table = pci_coreboot_config_table; - coreboot_hose.first_busno = 0; - coreboot_hose.last_busno = 0; - - pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff, - PCI_REGION_MEM); - coreboot_hose.region_count = 1; - - pci_setup_type1(&coreboot_hose); - - pci_register_hose(&coreboot_hose); + hose->config_table = pci_coreboot_config_table; + hose->first_busno = 0; + hose->last_busno = 0; - pci_hose_scan(&coreboot_hose); + pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff, + PCI_REGION_MEM); + hose->region_count = 1; } diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index 959feaa..e98a230 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -11,8 +11,10 @@ #include <asm/e820.h> #include <asm/u-boot-x86.h> #include <asm/global_data.h> +#include <asm/init_helpers.h> #include <asm/processor.h> #include <asm/sections.h> +#include <asm/zimage.h> #include <asm/arch/sysinfo.h> #include <asm/arch/tables.h> @@ -22,7 +24,7 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) { int i; - unsigned num_entries = min(lib_sysinfo.n_memranges, max_entries); + unsigned num_entries = min((unsigned)lib_sysinfo.n_memranges, max_entries); if (num_entries < lib_sysinfo.n_memranges) { printf("Warning: Limiting e820 map to %d entries.\n", num_entries); @@ -79,7 +81,7 @@ ulong board_get_usable_ram_top(ulong total_size) return (ulong)dest_addr; } -int dram_init_f(void) +int dram_init(void) { int i; phys_size_t ram_size = 0; @@ -94,10 +96,11 @@ int dram_init_f(void) gd->ram_size = ram_size; if (ram_size == 0) return -1; - return 0; + + return calculate_relocation_address(); } -int dram_init_banksize(void) +void dram_init_banksize(void) { int i, j; @@ -114,10 +117,4 @@ int dram_init_banksize(void) } } } - return 0; -} - -int dram_init(void) -{ - return dram_init_banksize(); } diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c index 0d91adc..92b7528 100644 --- a/arch/x86/cpu/coreboot/tables.c +++ b/arch/x86/cpu/coreboot/tables.c @@ -8,9 +8,9 @@ */ #include <common.h> -#include <asm/arch-coreboot/ipchecksum.h> -#include <asm/arch-coreboot/sysinfo.h> -#include <asm/arch-coreboot/tables.h> +#include <asm/arch/ipchecksum.h> +#include <asm/arch/sysinfo.h> +#include <asm/arch/tables.h> /* * This needs to be in the .data section so that it's copied over during diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 2e25253..30e5069 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -13,6 +13,9 @@ * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Alex Zuepke <azu@sysgo.de> * + * Part of this file is adapted from coreboot + * src/arch/x86/lib/cpu.c + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -22,11 +25,14 @@ #include <malloc.h> #include <asm/control_regs.h> #include <asm/cpu.h> +#include <asm/post.h> #include <asm/processor.h> #include <asm/processor-flags.h> #include <asm/interrupt.h> #include <linux/compiler.h> +DECLARE_GLOBAL_DATA_PTR; + /* * Constructor for a conventional segment GDT (or LDT) entry * This is a macro so it can be used in initialisers @@ -43,6 +49,52 @@ struct gdt_ptr { u32 ptr; } __packed; +struct cpu_device_id { + unsigned vendor; + unsigned device; +}; + +struct cpuinfo_x86 { + uint8_t x86; /* CPU family */ + uint8_t x86_vendor; /* CPU vendor */ + uint8_t x86_model; + uint8_t x86_mask; +}; + +/* + * List of cpu vendor strings along with their normalized + * id values. + */ +static struct { + int vendor; + const char *name; +} x86_vendors[] = { + { X86_VENDOR_INTEL, "GenuineIntel", }, + { X86_VENDOR_CYRIX, "CyrixInstead", }, + { X86_VENDOR_AMD, "AuthenticAMD", }, + { X86_VENDOR_UMC, "UMC UMC UMC ", }, + { X86_VENDOR_NEXGEN, "NexGenDriven", }, + { X86_VENDOR_CENTAUR, "CentaurHauls", }, + { X86_VENDOR_RISE, "RiseRiseRise", }, + { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, + { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, + { X86_VENDOR_NSC, "Geode by NSC", }, + { X86_VENDOR_SIS, "SiS SiS SiS ", }, +}; + +static const char *const x86_vendor_name[] = { + [X86_VENDOR_INTEL] = "Intel", + [X86_VENDOR_CYRIX] = "Cyrix", + [X86_VENDOR_AMD] = "AMD", + [X86_VENDOR_UMC] = "UMC", + [X86_VENDOR_NEXGEN] = "NexGen", + [X86_VENDOR_CENTAUR] = "Centaur", + [X86_VENDOR_RISE] = "Rise", + [X86_VENDOR_TRANSMETA] = "Transmeta", + [X86_VENDOR_NSC] = "NSC", + [X86_VENDOR_SIS] = "SiS", +}; + static void load_ds(u32 segment) { asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); @@ -72,7 +124,7 @@ static void load_gdt(const u64 *boot_gdt, u16 num_entries) { struct gdt_ptr gdt; - gdt.len = (num_entries * 8) - 1; + gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; gdt.ptr = (u32)boot_gdt; asm volatile("lgdtl %0\n" : : "m" (gdt)); @@ -92,10 +144,13 @@ void setup_gdt(gd_t *id, u64 *gdt_addr) (ulong)&id->arch.gd_addr, 0xfffff); /* 16-bit CS: code, read/execute, 64 kB, base 0 */ - gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff); + gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); /* 16-bit DS: data, read/write, 64 kB, base 0 */ - gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff); + gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); + + gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); + gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); load_ds(X86_GDT_ENTRY_32BIT_DS); @@ -115,6 +170,129 @@ int __weak x86_cleanup_before_linux(void) return 0; } +/* + * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected + * by the fact that they preserve the flags across the division of 5/2. + * PII and PPro exhibit this behavior too, but they have cpuid available. + */ + +/* + * Perform the Cyrix 5/2 test. A Cyrix won't change + * the flags, while other 486 chips will. + */ +static inline int test_cyrix_52div(void) +{ + unsigned int test; + + __asm__ __volatile__( + "sahf\n\t" /* clear flags (%eax = 0x0005) */ + "div %b2\n\t" /* divide 5 by 2 */ + "lahf" /* store flags into %ah */ + : "=a" (test) + : "0" (5), "q" (2) + : "cc"); + + /* AH is 0x02 on Cyrix after the divide.. */ + return (unsigned char) (test >> 8) == 0x02; +} + +/* + * Detect a NexGen CPU running without BIOS hypercode new enough + * to have CPUID. (Thanks to Herbert Oppmann) + */ + +static int deep_magic_nexgen_probe(void) +{ + int ret; + + __asm__ __volatile__ ( + " movw $0x5555, %%ax\n" + " xorw %%dx,%%dx\n" + " movw $2, %%cx\n" + " divw %%cx\n" + " movl $0, %%eax\n" + " jnz 1f\n" + " movl $1, %%eax\n" + "1:\n" + : "=a" (ret) : : "cx", "dx"); + return ret; +} + +static bool has_cpuid(void) +{ + return flag_is_changeable_p(X86_EFLAGS_ID); +} + +static int build_vendor_name(char *vendor_name) +{ + struct cpuid_result result; + result = cpuid(0x00000000); + unsigned int *name_as_ints = (unsigned int *)vendor_name; + + name_as_ints[0] = result.ebx; + name_as_ints[1] = result.edx; + name_as_ints[2] = result.ecx; + + return result.eax; +} + +static void identify_cpu(struct cpu_device_id *cpu) +{ + char vendor_name[16]; + int i; + + vendor_name[0] = '\0'; /* Unset */ + cpu->device = 0; /* fix gcc 4.4.4 warning */ + + /* Find the id and vendor_name */ + if (!has_cpuid()) { + /* Its a 486 if we can modify the AC flag */ + if (flag_is_changeable_p(X86_EFLAGS_AC)) + cpu->device = 0x00000400; /* 486 */ + else + cpu->device = 0x00000300; /* 386 */ + if ((cpu->device == 0x00000400) && test_cyrix_52div()) { + memcpy(vendor_name, "CyrixInstead", 13); + /* If we ever care we can enable cpuid here */ + } + /* Detect NexGen with old hypercode */ + else if (deep_magic_nexgen_probe()) + memcpy(vendor_name, "NexGenDriven", 13); + } + if (has_cpuid()) { + int cpuid_level; + + cpuid_level = build_vendor_name(vendor_name); + vendor_name[12] = '\0'; + + /* Intel-defined flags: level 0x00000001 */ + if (cpuid_level >= 0x00000001) { + cpu->device = cpuid_eax(0x00000001); + } else { + /* Have CPUID level 0 only unheard of */ + cpu->device = 0x00000400; + } + } + cpu->vendor = X86_VENDOR_UNKNOWN; + for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { + if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { + cpu->vendor = x86_vendors[i].vendor; + break; + } + } +} + +static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) +{ + c->x86 = (tfms >> 8) & 0xf; + c->x86_model = (tfms >> 4) & 0xf; + c->x86_mask = tfms & 0xf; + if (c->x86 == 0xf) + c->x86 += (tfms >> 20) & 0xff; + if (c->x86 >= 0x6) + c->x86_model += ((tfms >> 16) & 0xF) << 4; +} + int x86_cpu_init_f(void) { const u32 em_rst = ~X86_CR0_EM; @@ -128,17 +306,22 @@ int x86_cpu_init_f(void) "movl %%eax, %%cr0\n" \ : : "i" (em_rst), "i" (mp_ne_set) : "eax"); - return 0; -} -int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f"))); + /* identify CPU via cpuid and store the decoded info into gd->arch */ + if (has_cpuid()) { + struct cpu_device_id cpu; + struct cpuinfo_x86 c; + + identify_cpu(&cpu); + get_fms(&c, cpu.device); + gd->arch.x86 = c.x86; + gd->arch.x86_vendor = cpu.vendor; + gd->arch.x86_model = c.x86_model; + gd->arch.x86_mask = c.x86_mask; + gd->arch.x86_device = cpu.device; + } -int x86_cpu_init_r(void) -{ - /* Initialize core interrupt and exception functionality of CPU */ - cpu_init_interrupts(); return 0; } -int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); void x86_enable_caches(void) { @@ -198,14 +381,13 @@ asm(".globl generate_gpf\n" "generate_gpf:\n" "ljmp $0x70, $0x47114711\n"); -void __reset_cpu(ulong addr) +__weak void reset_cpu(ulong addr) { printf("Resetting using x86 Triple Fault\n"); set_vector(13, generate_gpf); /* general protection fault handler */ set_vector(8, generate_gpf); /* double fault handler */ generate_gpf(); /* start the show */ } -void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu"))); int dcache_status(void) { @@ -279,66 +461,63 @@ void cpu_disable_paging_pae(void) : "eax"); } -static bool has_cpuid(void) +static bool can_detect_long_mode(void) { - unsigned long flag; - - asm volatile("pushf\n" \ - "pop %%eax\n" - "mov %%eax, %%ecx\n" /* ecx = flags */ - "xor %1, %%eax\n" - "push %%eax\n" - "popf\n" /* flags ^= $2 */ - "pushf\n" - "pop %%eax\n" /* eax = flags */ - "push %%ecx\n" - "popf\n" /* flags = ecx */ - "xor %%ecx, %%eax\n" - "mov %%eax, %0" - : "=r" (flag) - : "i" (1 << 21) - : "eax", "ecx", "memory"); + return cpuid_eax(0x80000000) > 0x80000000UL; +} - return flag != 0; +static bool has_long_mode(void) +{ + return cpuid_edx(0x80000001) & (1 << 29) ? true : false; } -static bool can_detect_long_mode(void) +int cpu_has_64bit(void) { - unsigned long flag; + return has_cpuid() && can_detect_long_mode() && + has_long_mode(); +} - asm volatile("mov $0x80000000, %%eax\n" - "cpuid\n" - "mov %%eax, %0" - : "=r" (flag) - : - : "eax", "ebx", "ecx", "edx", "memory"); +const char *cpu_vendor_name(int vendor) +{ + const char *name; + name = "<invalid cpu vendor>"; + if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && + (x86_vendor_name[vendor] != 0)) + name = x86_vendor_name[vendor]; - return flag > 0x80000000UL; + return name; } -static bool has_long_mode(void) +char *cpu_get_name(char *name) { - unsigned long flag; + unsigned int *name_as_ints = (unsigned int *)name; + struct cpuid_result regs; + char *ptr; + int i; - asm volatile("mov $0x80000001, %%eax\n" - "cpuid\n" - "mov %%edx, %0" - : "=r" (flag) - : - : "eax", "ebx", "ecx", "edx", "memory"); + /* This bit adds up to 48 bytes */ + for (i = 0; i < 3; i++) { + regs = cpuid(0x80000002 + i); + name_as_ints[i * 4 + 0] = regs.eax; + name_as_ints[i * 4 + 1] = regs.ebx; + name_as_ints[i * 4 + 2] = regs.ecx; + name_as_ints[i * 4 + 3] = regs.edx; + } + name[CPU_MAX_NAME_LEN - 1] = '\0'; - return flag & (1 << 29) ? true : false; -} + /* Skip leading spaces. */ + ptr = name; + while (*ptr == ' ') + ptr++; -int cpu_has_64bit(void) -{ - return has_cpuid() && can_detect_long_mode() && - has_long_mode(); + return ptr; } -int print_cpuinfo(void) +int default_print_cpuinfo(void) { - printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86"); + printf("CPU: %s, vendor %s, device %xh\n", + cpu_has_64bit() ? "x86_64" : "x86", + cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); return 0; } @@ -384,3 +563,26 @@ int cpu_jump_to_64bit(ulong setup_base, ulong target) return -EFAULT; } + +void show_boot_progress(int val) +{ +#if MIN_PORT80_KCLOCKS_DELAY + /* + * Scale the time counter reading to avoid using 64 bit arithmetics. + * Can't use get_timer() here becuase it could be not yet + * initialized or even implemented. + */ + if (!gd->arch.tsc_prev) { + gd->arch.tsc_base_kclocks = rdtsc() / 1000; + gd->arch.tsc_prev = 0; + } else { + uint32_t now; + + do { + now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; + } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); + gd->arch.tsc_prev = now; + } +#endif + outb(val, POST_PORT); +} diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index 6f3d85f..a21d2a6 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -20,6 +20,7 @@ #include <linux/compiler.h> #include <asm/msr.h> #include <asm/u-boot-x86.h> +#include <asm/i8259.h> DECLARE_GLOBAL_DATA_PTR; @@ -31,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; "pushl $"#x"\n" \ "jmp irq_common_entry\n" -void dump_regs(struct irq_regs *regs) +static void dump_regs(struct irq_regs *regs) { unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; unsigned long d0, d1, d2, d3, d6, d7; @@ -128,9 +129,6 @@ int cpu_init_interrupts(void) int irq_entry_size = irq_1 - irq_0; void *irq_entry = (void *)irq_0; - /* Just in case... */ - disable_interrupts(); - /* Setup the IDT */ for (i = 0; i < 256; i++) { idt[i].access = 0x8e; @@ -146,9 +144,6 @@ int cpu_init_interrupts(void) load_idt(&idt_ptr); - /* It is now safe to enable interrupts */ - enable_interrupts(); - return 0; } @@ -172,6 +167,25 @@ int disable_interrupts(void) return flags & X86_EFLAGS_IF; } +int interrupt_init(void) +{ + /* Just in case... */ + disable_interrupts(); + +#ifdef CONFIG_SYS_PCAT_INTERRUPTS + /* Initialize the master/slave i8259 pic */ + i8259_init(); +#endif + + /* Initialize core interrupt and exception functionality of CPU */ + cpu_init_interrupts(); + + /* It is now safe to enable interrupts */ + enable_interrupts(); + + return 0; +} + /* IRQ Low-Level Service Routine */ void irq_llsr(struct irq_regs *regs) { @@ -603,31 +617,3 @@ asm(".globl irq_common_entry\n" \ DECLARE_INTERRUPT(253) \ DECLARE_INTERRUPT(254) \ DECLARE_INTERRUPT(255)); - -#if defined(CONFIG_INTEL_CORE_ARCH) -/* - * Get the number of CPU time counter ticks since it was read first time after - * restart. This yields a free running counter guaranteed to take almost 6 - * years to wrap around even at 100GHz clock rate. - */ -u64 get_ticks(void) -{ - u64 now_tick = rdtsc(); - - if (!gd->arch.tsc_base) - gd->arch.tsc_base = now_tick; - - return now_tick - gd->arch.tsc_base; -} - -#define PLATFORM_INFO_MSR 0xce - -unsigned long get_tbclk(void) -{ - u32 ratio; - u64 platform_info = native_read_msr(PLATFORM_INFO_MSR); - - ratio = (platform_info >> 8) & 0xff; - return 100 * 1000 * 1000 * ratio; /* 100MHz times Max Non Turbo ratio */ -} -#endif diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig new file mode 100644 index 0000000..afca957 --- /dev/null +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -0,0 +1,172 @@ +# +# From Coreboot src/northbridge/intel/sandybridge/Kconfig +# +# Copyright (C) 2010 Google Inc. +# +# SPDX-License-Identifier: GPL-2.0 + + +config NORTHBRIDGE_INTEL_SANDYBRIDGE + bool + select CACHE_MRC_BIN + select CPU_INTEL_MODEL_206AX + +config NORTHBRIDGE_INTEL_IVYBRIDGE + bool + select CACHE_MRC_BIN + select CPU_INTEL_MODEL_306AX + +if NORTHBRIDGE_INTEL_SANDYBRIDGE + +config VGA_BIOS_ID + string + default "8086,0106" + +config CACHE_MRC_SIZE_KB + int + default 256 + +config MRC_CACHE_BASE + hex + default 0xff800000 + +config MRC_CACHE_LOCATION + hex + depends on !CHROMEOS + default 0x1ec000 + +config MRC_CACHE_SIZE + hex + depends on !CHROMEOS + default 0x10000 + +config DCACHE_RAM_BASE + hex + default 0xff7f0000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + +endif + +if NORTHBRIDGE_INTEL_IVYBRIDGE + +config VGA_BIOS_ID + string + default "8086,0166" + +config EXTERNAL_MRC_BLOB + bool + default n + +config CACHE_MRC_SIZE_KB + int + default 512 + +config MRC_CACHE_BASE + hex + default 0xff800000 + +config MRC_CACHE_LOCATION + hex + depends on !CHROMEOS + default 0x370000 + +config MRC_CACHE_SIZE + hex + depends on !CHROMEOS + default 0x10000 + +config DCACHE_RAM_BASE + hex + default 0xff7e0000 + +config DCACHE_RAM_SIZE + hex + default 0x20000 + +endif + +if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE + +config HAVE_MRC + bool "Add a System Agent binary" + help + Select this option to add a System Agent binary to + the resulting U-Boot image. MRC stands for Memory Reference Code. + It is a binary blob which U-Boot uses to set up SDRAM. + + Note: Without this binary U-Boot will not be able to set up its + SDRAM so will not boot. + +config DCACHE_RAM_MRC_VAR_SIZE + hex + default 0x4000 + help + This is the amount of CAR (Cache as RAM) reserved for use by the + memory reference code. This should be set to 16KB (0x4000 hex) + so that MRC has enough space to run. + +config MRC_FILE + string "Intel System Agent path and filename" + depends on HAVE_MRC + default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE + default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE + help + The path and filename of the file to use as System Agent + binary. + +config CPU_SPECIFIC_OPTIONS + def_bool y + select SMM_TSEG + select ARCH_BOOTBLOCK_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select SMP + select SSE2 + select UDELAY_LAPIC + select CPU_MICROCODE_IN_CBFS + select TSC_SYNC_MFENCE + select HAVE_INTEL_ME + select X86_RAMTEST + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config ENABLE_VMX + bool "Enable VMX for virtualization" + default n + help + Virtual Machine Extensions are provided in many x86 CPUs. These + provide various facilities for allowing a host OS to provide an + environment where potentially several guest OSes have only + limited access to the underlying hardware. This is achieved + without resorting to software trapping and/or instruction set + emulation (which would be very slow). + + Intel's implementation of this is called VT-x. This option enables + VT-x this so that the OS that is booted by U-Boot can make use of + these facilities. If this option is not enabled, then the host OS + will be unable to support virtualisation, or it will run very + slowly. + +endif + +config CPU_INTEL_SOCKET_RPGA989 + bool + +if CPU_INTEL_SOCKET_RPGA989 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select MMX + select SSE + select CACHE_AS_RAM + +config CACHE_MRC_BIN + bool + default n + +endif diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile new file mode 100644 index 0000000..0c7efae --- /dev/null +++ b/arch/x86/cpu/ivybridge/Makefile @@ -0,0 +1,24 @@ +# +# Copyright (c) 2014 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += bd82x6x.o +obj-y += car.o +obj-y += cpu.o +obj-y += early_init.o +obj-y += early_me.o +obj-y += gma.o +obj-y += lpc.o +obj-y += me_status.o +obj-y += model_206ax.o +obj-y += microcode_intel.o +obj-y += northbridge.o +obj-y += pch.o +obj-y += pci.o +obj-y += report_platform.o +obj-y += sata.o +obj-y += sdram.o +obj-y += usb_ehci.o +obj-y += usb_xhci.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c new file mode 100644 index 0000000..65a17d3 --- /dev/null +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <malloc.h> +#include <asm/lapic.h> +#include <asm/pci.h> +#include <asm/arch/bd82x6x.h> +#include <asm/arch/model_206ax.h> +#include <asm/arch/pch.h> +#include <asm/arch/sandybridge.h> + +void bd82x6x_pci_init(pci_dev_t dev) +{ + u16 reg16; + u8 reg8; + + debug("bd82x6x PCI init.\n"); + /* Enable Bus Master */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* This device has no interrupt */ + pci_write_config8(dev, INTR, 0xff); + + /* disable parity error response and SERR */ + reg16 = pci_read_config16(dev, BCTRL); + reg16 &= ~(1 << 0); + reg16 &= ~(1 << 1); + pci_write_config16(dev, BCTRL, reg16); + + /* Master Latency Count must be set to 0x04! */ + reg8 = pci_read_config8(dev, SMLT); + reg8 &= 0x07; + reg8 |= (0x04 << 3); + pci_write_config8(dev, SMLT, reg8); + + /* Will this improve throughput of bus masters? */ + pci_write_config8(dev, PCI_MIN_GNT, 0x06); + + /* Clear errors in status registers */ + reg16 = pci_read_config16(dev, PSTS); + /* reg16 |= 0xf900; */ + pci_write_config16(dev, PSTS, reg16); + + reg16 = pci_read_config16(dev, SECSTS); + /* reg16 |= 0xf900; */ + pci_write_config16(dev, SECSTS, reg16); +} + +#define PCI_BRIDGE_UPDATE_COMMAND +void bd82x6x_pci_dev_enable_resources(pci_dev_t dev) +{ + uint16_t command; + + command = pci_read_config16(dev, PCI_COMMAND); + command |= PCI_COMMAND_IO; +#ifdef PCI_BRIDGE_UPDATE_COMMAND + /* + * If we write to PCI_COMMAND, on some systems this will cause the + * ROM and APICs to become invisible. + */ + debug("%x cmd <- %02x\n", dev, command); + pci_write_config16(dev, PCI_COMMAND, command); +#else + printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); +#endif +} + +void bd82x6x_pci_bus_enable_resources(pci_dev_t dev) +{ + uint16_t ctrl; + + ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + ctrl |= PCI_COMMAND_IO; + ctrl |= PCI_BRIDGE_CTL_VGA; + debug("%x bridge ctrl <- %04x\n", dev, ctrl); + pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); + + bd82x6x_pci_dev_enable_resources(dev); +} + +int bd82x6x_init_pci_devices(void) +{ + const void *blob = gd->fdt_blob; + struct pci_controller *hose; + struct x86_cpu_priv *cpu; + int sata_node, gma_node; + int ret; + + hose = pci_bus_to_hose(0); + lpc_enable(PCH_LPC_DEV); + lpc_init(hose, PCH_LPC_DEV); + sata_node = fdtdec_next_compatible(blob, 0, + COMPAT_INTEL_PANTHERPOINT_AHCI); + if (sata_node < 0) { + debug("%s: Cannot find SATA node\n", __func__); + return -EINVAL; + } + bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node); + bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); + bd82x6x_usb_ehci_init(PCH_EHCI2_DEV); + + cpu = calloc(1, sizeof(*cpu)); + if (!cpu) + return -ENOMEM; + model_206ax_init(cpu); + + gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA); + if (gma_node < 0) { + debug("%s: Cannot find GMA node\n", __func__); + return -EINVAL; + } + ret = gma_func0_init(PCH_VIDEO_DEV, pci_bus_to_hose(0), blob, + gma_node); + if (ret) + return ret; + + return 0; +} + +int bd82x6x_init(void) +{ + const void *blob = gd->fdt_blob; + int sata_node; + + sata_node = fdtdec_next_compatible(blob, 0, + COMPAT_INTEL_PANTHERPOINT_AHCI); + if (sata_node < 0) { + debug("%s: Cannot find SATA node\n", __func__); + return -EINVAL; + } + + bd82x6x_pci_init(PCH_DEV); + bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node); + northbridge_enable(PCH_DEV); + northbridge_init(PCH_DEV); + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S new file mode 100644 index 0000000..dca68e4 --- /dev/null +++ b/arch/x86/cpu/ivybridge/car.S @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> + * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/mtrr.h> +#include <asm/post.h> +#include <asm/processor-flags.h> + +#define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) +#define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + +/* Cache 4GB - MRC_SIZE_KB for MRC */ +#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) +#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) + +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) + +#define NOEVICTMOD_MSR 0x2e0 + + /* + * Note: ebp must not be touched in this code as it holds the BIST + * value (built-in self test). We preserve this value until it can + * be written to global_data when CAR is ready for use. + */ +.globl car_init +car_init: + post_code(POST_CAR_START) + + /* Send INIT IPI to all excluding ourself */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + post_code(POST_CAR_SIPI) + /* Zero out all fixed range and variable range MTRRs */ + movl $mtrr_table, %esi + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + post_code(POST_CAR_MTRR) + /* Configure the default memory type to uncacheable */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + post_code(POST_CAR_UNCACHEABLE) + /* Set Cache-as-RAM base address */ + movl $(MTRR_PHYS_BASE_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + post_code(POST_CAR_BASE_ADDRESS) + /* Set Cache-as-RAM mask */ + movl $(MTRR_PHYS_MASK_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + post_code(POST_CAR_MASK) + + /* Enable MTRR */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + /* Enable cache (CR0.CD = 0, CR0.NW = 0) */ + movl %cr0, %eax + andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax + invd + movl %eax, %cr0 + + /* enable the 'no eviction' mode */ + movl $NOEVICTMOD_MSR, %ecx + rdmsr + orl $1, %eax + andl $~2, %eax + wrmsr + + /* Clear the cache memory region. This will also fill up the cache */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + xorl %eax, %eax + rep stosl + + /* enable the 'no eviction run' state */ + movl $NOEVICTMOD_MSR, %ecx + rdmsr + orl $3, %eax + wrmsr + + post_code(POST_CAR_FILL) + /* Enable Cache-as-RAM mode by disabling cache */ + movl %cr0, %eax + orl $X86_CR0_CD, %eax + movl %eax, %cr0 + + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRR_PHYS_BASE_MSR(1), %ecx + xorl %edx, %edx + movl $car_init_ret, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRR_PHYS_MASK_MSR(1), %ecx + movl $CPU_PHYSMASK_HI, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr + + post_code(POST_CAR_ROM_CACHE) +#ifdef CONFIG_CACHE_MRC_BIN + /* Enable caching for ram init code to run faster */ + movl $MTRR_PHYS_BASE_MSR(2), %ecx + movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRR_PHYS_MASK_MSR(2), %ecx + movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr +#endif + + post_code(POST_CAR_MRC_CACHE) + /* Enable cache */ + movl %cr0, %eax + andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax + movl %eax, %cr0 + + post_code(POST_CAR_CPU_CACHE) + + /* All CPUs need to be in Wait for SIPI state */ +wait_for_sipi: + movl (%esi), %eax + bt $12, %eax + jc wait_for_sipi + + /* return */ + jmp car_init_ret + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F + .word 0x210, 0x211, 0x212, 0x213 +mtrr_table_end: diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c new file mode 100644 index 0000000..60976db --- /dev/null +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -0,0 +1,357 @@ +/* + * Copyright (c) 2014 Google, Inc + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * Some portions from coreboot src/mainboard/google/link/romstage.c + * and src/cpu/intel/model_206ax/bootblock.c + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <asm/cpu.h> +#include <asm/io.h> +#include <asm/lapic.h> +#include <asm/msr.h> +#include <asm/mtrr.h> +#include <asm/pci.h> +#include <asm/post.h> +#include <asm/processor.h> +#include <asm/arch/model_206ax.h> +#include <asm/arch/microcode.h> +#include <asm/arch/pch.h> +#include <asm/arch/sandybridge.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev) +{ + /* Enable port 80 POST on LPC */ + pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); + clrbits_le32(RCB_REG(GCS), 4); +} + +/* + * Enable Prefetching and Caching. + */ +static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev) +{ + u8 reg8; + + pci_hose_read_config_byte(hose, dev, 0xdc, ®8); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_hose_write_config_byte(hose, dev, 0xdc, reg8); +} + +static void set_var_mtrr( + unsigned reg, unsigned base, unsigned size, unsigned type) + +{ + /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ + /* FIXME: It only support 4G less range */ + wrmsr(MTRRphysBase_MSR(reg), base | type, 0); + wrmsr(MTRRphysMask_MSR(reg), ~(size - 1) | MTRRphysMaskValid, + (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1); +} + +static void enable_rom_caching(void) +{ + disable_caches(); + set_var_mtrr(1, 0xffc00000, 4 << 20, MTRR_TYPE_WRPROT); + enable_caches(); + + /* Enable Variable MTRRs */ + wrmsr(MTRRdefType_MSR, 0x800, 0); +} + +static int set_flex_ratio_to_tdp_nominal(void) +{ + msr_t flex_ratio, msr; + u8 nominal_ratio; + + /* Minimum CPU revision for configurable TDP support */ + if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) + return -EINVAL; + + /* Check for Flex Ratio support */ + flex_ratio = msr_read(MSR_FLEX_RATIO); + if (!(flex_ratio.lo & FLEX_RATIO_EN)) + return -EINVAL; + + /* Check for >0 configurable TDPs */ + msr = msr_read(MSR_PLATFORM_INFO); + if (((msr.hi >> 1) & 3) == 0) + return -EINVAL; + + /* Use nominal TDP ratio for flex ratio */ + msr = msr_read(MSR_CONFIG_TDP_NOMINAL); + nominal_ratio = msr.lo & 0xff; + + /* See if flex ratio is already set to nominal TDP ratio */ + if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) + return 0; + + /* Set flex ratio to nominal TDP ratio */ + flex_ratio.lo &= ~0xff00; + flex_ratio.lo |= nominal_ratio << 8; + flex_ratio.lo |= FLEX_RATIO_LOCK; + msr_write(MSR_FLEX_RATIO, flex_ratio); + + /* Set flex ratio in soft reset data register bits 11:6 */ + clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6, + (nominal_ratio & 0x3f) << 6); + + /* Set soft reset control to use register value */ + setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1); + + /* Issue warm reset, will be "CPU only" due to soft reset data */ + outb(0x0, PORT_RESET); + outb(0x6, PORT_RESET); + cpu_hlt(); + + /* Not reached */ + return -EINVAL; +} + +static void set_spi_speed(void) +{ + u32 fdod; + + /* Observe SPI Descriptor Component Section 0 */ + writel(0x1000, RCB_REG(SPI_DESC_COMP0)); + + /* Extract the1 Write/Erase SPI Frequency from descriptor */ + fdod = readl(RCB_REG(SPI_FREQ_WR_ERA)); + fdod >>= 24; + fdod &= 7; + + /* Set Software Sequence frequency to match */ + clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); +} + +int arch_cpu_init(void) +{ + const void *blob = gd->fdt_blob; + struct pci_controller *hose; + int node; + int ret; + + post_code(POST_CPU_INIT); + timer_set_base(rdtsc()); + + ret = x86_cpu_init_f(); + if (ret) + return ret; + + ret = pci_early_init_hose(&hose); + if (ret) + return ret; + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); + if (node < 0) + return -ENOENT; + ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); + if (ret) + return ret; + + enable_spi_prefetch(hose, PCH_LPC_DEV); + + /* This is already done in start.S, but let's do it in C */ + enable_port80_on_lpc(hose, PCH_LPC_DEV); + + /* already done in car.S */ + if (false) + enable_rom_caching(); + + set_spi_speed(); + + /* + * We should do as little as possible before the serial console is + * up. Perhaps this should move to later. Our next lot of init + * happens in print_cpuinfo() when we have a console + */ + ret = set_flex_ratio_to_tdp_nominal(); + if (ret) + return ret; + + return 0; +} + +static int enable_smbus(void) +{ + pci_dev_t dev; + uint16_t value; + + /* Set the SMBus device statically. */ + dev = PCI_BDF(0x0, 0x1f, 0x3); + + /* Check to make sure we've got the right device. */ + value = pci_read_config16(dev, 0x0); + if (value != 0x8086) { + printf("SMBus controller not found\n"); + return -ENOSYS; + } + + /* Set SMBus I/O base. */ + pci_write_config32(dev, SMB_BASE, + SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + + /* Set SMBus enable. */ + pci_write_config8(dev, HOSTC, HST_EN); + + /* Set SMBus I/O space enable. */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + /* Disable interrupt generation. */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); + + /* Clear any lingering errors, so transactions can run. */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + debug("SMBus controller enabled\n"); + + return 0; +} + +#define PCH_EHCI0_TEMP_BAR0 0xe8000000 +#define PCH_EHCI1_TEMP_BAR0 0xe8000400 +#define PCH_XHCI_TEMP_BAR0 0xe8001000 + +/* + * Setup USB controller MMIO BAR to prevent the reference code from + * resetting the controller. + * + * The BAR will be re-assigned during device enumeration so these are only + * temporary. + * + * This is used to speed up the resume path. + */ +static void enable_usb_bar(void) +{ + pci_dev_t usb0 = PCH_EHCI1_DEV; + pci_dev_t usb1 = PCH_EHCI2_DEV; + pci_dev_t usb3 = PCH_XHCI_DEV; + u32 cmd; + + /* USB Controller 1 */ + pci_write_config32(usb0, PCI_BASE_ADDRESS_0, + PCH_EHCI0_TEMP_BAR0); + cmd = pci_read_config32(usb0, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(usb0, PCI_COMMAND, cmd); + + /* USB Controller 1 */ + pci_write_config32(usb1, PCI_BASE_ADDRESS_0, + PCH_EHCI1_TEMP_BAR0); + cmd = pci_read_config32(usb1, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(usb1, PCI_COMMAND, cmd); + + /* USB3 Controller */ + pci_write_config32(usb3, PCI_BASE_ADDRESS_0, + PCH_XHCI_TEMP_BAR0); + cmd = pci_read_config32(usb3, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(usb3, PCI_COMMAND, cmd); +} + +static int report_bist_failure(void) +{ + if (gd->arch.bist != 0) { + printf("BIST failed: %08x\n", gd->arch.bist); + return -EFAULT; + } + + return 0; +} + +int print_cpuinfo(void) +{ + enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; + char processor_name[CPU_MAX_NAME_LEN]; + const char *name; + uint32_t pm1_cnt; + uint16_t pm1_sts; + int ret; + + /* Halt if there was a built in self test failure */ + ret = report_bist_failure(); + if (ret) + return ret; + + enable_lapic(); + + ret = microcode_update_intel(); + if (ret && ret != -ENOENT && ret != -EEXIST) + return ret; + + /* Enable upper 128bytes of CMOS */ + writel(1 << 2, RCB_REG(RC)); + + /* TODO: cmos_post_init() */ + if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) { + debug("soft reset detected\n"); + boot_mode = PEI_BOOT_SOFT_RESET; + + /* System is not happy after keyboard reset... */ + debug("Issuing CF9 warm reset\n"); + outb(0x6, 0xcf9); + cpu_hlt(); + } + + /* Early chipset init required before RAM init can work */ + sandybridge_early_init(SANDYBRIDGE_MOBILE); + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + + if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + debug("Resume from S3 detected.\n"); + boot_mode = PEI_BOOT_RESUME; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); +#else + debug("Resume from S3 detected, but disabled.\n"); +#endif + } else { + /* + * TODO: An indication of life might be possible here (e.g. + * keyboard light) + */ + } + post_code(POST_EARLY_INIT); + + /* Enable SPD ROMs and DDR-III DRAM */ + ret = enable_smbus(); + if (ret) + return ret; + + /* Prepare USB controller early in S3 resume */ + if (boot_mode == PEI_BOOT_RESUME) + enable_usb_bar(); + + gd->arch.pei_boot_mode = boot_mode; + + /* TODO: Move this to the board or driver */ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10); + + /* Print processor name */ + name = cpu_get_name(processor_name); + printf("CPU: %s\n", name); + + post_code(POST_CPU_INFO); + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c new file mode 100644 index 0000000..eb8f613 --- /dev/null +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -0,0 +1,145 @@ +/* + * From Coreboot + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 Google Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> +#include <asm/arch/sandybridge.h> + +static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev) +{ + /* Setting up Southbridge. In the northbridge code. */ + debug("Setting up static southbridge registers\n"); + pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); + + pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */ + + debug("Disabling watchdog reboot\n"); + setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ + outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + + /* Set up all hardcoded northbridge BARs */ + debug("Setting up static registers\n"); + pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1); + pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); + pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(pch_dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + /* 64MB - busses 0-63 */ + pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); + pci_write_config32(pch_dev, PCIEXBAR + 4, + (0LL + DEFAULT_PCIEXBAR) >> 32); + pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1); + pci_write_config32(pch_dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); + + /* Set C0000-FFFFF to access RAM on both reads and writes */ + pci_write_config8(pch_dev, PAM0, 0x30); + pci_write_config8(pch_dev, PAM1, 0x33); + pci_write_config8(pch_dev, PAM2, 0x33); + pci_write_config8(pch_dev, PAM3, 0x33); + pci_write_config8(pch_dev, PAM4, 0x33); + pci_write_config8(pch_dev, PAM5, 0x33); + pci_write_config8(pch_dev, PAM6, 0x33); +} + +static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev) +{ + u32 reg32; + u16 reg16; + u8 reg8; + + reg16 = pci_read_config16(video_dev, PCI_DEVICE_ID); + switch (reg16) { + case 0x0102: /* GT1 Desktop */ + case 0x0106: /* GT1 Mobile */ + case 0x010a: /* GT1 Server */ + case 0x0112: /* GT2 Desktop */ + case 0x0116: /* GT2 Mobile */ + case 0x0122: /* GT2 Desktop >=1.3GHz */ + case 0x0126: /* GT2 Mobile >=1.3GHz */ + case 0x0156: /* IvyBridge */ + case 0x0166: /* IvyBridge */ + break; + default: + debug("Graphics not supported by this CPU/chipset\n"); + return; + } + + debug("Initialising Graphics\n"); + + /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ + reg16 = pci_read_config16(pch_dev, GGC); + reg16 &= ~0x00f8; + reg16 |= 1 << 3; + /* Program GTT memory by setting GGC[9:8] = 2MB */ + reg16 &= ~0x0300; + reg16 |= 2 << 8; + /* Enable VGA decode */ + reg16 &= ~0x0002; + pci_write_config16(pch_dev, GGC, reg16); + + /* Enable 256MB aperture */ + reg8 = pci_read_config8(video_dev, MSAC); + reg8 &= ~0x06; + reg8 |= 0x02; + pci_write_config8(video_dev, MSAC, reg8); + + /* Erratum workarounds */ + reg32 = readl(MCHBAR_REG(0x5f00)); + reg32 |= (1 << 9) | (1 << 10); + writel(reg32, MCHBAR_REG(0x5f00)); + + /* Enable SA Clock Gating */ + reg32 = readl(MCHBAR_REG(0x5f00)); + writel(reg32 | 1, MCHBAR_REG(0x5f00)); + + /* GPU RC6 workaround for sighting 366252 */ + reg32 = readl(MCHBAR_REG(0x5d14)); + reg32 |= (1 << 31); + writel(reg32, MCHBAR_REG(0x5d14)); + + /* VLW */ + reg32 = readl(MCHBAR_REG(0x6120)); + reg32 &= ~(1 << 0); + writel(reg32, MCHBAR_REG(0x6120)); + + reg32 = readl(MCHBAR_REG(0x5418)); + reg32 |= (1 << 4) | (1 << 5); + writel(reg32, MCHBAR_REG(0x5418)); +} + +void sandybridge_early_init(int chipset_type) +{ + pci_dev_t pch_dev = PCH_DEV; + pci_dev_t video_dev = PCH_VIDEO_DEV; + pci_dev_t lpc_dev = PCH_LPC_DEV; + u32 capid0_a; + u8 reg8; + + /* Device ID Override Enable should be done very early */ + capid0_a = pci_read_config32(pch_dev, 0xe4); + if (capid0_a & (1 << 10)) { + reg8 = pci_read_config8(pch_dev, 0xf3); + reg8 &= ~7; /* Clear 2:0 */ + + if (chipset_type == SANDYBRIDGE_MOBILE) + reg8 |= 1; /* Set bit 0 */ + + pci_write_config8(pch_dev, 0xf3, reg8); + } + + /* Setup all BARs required for early PCIe and raminit */ + sandybridge_setup_bars(pch_dev, lpc_dev); + + /* Device Enable */ + pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD); + + sandybridge_setup_graphics(pch_dev, video_dev); +} diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c new file mode 100644 index 0000000..b24dea1 --- /dev/null +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -0,0 +1,191 @@ +/* + * From Coreboot src/southbridge/intel/bd82x6x/early_me.c + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <errno.h> +#include <asm/pci.h> +#include <asm/processor.h> +#include <asm/arch/me.h> +#include <asm/arch/pch.h> +#include <asm/io.h> + +static const char *const me_ack_values[] = { + [ME_HFS_ACK_NO_DID] = "No DID Ack received", + [ME_HFS_ACK_RESET] = "Non-power cycle reset", + [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset", + [ME_HFS_ACK_S3] = "Go to S3", + [ME_HFS_ACK_S4] = "Go to S4", + [ME_HFS_ACK_S5] = "Go to S5", + [ME_HFS_ACK_GBL_RESET] = "Global Reset", + [ME_HFS_ACK_CONTINUE] = "Continue to boot" +}; + +static inline void pci_read_dword_ptr(void *ptr, int offset) +{ + u32 dword; + + dword = pci_read_config32(PCH_ME_DEV, offset); + memcpy(ptr, &dword, sizeof(dword)); +} + +static inline void pci_write_dword_ptr(void *ptr, int offset) +{ + u32 dword = 0; + memcpy(&dword, ptr, sizeof(dword)); + pci_write_config32(PCH_ME_DEV, offset, dword); +} + +void intel_early_me_status(void) +{ + struct me_hfs hfs; + struct me_gmes gmes; + + pci_read_dword_ptr(&hfs, PCI_ME_HFS); + pci_read_dword_ptr(&gmes, PCI_ME_GMES); + + intel_me_status(&hfs, &gmes); +} + +int intel_early_me_init(void) +{ + int count; + struct me_uma uma; + struct me_hfs hfs; + + debug("Intel ME early init\n"); + + /* Wait for ME UMA SIZE VALID bit to be set */ + for (count = ME_RETRY; count > 0; --count) { + pci_read_dword_ptr(&uma, PCI_ME_UMA); + if (uma.valid) + break; + udelay(ME_DELAY); + } + if (!count) { + printf("ERROR: ME is not ready!\n"); + return -EBUSY; + } + + /* Check for valid firmware */ + pci_read_dword_ptr(&hfs, PCI_ME_HFS); + if (hfs.fpt_bad) { + printf("WARNING: ME has bad firmware\n"); + return -EBADF; + } + + debug("Intel ME firmware is ready\n"); + + return 0; +} + +int intel_early_me_uma_size(void) +{ + struct me_uma uma; + + pci_read_dword_ptr(&uma, PCI_ME_UMA); + if (uma.valid) { + debug("ME: Requested %uMB UMA\n", uma.size); + return uma.size; + } + + debug("ME: Invalid UMA size\n"); + return -EINVAL; +} + +static inline void set_global_reset(int enable) +{ + u32 etr3; + + etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); + + /* Clear CF9 Without Resume Well Reset Enable */ + etr3 &= ~ETR3_CWORWRE; + + /* CF9GR indicates a Global Reset */ + if (enable) + etr3 |= ETR3_CF9GR; + else + etr3 &= ~ETR3_CF9GR; + + pci_write_config32(PCH_LPC_DEV, ETR3, etr3); +} + +int intel_early_me_init_done(u8 status) +{ + u8 reset; + int count; + u32 mebase_l, mebase_h; + struct me_hfs hfs; + struct me_did did = { + .init_done = ME_INIT_DONE, + .status = status + }; + + /* MEBASE from MESEG_BASE[35:20] */ + mebase_l = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L); + mebase_h = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H); + mebase_h &= 0xf; + did.uma_base = (mebase_l >> 20) | (mebase_h << 12); + + /* Send message to ME */ + debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n", + status, did.uma_base); + + pci_write_dword_ptr(&did, PCI_ME_H_GS); + + /* Must wait for ME acknowledgement */ + for (count = ME_RETRY; count > 0; --count) { + pci_read_dword_ptr(&hfs, PCI_ME_HFS); + if (hfs.bios_msg_ack) + break; + udelay(ME_DELAY); + } + if (!count) { + printf("ERROR: ME failed to respond\n"); + return -1; + } + + /* Return the requested BIOS action */ + debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]); + + /* Check status after acknowledgement */ + intel_early_me_status(); + + reset = 0; + switch (hfs.ack_data) { + case ME_HFS_ACK_CONTINUE: + /* Continue to boot */ + return 0; + case ME_HFS_ACK_RESET: + /* Non-power cycle reset */ + set_global_reset(0); + reset = 0x06; + break; + case ME_HFS_ACK_PWR_CYCLE: + /* Power cycle reset */ + set_global_reset(0); + reset = 0x0e; + break; + case ME_HFS_ACK_GBL_RESET: + /* Global reset */ + set_global_reset(1); + reset = 0x0e; + break; + case ME_HFS_ACK_S3: + case ME_HFS_ACK_S4: + case ME_HFS_ACK_S5: + break; + } + + /* Perform the requested reset */ + if (reset) { + outb(reset, 0xcf9); + cpu_hlt(); + } + return -1; +} diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c new file mode 100644 index 0000000..3d7f740 --- /dev/null +++ b/arch/x86/cpu/ivybridge/gma.c @@ -0,0 +1,756 @@ +/* + * From Coreboot file of the same name + * + * Copyright (C) 2011 Chromium OS Authors + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <bios_emul.h> +#include <errno.h> +#include <fdtdec.h> +#include <pci_rom.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> +#include <asm/arch/sandybridge.h> + +struct gt_powermeter { + u16 reg; + u32 value; +}; + +static const struct gt_powermeter snb_pm_gt1[] = { + { 0xa200, 0xcc000000 }, + { 0xa204, 0x07000040 }, + { 0xa208, 0x0000fe00 }, + { 0xa20c, 0x00000000 }, + { 0xa210, 0x17000000 }, + { 0xa214, 0x00000021 }, + { 0xa218, 0x0817fe19 }, + { 0xa21c, 0x00000000 }, + { 0xa220, 0x00000000 }, + { 0xa224, 0xcc000000 }, + { 0xa228, 0x07000040 }, + { 0xa22c, 0x0000fe00 }, + { 0xa230, 0x00000000 }, + { 0xa234, 0x17000000 }, + { 0xa238, 0x00000021 }, + { 0xa23c, 0x0817fe19 }, + { 0xa240, 0x00000000 }, + { 0xa244, 0x00000000 }, + { 0xa248, 0x8000421e }, + { 0 } +}; + +static const struct gt_powermeter snb_pm_gt2[] = { + { 0xa200, 0x330000a6 }, + { 0xa204, 0x402d0031 }, + { 0xa208, 0x00165f83 }, + { 0xa20c, 0xf1000000 }, + { 0xa210, 0x00000000 }, + { 0xa214, 0x00160016 }, + { 0xa218, 0x002a002b }, + { 0xa21c, 0x00000000 }, + { 0xa220, 0x00000000 }, + { 0xa224, 0x330000a6 }, + { 0xa228, 0x402d0031 }, + { 0xa22c, 0x00165f83 }, + { 0xa230, 0xf1000000 }, + { 0xa234, 0x00000000 }, + { 0xa238, 0x00160016 }, + { 0xa23c, 0x002a002b }, + { 0xa240, 0x00000000 }, + { 0xa244, 0x00000000 }, + { 0xa248, 0x8000421e }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt1[] = { + { 0xa800, 0x00000000 }, + { 0xa804, 0x00021c00 }, + { 0xa808, 0x00000403 }, + { 0xa80c, 0x02001700 }, + { 0xa810, 0x05000200 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00690500 }, + { 0xa81c, 0x0000007f }, + { 0xa820, 0x01002501 }, + { 0xa824, 0x00000300 }, + { 0xa828, 0x01000331 }, + { 0xa82c, 0x0000000c }, + { 0xa830, 0x00010016 }, + { 0xa834, 0x01100101 }, + { 0xa838, 0x00010103 }, + { 0xa83c, 0x00041300 }, + { 0xa840, 0x00000b30 }, + { 0xa844, 0x00000000 }, + { 0xa848, 0x7f000000 }, + { 0xa84c, 0x05000008 }, + { 0xa850, 0x00000001 }, + { 0xa854, 0x00000004 }, + { 0xa858, 0x00000007 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00010000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00001c00 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x06000000 }, + { 0xa910, 0x09000200 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00590000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x04002501 }, + { 0xa924, 0x00000100 }, + { 0xa928, 0x03000410 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00020000 }, + { 0xa934, 0x02070106 }, + { 0xa938, 0x00010100 }, + { 0xa93c, 0x00401c00 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x10000e00 }, + { 0xa94c, 0x02000004 }, + { 0xa950, 0x00000001 }, + { 0xa954, 0x00000004 }, + { 0xa960, 0x00060000 }, + { 0xaa3c, 0x00001c00 }, + { 0xaa54, 0x00000004 }, + { 0xaa60, 0x00060000 }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt2[] = { + { 0xa800, 0x10000000 }, + { 0xa804, 0x00033800 }, + { 0xa808, 0x00000902 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x12000400 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20800 }, + { 0xa81c, 0x00000002 }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00010032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x0000151d }, + { 0xa844, 0x00000000 }, + { 0xa848, 0x20001b00 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000000 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x00000008 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003500 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000500 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000200 }, + { 0xa928, 0x07000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x050f020d }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt2_17w[] = { + { 0xa800, 0x20000000 }, + { 0xa804, 0x000e3800 }, + { 0xa808, 0x00000806 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x0c000800 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20d00 }, + { 0xa81c, 0x000000ff }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00020032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x000016ff }, + { 0xa844, 0x00000000 }, + { 0xa848, 0xff000000 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000002 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x0000000f }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003800 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000800 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000300 }, + { 0xa928, 0x01000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x15150406 }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt2_35w[] = { + { 0xa800, 0x00000000 }, + { 0xa804, 0x00030400 }, + { 0xa808, 0x00000806 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x0c000300 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20d00 }, + { 0xa81c, 0x000000ff }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00020032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x000016ff }, + { 0xa844, 0x00000000 }, + { 0xa848, 0xff000000 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000001 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x00000008 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003800 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000800 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000300 }, + { 0xa928, 0x01000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x15150406 }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + +/* + * Some vga option roms are used for several chipsets but they only have one + * PCI ID in their header. If we encounter such an option rom, we need to do + * the mapping ourselves. + */ + +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev = vendev; + + switch (vendev) { + case 0x80860102: /* GT1 Desktop */ + case 0x8086010a: /* GT1 Server */ + case 0x80860112: /* GT2 Desktop */ + case 0x80860116: /* GT2 Mobile */ + case 0x80860122: /* GT2 Desktop >=1.3GHz */ + case 0x80860126: /* GT2 Mobile >=1.3GHz */ + case 0x80860156: /* IVB */ + case 0x80860166: /* IVB */ + /* Set to GT1 Mobile */ + new_vendev = 0x80860106; + break; + } + + return new_vendev; +} + +static inline u32 gtt_read(void *bar, u32 reg) +{ + return readl(bar + reg); +} + +static inline void gtt_write(void *bar, u32 reg, u32 data) +{ + writel(data, bar + reg); +} + +static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm) +{ + for (; pm && pm->reg; pm++) + gtt_write(bar, pm->reg, pm->value); +} + +#define GTT_RETRY 1000 +static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value) +{ + unsigned try = GTT_RETRY; + u32 data; + + while (try--) { + data = gtt_read(bar, reg); + if ((data & mask) == value) + return 1; + udelay(10); + } + + printf("GT init timeout\n"); + return 0; +} + +static int gma_pm_init_pre_vbios(void *gtt_bar) +{ + u32 reg32; + + debug("GT Power Management Init, silicon = %#x\n", + bridge_silicon_revision()); + + if (bridge_silicon_revision() < IVB_STEP_C0) { + /* 1: Enable force wake */ + gtt_write(gtt_bar, 0xa18c, 0x00000001); + gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0)); + } else { + gtt_write(gtt_bar, 0xa180, 1 << 5); + gtt_write(gtt_bar, 0xa188, 0xffff0001); + gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0)); + } + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ + reg32 = gtt_read(gtt_bar, 0x42004); + reg32 |= (1 << 14) | (1 << 15); + gtt_write(gtt_bar, 0x42004, reg32); + } + + if (bridge_silicon_revision() >= IVB_STEP_A0) { + /* Display Reset Acknowledge Settings */ + reg32 = gtt_read(gtt_bar, 0x45010); + reg32 |= (1 << 1) | (1 << 0); + gtt_write(gtt_bar, 0x45010, reg32); + } + + /* 2: Get GT SKU from GTT+0x911c[13] */ + reg32 = gtt_read(gtt_bar, 0x911c); + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + if (reg32 & (1 << 13)) { + debug("SNB GT1 Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, snb_pm_gt1); + } else { + debug("SNB GT2 Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, snb_pm_gt2); + } + } else { + u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf; + + if (reg32 & (1 << 13)) { + /* GT1 SKU */ + debug("IVB GT1 Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt1); + } else { + /* GT2 SKU */ + u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff; + tdp /= (1 << unit); + + if (tdp <= 17) { + /* <=17W ULV */ + debug("IVB GT2 17W Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w); + } else if ((tdp >= 25) && (tdp <= 35)) { + /* 25W-35W */ + debug("IVB GT2 25W-35W Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w); + } else { + /* All others */ + debug("IVB GT2 35W Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w); + } + } + } + + /* 3: Gear ratio map */ + gtt_write(gtt_bar, 0xa004, 0x00000010); + + /* 4: GFXPAUSE */ + gtt_write(gtt_bar, 0xa000, 0x00070020); + + /* 5: Dynamic EU trip control */ + gtt_write(gtt_bar, 0xa080, 0x00000004); + + /* 6: ECO bits */ + reg32 = gtt_read(gtt_bar, 0xa180); + reg32 |= (1 << 26) | (1 << 31); + /* (bit 20=1 for SNB step D1+ / IVB A0+) */ + if (bridge_silicon_revision() >= SNB_STEP_D1) + reg32 |= (1 << 20); + gtt_write(gtt_bar, 0xa180, reg32); + + /* 6a: for SnB step D2+ only */ + if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && + (bridge_silicon_revision() >= SNB_STEP_D2)) { + reg32 = gtt_read(gtt_bar, 0x9400); + reg32 |= (1 << 7); + gtt_write(gtt_bar, 0x9400, reg32); + + reg32 = gtt_read(gtt_bar, 0x941c); + reg32 &= 0xf; + reg32 |= (1 << 1); + gtt_write(gtt_bar, 0x941c, reg32); + gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1)); + } + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + reg32 = gtt_read(gtt_bar, 0x907c); + reg32 |= (1 << 16); + gtt_write(gtt_bar, 0x907c, reg32); + + /* 6b: Clocking reset controls */ + gtt_write(gtt_bar, 0x9424, 0x00000001); + } else { + /* 6b: Clocking reset controls */ + gtt_write(gtt_bar, 0x9424, 0x00000000); + } + + /* 7 */ + if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) { + gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */ + /* Mailbox Cmd for RC6 VID */ + gtt_write(gtt_bar, 0x138124, 0x80000004); + if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) + gtt_write(gtt_bar, 0x138124, 0x8000000a); + gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)); + } + + /* 8 */ + gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */ + gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ + gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ + gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ + gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */ + gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */ + + /* 9 */ + gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */ + gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */ + gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */ + + /* 10 */ + gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */ + gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */ + gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */ + gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */ + gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */ + + /* 11 */ + gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */ + gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */ + gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */ + gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */ + gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */ + gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */ + gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */ + + /* 11a: Enable Render Standby (RC6) */ + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + /* + * IvyBridge should also support DeepRenderStandby. + * + * Unfortunately it does not work reliably on all SKUs so + * disable it here and it can be enabled by the kernel. + */ + gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */ + } else { + gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */ + } + + /* 12: Normal Frequency Request */ + /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */ + reg32 = readl(MCHBAR_REG(0x5998)); + reg32 >>= 16; + reg32 &= 0xef; + reg32 <<= 25; + gtt_write(gtt_bar, 0xa008, reg32); + + /* 13: RP Control */ + gtt_write(gtt_bar, 0xa024, 0x00000592); + + /* 14: Enable PM Interrupts */ + gtt_write(gtt_bar, 0x4402c, 0x03000076); + + /* Clear 0x6c024 [8:6] */ + reg32 = gtt_read(gtt_bar, 0x6c024); + reg32 &= ~0x000001c0; + gtt_write(gtt_bar, 0x6c024, reg32); + + return 0; +} + +int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node) +{ + u32 reg32, cycle_delay; + + debug("GT Power Management Init (post VBIOS)\n"); + + /* 15: Deassert Force Wake */ + if (bridge_silicon_revision() < IVB_STEP_C0) { + gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1); + gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0)); + } else { + gtt_write(gtt_bar, 0xa188, 0x1fffe); + if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) { + gtt_write(gtt_bar, 0xa188, + gtt_read(gtt_bar, 0xa188) | 1); + } + } + + /* 16: SW RC Control */ + gtt_write(gtt_bar, 0xa094, 0x00060000); + + /* Setup Digital Port Hotplug */ + reg32 = gtt_read(gtt_bar, 0xc4030); + if (!reg32) { + u32 dp_hotplug[3]; + + if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug", + dp_hotplug, ARRAY_SIZE(dp_hotplug))) + return -EINVAL; + + reg32 = (dp_hotplug[0] & 0x7) << 2; + reg32 |= (dp_hotplug[0] & 0x7) << 10; + reg32 |= (dp_hotplug[0] & 0x7) << 18; + gtt_write(gtt_bar, 0xc4030, reg32); + } + + /* Setup Panel Power On Delays */ + reg32 = gtt_read(gtt_bar, 0xc7208); + if (!reg32) { + reg32 = (unsigned)fdtdec_get_int(blob, node, + "panel-port-select", 0) << 30; + reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0) + << 16; + reg32 |= fdtdec_get_int(blob, node, + "panel-power-backlight-on-delay", 0); + gtt_write(gtt_bar, 0xc7208, reg32); + } + + /* Setup Panel Power Off Delays */ + reg32 = gtt_read(gtt_bar, 0xc720c); + if (!reg32) { + reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0) + << 16; + reg32 |= fdtdec_get_int(blob, node, + "panel-power-backlight-off-delay", 0); + gtt_write(gtt_bar, 0xc720c, reg32); + } + + /* Setup Panel Power Cycle Delay */ + cycle_delay = fdtdec_get_int(blob, node, + "intel,panel-power-cycle-delay", 0); + if (cycle_delay) { + reg32 = gtt_read(gtt_bar, 0xc7210); + reg32 &= ~0xff; + reg32 |= cycle_delay; + gtt_write(gtt_bar, 0xc7210, reg32); + } + + /* Enable Backlight if needed */ + reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0); + if (reg32) { + gtt_write(gtt_bar, 0x48250, (1 << 31)); + gtt_write(gtt_bar, 0x48254, reg32); + } + reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0); + if (reg32) { + gtt_write(gtt_bar, 0xc8250, (1 << 31)); + gtt_write(gtt_bar, 0xc8254, reg32); + } + + return 0; +} + +/* + * Some vga option roms are used for several chipsets but they only have one + * PCI ID in their header. If we encounter such an option rom, we need to do + * the mapping ourselves. + */ + +uint32_t board_map_oprom_vendev(uint32_t vendev) +{ + switch (vendev) { + case 0x80860102: /* GT1 Desktop */ + case 0x8086010a: /* GT1 Server */ + case 0x80860112: /* GT2 Desktop */ + case 0x80860116: /* GT2 Mobile */ + case 0x80860122: /* GT2 Desktop >=1.3GHz */ + case 0x80860126: /* GT2 Mobile >=1.3GHz */ + case 0x80860156: /* IVB */ + case 0x80860166: /* IVB */ + return 0x80860106; /* GT1 Mobile */ + } + + return vendev; +} + +static int int15_handler(void) +{ + int res = 0; + + debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX); + + switch (M.x86.R_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + M.x86.R_AX = 0x005f; + M.x86.R_CL = 0x00; /* Use video bios default */ + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) + * bit 2 = EFP + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; /* Use video bios default */ + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0003; /* eDP */ + res = 1; + break; + case 0x5f70: + switch (M.x86.R_CH) { + case 0: + /* Get Mux */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + debug("Unknown INT15 5f70 function: 0x%02x\n", + M.x86.R_CH); + break; + } + break; + case 0x5fac: + res = 1; + break; + default: + debug("Unknown INT15 function %04x!\n", M.x86.R_AX); + break; + } + return res; +} + +int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, + const void *blob, int node) +{ + void *gtt_bar; + u32 reg32; + int ret; + + /* IGD needs to be Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + + gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0); + debug("GT bar %p\n", gtt_bar); + ret = gma_pm_init_pre_vbios(gtt_bar); + if (ret) + return ret; + + ret = pci_run_vga_bios(dev, int15_handler, false); + + /* Post VBIOS init */ + ret = gma_pm_init_post_vbios(gtt_bar, blob, node); + if (ret) + return ret; + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/gma.h b/arch/x86/cpu/ivybridge/gma.h new file mode 100644 index 0000000..e7ec649 --- /dev/null +++ b/arch/x86/cpu/ivybridge/gma.h @@ -0,0 +1,156 @@ +/* + * From Coreboot file of the same name + * + * Copyright (C) 2012 Chromium OS Authors + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/* mailbox 0: header */ +__packed struct opregion_header { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +}; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +__packed struct opregion_mailbox1 { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +}; + +/* mailbox 2: software sci interface */ +__packed struct opregion_mailbox2 { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +}; + +/* mailbox 3: power conservation */ +__packed struct opregion_mailbox3 { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +}; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +__packed struct { + u8 gvd1[7168]; +} opregion_vbt_t; + +/* IGD OpRegion */ +__packed struct igd_opregion { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +}; + +/* Intel Video BIOS (Option ROM) */ +__packed struct optionrom_header { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +}; + +#define OPROM_SIGNATURE 0xaa55 + +__packed struct optionrom_pcir { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +}; + +__packed struct optionrom_vbt { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +}; + +#define VBT_SIGNATURE 0x54425624 diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c new file mode 100644 index 0000000..43fdd31 --- /dev/null +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -0,0 +1,569 @@ +/* + * From coreboot southbridge/intel/bd82x6x/lpc.c + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <rtc.h> +#include <pci.h> +#include <asm/acpi.h> +#include <asm/interrupt.h> +#include <asm/io.h> +#include <asm/ioapic.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> + +#define NMI_OFF 0 + +#define ENABLE_ACPI_MODE_IN_COREBOOT 0 +#define TEST_SMM_FLASH_LOCKDOWN 0 + +static int pch_enable_apic(pci_dev_t dev) +{ + u32 reg32; + int i; + + /* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */ + pci_write_config8(dev, ACPI_CNTL, 0x80); + + writel(0, IO_APIC_INDEX); + writel(1 << 25, IO_APIC_DATA); + + /* affirm full set of redirection table entries ("write once") */ + writel(1, IO_APIC_INDEX); + reg32 = readl(IO_APIC_DATA); + writel(1, IO_APIC_INDEX); + writel(reg32, IO_APIC_DATA); + + writel(0, IO_APIC_INDEX); + reg32 = readl(IO_APIC_DATA); + debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f); + if (reg32 != (1 << 25)) { + printf("APIC Error - cannot write to registers\n"); + return -EPERM; + } + + debug("Dumping IOAPIC registers\n"); + for (i = 0; i < 3; i++) { + writel(i, IO_APIC_INDEX); + debug(" reg 0x%04x:", i); + reg32 = readl(IO_APIC_DATA); + debug(" 0x%08x\n", reg32); + } + + /* Select Boot Configuration register. */ + writel(3, IO_APIC_INDEX); + + /* Use Processor System Bus to deliver interrupts. */ + writel(1, IO_APIC_DATA); + + return 0; +} + +static void pch_enable_serial_irqs(pci_dev_t dev) +{ + u32 value; + + /* Set packet length and toggle silent mode bit for one frame. */ + value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0); +#ifdef CONFIG_SERIRQ_CONTINUOUS_MODE + pci_write_config8(dev, SERIRQ_CNTL, value); +#else + pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6)); +#endif +} + +static int pch_pirq_init(const void *blob, int node, pci_dev_t dev) +{ + uint8_t route[8], *ptr; + + if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route, + sizeof(route))) + return -EINVAL; + ptr = route; + pci_write_config8(dev, PIRQA_ROUT, *ptr++); + pci_write_config8(dev, PIRQB_ROUT, *ptr++); + pci_write_config8(dev, PIRQC_ROUT, *ptr++); + pci_write_config8(dev, PIRQD_ROUT, *ptr++); + + pci_write_config8(dev, PIRQE_ROUT, *ptr++); + pci_write_config8(dev, PIRQF_ROUT, *ptr++); + pci_write_config8(dev, PIRQG_ROUT, *ptr++); + pci_write_config8(dev, PIRQH_ROUT, *ptr++); + + /* + * TODO(sjg@chromium.org): U-Boot does not set up the interrupts + * here. It's unclear if it is needed + */ + return 0; +} + +static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev) +{ + u8 route[16]; + u32 reg; + int gpi; + + if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route, + sizeof(route))) + return -EINVAL; + + for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++) + reg |= route[gpi] << (gpi * 2); + + pci_write_config32(dev, 0xb8, reg); + + return 0; +} + +static int pch_power_options(const void *blob, int node, pci_dev_t dev) +{ + u8 reg8; + u16 reg16, pmbase; + u32 reg32; + const char *state; + int pwr_on; + int nmi_option; + int ret; + + /* + * Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + * + * If the option is not existent (Laptops), use Kconfig setting. + * TODO(sjg@chromium.org): Make this configurable + */ + pwr_on = MAINBOARD_POWER_ON; + + reg16 = pci_read_config16(dev, GEN_PMCON_3); + reg16 &= 0xfffe; + switch (pwr_on) { + case MAINBOARD_POWER_OFF: + reg16 |= 1; + state = "off"; + break; + case MAINBOARD_POWER_ON: + reg16 &= ~1; + state = "on"; + break; + case MAINBOARD_POWER_KEEP: + reg16 &= ~1; + state = "state keep"; + break; + default: + state = "undefined"; + } + + reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ + reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ + + reg16 &= ~(1 << 10); + reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ + + reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ + + pci_write_config16(dev, GEN_PMCON_3, reg16); + debug("Set power %s after power failure.\n", state); + + /* Set up NMI on errors. */ + reg8 = inb(0x61); + reg8 &= 0x0f; /* Higher Nibble must be 0 */ + reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ + reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + outb(reg8, 0x61); + + reg8 = inb(0x70); + /* TODO(sjg@chromium.org): Make this configurable */ + nmi_option = NMI_OFF; + if (nmi_option) { + debug("NMI sources enabled.\n"); + reg8 &= ~(1 << 7); /* Set NMI. */ + } else { + debug("NMI sources disabled.\n"); + /* Can't mask NMI from PCI-E and NMI_NOW */ + reg8 |= (1 << 7); + } + outb(reg8, 0x70); + + /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ + reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 &= ~(3 << 0); /* SMI# rate 1 minute */ + reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ +#if DEBUG_PERIODIC_SMIS + /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */ + reg16 |= (3 << 0); /* Periodic SMI every 8s */ +#endif + pci_write_config16(dev, GEN_PMCON_1, reg16); + + /* Set the board's GPI routing. */ + ret = pch_gpi_routing(blob, node, dev); + if (ret) + return ret; + + pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + + writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node, + "intel,gpe0-enable", 0)); + writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node, + "intel,alt-gp-smi-enable", 0)); + + /* Set up power management block and determine sleep mode */ + reg32 = inl(pmbase + 0x04); /* PM1_CNT */ + reg32 &= ~(7 << 10); /* SLP_TYP */ + reg32 |= (1 << 0); /* SCI_EN */ + outl(reg32, pmbase + 0x04); + + /* Clear magic status bits to prevent unexpected wake */ + setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0)); + clrbits_le32(RCB_REG(0x3f02), 0xf); + + return 0; +} + +static void pch_rtc_init(pci_dev_t dev) +{ + int rtc_failed; + u8 reg8; + + reg8 = pci_read_config8(dev, GEN_PMCON_3); + rtc_failed = reg8 & RTC_BATTERY_DEAD; + if (rtc_failed) { + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(dev, GEN_PMCON_3, reg8); + } + debug("rtc_failed = 0x%x\n", rtc_failed); + +#if CONFIG_HAVE_ACPI_RESUME + /* Avoid clearing pending interrupts and resetting the RTC control + * register in the resume path because the Linux kernel relies on + * this to know if it should restart the RTC timerqueue if the wake + * was due to the RTC alarm. + */ + if (acpi_get_slp_type() == 3) + return; +#endif + /* TODO: Handle power failure */ + if (rtc_failed) + printf("RTC power failed\n"); + rtc_init(); +} + +/* CougarPoint PCH Power Management init */ +static void cpt_pm_init(pci_dev_t dev) +{ + debug("CougarPoint PM init\n"); + pci_write_config8(dev, 0xa9, 0x47); + setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0)); + + setbits_le32(RCB_REG(0x228c), 1 << 0); + setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14)); + setbits_le32(RCB_REG(0x0900), 1 << 14); + writel(0xc0388400, RCB_REG(0x2304)); + setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); + setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); + clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf); + writel(0x050f0000, RCB_REG(0x3318)); + writel(0x04000000, RCB_REG(0x3324)); + setbits_le32(RCB_REG(0x3340), 0xfffff); + setbits_le32(RCB_REG(0x3344), 1 << 1); + + writel(0x0001c000, RCB_REG(0x3360)); + writel(0x00061100, RCB_REG(0x3368)); + writel(0x7f8fdfff, RCB_REG(0x3378)); + writel(0x000003fc, RCB_REG(0x337c)); + writel(0x00001000, RCB_REG(0x3388)); + writel(0x0001c000, RCB_REG(0x3390)); + writel(0x00000800, RCB_REG(0x33a0)); + writel(0x00001000, RCB_REG(0x33b0)); + writel(0x00093900, RCB_REG(0x33c0)); + writel(0x24653002, RCB_REG(0x33cc)); + writel(0x062108fe, RCB_REG(0x33d0)); + clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); + writel(0x01010000, RCB_REG(0x3a28)); + writel(0x01010404, RCB_REG(0x3a2c)); + writel(0x01041041, RCB_REG(0x3a80)); + clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); + setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */ + setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */ + writel(0x00000001, RCB_REG(0x3a6c)); + clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c); + clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); + writel(0, RCB_REG(0x33c8)); + setbits_le32(RCB_REG(0x21b0), 0xf); +} + +/* PantherPoint PCH Power Management init */ +static void ppt_pm_init(pci_dev_t dev) +{ + debug("PantherPoint PM init\n"); + pci_write_config8(dev, 0xa9, 0x47); + setbits_le32(RCB_REG(0x2238), 1 << 0); + setbits_le32(RCB_REG(0x228c), 1 << 0); + setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14)); + setbits_le16(RCB_REG(0x0900), 1 << 14); + writel(0xc03b8400, RCB_REG(0x2304)); + setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); + setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); + clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf); + writel(0x054f0000, RCB_REG(0x3318)); + writel(0x04000000, RCB_REG(0x3324)); + setbits_le32(RCB_REG(0x3340), 0xfffff); + setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0)); + writel(0x0001c000, RCB_REG(0x3360)); + writel(0x00061100, RCB_REG(0x3368)); + writel(0x7f8fdfff, RCB_REG(0x3378)); + writel(0x000003fd, RCB_REG(0x337c)); + writel(0x00001000, RCB_REG(0x3388)); + writel(0x0001c000, RCB_REG(0x3390)); + writel(0x00000800, RCB_REG(0x33a0)); + writel(0x00001000, RCB_REG(0x33b0)); + writel(0x00093900, RCB_REG(0x33c0)); + writel(0x24653002, RCB_REG(0x33cc)); + writel(0x067388fe, RCB_REG(0x33d0)); + clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); + writel(0x01010000, RCB_REG(0x3a28)); + writel(0x01010404, RCB_REG(0x3a2c)); + writel(0x01040000, RCB_REG(0x3a80)); + clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); + /* SATA 2/3 disabled */ + setbits_le32(RCB_REG(0x3a84), 1 << 24); + /* SATA 4/5 disabled */ + setbits_le32(RCB_REG(0x3a88), 1 << 0); + writel(0x00000001, RCB_REG(0x3a6c)); + clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c); + clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); + setbits_le32(RCB_REG(0x33a4), (1 << 0)); + writel(0, RCB_REG(0x33c8)); + setbits_le32(RCB_REG(0x21b0), 0xf); +} + +static void enable_hpet(void) +{ + /* Move HPET to default address 0xfed00000 and enable it */ + clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7); +} + +static void enable_clock_gating(pci_dev_t dev) +{ + u32 reg32; + u16 reg16; + + setbits_le32(RCB_REG(0x2234), 0xf); + + reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 |= (1 << 2) | (1 << 11); + pci_write_config16(dev, GEN_PMCON_1, reg16); + + pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); + pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); + pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); + pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + + reg32 = readl(RCB_REG(CG)); + reg32 |= (1 << 31); + reg32 |= (1 << 29) | (1 << 28); + reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); + reg32 |= (1 << 16); + reg32 |= (1 << 17); + reg32 |= (1 << 18); + reg32 |= (1 << 22); + reg32 |= (1 << 23); + reg32 &= ~(1 << 20); + reg32 |= (1 << 19); + reg32 |= (1 << 0); + reg32 |= (0xf << 1); + writel(reg32, RCB_REG(CG)); + + setbits_le32(RCB_REG(0x38c0), 0x7); + setbits_le32(RCB_REG(0x36d4), 0x6680c004); + setbits_le32(RCB_REG(0x3564), 0x3); +} + +#if CONFIG_HAVE_SMI_HANDLER +static void pch_lock_smm(pci_dev_t dev) +{ +#if TEST_SMM_FLASH_LOCKDOWN + u8 reg8; +#endif + + if (acpi_slp_type != 3) { +#if ENABLE_ACPI_MODE_IN_COREBOOT + debug("Enabling ACPI via APMC:\n"); + outb(0xe1, 0xb2); /* Enable ACPI mode */ + debug("done.\n"); +#else + debug("Disabling ACPI via APMC:\n"); + outb(0x1e, 0xb2); /* Disable ACPI mode */ + debug("done.\n"); +#endif + } + + /* Don't allow evil boot loaders, kernels, or + * userspace applications to deceive us: + */ + smm_lock(); + +#if TEST_SMM_FLASH_LOCKDOWN + /* Now try this: */ + debug("Locking BIOS to RO... "); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", + (reg8 & 1) ? "rw" : "ro"); + reg8 &= ~(1 << 0); /* clear BIOSWE */ + pci_write_config8(dev, 0xdc, reg8); + reg8 |= (1 << 1); /* set BLE */ + pci_write_config8(dev, 0xdc, reg8); + debug("ok.\n"); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", + (reg8 & 1) ? "rw" : "ro"); + + debug("Writing:\n"); + writeb(0, 0xfff00000); + debug("Testing:\n"); + reg8 |= (1 << 0); /* set BIOSWE */ + pci_write_config8(dev, 0xdc, reg8); + + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", + (reg8 & 1) ? "rw" : "ro"); + debug("Done.\n"); +#endif +} +#endif + +static void pch_disable_smm_only_flashing(pci_dev_t dev) +{ + u8 reg8; + + debug("Enabling BIOS updates outside of SMM... "); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 &= ~(1 << 5); + pci_write_config8(dev, 0xdc, reg8); +} + +static void pch_fixups(pci_dev_t dev) +{ + u8 gen_pmcon_2; + + /* Indicate DRAM init done for MRC S3 to know it can resume */ + gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); + gen_pmcon_2 |= (1 << 7); + pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); + + /* Enable DMI ASPM in the PCH */ + clrbits_le32(RCB_REG(0x2304), 1 << 10); + setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10)); + setbits_le32(RCB_REG(0x21a8), 0x3); +} + +int lpc_early_init(const void *blob, int node, pci_dev_t dev) +{ + struct reg_info { + u32 base; + u32 size; + } values[4], *ptr; + int count; + int i; + + count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec", + (u32 *)values, sizeof(values) / sizeof(u32)); + if (count < 0) + return -EINVAL; + + /* Set COM1/COM2 decode range */ + pci_write_config16(dev, LPC_IO_DEC, 0x0010); + + /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ + pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + GAMEL_LPC_EN | COMA_LPC_EN); + + /* Write all registers but use 0 if we run out of data */ + count = count * sizeof(u32) / sizeof(values[0]); + for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) { + u32 reg = 0; + + if (i < count) + reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16); + pci_write_config32(dev, LPC_GENX_DEC(i), reg); + } + + return 0; +} + +int lpc_init(struct pci_controller *hose, pci_dev_t dev) +{ + const void *blob = gd->fdt_blob; + int node; + + debug("pch: lpc_init\n"); + pci_write_bar32(hose, dev, 0, 0); + pci_write_bar32(hose, dev, 1, 0xff800000); + pci_write_bar32(hose, dev, 2, 0xfec00000); + pci_write_bar32(hose, dev, 3, 0x800); + pci_write_bar32(hose, dev, 4, 0x900); + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); + if (node < 0) + return -ENOENT; + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); + + /* IO APIC initialization. */ + pch_enable_apic(dev); + + pch_enable_serial_irqs(dev); + + /* Setup the PIRQ. */ + pch_pirq_init(blob, node, dev); + + /* Setup power options. */ + pch_power_options(blob, node, dev); + + /* Initialize power management */ + switch (pch_silicon_type()) { + case PCH_TYPE_CPT: /* CougarPoint */ + cpt_pm_init(dev); + break; + case PCH_TYPE_PPT: /* PantherPoint */ + ppt_pm_init(dev); + break; + default: + printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev), + PCI_FUNC(dev)); + return -ENOSYS; + } + + /* Initialize the real time clock. */ + pch_rtc_init(dev); + + /* Initialize the High Precision Event Timers, if present. */ + enable_hpet(); + + /* Initialize Clock Gating */ + enable_clock_gating(dev); + + pch_disable_smm_only_flashing(dev); + +#if CONFIG_HAVE_SMI_HANDLER + pch_lock_smm(dev); +#endif + + pch_fixups(dev); + + return 0; +} + +void lpc_enable(pci_dev_t dev) +{ + /* Enable PCH Display Port */ + writew(0x0010, RCB_REG(DISPBDF)); + setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); +} diff --git a/arch/x86/cpu/ivybridge/me_status.c b/arch/x86/cpu/ivybridge/me_status.c new file mode 100644 index 0000000..15cf69f --- /dev/null +++ b/arch/x86/cpu/ivybridge/me_status.c @@ -0,0 +1,195 @@ +/* + * From Coreboot src/southbridge/intel/bd82x6x/me_status.c + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/arch/me.h> + +/* HFS1[3:0] Current Working State Values */ +static const char *const me_cws_values[] = { + [ME_HFS_CWS_RESET] = "Reset", + [ME_HFS_CWS_INIT] = "Initializing", + [ME_HFS_CWS_REC] = "Recovery", + [ME_HFS_CWS_NORMAL] = "Normal", + [ME_HFS_CWS_WAIT] = "Platform Disable Wait", + [ME_HFS_CWS_TRANS] = "OP State Transition", + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" +}; + +/* HFS1[8:6] Current Operation State Values */ +static const char *const me_opstate_values[] = { + [ME_HFS_STATE_PREBOOT] = "Preboot", + [ME_HFS_STATE_M0_UMA] = "M0 with UMA", + [ME_HFS_STATE_M3] = "M3 without UMA", + [ME_HFS_STATE_M0] = "M0 without UMA", + [ME_HFS_STATE_BRINGUP] = "Bring up", + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" +}; + +/* HFS[19:16] Current Operation Mode Values */ +static const char *const me_opmode_values[] = { + [ME_HFS_MODE_NORMAL] = "Normal", + [ME_HFS_MODE_DEBUG] = "Debug", + [ME_HFS_MODE_DIS] = "Soft Temporary Disable", + [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" +}; + +/* HFS[15:12] Error Code Values */ +static const char *const me_error_values[] = { + [ME_HFS_ERROR_NONE] = "No Error", + [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", + [ME_HFS_ERROR_IMAGE] = "Image Failure", + [ME_HFS_ERROR_DEBUG] = "Debug Failure" +}; + +/* GMES[31:28] ME Progress Code */ +static const char *const me_progress_values[] = { + [ME_GMES_PHASE_ROM] = "ROM Phase", + [ME_GMES_PHASE_BUP] = "BUP Phase", + [ME_GMES_PHASE_UKERNEL] = "uKernel Phase", + [ME_GMES_PHASE_POLICY] = "Policy Module", + [ME_GMES_PHASE_MODULE] = "Module Loading", + [ME_GMES_PHASE_UNKNOWN] = "Unknown", + [ME_GMES_PHASE_HOST] = "Host Communication" +}; + +/* GMES[27:24] Power Management Event */ +static const char *const me_pmevent_values[] = { + [0x00] = "Clean Moff->Mx wake", + [0x01] = "Moff->Mx wake after an error", + [0x02] = "Clean global reset", + [0x03] = "Global reset after an error", + [0x04] = "Clean Intel ME reset", + [0x05] = "Intel ME reset due to exception", + [0x06] = "Pseudo-global reset", + [0x07] = "S0/M0->Sx/M3", + [0x08] = "Sx/M3->S0/M0", + [0x09] = "Non-power cycle reset", + [0x0a] = "Power cycle reset through M3", + [0x0b] = "Power cycle reset through Moff", + [0x0c] = "Sx/Mx->Sx/Moff" +}; + +/* Progress Code 0 states */ +static const char *const me_progress_rom_values[] = { + [0x00] = "BEGIN", + [0x06] = "DISABLE" +}; + +/* Progress Code 1 states */ +static const char *const me_progress_bup_values[] = { + [0x00] = "Initialization starts", + [0x01] = "Disable the host wake event", + [0x04] = "Flow determination start process", + [0x08] = "Error reading/matching the VSCC table in the descriptor", + [0x0a] = "Check to see if straps say ME DISABLED", + [0x0b] = "Timeout waiting for PWROK", + [0x0d] = "Possibly handle BUP manufacturing override strap", + [0x11] = "Bringup in M3", + [0x12] = "Bringup in M0", + [0x13] = "Flow detection error", + [0x15] = "M3 clock switching error", + [0x18] = "M3 kernel load", + [0x1c] = "T34 missing - cannot program ICC", + [0x1f] = "Waiting for DID BIOS message", + [0x20] = "Waiting for DID BIOS message failure", + [0x21] = "DID reported an error", + [0x22] = "Enabling UMA", + [0x23] = "Enabling UMA error", + [0x24] = "Sending DID Ack to BIOS", + [0x25] = "Sending DID Ack to BIOS error", + [0x26] = "Switching clocks in M0", + [0x27] = "Switching clocks in M0 error", + [0x28] = "ME in temp disable", + [0x32] = "M0 kernel load", +}; + +/* Progress Code 3 states */ +static const char *const me_progress_policy_values[] = { + [0x00] = "Entery into Policy Module", + [0x03] = "Received S3 entry", + [0x04] = "Received S4 entry", + [0x05] = "Received S5 entry", + [0x06] = "Received UPD entry", + [0x07] = "Received PCR entry", + [0x08] = "Received NPCR entry", + [0x09] = "Received host wake", + [0x0a] = "Received AC<>DC switch", + [0x0b] = "Received DRAM Init Done", + [0x0c] = "VSCC Data not found for flash device", + [0x0d] = "VSCC Table is not valid", + [0x0e] = "Flash Partition Boundary is outside address space", + [0x0f] = "ME cannot access the chipset descriptor region", + [0x10] = "Required VSCC values for flash parts do not match", +}; + +void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) +{ + /* Check Current States */ + debug("ME: FW Partition Table : %s\n", + hfs->fpt_bad ? "BAD" : "OK"); + debug("ME: Bringup Loader Failure : %s\n", + hfs->ft_bup_ld_flr ? "YES" : "NO"); + debug("ME: Firmware Init Complete : %s\n", + hfs->fw_init_complete ? "YES" : "NO"); + debug("ME: Manufacturing Mode : %s\n", + hfs->mfg_mode ? "YES" : "NO"); + debug("ME: Boot Options Present : %s\n", + hfs->boot_options_present ? "YES" : "NO"); + debug("ME: Update In Progress : %s\n", + hfs->update_in_progress ? "YES" : "NO"); + debug("ME: Current Working State : %s\n", + me_cws_values[hfs->working_state]); + debug("ME: Current Operation State : %s\n", + me_opstate_values[hfs->operation_state]); + debug("ME: Current Operation Mode : %s\n", + me_opmode_values[hfs->operation_mode]); + debug("ME: Error Code : %s\n", + me_error_values[hfs->error_code]); + debug("ME: Progress Phase : %s\n", + me_progress_values[gmes->progress_code]); + debug("ME: Power Management Event : %s\n", + me_pmevent_values[gmes->current_pmevent]); + + debug("ME: Progress Phase State : "); + switch (gmes->progress_code) { + case ME_GMES_PHASE_ROM: /* ROM Phase */ + debug("%s", me_progress_rom_values[gmes->current_state]); + break; + + case ME_GMES_PHASE_BUP: /* Bringup Phase */ + if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) && + me_progress_bup_values[gmes->current_state]) + debug("%s", + me_progress_bup_values[gmes->current_state]); + else + debug("0x%02x", gmes->current_state); + break; + + case ME_GMES_PHASE_POLICY: /* Policy Module Phase */ + if (gmes->current_state < + ARRAY_SIZE(me_progress_policy_values) && + me_progress_policy_values[gmes->current_state]) + debug("%s", + me_progress_policy_values[gmes->current_state]); + else + debug("0x%02x", gmes->current_state); + break; + + case ME_GMES_PHASE_HOST: /* Host Communication Phase */ + if (!gmes->current_state) + debug("Host communication established"); + else + debug("0x%02x", gmes->current_state); + break; + + default: + debug("Unknown 0x%02x", gmes->current_state); + } + debug("\n"); +} diff --git a/arch/x86/cpu/ivybridge/microcode_intel.c b/arch/x86/cpu/ivybridge/microcode_intel.c new file mode 100644 index 0000000..8c11a63 --- /dev/null +++ b/arch/x86/cpu/ivybridge/microcode_intel.c @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2014 Google, Inc + * Copyright (C) 2000 Ronald G. Minnich + * + * Microcode update for Intel PIII and later CPUs + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <asm/cpu.h> +#include <asm/msr.h> +#include <asm/processor.h> + +/** + * struct microcode_update - standard microcode header from Intel + * + * We read this information out of the device tree and use it to determine + * whether the update is applicable or not. We also use the same structure + * to read information from the CPU. + */ +struct microcode_update { + uint header_version; + uint update_revision; + uint date_code; + uint processor_signature; + uint checksum; + uint loader_revision; + uint processor_flags; + const void *data; + int size; +}; + +static int microcode_decode_node(const void *blob, int node, + struct microcode_update *update) +{ + update->data = fdt_getprop(blob, node, "data", &update->size); + if (!update->data) + return -EINVAL; + + update->header_version = fdtdec_get_int(blob, node, + "intel,header-version", 0); + update->update_revision = fdtdec_get_int(blob, node, + "intel,update-revision", 0); + update->date_code = fdtdec_get_int(blob, node, + "intel,date-code", 0); + update->processor_signature = fdtdec_get_int(blob, node, + "intel.processor-signature", 0); + update->checksum = fdtdec_get_int(blob, node, "intel,checksum", 0); + update->loader_revision = fdtdec_get_int(blob, node, + "loader-revision", 0); + update->processor_flags = fdtdec_get_int(blob, node, + "processor-flags", 0); + + return 0; +} + +static uint32_t microcode_read_rev(void) +{ + /* + * Some Intel CPUs can be very finicky about the CPUID sequence used. + * So this is implemented in assembly so that it works reliably. + */ + uint32_t low, high; + + asm volatile ( + "xorl %%eax, %%eax\n" + "xorl %%edx, %%edx\n" + "movl $0x8b, %%ecx\n" + "wrmsr\n" + "movl $0x01, %%eax\n" + "cpuid\n" + "movl $0x8b, %%ecx\n" + "rdmsr\n" + : /* outputs */ + "=a" (low), "=d" (high) + : /* inputs */ + : /* clobbers */ + "ebx", "ecx" + ); + + return high; +} + +static void microcode_read_cpu(struct microcode_update *cpu) +{ + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ + unsigned int x86_model, x86_family; + struct cpuid_result result; + uint32_t low, high; + + wrmsr(0x8b, 0, 0); + result = cpuid(1); + rdmsr(0x8b, low, cpu->update_revision); + x86_model = (result.eax >> 4) & 0x0f; + x86_family = (result.eax >> 8) & 0x0f; + cpu->processor_signature = result.eax; + + cpu->processor_flags = 0; + if ((x86_model >= 5) || (x86_family > 6)) { + rdmsr(0x17, low, high); + cpu->processor_flags = 1 << ((high >> 18) & 7); + } + debug("microcode: sig=%#x pf=%#x revision=%#x\n", + cpu->processor_signature, cpu->processor_flags, + cpu->update_revision); +} + +/* Get a microcode update from the device tree and apply it */ +int microcode_update_intel(void) +{ + struct microcode_update cpu, update; + const void *blob = gd->fdt_blob; + int count; + int node; + int ret; + + microcode_read_cpu(&cpu); + node = 0; + count = 0; + do { + node = fdtdec_next_compatible(blob, node, + COMPAT_INTEL_MICROCODE); + if (node < 0) { + debug("%s: Found %d updates\n", __func__, count); + return count ? 0 : -ENOENT; + } + + ret = microcode_decode_node(blob, node, &update); + if (ret) { + debug("%s: Unable to decode update: %d\n", __func__, + ret); + return ret; + } + if (update.processor_signature == cpu.processor_signature && + (update.processor_flags & cpu.processor_flags)) { + debug("%s: Update already exists\n", __func__); + return -EEXIST; + } + + wrmsr(0x79, (ulong)update.data, 0); + debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n", + microcode_read_rev(), update.date_code & 0xffff, + (update.date_code >> 24) & 0xff, + (update.date_code >> 16) & 0xff); + count++; + } while (1); +} diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c new file mode 100644 index 0000000..11dc625 --- /dev/null +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -0,0 +1,514 @@ +/* + * From Coreboot file of same name + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium Authors + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <fdtdec.h> +#include <malloc.h> +#include <asm/acpi.h> +#include <asm/cpu.h> +#include <asm/lapic.h> +#include <asm/lapic_def.h> +#include <asm/msr.h> +#include <asm/mtrr.h> +#include <asm/processor.h> +#include <asm/speedstep.h> +#include <asm/turbo.h> +#include <asm/arch/model_206ax.h> + +static void enable_vmx(void) +{ + struct cpuid_result regs; +#ifdef CONFIG_ENABLE_VMX + int enable = true; +#else + int enable = false; +#endif + msr_t msr; + + regs = cpuid(1); + /* Check that the VMX is supported before reading or writing the MSR. */ + if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) + return; + + msr = msr_read(MSR_IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + debug("VMX is locked, so %s will do nothing\n", __func__); + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + /* The IA32_FEATURE_CONTROL MSR may initialize with random values. + * It must be cleared regardless of VMX config setting. + */ + msr.hi = 0; + msr.lo = 0; + + debug("%s VMX\n", enable ? "Enabling" : "Disabling"); + + /* + * Even though the Intel manual says you must set the lock bit in + * addition to the VMX bit in order for VMX to work, it is incorrect. + * Thus we leave it unlocked for the OS to manage things itself. + * This is good for a few reasons: + * - No need to reflash the bios just to toggle the lock bit. + * - The VMX bits really really should match each other across cores, + * so hard locking it on one while another has the opposite setting + * can easily lead to crashes as code using VMX migrates between + * them. + * - Vendors that want to "upsell" from a bios that disables+locks to + * one that doesn't is sleazy. + * By leaving this to the OS (e.g. Linux), people can do exactly what + * they want on the fly, and do it correctly (e.g. across multiple + * cores). + */ + if (enable) { + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); + } + + msr_write(MSR_IA32_FEATURE_CONTROL, msr); +} + +/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ +static const u8 power_limit_time_sec_to_msr[] = { + [0] = 0x00, + [1] = 0x0a, + [2] = 0x0b, + [3] = 0x4b, + [4] = 0x0c, + [5] = 0x2c, + [6] = 0x4c, + [7] = 0x6c, + [8] = 0x0d, + [10] = 0x2d, + [12] = 0x4d, + [14] = 0x6d, + [16] = 0x0e, + [20] = 0x2e, + [24] = 0x4e, + [28] = 0x6e, + [32] = 0x0f, + [40] = 0x2f, + [48] = 0x4f, + [56] = 0x6f, + [64] = 0x10, + [80] = 0x30, + [96] = 0x50, + [112] = 0x70, + [128] = 0x11, +}; + +/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ +static const u8 power_limit_time_msr_to_sec[] = { + [0x00] = 0, + [0x0a] = 1, + [0x0b] = 2, + [0x4b] = 3, + [0x0c] = 4, + [0x2c] = 5, + [0x4c] = 6, + [0x6c] = 7, + [0x0d] = 8, + [0x2d] = 10, + [0x4d] = 12, + [0x6d] = 14, + [0x0e] = 16, + [0x2e] = 20, + [0x4e] = 24, + [0x6e] = 28, + [0x0f] = 32, + [0x2f] = 40, + [0x4f] = 48, + [0x6f] = 56, + [0x10] = 64, + [0x30] = 80, + [0x50] = 96, + [0x70] = 112, + [0x11] = 128, +}; + +int cpu_config_tdp_levels(void) +{ + struct cpuid_result result; + msr_t platform_info; + + /* Minimum CPU revision */ + result = cpuid(1); + if (result.eax < IVB_CONFIG_TDP_MIN_CPUID) + return 0; + + /* Bits 34:33 indicate how many levels supported */ + platform_info = msr_read(MSR_PLATFORM_INFO); + return (platform_info.hi >> 1) & 3; +} + +/* + * Configure processor power limits if possible + * This must be done AFTER set of BIOS_RESET_CPL + */ +void set_power_limits(u8 power_limit_1_time) +{ + msr_t msr = msr_read(MSR_PLATFORM_INFO); + msr_t limit; + unsigned power_unit; + unsigned tdp, min_power, max_power, max_time; + u8 power_limit_1_val; + + if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) + return; + + if (!(msr.lo & PLATFORM_INFO_SET_TDP)) + return; + + /* Get units */ + msr = msr_read(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + + /* Get power defaults for this SKU */ + msr = msr_read(MSR_PKG_POWER_SKU); + tdp = msr.lo & 0x7fff; + min_power = (msr.lo >> 16) & 0x7fff; + max_power = msr.hi & 0x7fff; + max_time = (msr.hi >> 16) & 0x7f; + + debug("CPU TDP: %u Watts\n", tdp / power_unit); + + if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) + power_limit_1_time = power_limit_time_msr_to_sec[max_time]; + + if (min_power > 0 && tdp < min_power) + tdp = min_power; + + if (max_power > 0 && tdp > max_power) + tdp = max_power; + + power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; + + /* Set long term power limit to TDP */ + limit.lo = 0; + limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + limit.lo |= PKG_POWER_LIMIT_EN; + limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << + PKG_POWER_LIMIT_TIME_SHIFT; + + /* Set short term power limit to 1.25 * TDP */ + limit.hi = 0; + limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + /* Power limit 2 time is only programmable on SNB EP/EX */ + + msr_write(MSR_PKG_POWER_LIMIT, limit); + + /* Use nominal TDP values for CPUs with configurable TDP */ + if (cpu_config_tdp_levels()) { + msr = msr_read(MSR_CONFIG_TDP_NOMINAL); + limit.hi = 0; + limit.lo = msr.lo & 0xff; + msr_write(MSR_TURBO_ACTIVATION_RATIO, limit); + } +} + +static void configure_c_states(void) +{ + struct cpuid_result result; + msr_t msr; + + msr = msr_read(MSR_PMG_CST_CONFIG_CTL); + msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */ + msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */ + msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */ + msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */ + msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */ + msr.lo |= 7; /* No package C-state limit */ + msr_write(MSR_PMG_CST_CONFIG_CTL, msr); + + msr = msr_read(MSR_PMG_IO_CAPTURE_ADR); + msr.lo &= ~0x7ffff; + msr.lo |= (PMB0_BASE + 4); /* LVL_2 base address */ + msr.lo |= (2 << 16); /* CST Range: C7 is max C-state */ + msr_write(MSR_PMG_IO_CAPTURE_ADR, msr); + + msr = msr_read(MSR_MISC_PWR_MGMT); + msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */ + msr_write(MSR_MISC_PWR_MGMT, msr); + + msr = msr_read(MSR_POWER_CTL); + msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */ + msr.lo |= (1 << 1); /* C1E Enable */ + msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */ + msr_write(MSR_POWER_CTL, msr); + + /* C3 Interrupt Response Time Limit */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50; + msr_write(MSR_PKGC3_IRTL, msr); + + /* C6 Interrupt Response Time Limit */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68; + msr_write(MSR_PKGC6_IRTL, msr); + + /* C7 Interrupt Response Time Limit */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D; + msr_write(MSR_PKGC7_IRTL, msr); + + /* Primary Plane Current Limit */ + msr = msr_read(MSR_PP0_CURRENT_CONFIG); + msr.lo &= ~0x1fff; + msr.lo |= PP0_CURRENT_LIMIT; + msr_write(MSR_PP0_CURRENT_CONFIG, msr); + + /* Secondary Plane Current Limit */ + msr = msr_read(MSR_PP1_CURRENT_CONFIG); + msr.lo &= ~0x1fff; + result = cpuid(1); + if (result.eax >= 0x30600) + msr.lo |= PP1_CURRENT_LIMIT_IVB; + else + msr.lo |= PP1_CURRENT_LIMIT_SNB; + msr_write(MSR_PP1_CURRENT_CONFIG, msr); +} + +static int configure_thermal_target(void) +{ + int tcc_offset; + msr_t msr; + int node; + + /* Find pointer to CPU configuration */ + node = fdtdec_next_compatible(gd->fdt_blob, 0, + COMPAT_INTEL_MODEL_206AX); + if (node < 0) + return -ENOENT; + tcc_offset = fdtdec_get_int(gd->fdt_blob, node, "tcc-offset", 0); + + /* Set TCC activaiton offset if supported */ + msr = msr_read(MSR_PLATFORM_INFO); + if ((msr.lo & (1 << 30)) && tcc_offset) { + msr = msr_read(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ + msr.lo |= (tcc_offset & 0xf) << 24; + msr_write(MSR_TEMPERATURE_TARGET, msr); + } + + return 0; +} + +static void configure_misc(void) +{ + msr_t msr; + + msr = msr_read(IA32_MISC_ENABLE); + msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr_write(IA32_MISC_ENABLE, msr); + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + msr_write(IA32_THERM_INTERRUPT, msr); + + /* Enable package critical interrupt only */ + msr.lo = 1 << 4; + msr.hi = 0; + msr_write(IA32_PACKAGE_THERM_INTERRUPT, msr); +} + +static void enable_lapic_tpr(void) +{ + msr_t msr; + + msr = msr_read(MSR_PIC_MSG_CONTROL); + msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ + msr_write(MSR_PIC_MSG_CONTROL, msr); +} + +static void configure_dca_cap(void) +{ + struct cpuid_result cpuid_regs; + msr_t msr; + + /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ + cpuid_regs = cpuid(1); + if (cpuid_regs.ecx & (1 << 18)) { + msr = msr_read(IA32_PLATFORM_DCA_CAP); + msr.lo |= 1; + msr_write(IA32_PLATFORM_DCA_CAP, msr); + } +} + +static void set_max_ratio(void) +{ + msr_t msr, perf_ctl; + + perf_ctl.hi = 0; + + /* Check for configurable TDP option */ + if (cpu_config_tdp_levels()) { + /* Set to nominal TDP ratio */ + msr = msr_read(MSR_CONFIG_TDP_NOMINAL); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else { + /* Platform Info bits 15:8 give max ratio */ + msr = msr_read(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; + } + msr_write(IA32_PERF_CTL, perf_ctl); + + debug("model_x06ax: frequency set to %d\n", + ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); +} + +static void set_energy_perf_bias(u8 policy) +{ + msr_t msr; + + /* Energy Policy is bits 3:0 */ + msr = msr_read(IA32_ENERGY_PERFORMANCE_BIAS); + msr.lo &= ~0xf; + msr.lo |= policy & 0xf; + msr_write(IA32_ENERGY_PERFORMANCE_BIAS, msr); + + debug("model_x06ax: energy policy set to %u\n", policy); +} + +static void configure_mca(void) +{ + msr_t msr; + int i; + + msr.lo = 0; + msr.hi = 0; + /* This should only be done on a cold boot */ + for (i = 0; i < 7; i++) + msr_write(IA32_MC0_STATUS + (i * 4), msr); +} + +#if CONFIG_USBDEBUG +static unsigned ehci_debug_addr; +#endif + +/* + * Initialize any extra cores/threads in this package. + */ +static int intel_cores_init(struct x86_cpu_priv *cpu) +{ + struct cpuid_result result; + unsigned threads_per_package, threads_per_core, i; + + /* Logical processors (threads) per core */ + result = cpuid_ext(0xb, 0); + threads_per_core = result.ebx & 0xffff; + + /* Logical processors (threads) per package */ + result = cpuid_ext(0xb, 1); + threads_per_package = result.ebx & 0xffff; + + debug("CPU: %u has %u cores, %u threads per core\n", + cpu->apic_id, threads_per_package / threads_per_core, + threads_per_core); + + for (i = 1; i < threads_per_package; ++i) { + struct x86_cpu_priv *new_cpu; + + new_cpu = calloc(1, sizeof(*new_cpu)); + if (!new_cpu) + return -ENOMEM; + + new_cpu->apic_id = cpu->apic_id + i; + + /* Update APIC ID if no hyperthreading */ + if (threads_per_core == 1) + new_cpu->apic_id <<= 1; + + debug("CPU: %u has core %u\n", cpu->apic_id, new_cpu->apic_id); + +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 + /* Start the new cpu */ + if (!start_cpu(new_cpu)) { + /* Record the error in cpu? */ + printk(BIOS_ERR, "CPU %u would not start!\n", + new_cpu->apic_id); + new_cpu->start_err = 1; + } +#endif + } + + return 0; +} + +int model_206ax_init(struct x86_cpu_priv *cpu) +{ + int ret; + + /* Clear out pending MCEs */ + configure_mca(); + +#if CONFIG_USBDEBUG + /* Is this caution really needed? */ + if (!ehci_debug_addr) + ehci_debug_addr = get_ehci_debug(); + set_ehci_debug(0); +#endif + + /* Setup MTRRs based on physical address size */ +#if 0 /* TODO: Implement this */ + struct cpuid_result cpuid_regs; + + cpuid_regs = cpuid(0x80000008); + x86_setup_fixed_mtrrs(); + x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_mtrr_check(); +#endif + +#if CONFIG_USBDEBUG + set_ehci_debug(ehci_debug_addr); +#endif + + /* Enable the local cpu apics */ + enable_lapic_tpr(); + lapic_setup(); + + /* Enable virtualization if enabled in CMOS */ + enable_vmx(); + + /* Configure C States */ + configure_c_states(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + /* Thermal throttle activation offset */ + ret = configure_thermal_target(); + if (ret) + return ret; + + /* Enable Direct Cache Access */ + configure_dca_cap(); + + /* Set energy policy */ + set_energy_perf_bias(ENERGY_POLICY_NORMAL); + + /* Set Max Ratio */ + set_max_ratio(); + + /* Enable Turbo */ + turbo_enable(); + + /* Start up extra cores */ + intel_cores_init(cpu); + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c new file mode 100644 index 0000000..c50b5de --- /dev/null +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -0,0 +1,188 @@ +/* + * From Coreboot northbridge/intel/sandybridge/northbridge.c + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium Authors + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/msr.h> +#include <asm/acpi.h> +#include <asm/cpu.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/processor.h> +#include <asm/arch/pch.h> +#include <asm/arch/model_206ax.h> +#include <asm/arch/sandybridge.h> + +static int bridge_revision_id = -1; + +int bridge_silicon_revision(void) +{ + if (bridge_revision_id < 0) { + struct cpuid_result result; + uint8_t stepping, bridge_id; + pci_dev_t dev; + + result = cpuid(1); + stepping = result.eax & 0xf; + dev = PCI_BDF(0, 0, 0); + bridge_id = pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0; + bridge_revision_id = bridge_id | stepping; + } + + return bridge_revision_id; +} + +/* + * Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) + * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI + */ +static const int legacy_hole_base_k = 0xa0000 / 1024; +static const int legacy_hole_size_k = 384; + +static int get_pcie_bar(u32 *base, u32 *len) +{ + pci_dev_t dev = PCI_BDF(0, 0, 0); + u32 pciexbar_reg; + + *base = 0; + *len = 0; + + pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + + if (!(pciexbar_reg & (1 << 0))) + return 0; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: /* 256MB */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28)); + *len = 256 * 1024 * 1024; + return 1; + case 1: /* 128M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27)); + *len = 128 * 1024 * 1024; + return 1; + case 2: /* 64M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27) | (1 << 26)); + *len = 64 * 1024 * 1024; + return 1; + } + + return 0; +} + +static void add_fixed_resources(pci_dev_t dev, int index) +{ + u32 pcie_config_base, pcie_config_size; + + if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { + debug("Adding PCIe config bar base=0x%08x size=0x%x\n", + pcie_config_base, pcie_config_size); + } +} + +static void northbridge_dmi_init(pci_dev_t dev) +{ + /* Clear error status bits */ + writel(0xffffffff, DMIBAR_REG(0x1c4)); + writel(0xffffffff, DMIBAR_REG(0x1d0)); + + /* Steps prior to DMI ASPM */ + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20), + 1 << 21); + } + + setbits_le32(DMIBAR_REG(0x238), 1 << 29); + + if (bridge_silicon_revision() >= SNB_STEP_D0) { + setbits_le32(DMIBAR_REG(0x1f8), 1 << 16); + } else if (bridge_silicon_revision() >= SNB_STEP_D1) { + clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16); + setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23)); + } + + /* Enable ASPM on SNB link, should happen before PCH link */ + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) + setbits_le32(DMIBAR_REG(0xd04), 1 << 4); + + setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0)); +} + +void northbridge_init(pci_dev_t dev) +{ + u32 bridge_type; + + add_fixed_resources(dev, 6); + northbridge_dmi_init(dev); + + bridge_type = readl(MCHBAR_REG(0x5f10)); + bridge_type &= ~0xff; + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + /* Enable Power Aware Interrupt Routing - fixed priority */ + clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4); + + /* 30h for IvyBridge */ + bridge_type |= 0x30; + } else { + /* 20h for Sandybridge */ + bridge_type |= 0x20; + } + writel(bridge_type, MCHBAR_REG(0x5f10)); + + /* + * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU + * that BIOS has initialized memory and power management + */ + setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1); + debug("Set BIOS_RESET_CPL\n"); + + /* Configure turbo power limits 1ms after reset complete bit */ + mdelay(1); + set_power_limits(28); + + /* + * CPUs with configurable TDP also need power limits set + * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. + */ + if (cpu_config_tdp_levels()) { + msr_t msr = msr_read(MSR_PKG_POWER_LIMIT); + + writel(msr.lo, MCHBAR_REG(0x59A0)); + writel(msr.hi, MCHBAR_REG(0x59A4)); + } + + /* Set here before graphics PM init */ + writel(0x00100001, MCHBAR_REG(0x5500)); +} + +void northbridge_enable(pci_dev_t dev) +{ +#if CONFIG_HAVE_ACPI_RESUME + switch (pci_read_config32(dev, SKPAD)) { + case 0xcafebabe: + debug("Normal boot.\n"); + apci_set_slp_type(0); + break; + case 0xcafed00d: + debug("S3 Resume.\n"); + apci_set_slp_type(3); + break; + default: + debug("Unknown boot method, assuming normal.\n"); + apci_set_slp_type(0); + break; + } +#endif +} diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c new file mode 100644 index 0000000..fa04d48 --- /dev/null +++ b/arch/x86/cpu/ivybridge/pch.c @@ -0,0 +1,123 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2012 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> + +static int pch_revision_id = -1; +static int pch_type = -1; + +int pch_silicon_revision(void) +{ + pci_dev_t dev; + + dev = PCH_LPC_DEV; + + if (pch_revision_id < 0) + pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID); + return pch_revision_id; +} + +int pch_silicon_type(void) +{ + pci_dev_t dev; + + dev = PCH_LPC_DEV; + + if (pch_type < 0) + pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1); + return pch_type; +} + +int pch_silicon_supported(int type, int rev) +{ + int cur_type = pch_silicon_type(); + int cur_rev = pch_silicon_revision(); + + switch (type) { + case PCH_TYPE_CPT: + /* CougarPoint minimum revision */ + if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) + return 1; + /* PantherPoint any revision */ + if (cur_type == PCH_TYPE_PPT) + return 1; + break; + + case PCH_TYPE_PPT: + /* PantherPoint minimum revision */ + if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) + return 1; + break; + } + + return 0; +} + +#define IOBP_RETRY 1000 +static inline int iobp_poll(void) +{ + unsigned try = IOBP_RETRY; + u32 data; + + while (try--) { + data = readl(RCB_REG(IOBPS)); + if ((data & 1) == 0) + return 1; + udelay(10); + } + + printf("IOBP timeout\n"); + return 0; +} + +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +{ + u32 data; + + /* Set the address */ + writel(address, RCB_REG(IOBPIRI)); + + /* READ OPCODE */ + if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + writel(IOBPS_RW_BX, RCB_REG(IOBPS)); + else + writel(IOBPS_READ_AX, RCB_REG(IOBPS)); + if (!iobp_poll()) + return; + + /* Read IOBP data */ + data = readl(RCB_REG(IOBPD)); + if (!iobp_poll()) + return; + + /* Check for successful transaction */ + if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) { + printf("IOBP read 0x%08x failed\n", address); + return; + } + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + /* WRITE OPCODE */ + if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + writel(IOBPS_RW_BX, RCB_REG(IOBPS)); + else + writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); + if (!iobp_poll()) + return; + + /* Write IOBP data */ + writel(data, RCB_REG(IOBPD)); + if (!iobp_poll()) + return; +} diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c new file mode 100644 index 0000000..452d1c3 --- /dev/null +++ b/arch/x86/cpu/ivybridge/pci.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008,2009 + * Graeme Russ, <graeme.russ@gmail.com> + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <pci.h> +#include <asm/pci.h> +#include <asm/arch/bd82x6x.h> +#include <asm/arch/pch.h> + +static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *table) +{ + u8 secondary; + + hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); + if (secondary != 0) + pci_hose_scan_bus(hose, secondary); +} + +static struct pci_config_table pci_ivybridge_config_table[] = { + /* vendor, device, class, bus, dev, func */ + { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, + {} +}; + +void board_pci_setup_hose(struct pci_controller *hose) +{ + hose->config_table = pci_ivybridge_config_table; + hose->first_busno = 0; + hose->last_busno = 0; + + /* PCI memory space */ + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 1, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); + + pci_set_region(hose->regions + 2, + CONFIG_PCI_PREF_BUS, + CONFIG_PCI_PREF_PHYS, + CONFIG_PCI_PREF_SIZE, + PCI_REGION_PREFETCH); + + hose->region_count = 3; +} + +int board_pci_pre_scan(struct pci_controller *hose) +{ + pci_dev_t dev; + u16 reg16; + + bd82x6x_init(); + + reg16 = 0xff; + dev = PCH_DEV; + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + + pci_write_bar32(hose, dev, 0, 0xf0000000); + + return 0; +} + +int board_pci_post_scan(struct pci_controller *hose) +{ + int ret; + + ret = bd82x6x_init_pci_devices(); + if (ret) { + printf("bd82x6x_init_pci_devices() failed: %d\n", ret); + return ret; + } + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/ivybridge/report_platform.c new file mode 100644 index 0000000..69e31b3 --- /dev/null +++ b/arch/x86/cpu/ivybridge/report_platform.c @@ -0,0 +1,89 @@ +/* + * From Coreboot src/northbridge/intel/sandybridge/report_platform.c + * + * Copyright (C) 2012 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/cpu.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> + +static void report_cpu_info(void) +{ + char cpu_string[CPU_MAX_NAME_LEN], *cpu_name; + const char *mode[] = {"NOT ", ""}; + struct cpuid_result cpuidr; + int vt, txt, aes; + u32 index; + + index = 0x80000000; + cpuidr = cpuid(index); + if (cpuidr.eax < 0x80000004) { + strcpy(cpu_string, "Platform info not available"); + cpu_name = cpu_string; + } else { + cpu_name = cpu_get_name(cpu_string); + } + + cpuidr = cpuid(1); + debug("CPU id(%x): %s\n", cpuidr.eax, cpu_name); + aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; + txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; + vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + debug("AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +/* The PCI id name match comes from Intel document 472178 */ +static struct { + u16 dev_id; + const char *dev_name; +} pch_table[] = { + {0x1E41, "Desktop Sample"}, + {0x1E42, "Mobile Sample"}, + {0x1E43, "SFF Sample"}, + {0x1E44, "Z77"}, + {0x1E45, "H71"}, + {0x1E46, "Z75"}, + {0x1E47, "Q77"}, + {0x1E48, "Q75"}, + {0x1E49, "B75"}, + {0x1E4A, "H77"}, + {0x1E53, "C216"}, + {0x1E55, "QM77"}, + {0x1E56, "QS77"}, + {0x1E58, "UM77"}, + {0x1E57, "HM77"}, + {0x1E59, "HM76"}, + {0x1E5D, "HM75"}, + {0x1E5E, "HM70"}, + {0x1E5F, "NM70"}, +}; + +static void report_pch_info(void) +{ + const char *pch_type = "Unknown"; + int i; + u16 dev_id; + uint8_t rev_id; + + dev_id = pci_read_config16(PCH_LPC_DEV, 2); + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].dev_id == dev_id) { + pch_type = pch_table[i].dev_name; + break; + } + } + rev_id = pci_read_config8(PCH_LPC_DEV, 8); + debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id, + rev_id); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_pch_info(); +} diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c new file mode 100644 index 0000000..bbcd47d --- /dev/null +++ b/arch/x86/cpu/ivybridge/sata.c @@ -0,0 +1,225 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <fdtdec.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> +#include <asm/arch/bd82x6x.h> + +static inline u32 sir_read(pci_dev_t dev, int idx) +{ + pci_write_config32(dev, SATA_SIRI, idx); + return pci_read_config32(dev, SATA_SIRD); +} + +static inline void sir_write(pci_dev_t dev, int idx, u32 value) +{ + pci_write_config32(dev, SATA_SIRI, idx); + pci_write_config32(dev, SATA_SIRD, value); +} + +static void common_sata_init(pci_dev_t dev, unsigned int port_map) +{ + u32 reg32; + u16 reg16; + + /* Set IDE I/O Configuration */ + reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + pci_write_config32(dev, IDE_CONFIG, reg32); + + /* Port enable */ + reg16 = pci_read_config16(dev, 0x92); + reg16 &= ~0x3f; + reg16 |= port_map; + pci_write_config16(dev, 0x92, reg16); + + /* SATA Initialization register */ + port_map &= 0xff; + pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); +} + +void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) +{ + unsigned int port_map, speed_support, port_tx; + struct pci_controller *hose = pci_bus_to_hose(0); + const char *mode; + u32 reg32; + u16 reg16; + + debug("SATA: Initializing...\n"); + + /* SATA configuration */ + port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); + speed_support = fdtdec_get_int(blob, node, + "sata_interface_speed_support", 0); + + /* Enable BARs */ + pci_write_config16(dev, PCI_COMMAND, 0x0007); + + mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); + if (!mode || !strcmp(mode, "ahci")) { + u32 abar; + + debug("SATA: Controller in AHCI mode\n"); + + /* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, INTR_LN, 0x0a); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | + IDE_PPE0 | IDE_IE0 | IDE_TIME0); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); + + /* Sync DMA */ + pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); + pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); + + common_sata_init(dev, 0x8000 | port_map); + + /* Initialize AHCI memory-mapped space */ + abar = pci_read_bar32(hose, dev, 5); + debug("ABAR: %08X\n", abar); + /* CAP (HBA Capabilities) : enable power management */ + reg32 = readl(abar + 0x00); + reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ + reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ + /* Set ISS, if available */ + if (speed_support) { + reg32 &= ~0x00f00000; + reg32 |= (speed_support & 0x03) << 20; + } + writel(reg32, abar + 0x00); + /* PI (Ports implemented) */ + writel(port_map, abar + 0x0c); + (void) readl(abar + 0x0c); /* Read back 1 */ + (void) readl(abar + 0x0c); /* Read back 2 */ + /* CAP2 (HBA Capabilities Extended)*/ + reg32 = readl(abar + 0x24); + reg32 &= ~0x00000002; + writel(reg32, abar + 0x24); + /* VSP (Vendor Specific Register */ + reg32 = readl(abar + 0xa0); + reg32 &= ~0x00000005; + writel(reg32, abar + 0xa0); + } else if (!strcmp(mode, "combined")) { + debug("SATA: Controller in combined mode\n"); + + /* No AHCI: clear AHCI base */ + pci_write_bar32(hose, dev, 5, 0x00000000); + /* And without AHCI BAR no memory decoding */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); + + pci_write_config8(dev, 0x09, 0x80); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | + IDE_PPE0 | IDE_IE0 | IDE_TIME0); + + /* Sync DMA */ + pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); + pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); + + common_sata_init(dev, port_map); + } else { + debug("SATA: Controller in plain-ide mode\n"); + + /* No AHCI: clear AHCI base */ + pci_write_bar32(hose, dev, 5, 0x00000000); + + /* And without AHCI BAR no memory decoding */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* + * Native mode capable on both primary and secondary (0xa) + * OR'ed with enabled (0x50) = 0xf + */ + pci_write_config8(dev, 0x09, 0x8f); + + /* Set Interrupt Line */ + /* Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, INTR_LN, 0xff); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | + IDE_PPE0 | IDE_IE0 | IDE_TIME0); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + IDE_SITRE | IDE_ISP_3_CLOCKS | + IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); + + /* Sync DMA */ + pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); + pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); + + common_sata_init(dev, port_map); + } + + /* Set Gen3 Transmitter settings if needed */ + port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0); + if (port_tx) + pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx); + + port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0); + if (port_tx) + pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx); + + /* Additional Programming Requirements */ + sir_write(dev, 0x04, 0x00001600); + sir_write(dev, 0x28, 0xa0000033); + reg32 = sir_read(dev, 0x54); + reg32 &= 0xff000000; + reg32 |= 0x5555aa; + sir_write(dev, 0x54, reg32); + sir_write(dev, 0x64, 0xcccc8484); + reg32 = sir_read(dev, 0x68); + reg32 &= 0xffff0000; + reg32 |= 0xcccc; + sir_write(dev, 0x68, reg32); + reg32 = sir_read(dev, 0x78); + reg32 &= 0x0000ffff; + reg32 |= 0x88880000; + sir_write(dev, 0x78, reg32); + sir_write(dev, 0x84, 0x001c7000); + sir_write(dev, 0x88, 0x88338822); + sir_write(dev, 0xa0, 0x001c7000); + sir_write(dev, 0xc4, 0x0c0c0c0c); + sir_write(dev, 0xc8, 0x0c0c0c0c); + sir_write(dev, 0xd4, 0x10000000); + + pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); + pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); +} + +void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node) +{ + unsigned port_map; + const char *mode; + u16 map = 0; + + /* + * Set SATA controller mode early so the resource allocator can + * properly assign IO/Memory resources for the controller. + */ + mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); + if (mode && !strcmp(mode, "ahci")) + map = 0x0060; + port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); + + map |= (port_map ^ 0x3f) << 8; + pci_write_config16(dev, 0x90, map); +} diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c new file mode 100644 index 0000000..df2b990 --- /dev/null +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -0,0 +1,571 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 + * Graeme Russ, <graeme.russ@gmail.com> + * + * Portions from Coreboot mainboard/google/link/romstage.c + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <malloc.h> +#include <asm/processor.h> +#include <asm/gpio.h> +#include <asm/global_data.h> +#include <asm/pci.h> +#include <asm/arch/me.h> +#include <asm/arch/pei_data.h> +#include <asm/arch/pch.h> +#include <asm/post.h> +#include <asm/arch/sandybridge.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * This function looks for the highest region of memory lower than 4GB which + * has enough space for U-Boot where U-Boot is aligned on a page boundary. + * It overrides the default implementation found elsewhere which simply + * picks the end of ram, wherever that may be. The location of the stack, + * the relocation address, and how far U-Boot is moved by relocation are + * set in the global data structure. + */ +ulong board_get_usable_ram_top(ulong total_size) +{ + struct memory_info *info = &gd->arch.meminfo; + uintptr_t dest_addr = 0; + struct memory_area *largest = NULL; + int i; + + /* Find largest area of memory below 4GB */ + + for (i = 0; i < info->num_areas; i++) { + struct memory_area *area = &info->area[i]; + + if (area->start >= 1ULL << 32) + continue; + if (!largest || area->size > largest->size) + largest = area; + } + + /* If no suitable area was found, return an error. */ + assert(largest); + if (!largest || largest->size < (2 << 20)) + panic("No available memory found for relocation"); + + dest_addr = largest->start + largest->size; + + return (ulong)dest_addr; +} + +void dram_init_banksize(void) +{ + struct memory_info *info = &gd->arch.meminfo; + int num_banks; + int i; + + for (i = 0, num_banks = 0; i < info->num_areas; i++) { + struct memory_area *area = &info->area[i]; + + if (area->start >= 1ULL << 32) + continue; + gd->bd->bi_dram[num_banks].start = area->start; + gd->bd->bi_dram[num_banks].size = area->size; + num_banks++; + } +} + +static const char *const ecc_decoder[] = { + "inactive", + "active on IO", + "disabled on IO", + "active" +}; + +/* + * Dump in the log memory controller configuration as read from the memory + * controller registers. + */ +static void report_memory_config(void) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + int i; + + addr_decoder_common = readl(MCHBAR_REG(0x5000)); + addr_decode_ch[0] = readl(MCHBAR_REG(0x5004)); + addr_decode_ch[1] = readl(MCHBAR_REG(0x5008)); + + debug("memcfg DDR3 clock %d MHz\n", + (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100); + debug("memcfg channel assignment: A: %d, B % d, C % d\n", + addr_decoder_common & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3); + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf); + debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); + debug(" enhanced interleave mode %s\n", + ((ch_conf >> 22) & 1) ? "on" : "off"); + debug(" rank interleave %s\n", + ((ch_conf >> 21) & 1) ? "on" : "off"); + debug(" DIMMA %d MB width x%d %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? 16 : 8, + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + debug(" DIMMB %d MB width x%d %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 20) & 1) ? 16 : 8, + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); + } +} + +static void post_system_agent_init(struct pei_data *pei_data) +{ + /* If PCIe init is skipped, set the PEG clock gating */ + if (!pei_data->pcie_init) + setbits_le32(MCHBAR_REG(0x7010), 1); +} + +static asmlinkage void console_tx_byte(unsigned char byte) +{ +#ifdef DEBUG + putc(byte); +#endif +} + +/** + * Find the PEI executable in the ROM and execute it. + * + * @param pei_data: configuration data for UEFI PEI reference code + */ +int sdram_initialise(struct pei_data *pei_data) +{ + unsigned version; + const char *data; + uint16_t done; + int ret; + + report_platform_info(); + + /* Wait for ME to be ready */ + ret = intel_early_me_init(); + if (ret) + return ret; + ret = intel_early_me_uma_size(); + if (ret < 0) + return ret; + + debug("Starting UEFI PEI System Agent\n"); + + /* If MRC data is not found we cannot continue S3 resume. */ + if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { + debug("Giving up in sdram_initialize: No MRC data\n"); + outb(0x6, PORT_RESET); + cpu_hlt(); + } + + /* Pass console handler in pei_data */ + pei_data->tx_byte = console_tx_byte; + + debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data)); + + data = (char *)CONFIG_X86_MRC_START; + if (data) { + int rv; + int (*func)(struct pei_data *); + + debug("Calling MRC at %p\n", data); + post_code(POST_PRE_MRC); + func = (int (*)(struct pei_data *))data; + rv = func(pei_data); + post_code(POST_MRC); + if (rv) { + switch (rv) { + case -1: + printf("PEI version mismatch.\n"); + break; + case -2: + printf("Invalid memory frequency.\n"); + break; + default: + printf("MRC returned %x.\n", rv); + } + printf("Nonzero MRC return value.\n"); + return -EFAULT; + } + } else { + printf("UEFI PEI System Agent not found.\n"); + return -ENOSYS; + } + +#if CONFIG_USBDEBUG + /* mrc.bin reconfigures USB, so reinit it to have debug */ + early_usbdebug_init(); +#endif + + version = readl(MCHBAR_REG(0x5034)); + debug("System Agent Version %d.%d.%d Build %d\n", + version >> 24 , (version >> 16) & 0xff, + (version >> 8) & 0xff, version & 0xff); + + /* + * Send ME init done for SandyBridge here. This is done inside the + * SystemAgent binary on IvyBridge + */ + done = pci_read_config32(PCH_DEV, PCI_DEVICE_ID); + done &= BASE_REV_MASK; + if (BASE_REV_SNB == done) + intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); + else + intel_early_me_status(); + + post_system_agent_init(pei_data); + report_memory_config(); + + return 0; +} + +static int copy_spd(struct pei_data *peid) +{ + const int gpio_vector[] = {41, 42, 43, 10, -1}; + int spd_index; + const void *blob = gd->fdt_blob; + int node, spd_node; + int ret, i; + + for (i = 0; ; i++) { + if (gpio_vector[i] == -1) + break; + ret = gpio_requestf(gpio_vector[i], "spd_id%d", i); + if (ret) { + debug("%s: Could not request gpio %d\n", __func__, + gpio_vector[i]); + return ret; + } + } + spd_index = gpio_get_values_as_int(gpio_vector); + debug("spd index %d\n", spd_index); + node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD); + if (node < 0) { + printf("SPD data not found.\n"); + return -ENOENT; + } + + for (spd_node = fdt_first_subnode(blob, node); + spd_node > 0; + spd_node = fdt_next_subnode(blob, spd_node)) { + const char *data; + int len; + + if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index) + continue; + data = fdt_getprop(blob, spd_node, "data", &len); + if (len < sizeof(peid->spd_data[0])) { + printf("Missing SPD data\n"); + return -EINVAL; + } + + debug("Using SDRAM SPD data for '%s'\n", + fdt_get_name(blob, spd_node, NULL)); + memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0])); + break; + } + + if (spd_node < 0) { + printf("No SPD data found for index %d\n", spd_index); + return -ENOENT; + } + + return 0; +} + +/** + * add_memory_area() - Add a new usable memory area to our list + * + * Note: @start and @end must not span the first 4GB boundary + * + * @info: Place to store memory info + * @start: Start of this memory area + * @end: End of this memory area + 1 + */ +static int add_memory_area(struct memory_info *info, + uint64_t start, uint64_t end) +{ + struct memory_area *ptr; + + if (info->num_areas == CONFIG_NR_DRAM_BANKS) + return -ENOSPC; + + ptr = &info->area[info->num_areas]; + ptr->start = start; + ptr->size = end - start; + info->total_memory += ptr->size; + if (ptr->start < (1ULL << 32)) + info->total_32bit_memory += ptr->size; + debug("%d: memory %llx size %llx, total now %llx / %llx\n", + info->num_areas, ptr->start, ptr->size, + info->total_32bit_memory, info->total_memory); + info->num_areas++; + + return 0; +} + +/** + * sdram_find() - Find available memory + * + * This is a bit complicated since on x86 there are system memory holes all + * over the place. We create a list of available memory blocks + */ +static int sdram_find(pci_dev_t dev) +{ + struct memory_info *info = &gd->arch.meminfo; + uint32_t tseg_base, uma_size, tolud; + uint64_t tom, me_base, touud; + uint64_t uma_memory_base = 0; + uint64_t uma_memory_size; + unsigned long long tomk; + uint16_t ggc; + + /* Total Memory 2GB example: + * + * 00000000 0000MB-1992MB 1992MB RAM (writeback) + * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) + * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) + * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) + * 7f200000 2034MB TOLUD + * 7f800000 2040MB MEBASE + * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) + * 80000000 2048MB TOM + * 100000000 4096MB-4102MB 6MB RAM (writeback) + * + * Total Memory 4GB example: + * + * 00000000 0000MB-2768MB 2768MB RAM (writeback) + * ad000000 2768MB-2776MB 8MB TSEG (SMRR) + * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) + * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) + * afa00000 2810MB TOLUD + * ff800000 4088MB MEBASE + * ff800000 4088MB-4096MB 8MB ME UMA (uncached) + * 100000000 4096MB TOM + * 100000000 4096MB-5374MB 1278MB RAM (writeback) + * 14fe00000 5368MB TOUUD + */ + + /* Top of Upper Usable DRAM, including remap */ + touud = pci_read_config32(dev, TOUUD+4); + touud <<= 32; + touud |= pci_read_config32(dev, TOUUD); + + /* Top of Lower Usable DRAM */ + tolud = pci_read_config32(dev, TOLUD); + + /* Top of Memory - does not account for any UMA */ + tom = pci_read_config32(dev, 0xa4); + tom <<= 32; + tom |= pci_read_config32(dev, 0xa0); + + debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom); + + /* ME UMA needs excluding if total memory <4GB */ + me_base = pci_read_config32(dev, 0x74); + me_base <<= 32; + me_base |= pci_read_config32(dev, 0x70); + + debug("MEBASE %llx\n", me_base); + + /* TODO: Get rid of all this shifting by 10 bits */ + tomk = tolud >> 10; + if (me_base == tolud) { + /* ME is from MEBASE-TOM */ + uma_size = (tom - me_base) >> 10; + /* Increment TOLUD to account for ME as RAM */ + tolud += uma_size << 10; + /* UMA starts at old TOLUD */ + uma_memory_base = tomk * 1024ULL; + uma_memory_size = uma_size * 1024ULL; + debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10); + } + + /* Graphics memory comes next */ + ggc = pci_read_config16(dev, GGC); + if (!(ggc & 2)) { + debug("IGD decoded, subtracting "); + + /* Graphics memory */ + uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; + debug("%uM UMA", uma_size >> 10); + tomk -= uma_size; + uma_memory_base = tomk * 1024ULL; + uma_memory_size += uma_size * 1024ULL; + + /* GTT Graphics Stolen Memory Size (GGMS) */ + uma_size = ((ggc >> 8) & 0x3) * 1024ULL; + tomk -= uma_size; + uma_memory_base = tomk * 1024ULL; + uma_memory_size += uma_size * 1024ULL; + debug(" and %uM GTT\n", uma_size >> 10); + } + + /* Calculate TSEG size from its base which must be below GTT */ + tseg_base = pci_read_config32(dev, 0xb8); + uma_size = (uma_memory_base - tseg_base) >> 10; + tomk -= uma_size; + uma_memory_base = tomk * 1024ULL; + uma_memory_size += uma_size * 1024ULL; + debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); + + debug("Available memory below 4GB: %lluM\n", tomk >> 10); + + /* Report the memory regions */ + add_memory_area(info, 1 << 20, 2 << 28); + add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28); + add_memory_area(info, (4 << 28) + (2 << 20), tseg_base); + add_memory_area(info, 1ULL << 32, touud); + /* + * If >= 4GB installed then memory from TOLUD to 4GB + * is remapped above TOM, TOUUD will account for both + */ + if (touud > (1ULL << 32ULL)) { + debug("Available memory above 4GB: %lluM\n", + (touud >> 20) - 4096); + } + + return 0; +} + +static void rcba_config(void) +{ + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P3IP WLAN INTA -> PIRQB + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * TRACKPAD -> PIRQE (Edge Triggered) + * TOUCHSCREEN -> PIRQG (Edge Triggered) + */ + + /* Device interrupt pin register (board specific) */ + writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP)); + writel(NOINT << D30IP_PIP, RCB_REG(D30IP)); + writel(INTA << D29IP_E1P, RCB_REG(D29IP)); + writel(INTA << D28IP_P3IP, RCB_REG(D28IP)); + writel(INTA << D27IP_ZIP, RCB_REG(D27IP)); + writel(INTA << D26IP_E2P, RCB_REG(D26IP)); + writel(NOINT << D25IP_LIP, RCB_REG(D25IP)); + writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP)); + + /* Device interrupt route registers */ + writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR)); + writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR)); + writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR)); + writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR)); + writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR)); + writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR)); + writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR)); + + /* Enable IOAPIC (generic) */ + writew(0x0100, RCB_REG(OIC)); + /* PCH BWG says to read back the IOAPIC enable register */ + (void)readw(RCB_REG(OIC)); + + /* Disable unused devices (board specific) */ + setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); +} + +int dram_init(void) +{ + struct pei_data pei_data __aligned(8) = { + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .ddr3lv_support = 1, + /* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { + /* + * Empty and onboard Ports 0-7, set to un-used pin + * OC3 + */ + { 0, 3, 0x0000 }, /* P0= Empty */ + { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */ + { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */ + { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */ + { 0, 3, 0x0000 }, /* P4= Empty */ + { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */ + { 0, 3, 0x0000 }, /* P6= Empty */ + { 0, 3, 0x0000 }, /* P7= Empty */ + /* + * Empty and onboard Ports 8-13, set to un-used pin + * OC4 + */ + { 1, 4, 0x0040 }, /* P8= Camera (no OC) */ + { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */ + { 0, 4, 0x0000 }, /* P10= Empty */ + { 0, 4, 0x0000 }, /* P11= Empty */ + { 0, 4, 0x0000 }, /* P12= Empty */ + { 0, 4, 0x0000 }, /* P13= Empty */ + }, + }; + pci_dev_t dev = PCI_BDF(0, 0, 0); + int ret; + + debug("Boot mode %d\n", gd->arch.pei_boot_mode); + debug("mcr_input %p\n", pei_data.mrc_input); + pei_data.boot_mode = gd->arch.pei_boot_mode; + ret = copy_spd(&pei_data); + if (!ret) + ret = sdram_initialise(&pei_data); + if (ret) + return ret; + + rcba_config(); + quick_ram_check(); + + writew(0xCAFE, MCHBAR_REG(SSKPD)); + + post_code(POST_DRAM); + + ret = sdram_find(dev); + if (ret) + return ret; + + gd->ram_size = gd->arch.meminfo.total_32bit_memory; + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c new file mode 100644 index 0000000..291c971 --- /dev/null +++ b/arch/x86/cpu/ivybridge/usb_ehci.c @@ -0,0 +1,29 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> + +void bd82x6x_usb_ehci_init(pci_dev_t dev) +{ + u32 reg32; + + /* Disable Wake on Disconnect in RMH */ + reg32 = readl(RCB_REG(0x35b0)); + reg32 |= 0x22; + writel(reg32, RCB_REG(0x35b0)); + + debug("EHCI: Setting up controller.. "); + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER; + /* reg32 |= PCI_COMMAND_SERR; */ + pci_write_config32(dev, PCI_COMMAND, reg32); + + debug("done.\n"); +} diff --git a/arch/x86/cpu/ivybridge/usb_xhci.c b/arch/x86/cpu/ivybridge/usb_xhci.c new file mode 100644 index 0000000..4a32a7e --- /dev/null +++ b/arch/x86/cpu/ivybridge/usb_xhci.c @@ -0,0 +1,32 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> + +void bd82x6x_usb_xhci_init(pci_dev_t dev) +{ + u32 reg32; + + debug("XHCI: Setting up controller.. "); + + /* lock overcurrent map */ + reg32 = pci_read_config32(dev, 0x44); + reg32 |= 1; + pci_write_config32(dev, 0x44, reg32); + + /* Enable clock gating */ + reg32 = pci_read_config32(dev, 0x40); + reg32 &= ~((1 << 20) | (1 << 21)); + reg32 |= (1 << 19) | (1 << 18) | (1 << 17); + reg32 |= (1 << 10) | (1 << 9) | (1 << 8); + reg32 |= (1 << 31); /* lock */ + pci_write_config32(dev, 0x40, reg32); + + debug("done.\n"); +} diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c new file mode 100644 index 0000000..4690603 --- /dev/null +++ b/arch/x86/cpu/lapic.c @@ -0,0 +1,57 @@ +/* + * From coreboot file of same name + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/msr.h> +#include <asm/io.h> +#include <asm/lapic.h> +#include <asm/post.h> + +void lapic_setup(void) +{ +#if NEED_LAPIC == 1 + /* Only Pentium Pro and later have those MSR stuff */ + debug("Setting up local apic: "); + + /* Enable the local apic */ + enable_lapic(); + + /* + * Set Task Priority to 'accept all'. + */ + lapic_write_around(LAPIC_TASKPRI, + lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK); + + /* Put the local apic in virtual wire mode */ + lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) & + ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE); + lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) & + ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | + LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | + LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 | + LAPIC_DELIVERY_MODE_MASK)) | + (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING | + LAPIC_DELIVERY_MODE_EXTINT)); + lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) & + ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | + LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | + LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 | + LAPIC_DELIVERY_MODE_MASK)) | + (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING | + LAPIC_DELIVERY_MODE_NMI)); + + debug("apic_id: 0x%02lx, ", lapicid()); +#else /* !NEED_LLAPIC */ + /* Only Pentium Pro and later have those MSR stuff */ + debug("Disabling local apic: "); + disable_lapic(); +#endif /* !NEED_LAPIC */ + debug("done.\n"); + post_code(POST_LAPIC); +} diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c new file mode 100644 index 0000000..f3492c3 --- /dev/null +++ b/arch/x86/cpu/pci.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008,2009 + * Graeme Russ, <graeme.russ@gmail.com> + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <malloc.h> +#include <pci.h> +#include <asm/pci.h> + +static struct pci_controller x86_hose; + +int pci_early_init_hose(struct pci_controller **hosep) +{ + struct pci_controller *hose; + + hose = calloc(1, sizeof(struct pci_controller)); + if (!hose) + return -ENOMEM; + + board_pci_setup_hose(hose); + pci_setup_type1(hose); + gd->arch.hose = hose; + *hosep = hose; + + return 0; +} + +__weak int board_pci_pre_scan(struct pci_controller *hose) +{ + return 0; +} + +__weak int board_pci_post_scan(struct pci_controller *hose) +{ + return 0; +} + +void pci_init_board(void) +{ + struct pci_controller *hose = &x86_hose; + + /* Stop using the early hose */ + gd->arch.hose = NULL; + + board_pci_setup_hose(hose); + pci_setup_type1(hose); + pci_register_hose(hose); + + board_pci_pre_scan(hose); + hose->last_busno = pci_hose_scan(hose); + board_pci_post_scan(hose); +} + +static struct pci_controller *get_hose(void) +{ + if (gd->arch.hose) + return gd->arch.hose; + + return pci_bus_to_hose(0); +} + +unsigned int pci_read_config8(pci_dev_t dev, unsigned where) +{ + uint8_t value; + + pci_hose_read_config_byte(get_hose(), dev, where, &value); + + return value; +} + +unsigned int pci_read_config16(pci_dev_t dev, unsigned where) +{ + uint16_t value; + + pci_hose_read_config_word(get_hose(), dev, where, &value); + + return value; +} + +unsigned int pci_read_config32(pci_dev_t dev, unsigned where) +{ + uint32_t value; + + pci_hose_read_config_dword(get_hose(), dev, where, &value); + + return value; +} + +void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value) +{ + pci_hose_write_config_byte(get_hose(), dev, where, value); +} + +void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value) +{ + pci_hose_write_config_word(get_hose(), dev, where, value); +} + +void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value) +{ + pci_hose_write_config_dword(get_hose(), dev, where, value); +} diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 338bab1..b0d0ac0 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -13,6 +13,7 @@ #include <config.h> #include <version.h> #include <asm/global_data.h> +#include <asm/post.h> #include <asm/processor.h> #include <asm/processor-flags.h> #include <generated/generic-asm-offsets.h> @@ -49,6 +50,8 @@ _start: */ movw $GD_FLG_COLD_BOOT, %bx 1: + /* Save BIST */ + movl %eax, %ebp /* Load the segement registes to match the gdt loaded in start16.S */ movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax @@ -65,6 +68,7 @@ _start: jmp early_board_init .globl early_board_init_ret early_board_init_ret: + post_code(POST_START) /* Initialise Cache-As-RAM */ jmp car_init @@ -74,16 +78,29 @@ car_init_ret: * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM, * or fully initialised SDRAM - we really don't care which) * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack + * and early malloc area. The MRC requires some space at the top. + * + * Stack grows down from top of CAR. We have: + * + * top-> CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE + * MRC area + * global_data + * x86 global descriptor table + * early malloc area + * stack + * bottom-> CONFIG_SYS_CAR_ADDR */ - - /* Stack grows down from top of CAR */ - movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE), %esp + movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp +#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE + subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp +#endif /* Reserve space on stack for global data */ subl $GENERATED_GBL_DATA_SIZE, %esp /* Align global data to 16-byte boundary */ andl $0xfffffff0, %esp + post_code(POST_START_STACK) /* Zero the global data since it won't happen later */ xorl %eax, %eax @@ -91,31 +108,36 @@ car_init_ret: movl %esp, %edi rep stosb - /* Setup first parameter to setup_gdt */ + /* Setup first parameter to setup_gdt, pointer to global_data */ movl %esp, %eax /* Reserve space for global descriptor table */ subl $X86_GDT_SIZE, %esp + /* Align temporary global descriptor table to 16-byte boundary */ + andl $0xfffffff0, %esp + movl %esp, %ecx + #if defined(CONFIG_SYS_MALLOC_F_LEN) subl $CONFIG_SYS_MALLOC_F_LEN, %esp movl %eax, %edx addl $GD_MALLOC_BASE, %edx movl %esp, (%edx) #endif - - /* Align temporary global descriptor table to 16-byte boundary */ - andl $0xfffffff0, %esp + /* Store BIST */ + movl %eax, %edx + addl $GD_BIST, %edx + movl %ebp, (%edx) /* Set second parameter to setup_gdt */ - movl %esp, %edx + movl %ecx, %edx /* Setup global descriptor table so gd->xyz works */ call setup_gdt /* Set parameter to board_init_f() to boot flags */ + post_code(POST_START_DONE) xorl %eax, %eax - movw %bx, %ax /* Enter, U-boot! */ call board_init_f diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index 6968fda..9550502 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -21,18 +21,16 @@ .code16 .globl start16 start16: + /* Save BIST */ + movl %eax, %ecx + /* Set the Cold Boot / Hard Reset flag */ movl $GD_FLG_COLD_BOOT, %ebx - /* - * First we let the BSP do some early initialization - * this code have to map the flash to its final position - */ - jmp board_init16 -.globl board_init16_ret -board_init16_ret: + xorl %eax, %eax + movl %eax, %cr3 /* Invalidate TLB */ - /* Turn of cache (this might require a 486-class CPU) */ + /* Turn off cache (this might require a 486-class CPU) */ movl %cr0, %eax orl $(X86_CR0_NW | X86_CR0_CD), %eax movl %eax, %cr0 @@ -50,9 +48,11 @@ o32 cs lgdt gdt_ptr /* Flush the prefetch queue */ jmp ff ff: - /* Finally jump to the 32bit initialization code */ + + /* Finally restore BIST and jump to the 32bit initialization code */ movw $code32start, %ax movw %ax, %bp + movl %ecx, %eax o32 cs ljmp *(%bp) /* 48-bit far pointer */ diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c new file mode 100644 index 0000000..254d0de --- /dev/null +++ b/arch/x86/cpu/turbo.c @@ -0,0 +1,98 @@ +/* + * From Coreboot file of the same name + * + * Copyright (C) 2011 The Chromium Authors. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/cpu.h> +#include <asm/msr.h> +#include <asm/processor.h> +#include <asm/turbo.h> + +#if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED +static inline int get_global_turbo_state(void) +{ + return TURBO_UNKNOWN; +} + +static inline void set_global_turbo_state(int state) +{ +} +#else +static int g_turbo_state = TURBO_UNKNOWN; + +static inline int get_global_turbo_state(void) +{ + return g_turbo_state; +} + +static inline void set_global_turbo_state(int state) +{ + g_turbo_state = state; +} +#endif + +static const char *const turbo_state_desc[] = { + [TURBO_UNKNOWN] = "unknown", + [TURBO_UNAVAILABLE] = "unavailable", + [TURBO_DISABLED] = "available but hidden", + [TURBO_ENABLED] = "available and visible" +}; + +/* + * Determine the current state of Turbo and cache it for later. + * Turbo is a package level config so it does not need to be + * enabled on every core. + */ +int turbo_get_state(void) +{ + struct cpuid_result cpuid_regs; + int turbo_en, turbo_cap; + msr_t msr; + int turbo_state = get_global_turbo_state(); + + /* Return cached state if available */ + if (turbo_state != TURBO_UNKNOWN) + return turbo_state; + + cpuid_regs = cpuid(CPUID_LEAF_PM); + turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE); + + msr = msr_read(MSR_IA32_MISC_ENABLES); + turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO); + + if (!turbo_cap && turbo_en) { + /* Unavailable */ + turbo_state = TURBO_UNAVAILABLE; + } else if (!turbo_cap && !turbo_en) { + /* Available but disabled */ + turbo_state = TURBO_DISABLED; + } else if (turbo_cap && turbo_en) { + /* Available */ + turbo_state = TURBO_ENABLED; + } + + set_global_turbo_state(turbo_state); + debug("Turbo is %s\n", turbo_state_desc[turbo_state]); + return turbo_state; +} + +void turbo_enable(void) +{ + msr_t msr; + + /* Only possible if turbo is available but hidden */ + if (turbo_get_state() == TURBO_DISABLED) { + /* Clear Turbo Disable bit in Misc Enables */ + msr = msr_read(MSR_IA32_MISC_ENABLES); + msr.hi &= ~H_MISC_DISABLE_TURBO; + msr_write(MSR_IA32_MISC_ENABLES, msr); + + /* Update cached turbo state */ + set_global_turbo_state(TURBO_ENABLED); + debug("Turbo has been enabled\n"); + } +} diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index f48bff5..b0d8531 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -44,7 +44,9 @@ SECTIONS . = ALIGN(4); __rel_dyn_start = .; - .rel.dyn : { *(.rel.dyn) } + .rel.dyn : { + *(.rel*) + } __rel_dyn_end = .; . = ALIGN(4); _end = .; @@ -64,15 +66,19 @@ SECTIONS /DISCARD/ : { *(.gnu*) } #ifdef CONFIG_X86_RESET_VECTOR - /* * The following expressions place the 16-bit Real-Mode code and * Reset Vector at the end of the Flash ROM */ - . = START_16; - .start16 : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + START_16)) { KEEP(*(.start16)); } + . = START_16 - RESET_SEG_START; + .start16 : AT (START_16) { + KEEP(*(.start16)); + } - . = RESET_VEC_LOC; - .resetvec : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); } + . = RESET_VEC_LOC - RESET_SEG_START; + .resetvec : AT (RESET_VEC_LOC) { + KEEP(*(.resetvec)); + } #endif + } diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 48265ef..bb3b116 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,4 +1,5 @@ dtb-y += link.dtb \ + chromebook_link.dtb \ alex.dtb targets += $(dtb-y) diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts new file mode 120000 index 0000000..6f8c5cd --- /dev/null +++ b/arch/x86/dts/chromebook_link.dts @@ -0,0 +1 @@ +link.dts
\ No newline at end of file diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts index f2fcb39..592af16 100644 --- a/arch/x86/dts/link.dts +++ b/arch/x86/dts/link.dts @@ -14,18 +14,21 @@ gpioa { compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; reg = <0 0x10>; bank-name = "A"; }; gpiob { compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; reg = <0x30 0x10>; bank-name = "B"; }; gpioc { compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; reg = <0x40 0x10>; bank-name = "C"; }; @@ -38,6 +41,117 @@ chosen { }; memory { device_type = "memory"; reg = <0 0>; }; + spd { + compatible = "memory-spd"; + #address-cells = <1>; + #size-cells = <0>; + elpida_4Gb_1600_x16 { + reg = <0>; + data = [92 10 0b 03 04 19 02 02 + 03 52 01 08 0a 00 fe 00 + 69 78 69 3c 69 11 18 81 + 20 08 3c 3c 01 40 83 81 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 0f 11 42 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 02 fe 00 + 11 52 00 00 00 07 7f 37 + 45 42 4a 32 30 55 47 36 + 45 42 55 30 2d 47 4e 2d + 46 20 30 20 02 fe 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00]; + }; + samsung_4Gb_1600_1.35v_x16 { + reg = <1>; + data = [92 11 0b 03 04 19 02 02 + 03 11 01 08 0a 00 fe 00 + 69 78 69 3c 69 11 18 81 + f0 0a 3c 3c 01 40 83 01 + 00 80 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 0f 11 02 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 80 ce 01 + 00 00 00 00 00 00 6a 04 + 4d 34 37 31 42 35 36 37 + 34 42 48 30 2d 59 4b 30 + 20 20 00 00 80 ce 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00]; + }; + micron_4Gb_1600_1.35v_x16 { + reg = <2>; + data = [92 11 0b 03 04 19 02 02 + 03 11 01 08 0a 00 fe 00 + 69 78 69 3c 69 11 18 81 + 20 08 3c 3c 01 40 83 05 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 0f 01 02 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 80 2c 00 + 00 00 00 00 00 00 ad 75 + 34 4b 54 46 32 35 36 36 + 34 48 5a 2d 31 47 36 45 + 31 20 45 31 80 2c 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff]; + }; + }; + spi { #address-cells = <1>; #size-cells = <0>; @@ -49,21 +163,62 @@ }; }; - lpc { - compatible = "intel,lpc"; - #address-cells = <1>; - #size-cells = <1>; - cros-ec@200 { - compatible = "google,cros-ec"; - reg = <0x204 1 0x200 1 0x880 0x80>; + pci { + sata { + compatible = "intel,pantherpoint-ahci"; + intel,sata-mode = "ahci"; + intel,sata-port-map = <1>; + intel,sata-port0-gen3-tx = <0x00880a7f>; + }; - /* This describes the flash memory within the EC */ + gma { + compatible = "intel,gma"; + intel,dp_hotplug = <0 0 0x06>; + intel,panel-port-select = <1>; + intel,panel-power-cycle-delay = <6>; + intel,panel-power-up-delay = <2000>; + intel,panel-power-down-delay = <500>; + intel,panel-power-backlight-on-delay = <2000>; + intel,panel-power-backlight-off-delay = <2000>; + intel,cpu-backlight = <0x00000200>; + intel,pch-backlight = <0x04000000>; + }; + + lpc { + compatible = "intel,lpc"; #address-cells = <1>; #size-cells = <1>; - flash@8000000 { - reg = <0x08000000 0x20000>; - erase-value = <0xff>; + gen-dec = <0x800 0xfc 0x900 0xfc>; + intel,gen-dec = <0x800 0xfc 0x900 0xfc>; + intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b + 0x80 0x80 0x80 0x80>; + intel,gpi-routing = <0 0 0 0 0 0 0 2 + 1 0 0 0 0 0 0 0>; + /* Enable EC SMI source */ + intel,alt-gp-smi-enable = <0x0100>; + + cros-ec@200 { + compatible = "google,cros-ec"; + reg = <0x204 1 0x200 1 0x880 0x80>; + + /* Describes the flash memory within the EC */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0xff>; + }; }; }; }; + + microcode { + update@0 { +#include "m12206a7_00000028.dtsi" + }; + update@1 { +#include "m12306a9_00000017.dtsi" + }; + }; + }; diff --git a/arch/x86/dts/m12206a7_00000028.dtsi b/arch/x86/dts/m12206a7_00000028.dtsi new file mode 100644 index 0000000..bcd5248 --- /dev/null +++ b/arch/x86/dts/m12206a7_00000028.dtsi @@ -0,0 +1,622 @@ +/* + * Copyright (c) <1995-2013>, Intel Corporation. + * All rights reserved. + * + * Redistribution. Redistribution and use in binary form, without modification, are + * permitted provided that the following conditions are met: + * .Redistributions must reproduce the above copyright notice and the following + * disclaimer in the documentation and/or other materials provided with the + * distribution. + * Neither the name of Intel Corporation nor the names of its suppliers may be used + * to endorse or promote products derived from this software without specific prior + * written permission. + * .No reverse engineering, decompilation, or disassembly of this software is + * permitted. + * ."Binary form" includes any format commonly used for electronic conveyance + * which is a reversible, bit-exact translation of binary representation to ASCII or + * ISO text, for example, "uuencode." + * + * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *--- + * This is a device tree fragment. Use #include to add these properties to a + * node. + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x28>; +intel,date-code = <0x04242012>; +intel,processor-signature = <0x000206a7>; +intel,checksum = <0xf3e9935d>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The 48-byte public header is omitted. */ +data = < + 0x00000000 0x000000a1 0x00020001 0x00000028 + 0x00000000 0x00000000 0x20120423 0x000008f1 + 0x00000001 0x000206a7 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000008f1 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x52b813ac 0xdb8994c7 0x70e9f6bb 0x9d6db2ff + 0xf4d70f5d 0x5b1eccf6 0xac59106f 0x0ae2e2c1 + 0x1a7bbeb1 0x355a1d62 0x2e7eb594 0x09f8dea9 + 0x432a49e4 0xbf520253 0xdafa4010 0x893a858a + 0x766e0efb 0xd91e196d 0x838bd2ef 0xe5146494 + 0xd515f413 0x29704828 0xe85598b6 0xdcbe6c51 + 0x88eabbfa 0xa1e8909f 0xd8931721 0x35386554 + 0x089a78a7 0xd9914775 0xd4644748 0x1556a4dc + 0xf44448f6 0xd054d7db 0xf30f2b7d 0x5ae223d0 + 0xcbbb48b0 0x5c8b0383 0x177de157 0x9c1e5f73 + 0x2ec28289 0xd72a7b6c 0x823b6eb2 0x35e02171 + 0xba8deae4 0x06f4d468 0x13dbafaa 0x72b419f1 + 0x033385b5 0x05806920 0x4c6034cf 0x9bd117dc + 0x976e2d04 0x250330f0 0x7250b5e1 0x184980c2 + 0x12a9d7d6 0x1bc808f9 0xae79994f 0xc6f87901 + 0xc0e3132f 0x671491c5 0x236cad39 0x37889d9c + 0x67f7c3f3 0x964a6be5 0xbcced7da 0x57eeaa6e + 0x7bca1522 0x654fee4c 0x2a1ca5d9 0xa1803cf3 + 0x00000011 0x8c316d2c 0x17603b7e 0x32e42981 + 0xc26c1400 0xf0fbccb6 0xeab6b43a 0x11d456a5 + 0x5b912d46 0x15195fe0 0x542f6db3 0x0b7f212e + 0x47718dd9 0x7c41b108 0x06c21111 0x4445d5ea + 0xb4fb8128 0xe07404a6 0x8d503da4 0x78fc7e44 + 0xb9919656 0x9968c797 0x87f26ab0 0x23bb1af7 + 0x1ec5d761 0x26f30d2c 0x7cdb747c 0xe4d42033 + 0x8a5d4801 0x768aff57 0xbcfd5d11 0x7c853c2d + 0x231e6207 0x8b1988a6 0xd68fdb75 0x58dcb417 + 0x44422ef9 0x2a186ebb 0x7d27e85f 0x36ac31f7 + 0x1e487e77 0x2b0b8c37 0xd8ba682f 0x2cba791b + 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* All rights reserved. + * + * Redistribution. Redistribution and use in binary form, without modification, are + * permitted provided that the following conditions are met: + * .Redistributions must reproduce the above copyright notice and the following + * disclaimer in the documentation and/or other materials provided with the + * distribution. + * Neither the name of Intel Corporation nor the names of its suppliers may be used + * to endorse or promote products derived from this software without specific prior + * written permission. + * .No reverse engineering, decompilation, or disassembly of this software is + * permitted. + * ."Binary form" includes any format commonly used for electronic conveyance + * which is a reversible, bit-exact translation of binary representation to ASCII or + * ISO text, for example, "uuencode." + * + * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *--- + * This is a device tree fragment. Use #include to add these properties to a + * node. + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x17>; +intel,date-code = <0x01092013>; +intel,processor-signature = <0x000306a9>; +intel,checksum = <0x3546450b>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The 48-byte public header is omitted. */ +data = < + 0x00000000 0x000000a1 0x00020001 0x00000017 + 0x00000000 0x00000000 0x20130107 0x00000a61 + 0x00000001 0x000306a9 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x86c5b0d4 0xf6978804 0x7f4f5870 0x6319dc3c + 0xbb3b7d61 0x33cf9075 0xe8424658 0xf611a357 + 0x5a3401db 0x42caecce 0xb4d8e75e 0xe6dbaf24 + 0x7861b35f 0x6bd717bc 0x23b9b731 0x82ec1ac8 + 0x20337b64 0x5396dbf1 0x59973bff 0x724bc7e9 + 0x5237193b 0x0b8647c1 0x6a0d0e16 0xbf9ddb5b + 0xace2cc1c 0xad707638 0x056f102f 0xa37e60f8 + 0x76255642 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0x5fdfa5da 0x02ef9bb2 + 0x792d3194 0xbed63f21 0x0b6dc5f1 0xc9d7fe08 + 0x6df7883d 0x366566cf 0xef772769 0x37826465 + 0x1cdc3086 0xa69ff7b6 0x235012ea 0x292f7e75 + 0x30bdd0fd 0xffdc9df1 0x95c6d570 0xec206204 + 0xc6cd42cb 0xc0d6dfd9 0xb7a16b71 0x17fa527e + 0x295f2c79 0x990f9820 0x8b8f447d 0x193f9ad1 + 0xebddb2af 0x5dd532eb 0xf1bbd8e8 0x3444a3f4 + 0x18ccce93 0x05edeb4f 0xc4a6b935 0xba37aab0 + 0x96076ba4 0x250dc2f7 0xc4093548 0x030e777d + 0x7ea40933 0x8da7b1dd 0x59c0b79f 0x807d437c + 0xf5233ddf 0x54c1983f 0xfc18771b 0xe74b85f0 + 0xdbd725b5 0x70cdd153 0x4ffe300c 0xfda4bdae + 0xf4ac75d2 0x91c4e15a 0x34d92b97 0x16356a79 + >; diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h new file mode 100644 index 0000000..4872b92 --- /dev/null +++ b/arch/x86/include/asm/acpi.h @@ -0,0 +1,24 @@ +/* + * From coreboot + * + * Copyright (C) 2004 SUSE LINUX AG + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2008-2009 coresystems GmbH + * (Written by Stefan Reinauer <stepan@coresystems.de>) + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ACPI_H +#define __ASM_ACPI_H + +#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ +#define ACPI_TABLE_CREATOR "U-BootAC" /* Must be exactly 8 bytes long! */ +#define OEM_ID "U-Boot" /* Must be exactly 6 bytes long! */ +#define ASLC "U-Bo" /* Must be exactly 4 bytes long! */ + +/* 0 = S0, 1 = S1 ...*/ +int acpi_get_slp_type(void); +void apci_set_slp_type(int type); + +#endif diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h index 3ec1816..4951a8c 100644 --- a/arch/x86/include/asm/arch-coreboot/gpio.h +++ b/arch/x86/include/asm/arch-coreboot/gpio.h @@ -7,9 +7,4 @@ #ifndef _X86_ARCH_GPIO_H_ #define _X86_ARCH_GPIO_H_ -struct ich6_bank_platdata { - uint32_t base_addr; - const char *bank_name; -}; - #endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-coreboot/sysinfo.h b/arch/x86/include/asm/arch-coreboot/sysinfo.h index 8e4a61d..832c50a 100644 --- a/arch/x86/include/asm/arch-coreboot/sysinfo.h +++ b/arch/x86/include/asm/arch-coreboot/sysinfo.h @@ -10,7 +10,7 @@ #define _COREBOOT_SYSINFO_H #include <common.h> -#include <compiler.h> +#include <linux/compiler.h> #include <libfdt.h> #include <asm/arch/tables.h> diff --git a/arch/x86/include/asm/arch-coreboot/tables.h b/arch/x86/include/asm/arch-coreboot/tables.h index 0d02fe0..e254484 100644 --- a/arch/x86/include/asm/arch-coreboot/tables.h +++ b/arch/x86/include/asm/arch-coreboot/tables.h @@ -9,7 +9,7 @@ #ifndef _COREBOOT_TABLES_H #define _COREBOOT_TABLES_H -#include <compiler.h> +#include <linux/compiler.h> struct cbuint64 { u32 lo; diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h new file mode 100644 index 0000000..e1d9a9b --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_BD82X6X_H +#define _ASM_ARCH_BD82X6X_H + +void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node); +void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node); +void bd82x6x_pci_init(pci_dev_t dev); +void bd82x6x_usb_ehci_init(pci_dev_t dev); +void bd82x6x_usb_xhci_init(pci_dev_t dev); +int bd82x6x_init_pci_devices(void); +int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, + const void *blob, int node); +int bd82x6x_init(void); + +struct x86_cpu_priv; +int model_206ax_init(struct x86_cpu_priv *cpu); + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h b/arch/x86/include/asm/arch-ivybridge/gpio.h new file mode 100644 index 0000000..4951a8c --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/gpio.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2014, Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_ARCH_GPIO_H_ +#define _X86_ARCH_GPIO_H_ + +#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h new file mode 100644 index 0000000..3a0809d --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/me.h @@ -0,0 +1,356 @@ +/* + * From Coreboot src/southbridge/intel/bd82x6x/me.h + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_INTEL_ME_H +#define _ASM_INTEL_ME_H + +#include <linux/compiler.h> +#include <linux/types.h> + +#define ME_RETRY 100000 /* 1 second */ +#define ME_DELAY 10 /* 10 us */ + +/* + * Management Engine PCI registers + */ + +#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ +#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ + +#define PCI_ME_HFS 0x40 +#define ME_HFS_CWS_RESET 0 +#define ME_HFS_CWS_INIT 1 +#define ME_HFS_CWS_REC 2 +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_CWS_WAIT 6 +#define ME_HFS_CWS_TRANS 7 +#define ME_HFS_CWS_INVALID 8 +#define ME_HFS_STATE_PREBOOT 0 +#define ME_HFS_STATE_M0_UMA 1 +#define ME_HFS_STATE_M3 4 +#define ME_HFS_STATE_M0 5 +#define ME_HFS_STATE_BRINGUP 6 +#define ME_HFS_STATE_ERROR 7 +#define ME_HFS_ERROR_NONE 0 +#define ME_HFS_ERROR_UNCAT 1 +#define ME_HFS_ERROR_IMAGE 3 +#define ME_HFS_ERROR_DEBUG 4 +#define ME_HFS_MODE_NORMAL 0 +#define ME_HFS_MODE_DEBUG 2 +#define ME_HFS_MODE_DIS 3 +#define ME_HFS_MODE_OVER_JMPR 4 +#define ME_HFS_MODE_OVER_MEI 5 +#define ME_HFS_BIOS_DRAM_ACK 1 +#define ME_HFS_ACK_NO_DID 0 +#define ME_HFS_ACK_RESET 1 +#define ME_HFS_ACK_PWR_CYCLE 2 +#define ME_HFS_ACK_S3 3 +#define ME_HFS_ACK_S4 4 +#define ME_HFS_ACK_S5 5 +#define ME_HFS_ACK_GBL_RESET 6 +#define ME_HFS_ACK_CONTINUE 7 + +struct me_hfs { + u32 working_state:4; + u32 mfg_mode:1; + u32 fpt_bad:1; + u32 operation_state:3; + u32 fw_init_complete:1; + u32 ft_bup_ld_flr:1; + u32 update_in_progress:1; + u32 error_code:4; + u32 operation_mode:4; + u32 reserved:4; + u32 boot_options_present:1; + u32 ack_data:3; + u32 bios_msg_ack:4; +} __packed; + +#define PCI_ME_UMA 0x44 + +struct me_uma { + u32 size:6; + u32 reserved_1:10; + u32 valid:1; + u32 reserved_0:14; + u32 set_to_one:1; +} __packed; + +#define PCI_ME_H_GS 0x4c +#define ME_INIT_DONE 1 +#define ME_INIT_STATUS_SUCCESS 0 +#define ME_INIT_STATUS_NOMEM 1 +#define ME_INIT_STATUS_ERROR 2 + +struct me_did { + u32 uma_base:16; + u32 reserved:8; + u32 status:4; + u32 init_done:4; +} __packed; + +#define PCI_ME_GMES 0x48 +#define ME_GMES_PHASE_ROM 0 +#define ME_GMES_PHASE_BUP 1 +#define ME_GMES_PHASE_UKERNEL 2 +#define ME_GMES_PHASE_POLICY 3 +#define ME_GMES_PHASE_MODULE 4 +#define ME_GMES_PHASE_UNKNOWN 5 +#define ME_GMES_PHASE_HOST 6 + +struct me_gmes { + u32 bist_in_prog:1; + u32 icc_prog_sts:2; + u32 invoke_mebx:1; + u32 cpu_replaced_sts:1; + u32 mbp_rdy:1; + u32 mfs_failure:1; + u32 warm_rst_req_for_df:1; + u32 cpu_replaced_valid:1; + u32 reserved_1:2; + u32 fw_upd_ipu:1; + u32 reserved_2:4; + u32 current_state:8; + u32 current_pmevent:4; + u32 progress_code:4; +} __packed; + +#define PCI_ME_HERES 0xbc +#define PCI_ME_EXT_SHA1 0x00 +#define PCI_ME_EXT_SHA256 0x02 +#define PCI_ME_HER(x) (0xc0+(4*(x))) + +struct me_heres { + u32 extend_reg_algorithm:4; + u32 reserved:26; + u32 extend_feature_present:1; + u32 extend_reg_valid:1; +} __packed; + +/* + * Management Engine MEI registers + */ + +#define MEI_H_CB_WW 0x00 +#define MEI_H_CSR 0x04 +#define MEI_ME_CB_RW 0x08 +#define MEI_ME_CSR_HA 0x0c + +struct mei_csr { + u32 interrupt_enable:1; + u32 interrupt_status:1; + u32 interrupt_generate:1; + u32 ready:1; + u32 reset:1; + u32 reserved:3; + u32 buffer_read_ptr:8; + u32 buffer_write_ptr:8; + u32 buffer_depth:8; +} __packed; + +#define MEI_ADDRESS_CORE 0x01 +#define MEI_ADDRESS_AMT 0x02 +#define MEI_ADDRESS_RESERVED 0x03 +#define MEI_ADDRESS_WDT 0x04 +#define MEI_ADDRESS_MKHI 0x07 +#define MEI_ADDRESS_ICC 0x08 +#define MEI_ADDRESS_THERMAL 0x09 + +#define MEI_HOST_ADDRESS 0 + +struct mei_header { + u32 client_address:8; + u32 host_address:8; + u32 length:9; + u32 reserved:6; + u32 is_complete:1; +} __packed; + +#define MKHI_GROUP_ID_CBM 0x00 +#define MKHI_GROUP_ID_FWCAPS 0x03 +#define MKHI_GROUP_ID_MDES 0x08 +#define MKHI_GROUP_ID_GEN 0xff + +#define MKHI_GLOBAL_RESET 0x0b + +#define MKHI_FWCAPS_GET_RULE 0x02 + +#define MKHI_MDES_ENABLE 0x09 + +#define MKHI_GET_FW_VERSION 0x02 +#define MKHI_END_OF_POST 0x0c +#define MKHI_FEATURE_OVERRIDE 0x14 + +struct mkhi_header { + u32 group_id:8; + u32 command:7; + u32 is_response:1; + u32 reserved:8; + u32 result:8; +} __packed; + +struct me_fw_version { + u16 code_minor; + u16 code_major; + u16 code_build_number; + u16 code_hot_fix; + u16 recovery_minor; + u16 recovery_major; + u16 recovery_build_number; + u16 recovery_hot_fix; +} __packed; + + +#define HECI_EOP_STATUS_SUCCESS 0x0 +#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 + +#define CBM_RR_GLOBAL_RESET 0x01 + +#define GLOBAL_RESET_BIOS_MRC 0x01 +#define GLOBAL_RESET_BIOS_POST 0x02 +#define GLOBAL_RESET_MEBX 0x03 + +struct me_global_reset { + u8 request_origin; + u8 reset_type; +} __packed; + +enum me_bios_path { + ME_NORMAL_BIOS_PATH, + ME_S3WAKE_BIOS_PATH, + ME_ERROR_BIOS_PATH, + ME_RECOVERY_BIOS_PATH, + ME_DISABLE_BIOS_PATH, + ME_FIRMWARE_UPDATE_BIOS_PATH, +}; + +struct __packed mbp_fw_version_name { + u32 major_version:16; + u32 minor_version:16; + u32 hotfix_version:16; + u32 build_version:16; +}; + +struct __packed mbp_icc_profile { + u8 num_icc_profiles; + u8 icc_profile_soft_strap; + u8 icc_profile_index; + u8 reserved; + u32 register_lock_mask[3]; +}; + +struct __packed mefwcaps_sku { + u32 full_net:1; + u32 std_net:1; + u32 manageability:1; + u32 small_business:1; + u32 l3manageability:1; + u32 intel_at:1; + u32 intel_cls:1; + u32 reserved:3; + u32 intel_mpc:1; + u32 icc_over_clocking:1; + u32 pavp:1; + u32 reserved_1:4; + u32 ipv6:1; + u32 kvm:1; + u32 och:1; + u32 vlan:1; + u32 tls:1; + u32 reserved_4:1; + u32 wlan:1; + u32 reserved_5:8; +}; + +struct __packed tdt_state_flag { + u16 lock_state:1; + u16 authenticate_module:1; + u16 s3authentication:1; + u16 flash_wear_out:1; + u16 flash_variable_security:1; + u16 wwan3gpresent:1; + u16 wwan3goob:1; + u16 reserved:9; +}; + +struct __packed tdt_state_info { + u8 state; + u8 last_theft_trigger; + struct tdt_state_flag flags; +}; + +struct __packed platform_type_rule_data { + u32 platform_target_usage_type:4; + u32 platform_target_market_type:2; + u32 super_sku:1; + u32 reserved:1; + u32 intel_me_fw_image_type:4; + u32 platform_brand:4; + u32 reserved_1:16; +}; + +struct __packed mbp_fw_caps { + struct mefwcaps_sku fw_capabilities; + u8 available; +}; + +struct __packed mbp_rom_bist_data { + u16 device_id; + u16 fuse_test_flags; + u32 umchid[4]; +}; + +struct __packed mbp_platform_key { + u32 key[8]; +}; + +struct __packed mbp_plat_type { + struct platform_type_rule_data rule_data; + u8 available; +}; + +struct __packed me_bios_payload { + struct mbp_fw_version_name fw_version_name; + struct mbp_fw_caps fw_caps_sku; + struct mbp_rom_bist_data rom_bist_data; + struct mbp_platform_key platform_key; + struct mbp_plat_type fw_plat_type; + struct mbp_icc_profile icc_profile; + struct tdt_state_info at_state; + u32 mfsintegrity; +}; + +struct __packed mbp_header { + u32 mbp_size:8; + u32 num_entries:8; + u32 rsvd:16; +}; + +struct __packed mbp_item_header { + u32 app_id:8; + u32 item_id:8; + u32 length:8; + u32 rsvd:8; +}; + +struct __packed me_fwcaps { + u32 id; + u8 length; + struct mefwcaps_sku caps_sku; + u8 reserved[3]; +}; + +/* Defined in me_status.c for both romstage and ramstage */ +void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); + +void intel_early_me_status(void); +int intel_early_me_init(void); +int intel_early_me_uma_size(void); +int intel_early_me_init_done(u8 status); + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/microcode.h b/arch/x86/include/asm/arch-ivybridge/microcode.h new file mode 100644 index 0000000..bc9b87c --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/microcode.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MICROCODE_H +#define __ASM_ARCH_MICROCODE_H + +/** + * microcode_update_intel() - Apply microcode updates + * + * Applies any microcode updates in the device tree. + * + * @return 0 if OK, -EEXIST if the updates were already applied, -ENOENT if + * not updates were found, -EINVAL if an update was invalid + */ +int microcode_update_intel(void); + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h new file mode 100644 index 0000000..7b4f2e7 --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h @@ -0,0 +1,86 @@ +/* + * From Coreboot file of the same name + * + * Copyright (C) 2011 The ChromiumOS Authors. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_MODEL_206AX_H +#define _ASM_ARCH_MODEL_206AX_H + +/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ +#define SANDYBRIDGE_BCLK 100 + +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +#define MSR_FEATURE_CONFIG 0x13c +#define MSR_FLEX_RATIO 0x194 +#define FLEX_RATIO_LOCK (1 << 20) +#define FLEX_RATIO_EN (1 << 16) +#define IA32_PLATFORM_DCA_CAP 0x1f8 +#define IA32_MISC_ENABLE 0x1a0 +#define MSR_TEMPERATURE_TARGET 0x1a2 +#define IA32_PERF_CTL 0x199 +#define IA32_THERM_INTERRUPT 0x19b +#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 +#define ENERGY_POLICY_PERFORMANCE 0 +#define ENERGY_POLICY_NORMAL 6 +#define ENERGY_POLICY_POWERSAVE 15 +#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 +#define MSR_LT_LOCK_MEMORY 0x2e7 +#define IA32_MC0_STATUS 0x401 + +#define MSR_PIC_MSG_CONTROL 0x2e +#define PLATFORM_INFO_SET_TDP (1 << 29) + +#define MSR_MISC_PWR_MGMT 0x1aa +#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_POWER_CTL 0x1fc + +#define MSR_PKGC3_IRTL 0x60a +#define MSR_PKGC6_IRTL 0x60b +#define MSR_PKGC7_IRTL 0x60c +#define IRTL_VALID (1 << 15) +#define IRTL_1_NS (0 << 10) +#define IRTL_32_NS (1 << 10) +#define IRTL_1024_NS (2 << 10) +#define IRTL_32768_NS (3 << 10) +#define IRTL_1048576_NS (4 << 10) +#define IRTL_33554432_NS (5 << 10) +#define IRTL_RESPONSE_MASK (0x3ff) + +/* long duration in low dword, short duration in high dword */ +#define PKG_POWER_LIMIT_MASK 0x7fff +#define PKG_POWER_LIMIT_EN (1 << 15) +#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_TIME_SHIFT 17 +#define PKG_POWER_LIMIT_TIME_MASK 0x7f + +#define MSR_PP0_CURRENT_CONFIG 0x601 +#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ +#define MSR_PP1_CURRENT_CONFIG 0x602 +#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ +#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_SKU 0x614 + +#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_CONFIG_TDP_LEVEL1 0x649 +#define MSR_CONFIG_TDP_LEVEL2 0x64a +#define MSR_CONFIG_TDP_CONTROL 0x64b +#define MSR_TURBO_ACTIVATION_RATIO 0x64c + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time); +int cpu_config_tdp_levels(void); + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h new file mode 100644 index 0000000..21df083 --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -0,0 +1,476 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * From Coreboot src/southbridge/intel/bd82x6x/pch.h + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_PCH_H +#define _ASM_ARCH_PCH_H + +#include <pci.h> + +/* PCH types */ +#define PCH_TYPE_CPT 0x1c /* CougarPoint */ +#define PCH_TYPE_PPT 0x1e /* IvyBridge */ + +/* PCH stepping values for LPC device */ +#define PCH_STEP_A0 0 +#define PCH_STEP_A1 1 +#define PCH_STEP_B0 2 +#define PCH_STEP_B1 3 +#define PCH_STEP_B2 4 +#define PCH_STEP_B3 5 +#define DEFAULT_GPIOBASE 0x0480 +#define DEFAULT_PMBASE 0x0500 + +#define SMBUS_IO_BASE 0x0400 + +int pch_silicon_revision(void); +int pch_silicon_type(void); +int pch_silicon_supported(int type, int rev); +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +/* PCI Configuration Space (D30:F0): PCI2PCI */ +#define PSTS 0x06 +#define SMLT 0x1b +#define SECSTS 0x1e +#define INTR 0x3c +#define BCTRL 0x3e +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0) + +#define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0) +#define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0) +#define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0) +#define PCH_ME_DEV PCI_BDF(0, 0x16, 0) +#define PCH_PCIE_DEV_SLOT 28 + +#define PCH_DEV PCI_BDF(0, 0, 0) +#define PCH_VIDEO_DEV PCI_BDF(0, 2, 0) + +/* PCI Configuration Space (D31:F0): LPC */ +#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0) +#define SERIRQ_CNTL 0x64 + +#define GEN_PMCON_1 0xa0 +#define GEN_PMCON_2 0xa2 +#define GEN_PMCON_3 0xa4 +#define ETR3 0xac +#define ETR3_CWORWRE (1 << 18) +#define ETR3_CF9GR (1 << 20) + +/* GEN_PMCON_3 bits */ +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define BIOS_CNTL 0xDC +#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ +#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ +#define GPIO_ROUT 0xb8 + +#define PIRQA_ROUT 0x60 +#define PIRQB_ROUT 0x61 +#define PIRQC_ROUT 0x62 +#define PIRQD_ROUT 0x63 +#define PIRQE_ROUT 0x68 +#define PIRQF_ROUT 0x69 +#define PIRQG_ROUT 0x6A +#define PIRQH_ROUT 0x6B + +#define GEN_PMCON_1 0xa0 +#define GEN_PMCON_2 0xa2 +#define GEN_PMCON_3 0xa4 +#define ETR3 0xac +#define ETR3_CWORWRE (1 << 18) +#define ETR3_CF9GR (1 << 20) + +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define BIOS_CNTL 0xDC +#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ +#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ +#define GPIO_ROUT 0xb8 + +#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define LPC_EN 0x82 /* LPC IF Enables Register */ +#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ +#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ +#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ +#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ +#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ +#define LPC_GENX_DEC(x) (0x84 + 4 * (x)) + +/* PCI Configuration Space (D31:F1): IDE */ +#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1) +#define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2) +#define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5) + +#define INTR_LN 0x3c +#define IDE_TIM_PRI 0x40 /* IDE timings, primary */ +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) +#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ + +#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0) + +#define IDE_SDMA_TIM 0x4a + +#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0) + +#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ +#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ +#define SATA_SP 0xd0 /* Scratchpad */ + +/* SATA IOBP Registers */ +#define SATA_IOBP_SP0G3IR 0xea000151 +#define SATA_IOBP_SP1G3IR 0xea000051 + +/* PCI Configuration Space (D31:F3): SMBus */ +#define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3) +#define SMB_BASE 0x20 +#define HOSTC 0x40 +#define SMB_RCV_SLVA 0x09 + +/* HOSTC bits */ +#define I2C_EN (1 << 2) +#define SMB_SMI_EN (1 << 1) +#define HST_EN (1 << 0) + +/* SMBus I/O bits. */ +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +#define SMBUS_TIMEOUT (10 * 1000 * 100) + + +/* Root Complex Register Block */ +#define DEFAULT_RCBA 0xfed1c000 +#define RCB_REG(reg) (DEFAULT_RCBA + (reg)) + +#define PCH_RCBA_BASE 0xf0 + +#define VCH 0x0000 /* 32bit */ +#define VCAP1 0x0004 /* 32bit */ +#define VCAP2 0x0008 /* 32bit */ +#define PVC 0x000c /* 16bit */ +#define PVS 0x000e /* 16bit */ + +#define V0CAP 0x0010 /* 32bit */ +#define V0CTL 0x0014 /* 32bit */ +#define V0STS 0x001a /* 16bit */ + +#define V1CAP 0x001c /* 32bit */ +#define V1CTL 0x0020 /* 32bit */ +#define V1STS 0x0026 /* 16bit */ + +#define RCTCL 0x0100 /* 32bit */ +#define ESD 0x0104 /* 32bit */ +#define ULD 0x0110 /* 32bit */ +#define ULBA 0x0118 /* 64bit */ + +#define RP1D 0x0120 /* 32bit */ +#define RP1BA 0x0128 /* 64bit */ +#define RP2D 0x0130 /* 32bit */ +#define RP2BA 0x0138 /* 64bit */ +#define RP3D 0x0140 /* 32bit */ +#define RP3BA 0x0148 /* 64bit */ +#define RP4D 0x0150 /* 32bit */ +#define RP4BA 0x0158 /* 64bit */ +#define HDD 0x0160 /* 32bit */ +#define HDBA 0x0168 /* 64bit */ +#define RP5D 0x0170 /* 32bit */ +#define RP5BA 0x0178 /* 64bit */ +#define RP6D 0x0180 /* 32bit */ +#define RP6BA 0x0188 /* 64bit */ + +#define RPC 0x0400 /* 32bit */ +#define RPFN 0x0404 /* 32bit */ + +#define TRSR 0x1e00 /* 8bit */ +#define TRCR 0x1e10 /* 64bit */ +#define TWDR 0x1e18 /* 64bit */ + +#define IOTR0 0x1e80 /* 64bit */ +#define IOTR1 0x1e88 /* 64bit */ +#define IOTR2 0x1e90 /* 64bit */ +#define IOTR3 0x1e98 /* 64bit */ + +#define TCTL 0x3000 /* 8bit */ + +#define NOINT 0 +#define INTA 1 +#define INTB 2 +#define INTC 3 +#define INTD 4 + +#define DIR_IDR 12 /* Interrupt D Pin Offset */ +#define DIR_ICR 8 /* Interrupt C Pin Offset */ +#define DIR_IBR 4 /* Interrupt B Pin Offset */ +#define DIR_IAR 0 /* Interrupt A Pin Offset */ + +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +/* IO Buffer Programming */ +#define IOBPIRI 0x2330 +#define IOBPD 0x2334 +#define IOBPS 0x2338 +#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) +#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) +#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) + +#define D31IP 0x3100 /* 32bit */ +#define D31IP_TTIP 24 /* Thermal Throttle Pin */ +#define D31IP_SIP2 20 /* SATA Pin 2 */ +#define D31IP_SMIP 12 /* SMBUS Pin */ +#define D31IP_SIP 8 /* SATA Pin */ +#define D30IP 0x3104 /* 32bit */ +#define D30IP_PIP 0 /* PCI Bridge Pin */ +#define D29IP 0x3108 /* 32bit */ +#define D29IP_E1P 0 /* EHCI #1 Pin */ +#define D28IP 0x310c /* 32bit */ +#define D28IP_P8IP 28 /* PCI Express Port 8 */ +#define D28IP_P7IP 24 /* PCI Express Port 7 */ +#define D28IP_P6IP 20 /* PCI Express Port 6 */ +#define D28IP_P5IP 16 /* PCI Express Port 5 */ +#define D28IP_P4IP 12 /* PCI Express Port 4 */ +#define D28IP_P3IP 8 /* PCI Express Port 3 */ +#define D28IP_P2IP 4 /* PCI Express Port 2 */ +#define D28IP_P1IP 0 /* PCI Express Port 1 */ +#define D27IP 0x3110 /* 32bit */ +#define D27IP_ZIP 0 /* HD Audio Pin */ +#define D26IP 0x3114 /* 32bit */ +#define D26IP_E2P 0 /* EHCI #2 Pin */ +#define D25IP 0x3118 /* 32bit */ +#define D25IP_LIP 0 /* GbE LAN Pin */ +#define D22IP 0x3124 /* 32bit */ +#define D22IP_KTIP 12 /* KT Pin */ +#define D22IP_IDERIP 8 /* IDE-R Pin */ +#define D22IP_MEI2IP 4 /* MEI #2 Pin */ +#define D22IP_MEI1IP 0 /* MEI #1 Pin */ +#define D20IP 0x3128 /* 32bit */ +#define D20IP_XHCIIP 0 +#define D31IR 0x3140 /* 16bit */ +#define D30IR 0x3142 /* 16bit */ +#define D29IR 0x3144 /* 16bit */ +#define D28IR 0x3146 /* 16bit */ +#define D27IR 0x3148 /* 16bit */ +#define D26IR 0x314c /* 16bit */ +#define D25IR 0x3150 /* 16bit */ +#define D22IR 0x315c /* 16bit */ +#define D20IR 0x3160 /* 16bit */ +#define OIC 0x31fe /* 16bit */ + +#define SPI_FREQ_SWSEQ 0x3893 +#define SPI_DESC_COMP0 0x38b0 +#define SPI_FREQ_WR_ERA 0x38b4 +#define SOFT_RESET_CTRL 0x38f4 +#define SOFT_RESET_DATA 0x38f8 + +#define DIR_ROUTE(a, b, c, d) \ + (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ + ((b) << DIR_IBR) | ((a) << DIR_IAR)) + +#define RC 0x3400 /* 32bit */ +#define HPTC 0x3404 /* 32bit */ +#define GCS 0x3410 /* 32bit */ +#define BUC 0x3414 /* 32bit */ +#define PCH_DISABLE_GBE (1 << 5) +#define FD 0x3418 /* 32bit */ +#define DISPBDF 0x3424 /* 16bit */ +#define FD2 0x3428 /* 32bit */ +#define CG 0x341c /* 32bit */ + +/* Function Disable 1 RCBA 0x3418 */ +#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) +#define PCH_DISABLE_P2P (1 << 1) +#define PCH_DISABLE_SATA1 (1 << 2) +#define PCH_DISABLE_SMBUS (1 << 3) +#define PCH_DISABLE_HD_AUDIO (1 << 4) +#define PCH_DISABLE_EHCI2 (1 << 13) +#define PCH_DISABLE_LPC (1 << 14) +#define PCH_DISABLE_EHCI1 (1 << 15) +#define PCH_DISABLE_PCIE(x) (1 << (16 + x)) +#define PCH_DISABLE_THERMAL (1 << 24) +#define PCH_DISABLE_SATA2 (1 << 25) +#define PCH_DISABLE_XHCI (1 << 27) + +/* Function Disable 2 RCBA 0x3428 */ +#define PCH_DISABLE_KT (1 << 4) +#define PCH_DISABLE_IDER (1 << 3) +#define PCH_DISABLE_MEI2 (1 << 2) +#define PCH_DISABLE_MEI1 (1 << 1) +#define PCH_ENABLE_DBDF (1 << 0) + +/* ICH7 GPIOBASE */ +#define GPIO_USE_SEL 0x00 +#define GP_IO_SEL 0x04 +#define GP_LVL 0x0c +#define GPO_BLINK 0x18 +#define GPI_INV 0x2c +#define GPIO_USE_SEL2 0x30 +#define GP_IO_SEL2 0x34 +#define GP_LVL2 0x38 +#define GPIO_USE_SEL3 0x40 +#define GP_IO_SEL3 0x44 +#define GP_LVL3 0x48 +#define GP_RST_SEL1 0x60 +#define GP_RST_SEL2 0x64 +#define GP_RST_SEL3 0x68 + +/* ICH7 PMBASE */ +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define PROC_CNT 0x10 +#define LV2 0x14 +#define LV3 0x15 +#define LV4 0x16 +#define PM2_CNT 0x50 /* mobile only */ +#define GPE0_STS 0x20 +#define PME_B0_STS (1 << 13) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN 0x28 +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define TCOSCI_EN (1 << 6) +#define SMI_EN 0x30 +#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */ +#define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */ +#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ +#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ +#define MCSMI_EN (1 << 11) /* Trap microcontroller range access */ +#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ +#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ +#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ +#define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */ +#define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */ +#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ +#define EOS (1 << 1) /* End of SMI (deassert SMI#) */ +#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ +#define SMI_STS 0x34 +#define ALT_GP_SMI_EN 0x38 +#define ALT_GP_SMI_STS 0x3a +#define GPE_CNTL 0x42 +#define DEVACT_STS 0x44 +#define SS_CNT 0x50 +#define C3_RES 0x54 +#define TCO1_STS 0x64 +#define DMISCI_STS (1 << 9) +#define TCO2_STS 0x66 + +int lpc_init(struct pci_controller *hose, pci_dev_t dev); +void lpc_enable(pci_dev_t dev); + +/** + * lpc_early_init() - set up LPC serial ports and other early things + * + * @blob: Device tree blob + * @node: Offset of LPC node + * @dev: PCH PCI device containing the LPC + * @return 0 if OK, -ve on error + */ +int lpc_early_init(const void *blob, int node, pci_dev_t dev); + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/pei_data.h b/arch/x86/include/asm/arch-ivybridge/pei_data.h new file mode 100644 index 0000000..5026c8b --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/pei_data.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2011, Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef ASM_ARCH_PEI_DATA_H +#define ASM_ARCH_PEI_DATA_H + +struct pch_usb3_controller_settings { + /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ + uint16_t mode; + /* 4 bit mask, 1: switchable, 0: not switchable */ + uint16_t hs_port_switch_mask; + /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ + uint16_t preboot_support; + /* 0: Disable, 1: Enable */ + uint16_t xhci_streams; +}; + +typedef asmlinkage void (*tx_byte_func)(unsigned char byte); + +#define PEI_VERSION 6 + +struct __packed pei_data { + uint32_t pei_version; + uint32_t mchbar; + uint32_t dmibar; + uint32_t epbar; + uint32_t pciexbar; + uint16_t smbusbar; + uint32_t wdbbar; + uint32_t wdbsize; + uint32_t hpet_address; + uint32_t rcba; + uint32_t pmbase; + uint32_t gpiobase; + uint32_t thermalbase; + uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */ + uint32_t tseg_size; + uint8_t spd_addresses[4]; + uint8_t ts_addresses[4]; + int boot_mode; + int ec_present; + int gbe_enable; + /* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ + int dimm_channel0_disabled; + int dimm_channel1_disabled; + /* Seed values saved in CMOS */ + uint32_t scrambler_seed; + uint32_t scrambler_seed_s3; + /* Data read from flash and passed into MRC */ + unsigned char *mrc_input; + unsigned int mrc_input_len; + /* Data from MRC that should be saved to flash */ + unsigned char *mrc_output; + unsigned int mrc_output_len; + /* + * Max frequency DDR3 could be ran at. Could be one of four values: + * 800, 1067, 1333, 1600 + */ + uint32_t max_ddr3_freq; + /* + * USB Port Configuration: + * [0] = enable + * [1] = overcurrent pin + * [2] = length + * + * Ports 0-7 can be mapped to OC0-OC3 + * Ports 8-13 can be mapped to OC4-OC7 + * + * Port Length + * MOBILE: + * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) + * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) + * DESKTOP: + * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) + * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) + * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude) + */ + uint16_t usb_port_config[16][3]; + /* See the usb3 struct above for details */ + struct pch_usb3_controller_settings usb3; + /* + * SPD data array for onboard RAM. Specify address 0xf0, + * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in + * spd_address for a given "DIMM". + */ + uint8_t spd_data[4][256]; + tx_byte_func tx_byte; + int ddr3lv_support; + /* + * pcie_init needs to be set to 1 to have the system agent initialise + * PCIe. Note: This should only be required if your system has Gen3 + * devices and it will increase your boot time by at least 100ms. + */ + int pcie_init; + /* + * N mode functionality. Leave this setting at 0. + * 0 Auto + * 1 1N + * 2 2N + */ + int nmode; + /* + * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows + * for DIMM SPD data to specify whether double-rate is required for + * extended operating temperature range. + * 0 Enable double rate based upon temperature thresholds + * 1 Normal rate + * 2 Always enable double rate + */ + int ddr_refresh_rate_config; +}; + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h new file mode 100644 index 0000000..cf7457f --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * From Coreboot file of the same name + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ACH_ASM_SANDYBRIDGE_H +#define _ACH_ASM_SANDYBRIDGE_H + +/* Chipset types */ +#define SANDYBRIDGE_MOBILE 0 +#define SANDYBRIDGE_DESKTOP 1 +#define SANDYBRIDGE_SERVER 2 + +/* Device ID for SandyBridge and IvyBridge */ +#define BASE_REV_SNB 0x00 +#define BASE_REV_IVB 0x50 +#define BASE_REV_MASK 0x50 + +/* SandyBridge CPU stepping */ +#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ +#define SNB_STEP_D1 (BASE_REV_SNB + 6) +#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ + +/* IvyBridge CPU stepping */ +#define IVB_STEP_A0 (BASE_REV_IVB + 0) +#define IVB_STEP_B0 (BASE_REV_IVB + 2) +#define IVB_STEP_C0 (BASE_REV_IVB + 4) +#define IVB_STEP_K0 (BASE_REV_IVB + 5) +#define IVB_STEP_D0 (BASE_REV_IVB + 6) + +/* Intel Enhanced Debug region must be 4MB */ +#define IED_SIZE 0x400000 + +/* Northbridge BARs */ +#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#define DEFAULT_RCBABASE 0xfed1c000 +/* 4 KB per PCIe device */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS + +/* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define X60BAR 0x60 + +#define GGC 0x50 /* GMCH Graphics Control */ + +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_PEG60 (1 << 13) +#define DEVEN_IGD (1 << 4) +#define DEVEN_PEG10 (1 << 3) +#define DEVEN_PEG11 (1 << 2) +#define DEVEN_PEG12 (1 << 1) +#define DEVEN_HOST (1 << 0) + +#define PAM0 0x80 +#define PAM1 0x81 +#define PAM2 0x82 +#define PAM3 0x83 +#define PAM4 0x84 +#define PAM5 0x85 +#define PAM6 0x86 + +#define LAC 0x87 /* Legacy Access Control */ +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +#define TOM 0xa0 +#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define TSEG 0xb8 /* TSEG base */ +#define TOLUD 0xbc /* Top of Low Used Memory */ + +#define SKPAD 0xdc /* Scratchpad Data */ + +/* Device 0:1.0 PCI configuration space (PCI Express) */ +#define BCTRL1 0x3e /* 16bit */ + +/* Device 0:2.0 PCI configuration space (Graphics Device) */ + +#define MSAC 0x62 /* Multi Size Aperture Control */ +#define SWSCI 0xe8 /* SWSCI enable */ +#define ASLS 0xfc /* OpRegion Base */ + +/* + * MCHBAR + */ +#define MCHBAR_REG(reg) (DEFAULT_MCHBAR + (reg)) + +#define SSKPD 0x5d14 /* 16bit (scratchpad) */ +#define BIOS_RESET_CPL 0x5da8 /* 8bit */ + +/* + * DMIBAR + */ + +#define DMIBAR_REG(x) (DEFAULT_DMIBAR + x) + +int bridge_silicon_revision(void); + +void northbridge_enable(pci_dev_t dev); +void northbridge_init(pci_dev_t dev); + +void report_platform_info(void); + +void sandybridge_early_init(int chipset_type); + +#endif diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h index ff15828..c97d988 100644 --- a/arch/x86/include/asm/config.h +++ b/arch/x86/include/asm/config.h @@ -10,5 +10,6 @@ #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH +#define asmlinkage __attribute__((regparm(0))) #endif diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 6c6774a..c839291 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -1,16 +1,160 @@ /* * Copyright (c) 2014 The Chromium OS Authors. * + * Part of this file is adapted from coreboot + * src/arch/x86/include/arch/cpu.h and + * src/arch/x86/lib/cpu.c + * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __X86_CPU_H -#define __X86_CPU_H +#ifndef _ASM_CPU_H +#define _ASM_CPU_H + +enum { + X86_VENDOR_INVALID = 0, + X86_VENDOR_INTEL, + X86_VENDOR_CYRIX, + X86_VENDOR_AMD, + X86_VENDOR_UMC, + X86_VENDOR_NEXGEN, + X86_VENDOR_CENTAUR, + X86_VENDOR_RISE, + X86_VENDOR_TRANSMETA, + X86_VENDOR_NSC, + X86_VENDOR_SIS, + X86_VENDOR_ANY = 0xfe, + X86_VENDOR_UNKNOWN = 0xff +}; + +struct cpuid_result { + uint32_t eax; + uint32_t ebx; + uint32_t ecx; + uint32_t edx; +}; + +/* + * Generic CPUID function + */ +static inline struct cpuid_result cpuid(int op) +{ + struct cpuid_result result; + asm volatile( + "mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" + : "=a" (result.eax), + "=S" (result.ebx), + "=c" (result.ecx), + "=d" (result.edx) + : "0" (op) + : "edi"); + return result; +} + +/* + * Generic Extended CPUID function + */ +static inline struct cpuid_result cpuid_ext(int op, unsigned ecx) +{ + struct cpuid_result result; + asm volatile( + "mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" + : "=a" (result.eax), + "=S" (result.ebx), + "=c" (result.ecx), + "=d" (result.edx) + : "0" (op), "2" (ecx) + : "edi"); + return result; +} + +/* + * CPUID functions returning a single datum + */ +static inline unsigned int cpuid_eax(unsigned int op) +{ + unsigned int eax; + + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" + : "=a" (eax) + : "0" (op) + : "ecx", "edx", "edi"); + return eax; +} + +static inline unsigned int cpuid_ebx(unsigned int op) +{ + unsigned int eax, ebx; + + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" + : "=a" (eax), "=S" (ebx) + : "0" (op) + : "ecx", "edx", "edi"); + return ebx; +} + +static inline unsigned int cpuid_ecx(unsigned int op) +{ + unsigned int eax, ecx; - /** + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" + : "=a" (eax), "=c" (ecx) + : "0" (op) + : "edx", "edi"); + return ecx; +} + +static inline unsigned int cpuid_edx(unsigned int op) +{ + unsigned int eax, edx; + + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" + : "=a" (eax), "=d" (edx) + : "0" (op) + : "ecx", "edi"); + return edx; +} + +/* Standard macro to see if a specific flag is changeable */ +static inline int flag_is_changeable_p(uint32_t flag) +{ + uint32_t f1, f2; + + asm( + "pushfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "movl %0,%1\n\t" + "xorl %2,%0\n\t" + "pushl %0\n\t" + "popfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "popfl\n\t" + : "=&r" (f1), "=&r" (f2) + : "ir" (flag)); + return ((f1^f2) & flag) != 0; +} + +/** * cpu_enable_paging_pae() - Enable PAE-paging * - * @pdpt: Value to set in cr3 (PDPT or PML4T) + * @cr3: Value to set in cr3 (PDPT or PML4T) */ void cpu_enable_paging_pae(ulong cr3); @@ -27,6 +171,27 @@ void cpu_disable_paging_pae(void); int cpu_has_64bit(void); /** + * cpu_vendor_name() - Get CPU vendor name + * + * @vendor: CPU vendor enumeration number + * + * @return: Address to hold the CPU vendor name string + */ +const char *cpu_vendor_name(int vendor); + +#define CPU_MAX_NAME_LEN 49 + +/** + * cpu_get_name() - Get the name of the current cpu + * + * @name: Place to put name, which must be CPU_MAX_NAME_LEN bytes including + * @return pointer to name, which will likely be a few bytes after the start + * of @name + * \0 terminator + */ +char *cpu_get_name(char *name); + +/** * cpu_call64() - Jump to a 64-bit Linux kernel (internal function) * * The kernel is uncompressed and the 64-bit entry point is expected to be diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 3e8e2cd..48bbd1a 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -10,13 +10,43 @@ #ifndef __ASSEMBLY__ +enum pei_boot_mode_t { + PEI_BOOT_NONE = 0, + PEI_BOOT_SOFT_RESET, + PEI_BOOT_RESUME, + +}; + +struct memory_area { + uint64_t start; + uint64_t size; +}; + +struct memory_info { + int num_areas; + uint64_t total_memory; + uint64_t total_32bit_memory; + struct memory_area area[CONFIG_NR_DRAM_BANKS]; +}; + /* Architecture-specific global data */ struct arch_global_data { struct global_data *gd_addr; /* Location of Global Data */ + uint8_t x86; /* CPU family */ + uint8_t x86_vendor; /* CPU vendor */ + uint8_t x86_model; + uint8_t x86_mask; + uint32_t x86_device; uint64_t tsc_base; /* Initial value returned by rdtsc() */ uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */ uint32_t tsc_prev; /* For show_boot_progress() */ + uint32_t tsc_mhz; /* TSC frequency in MHz */ void *new_fdt; /* Relocated FDT */ + uint32_t bist; /* Built-in self test value */ + struct pci_controller *hose; /* PCI hose for early use */ + enum pei_boot_mode_t pei_boot_mode; + const struct pch_gpio_map *gpio_map; /* board GPIO map */ + struct memory_info meminfo; /* Memory information */ }; #endif diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h index 8bda414..5540d42 100644 --- a/arch/x86/include/asm/gpio.h +++ b/arch/x86/include/asm/gpio.h @@ -1,12 +1,152 @@ /* * Copyright (c) 2012, Google Inc. All rights reserved. - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _X86_GPIO_H_ #define _X86_GPIO_H_ +#include <linux/compiler.h> #include <asm/arch/gpio.h> #include <asm-generic/gpio.h> +struct ich6_bank_platdata { + uint32_t base_addr; + const char *bank_name; +}; + +#define GPIO_MODE_NATIVE 0 +#define GPIO_MODE_GPIO 1 +#define GPIO_MODE_NONE 1 + +#define GPIO_DIR_OUTPUT 0 +#define GPIO_DIR_INPUT 1 + +#define GPIO_NO_INVERT 0 +#define GPIO_INVERT 1 + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 + +#define GPIO_NO_BLINK 0 +#define GPIO_BLINK 1 + +#define GPIO_RESET_PWROK 0 +#define GPIO_RESET_RSMRST 1 + +struct pch_gpio_set1 { + u32 gpio0:1; + u32 gpio1:1; + u32 gpio2:1; + u32 gpio3:1; + u32 gpio4:1; + u32 gpio5:1; + u32 gpio6:1; + u32 gpio7:1; + u32 gpio8:1; + u32 gpio9:1; + u32 gpio10:1; + u32 gpio11:1; + u32 gpio12:1; + u32 gpio13:1; + u32 gpio14:1; + u32 gpio15:1; + u32 gpio16:1; + u32 gpio17:1; + u32 gpio18:1; + u32 gpio19:1; + u32 gpio20:1; + u32 gpio21:1; + u32 gpio22:1; + u32 gpio23:1; + u32 gpio24:1; + u32 gpio25:1; + u32 gpio26:1; + u32 gpio27:1; + u32 gpio28:1; + u32 gpio29:1; + u32 gpio30:1; + u32 gpio31:1; +} __packed; + +struct pch_gpio_set2 { + u32 gpio32:1; + u32 gpio33:1; + u32 gpio34:1; + u32 gpio35:1; + u32 gpio36:1; + u32 gpio37:1; + u32 gpio38:1; + u32 gpio39:1; + u32 gpio40:1; + u32 gpio41:1; + u32 gpio42:1; + u32 gpio43:1; + u32 gpio44:1; + u32 gpio45:1; + u32 gpio46:1; + u32 gpio47:1; + u32 gpio48:1; + u32 gpio49:1; + u32 gpio50:1; + u32 gpio51:1; + u32 gpio52:1; + u32 gpio53:1; + u32 gpio54:1; + u32 gpio55:1; + u32 gpio56:1; + u32 gpio57:1; + u32 gpio58:1; + u32 gpio59:1; + u32 gpio60:1; + u32 gpio61:1; + u32 gpio62:1; + u32 gpio63:1; +} __packed; + +struct pch_gpio_set3 { + u32 gpio64:1; + u32 gpio65:1; + u32 gpio66:1; + u32 gpio67:1; + u32 gpio68:1; + u32 gpio69:1; + u32 gpio70:1; + u32 gpio71:1; + u32 gpio72:1; + u32 gpio73:1; + u32 gpio74:1; + u32 gpio75:1; +} __packed; + +/* + * This hilariously complex structure came from Coreboot. The + * setup_pch_gpios() function uses it. It could be move to device tree, or + * adjust to use masks instead of bitfields. + */ +struct pch_gpio_map { + struct { + const struct pch_gpio_set1 *mode; + const struct pch_gpio_set1 *direction; + const struct pch_gpio_set1 *level; + const struct pch_gpio_set1 *reset; + const struct pch_gpio_set1 *invert; + const struct pch_gpio_set1 *blink; + } set1; + struct { + const struct pch_gpio_set2 *mode; + const struct pch_gpio_set2 *direction; + const struct pch_gpio_set2 *level; + const struct pch_gpio_set2 *reset; + } set2; + struct { + const struct pch_gpio_set3 *mode; + const struct pch_gpio_set3 *direction; + const struct pch_gpio_set3 *level; + const struct pch_gpio_set3 *reset; + } set3; +}; + +void ich_gpio_set_gpio_map(const struct pch_gpio_map *map); + #endif /* _X86_GPIO_H_ */ diff --git a/arch/x86/include/asm/i8254.h b/arch/x86/include/asm/i8254.h index c3ccd4f..4116de1 100644 --- a/arch/x86/include/asm/i8254.h +++ b/arch/x86/include/asm/i8254.h @@ -36,4 +36,7 @@ #define PIT_CMD_MODE4 0x08 /* Select mode 4 */ #define PIT_CMD_MODE5 0x0A /* Select mode 5 */ +/* The clock frequency of the i8253/i8254 PIT */ +#define PIT_TICK_RATE 1193182ul + #endif diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h index 73113f9..bc4033b 100644 --- a/arch/x86/include/asm/i8259.h +++ b/arch/x86/include/asm/i8259.h @@ -69,4 +69,6 @@ #define ICW4_AEOI 0x02 /* Automatic EOI Mode */ #define ICW4_PM 0x01 /* Microprocessor Mode */ +int i8259_init(void); + #endif diff --git a/arch/x86/include/asm/init_helpers.h b/arch/x86/include/asm/init_helpers.h index b07887e..8cbe08e 100644 --- a/arch/x86/include/asm/init_helpers.h +++ b/arch/x86/include/asm/init_helpers.h @@ -13,7 +13,5 @@ int calculate_relocation_address(void); int init_cache_f_r(void); int init_bd_struct_r(void); int init_func_spi(void); -int find_fdt(void); -int prepare_fdt(void); #endif /* !_INIT_HELPERS_H_ */ diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h index 3f46e09..25abde7 100644 --- a/arch/x86/include/asm/interrupt.h +++ b/arch/x86/include/asm/interrupt.h @@ -27,4 +27,15 @@ void specific_eoi(int irq); extern char exception_stack[]; +/** + * configure_irq_trigger() - Configure IRQ triggering + * + * Switch the given interrupt to be level / edge triggered + * + * @param int_num legacy interrupt number (3-7, 9-15) + * @param is_level_triggered true for level triggered interrupt, false for + * edge triggered interrupt + */ +void configure_irq_trigger(int int_num, bool is_level_triggered); + #endif diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 86bac90..e0b2561 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -1,7 +1,7 @@ #ifndef _ASM_IO_H #define _ASM_IO_H -#include <compiler.h> +#include <linux/compiler.h> /* * This file contains the definitions for the x86 IO instructions @@ -69,6 +69,55 @@ #define memcpy_fromio(a,b,c) memcpy((a),(b),(c)) #define memcpy_toio(a,b,c) memcpy((a),(b),(c)) +#define write_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a) +#define read_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) + +#define write_le64(a, v) write_arch(q, le64, a, v) +#define write_le32(a, v) write_arch(l, le32, a, v) +#define write_le16(a, v) write_arch(w, le16, a, v) + +#define read_le64(a) read_arch(q, le64, a) +#define read_le32(a) read_arch(l, le32, a) +#define read_le16(a) read_arch(w, le16, a) + +#define write_be32(a, v) write_arch(l, be32, a, v) +#define write_be16(a, v) write_arch(w, be16, a, v) + +#define read_be32(a) read_arch(l, be32, a) +#define read_be16(a) read_arch(w, be16, a) + +#define write_8(a, v) __raw_writeb(v, a) +#define read_8(a) __raw_readb(a) + +#define clrbits(type, addr, clear) \ + write_##type((addr), read_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + write_##type((addr), read_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + write_##type((addr), (read_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + /* * ISA space is 'always mapped' on a typical x86 system, no need to * explicitly ioremap() it. The fact that the ISA IO space is mapped diff --git a/arch/x86/include/asm/ioapic.h b/arch/x86/include/asm/ioapic.h new file mode 100644 index 0000000..699160f --- /dev/null +++ b/arch/x86/include/asm/ioapic.h @@ -0,0 +1,38 @@ +/* + * From coreboot file of the same name + * + * Copyright (C) 2010 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_IOAPIC_H +#define __ASM_IOAPIC_H + +#define IO_APIC_ADDR 0xfec00000 +#define IO_APIC_INDEX IO_APIC_ADDR +#define IO_APIC_DATA (IO_APIC_ADDR + 0x10) +#define IO_APIC_INTERRUPTS 24 + +#define ALL (0xff << 24) +#define NONE 0 +#define DISABLED (1 << 16) +#define ENABLED (0 << 16) +#define TRIGGER_EDGE (0 << 15) +#define TRIGGER_LEVEL (1 << 15) +#define POLARITY_HIGH (0 << 13) +#define POLARITY_LOW (1 << 13) +#define PHYSICAL_DEST (0 << 11) +#define LOGICAL_DEST (1 << 11) +#define ExtINT (7 << 8) +#define NMI (4 << 8) +#define SMI (2 << 8) +#define INT (1 << 8) + +u32 io_apic_read(u32 ioapic_base, u32 reg); +void io_apic_write(u32 ioapic_base, u32 reg, u32 value); +void set_ioapic_id(u32 ioapic_base, u8 ioapic_id); +void setup_ioapic(u32 ioapic_base, u8 ioapic_id); +void clear_ioapic(u32 ioapic_base); + +#endif diff --git a/arch/x86/include/asm/lapic.h b/arch/x86/include/asm/lapic.h new file mode 100644 index 0000000..0a7f443 --- /dev/null +++ b/arch/x86/include/asm/lapic.h @@ -0,0 +1,179 @@ +/* + * From Coreboot file of same name + * + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ARCH_ASM_LAPIC_H +#define _ARCH_ASM_LAPIC_H + +#include <asm/io.h> +#include <asm/lapic_def.h> +#include <asm/msr.h> +#include <asm/processor.h> + +/* See if I need to initialize the local apic */ +#if CONFIG_SMP || CONFIG_IOAPIC +# define NEED_LAPIC 1 +#else +# define NEED_LAPIC 0 +#endif + +static inline __attribute__((always_inline)) + unsigned long lapic_read(unsigned long reg) +{ + return readl(LAPIC_DEFAULT_BASE + reg); +} + +static inline __attribute__((always_inline)) + void lapic_write(unsigned long reg, unsigned long val) +{ + writel(val, LAPIC_DEFAULT_BASE + reg); +} + +static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void) +{ + do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY); +} + +static inline void enable_lapic(void) +{ + msr_t msr; + + msr = msr_read(LAPIC_BASE_MSR); + msr.hi &= 0xffffff00; + msr.lo |= LAPIC_BASE_MSR_ENABLE; + msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK; + msr.lo |= LAPIC_DEFAULT_BASE; + msr_write(LAPIC_BASE_MSR, msr); +} + +static inline void disable_lapic(void) +{ + msr_t msr; + + msr = msr_read(LAPIC_BASE_MSR); + msr.lo &= ~(1 << 11); + msr_write(LAPIC_BASE_MSR, msr); +} + +static inline __attribute__((always_inline)) unsigned long lapicid(void) +{ + return lapic_read(LAPIC_ID) >> 24; +} + +#if !CONFIG_AP_IN_SIPI_WAIT +/* If we need to go back to sipi wait, we use the long non-inlined version of + * this function in lapic_cpu_init.c + */ +static inline __attribute__((always_inline)) void stop_this_cpu(void) +{ + /* Called by an AP when it is ready to halt and wait for a new task */ + for (;;) + cpu_hlt(); +} +#else +void stop_this_cpu(void); +#endif + +#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \ + sizeof(*(ptr)))) + +struct __xchg_dummy { unsigned long a[100]; }; +#define __xg(x) ((struct __xchg_dummy *)(x)) + +/* + * Note: no "lock" prefix even on SMP: xchg always implies lock anyway + * Note 2: xchg has side effect, so that attribute volatile is necessary, + * but generally the primitive is invalid, *ptr is output argument. --ANK + */ +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, + int size) +{ + switch (size) { + case 1: + __asm__ __volatile__("xchgb %b0,%1" + : "=q" (x) + : "m" (*__xg(ptr)), "0" (x) + : "memory"); + break; + case 2: + __asm__ __volatile__("xchgw %w0,%1" + : "=r" (x) + : "m" (*__xg(ptr)), "0" (x) + : "memory"); + break; + case 4: + __asm__ __volatile__("xchgl %0,%1" + : "=r" (x) + : "m" (*__xg(ptr)), "0" (x) + : "memory"); + break; + } + + return x; +} + +static inline void lapic_write_atomic(unsigned long reg, unsigned long v) +{ + (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v); +} + + +#ifdef X86_GOOD_APIC +# define FORCE_READ_AROUND_WRITE 0 +# define lapic_read_around(x) lapic_read(x) +# define lapic_write_around(x, y) lapic_write((x), (y)) +#else +# define FORCE_READ_AROUND_WRITE 1 +# define lapic_read_around(x) lapic_read(x) +# define lapic_write_around(x, y) lapic_write_atomic((x), (y)) +#endif + +static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue) +{ + int timeout; + unsigned long status; + int result; + lapic_wait_icr_idle(); + lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4)); + timeout = 0; + do { + status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK; + } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000); + + result = -1; + if (status == LAPIC_ICR_RR_VALID) { + *pvalue = lapic_read(LAPIC_RRR); + result = 0; + } + return result; +} + + +void lapic_setup(void); + +#if CONFIG_SMP +struct device; +int start_cpu(struct device *cpu); +#endif /* CONFIG_SMP */ + +int boot_cpu(void); + +/** + * struct x86_cpu_priv - Information about a single CPU + * + * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is + * just a number representing the CPU core + * + * TODO: Move this to driver model once lifecycle is understood + */ +struct x86_cpu_priv { + int apic_id; + int start_err; +}; + +#endif diff --git a/arch/x86/include/asm/lapic_def.h b/arch/x86/include/asm/lapic_def.h new file mode 100644 index 0000000..722cead --- /dev/null +++ b/arch/x86/include/asm/lapic_def.h @@ -0,0 +1,101 @@ +/* + * Taken from the Coreboot file of the same name + * + * (C) Copyright 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_LAPIC_DEF_H +#define _ASM_LAPIC_DEF_H + +#define LAPIC_BASE_MSR 0x1B +#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8) +#define LAPIC_BASE_MSR_ENABLE (1 << 11) +#define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000 + +#define LOCAL_APIC_ADDR 0xfee00000 +#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR + +#define LAPIC_ID 0x020 +#define LAPIC_LVR 0x030 +#define LAPIC_TASKPRI 0x80 +#define LAPIC_TPRI_MASK 0xFF +#define LAPIC_ARBID 0x090 +#define LAPIC_RRR 0x0C0 +#define LAPIC_SVR 0x0f0 +#define LAPIC_SPIV 0x0f0 +#define LAPIC_SPIV_ENABLE 0x100 +#define LAPIC_ESR 0x280 +#define LAPIC_ESR_SEND_CS 0x00001 +#define LAPIC_ESR_RECV_CS 0x00002 +#define LAPIC_ESR_SEND_ACC 0x00004 +#define LAPIC_ESR_RECV_ACC 0x00008 +#define LAPIC_ESR_SENDILL 0x00020 +#define LAPIC_ESR_RECVILL 0x00040 +#define LAPIC_ESR_ILLREGA 0x00080 +#define LAPIC_ICR 0x300 +#define LAPIC_DEST_SELF 0x40000 +#define LAPIC_DEST_ALLINC 0x80000 +#define LAPIC_DEST_ALLBUT 0xC0000 +#define LAPIC_ICR_RR_MASK 0x30000 +#define LAPIC_ICR_RR_INVALID 0x00000 +#define LAPIC_ICR_RR_INPROG 0x10000 +#define LAPIC_ICR_RR_VALID 0x20000 +#define LAPIC_INT_LEVELTRIG 0x08000 +#define LAPIC_INT_ASSERT 0x04000 +#define LAPIC_ICR_BUSY 0x01000 +#define LAPIC_DEST_LOGICAL 0x00800 +#define LAPIC_DM_FIXED 0x00000 +#define LAPIC_DM_LOWEST 0x00100 +#define LAPIC_DM_SMI 0x00200 +#define LAPIC_DM_REMRD 0x00300 +#define LAPIC_DM_NMI 0x00400 +#define LAPIC_DM_INIT 0x00500 +#define LAPIC_DM_STARTUP 0x00600 +#define LAPIC_DM_EXTINT 0x00700 +#define LAPIC_VECTOR_MASK 0x000FF +#define LAPIC_ICR2 0x310 +#define GET_LAPIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) +#define SET_LAPIC_DEST_FIELD(x) ((x) << 24) +#define LAPIC_LVTT 0x320 +#define LAPIC_LVTPC 0x340 +#define LAPIC_LVT0 0x350 +#define LAPIC_LVT_TIMER_BASE_MASK (0x3 << 18) +#define GET_LAPIC_TIMER_BASE(x) (((x) >> 18) & 0x3) +#define SET_LAPIC_TIMER_BASE(x) (((x) << 18)) +#define LAPIC_TIMER_BASE_CLKIN 0x0 +#define LAPIC_TIMER_BASE_TMBASE 0x1 +#define LAPIC_TIMER_BASE_DIV 0x2 +#define LAPIC_LVT_TIMER_PERIODIC (1 << 17) +#define LAPIC_LVT_MASKED (1 << 16) +#define LAPIC_LVT_LEVEL_TRIGGER (1 << 15) +#define LAPIC_LVT_REMOTE_IRR (1 << 14) +#define LAPIC_INPUT_POLARITY (1 << 13) +#define LAPIC_SEND_PENDING (1 << 12) +#define LAPIC_LVT_RESERVED_1 (1 << 11) +#define LAPIC_DELIVERY_MODE_MASK (7 << 8) +#define LAPIC_DELIVERY_MODE_FIXED (0 << 8) +#define LAPIC_DELIVERY_MODE_NMI (4 << 8) +#define LAPIC_DELIVERY_MODE_EXTINT (7 << 8) +#define GET_LAPIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) +#define SET_LAPIC_DELIVERY_MODE(x, y) (((x) & ~0x700)|((y) << 8)) +#define LAPIC_MODE_FIXED 0x0 +#define LAPIC_MODE_NMI 0x4 +#define LAPIC_MODE_EXINT 0x7 +#define LAPIC_LVT1 0x360 +#define LAPIC_LVTERR 0x370 +#define LAPIC_TMICT 0x380 +#define LAPIC_TMCCT 0x390 +#define LAPIC_TDCR 0x3E0 +#define LAPIC_TDR_DIV_TMBASE (1 << 2) +#define LAPIC_TDR_DIV_1 0xB +#define LAPIC_TDR_DIV_2 0x0 +#define LAPIC_TDR_DIV_4 0x1 +#define LAPIC_TDR_DIV_8 0x2 +#define LAPIC_TDR_DIV_16 0x3 +#define LAPIC_TDR_DIV_32 0x8 +#define LAPIC_TDR_DIV_64 0x9 +#define LAPIC_TDR_DIV_128 0xA + +#endif diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 6027d59..2cbb270 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -326,6 +326,8 @@ #define MSR_AMD_PERF_STATUS 0xc0010063 #define MSR_AMD_PERF_CTL 0xc0010062 +#define MSR_PMG_CST_CONFIG_CTL 0x000000e2 +#define MSR_PMG_IO_CAPTURE_ADR 0x000000e4 #define MSR_IA32_MPERF 0x000000e7 #define MSR_IA32_APERF 0x000000e8 diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 3b5915d..1955a75 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -175,6 +175,25 @@ static inline int wrmsr_safe_regs(u32 regs[8]) return native_wrmsr_safe_regs(regs); } +typedef struct msr_t { + uint32_t lo; + uint32_t hi; +} msr_t; + +static inline struct msr_t msr_read(unsigned msr_num) +{ + struct msr_t msr; + + rdmsr(msr_num, msr.lo, msr.hi); + + return msr; +} + +static inline void msr_write(unsigned msr_num, msr_t msr) +{ + wrmsr(msr_num, msr.lo, msr.hi); +} + #define rdtscl(low) \ ((low) = (u32)__native_read_tsc()) @@ -210,17 +229,6 @@ do { \ struct msr *msrs_alloc(void); void msrs_free(struct msr *msrs); -#ifdef CONFIG_SMP -int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); -int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); -void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); -void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); -int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); -int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); -int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); -int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); - -#endif /* CONFIG_SMP */ #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ #endif /* _ASM_X86_MSR_H */ diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h new file mode 100644 index 0000000..5f05a48 --- /dev/null +++ b/arch/x86/include/asm/mtrr.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * From Coreboot file of the same name + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_MTRR_H +#define _ASM_MTRR_H + +/* These are the region types */ +#define MTRR_TYPE_UNCACHEABLE 0 +#define MTRR_TYPE_WRCOMB 1 +/*#define MTRR_TYPE_ 2*/ +/*#define MTRR_TYPE_ 3*/ +#define MTRR_TYPE_WRTHROUGH 4 +#define MTRR_TYPE_WRPROT 5 +#define MTRR_TYPE_WRBACK 6 +#define MTRR_NUM_TYPES 7 + +#define MTRRcap_MSR 0x0fe +#define MTRRdefType_MSR 0x2ff + +#define MTRRdefTypeEn (1 << 11) +#define MTRRdefTypeFixEn (1 << 10) + +#define SMRRphysBase_MSR 0x1f2 +#define SMRRphysMask_MSR 0x1f3 + +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) + +#define MTRRphysMaskValid (1 << 11) + +#define NUM_FIXED_RANGES 88 +#define RANGES_PER_FIXED_MTRR 8 +#define MTRRfix64K_00000_MSR 0x250 +#define MTRRfix16K_80000_MSR 0x258 +#define MTRRfix16K_A0000_MSR 0x259 +#define MTRRfix4K_C0000_MSR 0x268 +#define MTRRfix4K_C8000_MSR 0x269 +#define MTRRfix4K_D0000_MSR 0x26a +#define MTRRfix4K_D8000_MSR 0x26b +#define MTRRfix4K_E0000_MSR 0x26c +#define MTRRfix4K_E8000_MSR 0x26d +#define MTRRfix4K_F0000_MSR 0x26e +#define MTRRfix4K_F8000_MSR 0x26f + +#if !defined(__ASSEMBLER__) + +/* + * The MTRR code has some side effects that the callers should be aware for. + * 1. The call sequence matters. x86_setup_mtrrs() calls + * x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent + * of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers + * want to call the components of x86_setup_mtrrs() because of other + * rquirements the ordering should still preserved. + * 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because + * of the nature of the global MTRR enable flag. Therefore, all direct + * or indirect callers of enable_fixed_mtrr() should ensure that the + * variable MTRR MSRs do not contain bad ranges. + * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling + * the caching of the ROM. However, it is set to uncacheable (UC). It + * is the responsiblity of the caller to enable it by calling + * x86_mtrr_enable_rom_caching(). + */ +void x86_setup_mtrrs(void); +/* + * x86_setup_var_mtrrs() parameters: + * address_bits - number of physical address bits supported by cpu + * above4gb - 2 means dynamically detect number of variable MTRRs available. + * non-zero means handle memory ranges above 4GiB. + * 0 means ignore memory ranges above 4GiB + */ +void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); +void enable_fixed_mtrr(void); +void x86_setup_fixed_mtrrs(void); +/* Set up fixed MTRRs but do not enable them. */ +void x86_setup_fixed_mtrrs_no_enable(void); +int x86_mtrr_check(void); +/* ROM caching can be used after variable MTRRs are set up. Beware that + * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on + * one's IO hole size and WRCOMB resources. Be sure to check the console + * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that + * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the + * rom caching will be disabled if all threads run the MTRR code. Therefore, + * one needs to call x86_mtrr_enable_rom_caching() after all threads of the + * same core have run the MTRR code. */ +#if CONFIG_CACHE_ROM +void x86_mtrr_enable_rom_caching(void); +void x86_mtrr_disable_rom_caching(void); +/* Return the variable range MTRR index of the ROM cache. */ +long x86_mtrr_rom_cache_var_index(void); +#else +static inline void x86_mtrr_enable_rom_caching(void) {} +static inline void x86_mtrr_disable_rom_caching(void) {} +static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } +#endif /* CONFIG_CACHE_ROM */ + +#endif + +#if !defined(CONFIG_RAMTOP) +# error "CONFIG_RAMTOP not defined" +#endif + +#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) +# error "CONFIG_XIP_ROM_SIZE is not a power of 2" +#endif + +#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0) +# error "CONFIG_CACHE_ROM_SIZE is not a power of 2" +#endif + +#define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12) + +#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 +# error "CONFIG_RAMTOP must be a power of 2" +#endif + +#endif diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 6b16188..ac1a808 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -12,5 +12,41 @@ #define DEFINE_PCI_DEVICE_TABLE(_table) \ const struct pci_device_id _table[] +struct pci_controller; + void pci_setup_type1(struct pci_controller *hose); + +/** + * board_pci_setup_hose() - Set up the PCI hose + * + * This is called by the common x86 PCI code to set up the PCI controller + * hose. It may be called when no memory/BSS is available so should just + * store things in 'hose' and not in BSS variables. + */ +void board_pci_setup_hose(struct pci_controller *hose); + +/** + * pci_early_init_hose() - Set up PCI host before relocation + * + * This allocates memory for, sets up and returns the PCI hose. It can be + * called before relocation. The hose will be stored in gd->arch.hose for + * later use, but will become invalid one DRAM is available. + */ +int pci_early_init_hose(struct pci_controller **hosep); + +int board_pci_pre_scan(struct pci_controller *hose); +int board_pci_post_scan(struct pci_controller *hose); + +/* + * Simple PCI access routines - these work from either the early PCI hose + * or the 'real' one, created after U-Boot has memory available + */ +unsigned int pci_read_config8(pci_dev_t dev, unsigned where); +unsigned int pci_read_config16(pci_dev_t dev, unsigned where); +unsigned int pci_read_config32(pci_dev_t dev, unsigned where); + +void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value); +void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value); +void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value); + #endif diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h new file mode 100644 index 0000000..6d2ae5d --- /dev/null +++ b/arch/x86/include/asm/post.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _post_h +#define _post_h + +/* port to use for post codes */ +#define POST_PORT 0x80 + +/* post codes which represent various stages of init */ +#define POST_START 0x1e +#define POST_CAR_START 0x1f +#define POST_CAR_SIPI 0x20 +#define POST_CAR_MTRR 0x21 +#define POST_CAR_UNCACHEABLE 0x22 +#define POST_CAR_BASE_ADDRESS 0x23 +#define POST_CAR_MASK 0x24 +#define POST_CAR_FILL 0x25 +#define POST_CAR_ROM_CACHE 0x26 +#define POST_CAR_MRC_CACHE 0x27 +#define POST_CAR_CPU_CACHE 0x28 +#define POST_START_STACK 0x29 +#define POST_START_DONE 0x2a +#define POST_CPU_INIT 0x2b +#define POST_EARLY_INIT 0x2c +#define POST_CPU_INFO 0x2d +#define POST_PRE_MRC 0x2e +#define POST_MRC 0x2f +#define POST_DRAM 0x2f +#define POST_LAPIC 0x30 + +#define POST_RAM_FAILURE 0xea + +/* Output a post code using al - value must be 0 to 0xff */ +#ifdef __ASSEMBLY__ +#define post_code(value) \ + movb $value, %al; \ + outb %al, $POST_PORT +#else +#include <asm/io.h> + +static inline void post_code(int code) +{ + outb(code, POST_PORT); +} +#endif + +#endif diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index bb3172f..3e26202 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -8,26 +8,40 @@ #ifndef __ASM_PROCESSOR_H_ #define __ASM_PROCESSOR_H_ 1 -#define X86_GDT_ENTRY_SIZE 8 +#define X86_GDT_ENTRY_SIZE 8 + +#define X86_GDT_ENTRY_NULL 0 +#define X86_GDT_ENTRY_UNUSED 1 +#define X86_GDT_ENTRY_32BIT_CS 2 +#define X86_GDT_ENTRY_32BIT_DS 3 +#define X86_GDT_ENTRY_32BIT_FS 4 +#define X86_GDT_ENTRY_16BIT_CS 5 +#define X86_GDT_ENTRY_16BIT_DS 6 +#define X86_GDT_ENTRY_16BIT_FLAT_CS 7 +#define X86_GDT_ENTRY_16BIT_FLAT_DS 8 +#define X86_GDT_NUM_ENTRIES 9 + +#define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE) #ifndef __ASSEMBLY__ -enum { - X86_GDT_ENTRY_NULL = 0, - X86_GDT_ENTRY_UNUSED, - X86_GDT_ENTRY_32BIT_CS, - X86_GDT_ENTRY_32BIT_DS, - X86_GDT_ENTRY_32BIT_FS, - X86_GDT_ENTRY_16BIT_CS, - X86_GDT_ENTRY_16BIT_DS, - X86_GDT_NUM_ENTRIES -}; -#else -/* NOTE: If the above enum is modified, this define must be checked */ -#define X86_GDT_ENTRY_32BIT_DS 3 -#define X86_GDT_NUM_ENTRIES 7 -#endif +#define PORT_RESET 0xcf9 -#define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE) +static inline __attribute__((always_inline)) void cpu_hlt(void) +{ + asm("hlt"); +} + +static inline ulong cpu_get_sp(void) +{ + ulong result; + + asm volatile( + "mov %%esp, %%eax" + : "=a" (result)); + return result; +} + +#endif /* __ASSEMBLY__ */ #endif diff --git a/arch/x86/include/asm/speedstep.h b/arch/x86/include/asm/speedstep.h new file mode 100644 index 0000000..b938b86 --- /dev/null +++ b/arch/x86/include/asm/speedstep.h @@ -0,0 +1,89 @@ +/* + * From Coreboot file of same name + * + * Copyright (C) 2007-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_SPEEDSTEP_H +#define _ASM_SPEEDSTEP_H + +/* Magic value used to locate speedstep configuration in the device tree */ +#define SPEEDSTEP_APIC_MAGIC 0xACAC + +/* MWAIT coordination I/O base address. This must match + * the \_PR_.CPU0 PM base address. + */ +#define PMB0_BASE 0x510 + +/* PMB1: I/O port that triggers SMI once cores are in the same state. + * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] + */ +#define PMB1_BASE 0x800 + +struct sst_state { + uint8_t dynfsb:1; /* whether this is SLFM */ + uint8_t nonint:1; /* add .5 to ratio */ + uint8_t ratio:6; + uint8_t vid; + uint8_t is_turbo; + uint8_t is_slfm; + uint32_t power; +}; +#define SPEEDSTEP_RATIO_SHIFT 8 +#define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT) +#define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT) +#define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_VID_MASK 0x3f +#define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((struct sst_state){ \ + 0, /* dynfsb won't be read. */ \ + ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \ + (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \ + >> SPEEDSTEP_RATIO_SHIFT), \ + (val & mask) & SPEEDSTEP_VID_MASK, \ + 0, /* not turbo by default */ \ + 0, /* not slfm by default */ \ + 0 /* power is hardcoded in software. */ \ + }) +#define SPEEDSTEP_ENCODE_STATE(state) ( \ + ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \ + ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \ + ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \ + ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK)) +#define SPEEDSTEP_DOUBLE_RATIO(state) ( \ + ((uint8_t)(state).ratio * 2) + (state).nonint) + +struct sst_params { + struct sst_state slfm; + struct sst_state min; + struct sst_state max; + struct sst_state turbo; +}; + +/* Looking at core2's spec, the highest normal bus ratio for an eist enabled + processor is 14, the lowest is always 6. This makes 5 states with the + minimal step width of 2. With turbo mode and super LFM we have at most 7. */ +#define SPEEDSTEP_MAX_NORMAL_STATES 5 +#define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2) +struct sst_table { + /* Table of p-states for EMTTM and ACPI by decreasing performance. */ + struct sst_state states[SPEEDSTEP_MAX_STATES]; + int num_states; +}; + +void speedstep_gen_pstates(struct sst_table *); + +#define SPEEDSTEP_MAX_POWER_YONAH 31000 +#define SPEEDSTEP_MIN_POWER_YONAH 13100 +#define SPEEDSTEP_MAX_POWER_MEROM 35000 +#define SPEEDSTEP_MIN_POWER_MEROM 25000 +#define SPEEDSTEP_SLFM_POWER_MEROM 12000 +#define SPEEDSTEP_MAX_POWER_PENRYN 35000 +#define SPEEDSTEP_MIN_POWER_PENRYN 15000 +#define SPEEDSTEP_SLFM_POWER_PENRYN 12000 + +#endif diff --git a/arch/x86/include/asm/turbo.h b/arch/x86/include/asm/turbo.h new file mode 100644 index 0000000..bb0d4b4 --- /dev/null +++ b/arch/x86/include/asm/turbo.h @@ -0,0 +1,31 @@ +/* + * From coreboot file of the same name + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_TURBO_H +#define _ASM_TURBO_H + +#define CPUID_LEAF_PM 6 +#define PM_CAP_TURBO_MODE (1 << 1) + +#define MSR_IA32_MISC_ENABLES 0x1a0 +#define H_MISC_DISABLE_TURBO (1 << 6) + +enum { + TURBO_UNKNOWN, + TURBO_UNAVAILABLE, + TURBO_DISABLED, + TURBO_ENABLED, +}; + +/* Return current turbo state */ +int turbo_get_state(void); + +/* Enable turbo */ +void turbo_enable(void); + +#endif diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 9e525dd..36145cb 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -9,8 +9,7 @@ #define _U_BOOT_I386_H_ 1 /* cpu/.../cpu.c */ -int x86_cpu_init_r(void); -int cpu_init_r(void); +int arch_cpu_init(void); int x86_cpu_init_f(void); int cpu_init_f(void); void init_gd(gd_t *id, u64 *gdt_addr); @@ -27,8 +26,8 @@ unsigned long get_tbclk_mhz(void); void timer_set_base(uint64_t base); int pcat_timer_init(void); -/* Architecture specific - can be in arch/x86/cpu/, arch/x86/lib/, or $(BOARD)/ */ -int dram_init_f(void); +/* Architecture specific DRAM init */ +int dram_init(void); /* cpu/.../interrupts.c */ int cpu_init_interrupts(void); @@ -36,6 +35,16 @@ int cpu_init_interrupts(void); /* board/.../... */ int dram_init(void); +int cleanup_before_linux(void); +int x86_cleanup_before_linux(void); +void x86_enable_caches(void); +void x86_disable_caches(void); +int x86_init_cache(void); +void reset_cpu(ulong addr); +ulong board_get_usable_ram_top(ulong total_size); +void dram_init_banksize(void); +int default_print_cpuinfo(void); + void setup_pcat_compatibility(void); void isa_unmap_rom(u32 addr); @@ -59,4 +68,6 @@ static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void) void timer_set_tsc_base(uint64_t new_base); uint64_t timer_get_tsc(void); +void quick_ram_check(void); + #endif /* _U_BOOT_I386_H_ */ diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 25b672a..55de788 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -5,6 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-y += bios.o +obj-y += bios_asm.o +obj-y += bios_interrupts.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cmd_boot.o obj-y += gcc.o @@ -15,6 +18,7 @@ obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o obj-$(CONFIG_PCI) += pci_type1.o obj-y += relocate.o obj-y += physmem.o +obj-$(CONFIG_X86_RAMTEST) += ramtest.o obj-y += string.o obj-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_VIDEO_VGA) += video.o diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c new file mode 100644 index 0000000..298fca6 --- /dev/null +++ b/arch/x86/lib/bios.c @@ -0,0 +1,347 @@ +/* + * From Coreboot file device/oprom/realmode/x86.c + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2009-2010 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include <common.h> +#include <bios_emul.h> +#include <vbe.h> +#include <asm/cache.h> +#include <asm/processor.h> +#include <asm/i8259.h> +#include <asm/io.h> +#include <asm/post.h> +#include "bios.h" + +/* Interrupt handlers for each interrupt the ROM can call */ +static int (*int_handler[256])(void); + +/* to have a common register file for interrupt handlers */ +X86EMU_sysEnv _X86EMU_env; + +asmlinkage void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi); + +asmlinkage void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, + u32 edx, u32 esi, u32 edi); + +static void setup_realmode_code(void) +{ + memcpy((void *)REALMODE_BASE, &asm_realmode_code, + asm_realmode_code_size); + + /* Ensure the global pointers are relocated properly. */ + realmode_call = PTR_TO_REAL_MODE(asm_realmode_call); + realmode_interrupt = PTR_TO_REAL_MODE(__realmode_interrupt); + + debug("Real mode stub @%x: %d bytes\n", REALMODE_BASE, + asm_realmode_code_size); +} + +static void setup_rombios(void) +{ + const char date[] = "06/11/99"; + memcpy((void *)0xffff5, &date, 8); + + const char ident[] = "PCI_ISA"; + memcpy((void *)0xfffd9, &ident, 7); + + /* system model: IBM-AT */ + writeb(0xfc, 0xffffe); +} + +static int int_exception_handler(void) +{ + /* compatibility shim */ + struct eregs reg_info = { + .eax = M.x86.R_EAX, + .ecx = M.x86.R_ECX, + .edx = M.x86.R_EDX, + .ebx = M.x86.R_EBX, + .esp = M.x86.R_ESP, + .ebp = M.x86.R_EBP, + .esi = M.x86.R_ESI, + .edi = M.x86.R_EDI, + .vector = M.x86.intno, + .error_code = 0, + .eip = M.x86.R_EIP, + .cs = M.x86.R_CS, + .eflags = M.x86.R_EFLG + }; + struct eregs *regs = ®_info; + + debug("Oops, exception %d while executing option rom\n", regs->vector); + cpu_hlt(); + + return 0; +} + +static int int_unknown_handler(void) +{ + debug("Unsupported software interrupt #0x%x eax 0x%x\n", + M.x86.intno, M.x86.R_EAX); + + return -1; +} + +/* setup interrupt handlers for mainboard */ +void bios_set_interrupt_handler(int intnum, int (*int_func)(void)) +{ + int_handler[intnum] = int_func; +} + +static void setup_interrupt_handlers(void) +{ + int i; + + /* + * The first 16 int_handler functions are not BIOS services, + * but the CPU-generated exceptions ("hardware interrupts") + */ + for (i = 0; i < 0x10; i++) + int_handler[i] = &int_exception_handler; + + /* Mark all other int_handler calls as unknown first */ + for (i = 0x10; i < 0x100; i++) { + /* Skip if bios_set_interrupt_handler() isn't called first */ + if (int_handler[i]) + continue; + + /* + * Now set the default functions that are actually needed + * to initialize the option roms. The board may override + * these with bios_set_interrupt_handler() + */ + switch (i) { + case 0x10: + int_handler[0x10] = &int10_handler; + break; + case 0x12: + int_handler[0x12] = &int12_handler; + break; + case 0x16: + int_handler[0x16] = &int16_handler; + break; + case 0x1a: + int_handler[0x1a] = &int1a_handler; + break; + default: + int_handler[i] = &int_unknown_handler; + break; + } + } +} + +static void write_idt_stub(void *target, u8 intnum) +{ + unsigned char *codeptr; + + codeptr = (unsigned char *)target; + memcpy(codeptr, &__idt_handler, __idt_handler_size); + codeptr[3] = intnum; /* modify int# in the code stub. */ +} + +static void setup_realmode_idt(void) +{ + struct realmode_idt *idts = NULL; + int i; + + /* + * Copy IDT stub code for each interrupt. This might seem wasteful + * but it is really simple + */ + for (i = 0; i < 256; i++) { + idts[i].cs = 0; + idts[i].offset = 0x1000 + (i * __idt_handler_size); + write_idt_stub((void *)((u32)idts[i].offset), i); + } + + /* + * Many option ROMs use the hard coded interrupt entry points in the + * system bios. So install them at the known locations. + */ + + /* int42 is the relocated int10 */ + write_idt_stub((void *)0xff065, 0x42); + /* BIOS Int 11 Handler F000:F84D */ + write_idt_stub((void *)0xff84d, 0x11); + /* BIOS Int 12 Handler F000:F841 */ + write_idt_stub((void *)0xff841, 0x12); + /* BIOS Int 13 Handler F000:EC59 */ + write_idt_stub((void *)0xfec59, 0x13); + /* BIOS Int 14 Handler F000:E739 */ + write_idt_stub((void *)0xfe739, 0x14); + /* BIOS Int 15 Handler F000:F859 */ + write_idt_stub((void *)0xff859, 0x15); + /* BIOS Int 16 Handler F000:E82E */ + write_idt_stub((void *)0xfe82e, 0x16); + /* BIOS Int 17 Handler F000:EFD2 */ + write_idt_stub((void *)0xfefd2, 0x17); + /* ROM BIOS Int 1A Handler F000:FE6E */ + write_idt_stub((void *)0xffe6e, 0x1a); +} + +static u8 vbe_get_mode_info(struct vbe_mode_info *mi) +{ + u16 buffer_seg; + u16 buffer_adr; + char *buffer; + + debug("VBE: Getting information about VESA mode %04x\n", + mi->video_mode); + buffer = PTR_TO_REAL_MODE(asm_realmode_buffer); + buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00; + buffer_adr = ((unsigned long)buffer) & 0xffff; + + realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, mi->video_mode, + 0x0000, buffer_seg, buffer_adr); + memcpy(mi->mode_info_block, buffer, sizeof(struct vbe_mode_info)); + mi->valid = true; + + return 0; +} + +static u8 vbe_set_mode(struct vbe_mode_info *mi) +{ + debug("VBE: Setting VESA mode %#04x\n", mi->video_mode); + /* request linear framebuffer mode */ + mi->video_mode |= (1 << 14); + /* request clearing of framebuffer */ + mi->video_mode &= ~(1 << 15); + realmode_interrupt(0x10, VESA_SET_MODE, mi->video_mode, + 0x0000, 0x0000, 0x0000, 0x0000); + + return 0; +} + +static void vbe_set_graphics(int vesa_mode, struct vbe_mode_info *mode_info) +{ + unsigned char *framebuffer; + + mode_info->video_mode = (1 << 14) | vesa_mode; + vbe_get_mode_info(mode_info); + + framebuffer = (unsigned char *)mode_info->vesa.phys_base_ptr; + debug("VBE: resolution: %dx%d@%d\n", + le16_to_cpu(mode_info->vesa.x_resolution), + le16_to_cpu(mode_info->vesa.y_resolution), + mode_info->vesa.bits_per_pixel); + debug("VBE: framebuffer: %p\n", framebuffer); + if (!framebuffer) { + debug("VBE: Mode does not support linear framebuffer\n"); + return; + } + + vbe_set_mode(mode_info); +} + +void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode, + struct vbe_mode_info *mode_info) +{ + u32 num_dev; + + num_dev = PCI_BUS(pcidev) << 8 | PCI_DEV(pcidev) << 3 | + PCI_FUNC(pcidev); + + /* Needed to avoid exceptions in some ROMs */ + interrupt_init(); + + /* Set up some legacy information in the F segment */ + setup_rombios(); + + /* Set up C interrupt handlers */ + setup_interrupt_handlers(); + + /* Set up real-mode IDT */ + setup_realmode_idt(); + + /* Make sure the code is placed. */ + setup_realmode_code(); + + disable_caches(); + debug("Calling Option ROM at %lx, pci device %#x...", addr, num_dev); + + /* Option ROM entry point is at OPROM start + 3 */ + realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, + 0x0); + debug("done\n"); + + if (vesa_mode != -1) + vbe_set_graphics(vesa_mode, mode_info); +} + +asmlinkage int interrupt_handler(u32 intnumber, u32 gsfs, u32 dses, + u32 edi, u32 esi, u32 ebp, u32 esp, + u32 ebx, u32 edx, u32 ecx, u32 eax, + u32 cs_ip, u16 stackflags) +{ + u32 ip; + u32 cs; + u32 flags; + int ret = 0; + + ip = cs_ip & 0xffff; + cs = cs_ip >> 16; + flags = stackflags; + +#ifdef CONFIG_REALMODE_DEBUG + debug("oprom: INT# 0x%x\n", intnumber); + debug("oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n", + eax, ebx, ecx, edx); + debug("oprom: ebp: %08x esp: %08x edi: %08x esi: %08x\n", + ebp, esp, edi, esi); + debug("oprom: ip: %04x cs: %04x flags: %08x\n", + ip, cs, flags); + debug("oprom: stackflags = %04x\n", stackflags); +#endif + + /* + * Fetch arguments from the stack and put them to a place + * suitable for the interrupt handlers + */ + M.x86.R_EAX = eax; + M.x86.R_ECX = ecx; + M.x86.R_EDX = edx; + M.x86.R_EBX = ebx; + M.x86.R_ESP = esp; + M.x86.R_EBP = ebp; + M.x86.R_ESI = esi; + M.x86.R_EDI = edi; + M.x86.intno = intnumber; + M.x86.R_EIP = ip; + M.x86.R_CS = cs; + M.x86.R_EFLG = flags; + + /* Call the interrupt handler for this interrupt number */ + ret = int_handler[intnumber](); + + /* + * This code is quite strange... + * + * Put registers back on the stack. The assembler code will pop them + * later. We force (volatile!) changing the values of the parameters + * of this function. We know that they stay alive on the stack after + * we leave this function. + */ + *(volatile u32 *)&eax = M.x86.R_EAX; + *(volatile u32 *)&ecx = M.x86.R_ECX; + *(volatile u32 *)&edx = M.x86.R_EDX; + *(volatile u32 *)&ebx = M.x86.R_EBX; + *(volatile u32 *)&esi = M.x86.R_ESI; + *(volatile u32 *)&edi = M.x86.R_EDI; + flags = M.x86.R_EFLG; + + /* Pass success or error back to our caller via the CARRY flag */ + if (ret) { + flags &= ~1; /* no error: clear carry */ + } else { + debug("int%02x call returned error\n", intnumber); + flags |= 1; /* error: set carry */ + } + *(volatile u16 *)&stackflags = flags; + + return ret; +} diff --git a/arch/x86/lib/bios.h b/arch/x86/lib/bios.h new file mode 100644 index 0000000..8491b4a --- /dev/null +++ b/arch/x86/lib/bios.h @@ -0,0 +1,98 @@ +/* + * From Coreboot file device/oprom/realmode/x86.h + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2009-2010 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _X86_LIB_BIOS_H +#define _X86_LIB_BIOS_H + +#define REALMODE_BASE 0x600 + +#ifdef __ASSEMBLY__ + +#define PTR_TO_REAL_MODE(x) (x - asm_realmode_code + REALMODE_BASE) + +#else + +/* Convert a symbol address to our real mode area */ +#define PTR_TO_REAL_MODE(sym)\ + (void *)(REALMODE_BASE + ((char *)&(sym) - (char *)&asm_realmode_code)) + +/* + * The following symbols cannot be used directly. They need to be fixed up + * to point to the correct address location after the code has been copied + * to REALMODE_BASE. Absolute symbols are not used because those symbols are + * relocated by U-Boot. + */ +extern unsigned char asm_realmode_call, __realmode_interrupt; +extern unsigned char asm_realmode_buffer; + +#define DOWNTO8(A) \ + union { \ + struct { \ + union { \ + struct { \ + uint8_t A##l; \ + uint8_t A##h; \ + } __packed; \ + uint16_t A##x; \ + } __packed; \ + uint16_t h##A##x; \ + } __packed; \ + uint32_t e##A##x; \ + } __packed; + +#define DOWNTO16(A) \ + union { \ + struct { \ + uint16_t A; \ + uint16_t h##A; \ + } __packed; \ + uint32_t e##A; \ + } __packed; + +struct eregs { + DOWNTO8(a); + DOWNTO8(c); + DOWNTO8(d); + DOWNTO8(b); + DOWNTO16(sp); + DOWNTO16(bp); + DOWNTO16(si); + DOWNTO16(di); + uint32_t vector; + uint32_t error_code; + uint32_t eip; + uint32_t cs; + uint32_t eflags; +}; + +struct realmode_idt { + u16 offset, cs; +}; + +void x86_exception(struct eregs *info); + +/* From x86_asm.S */ +extern unsigned char __idt_handler; +extern unsigned int __idt_handler_size; +extern unsigned char asm_realmode_code; +extern unsigned int asm_realmode_code_size; + +asmlinkage void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi); + +asmlinkage void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, + u32 edx, u32 esi, u32 edi); + +int int10_handler(void); +int int12_handler(void); +int int16_handler(void); +int int1a_handler(void); +#endif /*__ASSEMBLY__ */ + +#endif diff --git a/arch/x86/lib/bios_asm.S b/arch/x86/lib/bios_asm.S new file mode 100644 index 0000000..4faa70e --- /dev/null +++ b/arch/x86/lib/bios_asm.S @@ -0,0 +1,281 @@ +/* + * From coreboot x86_asm.S, cleaned up substantially + * + * Copyright (C) 2009-2010 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <asm/processor.h> +#include <asm/processor-flags.h> +#include "bios.h" + +#define SEG(segment) $segment * X86_GDT_ENTRY_SIZE + +/* + * This is the interrupt handler stub code. It gets copied to the IDT and + * to some fixed addresses in the F segment. Before the code can used, + * it gets patched up by the C function copying it: byte 3 (the $0 in + * movb $0, %al) is overwritten with the interrupt numbers. + */ + + .code16 + .globl __idt_handler +__idt_handler: + pushal + movb $0, %al /* This instruction gets modified */ + ljmp $0, $__interrupt_handler_16bit + .globl __idt_handler_size +__idt_handler_size: + .long . - __idt_handler + +.macro setup_registers + /* initial register values */ + movl 44(%ebp), %eax + movl %eax, __registers + 0 /* eax */ + movl 48(%ebp), %eax + movl %eax, __registers + 4 /* ebx */ + movl 52(%ebp), %eax + movl %eax, __registers + 8 /* ecx */ + movl 56(%ebp), %eax + movl %eax, __registers + 12 /* edx */ + movl 60(%ebp), %eax + movl %eax, __registers + 16 /* esi */ + movl 64(%ebp), %eax + movl %eax, __registers + 20 /* edi */ +.endm + +.macro enter_real_mode + /* Activate the right segment descriptor real mode. */ + ljmp SEG(X86_GDT_ENTRY_16BIT_CS), $PTR_TO_REAL_MODE(1f) +1: +.code16 + /* + * Load the segment registers with properly configured segment + * descriptors. They will retain these configurations (limits, + * writability, etc.) once protected mode is turned off. + */ + mov SEG(X86_GDT_ENTRY_16BIT_DS), %ax + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss + + /* Turn off protection */ + movl %cr0, %eax + andl $~X86_CR0_PE, %eax + movl %eax, %cr0 + + /* Now really going into real mode */ + ljmp $0, $PTR_TO_REAL_MODE(1f) +1: + /* + * Set up a stack: Put the stack at the end of page zero. That way + * we can easily share it between real and protected, since the + * 16-bit ESP at segment 0 will work for any case. + */ + mov $0x0, %ax + mov %ax, %ss + + /* Load 16 bit IDT */ + xor %ax, %ax + mov %ax, %ds + lidt __realmode_idt + +.endm + +.macro prepare_for_irom + movl $0x1000, %eax + movl %eax, %esp + + /* Initialise registers for option rom lcall */ + movl __registers + 0, %eax + movl __registers + 4, %ebx + movl __registers + 8, %ecx + movl __registers + 12, %edx + movl __registers + 16, %esi + movl __registers + 20, %edi + + /* Set all segments to 0x0000, ds to 0x0040 */ + push %ax + xor %ax, %ax + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov SEG(X86_GDT_ENTRY_16BIT_FLAT_DS), %ax + mov %ax, %ds + pop %ax + +.endm + +.macro enter_protected_mode + /* Go back to protected mode */ + movl %cr0, %eax + orl $X86_CR0_PE, %eax + movl %eax, %cr0 + + /* Now that we are in protected mode jump to a 32 bit code segment */ + data32 ljmp SEG(X86_GDT_ENTRY_32BIT_CS), $PTR_TO_REAL_MODE(1f) +1: + .code32 + mov SEG(X86_GDT_ENTRY_32BIT_DS), %ax + mov %ax, %ds + mov %ax, %es + mov %ax, %gs + mov %ax, %ss + mov SEG(X86_GDT_ENTRY_32BIT_FS), %ax + mov %ax, %fs + + /* restore proper idt */ + lidt idt_ptr +.endm + +/* + * In order to be independent of U-Boot's position in RAM we relocate a part + * of the code to the first megabyte of RAM, so the CPU can use it in + * real-mode. This code lives at asm_realmode_code. + */ + .globl asm_realmode_code +asm_realmode_code: + +/* Realmode IDT pointer structure. */ +__realmode_idt = PTR_TO_REAL_MODE(.) + .word 1023 /* 16 bit limit */ + .long 0 /* 24 bit base */ + .word 0 + +/* Preserve old stack */ +__stack = PTR_TO_REAL_MODE(.) + .long 0 + +/* Register store for realmode_call and realmode_interrupt */ +__registers = PTR_TO_REAL_MODE(.) + .long 0 /* 0 - EAX */ + .long 0 /* 4 - EBX */ + .long 0 /* 8 - ECX */ + .long 0 /* 12 - EDX */ + .long 0 /* 16 - ESI */ + .long 0 /* 20 - EDI */ + +/* 256 byte buffer, used by int10 */ + .globl asm_realmode_buffer +asm_realmode_buffer: + .skip 256 + + .code32 + .globl asm_realmode_call +asm_realmode_call: + /* save all registers to the stack */ + pusha + pushf + movl %esp, __stack + movl %esp, %ebp + + /* + * This function is called with regparm=0 and we have to skip the + * 36 bytes from pushf+pusha. Hence start at 40. + * Set up our call instruction. + */ + movl 40(%ebp), %eax + mov %ax, __lcall_instr + 1 + andl $0xffff0000, %eax + shrl $4, %eax + mov %ax, __lcall_instr + 3 + + wbinvd + + setup_registers + enter_real_mode + prepare_for_irom + +__lcall_instr = PTR_TO_REAL_MODE(.) + .byte 0x9a + .word 0x0000, 0x0000 + + enter_protected_mode + + /* restore stack pointer, eflags and register values and exit */ + movl __stack, %esp + popf + popa + ret + + .globl __realmode_interrupt +__realmode_interrupt: + /* save all registers to the stack and store the stack pointer */ + pusha + pushf + movl %esp, __stack + movl %esp, %ebp + + /* + * This function is called with regparm=0 and we have to skip the + * 36 bytes from pushf+pusha. Hence start at 40. + * Prepare interrupt calling code. + */ + movl 40(%ebp), %eax + movb %al, __intXX_instr + 1 /* intno */ + + setup_registers + enter_real_mode + prepare_for_irom + +__intXX_instr = PTR_TO_REAL_MODE(.) + .byte 0xcd, 0x00 /* This becomes intXX */ + + enter_protected_mode + + /* restore stack pointer, eflags and register values and exit */ + movl __stack, %esp + popf + popa + ret + +/* + * This is the 16-bit interrupt entry point called by the IDT stub code. + * + * Before this code code is called, %eax is pushed to the stack, and the + * interrupt number is loaded into %al. On return this function cleans up + * for its caller. + */ + .code16 +__interrupt_handler_16bit = PTR_TO_REAL_MODE(.) + push %ds + push %es + push %fs + push %gs + + /* Clear DF to not break ABI assumptions */ + cld + + /* + * Clean up the interrupt number. We could do this in the stub, but + * it would cost two more bytes per stub entry. + */ + andl $0xff, %eax + pushl %eax /* ... and make it the first parameter */ + + enter_protected_mode + + /* Call the C interrupt handler */ + movl $interrupt_handler, %eax + call *%eax + + enter_real_mode + + /* + * Restore all registers, including those manipulated by the C + * handler + */ + popl %eax + pop %gs + pop %fs + pop %es + pop %ds + popal + iret + + .globl asm_realmode_code_size +asm_realmode_code_size: + .long . - asm_realmode_code diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c new file mode 100644 index 0000000..b0e2ecb --- /dev/null +++ b/arch/x86/lib/bios_interrupts.c @@ -0,0 +1,217 @@ +/* + * From Coreboot + * + * Copyright (C) 2001 Ronald G. Minnich + * Copyright (C) 2005 Nick.Barker9@btinternet.com + * Copyright (C) 2007-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/pci.h> +#include "bios_emul.h" + +/* errors go in AH. Just set these up so that word assigns will work */ +enum { + PCIBIOS_SUCCESSFUL = 0x0000, + PCIBIOS_UNSUPPORTED = 0x8100, + PCIBIOS_BADVENDOR = 0x8300, + PCIBIOS_NODEV = 0x8600, + PCIBIOS_BADREG = 0x8700 +}; + +int int10_handler(void) +{ + static u8 cursor_row, cursor_col; + int res = 0; + + switch ((M.x86.R_EAX & 0xff00) >> 8) { + case 0x01: /* Set cursor shape */ + res = 1; + break; + case 0x02: /* Set cursor position */ + if (cursor_row != ((M.x86.R_EDX >> 8) & 0xff) || + cursor_col >= (M.x86.R_EDX & 0xff)) { + debug("\n"); + } + cursor_row = (M.x86.R_EDX >> 8) & 0xff; + cursor_col = M.x86.R_EDX & 0xff; + res = 1; + break; + case 0x03: /* Get cursor position */ + M.x86.R_EAX &= 0x00ff; + M.x86.R_ECX = 0x0607; + M.x86.R_EDX = (cursor_row << 8) | cursor_col; + res = 1; + break; + case 0x06: /* Scroll up */ + debug("\n"); + res = 1; + break; + case 0x08: /* Get Character and Mode at Cursor Position */ + M.x86.R_EAX = 0x0f00 | 'A'; /* White on black 'A' */ + res = 1; + break; + case 0x09: /* Write Character and attribute */ + case 0x0e: /* Write Character */ + debug("%c", M.x86.R_EAX & 0xff); + res = 1; + break; + case 0x0f: /* Get video mode */ + M.x86.R_EAX = 0x5002; /*80 x 25 */ + M.x86.R_EBX &= 0x00ff; + res = 1; + break; + default: + printf("Unknown INT10 function %04x\n", M.x86.R_EAX & 0xffff); + break; + } + return res; +} + +int int12_handler(void) +{ + M.x86.R_EAX = 64 * 1024; + return 1; +} + +int int16_handler(void) +{ + int res = 0; + + switch ((M.x86.R_EAX & 0xff00) >> 8) { + case 0x00: /* Check for Keystroke */ + M.x86.R_EAX = 0x6120; /* Space Bar, Space */ + res = 1; + break; + case 0x01: /* Check for Keystroke */ + M.x86.R_EFLG |= 1 << 6; /* Zero Flag set (no key available) */ + res = 1; + break; + default: + printf("Unknown INT16 function %04x\n", M.x86.R_EAX & 0xffff); + +break; + } + return res; +} + +#define PCI_CONFIG_SPACE_TYPE1 (1 << 0) +#define PCI_SPECIAL_CYCLE_TYPE1 (1 << 4) + +int int1a_handler(void) +{ + unsigned short func = (unsigned short)M.x86.R_EAX; + int retval = 1; + unsigned short devid, vendorid, devfn; + /* Use short to get rid of gabage in upper half of 32-bit register */ + short devindex; + unsigned char bus; + pci_dev_t dev; + u32 dword; + u16 word; + u8 byte, reg; + + switch (func) { + case 0xb101: /* PCIBIOS Check */ + M.x86.R_EDX = 0x20494350; /* ' ICP' */ + M.x86.R_EAX &= 0xffff0000; /* Clear AH / AL */ + M.x86.R_EAX |= PCI_CONFIG_SPACE_TYPE1 | + PCI_SPECIAL_CYCLE_TYPE1; + /* + * last bus in the system. Hard code to 255 for now. + * dev_enumerate() does not seem to tell us (publically) + */ + M.x86.R_ECX = 0xff; + M.x86.R_EDI = 0x00000000; /* protected mode entry */ + retval = 1; + break; + case 0xb102: /* Find Device */ + devid = M.x86.R_ECX; + vendorid = M.x86.R_EDX; + devindex = M.x86.R_ESI; + dev = pci_find_device(vendorid, devid, devindex); + if (dev != -1) { + unsigned short busdevfn; + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_SUCCESSFUL; + /* + * busnum is an unsigned char; + * devfn is an int, so we mask it off. + */ + busdevfn = (PCI_BUS(dev) << 8) | PCI_DEV(dev) << 3 | + PCI_FUNC(dev); + debug("0x%x: return 0x%x\n", func, busdevfn); + M.x86.R_EBX = busdevfn; + retval = 1; + } else { + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_NODEV; + retval = 0; + } + break; + case 0xb10a: /* Read Config Dword */ + case 0xb109: /* Read Config Word */ + case 0xb108: /* Read Config Byte */ + case 0xb10d: /* Write Config Dword */ + case 0xb10c: /* Write Config Word */ + case 0xb10b: /* Write Config Byte */ + devfn = M.x86.R_EBX & 0xff; + bus = M.x86.R_EBX >> 8; + reg = M.x86.R_EDI; + dev = PCI_BDF(bus, devfn >> 3, devfn & 7); + if (!dev) { + debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, + bus, devfn); + /* Or are we supposed to return PCIBIOS_NODEV? */ + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_BADREG; + retval = 0; + return retval; + } + switch (func) { + case 0xb108: /* Read Config Byte */ + byte = pci_read_config8(dev, reg); + M.x86.R_ECX = byte; + break; + case 0xb109: /* Read Config Word */ + word = pci_read_config16(dev, reg); + M.x86.R_ECX = word; + break; + case 0xb10a: /* Read Config Dword */ + dword = pci_read_config32(dev, reg); + M.x86.R_ECX = dword; + break; + case 0xb10b: /* Write Config Byte */ + byte = M.x86.R_ECX; + pci_write_config8(dev, reg, byte); + break; + case 0xb10c: /* Write Config Word */ + word = M.x86.R_ECX; + pci_write_config16(dev, reg, word); + break; + case 0xb10d: /* Write Config Dword */ + dword = M.x86.R_ECX; + pci_write_config32(dev, reg, dword); + break; + } + +#ifdef CONFIG_REALMODE_DEBUG + debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func, + bus, devfn, reg, M.x86.R_ECX); +#endif + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_SUCCESSFUL; + retval = 1; + break; + default: + printf("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func); + M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ + M.x86.R_EAX |= PCIBIOS_UNSUPPORTED; + retval = 0; + break; + } + + return retval; +} diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index b5d937f..be4eb12 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -87,30 +87,3 @@ int init_func_spi(void) puts("ready\n"); return 0; } - -int find_fdt(void) -{ -#ifdef CONFIG_OF_EMBED - /* Get a pointer to the FDT */ - gd->fdt_blob = __dtb_dt_begin; -#elif defined CONFIG_OF_SEPARATE - /* FDT is at end of image */ - gd->fdt_blob = (ulong *)&_end; -#endif - /* Allow the early environment to override the fdt address */ - gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, - (uintptr_t)gd->fdt_blob); - - return 0; -} - -int prepare_fdt(void) -{ - /* For now, put this check after the console is ready */ - if (fdtdec_prepare_fdt()) { - panic("** CONFIG_OF_CONTROL defined but no FDT - please see " - "doc/README.fdt-control"); - } - - return 0; -} diff --git a/arch/x86/lib/pcat_interrupts.c b/arch/x86/lib/pcat_interrupts.c index 4c86f7f..a9af87e 100644 --- a/arch/x86/lib/pcat_interrupts.c +++ b/arch/x86/lib/pcat_interrupts.c @@ -24,12 +24,10 @@ #error "CONFIG_SYS_NUM_IRQS must equal 16 if CONFIG_SYS_NUM_IRQS is defined" #endif -int interrupt_init(void) +int i8259_init(void) { u8 i; - disable_interrupts(); - /* Mask all interrupts */ outb(0xff, MASTER_PIC + IMR); outb(0xff, SLAVE_PIC + IMR); @@ -62,7 +60,8 @@ int interrupt_init(void) */ unmask_irq(2); - enable_interrupts(); + /* Interrupt 9 should be level triggered (SCI). The OS might do this */ + configure_irq_trigger(9, true); return 0; } @@ -114,3 +113,38 @@ void specific_eoi(int irq) outb(OCW2_SEOI | irq, MASTER_PIC + OCW2); } + +#define ELCR1 0x4d0 +#define ELCR2 0x4d1 + +void configure_irq_trigger(int int_num, bool is_level_triggered) +{ + u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8); + + debug("%s: current interrupts are 0x%x\n", __func__, int_bits); + if (is_level_triggered) + int_bits |= (1 << int_num); + else + int_bits &= ~(1 << int_num); + + /* Write new values */ + debug("%s: try to set interrupts 0x%x\n", __func__, int_bits); + outb((u8)(int_bits & 0xff), ELCR1); + outb((u8)(int_bits >> 8), ELCR2); + +#ifdef PARANOID_IRQ_TRIGGERS + /* + * Try reading back the new values. This seems like an error but is + * not + */ + if (inb(ELCR1) != (int_bits & 0xff)) { + printf("%s: lower order bits are wrong: want 0x%x, got 0x%x\n", + __func__, (int_bits & 0xff), inb(ELCR1)); + } + + if (inb(ELCR2) != (int_bits >> 8)) { + printf("%s: higher order bits are wrong: want 0x%x, got 0x%x\n", + __func__, (int_bits>>8), inb(ELCR2)); + } +#endif +} diff --git a/arch/x86/lib/ramtest.c b/arch/x86/lib/ramtest.c new file mode 100644 index 0000000..c21be03 --- /dev/null +++ b/arch/x86/lib/ramtest.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * From Coreboot src/lib/ramtest.c + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/post.h> + +static void write_phys(unsigned long addr, u32 value) +{ +#if CONFIG_SSE2 + asm volatile( + "movnti %1, (%0)" + : /* outputs */ + : "r" (addr), "r" (value) /* inputs */ + : /* clobbers */ + ); +#else + writel(value, addr); +#endif +} + +static u32 read_phys(unsigned long addr) +{ + return readl(addr); +} + +static void phys_memory_barrier(void) +{ +#if CONFIG_SSE2 + /* Needed for movnti */ + asm volatile( + "sfence" + : + : + : "memory" + ); +#else + asm volatile("" + : + : + : "memory"); +#endif +} + +void quick_ram_check(void) +{ + int fail = 0; + u32 backup; + + backup = read_phys(CONFIG_RAMBASE); + write_phys(CONFIG_RAMBASE, 0x55555555); + phys_memory_barrier(); + if (read_phys(CONFIG_RAMBASE) != 0x55555555) + fail = 1; + write_phys(CONFIG_RAMBASE, 0xaaaaaaaa); + phys_memory_barrier(); + if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa) + fail = 1; + write_phys(CONFIG_RAMBASE, 0x00000000); + phys_memory_barrier(); + if (read_phys(CONFIG_RAMBASE) != 0x00000000) + fail = 1; + write_phys(CONFIG_RAMBASE, 0xffffffff); + phys_memory_barrier(); + if (read_phys(CONFIG_RAMBASE) != 0xffffffff) + fail = 1; + + write_phys(CONFIG_RAMBASE, backup); + if (fail) { + post_code(POST_RAM_FAILURE); + panic("RAM INIT FAILURE!\n"); + } + phys_memory_barrier(); +} diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index faca38f..b33586b 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -76,6 +76,9 @@ int do_elf_reloc_fixups(void) /* The size of the region of u-boot that runs out of RAM. */ uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start; + if (re_src == re_end) + panic("No relocation data"); + do { /* Get the location from the relocation entry */ offset_ptr_rom = (Elf32_Addr *)re_src->r_offset; diff --git a/arch/x86/lib/string.c b/arch/x86/lib/string.c index a1656cc..6c66431 100644 --- a/arch/x86/lib/string.c +++ b/arch/x86/lib/string.c @@ -8,9 +8,9 @@ /* From glibc-2.14, sysdeps/i386/memset.c */ -#include <compiler.h> -#include <asm/string.h> #include <linux/types.h> +#include <linux/compiler.h> +#include <asm/string.h> typedef uint32_t op_t; diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c index 8b38702..fb9afed 100644 --- a/arch/x86/lib/tsc_timer.c +++ b/arch/x86/lib/tsc_timer.c @@ -1,6 +1,9 @@ /* * Copyright (c) 2012 The Chromium OS Authors. * + * TSC calibration codes are adapted from Linux kernel + * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -12,8 +15,269 @@ #include <asm/msr.h> #include <asm/u-boot-x86.h> +/* CPU reference clock frequency: in KHz */ +#define FREQ_83 83200 +#define FREQ_100 99840 +#define FREQ_133 133200 +#define FREQ_166 166400 + +#define MAX_NUM_FREQS 8 + DECLARE_GLOBAL_DATA_PTR; +/* + * According to Intel 64 and IA-32 System Programming Guide, + * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be + * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40]. + * Unfortunately some Intel Atom SoCs aren't quite compliant to this, + * so we need manually differentiate SoC families. This is what the + * field msr_plat does. + */ +struct freq_desc { + u8 x86_family; /* CPU family */ + u8 x86_model; /* model */ + /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */ + u8 msr_plat; + u32 freqs[MAX_NUM_FREQS]; +}; + +static struct freq_desc freq_desc_tables[] = { + /* PNW */ + { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } }, + /* CLV+ */ + { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } }, + /* TNG */ + { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } }, + /* VLV2 */ + { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } }, + /* Ivybridge */ + { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } }, + /* ANN */ + { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } }, +}; + +static int match_cpu(u8 family, u8 model) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) { + if ((family == freq_desc_tables[i].x86_family) && + (model == freq_desc_tables[i].x86_model)) + return i; + } + + return -1; +} + +/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */ +#define id_to_freq(cpu_index, freq_id) \ + (freq_desc_tables[cpu_index].freqs[freq_id]) + +/* + * Do MSR calibration only for known/supported CPUs. + * + * Returns the calibration value or 0 if MSR calibration failed. + */ +static unsigned long try_msr_calibrate_tsc(void) +{ + u32 lo, hi, ratio, freq_id, freq; + unsigned long res; + int cpu_index; + + cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model); + if (cpu_index < 0) + return 0; + + if (freq_desc_tables[cpu_index].msr_plat) { + rdmsr(MSR_PLATFORM_INFO, lo, hi); + ratio = (lo >> 8) & 0x1f; + } else { + rdmsr(MSR_IA32_PERF_STATUS, lo, hi); + ratio = (hi >> 8) & 0x1f; + } + debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio); + + if (!ratio) + goto fail; + + if (freq_desc_tables[cpu_index].msr_plat == 2) { + /* TODO: Figure out how best to deal with this */ + freq = FREQ_100; + debug("Using frequency: %u KHz\n", freq); + } else { + /* Get FSB FREQ ID */ + rdmsr(MSR_FSB_FREQ, lo, hi); + freq_id = lo & 0x7; + freq = id_to_freq(cpu_index, freq_id); + debug("Resolved frequency ID: %u, frequency: %u KHz\n", + freq_id, freq); + } + if (!freq) + goto fail; + + /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ + res = freq * ratio / 1000; + debug("TSC runs at %lu MHz\n", res); + + return res; + +fail: + debug("Fast TSC calibration using MSR failed\n"); + return 0; +} + +/* + * This reads the current MSB of the PIT counter, and + * checks if we are running on sufficiently fast and + * non-virtualized hardware. + * + * Our expectations are: + * + * - the PIT is running at roughly 1.19MHz + * + * - each IO is going to take about 1us on real hardware, + * but we allow it to be much faster (by a factor of 10) or + * _slightly_ slower (ie we allow up to a 2us read+counter + * update - anything else implies a unacceptably slow CPU + * or PIT for the fast calibration to work. + * + * - with 256 PIT ticks to read the value, we have 214us to + * see the same MSB (and overhead like doing a single TSC + * read per MSB value etc). + * + * - We're doing 2 reads per loop (LSB, MSB), and we expect + * them each to take about a microsecond on real hardware. + * So we expect a count value of around 100. But we'll be + * generous, and accept anything over 50. + * + * - if the PIT is stuck, and we see *many* more reads, we + * return early (and the next caller of pit_expect_msb() + * then consider it a failure when they don't see the + * next expected value). + * + * These expectations mean that we know that we have seen the + * transition from one expected value to another with a fairly + * high accuracy, and we didn't miss any events. We can thus + * use the TSC value at the transitions to calculate a pretty + * good value for the TSC frequencty. + */ +static inline int pit_verify_msb(unsigned char val) +{ + /* Ignore LSB */ + inb(0x42); + return inb(0x42) == val; +} + +static inline int pit_expect_msb(unsigned char val, u64 *tscp, + unsigned long *deltap) +{ + int count; + u64 tsc = 0, prev_tsc = 0; + + for (count = 0; count < 50000; count++) { + if (!pit_verify_msb(val)) + break; + prev_tsc = tsc; + tsc = rdtsc(); + } + *deltap = rdtsc() - prev_tsc; + *tscp = tsc; + + /* + * We require _some_ success, but the quality control + * will be based on the error terms on the TSC values. + */ + return count > 5; +} + +/* + * How many MSB values do we want to see? We aim for + * a maximum error rate of 500ppm (in practice the + * real error is much smaller), but refuse to spend + * more than 50ms on it. + */ +#define MAX_QUICK_PIT_MS 50 +#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) + +static unsigned long quick_pit_calibrate(void) +{ + int i; + u64 tsc, delta; + unsigned long d1, d2; + + /* Set the Gate high, disable speaker */ + outb((inb(0x61) & ~0x02) | 0x01, 0x61); + + /* + * Counter 2, mode 0 (one-shot), binary count + * + * NOTE! Mode 2 decrements by two (and then the + * output is flipped each time, giving the same + * final output frequency as a decrement-by-one), + * so mode 0 is much better when looking at the + * individual counts. + */ + outb(0xb0, 0x43); + + /* Start at 0xffff */ + outb(0xff, 0x42); + outb(0xff, 0x42); + + /* + * The PIT starts counting at the next edge, so we + * need to delay for a microsecond. The easiest way + * to do that is to just read back the 16-bit counter + * once from the PIT. + */ + pit_verify_msb(0); + + if (pit_expect_msb(0xff, &tsc, &d1)) { + for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { + if (!pit_expect_msb(0xff-i, &delta, &d2)) + break; + + /* + * Iterate until the error is less than 500 ppm + */ + delta -= tsc; + if (d1+d2 >= delta >> 11) + continue; + + /* + * Check the PIT one more time to verify that + * all TSC reads were stable wrt the PIT. + * + * This also guarantees serialization of the + * last cycle read ('d2') in pit_expect_msb. + */ + if (!pit_verify_msb(0xfe - i)) + break; + goto success; + } + } + debug("Fast TSC calibration failed\n"); + return 0; + +success: + /* + * Ok, if we get here, then we've seen the + * MSB of the PIT decrement 'i' times, and the + * error has shrunk to less than 500 ppm. + * + * As a result, we can depend on there not being + * any odd delays anywhere, and the TSC reads are + * reliable (within the error). + * + * kHz = ticks / time-in-seconds / 1000; + * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 + * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) + */ + delta *= PIT_TICK_RATE; + delta /= (i*256*1000); + debug("Fast TSC calibration using PIT\n"); + return delta / 1000; +} + void timer_set_base(u64 base) { gd->arch.tsc_base = base; @@ -34,17 +298,24 @@ u64 __attribute__((no_instrument_function)) get_ticks(void) return now_tick - gd->arch.tsc_base; } -#define PLATFORM_INFO_MSR 0xce - /* Get the speed of the TSC timer in MHz */ unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void) { - u32 ratio; - u64 platform_info = native_read_msr(PLATFORM_INFO_MSR); + unsigned long fast_calibrate; + + if (gd->arch.tsc_mhz) + return gd->arch.tsc_mhz; + + fast_calibrate = try_msr_calibrate_tsc(); + if (!fast_calibrate) { + + fast_calibrate = quick_pit_calibrate(); + if (!fast_calibrate) + panic("TSC frequency is ZERO"); + } - /* 100MHz times Max Non Turbo ratio */ - ratio = (platform_info >> 8) & 0xff; - return 100 * ratio; + gd->arch.tsc_mhz = fast_calibrate; + return fast_calibrate; } unsigned long get_tbclk(void) diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c index b96ba81..ee1681b 100644 --- a/board/a3m071/a3m071.c +++ b/board/a3m071/a3m071.c @@ -392,9 +392,11 @@ int misc_init_r(void) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t * bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c index d3d4c18..c5d161b 100644 --- a/board/a4m072/a4m072.c +++ b/board/a4m072/a4m072.c @@ -171,10 +171,11 @@ void pci_init_board(void) #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/alphaproject/ap_sh4a_4a/Kconfig b/board/alphaproject/ap_sh4a_4a/Kconfig index 2352e66..4692851 100644 --- a/board/alphaproject/ap_sh4a_4a/Kconfig +++ b/board/alphaproject/ap_sh4a_4a/Kconfig @@ -1,8 +1,5 @@ if TARGET_AP_SH4A_4A -config SYS_CPU - default "sh4" - config SYS_BOARD default "ap_sh4a_4a" diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 79d4bab..c5cc4ff 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -490,9 +490,9 @@ int misc_init_r(void) #endif /* !defined(CONFIG_ARCHES) */ #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -extern void __ft_board_setup(void *blob, bd_t *bd); +extern int __ft_board_setup(void *blob, bd_t *bd); -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { __ft_board_setup(blob, bd); @@ -515,5 +515,7 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", "disabled", sizeof("disabled"), 1); } + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 53f9b34..91c6cbf 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -10,6 +10,7 @@ */ #include <common.h> +#include <errno.h> #include <libfdt.h> #include <fdt_support.h> #include <asm/ppc4xx.h> @@ -363,7 +364,7 @@ void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) * On NAND-booting sequoia, we need to patch the chips select numbers * in the dtb (CS0 - NAND, CS3 - NOR) */ -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int rc; int len; @@ -381,15 +382,14 @@ void ft_board_setup(void *blob, bd_t *bd) prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); if (prop == NULL) { printf("Unable to update NOR chip select for NAND booting\n"); - return; + return -FDT_ERR_NOTFOUND; } reg = (u32 *)&prop->data[0]; reg[0] = 3; rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); if (rc) { - printf("Unable to update property NOR mappings, err=%s\n", - fdt_strerror(rc)); - return; + printf("Unable to update property NOR mappings\n"); + return rc; } /* And now configure NAND chip select to 0 instead of 3 */ @@ -398,15 +398,16 @@ void ft_board_setup(void *blob, bd_t *bd) prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); if (prop == NULL) { printf("Unable to update NDFC chip select for NAND booting\n"); - return; + return len; } reg = (u32 *)&prop->data[0]; reg[0] = 0; rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); if (rc) { - printf("Unable to update property NDFC mappings, err=%s\n", - fdt_strerror(rc)); - return; + printf("Unable to update property NDFC mapping\n"); + return rc; } + + return 0; } #endif /* CONFIG_SYS_RAMBOOT */ diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 06922c0..67ac260 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -301,7 +301,7 @@ int board_eth_init(bd_t *bis) /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - ret = enable_fec_anatop_clock(ENET_50MHz); + ret = enable_fec_anatop_clock(ENET_50MHZ); if (ret) return ret; diff --git a/board/atmel/sama5d4_xplained/Kconfig b/board/atmel/sama5d4_xplained/Kconfig new file mode 100644 index 0000000..f6440c0 --- /dev/null +++ b/board/atmel/sama5d4_xplained/Kconfig @@ -0,0 +1,18 @@ +if TARGET_SAMA5D4_XPLAINED + +config SYS_CPU + default "armv7" + +config SYS_BOARD + default "sama5d4_xplained" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d4_xplained" + +endif diff --git a/board/atmel/sama5d4_xplained/MAINTAINERS b/board/atmel/sama5d4_xplained/MAINTAINERS new file mode 100644 index 0000000..035f64c --- /dev/null +++ b/board/atmel/sama5d4_xplained/MAINTAINERS @@ -0,0 +1,8 @@ +SAMA5D4 XPLAINED ULTRA BOARD +M: Bo Shen <voice.shen@atmel.com> +S: Maintained +F: board/atmel/sama5d4_xplained/ +F: include/configs/sama5d4_xplained.h +F: configs/sama5d4_xplained_mmc_defconfig +F: configs/sama5d4_xplained_nandflash_defconfig +F: configs/sama5d4_xplained_spiflash_defconfig diff --git a/board/atmel/sama5d4_xplained/Makefile b/board/atmel/sama5d4_xplained/Makefile new file mode 100644 index 0000000..c59b12d --- /dev/null +++ b/board/atmel/sama5d4_xplained/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2014 Atmel +# Bo Shen <voice.shen@atmel.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d4_xplained.o diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c new file mode 100644 index 0000000..de0baad --- /dev/null +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -0,0 +1,319 @@ +/* + * Copyright (C) 2014 Atmel + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <asm/arch/sama5d3_smc.h> +#include <asm/arch/sama5d4.h> +#include <atmel_lcdc.h> +#include <atmel_mci.h> +#include <lcd.h> +#include <mmc.h> +#include <net.h> +#include <netdev.h> +#include <nand.h> +#include <spi.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_ATMEL_SPI +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + at91_set_pio_output(AT91_PIO_PORTC, 3, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); +} + +static void sama5d4_xplained_spi0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ + + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_SPI0); +} +#endif /* CONFIG_ATMEL_SPI */ + +#ifdef CONFIG_NAND_ATMEL +static void sama5d4_xplained_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS3 for NAND */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | + AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | + AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ + at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ + at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ +} +#endif + +#ifdef CONFIG_CMD_USB +static void sama5d4_xplained_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTE, 11, 1); + at91_set_pio_output(AT91_PIO_PORTE, 14, 1); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 480, + .vl_row = 272, + .vl_clk = 9000, + .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL, + .vl_bpix = LCD_BPP, + .vl_bpox = LCD_OUTPUT_BPP, + .vl_tft = 1, + .vl_hsync_len = 41, + .vl_left_margin = 2, + .vl_right_margin = 2, + .vl_vsync_len = 11, + .vl_upper_margin = 2, + .vl_lower_margin = 2, + .mmio = ATMEL_BASE_LCDC, +}; + +/* No power up/down pin for the LCD pannel */ +void lcd_enable(void) { /* Empty! */ } +void lcd_disable(void) { /* Empty! */ } + +unsigned int has_lcdc(void) +{ + return 1; +} + +static void sama5d4_xplained_lcd_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ + at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ + at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ + + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + + at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + + at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ + at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ + at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ + at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_LCDC); +} + +#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf("2014 ATMEL Corp\n"); + lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + + nand_size = 0; +#ifdef CONFIG_NAND_ATMEL + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; +#endif + lcd_printf("%ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, nand_size >> 20); +} +#endif /* CONFIG_LCD_INFO */ + +#endif /* CONFIG_LCD */ + +#ifdef CONFIG_GENERIC_ATMEL_MCI +void sama5d4_xplained_mci1_hw_init(void) +{ + at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ + at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ + at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ + at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ + at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ + at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ + + /* + * As the mci io internal pull down is too strong, so if the io needs + * external pull up, the pull up resistor will be very small, if so + * the power consumption will increase, so disable the interanl pull + * down to save the power. + */ + at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_MCI1); +} + +int board_mmc_init(bd_t *bis) +{ + return atmel_mci_init((void *)ATMEL_BASE_MCI1); +} +#endif /* CONFIG_GENERIC_ATMEL_MCI */ + +#ifdef CONFIG_MACB +void sama5d4_xplained_macb0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_GMAC0); +} +#endif + +static void sama5d4_xplained_serial3_hw_init(void) +{ + at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART3); +} + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + at91_periph_clk_enable(ATMEL_ID_PIOE); + + sama5d4_xplained_serial3_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_ATMEL_SPI + sama5d4_xplained_spi0_hw_init(); +#endif +#ifdef CONFIG_NAND_ATMEL + sama5d4_xplained_nand_hw_init(); +#endif +#ifdef CONFIG_GENERIC_ATMEL_MCI + sama5d4_xplained_mci1_hw_init(); +#endif +#ifdef CONFIG_MACB + sama5d4_xplained_macb0_hw_init(); +#endif +#ifdef CONFIG_LCD + sama5d4_xplained_lcd_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + sama5d4_xplained_usb_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); +#endif + + return rc; +} diff --git a/board/atmel/sama5d4ek/Kconfig b/board/atmel/sama5d4ek/Kconfig new file mode 100644 index 0000000..a889895 --- /dev/null +++ b/board/atmel/sama5d4ek/Kconfig @@ -0,0 +1,18 @@ +if TARGET_SAMA5D4EK + +config SYS_CPU + default "armv7" + +config SYS_BOARD + default "sama5d4ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d4ek" + +endif diff --git a/board/atmel/sama5d4ek/MAINTAINERS b/board/atmel/sama5d4ek/MAINTAINERS new file mode 100644 index 0000000..afe88dd --- /dev/null +++ b/board/atmel/sama5d4ek/MAINTAINERS @@ -0,0 +1,8 @@ +SAMA5D4EK BOARD +M: Bo Shen <voice.shen@atmel.com> +S: Maintained +F: board/atmel/sama5d4ek/ +F: include/configs/sama5d4ek.h +F: configs/sama5d4ek_mmc_defconfig +F: configs/sama5d4ek_nandflash_defconfig +F: configs/sama5d4ek_spiflash_defconfig diff --git a/board/atmel/sama5d4ek/Makefile b/board/atmel/sama5d4ek/Makefile new file mode 100644 index 0000000..55823ba --- /dev/null +++ b/board/atmel/sama5d4ek/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2014 Atmel +# Bo Shen <voice.shen@atmel.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d4ek.o diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c new file mode 100644 index 0000000..f8394f5 --- /dev/null +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -0,0 +1,317 @@ +/* + * Copyright (C) 2014 Atmel + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <asm/arch/sama5d3_smc.h> +#include <asm/arch/sama5d4.h> +#include <atmel_lcdc.h> +#include <atmel_mci.h> +#include <lcd.h> +#include <mmc.h> +#include <net.h> +#include <netdev.h> +#include <nand.h> +#include <spi.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_ATMEL_SPI +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + at91_set_pio_output(AT91_PIO_PORTC, 3, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); +} + +static void sama5d4ek_spi0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ + + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_SPI0); +} +#endif /* CONFIG_ATMEL_SPI */ + +#ifdef CONFIG_NAND_ATMEL +static void sama5d4ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS3 for NAND */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | + AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | + AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ + at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ + at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ +} +#endif + +#ifdef CONFIG_CMD_USB +static void sama5d4ek_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTE, 11, 0); + at91_set_pio_output(AT91_PIO_PORTE, 12, 0); + at91_set_pio_output(AT91_PIO_PORTE, 10, 0); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 800, + .vl_row = 480, + .vl_clk = 33260000, + .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL, + .vl_bpix = LCD_BPP, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 128, + .vl_right_margin = 0, + .vl_vsync_len = 5, + .vl_upper_margin = 23, + .vl_lower_margin = 22, + .mmio = ATMEL_BASE_LCDC, +}; + +/* No power up/down pin for the LCD pannel */ +void lcd_enable(void) { /* Empty! */ } +void lcd_disable(void) { /* Empty! */ } + +unsigned int has_lcdc(void) +{ + return 1; +} + +static void sama5d4ek_lcd_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ + at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ + at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ + + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + + at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + + at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ + at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_LCDC); +} + +#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf("2014 ATMEL Corp\n"); + lcd_printf("at91@atmel.com\n"); + lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + + nand_size = 0; +#ifdef CONFIG_NAND_ATMEL + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; +#endif + lcd_printf("%ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, nand_size >> 20); +} +#endif /* CONFIG_LCD_INFO */ + +#endif /* CONFIG_LCD */ + +#ifdef CONFIG_GENERIC_ATMEL_MCI +void sama5d4ek_mci1_hw_init(void) +{ + at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ + at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ + at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ + at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ + at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ + at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ + + /* + * As the mci io internal pull down is too strong, so if the io needs + * external pull up, the pull up resistor will be very small, if so + * the power consumption will increase, so disable the interanl pull + * down to save the power. + */ + at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_MCI1); +} + +int board_mmc_init(bd_t *bis) +{ + /* Enable power for MCI1 interface */ + at91_set_pio_output(AT91_PIO_PORTE, 15, 0); + + return atmel_mci_init((void *)ATMEL_BASE_MCI1); +} +#endif /* CONFIG_GENERIC_ATMEL_MCI */ + +#ifdef CONFIG_MACB +void sama5d4ek_macb0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_GMAC0); +} +#endif + +static void sama5d4ek_serial3_hw_init(void) +{ + at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART3); +} + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + at91_periph_clk_enable(ATMEL_ID_PIOE); + + sama5d4ek_serial3_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_ATMEL_SPI + sama5d4ek_spi0_hw_init(); +#endif +#ifdef CONFIG_NAND_ATMEL + sama5d4ek_nand_hw_init(); +#endif +#ifdef CONFIG_GENERIC_ATMEL_MCI + sama5d4ek_mci1_hw_init(); +#endif +#ifdef CONFIG_MACB + sama5d4ek_macb0_hw_init(); +#endif +#ifdef CONFIG_LCD + sama5d4ek_lcd_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + sama5d4ek_usb_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); +#endif + + return rc; +} diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index 2ed8cf7..93f3d65 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -159,8 +159,8 @@ int board_mmc_getcd(struct mmc *mmc) gpio_direction_input(IMX_GPIO_NR(4, 5)); ret = gpio_get_value(IMX_GPIO_NR(4, 5)); } else { - gpio_direction_input(IMX_GPIO_NR(1, 4)); - ret = !gpio_get_value(IMX_GPIO_NR(1, 4)); + gpio_direction_input(IMX_GPIO_NR(1, 5)); + ret = !gpio_get_value(IMX_GPIO_NR(1, 5)); } return ret; @@ -173,7 +173,7 @@ struct fsl_esdhc_cfg usdhc_cfg[2] = { int board_mmc_init(bd_t *bis) { - s32 status = 0; + int ret; u32 index = 0; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); @@ -196,13 +196,15 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) diff --git a/board/bluewater/snapper9260/MAINTAINERS b/board/bluewater/snapper9260/MAINTAINERS index ff1e997..1f8f4d6 100644 --- a/board/bluewater/snapper9260/MAINTAINERS +++ b/board/bluewater/snapper9260/MAINTAINERS @@ -1,5 +1,5 @@ SNAPPER9260 BOARD -M: Ryan Mallon <ryan@bluewatersys.com> +M: Simon Glass <sjg@chromium.org> S: Maintained F: board/bluewater/snapper9260/ F: include/configs/snapper9260.h diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c index bfde129..95633b0 100644 --- a/board/bluewater/snapper9260/snapper9260.c +++ b/board/bluewater/snapper9260/snapper9260.c @@ -9,12 +9,15 @@ */ #include <common.h> +#include <dm.h> #include <asm/io.h> +#include <asm/gpio.h> #include <asm/arch/at91sam9260_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> +#include <asm/arch/atmel_serial.h> #include <net.h> #include <netdev.h> #include <i2c.h> @@ -95,10 +98,12 @@ static void nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy"); + gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce"); + gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } int board_init(void) @@ -140,3 +145,12 @@ int dram_init(void) void reset_phy(void) { } + +static struct atmel_serial_platdata at91sam9260_serial_plat = { + .base_addr = ATMEL_BASE_DBGU, +}; + +U_BOOT_DEVICE(at91sam9260_serial) = { + .name = "serial_atmel", + .platdata = &at91sam9260_serial_plat, +}; diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index fcd4d82..e8ea256 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -302,7 +302,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - s32 status = 0; + int ret; u32 index = 0; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); @@ -325,13 +325,15 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #endif diff --git a/board/broadcom/bcm11130/MAINTAINERS b/board/broadcom/bcm11130/MAINTAINERS new file mode 100644 index 0000000..b22e86f --- /dev/null +++ b/board/broadcom/bcm11130/MAINTAINERS @@ -0,0 +1,6 @@ +BCM11130 BOARD +M: Steve Rae <srae@broadcom.com> +S: Maintained +F: board/broadcom/bcm28155_ap/ +F: include/configs/bcm_ep_board.h +F: configs/bcm11130_defconfig diff --git a/board/broadcom/bcm11130_nand/MAINTAINERS b/board/broadcom/bcm11130_nand/MAINTAINERS new file mode 100644 index 0000000..881db5b --- /dev/null +++ b/board/broadcom/bcm11130_nand/MAINTAINERS @@ -0,0 +1,6 @@ +BCM11130_NAND BOARD +M: Steve Rae <srae@broadcom.com> +S: Maintained +F: board/broadcom/bcm28155_ap/ +F: include/configs/bcm_ep_board.h +F: configs/bcm11130_nand_defconfig diff --git a/board/broadcom/bcm911360_entphn-ns/MAINTAINERS b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS new file mode 100644 index 0000000..b5f0207 --- /dev/null +++ b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS @@ -0,0 +1,6 @@ +BCM911360_ENTPHN-NS BOARD +M: Steve Rae <srae@broadcom.com> +S: Maintained +F: board/broadcom/bcmcygnus/ +F: include/configs/bcm_ep_board.h +F: configs/bcm911360_entphn-ns_defconfig diff --git a/board/broadcom/bcm911360_entphn/MAINTAINERS b/board/broadcom/bcm911360_entphn/MAINTAINERS new file mode 100644 index 0000000..fb7ee2b --- /dev/null +++ b/board/broadcom/bcm911360_entphn/MAINTAINERS @@ -0,0 +1,6 @@ +BCM911360_ENTPHN BOARD +M: Steve Rae <srae@broadcom.com> +S: Maintained +F: board/broadcom/bcmcygnus/ +F: include/configs/bcm_ep_board.h +F: configs/bcm911360_entphn_defconfig diff --git a/board/broadcom/bcm911360k/MAINTAINERS b/board/broadcom/bcm911360k/MAINTAINERS new file mode 100644 index 0000000..754a15f --- /dev/null +++ b/board/broadcom/bcm911360k/MAINTAINERS @@ -0,0 +1,6 @@ +BCM911360K BOARD +M: Steve Rae <srae@broadcom.com> +S: Maintained +F: board/broadcom/bcmcygnus/ +F: include/configs/bcm_ep_board.h +F: configs/bcm911360k_defconfig diff --git a/board/broadcom/bcm958300k-ns/MAINTAINERS b/board/broadcom/bcm958300k-ns/MAINTAINERS new file mode 100644 index 0000000..763401a --- /dev/null +++ b/board/broadcom/bcm958300k-ns/MAINTAINERS @@ -0,0 +1,6 @@ +BCM958300K-NS BOARD +M: Steve Rae <srae@broadcom.com> +S: Maintained +F: board/broadcom/bcmcygnus/ +F: include/configs/bcm_ep_board.h +F: configs/bcm958300k-ns_defconfig diff --git a/board/broadcom/bcm958300k/MAINTAINERS b/board/broadcom/bcm958300k/MAINTAINERS index f75ee6e..8afc728 100644 --- a/board/broadcom/bcm958300k/MAINTAINERS +++ b/board/broadcom/bcm958300k/MAINTAINERS @@ -1,6 +1,6 @@ -Broadcom: Cygnus +BCM958300K BOARD M: Steve Rae <srae@broadcom.com> S: Maintained -F: board/broadcom/bcm958300k/ +F: board/broadcom/bcmcygnus/ F: include/configs/bcm_ep_board.h F: configs/bcm958300k_defconfig diff --git a/board/broadcom/bcm958305k/MAINTAINERS b/board/broadcom/bcm958305k/MAINTAINERS new file mode 100644 index 0000000..179fd4e --- /dev/null +++ b/board/broadcom/bcm958305k/MAINTAINERS @@ -0,0 +1,6 @@ +BCM958305K BOARD +M: Steve Rae <srae@broadcom.com> +S: Maintained +F: board/broadcom/bcmcygnus/ +F: include/configs/bcm_ep_board.h +F: configs/bcm958305k_defconfig diff --git a/board/broadcom/bcm958622hr/MAINTAINERS b/board/broadcom/bcm958622hr/MAINTAINERS index c34272f..d08aded 100644 --- a/board/broadcom/bcm958622hr/MAINTAINERS +++ b/board/broadcom/bcm958622hr/MAINTAINERS @@ -1,6 +1,6 @@ -Broadcom: Northstar Plus +BCM958622HR BOARD M: Steve Rae <srae@broadcom.com> S: Maintained -F: board/broadcom/bcm958622hr/ +F: board/broadcom/bcmnsp/ F: include/configs/bcm_ep_board.h F: configs/bcm958622hr_defconfig diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c index e48cd3f..6a70a2e 100644 --- a/board/broadcom/bcm_ep/board.c +++ b/board/broadcom/bcm_ep/board.c @@ -53,3 +53,17 @@ int board_early_init_f(void) return status; } + +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ +} + +void smp_kick_all_cpus(void) +{ +} + +void smp_waitloop(unsigned previous_address) +{ +} +#endif diff --git a/board/broadcom/bcm958300k/Kconfig b/board/broadcom/bcmcygnus/Kconfig index 9289288..faba4cf 100644 --- a/board/broadcom/bcm958300k/Kconfig +++ b/board/broadcom/bcmcygnus/Kconfig @@ -1,4 +1,4 @@ -if TARGET_BCM958300K +if TARGET_BCMCYGNUS config SYS_BOARD default "bcm_ep" diff --git a/board/broadcom/bcm958622hr/Kconfig b/board/broadcom/bcmnsp/Kconfig index 861c559..a975082 100644 --- a/board/broadcom/bcm958622hr/Kconfig +++ b/board/broadcom/bcmnsp/Kconfig @@ -1,4 +1,4 @@ -if TARGET_BCM958622HR +if TARGET_BCMNSP config SYS_BOARD default "bcm_ep" diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c index 048aa6c..5276907 100644 --- a/board/cm5200/cm5200.c +++ b/board/cm5200/cm5200.c @@ -359,9 +359,11 @@ int last_stage_init(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); ft_blob_update(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c index 2b826df..9d4c41b 100644 --- a/board/comelit/dig297/dig297.c +++ b/board/comelit/dig297/dig297.c @@ -133,6 +133,11 @@ int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} #endif #ifdef CONFIG_CMD_NET diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 0206ae8..84e3643 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -98,9 +98,6 @@ int sata_initialize(void) /* Make sure this gpio has logical 0 value */ gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); udelay(100); - - cm_fx6_sata_power(0); - mdelay(250); cm_fx6_sata_power(1); for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) { @@ -125,6 +122,15 @@ int sata_initialize(void) return err; } + +int sata_stop(void) +{ + __sata_stop(); + cm_fx6_sata_power(0); + mdelay(250); + + return 0; +} #else static int cm_fx6_setup_issd(void) { return 0; } #endif @@ -452,7 +458,7 @@ int cm_fx6_setup_ecspi(void) { return 0; } #endif #ifdef CONFIG_OF_BOARD_SETUP -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { uint8_t enetaddr[6]; @@ -461,6 +467,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_find_and_setprop(blob, "/fec", "local-mac-address", enetaddr, 6, 1); } + + return 0; } #endif diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 886c723..43463d5 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -382,6 +382,13 @@ int board_mmc_init(bd_t *bis) } #endif +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + #ifdef CONFIG_SYS_I2C_OMAP34XX /* * Routine: reset_net_chip diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c index b1a067d..2c2530a 100644 --- a/board/compulab/cm_t54/cm_t54.c +++ b/board/compulab/cm_t54/cm_t54.c @@ -121,7 +121,7 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_USB_HOST_ETHER -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { uint8_t enetaddr[6]; @@ -130,6 +130,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_find_and_setprop(blob, "/smsc95xx@0", "mac-address", enetaddr, 6, 1); } + + return 0; } static void generate_mac_addr(uint8_t *enetaddr) diff --git a/board/chromebook-x86/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig index 83385c7..6ca6ced 100644 --- a/board/chromebook-x86/coreboot/Kconfig +++ b/board/coreboot/coreboot/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "coreboot" config SYS_VENDOR - default "chromebook-x86" + default "coreboot" config SYS_SOC default "coreboot" diff --git a/board/chromebook-x86/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS index 3b2fb52..6ce66f5 100644 --- a/board/chromebook-x86/coreboot/MAINTAINERS +++ b/board/coreboot/coreboot/MAINTAINERS @@ -1,6 +1,6 @@ COREBOOT BOARD M: Simon Glass <sjg@chromium.org> S: Maintained -F: board/chromebook-x86/coreboot/ +F: board/coreboot/coreboot/ F: include/configs/coreboot.h F: configs/coreboot-x86_defconfig diff --git a/board/chromebook-x86/coreboot/Makefile b/board/coreboot/coreboot/Makefile index 27ebe78..27ebe78 100644 --- a/board/chromebook-x86/coreboot/Makefile +++ b/board/coreboot/coreboot/Makefile diff --git a/board/chromebook-x86/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index 0240c34..0240c34 100644 --- a/board/chromebook-x86/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c diff --git a/board/chromebook-x86/coreboot/coreboot_start.S b/board/coreboot/coreboot/coreboot_start.S index 932fe6c..932fe6c 100644 --- a/board/chromebook-x86/coreboot/coreboot_start.S +++ b/board/coreboot/coreboot/coreboot_start.S diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index 9e81bf3..0fddf45 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -147,6 +147,13 @@ int board_mmc_init(bd_t *bis) } #endif +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + /* * Routine: get_board_mem_timings * Description: If we use SPL then there is no x-loader nor config header diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c index c740669..a15a9ed 100644 --- a/board/davedenx/aria/aria.c +++ b/board/davedenx/aria/aria.c @@ -107,8 +107,10 @@ int checkboard (void) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds index 682f268..5c629db 100644 --- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds +++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds @@ -20,7 +20,7 @@ SECTIONS { *(.vectors) arch/arm/cpu/arm926ejs/start.o (.text*) - arch/arm/cpu/arm926ejs/davinci/built-in.o (.text*) + arch/arm/cpu/arm926ejs/built-in.o (.text*) drivers/mtd/nand/built-in.o (.text*) *(.text*) diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c index 02fb3fa..f8c7468 100644 --- a/board/embest/mx6boards/mx6boards.c +++ b/board/embest/mx6boards/mx6boards.c @@ -216,7 +216,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - s32 status = 0; + int ret; int i; /* @@ -268,13 +268,15 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; } - return status; + return 0; } #endif diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index b168074..f3f70ff 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -12,6 +12,7 @@ #include <image.h> #include <asm/byteorder.h> #include <fat.h> +#include <flash.h> #include <part.h> #include "auto_update.h" @@ -30,14 +31,8 @@ extern int N_AU_IMAGES; #define MAX_LOADSZ 0x1c00000 /* externals */ -extern int fat_register_device(block_dev_desc_t *, int); -extern int file_fat_detectfs(void); -extern long file_fat_read(const char *, void *, unsigned long); long do_fat_read (const char *filename, void *buffer, unsigned long maxsize, int dols); -extern int flash_sect_erase(ulong, ulong); -extern int flash_sect_protect (int, ulong, ulong); -extern int flash_write (char *, ulong, ulong); extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE]; diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 63cd862..e23ec55 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -508,7 +508,7 @@ int pci_pre_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int rc; @@ -526,6 +526,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_strerror(rc)); } } + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c index 9700611..cda1d7b 100644 --- a/board/esd/mecp5123/mecp5123.c +++ b/board/esd/mecp5123/mecp5123.c @@ -199,8 +199,10 @@ int checkboard(void) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c index 4409ea6..3e17132 100644 --- a/board/esd/pmc405de/pmc405de.c +++ b/board/esd/pmc405de/pmc405de.c @@ -300,7 +300,7 @@ int pci_pre_init(struct pci_controller *hose) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int rc; @@ -318,6 +318,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_strerror(rc)); } } + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 062ae67..15c3151 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -882,7 +882,7 @@ int board_usb_cleanup(int index, enum usb_init_type init) #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */ #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int rc; @@ -899,5 +899,7 @@ void ft_board_setup(void *blob, bd_t *bd) printf("err=%s\n", fdt_strerror(rc)); } } + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index 01365dc..f8f1834 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -74,13 +74,15 @@ int board_eth_init(bd_t *bis) #endif #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif diff --git a/board/espt/Kconfig b/board/espt/Kconfig index 6c7cd24..0294926 100644 --- a/board/espt/Kconfig +++ b/board/espt/Kconfig @@ -1,8 +1,5 @@ if TARGET_ESPT -config SYS_CPU - default "sh4" - config SYS_BOARD default "espt" diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index 34d66d5..6a8fca6 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -19,6 +19,7 @@ #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> +#include <hwconfig.h> #include "../common/qixis.h" #include "../common/vsc3316_3308.h" @@ -333,6 +334,8 @@ int configure_vsc3316_3308(void) unsigned int num_vsc16_con, num_vsc08_con; u32 serdes1_prtcl, serdes2_prtcl; int ret; + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; serdes1_prtcl = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; @@ -385,15 +388,18 @@ int configure_vsc3316_3308(void) } break; + case 0x01: case 0x02: case 0x04: case 0x05: case 0x06: + case 0x07: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: + case 0x2F: case 0x30: case 0x32: case 0x33: @@ -487,6 +493,9 @@ int configure_vsc3316_3308(void) return -1; } + num_vsc08_con = NUM_CON_VSC3308; + /* Configure VSC3308 crossbar switch */ + ret = select_i2c_ch_pca(I2C_CH_VSC3308); switch (serdes2_prtcl) { #ifdef CONFIG_PPC_B4420 case 0x9d: @@ -494,14 +503,11 @@ int configure_vsc3316_3308(void) case 0x9E: case 0x9A: case 0x98: - case 0xb2: + case 0x48: case 0x49: case 0x4E: - case 0x8D: + case 0x79: case 0x7A: - num_vsc08_con = NUM_CON_VSC3308; - /* Configure VSC3308 crossbar switch */ - ret = select_i2c_ch_pca(I2C_CH_VSC3308); if (!ret) { ret = vsc3308_config(VSC3308_TX_ADDRESS, vsc08_tx_amc, num_vsc08_con); @@ -515,6 +521,71 @@ int configure_vsc3316_3308(void) return ret; } break; + case 0x80: + case 0x81: + case 0x82: + case 0x83: + case 0x84: + case 0x85: + case 0x86: + case 0x87: + case 0x88: + case 0x89: + case 0x8a: + case 0x8b: + case 0x8c: + case 0x8d: + case 0x8e: + case 0xb1: + case 0xb2: + if (!ret) { + /* + * Extract hwconfig from environment since environment + * is not setup properly yet + */ + getenv_f("hwconfig", buffer, sizeof(buffer)); + buf = buffer; + + if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2", + "sfp_amc", "sfp", buf)) { +#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR + /* change default VSC3308 for XFI erratum */ + ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS, + vsc08_tx_sfp, num_vsc08_con); + if (ret) + return ret; + + ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS, + vsc08_rx_sfp, num_vsc08_con); + if (ret) + return ret; +#else + ret = vsc3308_config(VSC3308_TX_ADDRESS, + vsc08_tx_sfp, num_vsc08_con); + if (ret) + return ret; + + ret = vsc3308_config(VSC3308_RX_ADDRESS, + vsc08_rx_sfp, num_vsc08_con); + if (ret) + return ret; +#endif + } else { + ret = vsc3308_config(VSC3308_TX_ADDRESS, + vsc08_tx_amc, num_vsc08_con); + if (ret) + return ret; + + ret = vsc3308_config(VSC3308_RX_ADDRESS, + vsc08_rx_amc, num_vsc08_con); + if (ret) + return ret; + } + + } else { + return ret; + } + break; default: printf("WARNING:VSC crossbars programming not supported for: %x" " SerDes2 Protocol.\n", serdes2_prtcl); @@ -730,19 +801,23 @@ int config_serdes1_refclks(void) * to 122.88MHz */ switch (serdes1_prtcl) { + case 0x29: case 0x2A: case 0x2C: case 0x2D: case 0x2E: + case 0x01: case 0x02: case 0x04: case 0x05: case 0x06: + case 0x07: case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: + case 0x2F: case 0x30: case 0x32: case 0x33: @@ -860,6 +935,8 @@ int config_serdes2_refclks(void) #endif case 0x9E: case 0x9A: + /* fallthrough */ + case 0xb1: case 0xb2: debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n", serdes2_prtcl); @@ -915,6 +992,14 @@ int board_early_init_r(void) const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); int ret; + u32 svr = SVR_SOC_VER(get_svr()); + + /* Create law for MAPLE only for personalities having MAPLE */ + if ((svr == SVR_B4860) || (svr == SVR_B4440) || + (svr == SVR_B4420) || (svr == SVR_B4220)) { + set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, + LAW_TRGT_IF_MAPLE); + } /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -1110,7 +1195,7 @@ int misc_init_r(void) return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -1136,6 +1221,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); fdt_fixup_board_enet(blob); #endif + + return 0; } /* diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index 12df9a8..501d4b3 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -112,7 +112,10 @@ static void initialize_lane_to_slot(void) * Lanes: A,B,C,D: PCI * Lanes: E,F,G,H: XAUI2 */ + case 0xb1: case 0xb2: + case 0x8c: + case 0x8d: /* * Configuration: * SERDES: 2 @@ -195,34 +198,34 @@ int board_eth_init(bd_t *bis) * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and * 6 to on board SGMII phys */ - fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); switch (serdes1_prtcl) { case 0x29: case 0x2a: /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */ - debug("Setting phy addresses for FM1_DTSEC5: %x and" - "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n", + CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR, + CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); fm_info_set_phy_address(FM1_DTSEC5, - CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC6, - CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); break; #ifdef CONFIG_PPC_B4420 case 0x17: case 0x18: /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ - debug("Setting phy addresses for FM1_DTSEC3: %x and" - "FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n", + CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR, + CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); /* Fixing Serdes clock by programming FPGA register */ QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC4, - CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); break; #endif default: @@ -233,8 +236,8 @@ int board_eth_init(bd_t *bis) switch (serdes2_prtcl) { case 0x17: case 0x18: - debug("Setting phy addresses on SGMII Riser card for" - "FM1_DTSEC ports: \n"); + debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n", + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, @@ -246,8 +249,8 @@ int board_eth_init(bd_t *bis) break; case 0x48: case 0x49: - debug("Setting phy addresses on SGMII Riser card for" - "FM1_DTSEC ports: \n"); + debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n", + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, @@ -255,29 +258,37 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); break; - case 0x8d: + case 0xb1: case 0xb2: - debug("Setting phy addresses on SGMII Riser card for" - "FM1_DTSEC ports: \n"); + case 0x8c: + case 0x8d: + debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n", + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); + /* + * XFI does not need a PHY to work, but to make U-boot + * happy, assign a fake PHY address for a XFI port. + */ + fm_info_set_phy_address(FM1_10GEC1, 0); + fm_info_set_phy_address(FM1_10GEC2, 1); break; case 0x98: /* XAUI in Slot1 and Slot2 */ - debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n", + debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n", CONFIG_SYS_FM1_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); - debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n", + debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n", CONFIG_SYS_FM1_10GEC2_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, CONFIG_SYS_FM1_10GEC2_PHY_ADDR); break; case 0x9E: /* XAUI in Slot2 */ - debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n", + debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n", CONFIG_SYS_FM1_10GEC2_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, CONFIG_SYS_FM1_10GEC2_PHY_ADDR); @@ -329,17 +340,20 @@ int board_eth_init(bd_t *bis) switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: fm_info_set_mdio(i, - miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); + miiphy_get_dev_by_name + (DEFAULT_FM_TGEC_MDIO_NAME)); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); break; default: - printf("Fman1: 10GSEC%u set to unknown interface %i\n", + printf("Fman1: TGEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } - cpu_eth_init(bis); #endif @@ -351,21 +365,82 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, { int phy; char alias[32]; + struct fixed_link f_link; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + + prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { phy = fm_info_get_phy_address(port); sprintf(alias, "phy_sgmii_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, alias); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { + /* check if it's XFI interface for 10g */ + switch (prtcl2) { + case 0x80: + case 0x81: + case 0x82: + case 0x83: + case 0x84: + case 0x85: + case 0x86: + case 0x87: + case 0x88: + case 0x89: + case 0x8a: + case 0x8b: + case 0x8c: + case 0x8d: + case 0x8e: + case 0xb1: + case 0xb2: + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, + sizeof(f_link)); + break; + case 0x98: /* XAUI interface */ + sprintf(alias, "phy_xaui_slot1"); + fdt_status_okay_by_alias(fdt, alias); + + sprintf(alias, "phy_xaui_slot2"); + fdt_status_okay_by_alias(fdt, alias); + break; + case 0x9e: /* XAUI interface */ + case 0x9a: + case 0x93: + case 0x91: + sprintf(alias, "phy_xaui_slot1"); + fdt_status_okay_by_alias(fdt, alias); + break; + case 0x97: /* XAUI interface */ + case 0xc3: + sprintf(alias, "phy_xaui_slot2"); + fdt_status_okay_by_alias(fdt, alias); + break; + default: + break; + } } } +/* + * Set status to disabled for unused ethernet node + */ void fdt_fixup_board_enet(void *fdt) { int i; char alias[32]; - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_NONE: sprintf(alias, "ethernet%u", i); diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c index 5b327cc..047c3cb 100644 --- a/board/freescale/b4860qds/law.c +++ b/board/freescale/b4860qds/law.c @@ -17,9 +17,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_MAPLE_MEM_PHYS - SET_LAW(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_MAPLE), -#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c index 7fe4ae7..75e1142 100644 --- a/board/freescale/bsc9131rdb/bsc9131rdb.c +++ b/board/freescale/bsc9131rdb/bsc9131rdb.c @@ -15,6 +15,9 @@ #include <fdt_support.h> #include <fsl_mdio.h> #include <tsec.h> +#include <jffs2/load_kernel.h> +#include <mtd_node.h> +#include <flash.h> #include <netdev.h> @@ -50,7 +53,12 @@ int checkboard(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +struct node_info nodes[] = { + { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, +}; +#endif +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -61,7 +69,12 @@ void ft_board_setup(void *blob, bd_t *bd) size = getenv_bootm_size(); fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif fdt_fixup_dr_usb(blob, bd); + + return 0; } #endif diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index 10580bc..36a68db 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -21,6 +21,9 @@ #include <hwconfig.h> #include <i2c.h> #include <fsl_ddr_sdram.h> +#include <jffs2/load_kernel.h> +#include <mtd_node.h> +#include <flash.h> #ifdef CONFIG_PCI #include <pci.h> @@ -354,7 +357,13 @@ void fdt_del_node_compat(void *blob, const char *compatible) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +struct node_info nodes[] = { + { "cfi-flash", MTD_DEV_TYPE_NOR, }, + { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, +}; +#endif +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -369,6 +378,9 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 porbmsr = in_be32(&gur->porbmsr); @@ -411,5 +423,7 @@ void ft_board_setup(void *blob, bd_t *bd) printf("\nRemove sim from hwconfig and reset\n"); } } + + return 0; } #endif diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c index 534c6d1..d7577096 100644 --- a/board/freescale/c29xpcie/c29xpcie.c +++ b/board/freescale/c29xpcie/c29xpcie.c @@ -128,7 +128,7 @@ void fdt_del_sec(void *blob, int offset) } } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -150,5 +150,7 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_del_sec(blob, 1); else if (cpu->soc_ver == SVR_C292) fdt_del_sec(blob, 2); + + return 0; } #endif diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 32b5a3b..14af660 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_FMAN_ENET) += fman.o obj-$(CONFIG_FSL_PIXIS) += pixis.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o +obj-$(CONFIG_VID) += vid.o endif obj-$(CONFIG_FSL_QIXIS) += qixis.o obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o @@ -36,6 +37,12 @@ endif obj-$(CONFIG_FSL_DIU_CH7301) += diu_ch7301.o +ifdef CONFIG_ARM +obj-$(CONFIG_DEEP_SLEEP) += arm_sleep.o +else +obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o +endif + obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o @@ -53,6 +60,9 @@ obj-$(CONFIG_P5040DS) += ics307_clk.o obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o obj-$(CONFIG_ZM7300) += zm7300.o +obj-$(CONFIG_POWER_PFUZE100) += pfuze.o + +obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o # deal with common files for P-series corenet based devices obj-$(CONFIG_P2041RDB) += p_corenet/ @@ -60,4 +70,6 @@ obj-$(CONFIG_P3041DS) += p_corenet/ obj-$(CONFIG_P4080DS) += p_corenet/ obj-$(CONFIG_P5020DS) += p_corenet/ obj-$(CONFIG_P5040DS) += p_corenet/ + +obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o endif diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c new file mode 100644 index 0000000..8edf878 --- /dev/null +++ b/board/freescale/common/arm_sleep.c @@ -0,0 +1,95 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT) +#error " Deep sleep needs non-secure mode support. " +#else +#include <asm/secure.h> +#endif +#include <asm/armv7.h> +#include <asm/cache.h> + +#if defined(CONFIG_LS102XA) +#include <asm/arch/immap_ls102xa.h> +#endif + +#include "sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +void __weak board_mem_sleep_setup(void) +{ +} + +void __weak board_sleep_prepare(void) +{ +} + +bool is_warm_boot(void) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} + +void fsl_dp_disable_console(void) +{ + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +} + +/* + * When wakeup from deep sleep, the first 128 bytes space + * will be used to do DDR training which corrupts the data + * in there. This function will restore them. + */ +static void dp_ddr_restore(void) +{ + u64 *src, *dst; + int i; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + + /* get the address of ddr date from SPARECR3 */ + src = (u64 *)in_le32(&scfg->sparecr[2]); + dst = (u64 *)CONFIG_SYS_SDRAM_BASE; + + for (i = 0; i < DDR_BUFF_LEN / 8; i++) + *dst++ = *src++; + + flush_dcache_all(); +} + +static void dp_resume_prepare(void) +{ + dp_ddr_restore(); + board_sleep_prepare(); + armv7_init_nonsec(); + cleanup_before_linux(); +} + +int fsl_dp_resume(void) +{ + u32 start_addr; + void (*kernel_resume)(void); + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + + if (!is_warm_boot()) + return 0; + + dp_resume_prepare(); + + /* Get the entry address and jump to kernel */ + start_addr = in_le32(&scfg->sparecr[1]); + debug("Entry address is 0x%08x\n", start_addr); + kernel_resume = (void (*)(void))start_addr; + secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0); + + return 0; +} diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c index 2e5dcdf..571dfbb 100644 --- a/board/freescale/common/cds_pci_ft.c +++ b/board/freescale/common/cds_pci_ft.c @@ -63,13 +63,14 @@ static void cds_pci_fixup(void *blob) } } -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); cds_pci_fixup(blob); #endif + + return 0; } #endif diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c new file mode 100644 index 0000000..6154c9c --- /dev/null +++ b/board/freescale/common/ls102xa_stream_id.c @@ -0,0 +1,18 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ls102xa_stream_id.h> + +void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num) +{ + uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR; + int i; + + for (i = 0; i < num; i++) + out_be32(scfg + id[i].offset, id[i].stream_id); +} diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c new file mode 100644 index 0000000..f924e7f --- /dev/null +++ b/board/freescale/common/mpc85xx_sleep.c @@ -0,0 +1,88 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/immap_85xx.h> +#include "sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +void __weak board_mem_sleep_setup(void) +{ +} + +void __weak board_sleep_prepare(void) +{ +} + +bool is_warm_boot(void) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} + +void fsl_dp_disable_console(void) +{ + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +} + +/* + * When wakeup from deep sleep, the first 128 bytes space + * will be used to do DDR training which corrupts the data + * in there. This function will restore them. + */ +static void dp_ddr_restore(void) +{ + volatile u64 *src, *dst; + int i; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; + + /* get the address of ddr date from SPARECR3 */ + src = (u64 *)in_be32(&scfg->sparecr[2]); + dst = (u64 *)CONFIG_SYS_SDRAM_BASE; + + for (i = 0; i < DDR_BUFF_LEN / 8; i++) + *dst++ = *src++; + + flush_dcache(); +} + +static void dp_resume_prepare(void) +{ + dp_ddr_restore(); + + board_sleep_prepare(); + + l2cache_init(); +#if defined(CONFIG_RAMBOOT_PBL) + disable_cpc_sram(); +#endif + enable_cpc(); +} + +int fsl_dp_resume(void) +{ + u32 start_addr; + void (*kernel_resume)(void); + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; + + if (!is_warm_boot()) + return 0; + + dp_resume_prepare(); + + /* Get the entry address and jump to kernel */ + start_addr = in_be32(&scfg->sparecr[1]); + debug("Entry address is 0x%08x\n", start_addr); + kernel_resume = (void (*)(void))start_addr; + kernel_resume(); + + return 0; +} diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c new file mode 100644 index 0000000..d7de982 --- /dev/null +++ b/board/freescale/common/ns_access.c @@ -0,0 +1,30 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ns_access.h> + +void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) +{ + u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; + u32 *reg; + uint32_t val; + int i; + + for (i = 0; i < num; i++) { + reg = base + ns_dev[i].ind / 2; + val = in_be32(reg); + if (ns_dev[i].ind % 2 == 0) { + val &= 0x0000ffff; + val |= ns_dev[i].val << 16; + } else { + val &= 0xffff0000; + val |= ns_dev[i].val; + } + out_be32(reg, val); + } +} diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c new file mode 100644 index 0000000..2cd1794 --- /dev/null +++ b/board/freescale/common/pfuze.c @@ -0,0 +1,54 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> + +struct pmic *pfuze_common_init(unsigned char i2cbus) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(i2cbus); + if (ret) + return NULL; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return NULL; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set SW1AB stanby volage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PUZE_100_SW1ABCONF, ®); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(p, PUZE_100_SW1ABCONF, reg); + + /* Set SW1C standby voltage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); + + /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE100_SW1CCONF, ®); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(p, PFUZE100_SW1CCONF, reg); + + return p; +} diff --git a/board/freescale/common/pfuze.h b/board/freescale/common/pfuze.h new file mode 100644 index 0000000..7a4126c --- /dev/null +++ b/board/freescale/common/pfuze.h @@ -0,0 +1,12 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PFUZE_BOARD_HELPER__ +#define __PFUZE_BOARD_HELPER__ + +struct pmic *pfuze_common_init(unsigned char i2cbus); + +#endif diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index d8fed14..52d2021 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -100,8 +100,15 @@ u8 qixis_read_i2c(unsigned int reg); void qixis_write_i2c(unsigned int reg, u8 value); #endif +#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR) +#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg)) +#define QIXIS_WRITE(reg, value) \ + qixis_write_i2c(offsetof(struct qixis, reg), value) +#else #define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg)) #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) +#endif + #ifdef CONFIG_SYS_I2C_FPGA_ADDR #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg)) #define QIXIS_WRITE_I2C(reg, value) \ diff --git a/board/freescale/common/sleep.h b/board/freescale/common/sleep.h new file mode 100644 index 0000000..c26c542 --- /dev/null +++ b/board/freescale/common/sleep.h @@ -0,0 +1,21 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SLEEP_H +#define __SLEEP_H + +#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) +#define DDR_BUFF_LEN 128 + +/* determine if it is a wakeup from deep sleep */ +bool is_warm_boot(void); + +/* disable console output */ +void fsl_dp_disable_console(void); + +/* clean up everything and jump to kernel */ +int fsl_dp_resume(void); +#endif diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 6144c53..5cb7570 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -90,7 +90,7 @@ static void show_eeprom(void) /* EEPROM tag ID, either CCID or NXID */ #ifdef CONFIG_SYS_I2C_EEPROM_NXID printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], - be32_to_cpu(e.version)); + e.version); #else printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); #endif @@ -114,7 +114,7 @@ static void show_eeprom(void) e.date[3] & 0x80 ? "PM" : ""); /* Show MAC addresses */ - for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) { + for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) { u8 *p = e.mac[i]; @@ -223,7 +223,7 @@ static int prog_eeprom(void) */ for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - p, min((sizeof(e) - i), 8)); + p, min((int)(sizeof(e) - i), 8)); if (ret) break; udelay(5000); /* 5ms write cycle timing */ @@ -461,7 +461,7 @@ int mac_read_from_eeprom(void) memset(e.mac[8], 0xff, 6); #endif - for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) { + for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) { if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) && memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { char ethaddr[18]; @@ -485,7 +485,7 @@ int mac_read_from_eeprom(void) #ifdef CONFIG_SYS_I2C_EEPROM_NXID printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], - be32_to_cpu(e.version)); + e.version); #else printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); #endif diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c new file mode 100644 index 0000000..6b8af14 --- /dev/null +++ b/board/freescale/common/vid.c @@ -0,0 +1,491 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <asm/immap_85xx.h> +#include "vid.h" + +DECLARE_GLOBAL_DATA_PTR; + +int __weak i2c_multiplexer_select_vid_channel(u8 channel) +{ + return 0; +} + +/* + * Compensate for a board specific voltage drop between regulator and SoC + * return a value in mV + */ +int __weak board_vdd_drop_compensation(void) +{ + return 0; +} + +/* + * Get the i2c address configuration for the IR regulator chip + * + * There are some variance in the RDB HW regarding the I2C address configuration + * for the IR regulator chip, which is likely a problem of external resistor + * accuracy. So we just check each address in a hopefully non-intrusive mode + * and use the first one that seems to work + * + * The IR chip can show up under the following addresses: + * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA) + * 0x09 (Verified on T1040RDB-PA) + * 0x38 (Verified on T2080QDS, T2081QDS) + */ +static int find_ir_chip_on_i2c(void) +{ + int i2caddress; + int ret; + u8 byte; + int i; + const int ir_i2c_addr[] = {0x38, 0x08, 0x09}; + + /* Check all the address */ + for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) { + i2caddress = ir_i2c_addr[i]; + ret = i2c_read(i2caddress, + IR36021_MFR_ID_OFFSET, 1, (void *)&byte, + sizeof(byte)); + if ((ret >= 0) && (byte == IR36021_MFR_ID)) + return i2caddress; + } + return -1; +} + +/* Maximum loop count waiting for new voltage to take effect */ +#define MAX_LOOP_WAIT_NEW_VOL 100 +/* Maximum loop count waiting for the voltage to be stable */ +#define MAX_LOOP_WAIT_VOL_STABLE 100 +/* + * read_voltage from sensor on I2C bus + * We use average of 4 readings, waiting for WAIT_FOR_ADC before + * another reading + */ +#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ + +/* If an INA220 chip is available, we can use it to read back the voltage + * as it may have a higher accuracy than the IR chip for the same purpose + */ +#ifdef CONFIG_VOL_MONITOR_INA220 +#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ +#define ADC_MIN_ACCURACY 4 +#else +#define WAIT_FOR_ADC 138 /* wait for 138 microseconds for ADC */ +#define ADC_MIN_ACCURACY 4 +#endif + +#ifdef CONFIG_VOL_MONITOR_INA220 +static int read_voltage_from_INA220(int i2caddress) +{ + int i, ret, voltage_read = 0; + u16 vol_mon; + u8 buf[2]; + + for (i = 0; i < NUM_READINGS; i++) { + ret = i2c_read(I2C_VOL_MONITOR_ADDR, + I2C_VOL_MONITOR_BUS_V_OFFSET, 1, + (void *)&buf, 2); + if (ret) { + printf("VID: failed to read core voltage\n"); + return ret; + } + vol_mon = (buf[0] << 8) | buf[1]; + if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { + printf("VID: Core voltage sensor error\n"); + return -1; + } + debug("VID: bus voltage reads 0x%04x\n", vol_mon); + /* LSB = 4mv */ + voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; + udelay(WAIT_FOR_ADC); + } + /* calculate the average */ + voltage_read /= NUM_READINGS; + + return voltage_read; +} +#endif + +/* read voltage from IR */ +#ifdef CONFIG_VOL_MONITOR_IR36021_READ +static int read_voltage_from_IR(int i2caddress) +{ + int i, ret, voltage_read = 0; + u16 vol_mon; + u8 buf; + + for (i = 0; i < NUM_READINGS; i++) { + ret = i2c_read(i2caddress, + IR36021_LOOP1_VOUT_OFFSET, + 1, (void *)&buf, 1); + if (ret) { + printf("VID: failed to read vcpu\n"); + return ret; + } + vol_mon = buf; + if (!vol_mon) { + printf("VID: Core voltage sensor error\n"); + return -1; + } + debug("VID: bus voltage reads 0x%02x\n", vol_mon); + /* Resolution is 1/128V. We scale up here to get 1/128mV + * and divide at the end + */ + voltage_read += vol_mon * 1000; + udelay(WAIT_FOR_ADC); + } + /* Scale down to the real mV as IR resolution is 1/128V, rounding up */ + voltage_read = DIV_ROUND_UP(voltage_read, 128); + + /* calculate the average */ + voltage_read /= NUM_READINGS; + + /* Compensate for a board specific voltage drop between regulator and + * SoC before converting into an IR VID value + */ + voltage_read -= board_vdd_drop_compensation(); + + return voltage_read; +} +#endif + +static int read_voltage(int i2caddress) +{ + int voltage_read; +#ifdef CONFIG_VOL_MONITOR_INA220 + voltage_read = read_voltage_from_INA220(i2caddress); +#elif defined CONFIG_VOL_MONITOR_IR36021_READ + voltage_read = read_voltage_from_IR(i2caddress); +#else + return -1; +#endif + return voltage_read; +} + +/* + * We need to calculate how long before the voltage stops to drop + * or increase. It returns with the loop count. Each loop takes + * several readings (WAIT_FOR_ADC) + */ +static int wait_for_new_voltage(int vdd, int i2caddress) +{ + int timeout, vdd_current; + + vdd_current = read_voltage(i2caddress); + /* wait until voltage starts to reach the target. Voltage slew + * rates by typical regulators will always lead to stable readings + * within each fairly long ADC interval in comparison to the + * intended voltage delta change until the target voltage is + * reached. The fairly small voltage delta change to any target + * VID voltage also means that this function will always complete + * within few iterations. If the timeout was ever reached, it would + * point to a serious failure in the regulator system. + */ + for (timeout = 0; + abs(vdd - vdd_current) > (IR_VDD_STEP_UP + IR_VDD_STEP_DOWN) && + timeout < MAX_LOOP_WAIT_NEW_VOL; timeout++) { + vdd_current = read_voltage(i2caddress); + } + if (timeout >= MAX_LOOP_WAIT_NEW_VOL) { + printf("VID: Voltage adjustment timeout\n"); + return -1; + } + return timeout; +} + +/* + * this function keeps reading the voltage until it is stable or until the + * timeout expires + */ +static int wait_for_voltage_stable(int i2caddress) +{ + int timeout, vdd_current, vdd; + + vdd = read_voltage(i2caddress); + udelay(NUM_READINGS * WAIT_FOR_ADC); + + /* wait until voltage is stable */ + vdd_current = read_voltage(i2caddress); + /* The maximum timeout is + * MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC + */ + for (timeout = MAX_LOOP_WAIT_VOL_STABLE; + abs(vdd - vdd_current) > ADC_MIN_ACCURACY && + timeout > 0; timeout--) { + vdd = vdd_current; + udelay(NUM_READINGS * WAIT_FOR_ADC); + vdd_current = read_voltage(i2caddress); + } + if (timeout == 0) + return -1; + return vdd_current; +} + +#ifdef CONFIG_VOL_MONITOR_IR36021_SET +/* Set the voltage to the IR chip */ +static int set_voltage_to_IR(int i2caddress, int vdd) +{ + int wait, vdd_last; + int ret; + u8 vid; + + /* Compensate for a board specific voltage drop between regulator and + * SoC before converting into an IR VID value + */ + vdd += board_vdd_drop_compensation(); + vid = DIV_ROUND_UP(vdd - 245, 5); + + ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET, + 1, (void *)&vid, sizeof(vid)); + if (ret) { + printf("VID: failed to write VID\n"); + return -1; + } + wait = wait_for_new_voltage(vdd, i2caddress); + if (wait < 0) + return -1; + debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC); + + vdd_last = wait_for_voltage_stable(i2caddress); + if (vdd_last < 0) + return -1; + debug("VID: Current voltage is %d mV\n", vdd_last); + return vdd_last; +} +#endif + +static int set_voltage(int i2caddress, int vdd) +{ + int vdd_last = -1; + +#ifdef CONFIG_VOL_MONITOR_IR36021_SET + vdd_last = set_voltage_to_IR(i2caddress, vdd); +#else + #error Specific voltage monitor must be defined +#endif + return vdd_last; +} + +int adjust_vdd(ulong vdd_override) +{ + int re_enable = disable_interrupts(); + ccsr_gur_t __iomem *gur = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 fusesr; + u8 vid; + int vdd_target, vdd_current, vdd_last; + int ret, i2caddress; + unsigned long vdd_string_override; + char *vdd_string; + static const uint16_t vdd[32] = { + 0, /* unused */ + 9875, /* 0.9875V */ + 9750, + 9625, + 9500, + 9375, + 9250, + 9125, + 9000, + 8875, + 8750, + 8625, + 8500, + 8375, + 8250, + 8125, + 10000, /* 1.0000V */ + 10125, + 10250, + 10375, + 10500, + 10625, + 10750, + 10875, + 11000, + 0, /* reserved */ + }; + struct vdd_drive { + u8 vid; + unsigned voltage; + }; + + ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + debug("VID: I2C failed to switch channel\n"); + ret = -1; + goto exit; + } + ret = find_ir_chip_on_i2c(); + if (ret < 0) { + printf("VID: Could not find voltage regulator on I2C.\n"); + ret = -1; + goto exit; + } else { + i2caddress = ret; + debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); + } + + /* get the voltage ID from fuse status register */ + fusesr = in_be32(&gur->dcfg_fusesr); + /* + * VID is used according to the table below + * --------------------------------------- + * | DA_V | + * |-------------------------------------| + * | 5b00000 | 5b00001-5b11110 | 5b11111 | + * ---------------+---------+-----------------+---------| + * | D | 5b00000 | NO VID | VID = DA_V | NO VID | + * | A |----------+---------+-----------------+---------| + * | _ | 5b00001 |VID = | VID = |VID = | + * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT| + * | _ | 5b11110 | | | | + * | A |----------+---------+-----------------+---------| + * | L | 5b11111 | No VID | VID = DA_V | NO VID | + * | T | | | | | + * ------------------------------------------------------ + */ + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; + if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) { + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_VID_MASK; + } + vdd_target = vdd[vid]; + + /* check override variable for overriding VDD */ + vdd_string = getenv(CONFIG_VID_FLS_ENV); + if (vdd_override == 0 && vdd_string && + !strict_strtoul(vdd_string, 10, &vdd_string_override)) + vdd_override = vdd_string_override; + if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) { + vdd_target = vdd_override * 10; /* convert to 1/10 mV */ + debug("VDD override is %lu\n", vdd_override); + } else if (vdd_override != 0) { + printf("Invalid value.\n"); + } + if (vdd_target == 0) { + debug("VID: VID not used\n"); + ret = 0; + goto exit; + } else { + /* divide and round up by 10 to get a value in mV */ + vdd_target = DIV_ROUND_UP(vdd_target, 10); + debug("VID: vid = %d mV\n", vdd_target); + } + + /* + * Read voltage monitor to check real voltage. + */ + vdd_last = read_voltage(i2caddress); + if (vdd_last < 0) { + printf("VID: Couldn't read sensor abort VID adjustment\n"); + ret = -1; + goto exit; + } + vdd_current = vdd_last; + debug("VID: Core voltage is currently at %d mV\n", vdd_last); + /* + * Adjust voltage to at or one step above target. + * As measurements are less precise than setting the values + * we may run through dummy steps that cancel each other + * when stepping up and then down. + */ + while (vdd_last > 0 && + vdd_last < vdd_target) { + vdd_current += IR_VDD_STEP_UP; + vdd_last = set_voltage(i2caddress, vdd_current); + } + while (vdd_last > 0 && + vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) { + vdd_current -= IR_VDD_STEP_DOWN; + vdd_last = set_voltage(i2caddress, vdd_current); + } + + if (vdd_last > 0) + printf("VID: Core voltage after adjustment is at %d mV\n", + vdd_last); + else + ret = -1; +exit: + if (re_enable) + enable_interrupts(); + return ret; +} + +static int print_vdd(void) +{ + int vdd_last, ret, i2caddress; + + ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + debug("VID : I2c failed to switch channel\n"); + return -1; + } + ret = find_ir_chip_on_i2c(); + if (ret < 0) { + printf("VID: Could not find voltage regulator on I2C.\n"); + return -1; + } else { + i2caddress = ret; + debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); + } + + /* + * Read voltage monitor to check real voltage. + */ + vdd_last = read_voltage(i2caddress); + if (vdd_last < 0) { + printf("VID: Couldn't read sensor abort VID adjustment\n"); + return -1; + } + printf("VID: Core voltage is at %d mV\n", vdd_last); + + return 0; +} + +static int do_vdd_override(cmd_tbl_t *cmdtp, + int flag, int argc, + char * const argv[]) +{ + ulong override; + + if (argc < 2) + return CMD_RET_USAGE; + + if (!strict_strtoul(argv[1], 10, &override)) + adjust_vdd(override); /* the value is checked by callee */ + else + return CMD_RET_USAGE; + return 0; +} + +static int do_vdd_read(cmd_tbl_t *cmdtp, + int flag, int argc, + char * const argv[]) +{ + if (argc < 1) + return CMD_RET_USAGE; + print_vdd(); + + return 0; +} + +U_BOOT_CMD( + vdd_override, 2, 0, do_vdd_override, + "override VDD", + " - override with the voltage specified in mV, eg. 1050" +); + +U_BOOT_CMD( + vdd_read, 1, 0, do_vdd_read, + "read VDD", + " - Read the voltage specified in mV" +) diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h new file mode 100644 index 0000000..a9c7bb4 --- /dev/null +++ b/board/freescale/common/vid.h @@ -0,0 +1,20 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __VID_H_ +#define __VID_H_ + +#define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A +#define IR36021_LOOP1_VOUT_OFFSET 0x9A +#define IR36021_MFR_ID_OFFSET 0x92 +#define IR36021_MFR_ID 0x43 + +/* step the IR regulator in 5mV increments */ +#define IR_VDD_STEP_DOWN 5 +#define IR_VDD_STEP_UP 5 +int adjust_vdd(ulong vdd_override); + +#endif /* __VID_H_ */ diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c index 97a25e8..dd9c37e 100644 --- a/board/freescale/common/vsc3316_3308.c +++ b/board/freescale/common/vsc3316_3308.c @@ -13,7 +13,12 @@ #define INPUT_STATE_REG 0x13 #define GLOBAL_INPUT_ISE1 0x51 #define GLOBAL_INPUT_ISE2 0x52 +#define GLOBAL_INPUT_GAIN 0x53 #define GLOBAL_INPUT_LOS 0x55 +#define GLOBAL_OUTPUT_PE1 0x56 +#define GLOBAL_OUTPUT_PE2 0x57 +#define GLOBAL_OUTPUT_LEVEL 0x58 +#define GLOBAL_OUTPUT_TERMINATION 0x5A #define GLOBAL_CORE_CNTRL 0x5D #define OUTPUT_MODE_PAGE 0x23 #define CORE_CONTROL_PAGE 0x25 @@ -92,6 +97,109 @@ int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], return 0; } +#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR +int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2], + unsigned int num_con) +{ + unsigned int i; + u8 rev_id = 0; + int ret; + + debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n", + vsc_addr); + + ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Configure Global Input ISE */ + i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0); + i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0); + + /* Configure Tx/Rx Global Output PE1 */ + i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE1, 0); + + /* Configure Tx/Rx Global Output PE2 */ + i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE2, 0); + + /* Configure Tx/Rx Global Input GAIN */ + i2c_reg_write(vsc_addr, GLOBAL_INPUT_GAIN, 0x3F); + + /* Setting Global Input LOS threshold value */ + i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0xE0); + + /* Setting Global output termination */ + i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_TERMINATION, 0); + + /* Configure Tx/Rx Global Output level */ + if (vsc_addr == VSC3308_TX_ADDRESS) + i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 4); + else + i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 2); + + /* Making crosspoint connections, by connecting required + * input to output */ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); + + /* input state - page 0x13 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Turning off all the required input of the switch */ + for (i = 0; i < num_con; i++) + i2c_reg_write(vsc_addr, con_arr[i][0], 1); + + /* only turn on specific Tx/Rx requested by the XFI erratum */ + if (vsc_addr == VSC3308_TX_ADDRESS) { + i2c_reg_write(vsc_addr, 2, 0); + i2c_reg_write(vsc_addr, 3, 0); + } else { + i2c_reg_write(vsc_addr, 0, 0); + i2c_reg_write(vsc_addr, 1, 0); + } + + /* config output mode - page 0x23 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn off the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][1], 1); + + /* only turn on specific Tx/Rx requested by the XFI erratum */ + if (vsc_addr == VSC3308_TX_ADDRESS) { + i2c_reg_write(vsc_addr, 0, 0); + i2c_reg_write(vsc_addr, 1, 0); + } else { + i2c_reg_write(vsc_addr, 3, 0); + i2c_reg_write(vsc_addr, 4, 0); + } + + /* configure global core control register, Turn on Global core power */ + i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); + + vsc_wp_config(vsc_addr); + + return 0; +} +#endif + int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], unsigned int num_con) { diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h index 2a49187..d722ea3 100644 --- a/board/freescale/common/vsc3316_3308.h +++ b/board/freescale/common/vsc3316_3308.h @@ -14,6 +14,10 @@ int vsc_if_enable(unsigned int vsc_addr); int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], unsigned int num_con); +#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR +int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2], + unsigned int num_con); +#endif int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], unsigned int num_con); void vsc_wp_config(unsigned int vsc_addr); diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 65b3867..6f0fea1 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -190,7 +190,7 @@ int misc_init_r(void) return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -213,4 +213,6 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); fdt_fixup_board_enet(blob); #endif + + return 0; } diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index 35825c4..396103f 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -62,7 +62,7 @@ #ifdef CONFIG_FMAN_ENET -#define BRDCFG1_EMI1_SEL_MASK 0x70 +#define BRDCFG1_EMI1_SEL_MASK 0x78 #define BRDCFG1_EMI1_SEL_SLOT1 0x10 #define BRDCFG1_EMI1_SEL_SLOT2 0x20 #define BRDCFG1_EMI1_SEL_SLOT5 0x30 @@ -202,6 +202,8 @@ static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux) if (!path) path = alias; + do_fixup_by_path(fdt, path, "reg", + &mux, sizeof(mux), 1); do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval", &mux, sizeof(mux), 1); } @@ -250,11 +252,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, return; } - if (mux == BRDCFG1_EMI1_SEL_RGMII) { + if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) { /* RGMII */ /* The RGMII PHY is identified by the MAC connected to it */ sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1); fdt_set_phy_handle(fdt, compat, addr, phy); + return; } /* If it's not RGMII or XGMII, it must be SGMII */ diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS index e30e944..638833d 100644 --- a/board/freescale/ls1021aqds/MAINTAINERS +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -6,3 +6,6 @@ F: include/configs/ls1021aqds.h F: configs/ls1021aqds_nor_defconfig F: configs/ls1021aqds_ddr4_nor_defconfig F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig +F: configs/ls1021aqds_sdcard_defconfig +F: configs/ls1021aqds_qspi_defconfig +F: configs/ls1021aqds_nand_defconfig diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 5898e33..a539ff9 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -153,9 +153,12 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) puts("Initializing DDR....using SPD\n"); dram_size = fsl_ddr_sdram(); - +#else + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 5fafc85..f08e54f 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -8,19 +8,40 @@ #include <i2c.h> #include <asm/io.h> #include <asm/arch/immap_ls102xa.h> +#include <asm/arch/ns_access.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#include <asm/arch/ls102xa_stream_id.h> +#include <asm/pcie_layerscape.h> +#include <hwconfig.h> #include <mmc.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> #include <fsl_sec.h> +#include <spl.h> #include "../common/qixis.h" #include "ls1021aqds_qixis.h" +#ifdef CONFIG_U_QE +#include "../../../drivers/qe/qe.h" +#endif + +#define PIN_MUX_SEL_CAN 0x03 +#define PIN_MUX_SEL_IIC2 0xa0 +#define PIN_MUX_SEL_RGMII 0x00 +#define PIN_MUX_SEL_SAI 0x0c +#define PIN_MUX_SEL_SDHC 0x00 +#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) +#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) DECLARE_GLOBAL_DATA_PTR; enum { + MUX_TYPE_CAN, + MUX_TYPE_IIC2, + MUX_TYPE_RGMII, + MUX_TYPE_SAI, + MUX_TYPE_SDHC, MUX_TYPE_SD_PCI4, MUX_TYPE_SD_PC_SA_SG_SG, MUX_TYPE_SD_PC_SA_PC_SG, @@ -29,11 +50,20 @@ enum { int checkboard(void) { +#ifndef CONFIG_QSPI_BOOT char buf[64]; +#endif +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) u8 sw; +#endif puts("Board: LS1021AQDS\n"); +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#elif CONFIG_QSPI_BOOT + puts("QSPI\n"); +#else sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; @@ -47,13 +77,16 @@ int checkboard(void) printf("IFCCard\n"); else printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif +#ifndef CONFIG_QSPI_BOOT printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); printf("FPGA: v%d (%s), build %d\n", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); +#endif return 0; } @@ -98,8 +131,27 @@ unsigned long get_board_ddr_clk(void) return 66666666; } +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + int dram_init(void) { + /* + * When resuming from deep sleep, the I2C channel may not be + * in the default channel. So, switch to the default channel + * before accessing DDR SPD. + */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); gd->ram_size = initdram(0); return 0; @@ -118,34 +170,24 @@ int board_mmc_init(bd_t *bis) } #endif -int select_i2c_ch_pca9547(u8 ch) -{ - int ret; - - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; #ifdef CONFIG_TSEC_ENET - out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV); out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); - out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV); + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); #endif #ifdef CONFIG_FSL_IFC init_early_memctl_regs(); #endif +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + /* Workaround for the issue that DDR could not respond to * barrier transaction which is generated by executing DSB/ISB * instruction. Set CCI-400 control override register to @@ -156,13 +198,75 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + +#ifdef CONFIG_NAND_BOOT + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 porsr1, pinctl; + + /* + * There is LS1 SoC issue where NOR, FPGA are inaccessible during + * NAND boot because IFC signals > IFC_AD7 are not enabled. + * This workaround changes RCW source to make all signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | + DCFG_CCSR_PORSR1_RCW_SRC_I2C); + out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), + pinctl); +#endif + + /* Set global data pointer */ + gd = &gdata; + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + + get_clocks(); + + preloader_console_init(); + +#ifdef CONFIG_SPL_I2C_SUPPORT + i2c_init_all(); +#endif + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + + dram_init(); + + board_init_r(NULL, 0); +} +#endif + int config_board_mux(int ctrl_type) { - u8 reg12; + u8 reg12, reg14; reg12 = QIXIS_READ(brdcfg[12]); + reg14 = QIXIS_READ(brdcfg[14]); switch (ctrl_type) { + case MUX_TYPE_CAN: + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); + break; + case MUX_TYPE_IIC2: + reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); + break; + case MUX_TYPE_RGMII: + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); + break; + case MUX_TYPE_SAI: + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); + break; + case MUX_TYPE_SDHC: + reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); + break; case MUX_TYPE_SD_PCI4: reg12 = 0x38; break; @@ -181,6 +285,7 @@ int config_board_mux(int ctrl_type) } QIXIS_WRITE(brdcfg[12], reg12); + QIXIS_WRITE(brdcfg[14], reg14); return 0; } @@ -214,15 +319,154 @@ int config_serdes_mux(void) return 0; } -#if defined(CONFIG_MISC_INIT_R) int misc_init_r(void) { + int conflict_flag; + + /* some signals can not enable simultaneous*/ + conflict_flag = 0; + if (hwconfig("sdhc")) + conflict_flag++; + if (hwconfig("iic2")) + conflict_flag++; + if (conflict_flag > 1) { + printf("WARNING: pin conflict !\n"); + return 0; + } + + conflict_flag = 0; + if (hwconfig("rgmii")) + conflict_flag++; + if (hwconfig("can")) + conflict_flag++; + if (hwconfig("sai")) + conflict_flag++; + if (conflict_flag > 1) { + printf("WARNING: pin conflict !\n"); + return 0; + } + + if (hwconfig("can")) + config_board_mux(MUX_TYPE_CAN); + else if (hwconfig("rgmii")) + config_board_mux(MUX_TYPE_RGMII); + else if (hwconfig("sai")) + config_board_mux(MUX_TYPE_SAI); + + if (hwconfig("iic2")) + config_board_mux(MUX_TYPE_IIC2); + else if (hwconfig("sdhc")) + config_board_mux(MUX_TYPE_SDHC); + #ifdef CONFIG_FSL_CAAM return sec_init(); #endif + return 0; } + +#ifdef CONFIG_LS102XA_NS_ACCESS +static struct csu_ns_dev ns_dev[] = { + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, + { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, + { CSU_CSLX_OCRAM, CSU_ALL_RW }, + { CSU_CSLX_GIC, CSU_ALL_RW }, + { CSU_CSLX_PCIE1, CSU_ALL_RW }, + { CSU_CSLX_OCRAM2, CSU_ALL_RW }, + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, + { CSU_CSLX_PCIE2, CSU_ALL_RW }, + { CSU_CSLX_SATA, CSU_ALL_RW }, + { CSU_CSLX_USB3, CSU_ALL_RW }, + { CSU_CSLX_SERDES, CSU_ALL_RW }, + { CSU_CSLX_QDMA, CSU_ALL_RW }, + { CSU_CSLX_LPUART2, CSU_ALL_RW }, + { CSU_CSLX_LPUART1, CSU_ALL_RW }, + { CSU_CSLX_LPUART4, CSU_ALL_RW }, + { CSU_CSLX_LPUART3, CSU_ALL_RW }, + { CSU_CSLX_LPUART6, CSU_ALL_RW }, + { CSU_CSLX_LPUART5, CSU_ALL_RW }, + { CSU_CSLX_DSPI2, CSU_ALL_RW }, + { CSU_CSLX_DSPI1, CSU_ALL_RW }, + { CSU_CSLX_QSPI, CSU_ALL_RW }, + { CSU_CSLX_ESDHC, CSU_ALL_RW }, + { CSU_CSLX_2D_ACE, CSU_ALL_RW }, + { CSU_CSLX_IFC, CSU_ALL_RW }, + { CSU_CSLX_I2C1, CSU_ALL_RW }, + { CSU_CSLX_USB2, CSU_ALL_RW }, + { CSU_CSLX_I2C3, CSU_ALL_RW }, + { CSU_CSLX_I2C2, CSU_ALL_RW }, + { CSU_CSLX_DUART2, CSU_ALL_RW }, + { CSU_CSLX_DUART1, CSU_ALL_RW }, + { CSU_CSLX_WDT2, CSU_ALL_RW }, + { CSU_CSLX_WDT1, CSU_ALL_RW }, + { CSU_CSLX_EDMA, CSU_ALL_RW }, + { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, + { CSU_CSLX_DDR, CSU_ALL_RW }, + { CSU_CSLX_QUICC, CSU_ALL_RW }, + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, + { CSU_CSLX_SFP, CSU_ALL_RW }, + { CSU_CSLX_TMU, CSU_ALL_RW }, + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, + { CSU_CSLX_RESERVED0, CSU_ALL_RW }, + { CSU_CSLX_ETSEC1, CSU_ALL_RW }, + { CSU_CSLX_SEC5_5, CSU_ALL_RW }, + { CSU_CSLX_ETSEC3, CSU_ALL_RW }, + { CSU_CSLX_ETSEC2, CSU_ALL_RW }, + { CSU_CSLX_GPIO2, CSU_ALL_RW }, + { CSU_CSLX_GPIO1, CSU_ALL_RW }, + { CSU_CSLX_GPIO4, CSU_ALL_RW }, + { CSU_CSLX_GPIO3, CSU_ALL_RW }, + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, + { CSU_CSLX_CSU, CSU_ALL_RW }, + { CSU_CSLX_ASRC, CSU_ALL_RW }, + { CSU_CSLX_SPDIF, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, + { CSU_CSLX_SAI2, CSU_ALL_RW }, + { CSU_CSLX_SAI1, CSU_ALL_RW }, + { CSU_CSLX_SAI4, CSU_ALL_RW }, + { CSU_CSLX_SAI3, CSU_ALL_RW }, + { CSU_CSLX_FTM2, CSU_ALL_RW }, + { CSU_CSLX_FTM1, CSU_ALL_RW }, + { CSU_CSLX_FTM4, CSU_ALL_RW }, + { CSU_CSLX_FTM3, CSU_ALL_RW }, + { CSU_CSLX_FTM6, CSU_ALL_RW }, + { CSU_CSLX_FTM5, CSU_ALL_RW }, + { CSU_CSLX_FTM8, CSU_ALL_RW }, + { CSU_CSLX_FTM7, CSU_ALL_RW }, + { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, + { CSU_CSLX_EPU, CSU_ALL_RW }, + { CSU_CSLX_GDI, CSU_ALL_RW }, + { CSU_CSLX_DDI, CSU_ALL_RW }, + { CSU_CSLX_RESERVED1, CSU_ALL_RW }, + { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, + { CSU_CSLX_RESERVED2, CSU_ALL_RW }, +}; #endif +struct smmu_stream_id dev_stream_id[] = { + { 0x100, 0x01, "ETSEC MAC1" }, + { 0x104, 0x02, "ETSEC MAC2" }, + { 0x108, 0x03, "ETSEC MAC3" }, + { 0x10c, 0x04, "PEX1" }, + { 0x110, 0x05, "PEX2" }, + { 0x114, 0x06, "qDMA" }, + { 0x118, 0x07, "SATA" }, + { 0x11c, 0x08, "USB3" }, + { 0x120, 0x09, "QE" }, + { 0x124, 0x0a, "eSDHC" }, + { 0x128, 0x0b, "eMA" }, + { 0x14c, 0x0c, "2D-ACE" }, + { 0x150, 0x0d, "USB2" }, + { 0x18c, 0x0e, "DEBUG" }, +}; + int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -230,6 +474,13 @@ int board_init(void) /* Set CCI-400 control override register to * enable barrier transaction */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + /* + * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register + * All transactions are treated as non-shareable + */ + out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); @@ -237,12 +488,30 @@ int board_init(void) fsl_serdes_init(); config_serdes_mux(); #endif + + ls102xa_config_smmu_stream_id(dev_stream_id, + ARRAY_SIZE(dev_stream_id)); + +#ifdef CONFIG_LS102XA_NS_ACCESS + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#endif + +#ifdef CONFIG_U_QE + u_qe_init(); +#endif + return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCIE_LAYERSCAPE + ft_pcie_setup(blob, bd); +#endif + + return 0; } u8 flash_read8(void *addr) diff --git a/board/freescale/ls1021aqds/ls102xa_pbi.cfg b/board/freescale/ls1021aqds/ls102xa_pbi.cfg new file mode 100644 index 0000000..f1a1b63 --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_pbi.cfg @@ -0,0 +1,12 @@ +#PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00001000 +#Flush PBL data +096100c0 000FFFFF diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg new file mode 100644 index 0000000..222c71d --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol +0608000a 00000000 00000000 00000000 +60000000 00407900 e0106a00 21046000 +00000000 00000000 00000000 00038000 +00000000 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg new file mode 100644 index 0000000..9d99bd8 --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +0608000a 00000000 00000000 00000000 +60000000 00407900 60040a00 21046000 +00000000 00000000 00000000 00038000 +00000000 001b7200 00000000 00000000 + +#disable IFC, enable QSPI and DSPI +#0608000a 00000000 00000000 00000000 +#60000000 00407900 60040a00 21046000 +#00000000 00000000 00000000 00038000 +#20024800 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS index 8def0e5..9176706 100644 --- a/board/freescale/ls1021atwr/MAINTAINERS +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -5,3 +5,5 @@ F: board/freescale/ls1021atwr/ F: include/configs/ls1021atwr.h F: configs/ls1021atwr_nor_defconfig F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig +F: configs/ls1021atwr_sdcard_defconfig +F: configs/ls1021atwr_qspi_defconfig diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 50d5640..8ab229d 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -8,8 +8,11 @@ #include <i2c.h> #include <asm/io.h> #include <asm/arch/immap_ls102xa.h> +#include <asm/arch/ns_access.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#include <asm/arch/ls102xa_stream_id.h> +#include <asm/pcie_layerscape.h> #include <mmc.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> @@ -17,6 +20,11 @@ #include <fsl_mdio.h> #include <tsec.h> #include <fsl_sec.h> +#include <spl.h> +#ifdef CONFIG_U_QE +#include "../../../drivers/qe/qe.h" +#endif + DECLARE_GLOBAL_DATA_PTR; @@ -66,6 +74,7 @@ struct cpld_data { u8 rev2; /* Reserved */ }; +#ifndef CONFIG_QSPI_BOOT static void convert_serdes_mux(int type, int need_reset); void cpld_show(void) @@ -101,11 +110,14 @@ void cpld_show(void) in_8(&cpld_data->serdes_mux)); #endif } +#endif int checkboard(void) { puts("Board: LS1021ATWR\n"); +#ifndef CONFIG_QSPI_BOOT cpld_show(); +#endif return 0; } @@ -214,6 +226,7 @@ int board_eth_init(bd_t *bis) } #endif +#ifndef CONFIG_QSPI_BOOT int config_serdes_mux(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -245,17 +258,15 @@ int config_serdes_mux(void) return 0; } +#endif int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; #ifdef CONFIG_TSEC_ENET - out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV); out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); - udelay(10); - out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV); #endif #ifdef CONFIG_FSL_IFC @@ -263,20 +274,167 @@ int board_early_init_f(void) #endif #ifdef CONFIG_FSL_DCU_FB - out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV); out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); - out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV); +#endif + +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif return 0; } +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + /* Set global data pointer */ + gd = &gdata; + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + get_clocks(); + + preloader_console_init(); + + dram_init(); + + board_init_r(NULL, 0); +} +#endif + +#ifdef CONFIG_LS102XA_NS_ACCESS +static struct csu_ns_dev ns_dev[] = { + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, + { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, + { CSU_CSLX_OCRAM, CSU_ALL_RW }, + { CSU_CSLX_GIC, CSU_ALL_RW }, + { CSU_CSLX_PCIE1, CSU_ALL_RW }, + { CSU_CSLX_OCRAM2, CSU_ALL_RW }, + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, + { CSU_CSLX_PCIE2, CSU_ALL_RW }, + { CSU_CSLX_SATA, CSU_ALL_RW }, + { CSU_CSLX_USB3, CSU_ALL_RW }, + { CSU_CSLX_SERDES, CSU_ALL_RW }, + { CSU_CSLX_QDMA, CSU_ALL_RW }, + { CSU_CSLX_LPUART2, CSU_ALL_RW }, + { CSU_CSLX_LPUART1, CSU_ALL_RW }, + { CSU_CSLX_LPUART4, CSU_ALL_RW }, + { CSU_CSLX_LPUART3, CSU_ALL_RW }, + { CSU_CSLX_LPUART6, CSU_ALL_RW }, + { CSU_CSLX_LPUART5, CSU_ALL_RW }, + { CSU_CSLX_DSPI2, CSU_ALL_RW }, + { CSU_CSLX_DSPI1, CSU_ALL_RW }, + { CSU_CSLX_QSPI, CSU_ALL_RW }, + { CSU_CSLX_ESDHC, CSU_ALL_RW }, + { CSU_CSLX_2D_ACE, CSU_ALL_RW }, + { CSU_CSLX_IFC, CSU_ALL_RW }, + { CSU_CSLX_I2C1, CSU_ALL_RW }, + { CSU_CSLX_USB2, CSU_ALL_RW }, + { CSU_CSLX_I2C3, CSU_ALL_RW }, + { CSU_CSLX_I2C2, CSU_ALL_RW }, + { CSU_CSLX_DUART2, CSU_ALL_RW }, + { CSU_CSLX_DUART1, CSU_ALL_RW }, + { CSU_CSLX_WDT2, CSU_ALL_RW }, + { CSU_CSLX_WDT1, CSU_ALL_RW }, + { CSU_CSLX_EDMA, CSU_ALL_RW }, + { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, + { CSU_CSLX_DDR, CSU_ALL_RW }, + { CSU_CSLX_QUICC, CSU_ALL_RW }, + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, + { CSU_CSLX_SFP, CSU_ALL_RW }, + { CSU_CSLX_TMU, CSU_ALL_RW }, + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, + { CSU_CSLX_RESERVED0, CSU_ALL_RW }, + { CSU_CSLX_ETSEC1, CSU_ALL_RW }, + { CSU_CSLX_SEC5_5, CSU_ALL_RW }, + { CSU_CSLX_ETSEC3, CSU_ALL_RW }, + { CSU_CSLX_ETSEC2, CSU_ALL_RW }, + { CSU_CSLX_GPIO2, CSU_ALL_RW }, + { CSU_CSLX_GPIO1, CSU_ALL_RW }, + { CSU_CSLX_GPIO4, CSU_ALL_RW }, + { CSU_CSLX_GPIO3, CSU_ALL_RW }, + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, + { CSU_CSLX_CSU, CSU_ALL_RW }, + { CSU_CSLX_ASRC, CSU_ALL_RW }, + { CSU_CSLX_SPDIF, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, + { CSU_CSLX_SAI2, CSU_ALL_RW }, + { CSU_CSLX_SAI1, CSU_ALL_RW }, + { CSU_CSLX_SAI4, CSU_ALL_RW }, + { CSU_CSLX_SAI3, CSU_ALL_RW }, + { CSU_CSLX_FTM2, CSU_ALL_RW }, + { CSU_CSLX_FTM1, CSU_ALL_RW }, + { CSU_CSLX_FTM4, CSU_ALL_RW }, + { CSU_CSLX_FTM3, CSU_ALL_RW }, + { CSU_CSLX_FTM6, CSU_ALL_RW }, + { CSU_CSLX_FTM5, CSU_ALL_RW }, + { CSU_CSLX_FTM8, CSU_ALL_RW }, + { CSU_CSLX_FTM7, CSU_ALL_RW }, + { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, + { CSU_CSLX_EPU, CSU_ALL_RW }, + { CSU_CSLX_GDI, CSU_ALL_RW }, + { CSU_CSLX_DDI, CSU_ALL_RW }, + { CSU_CSLX_RESERVED1, CSU_ALL_RW }, + { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, + { CSU_CSLX_RESERVED2, CSU_ALL_RW }, +}; +#endif + +struct smmu_stream_id dev_stream_id[] = { + { 0x100, 0x01, "ETSEC MAC1" }, + { 0x104, 0x02, "ETSEC MAC2" }, + { 0x108, 0x03, "ETSEC MAC3" }, + { 0x10c, 0x04, "PEX1" }, + { 0x110, 0x05, "PEX2" }, + { 0x114, 0x06, "qDMA" }, + { 0x118, 0x07, "SATA" }, + { 0x11c, 0x08, "USB3" }, + { 0x120, 0x09, "QE" }, + { 0x124, 0x0a, "eSDHC" }, + { 0x128, 0x0b, "eMA" }, + { 0x14c, 0x0c, "2D-ACE" }, + { 0x150, 0x0d, "USB2" }, + { 0x18c, 0x0e, "DEBUG" }, +}; + int board_init(void) { + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + + /* + * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register + * All transactions are treated as non-shareable + */ + out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); +#ifndef CONFIG_QSPI_BOOT config_serdes_mux(); #endif +#endif + + ls102xa_config_smmu_stream_id(dev_stream_id, + ARRAY_SIZE(dev_stream_id)); + +#ifdef CONFIG_LS102XA_NS_ACCESS + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#endif + +#ifdef CONFIG_U_QE + u_qe_init(); +#endif return 0; } @@ -290,9 +448,15 @@ int misc_init_r(void) } #endif -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCIE_LAYERSCAPE + ft_pcie_setup(blob, bd); +#endif + + return 0; } u8 flash_read8(void *addr) @@ -314,6 +478,7 @@ u16 flash_read16(void *addr) return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); } +#ifndef CONFIG_QSPI_BOOT static void convert_flash_bank(char bank) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); @@ -496,3 +661,4 @@ U_BOOT_CMD( " -change lane C & lane D to PCIeX2\n" "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" ); +#endif diff --git a/board/freescale/ls1021atwr/ls102xa_pbi.cfg b/board/freescale/ls1021atwr/ls102xa_pbi.cfg new file mode 100644 index 0000000..f1a1b63 --- /dev/null +++ b/board/freescale/ls1021atwr/ls102xa_pbi.cfg @@ -0,0 +1,12 @@ +#PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00001000 +#Flush PBL data +096100c0 000FFFFF diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg new file mode 100644 index 0000000..9c3e3b0 --- /dev/null +++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +0608000a 00000000 00000000 00000000 +20000000 00407900 60040a00 21046000 +00000000 00000000 00000000 00038000 +00080000 881b7340 00000000 00000000 + +#disable IFC, enable QSPI and DSPI +#0608000a 00000000 00000000 00000000 +#20000000 00407900 60040a00 21046000 +#00000000 00000000 00000000 00038000 +#20084800 881b7340 00000000 00000000 diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c index 2c79a71..163a4c4 100644 --- a/board/freescale/ls2085a/ls2085a.c +++ b/board/freescale/ls2085a/ls2085a.c @@ -100,7 +100,7 @@ void fdt_fixup_board_enet(void *fdt) #endif #ifdef CONFIG_OF_BOARD_SETUP -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -115,5 +115,7 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); #endif + + return 0; } #endif diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 940978e..40bd55d 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -275,8 +275,10 @@ int checkboard (void) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c index 71b760c..11747ca 100644 --- a/board/freescale/mpc7448hpc2/mpc7448hpc2.c +++ b/board/freescale/mpc7448hpc2/mpc7448hpc2.c @@ -70,11 +70,12 @@ phys_size_t initdram (int board_type) } #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + + return 0; } #endif diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c index fba41fe..93e1c50 100644 --- a/board/freescale/mpc8308rdb/mpc8308rdb.c +++ b/board/freescale/mpc8308rdb/mpc8308rdb.c @@ -161,11 +161,13 @@ int misc_init_r(void) return 0; } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); fdt_fixup_dr_usb(blob, bd); fdt_fixup_esdhc(blob, bd); + + return 0; } #endif diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index 69e98a5..eac193e 100644 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -116,12 +116,14 @@ int misc_init_r(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif #else /* CONFIG_SPL_BUILD */ diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index e6f091f..ed611c5 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -188,7 +188,7 @@ void fdt_tsec1_fixup(void *fdt, bd_t *bd) do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1); } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI @@ -196,6 +196,8 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_fixup_dr_usb(blob, bd); fdt_tsec1_fixup(blob, bd); + + return 0; } #endif diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 3dce362..0a0152a 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -172,12 +172,14 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c index b7ea0e4..adf4254 100644 --- a/board/freescale/mpc832xemds/mpc832xemds.c +++ b/board/freescale/mpc832xemds/mpc832xemds.c @@ -154,11 +154,13 @@ int checkboard(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index d909220..02b5040 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -273,11 +273,13 @@ void spi_cs_deactivate(struct spi_slave *slave) #endif /* CONFIG_HARD_SPI */ #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 803d722..22a1d99 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -378,11 +378,13 @@ int misc_init_r(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 5ff9dff..f0a55f8 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -402,7 +402,7 @@ static void ft_board_fixup_qe_usb(void *blob, bd_t *bd) "peripheral", sizeof("peripheral"), 1); } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI @@ -447,5 +447,7 @@ void ft_board_setup(void *blob, bd_t *bd) #endif } } + + return 0; } #endif diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c index fef230b..478f820 100644 --- a/board/freescale/mpc8360erdk/mpc8360erdk.c +++ b/board/freescale/mpc8360erdk/mpc8360erdk.c @@ -340,9 +340,11 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); ft_pci_setup(blob, bd); + + return 0; } #endif diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index c749e55..572913c 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -328,7 +328,7 @@ static void ft_pci_fixup(void *blob, bd_t *bd) #endif #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); ft_tsec_fixup(blob, bd); @@ -340,5 +340,7 @@ void ft_board_setup(void *blob, bd_t *bd) ft_pci_fixup(blob, bd); ft_pcie_fixup(blob, bd); #endif + + return 0; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 9afdcaf..e0a1031 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -199,7 +199,7 @@ int misc_init_r(void) #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { #ifdef CONFIG_PCI ft_pci_setup(blob, bd); @@ -207,5 +207,7 @@ void ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); fdt_fixup_dr_usb(blob, bd); fdt_fixup_esdhc(blob, bd); + + return 0; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 93eed59..7b0f461 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -271,7 +271,7 @@ int board_eth_init(bd_t *bis) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); @@ -285,5 +285,6 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_dr_usb(blob, bd); #endif + return 0; } #endif diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index 93288c7..1069e2c 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -218,8 +218,7 @@ pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int node, tmp[2]; const char *path; @@ -237,5 +236,7 @@ ft_board_setup(void *blob, bd_t *bd) } #endif } + + return 0; } #endif diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 1b33db6..66fb228 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -305,7 +305,7 @@ int board_eth_init(bd_t *bis) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); @@ -314,5 +314,7 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + + return 0; } #endif diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 7104e33..f99d639 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -438,8 +438,7 @@ pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int node, tmp[2]; const char *path; @@ -457,5 +456,7 @@ ft_board_setup(void *blob, bd_t *bd) } #endif } + + return 0; } #endif diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index a8fdcb5..a5c5d9d 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -345,10 +345,12 @@ void pci_init_board(void) #endif /* CONFIG_PCI */ #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); FT_FSL_PCI_SETUP; + + return 0; } #endif diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index cb55e1c..836578f 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -514,7 +514,7 @@ void pci_init_board(void) #endif /* CONFIG_PCI */ #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { #if defined(CONFIG_SYS_UCC_RMII_MODE) int nodeoff, off, err; @@ -579,5 +579,7 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_board_fixup_esdhc(blob, bd); fdt_board_fixup_qe_uart(blob, bd); fdt_board_fixup_qe_usb(blob, bd); + + return 0; } #endif diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 1bbf832..3f68cf4 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -232,7 +232,7 @@ int board_eth_init(bd_t *bis) #endif #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -249,5 +249,7 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + + return 0; } #endif diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index d8740dd..95e398c 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -258,12 +258,13 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); FT_FSL_PCI_SETUP; + + return 0; } #endif diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index a58b5f9..94633b5 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -119,12 +119,11 @@ void pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int off; u64 *tmp; - u32 *addrcells; + int addrcells; ft_cpu_setup(blob, bd); @@ -136,12 +135,13 @@ ft_board_setup(void *blob, bd_t *bd) * which is defined by the "reg" property in the soc node. */ off = fdt_path_offset(blob, "/soc8641"); - addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL); + addrcells = fdt_address_cells(blob, 0); tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); if (tmp) { u64 addr; - if (addrcells && (*addrcells == 1)) + + if (addrcells == 1) addr = *(u32 *)tmp; else addr = *tmp; @@ -152,6 +152,8 @@ ft_board_setup(void *blob, bd_t *bd) "in u-boot. This means your .dts might " "be old.\n"); } + + return 0; } #endif diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README index 958ebc6..f9d6324 100644 --- a/board/freescale/mx28evk/README +++ b/board/freescale/mx28evk/README @@ -1,7 +1,7 @@ FREESCALE MX28EVK ================== -Supported hardware: only MX28EVK rev D is supported in U-boot. +Supported hardware: MX28EVK rev C and D are supported in U-boot. Files of the MX28EVK port -------------------------- diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 9b43c84..f1e5eb4 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -320,7 +320,7 @@ int board_mmc_init(bd_t *bis) }; u32 index; - s32 status = 0; + int ret; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); @@ -340,11 +340,13 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more ESDHC controller" "(%d) as supported by the board(2)\n", CONFIG_SYS_FSL_ESDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #endif diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index c960c44..8ba2728 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -166,7 +166,7 @@ int board_mmc_init(bd_t *bis) }; u32 index; - s32 status = 0; + int ret; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); @@ -185,12 +185,14 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more ESDHC controller" "(%d) as supported by the board(2)\n", CONFIG_SYS_FSL_ESDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #endif diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index 13519e2..6ee6d73 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -195,7 +195,7 @@ int board_mmc_init(bd_t *bis) }; u32 index; - s32 status = 0; + int ret; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); @@ -214,12 +214,14 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more ESDHC controller" "(%d) as supported by the board(2)\n", CONFIG_SYS_FSL_ESDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #endif diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index b32a97f..efcf4b3 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -186,7 +186,7 @@ int board_mmc_init(bd_t *bis) }; u32 index; - s32 status = 0; + int ret; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); @@ -205,12 +205,14 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more ESDHC controller" "(%d) as supported by the board(2)\n", CONFIG_SYS_FSL_ESDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #endif @@ -242,6 +244,8 @@ static int power_init(void) if (!p) return -ENODEV; + setenv("fdt_file", "imx53-qsb.dtb"); + /* Set VDDA to 1.25V */ val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); @@ -283,6 +287,8 @@ static int power_init(void) if (!p) return -ENODEV; + setenv("fdt_file", "imx53-qsrb.dtb"); + /* Set VDDGP to 1.25V for 1GHz on SW1 */ pmic_reg_read(p, REG_SW_0, &val); val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index d64c674..0963fd7 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -106,7 +106,7 @@ int board_mmc_init(bd_t *bis) }; u32 index; - s32 status = 0; + int ret; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); @@ -121,12 +121,14 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more ESDHC controller" "(%d) as supported by the board(1)\n", CONFIG_SYS_FSL_ESDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #endif diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 667dca5..3a5b26d 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -125,7 +125,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - s32 status = 0; + int ret; u32 index = 0; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); @@ -145,13 +145,15 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } #endif diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 42ae6fa..59387ff 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -28,6 +28,8 @@ #include <asm/imx-common/video.h> #include <asm/arch/crm_regs.h> #include <pca953x.h> +#include <power/pmic.h> +#include "../common/pfuze.h" DECLARE_GLOBAL_DATA_PTR; @@ -46,8 +48,19 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PMIC 1 + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -92,6 +105,7 @@ static struct i2c_pads_info i2c_pad_info1 = { } }; +#ifndef CONFIG_SYS_FLASH_CFI /* * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor, * Compass Sensor, Accelerometer, Res Touch @@ -108,6 +122,7 @@ static struct i2c_pads_info i2c_pad_info2 = { .gp = IMX_GPIO_NR(3, 18) } }; +#endif static iomux_v3_cfg_t const i2c3_pads[] = { MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -155,6 +170,75 @@ static int port_exp_direction_output(unsigned gpio, int value) return 0; } +static iomux_v3_cfg_t const eimnor_pads[] = { + MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) , + MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void eimnor_cs_setup(void) +{ + struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; + + writel(0x00020181, &weim_regs->cs0gcr1); + writel(0x00000001, &weim_regs->cs0gcr2); + writel(0x0a020000, &weim_regs->cs0rcr1); + writel(0x0000c000, &weim_regs->cs0rcr2); + writel(0x0804a240, &weim_regs->cs0wcr1); + writel(0x00000120, &weim_regs->wcr); + + set_chipselect_size(CS0_128); +} + +static void setup_iomux_eimnor(void) +{ + imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads)); + + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + + eimnor_cs_setup(); +} + static void setup_iomux_enet(void) { imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); @@ -200,6 +284,63 @@ int board_mmc_init(bd_t *bis) } #endif +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t gpmi_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + /* gate ENFC_CLK_ROOT clock first,before clk source switch */ + clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + clrbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable ENFC_CLK_ROOT clock */ + setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + int mx6_rgmii_rework(struct phy_device *phydev) { unsigned short val; @@ -336,6 +477,11 @@ int board_early_init_f(void) #ifdef CONFIG_VIDEO_IPUV3 setup_display(); #endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + return 0; } @@ -349,11 +495,13 @@ int board_init(void) /* I2C 3 Steer */ gpio_direction_output(IMX_GPIO_NR(5, 4), 1); imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads)); +#ifndef CONFIG_SYS_FLASH_CFI setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - +#endif gpio_direction_output(IMX_GPIO_NR(1, 15), 1); imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp)); + setup_iomux_eimnor(); return 0; } @@ -364,6 +512,17 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) } #endif +int power_init_board(void) +{ + struct pmic *p; + + p = pfuze_common_init(I2C_PMIC); + if (!p) + return -ENODEV; + + return 0; +} + #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { /* 4 bit bus width */ diff --git a/board/freescale/mx6sabresd/MAINTAINERS b/board/freescale/mx6sabresd/MAINTAINERS index 69c0a30..0011ec7 100644 --- a/board/freescale/mx6sabresd/MAINTAINERS +++ b/board/freescale/mx6sabresd/MAINTAINERS @@ -5,3 +5,4 @@ F: board/freescale/mx6sabresd/ F: include/configs/mx6sabresd.h F: configs/mx6dlsabresd_defconfig F: configs/mx6qsabresd_defconfig +F: configs/mx6sabresd_spl_defconfig diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 3d81fff..ac3757f 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -27,6 +27,9 @@ #include <i2c.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> +#include "../common/pfuze.h" +#include <asm/arch/mx6-ddr.h> + DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ @@ -55,17 +58,16 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - + gd->ram_size = imx_ddr_size(); return 0; } -iomux_v3_cfg_t const uart1_pads[] = { +static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -iomux_v3_cfg_t const enet_pads[] = { +static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -95,7 +97,7 @@ static void setup_iomux_enet(void) gpio_set_value(IMX_GPIO_NR(1, 25), 1); } -iomux_v3_cfg_t const usdhc2_pads[] = { +static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -109,7 +111,7 @@ iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; -iomux_v3_cfg_t const usdhc3_pads[] = { +static iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -123,7 +125,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; -iomux_v3_cfg_t const usdhc4_pads[] = { +static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -136,7 +138,7 @@ iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; -iomux_v3_cfg_t const ecspi1_pads[] = { +static iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -253,7 +255,8 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - s32 status = 0; +#ifndef CONFIG_SPL_BUILD + int ret; int i; /* @@ -286,13 +289,53 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +#else + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x2 SD2 + * 0x3 SD4 + */ + + switch (reg & 0x3) { + case 0x1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x3: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; } - return status; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif } #endif @@ -517,60 +560,27 @@ int board_init(void) return 0; } -static int pfuze_init(void) +int power_init_board(void) { struct pmic *p; - int ret; unsigned int reg; - ret = power_pfuze100_init(I2C_PMIC); - if (ret) - return ret; - - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) - return ret; - - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + p = pfuze_common_init(I2C_PMIC); + if (!p) + return -ENODEV; /* Increase VGEN3 from 2.5 to 2.8V */ pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); - reg &= ~0xf; - reg |= 0xa; + reg &= ~LDO_VOL_MASK; + reg |= LDOB_2_80V; pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); /* Increase VGEN5 from 2.8 to 3V */ pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); - reg &= ~0xf; - reg |= 0xc; + reg &= ~LDO_VOL_MASK; + reg |= LDOB_3_00V; pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); - /* Set SW1AB stanby volage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); - reg &= ~0x3f; - reg |= 0x1b; - pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); - - /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PUZE_100_SW1ABCONF, ®); - reg &= ~0xc0; - reg |= 0x40; - pmic_reg_write(p, PUZE_100_SW1ABCONF, reg); - - /* Set SW1C standby voltage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); - reg &= ~0x3f; - reg |= 0x1b; - pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); - - /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1CCONF, ®); - reg &= ~0xc0; - reg |= 0x40; - pmic_reg_write(p, PFUZE100_SW1CCONF, reg); - return 0; } @@ -597,8 +607,6 @@ int board_late_init(void) #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif - pfuze_init(); - return 0; } @@ -607,3 +615,169 @@ int checkboard(void) puts("Board: MX6-SabreSD\n"); return 0; } + +#ifdef CONFIG_SPL_BUILD +#include <spl.h> +#include <libfdt.h> + +const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = 0x000C0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x001F001F, + .p0_mpwldectrl1 = 0x001F001F, + .p1_mpwldectrl0 = 0x00440044, + .p1_mpwldectrl1 = 0x00440044, + .p0_mpdgctrl0 = 0x434B0350, + .p0_mpdgctrl1 = 0x034C0359, + .p1_mpdgctrl0 = 0x434B0350, + .p1_mpdgctrl1 = 0x03650348, + .p0_mprddlctl = 0x4436383B, + .p1_mprddlctl = 0x39393341, + .p0_mpwrdlctl = 0x35373933, + .p1_mpwrdlctl = 0x48254A36, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 64, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +/* + * This section requires the differentiation between iMX6 Sabre boards, but + * for now, it will configure only for the mx6q variant. + */ +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = mem_ddr.width/32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} +#endif diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 3ae2c46..3834eec 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -232,16 +232,11 @@ int board_eth_init(bd_t *bis) static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - int ret; /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - ret = enable_fec_anatop_clock(ENET_50MHz); - if (ret) - return ret; - - return 0; + return enable_fec_anatop_clock(ENET_50MHZ); } #endif diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 02e82b2..fd8bc72 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -25,6 +25,7 @@ #include <netdev.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> +#include "../common/pfuze.h" #include <usb.h> #include <usb/ehci-fsl.h> @@ -70,6 +71,34 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD pin */ + MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* RST_B, used for power reset cycle */ + MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -121,7 +150,6 @@ static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int ret; int reg; /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ @@ -142,11 +170,7 @@ static int setup_fec(void) reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; writel(reg, &anatop->pll_enet); - ret = enable_fec_anatop_clock(ENET_125MHz); - if (ret) - return ret; - - return 0; + return enable_fec_anatop_clock(ENET_125MHZ); } int board_eth_init(bd_t *bis) @@ -172,57 +196,67 @@ static struct i2c_pads_info i2c_pad_info1 = { }, }; -static int pfuze_init(void) +int power_init_board(void) { struct pmic *p; - int ret; unsigned int reg; - ret = power_pfuze100_init(I2C_PMIC); - if (ret) - return ret; - - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) - return ret; - - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - - /* Set SW1AB standby voltage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); - reg &= ~0x3f; - reg |= 0x1b; - pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); - - /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PUZE_100_SW1ABCONF, ®); - reg &= ~0xc0; - reg |= 0x40; - pmic_reg_write(p, PUZE_100_SW1ABCONF, reg); - - /* Set SW1C standby voltage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); - reg &= ~0x3f; - reg |= 0x1b; - pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); - - /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1CCONF, ®); - reg &= ~0xc0; - reg |= 0x40; - pmic_reg_write(p, PFUZE100_SW1CCONF, reg); + p = pfuze_common_init(I2C_PMIC); + if (!p) + return -ENODEV; /* Enable power of VGEN5 3V3, needed for SD3 */ pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); - reg &= ~0x1F; - reg |= 0x1F; + reg &= ~LDO_VOL_MASK; + reg |= (LDOB_3_30V | (1 << LDO_EN)); pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); return 0; } +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + /* OGT1 */ + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + /* OTG2 */ + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + int board_phy_config(struct phy_device *phydev) { /* @@ -245,7 +279,6 @@ int board_phy_config(struct phy_device *phydev) int board_early_init_f(void) { setup_iomux_uart(); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, @@ -261,78 +294,97 @@ int board_early_init_f(void) return 0; } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, {USDHC4_BASE_ADDR}, }; +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) +#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11) +#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21) + int board_mmc_getcd(struct mmc *mmc) { - return 1; /* Assume boot SD always present */ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = 1; /* Assume uSDHC2 is always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = !gpio_get_value(USDHC4_CD_GPIO); + break; + } + + return ret; } int board_mmc_init(bd_t *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - -#ifdef CONFIG_USB_EHCI_MX6 -#define USB_OTHERREGS_OFFSET 0x800 -#define UCTRL_PWR_POL (1 << 9) - -static iomux_v3_cfg_t const usb_otg_pads[] = { - /* OGT1 */ - MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), - /* OTG2 */ - MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) -}; - -static void setup_usb(void) -{ - imx_iomux_v3_setup_multiple_pads(usb_otg_pads, - ARRAY_SIZE(usb_otg_pads)); -} - -int board_usb_phy_mode(int port) -{ - if (port == 1) - return USB_INIT_HOST; - else - return usb_phy_mode(port); -} - -int board_ehci_hcd_init(int port) -{ - u32 *usbnc_usb_ctrl; - - if (port > 1) - return -EINVAL; - - usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + - port * 4); + int i, ret; - /* Set Power polarity */ - setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC2 + * mmc1 USDHC3 + * mmc2 USDHC4 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + gpio_direction_output(USDHC3_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + gpio_direction_input(USDHC4_CD_GPIO); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } return 0; } -#endif int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + return 0; } int board_late_init(void) { - pfuze_init(); - return 0; } diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 491b576..1cf0ab7 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -444,7 +444,7 @@ void fdt_disable_uart1(void *blob) } } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -496,6 +496,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_del_flexcan(blob); fdt_disable_uart1(blob); } + + return 0; } #endif diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index f5e1851..d7dd478 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -332,7 +332,7 @@ static void ft_codec_setup(void *blob, const char *compatible) } } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -356,5 +356,7 @@ void ft_board_setup(void *blob, bd_t *bd) /* Update the WM8776 node's clock frequency property */ ft_codec_setup(blob, "wlf,wm8776"); + + return 0; } #endif diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c index d4d277b..56f561a 100644 --- a/board/freescale/p1023rdb/p1023rdb.c +++ b/board/freescale/p1023rdb/p1023rdb.c @@ -130,7 +130,7 @@ int board_eth_init(bd_t *bis) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -147,5 +147,7 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_fixup_fman_ethernet(blob); + + return 0; } #endif diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index aba4f53..61ed466 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -234,7 +234,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_OF_BOARD_SETUP) extern void ft_pci_board_setup(void *blob); -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { const char *soc_usb_compat = "fsl-usb2-dr"; int err, usb1_off, usb2_off; @@ -263,39 +263,41 @@ void ft_board_setup(void *blob, bd_t *bd) int off = fdt_node_offset_by_compatible(blob, -1, soc_elbc_compat); if (off < 0) { - printf("WARNING: could not find compatible node" - " %s: %s.\n", soc_elbc_compat, - fdt_strerror(off)); - return; + printf("WARNING: could not find compatible node %s\n", + soc_elbc_compat); + return off; } err = fdt_del_node(blob, off); if (err < 0) { - printf("WARNING: could not remove %s: %s.\n", - soc_elbc_compat, fdt_strerror(err)); + printf("WARNING: could not remove %s\n", + soc_elbc_compat); + return err; } - return; + return 0; } #endif /* Delete USB2 node as it is muxed with eLBC */ usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat); if (usb1_off < 0) { - printf("WARNING: could not find compatible node" - " %s: %s.\n", soc_usb_compat, - fdt_strerror(usb1_off)); - return; + printf("WARNING: could not find compatible node %s\n", + soc_usb_compat); + return usb1_off; } usb2_off = fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat); if (usb2_off < 0) { - printf("WARNING: could not find compatible node" - " %s: %s.\n", soc_usb_compat, - fdt_strerror(usb2_off)); - return; + printf("WARNING: could not find compatible node %s\n", + soc_usb_compat); + return usb2_off; } err = fdt_del_node(blob, usb2_off); - if (err < 0) - printf("WARNING: could not remove %s: %s.\n", - soc_usb_compat, fdt_strerror(err)); + if (err < 0) { + printf("WARNING: could not remove %s\n", soc_usb_compat); + return err; + } + + return 0; } + #endif diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index a6756c6..3f47cfb 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -424,7 +424,7 @@ static void fdt_board_fixup_qe_pins(void *blob) #endif #ifdef CONFIG_OF_BOARD_SETUP -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -459,17 +459,17 @@ void ft_board_setup(void *blob, bd_t *bd) int off = fdt_node_offset_by_compatible(blob, -1, soc_elbc_compat); if (off < 0) { - printf("WARNING: could not find compatible node %s: %s.\n", - soc_elbc_compat, - fdt_strerror(off)); - return; + printf("WARNING: could not find compatible node %s\n", + soc_elbc_compat); + return off; } err = fdt_del_node(blob, off); if (err < 0) { - printf("WARNING: could not remove %s: %s.\n", - soc_elbc_compat, fdt_strerror(err)); + printf("WARNING: could not remove %s\n", + soc_elbc_compat); + return err; } - return; + return 0; } #endif @@ -477,24 +477,23 @@ void ft_board_setup(void *blob, bd_t *bd) usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat); if (usb1_off < 0) { - printf("WARNING: could not find compatible node %s: %s.\n", - soc_usb_compat, - fdt_strerror(usb1_off)); - return; + printf("WARNING: could not find compatible node %s\n", + soc_usb_compat); + return usb1_off; } usb2_off = fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat); if (usb2_off < 0) { - printf("WARNING: could not find compatible node %s: %s.\n", - soc_usb_compat, - fdt_strerror(usb2_off)); - return; + printf("WARNING: could not find compatible node %s\n", + soc_usb_compat); + return usb2_off; } err = fdt_del_node(blob, usb2_off); if (err < 0) { - printf("WARNING: could not remove %s: %s.\n", - soc_usb_compat, fdt_strerror(err)); + printf("WARNING: could not remove %s\n", soc_usb_compat); + return err; } + return 0; } #endif diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c index a0a416b..a40bea3 100644 --- a/board/freescale/p1_twr/p1_twr.c +++ b/board/freescale/p1_twr/p1_twr.c @@ -261,7 +261,7 @@ static void fdt_board_fixup_qe_pins(void *blob) #endif #ifdef CONFIG_OF_BOARD_SETUP -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -283,5 +283,7 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_board_fixup_qe_pins(blob); #endif fdt_fixup_dr_usb(blob, bd); + + return 0; } #endif diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c index f777bb9..1db37e3 100644 --- a/board/freescale/p2020come/p2020come.c +++ b/board/freescale/p2020come/p2020come.c @@ -250,7 +250,7 @@ int board_eth_init(bd_t *bis) #endif #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -269,5 +269,7 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_HAS_FSL_DR_USB fdt_fixup_dr_usb(blob, bd); #endif + + return 0; } #endif diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index b72fcff..5d18e8d 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -236,7 +236,7 @@ int board_eth_init(bd_t *bis) #endif #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -257,5 +257,7 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + + return 0; } #endif diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index a14b43b..e600bdb 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -215,7 +215,7 @@ int misc_init_r(void) return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -239,4 +239,6 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); #endif + + return 0; } diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c index 230870d..a0fca0d 100644 --- a/board/freescale/qemu-ppce500/qemu-ppce500.c +++ b/board/freescale/qemu-ppce500/qemu-ppce500.c @@ -235,9 +235,11 @@ int board_eth_init(bd_t *bis) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; + + return 0; } #endif diff --git a/board/freescale/t102xqds/Kconfig b/board/freescale/t102xqds/Kconfig new file mode 100644 index 0000000..4d17798 --- /dev/null +++ b/board/freescale/t102xqds/Kconfig @@ -0,0 +1,12 @@ +if TARGET_T102XQDS + +config SYS_BOARD + default "t102xqds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "T102xQDS" + +endif diff --git a/board/freescale/t102xqds/MAINTAINERS b/board/freescale/t102xqds/MAINTAINERS new file mode 100644 index 0000000..1ffccc4 --- /dev/null +++ b/board/freescale/t102xqds/MAINTAINERS @@ -0,0 +1,12 @@ +T102XQDS BOARD +M: Shengzhou Liu <Shengzhou.Liu@freescale.com> +S: Maintained +F: board/freescale/t102xqds/ +F: include/configs/T102xQDS.h +F: configs/T1024QDS_defconfig +F: configs/T1024QDS_NAND_defconfig +F: configs/T1024QDS_SDCARD_defconfig +F: configs/T1024QDS_SPIFLASH_defconfig +F: configs/T1024QDS_D4_defconfig +F: configs/T1024QDS_SECURE_BOOT_defconfig +F: configs/T1024QDS_D4_SECURE_BOOT_defconfig diff --git a/board/freescale/t102xqds/Makefile b/board/freescale/t102xqds/Makefile new file mode 100644 index 0000000..d94f230 --- /dev/null +++ b/board/freescale/t102xqds/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += t102xqds.o +obj-y += eth_t102xqds.o +obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_FSL_DIU_FB) += ../t1040qds/diu.o +endif +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t102xqds/README b/board/freescale/t102xqds/README new file mode 100644 index 0000000..bb0f280 --- /dev/null +++ b/board/freescale/t102xqds/README @@ -0,0 +1,328 @@ +T1024 SoC Overview +------------------ +The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor +combines two or one 64-bit Power Architecture e5500 core respectively with high +performance datapath acceleration logic, and network peripheral bus interfaces +required for networking and telecommunications. This processor can be used in +applications such as enterprise WLAN access points, routers, switches, firewall +and other packet processing intensive small enterprise and branch office appliances, +and general-purpose embedded computing. Its high level of integration offers +significant performance benefits and greatly helps to simplify board design. + + +The T1024 SoC includes the following function and features: +- two e5500 cores, each with a private 256 KB L2 cache + - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant) + - Three levels of instructions: User, supervisor, and hypervisor + - Independent boot and reset + - Secure boot capability +- 256 KB shared L3 CoreNet platform cache (CPC) +- Interconnect CoreNet platform + - CoreNet coherency manager supporting coherent and noncoherent transactions + with prioritization and bandwidth allocation amongst CoreNet endpoints + - 150 Gbps coherent read bandwidth +- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support +- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: + - Packet parsing, classification, and distribution + - Queue management for scheduling, packet sequencing, and congestion management + - Cryptography Acceleration (SEC 5.x) + - IEEE 1588 support + - Hardware buffer management for buffer allocation and deallocation + - MACSEC on DPAA-based Ethernet ports +- Ethernet interfaces + - Four 1 Gbps Ethernet controllers +- Parallel Ethernet interfaces + - Two RGMII interfaces +- High speed peripheral interfaces + - Three PCI Express 2.0 controllers/ports running at up to 5 GHz + - One SATA controller supporting 1.5 and 3.0 Gb/s operation + - One QSGMII interface + - Four SGMII interface supporting 1000 Mbps + - Three SGMII interfaces supporting up to 2500 Mbps + - 10GbE XFI or 10Base-KR interface +- Additional peripheral interfaces + - Two USB 2.0 controllers with integrated PHY + - SD/eSDHC/eMMC + - eSPI controller + - Four I2C controllers + - Four UARTs + - Four GPIO controllers + - Integrated flash controller (IFC) + - LCD interface (DIU) with 12 bit dual data rate +- Multicore programmable interrupt controller (PIC) +- Two 8-channel DMA engines +- Single source clocking implementation +- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) +- QUICC Engine block + - 32-bit RISC controller for flexible support of the communications peripherals + - Serial DMA channel for receive and transmit on all serial channels + - Two universal communication controllers, supporting TDM, HDLC, and UART + +T1023 Personality +------------------ +T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and +unavailable deep sleep. Rest of the blocks are almost same as T1024. +Differences between T1024 and T1023 +Feature T1024 T1023 +QUICC Engine: yes no +DIU: yes no +Deep Sleep: yes no +I2C controller: 4 3 +DDR: 64-bit 32-bit +IFC: 32-bit 28-bit + + +T1024QDS board Overview +----------------------- +- SERDES Connections + 4 lanes supporting the following: + - PCI Express: supports Gen 1 and Gen 2 + - SGMII 1G and SGMII 2.5G + - QSGMII + - XFI + - SATA 2.0 + - High-speed multiplexers route the SerDes traffic to appropriate slots or connectors. + - Aurora debug with dedicated connectors. +- DDR Controller + - Supports up to 1600 MTPS data-rate. + - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card. + - Supports Single-, dual- or quad-rank DIMMs + - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT. +- IFC/Local Bus + - NAND Flash: 8-bit, async, up to 2GB + - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB + - NOR devices support 8 virtual banks + - Socketed to allow alternate devices + - GASIC: Simple (minimal) target within QIXIS FPGA + - PromJET rapid memory download support + - IFC Debug/Development card +- Ethernet + - Two on-board RGMII 10M/100M/1G ethernet ports. + - One QSGMII interface + - Four SGMII interface supporting 1Gbps + - Three SGMII interfaces supporting 2.5Gbps + - one 10Gbps XFI or 10Base-KR interface +- QIXIS System Logic FPGA + - Manages system power and reset sequencing. + - Manages the configurations of DUT, board, and clock for dynamic shmoo. + - Collects V-I-T data in background for code/power profiling. + - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion). + - General fault monitoring and logging. + - Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off. +- Clocks + - System and DDR clock (SYSCLK, DDRCLK). + - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz. + - Software programmable in 1 MHz increments from 1-200 MHz. + - SERDES clocks + - Provides clocks to SerDes blocks and slots. + - 100 MHz, 125 MHz and 156.25 MHz options. + - Spread-spectrum option for 100 MHz. +- Power Supplies + - Dedicated PMBus regulator for VDD and VDDC. + - Adjustable from 0.7V to 1.3V at 35A + - VDD can be disabled independanty from VDDC for “deep sleep”. + - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A. + - VTT/MVREF automatically track operating voltage. + - Dedicated 2.5V VPP supply. + - Dedicated regulators/filters for AVDD supplies. + - Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD. +- Video + - DIU supports video up to 1280x1024x32 bpp. + - Chrontel CH7201 for HDMI connection. + - TI DS90C387R for direct LCD connection. + - Raw (not encoded) video connector for testing or other encoders. +- USB + - Supports two USB 2.0 ports with integrated PHYs. + - Two type A ports with 5V@1.5A per port. + - Second port can be converted to OTG mini-AB. +- SDHC + For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features: + - upport for optional clock feedback paths. + - Support for optional high-speed voltage translation direction controls. + - Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC. + - Support for eMMC memory devices. +- SPI + -On-board support of 3 different devices and sizes. +- Other IO + - Two Serial ports + - ProfiBus port + - Four I2C ports + + +Memory map on T1024QDS +---------------------- +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB +0x0_0000_0000 0x0_ffff_ffff DDR 4GB + + +128MB NOR Flash memory Map +-------------------------- +Start Address End Address Definition Max size +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +SerDes clock vs DIP-switch settings +----------------------------------- +SRDS_PRTCL_S1 SD1_REF_CLK1 SD1_REF_CLK2 SW4[1:4] +0x6F 100MHz 125MHz 1101 +0xD6 100MHz 100MHz 1111 +0x99 156.25MHz 100MHz 1011 + + +T1024 Clock frequency +---------------------- +BIN Core DDR Platform FMan +Bin1: 1400MHz 1600MT/s 400MHz 700MHz +Bin2: 1200MHz 1600MT/s 400MHz 600MHz +Bin3: 1000MHz 1600MT/s 400MHz 500MHz + + + +Software configurations and board settings +------------------------------------------ +1. NOR boot: + a. build NOR boot image + $ make T1024QDS_defconfig (For DDR3L, by default) + or make T1024QDS_D4_defconfig (For DDR4) + $ make + b. program u-boot.bin image to NOR flash + => tftp 1000000 u-boot.bin + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize + set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot + + Switching between default bank0 and alternate bank4 on NOR flash + To change boot source to vbank4: + via software: run command 'qixis_reset altbank' in u-boot. + via DIP-switch: set SW6[1:4] = '0100' + + To change boot source to vbank0: + via software: run command 'qixis_reset' in u-boot. + via DIP-Switch: set SW6[1:4] = '0000' + +2. NAND Boot: + a. build PBL image for NAND boot + $ make T1024QDS_NAND_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to NAND flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => nand erase 0 $filesize + => nand write 1000000 0 $filesize + set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot + +3. SPI Boot: + a. build PBL image for SPI boot + $ make T1024QDS_SPIFLASH_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to SPI flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => sf probe 0 + => sf erase 0 f0000 + => sf write 1000000 0 $filesize + set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot + +4. SD Boot: + a. build PBL image for SD boot + $ make T1024QDS_SDCARD_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to SD/MMC card + => tftp 1000000 u-boot-with-spl-pbl.bin + => mmc write 1000000 8 0x800 + => tftp 1000000 fsl_fman_ucode_t1024_xx.bin + => mmc write 1000000 0x820 80 + set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot + + +DIU/QE-TDM/SDXC settings +------------------- +a) For TDM Riser: set pin_mux=tdm in hwconfig +b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig +c) For HDMI(DVI): set pin_mux=hdmi in hwconfig +d) For LCD(DFP): set pin_mux=lcd in hwconfig +e) For SDXC: set adaptor=sdxc in hwconfig + +2-stage NAND/SPI/SD boot loader +------------------------------- +PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. +SPL further initializes DDR using SPD and environment variables +and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (30KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T1024QDS +------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB +0x100000 0x15FFFF u-boot env 8KB +0x160000 0x17FFFF FMAN Ucode 128KB +0x180000 0x19FFFF QE Firmware 128KB + + +SD Card memory Map on T1024QDS +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 u-boot img 1MB +0x800 0016 u-boot env 8KB +0x820 0256 FMAN Ucode 128KB +0x920 0256 QE Firmware 128KB + + +SPI Flash memory Map on T1024QDS +---------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB +0x100000 0x101FFF u-boot env 8KB +0x110000 0x12FFFF FMAN Ucode 128KB +0x130000 0x14FFFF QE Firmware 128KB + + +For more details, please refer to T1024QDS Reference Manual and access +website www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c new file mode 100644 index 0000000..46fc64e --- /dev/null +++ b/board/freescale/t102xqds/ddr.c @@ -0,0 +1,170 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <hwconfig.h> +#include <asm/mmu.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * datarate_mhz_high values need to be in ascending order + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ +#if defined(CONFIG_SYS_FSL_DDR4) + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, + {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,}, +#elif defined(CONFIG_SYS_FSL_DDR3) + {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, +#else +#error DDR type not defined +#endif + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + struct cpu_type *cpu = gd->arch.cpu; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust according to the board ddr freqency and n_banks + * specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found\n"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ", + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2); + debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * rtt and rtt_wr override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif + + /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit, + * set DDR bus width to 32bit for T1023 + */ + if (cpu->soc_ver == SVR_T1023) + popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; + +#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32 + /* for DDR bus 32bit test on T1024 */ + popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; +#endif +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif + return dram_size; +} diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c new file mode 100644 index 0000000..7723f58 --- /dev/null +++ b/board/freescale/t102xqds/eth_t102xqds.c @@ -0,0 +1,442 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Shengzhou Liu <Shengzhou.Liu@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> +#include <malloc.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> +#include <asm/fsl_dtsec.h> +#include <asm/fsl_serdes.h> +#include "../common/qixis.h" +#include "../common/fman.h" +#include "t102xqds_qixis.h" + +#define EMI_NONE 0xFFFFFFFF +#define EMI1_RGMII1 0 +#define EMI1_RGMII2 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT2 3 +#define EMI1_SLOT3 4 +#define EMI1_SLOT4 5 +#define EMI1_SLOT5 6 +#define EMI2 7 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { + "T1024QDS_MDIO_RGMII1", + "T1024QDS_MDIO_RGMII2", + "T1024QDS_MDIO_SLOT1", + "T1024QDS_MDIO_SLOT2", + "T1024QDS_MDIO_SLOT3", + "T1024QDS_MDIO_SLOT4", + "T1024QDS_MDIO_SLOT5", + "T1024QDS_MDIO_10GC", + "NULL", +}; + +/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ +static u8 lane_to_slot[] = {2, 3, 4, 5}; + +static const char *t1024qds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name; + + if (muxval > EMI2) + return NULL; + + name = t1024qds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct t1024qds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void t1024qds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + + if (muxval < 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct t1024qds_mdio *priv = bus->priv; + + t1024qds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct t1024qds_mdio *priv = bus->priv; + + t1024qds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int t1024qds_mdio_reset(struct mii_dev *bus) +{ + struct t1024qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int t1024qds_mdio_init(char *realbusname, u8 muxval) +{ + struct t1024qds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate t1024qds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate t1024qds private data\n"); + free(bus); + return -1; + } + + bus->read = t1024qds_mdio_read; + bus->write = t1024qds_mdio_write; + bus->reset = t1024qds_mdio_reset; + sprintf(bus->name, t1024qds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + struct fixed_link f_link; + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) { + if (port == FM1_DTSEC3) { + fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2"); + fdt_setprop(fdt, offset, "phy-connection-type", + "rgmii", 5); + fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); + } + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + if (port == FM1_DTSEC1) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_vsc8234_phy_s5"); + } else if (port == FM1_DTSEC2) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_vsc8234_phy_s4"); + } + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { + if (port == FM1_DTSEC3) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_aqr105_phy_s3"); + } + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { + switch (port) { + case FM1_DTSEC1: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1"); + break; + case FM1_DTSEC2: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2"); + break; + case FM1_DTSEC3: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3"); + break; + case FM1_DTSEC4: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4"); + break; + default: + break; + } + fdt_delprop(fdt, offset, "phy-connection-type"); + fdt_setprop(fdt, offset, "phy-connection-type", "qsgmii", 6); + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { + /* XFI interface */ + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for XFI */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop(fdt, offset, "phy-connection-type", "xgmii", 5); + } +} + +void fdt_fixup_board_enet(void *fdt) +{ +} + +/* + * This function reads RCW to check if Serdes1{A:D} is configured + * to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly + */ +static void initialize_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + switch (srds_s1) { + case 0x46: + case 0x47: + lane_to_slot[1] = 2; + break; + default: + break; + } +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, idx, lane, slot, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + initialize_lane_to_slot(); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); + t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); + + switch (srds_s1) { + case 0xd5: + case 0xd6: + /* QSGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC1, 0x8); + fm_info_set_phy_address(FM1_DTSEC2, 0x9); + fm_info_set_phy_address(FM1_DTSEC3, 0xa); + fm_info_set_phy_address(FM1_DTSEC4, 0xb); + break; + case 0x95: + case 0x99: + /* + * XFI does not need a PHY to work, but to avoid U-boot use + * default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to XFI + * MAC, and should not use a real XAUI PHY address, since + * MDIO can access it successfully, and then MDIO thinks the + * XAUI card is used for the XFI MAC, which will cause error. + */ + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x6f: + /* SGMII in Slot3, Slot4, Slot5 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x7f: + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3); + break; + case 0x47: + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x77: + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3); + break; + case 0x5a: + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x6a: + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x5b: + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x6b: + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); + break; + default: + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_QSGMII: + if (interface == PHY_INTERFACE_MODE_SGMII) { + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_2500_FM1_DTSEC1 + idx); + } else { + lane = serdes_get_first_lane(FSL_SRDS_1, + QSGMII_FM1_A); + } + + if (lane < 0) + break; + + slot = lane_to_slot[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + + switch (slot) { + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 5: + mdio_mux[i] = EMI1_SLOT5; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC3) + mdio_mux[i] = EMI1_RGMII2; + else if (i == FM1_DTSEC4) + mdio_mux[i] = EMI1_RGMII1; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + idx = i - FM1_10GEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + XFI_FM1_MAC1 + idx); + if (lane < 0) + break; + mdio_mux[i] = EMI2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/t102xqds/law.c b/board/freescale/t102xqds/law.c new file mode 100644 index 0000000..b1c9d01 --- /dev/null +++ b/board/freescale/t102xqds/law.c @@ -0,0 +1,32 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { +#ifndef CONFIG_SYS_NO_FLASH + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef QIXIS_BASE_PHYS + SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t102xqds/pci.c b/board/freescale/t102xqds/pci.c new file mode 100644 index 0000000..7369289 --- /dev/null +++ b/board/freescale/t102xqds/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/fsl_serdes.h> + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c new file mode 100644 index 0000000..08aef6e --- /dev/null +++ b/board/freescale/t102xqds/spl.c @@ -0,0 +1,151 @@ +/* Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> +#include "../common/qixis.h" +#include "t102xqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT) + /* + * There is T1040 SoC issue where NOR, FPGA are inaccessible during + * NAND boot because IFC signals > IFC_AD7 are not enabled. + * This workaround changes RCW source to make all signals enabled. + */ + u32 porsr1, pinctl; +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 + + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#endif + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t102xqds/t1024_pbi.cfg b/board/freescale/t102xqds/t1024_pbi.cfg new file mode 100644 index 0000000..7b9e9b0 --- /dev/null +++ b/board/freescale/t102xqds/t1024_pbi.cfg @@ -0,0 +1,26 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF diff --git a/board/freescale/t102xqds/t1024_rcw.cfg b/board/freescale/t102xqds/t1024_rcw.cfg new file mode 100644 index 0000000..4b8f719 --- /dev/null +++ b/board/freescale/t102xqds/t1024_rcw.cfg @@ -0,0 +1,10 @@ +# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz +# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz + +# PBL preamble and RCW header for T1024QDS +aa55aa55 010e0100 +# Serdes protocol 0x6F +0810000e 00000000 00000000 00000000 +37800001 00000012 e8104000 21000000 +00000000 00000000 00000000 00030810 +00000000 036c5a00 00000000 00000006 diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c new file mode 100644 index 0000000..f3141b5 --- /dev/null +++ b/board/freescale/t102xqds/t102xqds.c @@ -0,0 +1,408 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <netdev.h> +#include <linux/compiler.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> +#include <fm_eth.h> +#include <hwconfig.h> +#include <asm/mpc85xx_gpio.h> +#include "../common/qixis.h" +#include "t102xqds.h" +#include "t102xqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + char buf[64]; + struct cpu_type *cpu = gd->arch.cpu; + static const char *const freq[] = {"100", "125", "156.25", "100.0"}; + int clock; + u8 sw = QIXIS_READ(arch); + + printf("Board: %sQDS, ", cpu->name); + printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); + printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); + +#ifdef CONFIG_SDCARD + puts("SD/MMC\n"); +#elif CONFIG_SPIFLASH + puts("SPI\n"); +#else + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("PromJet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else if (sw == 0x15) + printf("IFC Card\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif + + printf("FPGA: v%d (%s), build %d", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + + puts("SERDES Reference: "); + sw = QIXIS_READ(brdcfg[2]); + clock = (sw >> 6) & 3; + printf("Clock1=%sMHz ", freq[clock]); + clock = (sw >> 4) & 3; + printf("Clock2=%sMHz\n", freq[clock]); + + return 0; +} + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +static int board_mux_lane_to_slot(void) +{ + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1; + u8 brdcfg9; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + + brdcfg9 = QIXIS_READ(brdcfg[9]); + QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE); + + switch (srds_prtcl_s1) { + case 0: + /* SerDes1 is not enabled */ + break; + case 0xd5: + case 0x5b: + case 0x6b: + case 0x77: + case 0x6f: + case 0x7f: + QIXIS_WRITE(brdcfg[12], 0x8c); + break; + case 0x40: + QIXIS_WRITE(brdcfg[12], 0xfc); + break; + case 0xd6: + case 0x5a: + case 0x6a: + case 0x56: + QIXIS_WRITE(brdcfg[12], 0x88); + break; + case 0x47: + QIXIS_WRITE(brdcfg[12], 0xcc); + break; + case 0x46: + QIXIS_WRITE(brdcfg[12], 0xc8); + break; + case 0x95: + case 0x99: + brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE; + QIXIS_WRITE(brdcfg[9], brdcfg9); + QIXIS_WRITE(brdcfg[12], 0x8c); + break; + case 0x116: + QIXIS_WRITE(brdcfg[12], 0x00); + break; + case 0x115: + case 0x119: + case 0x129: + case 0x12b: + /* Aurora, PCIe, SGMII, SATA */ + QIXIS_WRITE(brdcfg[12], 0x04); + break; + default: + printf("WARNING: unsupported for SerDes Protocol %d\n", + srds_prtcl_s1); + return -1; + } + + return 0; +} + +#ifdef CONFIG_PPC_T1024 +static void board_mux_setup(void) +{ + u8 brdcfg15; + + brdcfg15 = QIXIS_READ(brdcfg[15]); + brdcfg15 &= ~BRDCFG15_DIUSEL_MASK; + + if (hwconfig_arg_cmp("pin_mux", "tdm")) { + /* Route QE_TDM multiplexed signals to TDM Riser slot */ + QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM); + QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2); + QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) & + ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM); + } else if (hwconfig_arg_cmp("pin_mux", "ucc")) { + /* to UCC (ProfiBus) interface */ + QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC); + } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) { + /* to DVI (HDMI) encoder */ + QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI); + } else if (hwconfig_arg_cmp("pin_mux", "lcd")) { + /* to DFP (LCD) encoder */ + QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM | + BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD); + } + + if (hwconfig_arg_cmp("adaptor", "sdxc")) + /* Route SPI_CS multiplexed signals to SD slot */ + QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) & + ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC); +} +#endif + +void board_retimer_ds125df111_init(void) +{ + u8 reg; + + /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ + reg = I2C_MUX_CH7; + i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); + reg = I2C_MUX_CH5; + i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); + + /* Access to Control/Shared register */ + reg = 0x0; + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); + + /* Read device revision and ID */ + i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast */ + reg = 0x0c; + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); + + /* Reset Channel Registers */ + i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); + reg |= 0x4; + i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); + + /* Enable override divider select and Enable Override Output Mux */ + i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); + reg |= 0x24; + i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); + + /* Select VCO Divider to full rate (000) */ + i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); + reg &= 0x8f; + i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); + + /* Select active PFD MUX input as re-timed data (001) */ + i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); + reg &= 0x3f; + reg |= 0x20; + i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x0; + i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); + reg = 0xb2; + i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); + reg = 0x90; + i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); + reg = 0xb3; + i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); + reg = 0xcd; + i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +} + +int board_early_init_r(void) +{ +#ifdef CONFIG_SYS_FLASH_BASE + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); +#endif + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + board_mux_lane_to_slot(); + board_retimer_ds125df111_init(); + + /* Increase IO drive strength to address FCS error on RGMII */ + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +#define NUM_SRDS_PLL 2 +int misc_init_r(void) +{ +#ifdef CONFIG_PPC_T1024 + board_mux_setup(); +#endif + return 0; +} + +void fdt_fixup_spi_mux(void *blob) +{ + int nodeoff = 0; + + if (hwconfig_arg_cmp("pin_mux", "tdm")) { + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "eon,en25s64")) >= 0) { + fdt_del_node(blob, nodeoff); + } + } else { + /* remove tdm node */ + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "maxim,ds26522")) >= 0) { + fdt_del_node(blob, nodeoff); + } + } +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif + fdt_fixup_spi_mux(blob); + + return 0; +} + +void qixis_dump_switch(void) +{ + int i, nr_of_cfgsw; + + QIXIS_WRITE(cms[0], 0x00); + nr_of_cfgsw = QIXIS_READ(cms[1]); + + puts("DIP switch settings dump:\n"); + for (i = 1; i <= nr_of_cfgsw; i++) { + QIXIS_WRITE(cms[0], i); + printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); + } +} + +#ifdef CONFIG_DEEP_SLEEP +void board_mem_sleep_setup(void) +{ + /* does not provide HW signals for power management */ + QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif diff --git a/board/freescale/t102xqds/t102xqds.h b/board/freescale/t102xqds/t102xqds.h new file mode 100644 index 0000000..64ff623 --- /dev/null +++ b/board/freescale/t102xqds/t102xqds.h @@ -0,0 +1,14 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T102x_QDS_H__ +#define __T102x_QDS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); +int select_i2c_ch_pca9547(u8 ch); + +#endif diff --git a/board/freescale/t102xqds/t102xqds_qixis.h b/board/freescale/t102xqds/t102xqds_qixis.h new file mode 100644 index 0000000..a429fb7 --- /dev/null +++ b/board/freescale/t102xqds/t102xqds_qixis.h @@ -0,0 +1,64 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T1024QDS_QIXIS_H__ +#define __T1024QDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for T1024/T1023 QDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/ +#define BRDCFG5_IMX_MASK 0xC0 +#define BRDCFG5_IMX_DIU 0x80 + +#define BRDCFG5_SPIRTE_MASK 0x07 +#define BRDCFG5_SPIRTE_TDM 0x01 +#define BRDCFG5_SPIRTE_SDHC 0x02 +#define BRDCFG9_XFI_TX_DISABLE 0x10 + +/* BRDCFG13[0:5] TDM configuration and setup */ +#define BRDCFG13_TDM_MASK 0xfc +#define BRDCFG13_TDM_INTERFACE 0x37 +#define BRDCFG13_HDLC_LOOPBACK 0x29 +#define BRDCFG13_TDM_LOOPBACK 0x31 + +/* BRDCFG15[3] controls LCD Panel Powerdown */ +#define BRDCFG15_LCDFM 0x20 +#define BRDCFG15_LCDPD 0x10 +#define BRDCFG15_LCDPD_MASK 0x10 +#define BRDCFG15_LCDPD_ENABLED 0x00 + +/* BRDCFG15[6:7] controls DIU MUX selction*/ +#define BRDCFG15_DIUSEL_MASK 0x03 +#define BRDCFG15_DIUSEL_HDMI 0x00 +#define BRDCFG15_DIUSEL_LCD 0x01 +#define BRDCFG15_DIUSEL_UCC 0x02 +#define BRDCFG15_DIUSEL_TDM 0x03 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 +#define QIXIS_SYSCLK_64 0x8 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + + +#define QIXIS_SRDS1CLK_122 0x5a +#define QIXIS_SRDS1CLK_125 0x5e +#endif diff --git a/board/freescale/t102xqds/tlb.c b/board/freescale/t102xqds/tlb.c new file mode 100644 index 0000000..409e173 --- /dev/null +++ b/board/freescale/t102xqds/tlb.c @@ -0,0 +1,117 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the + * SRAM is at 0xfffc0000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_SPL_BUILD + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_16M, 1), +#endif +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef QIXIS_BASE + SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_4K, 1), +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif + /* entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so if needed more, will use entry 16 later. + */ +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig new file mode 100644 index 0000000..10d49f5 --- /dev/null +++ b/board/freescale/t102xrdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_T102XRDB + +config SYS_BOARD + default "t102xrdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "T102xRDB" + +endif diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS new file mode 100644 index 0000000..dc554d4 --- /dev/null +++ b/board/freescale/t102xrdb/MAINTAINERS @@ -0,0 +1,10 @@ +T102XRDB BOARD +M: Shengzhou Liu <Shengzhou.Liu@freescale.com> +S: Maintained +F: board/freescale/t102xrdb/ +F: include/configs/T102xRDB.h +F: configs/T1024RDB_defconfig +F: configs/T1024RDB_NAND_defconfig +F: configs/T1024RDB_SDCARD_defconfig +F: configs/T1024RDB_SPIFLASH_defconfig +F: configs/T1024RDB_SECURE_BOOT_defconfig diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile new file mode 100644 index 0000000..a0cf8f6 --- /dev/null +++ b/board/freescale/t102xrdb/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += t102xrdb.o +obj-y += cpld.o +obj-y += eth_t102xrdb.o +obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README new file mode 100644 index 0000000..2b17f50 --- /dev/null +++ b/board/freescale/t102xrdb/README @@ -0,0 +1,258 @@ +T1024 SoC Overview +------------------ +The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor +combines two or one 64-bit Power Architecture e5500 core respectively with high +performance datapath acceleration logic, and network peripheral bus interfaces +required for networking and telecommunications. This processor can be used in +applications such as enterprise WLAN access points, routers, switches, firewall +and other packet processing intensive small enterprise and branch office appliances, +and general-purpose embedded computing. Its high level of integration offers +significant performance benefits and greatly helps to simplify board design. + + +The T1024 SoC includes the following function and features: +- two e5500 cores, each with a private 256 KB L2 cache + - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant) + - Three levels of instructions: User, supervisor, and hypervisor + - Independent boot and reset + - Secure boot capability +- 256 KB shared L3 CoreNet platform cache (CPC) +- Interconnect CoreNet platform + - CoreNet coherency manager supporting coherent and noncoherent transactions + with prioritization and bandwidth allocation amongst CoreNet endpoints + - 150 Gbps coherent read bandwidth +- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support +- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: + - Packet parsing, classification, and distribution + - Queue management for scheduling, packet sequencing, and congestion management + - Cryptography Acceleration (SEC 5.x) + - IEEE 1588 support + - Hardware buffer management for buffer allocation and deallocation + - MACSEC on DPAA-based Ethernet ports +- Ethernet interfaces + - Four 1 Gbps Ethernet controllers +- Parallel Ethernet interfaces + - Two RGMII interfaces +- High speed peripheral interfaces + - Three PCI Express 2.0 controllers/ports running at up to 5 GHz + - One SATA controller supporting 1.5 and 3.0 Gb/s operation + - One QSGMII interface + - Four SGMII interface supporting 1000 Mbps + - Three SGMII interfaces supporting up to 2500 Mbps + - 10GbE XFI or 10Base-KR interface +- Additional peripheral interfaces + - Two USB 2.0 controllers with integrated PHY + - SD/eSDHC/eMMC + - eSPI controller + - Four I2C controllers + - Four UARTs + - Four GPIO controllers + - Integrated flash controller (IFC) + - LCD interface (DIU) with 12 bit dual data rate +- Multicore programmable interrupt controller (PIC) +- Two 8-channel DMA engines +- Single source clocking implementation +- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) +- QUICC Engine block + - 32-bit RISC controller for flexible support of the communications peripherals + - Serial DMA channel for receive and transmit on all serial channels + - Two universal communication controllers, supporting TDM, HDLC, and UART + +T1023 Personality +------------------ +T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and +unavailable deep sleep. Rest of the blocks are almost same as T1024. +Differences between T1024 and T1023 +Feature T1024 T1023 +QUICC Engine: yes no +DIU: yes no +Deep Sleep: yes no +I2C controller: 4 3 +DDR: 64-bit 32-bit +IFC: 32-bit 28-bit + + +T1024RDB board Overview +----------------------- + - Ethernet + - Two on-board 10M/100M/1G bps RGMII ethernet ports + - One on-board 10G bps Base-T port. + - DDR Memory + - Supports 64-bit 4GB DDR3L DIMM + - PCIe + - One on-board PCIe slot. + - Two on-board PCIe Mini-PCIe connectors. + - IFC/Local Bus + - NOR: 128MB 16-bit NOR Flash + - NAND: 1GB 8-bit NAND flash + - CPLD: for system controlling with programable header on-board + - USB + - Supports two USB 2.0 ports with integrated PHYs + - Two type A ports with 5V@1.5A per port. + - SDHC + - one SD connector supporting 1.8V/3.3V via J53. + - SPI + - On-board 64MB SPI flash + - Other + - Two Serial ports + - Four I2C ports + + +Memory map on T1024RDB +---------------------- +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB +0x0_0000_0000 0x0_ffff_ffff DDR 4GB + + +128MB NOR Flash memory Map +-------------------------- +Start Address End Address Definition Max size +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +T1024 Clock frequency +--------------------- +BIN Core DDR Platform FMan +Bin1: 1400MHz 1600MT/s 400MHz 700MHz +Bin2: 1200MHz 1600MT/s 400MHz 600MHz +Bin3: 1000MHz 1600MT/s 400MHz 500MHz + + +Software configurations and board settings +------------------------------------------ +1. NOR boot: + a. build NOR boot image + $ make T1024RDB_defconfig + $ make + b. program u-boot.bin image to NOR flash + => tftp 1000000 u-boot.bin + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize + set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot + + Switching between default bank0 and alternate bank4 on NOR flash + To change boot source to vbank4: + via software: run command 'cpld reset altbank' in u-boot. + via DIP-switch: set SW3[5:7] = '100' + + To change boot source to vbank0: + via software: run command 'cpld reset' in u-boot. + via DIP-Switch: set SW3[5:7] = '000' + +2. NAND Boot: + a. build PBL image for NAND boot + $ make T1024RDB_NAND_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to NAND flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => nand erase 0 $filesize + => nand write 1000000 0 $filesize + set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot + +3. SPI Boot: + a. build PBL image for SPI boot + $ make T1024RDB_SPIFLASH_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to SPI flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => sf probe 0 + => sf erase 0 f0000 + => sf write 1000000 0 $filesize + set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot + +4. SD Boot: + a. build PBL image for SD boot + $ make T1024RDB_SDCARD_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to SD/MMC card + => tftp 1000000 u-boot-with-spl-pbl.bin + => mmc write 1000000 8 0x800 + => tftp 1000000 fsl_fman_ucode_t1024_xx.bin + => mmc write 1000000 0x820 80 + set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot + + +2-stage NAND/SPI/SD boot loader +------------------------------- +PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. +SPL further initializes DDR using SPD and environment variables +and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (30KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T1024RDB +------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB(2 block) +0x100000 0x17FFFF u-boot env 512KB(1 block) +0x180000 0x1FFFFF FMAN Ucode 512KB(1 block) +0x200000 0x27FFFF QE Firmware 512KB(1 block) + + +SD Card memory Map on T1024RDB +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 u-boot img 1MB +0x800 0016 u-boot env 8KB +0x820 0256 FMAN Ucode 128KB +0x920 0256 QE Firmware 128KB + + +SPI Flash memory Map on T1024RDB +---------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB +0x100000 0x101FFF u-boot env 8KB +0x110000 0x12FFFF FMAN Ucode 128KB +0x130000 0x14FFFF QE Firmware 128KB + + +For more details, please refer to T1024RDB Reference Manual and access +website www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c new file mode 100644 index 0000000..c03894a --- /dev/null +++ b/board/freescale/t102xrdb/cpld.c @@ -0,0 +1,103 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Freescale T1024RDB board-specific CPLD controlling supports. + * + * The following macros need to be defined: + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_csr); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + + CPLD_WRITE(flash_csr, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_csr); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + + CPLD_WRITE(flash_csr, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); + printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); + printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); + printf("int_status = 0x%02x\n", CPLD_READ(int_status)); + printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr)); + printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); + printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); + printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); + printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); + printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); + printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1)); + printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2)); + putc('\n'); +} + +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); + } else { + rc = cmd_usage(cmdtp); + } + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - hard reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" + "cpld dump - display the CPLD registers\n" + ); diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h new file mode 100644 index 0000000..5a3100f --- /dev/null +++ b/board/freescale/t102xrdb/cpld.h @@ -0,0 +1,45 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +struct cpld_data { + u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl1; /* 0x10 - Reset control Register1 */ + u8 reset_ctl2; /* 0x11 - Reset control Register2 */ + u8 int_status; /* 0x12 - Interrupt status Register */ + u8 flash_csr; /* 0x13 - Flash control and status register */ + u8 fan_ctl_status; /* 0x14 - Fan control and status register */ + u8 led_ctl_status; /* 0x15 - LED control and status register */ + u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ + u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ + u8 boot_override; /* 0x18 - Boot override register */ + u8 boot_config1; /* 0x19 - Boot config override register*/ + u8 boot_config2; /* 0x1A - Boot config override register*/ +} cpld_data_t; + + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value)\ + cpld_write(offsetof(struct cpld_data, reg), value) + +/* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 +#define CPLD_BOOT_SEL 0x80 diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c new file mode 100644 index 0000000..a20330b --- /dev/null +++ b/board/freescale/t102xrdb/ddr.c @@ -0,0 +1,154 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <hwconfig.h> +#include <asm/mmu.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * datarate_mhz_high values need to be in ascending order + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + struct cpu_type *cpu = gd->arch.cpu; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust according to the board ddr freqency and n_banks + * specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found\n"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ", + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2); + debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * rtt and rtt_wr override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF); + + /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit, + * force DDR bus width to 32bit for T1023 + */ + if (cpu->soc_ver == SVR_T1023) + popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; + +#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32 + /* for DDR bus 32bit test on T1024 */ + popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; +#endif +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif + return dram_size; +} diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c new file mode 100644 index 0000000..2e400c4 --- /dev/null +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -0,0 +1,100 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> +#include <malloc.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> +#include <asm/fsl_dtsec.h> +#include <asm/fsl_serdes.h> + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); + + switch (srds_s1) { + case 0x95: + /* 10G XFI with Aquantia PHY */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + break; + default: + printf("SerDes protocol 0x%x is not supported on T102xRDB\n", + srds_s1); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_RGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} + +void fdt_fixup_board_enet(void *fdt) +{ +} diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c new file mode 100644 index 0000000..1c9235f --- /dev/null +++ b/board/freescale/t102xrdb/law.c @@ -0,0 +1,32 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { +#ifndef CONFIG_SYS_NO_FLASH + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_CPLD_BASE_PHYS + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c new file mode 100644 index 0000000..ba7041a --- /dev/null +++ b/board/freescale/t102xrdb/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2007-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/fsl_serdes.h> + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c new file mode 100644 index 0000000..dd2dec4 --- /dev/null +++ b/board/freescale/t102xrdb/spl.c @@ -0,0 +1,107 @@ +/* Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t102xrdb/t1024_pbi.cfg b/board/freescale/t102xrdb/t1024_pbi.cfg new file mode 100644 index 0000000..7b9e9b0 --- /dev/null +++ b/board/freescale/t102xrdb/t1024_pbi.cfg @@ -0,0 +1,26 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF diff --git a/board/freescale/t102xrdb/t1024_rcw.cfg b/board/freescale/t102xrdb/t1024_rcw.cfg new file mode 100644 index 0000000..cd6f906 --- /dev/null +++ b/board/freescale/t102xrdb/t1024_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header for T1024RDB +aa55aa55 010e0100 +#SerDes Protocol: 0x95 +#Core/DDR: 1400Mhz/1600MT/s with single source clock +0810000c 00000000 00000000 00000000 +4a800003 80000012 ec027000 21000000 +00000000 00000000 00000000 00030810 +00000000 0b005a08 00000000 00000006 diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c new file mode 100644 index 0000000..f5c438d --- /dev/null +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -0,0 +1,144 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <netdev.h> +#include <linux/compiler.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> +#include <asm/mpc85xx_gpio.h> +#include <fm_eth.h> +#include "t102xrdb.h" +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; + + printf("Board: %sRDB, ", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + +#ifdef CONFIG_SDCARD + puts("SD/MMC\n"); +#elif CONFIG_SPIFLASH + puts("SPI\n"); +#else + u8 reg; + + reg = CPLD_READ(flash_csr); + + if (reg & CPLD_BOOT_SEL) { + puts("NAND\n"); + } else { + reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + printf("NOR vBank%d\n", reg); + } +#endif + + puts("SERDES Reference Clocks:\n"); + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); + + return 0; +} + +int board_early_init_r(void) +{ +#ifdef CONFIG_SYS_FLASH_BASE + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); +#endif + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif + + return 0; +} + +#ifdef CONFIG_DEEP_SLEEP +void board_mem_sleep_setup(void) +{ + /* does not provide HW signals for power management */ + CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40)); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h new file mode 100644 index 0000000..2f23579 --- /dev/null +++ b/board/freescale/t102xrdb/t102xrdb.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T1024_RDB_H__ +#define __T1024_RDB_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c new file mode 100644 index 0000000..8269b3d --- /dev/null +++ b/board/freescale/t102xrdb/tlb.c @@ -0,0 +1,117 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the + * SRAM is at 0xfffc0000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_SPL_BUILD + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_16M, 1), +#endif +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1), +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif + /* entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so if needed more, will use entry 16 later. + */ +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 19af46e..13285be 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -233,7 +233,7 @@ int misc_init_r(void) return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -259,6 +259,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); fdt_fixup_board_enet(blob); #endif + + return 0; } void qixis_dump_switch(void) diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index 3822a37..e394b12 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -34,20 +34,26 @@ unsigned long get_board_ddr_clk(void) void board_init_f(ulong bootflag) { u32 plat_ratio, sys_clk, uart_clk; -#ifdef CONFIG_SPL_NAND_BOOT +#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) u32 porsr1, pinctl; + u32 svr = get_svr(); #endif ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; -#ifdef CONFIG_SPL_NAND_BOOT - /* - * There is T1040 SoC issue where NOR, FPGA are inaccessible during - * NAND boot because IFC signals > IFC_AD7 are not enabled. - * This workaround changes RCW source to make all signals enabled. - */ - porsr1 = in_be32(&gur->porsr1); - pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); - out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) + if (IS_SVR_REV(svr, 1, 0)) { + /* + * There is T1040 SoC issue where NOR, FPGA are inaccessible + * during NAND boot because IFC signals > IFC_AD7 are not + * enabled. This workaround changes RCW source to make all + * signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) + | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), + pinctl); + } #endif /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg index 7b9e9b0..b83b9b7 100644 --- a/board/freescale/t104xrdb/t104x_pbi.cfg +++ b/board/freescale/t104xrdb/t104x_pbi.cfg @@ -1,4 +1,14 @@ #PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 #Initialize CPC1 09010000 00200400 09138000 00000000 diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index ddb669f..4734f9d 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -85,7 +85,7 @@ int misc_init_r(void) return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -110,6 +110,8 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); #endif + + return 0; } #ifdef CONFIG_DEEP_SLEEP diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README new file mode 100755 index 0000000..83060c1 --- /dev/null +++ b/board/freescale/t208xqds/README @@ -0,0 +1,274 @@ +The T2080QDS is a high-performance computing evaluation, development and +test platform supporting the T2080 QorIQ Power Architecture processor. + +T2080 SoC Overview +------------------ +The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power +Architecture processor cores with high-performance datapath acceleration +logic and network and peripheral bus interfaces required for networking, +telecom/datacom, wireless infrastructure, and mil/aerospace applications. + +T2080 includes the following functions and features: + - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz + - 2MB L2 cache and 512KB CoreNet platform cache (CPC) + - Hierarchical interconnect fabric + - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving + - Data Path Acceleration Architecture (DPAA) incorporating acceleration + - 16 SerDes lanes up to 10.3125 GHz + - 8 Ethernet interfaces, supporting combinations of the following: + - Up to four 10 Gbps Ethernet MACs + - Up to eight 1 Gbps Ethernet MACs + - Up to four 2.5 Gbps Ethernet MACs + - High-speed peripheral interfaces + - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) + - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz + - Additional peripheral interfaces + - Two serial ATA (SATA 2.0) controllers + - Two high-speed USB 2.0 controllers with integrated PHY + - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) + - Enhanced serial peripheral interface (eSPI) + - Four I2C controllers + - Four 2-pin UARTs or two 4-pin UARTs + - Integrated Flash Controller supporting NAND and NOR flash + - Three eight-channel DMA engines + - Support for hardware virtualization and partitioning enforcement + - QorIQ Platform's Trust Architecture 2.0 + +Differences between T2080 and T2081 +----------------------------------- + Feature T2080 T2081 + 1G Ethernet numbers: 8 6 + 10G Ethernet numbers: 4 2 + SerDes lanes: 16 8 + Serial RapidIO,RMan: 2 no + SATA Controller: 2 no + Aurora: yes no + SoC Package: 896-pins 780-pins + + +T2080QDS feature overview +------------------------- +Processor: + - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz +Memory: + - Single memory controller capable of supporting DDR3 and DDR3-LV devices + - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support +Ethernet interfaces: + - Two 1Gbps RGMII on-board ports + - Four 10Gbps XFI on-board cages + - 1Gbps/2.5Gbps SGMII Riser card + - 10Gbps XAUI Riser card +Accelerator: + - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC +SerDes: + - 16 lanes up to 10.3125GHz + - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI +IFC: + - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA +eSPI: + - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) +USB: + - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB) +PCIE: + - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) +SATA: + - Two SATA 2.0 ports on-board +SRIO: + - Two Serial RapidIO 2.0 ports up to 5 GHz +eSDHC: + - Supports SD/SDHC/SDXC/eMMC Card +I2C: + - Four I2C controllers. +UART: + - Dual 4-pins UART serial ports +System Logic: + - QIXIS-II FPGA system controll +Debug Features: + - Support Legacy, COP/JTAG, Aurora, Event and EVT +XFI: + - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to + a on-board SFP+ cages, which to house optical module (fiber cable) or + direct attach cable(copper), the copper cable is used to emulate + 10GBASE-KR scenario. + So, for XFI usage, there are two scenarios, one will use fiber cable, + another will use copper cable. An hwconfig env "fsl_10gkr_copper" is + introduced to indicate a XFI port will use copper cable, and U-boot + will fixup the dtb accordingly. + It's used as: fsl_10gkr_copper:<10g_mac_name> + The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they + do not have to be coexist in hwconfig. If a MAC is listed in the env + "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable + will be used by default. + for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in + hwconfig, then both four XFI ports will use copper cable. + set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two + XFI ports will use copper cable, the other two XFI ports will use fiber + cable. +1000BASE-KX(1G-KX): + - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane + runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane + in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration + Register 1 (PCCR1), and U-boot fixup the dtb for kernel to do proper + initialization. + Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC + 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a + MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1' + stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc. + For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in + hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode. + +System Memory map +---------------- + +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB +0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB +0x0_0000_0000 0x0_ffff_ffff DDR 4GB + + +128M NOR Flash memory Map +------------------------- +Start Address End Address Definition Max size +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + + +Software configurations and board settings +------------------------------------------ +1. NOR boot: + a. build NOR boot image + $ make T2080QDS_config + $ make + b. program u-boot.bin image to NOR flash + => tftp 1000000 u-boot.bin + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize + set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot + + Switching between default bank0 and alternate bank4 on NOR flash + To change boot source to vbank4: + by software: run command 'qixis_reset altbank' in u-boot. + by DIP-switch: set SW6[1:4] = '0100' + + To change boot source to vbank0: + by software: run command 'qixis_reset' in u-boot. + by DIP-Switch: set SW6[1:4] = '0000' + +2. NAND Boot: + a. build PBL image for NAND boot + $ make T2080QDS_NAND_config + $ make + b. program u-boot-with-spl-pbl.bin to NAND flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => nand erase 0 $filesize + => nand write 1000000 0 $filesize + set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot + +3. SPI Boot: + a. build PBL image for SPI boot + $ make T2080QDS_SPIFLASH_config + $ make + b. program u-boot-with-spl-pbl.bin to SPI flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => sf probe 0 + => sf erase 0 f0000 + => sf write 1000000 0 $filesize + set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot + +4. SD Boot: + a. build PBL image for SD boot + $ make T2080QDS_SDCARD_config + $ make + b. program u-boot-with-spl-pbl.bin to SD/MMC card + => tftp 1000000 u-boot-with-spl-pbl.bin + => mmc write 1000000 8 0x800 + => tftp 1000000 fsl_fman_ucode_T2080_xx.bin + => mmc write 1000000 0x820 80 + set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot + + +2-stage NAND/SPI/SD boot loader +------------------------------- +PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. +SPL further initializes DDR using SPD and environment variables +and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (50KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T2080QDS +-------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB (2 blocks) +0x100000 0x17FFFF u-boot env 512KB (1 block) +0x180000 0x1FFFFF FMAN ucode 512KB (1 block) + + +Micro SD Card memory Map on T2080QDS +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 u-boot img 1MB +0x800 0016 u-boot env 8KB +0x820 0128 FMAN ucode 64KB + + +SPI Flash memory Map on T2080QDS +---------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB +0x100000 0x101FFF u-boot env 8KB +0x110000 0x11FFFF FMAN ucode 64KB + + +How to update the ucode of Freescale FMAN +----------------------------------------- +=> tftp 1000000 fsl_fman_ucode_t2080_xx.bin +=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize + + +For more details, please refer to T2080QDS User Guide and access +website www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h index ed52fef6..9c26fdf 100644 --- a/board/freescale/t208xqds/ddr.h +++ b/board/freescale/t208xqds/ddr.h @@ -28,17 +28,16 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {2, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09}, - {2, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, - {2, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {2, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c}, - {2, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {2, 1200, 0, 5, 7, 0x0708090a, 0x0b0c0d09}, + {2, 1400, 0, 5, 7, 0x08090a0c, 0x0d0e0f0a}, + {2, 1700, 0, 5, 8, 0x090a0b0c, 0x0e10110c}, + {2, 1900, 0, 5, 8, 0x090b0c0f, 0x1012130d}, + {2, 2140, 0, 5, 8, 0x090b0c0f, 0x1012130d}, {1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a}, {1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09}, {1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, - {1, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {1, 1700, 0, 4, 8, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 5, 8, 0x090a0c0d, 0x0e0f110c}, {1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b}, {} }; diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 5879198..b82e9e7 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -23,6 +23,7 @@ #include <phy.h> #include <asm/fsl_dtsec.h> #include <asm/fsl_serdes.h> +#include <hwconfig.h> #include "../common/qixis.h" #include "../common/fman.h" #include "t208xqds_qixis.h" @@ -46,6 +47,15 @@ #define EMI2 8 #endif +#define PCCR1_SGMIIA_KX_MASK 0x00008000 +#define PCCR1_SGMIIB_KX_MASK 0x00004000 +#define PCCR1_SGMIIC_KX_MASK 0x00002000 +#define PCCR1_SGMIID_KX_MASK 0x00001000 +#define PCCR1_SGMIIE_KX_MASK 0x00000800 +#define PCCR1_SGMIIF_KX_MASK 0x00000400 +#define PCCR1_SGMIIG_KX_MASK 0x00000200 +#define PCCR1_SGMIIH_KX_MASK 0x00000100 + static int mdio_mux[NUM_FM_PORTS]; static const char * const mdio_names[] = { @@ -187,8 +197,18 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, { int phy; char alias[20]; + char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"}; + char buf[32] = "serdes-1,"; struct fixed_link f_link; + int media_type = 0; + int off; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_T2080QDS + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1); +#endif u32 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; @@ -199,9 +219,54 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, switch (port) { #if defined(CONFIG_T2080QDS) case FM1_DTSEC1: + if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx1"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1"); + sprintf(buf, "%s%s%s", buf, "lane-c,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIH_KX_MASK); + break; + } case FM1_DTSEC2: + if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx2"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2"); + sprintf(buf, "%s%s%s", buf, "lane-d,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIG_KX_MASK); + break; + } case FM1_DTSEC9: + if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx9"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9"); + sprintf(buf, "%s%s%s", buf, "lane-a,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIE_KX_MASK); + break; + } case FM1_DTSEC10: + if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx10"); + fdt_status_okay_by_alias(fdt, + "1gkx_pcs_mdio10"); + sprintf(buf, "%s%s%s", buf, "lane-b,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIF_KX_MASK); + break; + } if (mdio_mux[port] == EMI1_SLOT2) { sprintf(alias, "phy_sgmii_s2_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); @@ -213,7 +278,29 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } break; case FM1_DTSEC5: + if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx5"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5"); + sprintf(buf, "%s%s%s", buf, "lane-g,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIC_KX_MASK); + break; + } case FM1_DTSEC6: + if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx6"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6"); + sprintf(buf, "%s%s%s", buf, "lane-h,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIID_KX_MASK); + break; + } if (mdio_mux[port] == EMI1_SLOT1) { sprintf(alias, "phy_sgmii_s1_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); @@ -257,6 +344,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, default: break; } + if (media_type) { + /* set property for 1000BASE-KX in dtb */ + off = fdt_node_offset_by_compat_reg(fdt, + "fsl,fman-memac-mdio", addr + 0x1000); + fdt_setprop_string(fdt, off, "lane-instance", buf); + } } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { switch (srds_s1) { @@ -265,15 +358,77 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, case 0x6c: case 0x6d: case 0x71: - f_link.phy_id = port; - f_link.duplex = 1; - f_link.link_speed = 10000; - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for XFI */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, - sizeof(f_link)); + /* + * if the 10G is XFI, check hwconfig to see what is the + * media type, there are two types, fiber or copper, + * fix the dtb accordingly. + */ + switch (port) { + case FM1_10GEC1: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { + /* it's MAC9 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi9"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9"); + sprintf(buf, "%s%s%s", buf, "lane-a,", + (char *)lane_mode[1]); + } + break; + case FM1_10GEC2: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { + /* it's MAC10 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi10"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10"); + sprintf(buf, "%s%s%s", buf, "lane-b,", + (char *)lane_mode[1]); + } + break; + case FM1_10GEC3: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) { + /* it's MAC1 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi1"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1"); + sprintf(buf, "%s%s%s", buf, "lane-c,", + (char *)lane_mode[1]); + } + break; + case FM1_10GEC4: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) { + /* it's MAC2 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi2"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2"); + sprintf(buf, "%s%s%s", buf, "lane-d,", + (char *)lane_mode[1]); + } + break; + default: + return; + } + + if (!media_type) { + /* fixed-link is used for XFI fiber cable */ + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, + sizeof(f_link)); + } else { + /* set property for copper cable */ + off = fdt_node_offset_by_compat_reg(fdt, + "fsl,fman-memac-mdio", addr + 0x1000); + fdt_setprop_string(fdt, off, + "lane-instance", buf); + } break; default: break; diff --git a/board/freescale/t208xqds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg index 972dedc..52a1652 100644 --- a/board/freescale/t208xqds/t2080_rcw.cfg +++ b/board/freescale/t208xqds/t2080_rcw.cfg @@ -1,8 +1,16 @@ #PBL preamble and RCW header aa55aa55 010e0100 -#SerDes Protocol: 0x66_0x16 -#Core/DDR: 1533Mhz/2133MT/s -12100017 15000000 00000000 00000000 -66150002 00008400 e8104000 c1000000 + +#For T2080 v1.0 +#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s +#12100017 15000000 00000000 00000000 +#66150002 00008400 e8104000 c1000000 +#00000000 00000000 00000000 000307fc +#00000000 00000000 00000000 00000004 + +#For T2080 v1.1 +#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s +0c070012 0e000000 00000000 00000000 +66150002 00000000 e8104000 c1000000 00000000 00000000 00000000 000307fc 00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index fc6d256..7c89cd5 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -20,6 +20,7 @@ #include "../common/qixis.h" #include "../common/vsc3316_3308.h" +#include "../common/vid.h" #include "t208xqds.h" #include "t208xqds_qixis.h" @@ -86,6 +87,11 @@ int select_i2c_ch_pca9547(u8 ch) return 0; } +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel); +} + int brd_mux_lane_to_slot(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -358,6 +364,13 @@ int board_early_init_r(void) /* Disable remote I2C connection to qixis fpga */ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); + /* + * Adjust core voltage according to voltage ID + * This function changes I2C mux to channel 2. + */ + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); + brd_mux_lane_to_slot(); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); @@ -437,7 +450,7 @@ int misc_init_r(void) return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -460,4 +473,6 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); fdt_fixup_board_enet(blob); #endif + + return 0; } diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg index 15e1bf4..59025ea 100644 --- a/board/freescale/t208xrdb/t2080_rcw.cfg +++ b/board/freescale/t208xrdb/t2080_rcw.cfg @@ -1,8 +1,16 @@ -#PBL preamble and RCW header for T2080RDB +#PBL preamble and RCW header aa55aa55 010e0100 -#SerDes Protocol: 0x66_0x16 -#Core/DDR: 1533Mhz/1600MT/s -120c0017 15000000 00000000 00000000 -66150002 00008400 ec104000 c1000000 -00000000 00000000 00000000 000307fc + +#For T2080 v1.0 +#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s +#120c0017 15000000 00000000 00000000 +#66150002 00008400 ec104000 c1000000 +#00000000 00000000 00000000 000307fc +#00000000 00000000 00000000 00000004 + +#For T2080 v1.1 +#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s +1206001b 15000000 00000000 00000000 +66150002 00000000 e8104000 c1000000 +00800000 00000000 00000000 000307fc 00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index be99fb8..341453b 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -103,7 +103,7 @@ int misc_init_r(void) return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -126,4 +126,6 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); fdt_fixup_board_enet(blob); #endif + + return 0; } diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c index 479e124..5441094 100644 --- a/board/freescale/t4qds/t4240emu.c +++ b/board/freescale/t4qds/t4240emu.c @@ -69,7 +69,7 @@ int misc_init_r(void) return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -83,4 +83,6 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_liodn(blob); fdt_fixup_dr_usb(blob, bd); + + return 0; } diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index 6205fea..4f2cccd 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -683,7 +683,7 @@ int misc_init_r(void) return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -706,6 +706,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); fdt_fixup_board_enet(blob); #endif + + return 0; } /* diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile index f7f7fc0..3886e3d 100644 --- a/board/freescale/t4rdb/Makefile +++ b/board/freescale/t4rdb/Makefile @@ -5,6 +5,7 @@ # obj-$(CONFIG_T4240RDB) += t4240rdb.o +obj-y += cpld.o obj-y += ddr.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c new file mode 100644 index 0000000..d5f3812 --- /dev/null +++ b/board/freescale/t4rdb/cpld.c @@ -0,0 +1,136 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * Author: Chunhe Lan <Chunhe.Lan@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the + * CPLD register map + * + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 val, curbank, altbank, override; + + val = CPLD_READ(vbank); + curbank = val & CPLD_BANK_SEL_MASK; + + switch (curbank) { + case CPLD_SELECT_BANK0: + altbank = CPLD_SELECT_BANK4; + CPLD_WRITE(vbank, altbank); + override = CPLD_READ(software_on); + CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); + CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); + break; + case CPLD_SELECT_BANK4: + altbank = CPLD_SELECT_BANK0; + CPLD_WRITE(vbank, altbank); + override = CPLD_READ(software_on); + CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); + CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); + break; + default: + printf("CPLD Altbank Fail: Invalid value!\n"); + return; + } +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 val; + + val = CPLD_DEFAULT_BANK; + + CPLD_WRITE(global_reset, val); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1)); + printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2)); + printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver)); + printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("software_on = 0x%02x\n", CPLD_READ(software_on)); + printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src)); + printf("res0 = 0x%02x\n", CPLD_READ(res0)); + printf("vbank = 0x%02x\n", CPLD_READ(vbank)); + printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk)); + printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status)); + printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status)); + printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status)); + printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset)); + printf("global_reset = 0x%02x\n", CPLD_READ(global_reset)); + printf("res1 = 0x%02x\n", CPLD_READ(res1)); + putc('\n'); +} +#endif + +#ifndef CONFIG_SPL_BUILD +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif + ); +#endif diff --git a/board/freescale/t4rdb/cpld.h b/board/freescale/t4rdb/cpld.h new file mode 100644 index 0000000..0180082 --- /dev/null +++ b/board/freescale/t4rdb/cpld.h @@ -0,0 +1,49 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * Author: Chunhe Lan <Chunhe.Lan@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */ + u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */ + u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */ + u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */ + u8 hw_ver; /* 0x04 - PCBA Version Register */ + u8 software_on; /* 0x05 - Override Physical Switch Enable Register */ + u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */ + u8 res0; /* 0x07 - not used */ + u8 vbank; /* 0x08 - Flash Bank Selection Control Register */ + u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */ + u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */ + u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */ + u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */ + u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/ + u8 global_reset;/* 0x0e - Reset System With Default Registers Value */ + u8 res1; /* 0x0f - not used */ +}; + +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_SEL_EN 0x04 +#define CPLD_SYSTEM_RESET 0x01 +#define CPLD_SELECT_BANK0 0x00 +#define CPLD_SELECT_BANK4 0x04 +#define CPLD_DEFAULT_BANK 0x01 + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c index 1f58768..39818fc 100644 --- a/board/freescale/t4rdb/law.c +++ b/board/freescale/t4rdb/law.c @@ -16,6 +16,9 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_QMAN_MEM_PHYS SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif +#ifdef CONFIG_SYS_CPLD_BASE_PHYS + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index afef7e9..fac442b 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -20,14 +20,26 @@ #include <fm_eth.h> #include "t4rdb.h" +#include "cpld.h" DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; + u8 sw; printf("Board: %sRDB, ", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver)); + + sw = CPLD_READ(vbank); + sw = sw & CPLD_BANK_SEL_MASK; + + if (sw <= 7) + printf("vBank: %d\n", sw); + else + printf("Unsupported Bank=%x\n", sw); puts("SERDES Reference Clocks:\n"); printf(" SERDES1=100MHz SERDES2=156.25MHz\n" @@ -76,7 +88,7 @@ int misc_init_r(void) return 0; } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -99,6 +111,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); fdt_fixup_board_enet(blob); #endif + + return 0; } /* diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index 4b50bcd..474301e 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -106,6 +106,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/galaxy5200/galaxy5200.c b/board/galaxy5200/galaxy5200.c index 29e40eb..5d957b7 100644 --- a/board/galaxy5200/galaxy5200.c +++ b/board/galaxy5200/galaxy5200.c @@ -146,9 +146,11 @@ int checkboard(void) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t * bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/gateworks/gw_ventana/clocks.cfg b/board/gateworks/gw_ventana/clocks.cfg deleted file mode 100644 index a8118a2..0000000 --- a/board/gateworks/gw_ventana/clocks.cfg +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 Gateworks Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ -DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index df491a8..bb08cd2 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1483,7 +1483,7 @@ int misc_init_r(void) * - board (full model from EEPROM) * - peripherals removed from DTB if not loaded on board (per EEPROM config) */ -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { struct ventana_board_info *info = &ventana_info; struct ventana_eeprom_config *cfg; @@ -1495,7 +1495,7 @@ void ft_board_setup(void *blob, bd_t *bd) if (getenv("fdt_noauto")) { puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); - return; + return 0; } /* Update partition nodes using info from mtdparts env var */ @@ -1504,7 +1504,7 @@ void ft_board_setup(void *blob, bd_t *bd) if (!model) { puts("invalid board info: Leaving FDT fully enabled\n"); - return; + return 0; } printf(" Adjusting FDT per EEPROM for %s...\n", model); @@ -1523,7 +1523,7 @@ void ft_board_setup(void *blob, bd_t *bd) */ if (getenv("fdt_noconfig")) { puts(" Skiping periperhal config (fdt_noconfig defined)\n"); - return; + return 0; } cfg = econfig; while (cfg->name) { @@ -1533,6 +1533,8 @@ void ft_board_setup(void *blob, bd_t *bd) } cfg++; } + + return 0; } #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/gateworks/gw_ventana/gw_ventana.cfg b/board/gateworks/gw_ventana/gw_ventana.cfg deleted file mode 100644 index 9ab95f5..0000000 --- a/board/gateworks/gw_ventana/gw_ventana.cfg +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2013 Gateworks Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd, nand, sata - */ -#ifdef CONFIG_SPI_FLASH -BOOT_FROM spi -#else -BOOT_FROM nand -#endif - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" -#include "clocks.cfg" diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index ca35b3c..d6a5847 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -8,6 +8,7 @@ #include <common.h> #include <i2c.h> #include <asm/io.h> +#include <asm/arch/crm_regs.h> #include <asm/arch/iomux.h> #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> @@ -392,6 +393,30 @@ static void spl_dram_init(int width, int size_mb, int board_model) mx6_dram_cfg(&sysinfo, calib, mem); } +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + /* * called from C runtime startup code (arch/arm/lib/crt0.S:_main) * - we have a stack and a place to store GD, both in SRAM @@ -405,6 +430,9 @@ void board_init_f(ulong dummy) /* setup AIPS and disable watchdog */ arch_cpu_init(); + ccgr_init(); + gpr_init(); + /* iomux and setup of i2c */ board_early_init_f(); i2c_setup_iomux(); diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c index 1bac970..3a51d86 100644 --- a/board/gdsys/405ep/iocon.c +++ b/board/gdsys/405ep/iocon.c @@ -17,6 +17,7 @@ #include "../common/osd.h" #include "../common/mclink.h" +#include "../common/phy.h" #include <i2c.h> #include <pca953x.h> @@ -98,8 +99,6 @@ enum { unsigned int mclink_fpgacount; struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; -static int setup_88e1518(const char *bus, unsigned char addr); - int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) { int res; @@ -180,11 +179,11 @@ static void print_fpga_info(unsigned int fpga, bool rgmii2_present) unsigned feature_carriers; unsigned feature_video_channels; - int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; + int legacy = get_fpga_state(fpga) & FPGA_STATE_PLATFORM; - FPGA_GET_REG(0, versions, &versions); - FPGA_GET_REG(0, fpga_version, &fpga_version); - FPGA_GET_REG(0, fpga_features, &fpga_features); + FPGA_GET_REG(fpga, versions, &versions); + FPGA_GET_REG(fpga, fpga_version, &fpga_version); + FPGA_GET_REG(fpga, fpga_features, &fpga_features); unit_type = (versions & 0xf000) >> 12; feature_compression = (fpga_features & 0xe000) >> 13; @@ -369,10 +368,11 @@ int last_stage_init(void) unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 }; int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; u16 fpga_features; - int feature_carrier_speed = fpga_features & (1<<4); + int feature_carrier_speed; bool ch0_rgmii2_present = false; FPGA_GET_REG(0, fpga_features, &fpga_features); + feature_carrier_speed = fpga_features & (1<<4); if (!legacy) { /* Turn on Parade DP501 */ @@ -646,190 +646,3 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / sizeof(bb_miiphy_buses[0]); - -enum { - MIICMD_SET, - MIICMD_MODIFY, - MIICMD_VERIFY_VALUE, - MIICMD_WAIT_FOR_VALUE, -}; - -struct mii_setupcmd { - u8 token; - u8 reg; - u16 data; - u16 mask; - u32 timeout; -}; - -/* - * verify we are talking to a 88e1518 - */ -struct mii_setupcmd verify_88e1518[] = { - { MIICMD_SET, 22, 0x0000 }, - { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff }, - { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 }, -}; - -/* - * workaround for erratum mentioned in 88E1518 release notes - */ -struct mii_setupcmd fixup_88e1518[] = { - { MIICMD_SET, 22, 0x00ff }, - { MIICMD_SET, 17, 0x214b }, - { MIICMD_SET, 16, 0x2144 }, - { MIICMD_SET, 17, 0x0c28 }, - { MIICMD_SET, 16, 0x2146 }, - { MIICMD_SET, 17, 0xb233 }, - { MIICMD_SET, 16, 0x214d }, - { MIICMD_SET, 17, 0xcc0c }, - { MIICMD_SET, 16, 0x2159 }, - { MIICMD_SET, 22, 0x00fb }, - { MIICMD_SET, 7, 0xc00d }, - { MIICMD_SET, 22, 0x0000 }, -}; - -/* - * default initialization: - * - set RGMII receive timing to "receive clock transition when data stable" - * - set RGMII transmit timing to "transmit clock internally delayed" - * - set RGMII output impedance target to 78,8 Ohm - * - run output impedance calibration - * - set autonegotiation advertise to 1000FD only - */ -struct mii_setupcmd default_88e1518[] = { - { MIICMD_SET, 22, 0x0002 }, - { MIICMD_MODIFY, 21, 0x0030, 0x0030 }, - { MIICMD_MODIFY, 25, 0x0000, 0x0003 }, - { MIICMD_MODIFY, 24, 0x8000, 0x8000 }, - { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 }, - { MIICMD_SET, 22, 0x0000 }, - { MIICMD_MODIFY, 4, 0x0000, 0x01e0 }, - { MIICMD_MODIFY, 9, 0x0200, 0x0300 }, -}; - -/* - * turn off CLK125 for PHY daughterboard - */ -struct mii_setupcmd ch1fix_88e1518[] = { - { MIICMD_SET, 22, 0x0002 }, - { MIICMD_MODIFY, 16, 0x0006, 0x0006 }, - { MIICMD_SET, 22, 0x0000 }, -}; - -/* - * perform copper software reset - */ -struct mii_setupcmd swreset_88e1518[] = { - { MIICMD_SET, 22, 0x0000 }, - { MIICMD_MODIFY, 0, 0x8000, 0x8000 }, - { MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 }, -}; - -static int process_setupcmd(const char *bus, unsigned char addr, - struct mii_setupcmd *setupcmd) -{ - int res; - u8 reg = setupcmd->reg; - u16 data = setupcmd->data; - u16 mask = setupcmd->mask; - u32 timeout = setupcmd->timeout; - u16 orig_data; - unsigned long start; - - debug("mii %s:%u reg %2u ", bus, addr, reg); - - switch (setupcmd->token) { - case MIICMD_MODIFY: - res = miiphy_read(bus, addr, reg, &orig_data); - if (res) - break; - debug("is %04x. (value %04x mask %04x) ", orig_data, data, - mask); - data = (orig_data & ~mask) | (data & mask); - case MIICMD_SET: - debug("=> %04x\n", data); - res = miiphy_write(bus, addr, reg, data); - break; - case MIICMD_VERIFY_VALUE: - res = miiphy_read(bus, addr, reg, &orig_data); - if (res) - break; - if ((orig_data & mask) != (data & mask)) - res = -1; - debug("(value %04x mask %04x) == %04x? %s\n", data, mask, - orig_data, res ? "FAIL" : "PASS"); - break; - case MIICMD_WAIT_FOR_VALUE: - res = -1; - start = get_timer(0); - while ((res != 0) && (get_timer(start) < timeout)) { - res = miiphy_read(bus, addr, reg, &orig_data); - if (res) - continue; - if ((orig_data & mask) != (data & mask)) - res = -1; - } - debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data, - mask, orig_data, res ? "FAIL" : "PASS", - get_timer(start)); - break; - default: - res = -1; - break; - } - - return res; -} - -static int process_setup(const char *bus, unsigned char addr, - struct mii_setupcmd *setupcmd, unsigned int count) -{ - int res = 0; - unsigned int k; - - for (k = 0; k < count; ++k) { - res = process_setupcmd(bus, addr, &setupcmd[k]); - if (res) { - printf("mii cmd %u on bus %s addr %u failed, aborting setup", - setupcmd[k].token, bus, addr); - break; - } - } - - return res; -} - -static int setup_88e1518(const char *bus, unsigned char addr) -{ - int res; - - res = process_setup(bus, addr, - verify_88e1518, ARRAY_SIZE(verify_88e1518)); - if (res) - return res; - - res = process_setup(bus, addr, - fixup_88e1518, ARRAY_SIZE(fixup_88e1518)); - if (res) - return res; - - res = process_setup(bus, addr, - default_88e1518, ARRAY_SIZE(default_88e1518)); - if (res) - return res; - - if (addr) { - res = process_setup(bus, addr, - ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518)); - if (res) - return res; - } - - res = process_setup(bus, addr, - swreset_88e1518, ARRAY_SIZE(swreset_88e1518)); - if (res) - return res; - - return 0; -} diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 7f8b427..4957943 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -6,8 +6,10 @@ # obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o +obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o obj-$(CONFIG_IO) += miiphybb.o obj-$(CONFIG_IO64) += miiphybb.o -obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o +obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o obj-$(CONFIG_DLVISION_10G) += osd.o obj-$(CONFIG_CONTROLCENTERD) += dp501.o +obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o diff --git a/board/gdsys/common/cmd_ioloop.c b/board/gdsys/common/cmd_ioloop.c new file mode 100644 index 0000000..e0c74fe --- /dev/null +++ b/board/gdsys/common/cmd_ioloop.c @@ -0,0 +1,295 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> + +#include <gdsys_fpga.h> + +enum { + STATE_TX_PACKET_BUILDING = 1<<0, + STATE_TX_TRANSMITTING = 1<<1, + STATE_TX_BUFFER_FULL = 1<<2, + STATE_TX_ERR = 1<<3, + STATE_RECEIVE_TIMEOUT = 1<<4, + STATE_PROC_RX_STORE_TIMEOUT = 1<<5, + STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6, + STATE_RX_DIST_ERR = 1<<7, + STATE_RX_LENGTH_ERR = 1<<8, + STATE_RX_FRAME_CTR_ERR = 1<<9, + STATE_RX_FCS_ERR = 1<<10, + STATE_RX_PACKET_DROPPED = 1<<11, + STATE_RX_DATA_LAST = 1<<12, + STATE_RX_DATA_FIRST = 1<<13, + STATE_RX_DATA_AVAILABLE = 1<<15, +}; + +enum { + CTRL_PROC_RECEIVE_ENABLE = 1<<12, + CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15, +}; + +enum { + IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5, + IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6, + IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7, + IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8, +}; + +struct io_generic_packet { + u16 target_address; + u16 source_address; + u8 packet_type; + u8 bc; + u16 packet_length; +} __attribute__((__packed__)); + +unsigned long long rx_ctr; +unsigned long long tx_ctr; +unsigned long long err_ctr; + +static void io_check_status(unsigned int fpga, u16 status, bool silent) +{ + u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR | + STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR | + STATE_RX_PACKET_DROPPED | STATE_TX_ERR; + + if (!(status & mask)) { + FPGA_SET_REG(fpga, ep.rx_tx_status, status); + return; + } + + err_ctr++; + FPGA_SET_REG(fpga, ep.rx_tx_status, status); + + if (silent) + return; + + if (status & STATE_RX_PACKET_DROPPED) + printf("RX_PACKET_DROPPED, status %04x\n", status); + + if (status & STATE_RX_DIST_ERR) + printf("RX_DIST_ERR\n"); + if (status & STATE_RX_LENGTH_ERR) + printf("RX_LENGTH_ERR\n"); + if (status & STATE_RX_FRAME_CTR_ERR) + printf("RX_FRAME_CTR_ERR\n"); + if (status & STATE_RX_FCS_ERR) + printf("RX_FCS_ERR\n"); + + if (status & STATE_TX_ERR) + printf("TX_ERR\n"); +} + +static void io_send(unsigned int fpga, unsigned int size) +{ + unsigned int k; + struct io_generic_packet packet = { + .source_address = 1, + .packet_type = 1, + .packet_length = size, + }; + u16 *p = (u16 *)&packet; + + for (k = 0; k < sizeof(packet) / 2; ++k) + FPGA_SET_REG(fpga, ep.transmit_data, *p++); + + for (k = 0; k < (size + 1) / 2; ++k) + FPGA_SET_REG(fpga, ep.transmit_data, k); + + FPGA_SET_REG(fpga, ep.rx_tx_control, + CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER); + + tx_ctr++; +} + +static void io_receive(unsigned int fpga) +{ + unsigned int k = 0; + u16 rx_tx_status; + + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); + + while (rx_tx_status & STATE_RX_DATA_AVAILABLE) { + u16 rx; + + if (rx_tx_status & STATE_RX_DATA_LAST) + rx_ctr++; + + FPGA_GET_REG(fpga, ep.receive_data, &rx); + + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); + + ++k; + } +} + +static void io_reflect(unsigned int fpga) +{ + u16 buffer[128]; + + unsigned int k = 0; + unsigned int n; + u16 rx_tx_status; + + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); + + while (rx_tx_status & STATE_RX_DATA_AVAILABLE) { + FPGA_GET_REG(fpga, ep.receive_data, &buffer[k++]); + if (rx_tx_status & STATE_RX_DATA_LAST) + break; + + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); + } + + if (!k) + return; + + for (n = 0; n < k; ++n) + FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]); + + FPGA_SET_REG(fpga, ep.rx_tx_control, + CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER); + + tx_ctr++; +} + +/* + * FPGA io-endpoint reflector + * + * Syntax: + * ioreflect {fpga} {reportrate} + */ +int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int fpga; + unsigned int rate = 0; + unsigned long long last_seen = 0; + + if (argc < 2) + return CMD_RET_USAGE; + + fpga = simple_strtoul(argv[1], NULL, 10); + + /* + * If another parameter, it is the report rate in packets. + */ + if (argc > 2) + rate = simple_strtoul(argv[2], NULL, 10); + + /* enable receive path */ + FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE); + + /* set device address to dummy 1*/ + FPGA_SET_REG(fpga, ep.device_address, 1); + + rx_ctr = 0; tx_ctr = 0; err_ctr = 0; + + while (1) { + u16 top_int; + u16 rx_tx_status; + + FPGA_GET_REG(fpga, top_interrupt, &top_int); + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); + + io_check_status(fpga, rx_tx_status, true); + if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) && + (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)) + io_reflect(fpga); + + if (rate) { + if (!(tx_ctr % rate) && (tx_ctr != last_seen)) + printf("refl %llu, err %llu\n", tx_ctr, + err_ctr); + last_seen = tx_ctr; + } + + if (ctrlc()) + break; + } + + return 0; +} + +/* + * FPGA io-endpoint looptest + * + * Syntax: + * ioloop {fpga} {size} {rate} + */ +#define DISP_LINE_LEN 16 +int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int fpga; + unsigned int size; + unsigned int rate = 0; + + if (argc < 3) + return CMD_RET_USAGE; + + /* + * FPGA is specified since argc > 2 + */ + fpga = simple_strtoul(argv[1], NULL, 10); + + /* + * packet size is specified since argc > 2 + */ + size = simple_strtoul(argv[2], NULL, 10); + + /* + * If another parameter, it is the test rate in packets per second. + */ + if (argc > 3) + rate = simple_strtoul(argv[3], NULL, 10); + + /* enable receive path */ + FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE); + + /* set device address to dummy 1*/ + FPGA_SET_REG(fpga, ep.device_address, 1); + + rx_ctr = 0; tx_ctr = 0; err_ctr = 0; + + while (1) { + u16 top_int; + u16 rx_tx_status; + + FPGA_GET_REG(fpga, top_interrupt, &top_int); + FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); + + io_check_status(fpga, rx_tx_status, false); + if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS) + io_send(fpga, size); + if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) + io_receive(fpga); + + if (rate) { + if (ctrlc()) + break; + udelay(1000000 / rate); + if (!(tx_ctr % rate)) + printf("d %lld, tx %llu, rx %llu, err %llu\n", + tx_ctr - rx_ctr, tx_ctr, rx_ctr, + err_ctr); + } + } + + return 0; +} + +U_BOOT_CMD( + ioloop, 4, 0, do_ioloop, + "fpga io-endpoint looptest", + "fpga packetsize [packets/sec]" +); + +U_BOOT_CMD( + ioreflect, 3, 0, do_ioreflect, + "fpga io-endpoint reflector", + "fpga reportrate" +); diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c new file mode 100644 index 0000000..1d6eb7b --- /dev/null +++ b/board/gdsys/common/ihs_mdio.c @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#include <gdsys_fpga.h> +#include <miiphy.h> + +#include "ihs_mdio.h" + +static int ihs_mdio_idle(struct mii_dev *bus) +{ + struct ihs_mdio_info *info = bus->priv; + u16 val; + unsigned int ctr = 0; + + do { + FPGA_GET_REG(info->fpga, mdio.control, &val); + udelay(100); + if (ctr++ > 10) + return -1; + } while (!(val & (1 << 12))); + + return 0; +} + +static int ihs_mdio_reset(struct mii_dev *bus) +{ + ihs_mdio_idle(bus); + + return 0; +} + +static int ihs_mdio_read(struct mii_dev *bus, int addr, int dev_addr, + int regnum) +{ + struct ihs_mdio_info *info = bus->priv; + u16 val; + + ihs_mdio_idle(bus); + + FPGA_SET_REG(info->fpga, mdio.control, + ((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10)); + + /* wait for rx data available */ + udelay(100); + + FPGA_GET_REG(info->fpga, mdio.rx_data, &val); + + return val; +} + +static int ihs_mdio_write(struct mii_dev *bus, int addr, int dev_addr, + int regnum, u16 value) +{ + struct ihs_mdio_info *info = bus->priv; + + ihs_mdio_idle(bus); + + FPGA_SET_REG(info->fpga, mdio.address_data, value); + FPGA_SET_REG(info->fpga, mdio.control, + ((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10)); + + return 0; +} + +int ihs_mdio_init(struct ihs_mdio_info *info) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate FSL MDIO bus\n"); + return -1; + } + + bus->read = ihs_mdio_read; + bus->write = ihs_mdio_write; + bus->reset = ihs_mdio_reset; + sprintf(bus->name, info->name); + + bus->priv = info; + + return mdio_register(bus); +} diff --git a/board/gdsys/common/ihs_mdio.h b/board/gdsys/common/ihs_mdio.h new file mode 100644 index 0000000..64b4049 --- /dev/null +++ b/board/gdsys/common/ihs_mdio.h @@ -0,0 +1,18 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IHS_MDIO_H_ +#define _IHS_MDIO_H_ + +struct ihs_mdio_info { + u32 fpga; + char *name; +}; + +int ihs_mdio_init(struct ihs_mdio_info *info); + +#endif diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index 1c765e4..55ecdf1 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -289,7 +289,6 @@ int osd_probe(unsigned screen) { u16 version; u16 features; - u8 value; int old_bus = i2c_get_bus_num(); bool pixclock_present = false; bool output_driver_present = false; @@ -330,7 +329,8 @@ int osd_probe(unsigned screen) #ifdef CONFIG_SYS_CH7301_I2C i2c_set_bus_num(ch7301_i2c[screen]); if (!i2c_probe(CH7301_I2C_ADDR)) { - value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); + u8 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); + if (value == 0x17) { i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); @@ -345,8 +345,7 @@ int osd_probe(unsigned screen) #ifdef CONFIG_SYS_SIL1178_I2C i2c_set_bus_num(sil1178_i2c[screen]); if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) { - value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02); - if (value == 0x06) { + if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02) == 0x06) { /* * magic initialization sequence, * adapted from datasheet diff --git a/board/gdsys/common/phy.c b/board/gdsys/common/phy.c new file mode 100644 index 0000000..fb92658 --- /dev/null +++ b/board/gdsys/common/phy.c @@ -0,0 +1,280 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#include <miiphy.h> + +enum { + MIICMD_SET, + MIICMD_MODIFY, + MIICMD_VERIFY_VALUE, + MIICMD_WAIT_FOR_VALUE, +}; + +struct mii_setupcmd { + u8 token; + u8 reg; + u16 data; + u16 mask; + u32 timeout; +}; + +/* + * verify we are talking to a 88e1518 + */ +struct mii_setupcmd verify_88e1518[] = { + { MIICMD_SET, 22, 0x0000 }, + { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff }, + { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 }, +}; + +/* + * workaround for erratum mentioned in 88E1518 release notes + */ +struct mii_setupcmd fixup_88e1518[] = { + { MIICMD_SET, 22, 0x00ff }, + { MIICMD_SET, 17, 0x214b }, + { MIICMD_SET, 16, 0x2144 }, + { MIICMD_SET, 17, 0x0c28 }, + { MIICMD_SET, 16, 0x2146 }, + { MIICMD_SET, 17, 0xb233 }, + { MIICMD_SET, 16, 0x214d }, + { MIICMD_SET, 17, 0xcc0c }, + { MIICMD_SET, 16, 0x2159 }, + { MIICMD_SET, 22, 0x00fb }, + { MIICMD_SET, 7, 0xc00d }, + { MIICMD_SET, 22, 0x0000 }, +}; + +/* + * default initialization: + * - set RGMII receive timing to "receive clock transition when data stable" + * - set RGMII transmit timing to "transmit clock internally delayed" + * - set RGMII output impedance target to 78,8 Ohm + * - run output impedance calibration + * - set autonegotiation advertise to 1000FD only + */ +struct mii_setupcmd default_88e1518[] = { + { MIICMD_SET, 22, 0x0002 }, + { MIICMD_MODIFY, 21, 0x0030, 0x0030 }, + { MIICMD_MODIFY, 25, 0x0000, 0x0003 }, + { MIICMD_MODIFY, 24, 0x8000, 0x8000 }, + { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 }, + { MIICMD_SET, 22, 0x0000 }, + { MIICMD_MODIFY, 4, 0x0000, 0x01e0 }, + { MIICMD_MODIFY, 9, 0x0200, 0x0300 }, +}; + +/* + * turn off CLK125 for PHY daughterboard + */ +struct mii_setupcmd ch1fix_88e1518[] = { + { MIICMD_SET, 22, 0x0002 }, + { MIICMD_MODIFY, 16, 0x0006, 0x0006 }, + { MIICMD_SET, 22, 0x0000 }, +}; + +/* + * perform copper software reset + */ +struct mii_setupcmd swreset_88e1518[] = { + { MIICMD_SET, 22, 0x0000 }, + { MIICMD_MODIFY, 0, 0x8000, 0x8000 }, + { MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 }, +}; + +/* + * special one for 88E1514: + * Force SGMII to Copper mode + */ +struct mii_setupcmd mii_to_copper_88e1514[] = { + { MIICMD_SET, 22, 0x0012 }, + { MIICMD_MODIFY, 20, 0x0001, 0x0007 }, + { MIICMD_MODIFY, 20, 0x8000, 0x8000 }, + { MIICMD_SET, 22, 0x0000 }, +}; + +/* + * turn off SGMII auto-negotiation + */ +struct mii_setupcmd sgmii_autoneg_off_88e1518[] = { + { MIICMD_SET, 22, 0x0001 }, + { MIICMD_MODIFY, 0, 0x0000, 0x1000 }, + { MIICMD_MODIFY, 0, 0x8000, 0x8000 }, + { MIICMD_SET, 22, 0x0000 }, +}; + +/* + * invert LED2 polarity + */ +struct mii_setupcmd invert_led2_88e1514[] = { + { MIICMD_SET, 22, 0x0003 }, + { MIICMD_MODIFY, 17, 0x0030, 0x0010 }, + { MIICMD_SET, 22, 0x0000 }, +}; + +static int process_setupcmd(const char *bus, unsigned char addr, + struct mii_setupcmd *setupcmd) +{ + int res; + u8 reg = setupcmd->reg; + u16 data = setupcmd->data; + u16 mask = setupcmd->mask; + u32 timeout = setupcmd->timeout; + u16 orig_data; + unsigned long start; + + debug("mii %s:%u reg %2u ", bus, addr, reg); + + switch (setupcmd->token) { + case MIICMD_MODIFY: + res = miiphy_read(bus, addr, reg, &orig_data); + if (res) + break; + debug("is %04x. (value %04x mask %04x) ", orig_data, data, + mask); + data = (orig_data & ~mask) | (data & mask); + /* fallthrough */ + case MIICMD_SET: + debug("=> %04x\n", data); + res = miiphy_write(bus, addr, reg, data); + break; + case MIICMD_VERIFY_VALUE: + res = miiphy_read(bus, addr, reg, &orig_data); + if (res) + break; + if ((orig_data & mask) != (data & mask)) + res = -1; + debug("(value %04x mask %04x) == %04x? %s\n", data, mask, + orig_data, res ? "FAIL" : "PASS"); + break; + case MIICMD_WAIT_FOR_VALUE: + res = -1; + start = get_timer(0); + while ((res != 0) && (get_timer(start) < timeout)) { + res = miiphy_read(bus, addr, reg, &orig_data); + if (res) + continue; + if ((orig_data & mask) != (data & mask)) + res = -1; + } + debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data, + mask, orig_data, res ? "FAIL" : "PASS", + get_timer(start)); + break; + default: + res = -1; + break; + } + + return res; +} + +static int process_setup(const char *bus, unsigned char addr, + struct mii_setupcmd *setupcmd, unsigned int count) +{ + int res = 0; + unsigned int k; + + for (k = 0; k < count; ++k) { + res = process_setupcmd(bus, addr, &setupcmd[k]); + if (res) { + printf("mii cmd %u on bus %s addr %u failed, aborting setup\n", + setupcmd[k].token, bus, addr); + break; + } + } + + return res; +} + +int setup_88e1518(const char *bus, unsigned char addr) +{ + int res; + + res = process_setup(bus, addr, + verify_88e1518, ARRAY_SIZE(verify_88e1518)); + if (res) + return res; + + res = process_setup(bus, addr, + fixup_88e1518, ARRAY_SIZE(fixup_88e1518)); + if (res) + return res; + + res = process_setup(bus, addr, + default_88e1518, ARRAY_SIZE(default_88e1518)); + if (res) + return res; + + if (addr) { + res = process_setup(bus, addr, + ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518)); + if (res) + return res; + } + + res = process_setup(bus, addr, + swreset_88e1518, ARRAY_SIZE(swreset_88e1518)); + if (res) + return res; + + return 0; +} + +int setup_88e1514(const char *bus, unsigned char addr) +{ + int res; + + res = process_setup(bus, addr, + verify_88e1518, ARRAY_SIZE(verify_88e1518)); + if (res) + return res; + + res = process_setup(bus, addr, + fixup_88e1518, ARRAY_SIZE(fixup_88e1518)); + if (res) + return res; + + res = process_setup(bus, addr, + mii_to_copper_88e1514, + ARRAY_SIZE(mii_to_copper_88e1514)); + if (res) + return res; + + res = process_setup(bus, addr, + sgmii_autoneg_off_88e1518, + ARRAY_SIZE(sgmii_autoneg_off_88e1518)); + if (res) + return res; + + res = process_setup(bus, addr, + invert_led2_88e1514, + ARRAY_SIZE(invert_led2_88e1514)); + if (res) + return res; + + res = process_setup(bus, addr, + default_88e1518, ARRAY_SIZE(default_88e1518)); + if (res) + return res; + + if (addr) { + res = process_setup(bus, addr, + ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518)); + if (res) + return res; + } + + res = process_setup(bus, addr, + swreset_88e1518, ARRAY_SIZE(swreset_88e1518)); + if (res) + return res; + + return 0; +} diff --git a/board/gdsys/common/phy.h b/board/gdsys/common/phy.h new file mode 100644 index 0000000..afbdc65 --- /dev/null +++ b/board/gdsys/common/phy.h @@ -0,0 +1,14 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PHY_H_ +#define _PHY_H_ + +int setup_88e1514(const char *bus, unsigned char addr); +int setup_88e1518(const char *bus, unsigned char addr); + +#endif diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c index ee6f9e0..8d01d8b 100644 --- a/board/gdsys/intip/intip.c +++ b/board/gdsys/intip/intip.c @@ -206,7 +206,7 @@ int misc_init_r(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) extern void __ft_board_setup(void *blob, bd_t *bd); -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { __ft_board_setup(blob, bd); @@ -215,5 +215,7 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", "disabled", sizeof("disabled"), 1); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig new file mode 100644 index 0000000..43e1663 --- /dev/null +++ b/board/gdsys/mpc8308/Kconfig @@ -0,0 +1,12 @@ +if TARGET_HRCON + +config SYS_BOARD + default "mpc8308" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "hrcon" + +endif diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS new file mode 100644 index 0000000..a7853a5 --- /dev/null +++ b/board/gdsys/mpc8308/MAINTAINERS @@ -0,0 +1,6 @@ +MPC8308 BOARD +M: Dirk Eibach <eibach@gdsys.de> +S: Maintained +F: board/gdsys/mpc8308/ +F: include/configs/hrcon.h +F: configs/hrcon_defconfig diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile new file mode 100644 index 0000000..b5dfdbb --- /dev/null +++ b/board/gdsys/mpc8308/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 +# Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mpc8308.o sdram.o +obj-$(CONFIG_HRCON) += hrcon.o diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c new file mode 100644 index 0000000..e4434b3 --- /dev/null +++ b/board/gdsys/mpc8308/hrcon.c @@ -0,0 +1,677 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <hwconfig.h> +#include <i2c.h> +#include <spi.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <pci.h> +#include <mpc83xx.h> +#include <fsl_esdhc.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_mpc83xx_serdes.h> + +#include "mpc8308.h" + +#include <gdsys_fpga.h> + +#include "../common/osd.h" +#include "../common/mclink.h" +#include "../common/phy.h" + +#include <pca953x.h> +#include <pca9698.h> + +#include <miiphy.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MAX_MUX_CHANNELS 2 + +enum { + UNITTYPE_MAIN_SERVER = 0, + UNITTYPE_MAIN_USER = 1, + UNITTYPE_VIDEO_SERVER = 2, + UNITTYPE_VIDEO_USER = 3, +}; + +enum { + UNITTYPEPCB_DVI = 0, + UNITTYPEPCB_DP_165 = 1, + UNITTYPEPCB_DP_300 = 2, + UNITTYPEPCB_HDMI = 3, +}; + +enum { + HWVER_100 = 0, + HWVER_110 = 1, +}; + +enum { + FPGA_HWVER_200 = 0, + FPGA_HWVER_210 = 1, +}; + +enum { + COMPRESSION_NONE = 0, + COMPRESSION_TYPE1_DELTA = 1, + COMPRESSION_TYPE1_TYPE2_DELTA = 3, +}; + +enum { + AUDIO_NONE = 0, + AUDIO_TX = 1, + AUDIO_RX = 2, + AUDIO_RXTX = 3, +}; + +enum { + SYSCLK_147456 = 0, +}; + +enum { + RAM_DDR2_32 = 0, + RAM_DDR3_32 = 1, +}; + +enum { + CARRIER_SPEED_1G = 0, + CARRIER_SPEED_2_5G = 1, +}; + +enum { + MCFPGA_DONE = 1 << 0, + MCFPGA_INIT_N = 1 << 1, + MCFPGA_PROGRAM_N = 1 << 2, + MCFPGA_UPDATE_ENABLE_N = 1 << 3, + MCFPGA_RESET_N = 1 << 4, +}; + +enum { + GPIO_MDC = 1 << 14, + GPIO_MDIO = 1 << 15, +}; + +unsigned int mclink_fpgacount; +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; + +int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) +{ + int res; + + switch (fpga) { + case 0: + out_le16(reg, data); + break; + default: + res = mclink_send(fpga - 1, regoff, data); + if (res < 0) { + printf("mclink_send reg %02lx data %04x returned %d\n", + regoff, data, res); + return res; + } + break; + } + + return 0; +} + +int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) +{ + int res; + + switch (fpga) { + case 0: + *data = in_le16(reg); + break; + default: + if (fpga > mclink_fpgacount) + return -EINVAL; + res = mclink_receive(fpga - 1, regoff, data); + if (res < 0) { + printf("mclink_receive reg %02lx returned %d\n", + regoff, res); + return res; + } + } + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + bool hw_type_cat = pca9698_get_value(0x20, 20); + + puts("Board: "); + + printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + + puts("\n"); + + return 0; +} + +static void print_fpga_info(unsigned int fpga, bool rgmii2_present) +{ + u16 versions; + u16 fpga_version; + u16 fpga_features; + unsigned unit_type; + unsigned unit_type_pcb_video; + unsigned hardware_version; + unsigned feature_compression; + unsigned feature_osd; + unsigned feature_audio; + unsigned feature_sysclock; + unsigned feature_ramconfig; + unsigned feature_carrier_speed; + unsigned feature_carriers; + unsigned feature_video_channels; + + FPGA_GET_REG(fpga, versions, &versions); + FPGA_GET_REG(fpga, fpga_version, &fpga_version); + FPGA_GET_REG(fpga, fpga_features, &fpga_features); + + unit_type = (versions & 0xf000) >> 12; + unit_type_pcb_video = (versions & 0x01c0) >> 6; + feature_compression = (fpga_features & 0xe000) >> 13; + feature_osd = fpga_features & (1<<11); + feature_audio = (fpga_features & 0x0600) >> 9; + feature_sysclock = (fpga_features & 0x0180) >> 7; + feature_ramconfig = (fpga_features & 0x0060) >> 5; + feature_carrier_speed = fpga_features & (1<<4); + feature_carriers = (fpga_features & 0x000c) >> 2; + feature_video_channels = fpga_features & 0x0003; + + switch (unit_type) { + case UNITTYPE_MAIN_USER: + printf("Mainchannel"); + break; + + case UNITTYPE_VIDEO_USER: + printf("Videochannel"); + break; + + default: + printf("UnitType %d(not supported)", unit_type); + break; + } + + if (unit_type == UNITTYPE_MAIN_USER) { + hardware_version = + (!!pca9698_get_value(0x20, 24) << 0) + | (!!pca9698_get_value(0x20, 25) << 1) + | (!!pca9698_get_value(0x20, 26) << 2) + | (!!pca9698_get_value(0x20, 27) << 3) + | (!!pca9698_get_value(0x20, 28) << 4); + switch (hardware_version) { + case HWVER_100: + printf(" HW-Ver 1.00,"); + break; + + case HWVER_110: + printf(" HW-Ver 1.10,"); + break; + + default: + printf(" HW-Ver %d(not supported),", + hardware_version); + break; + } + if (rgmii2_present) + printf(" RGMII2,"); + } + + if (unit_type == UNITTYPE_VIDEO_USER) { + hardware_version = versions & 0x000f; + switch (hardware_version) { + case FPGA_HWVER_200: + printf(" HW-Ver 2.00,"); + break; + + case FPGA_HWVER_210: + printf(" HW-Ver 2.10,"); + break; + + default: + printf(" HW-Ver %d(not supported),", + hardware_version); + break; + } + } + + switch (unit_type_pcb_video) { + case UNITTYPEPCB_DVI: + printf(" DVI,"); + break; + + case UNITTYPEPCB_DP_165: + printf(" DP 165MPix/s,"); + break; + + case UNITTYPEPCB_DP_300: + printf(" DP 300MPix/s,"); + break; + + case UNITTYPEPCB_HDMI: + printf(" HDMI,"); + break; + } + + printf(" FPGA V %d.%02d\n features:", + fpga_version / 100, fpga_version % 100); + + + switch (feature_compression) { + case COMPRESSION_NONE: + printf(" no compression"); + break; + + case COMPRESSION_TYPE1_DELTA: + printf(" type1-deltacompression"); + break; + + case COMPRESSION_TYPE1_TYPE2_DELTA: + printf(" type1-deltacompression, type2-inlinecompression"); + break; + + default: + printf(" compression %d(not supported)", feature_compression); + break; + } + + printf(", %sosd", feature_osd ? "" : "no "); + + switch (feature_audio) { + case AUDIO_NONE: + printf(", no audio"); + break; + + case AUDIO_TX: + printf(", audio tx"); + break; + + case AUDIO_RX: + printf(", audio rx"); + break; + + case AUDIO_RXTX: + printf(", audio rx+tx"); + break; + + default: + printf(", audio %d(not supported)", feature_audio); + break; + } + + puts(",\n "); + + switch (feature_sysclock) { + case SYSCLK_147456: + printf("clock 147.456 MHz"); + break; + + default: + printf("clock %d(not supported)", feature_sysclock); + break; + } + + switch (feature_ramconfig) { + case RAM_DDR2_32: + printf(", RAM 32 bit DDR2"); + break; + + case RAM_DDR3_32: + printf(", RAM 32 bit DDR3"); + break; + + default: + printf(", RAM %d(not supported)", feature_ramconfig); + break; + } + + printf(", %d carrier(s) %s", feature_carriers, + feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); + + printf(", %d video channel(s)\n", feature_video_channels); +} + +int last_stage_init(void) +{ + int slaves; + unsigned int k; + unsigned int mux_ch; + unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 }; + u16 fpga_features; + bool hw_type_cat = pca9698_get_value(0x20, 20); + bool ch0_rgmii2_present = false; + + FPGA_GET_REG(0, fpga_features, &fpga_features); + + /* Turn on Parade DP501 */ + pca9698_direction_output(0x20, 10, 1); + + ch0_rgmii2_present = !pca9698_get_value(0x20, 30); + + /* wait for FPGA done */ + for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { + unsigned int ctr = 0; + + if (i2c_probe(mclink_controllers[k])) + continue; + + while (!(pca953x_get_val(mclink_controllers[k]) + & MCFPGA_DONE)) { + udelay(100000); + if (ctr++ > 5) { + printf("no done for mclink_controller %d\n", k); + break; + } + } + } + + if (hw_type_cat) { + miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, + bb_miiphy_write); + for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { + if ((mux_ch == 1) && !ch0_rgmii2_present) + continue; + + setup_88e1514(bb_miiphy_buses[0].name, mux_ch); + } + } + + /* give slave-PLLs and Parade DP501 some time to be up and running */ + udelay(500000); + + mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; + slaves = mclink_probe(); + mclink_fpgacount = 0; + + print_fpga_info(0, ch0_rgmii2_present); + osd_probe(0); + + if (slaves <= 0) + return 0; + + mclink_fpgacount = slaves; + + for (k = 1; k <= slaves; ++k) { + FPGA_GET_REG(k, fpga_features, &fpga_features); + + print_fpga_info(k, false); + osd_probe(k); + if (hw_type_cat) { + miiphy_register(bb_miiphy_buses[k].name, + bb_miiphy_read, bb_miiphy_write); + setup_88e1514(bb_miiphy_buses[k].name, 0); + } + } + + return 0; +} + +/* + * provide access to fpga gpios (for I2C bitbang) + * (these may look all too simple but make iocon.h much more readable) + */ +void fpga_gpio_set(unsigned int bus, int pin) +{ + FPGA_SET_REG(bus, gpio.set, pin); +} + +void fpga_gpio_clear(unsigned int bus, int pin) +{ + FPGA_SET_REG(bus, gpio.clear, pin); +} + +int fpga_gpio_get(unsigned int bus, int pin) +{ + u16 val; + + FPGA_GET_REG(bus, gpio.read, &val); + + return val & pin; +} + +void mpc8308_init(void) +{ + pca9698_direction_output(0x20, 4, 1); +} + +void mpc8308_set_fpga_reset(unsigned state) +{ + pca9698_set_value(0x20, 4, state ? 0 : 1); +} + +void mpc8308_setup_hw(void) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + /* + * set "startup-finished"-gpios + */ + setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); + setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); +} + +int mpc8308_get_fpga_done(unsigned fpga) +{ + return pca9698_get_value(0x20, 19); +} + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_init(bd_t *bd) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + sysconf83xx_t *sysconf = &immr->sysconf; + + /* Enable cache snooping in eSDHC system configuration register */ + out_be32(&sysconf->sdhccr, 0x02000000); + + return fsl_esdhc_mmc_init(bd); +} +#endif + +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +void pci_init_board(void) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + sysconf83xx_t *sysconf = &immr->sysconf; + law83xx_t *pcie_law = sysconf->pcielaw; + struct pci_region *pcie_reg[] = { pcie_regions_0 }; + + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(1, pcie_reg); +} + +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); + + return 0; +} +#endif + +/* + * FPGA MII bitbang implementation + */ + +struct fpga_mii { + unsigned fpga; + int mdio; +} fpga_mii[] = { + { 0, 1}, + { 1, 1}, + { 2, 1}, + { 3, 1}, +}; + +static int mii_dummy_init(struct bb_miiphy_bus *bus) +{ + return 0; +} + +static int mii_mdio_active(struct bb_miiphy_bus *bus) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (fpga_mii->mdio) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); + + return 0; +} + +static int mii_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct fpga_mii *fpga_mii = bus->priv; + + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + + return 0; +} + +static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (v) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); + + fpga_mii->mdio = v; + + return 0; +} + +static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + u16 gpio; + struct fpga_mii *fpga_mii = bus->priv; + + FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); + + *v = ((gpio & GPIO_MDIO) != 0); + + return 0; +} + +static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (v) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); + + return 0; +} + +static int mii_delay(struct bb_miiphy_bus *bus) +{ + udelay(1); + + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = "board0", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[0], + }, + { + .name = "board1", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[1], + }, + { + .name = "board2", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[2], + }, + { + .name = "board3", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[3], + }, +}; + +int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / + sizeof(bb_miiphy_buses[0]); diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c new file mode 100644 index 0000000..4338a33 --- /dev/null +++ b/board/gdsys/mpc8308/mpc8308.c @@ -0,0 +1,109 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/ppc4xx-gpio.h> +#include <asm/global_data.h> + +#include "mpc8308.h" +#include <gdsys_fpga.h> + +#define REFLECTION_TESTPATTERN 0xdede +#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) + +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI +#define REFLECTION_TESTREG reflection_low +#else +#define REFLECTION_TESTREG reflection_high +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int get_fpga_state(unsigned dev) +{ + return gd->arch.fpga_state[dev]; +} + +void print_fpga_state(unsigned dev) +{ + if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED) + puts(" Waiting for FPGA-DONE timed out.\n"); + if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) + puts(" FPGA reflection test failed.\n"); +} + +int board_early_init_f(void) +{ + unsigned k; + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->arch.fpga_state[k] = 0; + + return 0; +} + +int board_early_init_r(void) +{ + unsigned k; + unsigned ctr; + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->arch.fpga_state[k] = 0; + + /* + * reset FPGA + */ + mpc8308_init(); + + mpc8308_set_fpga_reset(1); + + mpc8308_setup_hw(); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + ctr = 0; + while (!mpc8308_get_fpga_done(k)) { + udelay(100000); + if (ctr++ > 5) { + gd->arch.fpga_state[k] |= + FPGA_STATE_DONE_FAILED; + break; + } + } + } + + udelay(10); + + mpc8308_set_fpga_reset(0); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + /* + * wait for fpga out of reset + */ + ctr = 0; + while (1) { + u16 val; + + FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); + + FPGA_GET_REG(k, REFLECTION_TESTREG, &val); + if (val == REFLECTION_TESTPATTERN_INV) + break; + + udelay(100000); + if (ctr++ > 5) { + gd->arch.fpga_state[k] |= + FPGA_STATE_REFLECTION_FAILED; + break; + } + } + } + + return 0; +} diff --git a/board/gdsys/mpc8308/mpc8308.h b/board/gdsys/mpc8308/mpc8308.h new file mode 100644 index 0000000..dc07d56 --- /dev/null +++ b/board/gdsys/mpc8308/mpc8308.h @@ -0,0 +1,10 @@ +#ifndef __MPC8308_H_ +#define __MPC8308_H_ + +/* functions to be provided by board implementation */ +void mpc8308_init(void); +void mpc8308_set_fpga_reset(unsigned state); +void mpc8308_setup_hw(void); +int mpc8308_get_fpga_done(unsigned fpga); + +#endif /* __MPC8308_H_ */ diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c new file mode 100644 index 0000000..0fce8cf --- /dev/null +++ b/board/gdsys/mpc8308/sdram.c @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + * Authors: Nick.Spence@freescale.com + * Wilson.Lo@freescale.com + * scottwood@freescale.com + * + * This files is mostly identical to the original from + * board\freescale\mpc8315erdb\sdram.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mpc83xx.h> +#include <spd_sdram.h> + +#include <asm/bitops.h> +#include <asm/io.h> + +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Fixed sdram init -- doesn't use serial presence detect. + * + * This is useful for faster booting in configs where the RAM is unlikely + * to be changed, or for things like NAND booting where space is tight. + */ +static long fixed_sdram(void) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + + out_be32(&im->sysconf.ddrlaw[0].bar, + CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); + out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); + + out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); + + /* Currently we use only one CS, so disable the other bank. */ + out_be32(&im->ddr.cs_config[1], 0); + + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); + + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + sync(); + + /* enable DDR controller */ + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + sync(); + + return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); +} + +phys_size_t initdram(int board_type) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize; + + if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM */ + msize = fixed_sdram(); + + /* return total bus SDRAM size(bytes) -- DDR */ + return msize; +} diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c index 70eff91..11d075c 100644 --- a/board/gdsys/p1022/controlcenterd-id.c +++ b/board/gdsys/p1022/controlcenterd-id.c @@ -236,7 +236,7 @@ static int ccdm_mmc_read(struct mmc *mmc, u64 src, u8 *dst, int size) tmp_buf); if (!n) goto failure; - result = min(size, blk_len - ofs); + result = min(size, (int)(blk_len - ofs)); memcpy(dst, tmp_buf + ofs, result); dst += result; size -= result; @@ -736,7 +736,8 @@ do_bin_func: src_buf = buf; for (ptr = (uint8_t *)src_buf, i = 20; i > 0; i -= data_size, ptr += data_size) - memcpy(ptr, data, min(i, data_size)); + memcpy(ptr, data, + min_t(size_t, i, data_size)); } } bin_func(dst_reg->digest, src_buf, 20); @@ -931,11 +932,12 @@ static struct key_program *load_key_chunk(const char *ifname, struct key_program header; uint32_t crc; uint8_t buf[12]; - int i; + loff_t i; if (fs_set_blk_dev(ifname, dev_part_str, fs_type)) goto failure; - i = fs_read(path, (ulong)buf, 0, 12); + if (fs_read(path, (ulong)buf, 0, 12, &i) < 0) + goto failure; if (i < 12) goto failure; header.magic = get_unaligned_be32(buf); @@ -950,8 +952,9 @@ static struct key_program *load_key_chunk(const char *ifname, goto failure; if (fs_set_blk_dev(ifname, dev_part_str, fs_type)) goto failure; - i = fs_read(path, (ulong)result, 0, - sizeof(struct key_program) + header.code_size); + if (fs_read(path, (ulong)result, 0, + sizeof(struct key_program) + header.code_size, &i) < 0) + goto failure; if (i <= 0) goto failure; *result = header; @@ -1042,7 +1045,7 @@ static int second_stage_init(void) const char *image_path = "/ccdm.itb"; char *mac_path = NULL; ulong image_addr; - size_t image_size; + loff_t image_size; uint32_t err; printf("CCDM S2\n"); @@ -1084,10 +1087,11 @@ static int second_stage_init(void) image_addr = (ulong)get_image_location(); if (fs_set_blk_dev("mmc", mmcdev, FS_TYPE_EXT)) goto failure; - image_size = fs_read(image_path, image_addr, 0, 0); + if (fs_read(image_path, image_addr, 0, 0, &image_size) < 0) + goto failure; if (image_size <= 0) goto failure; - printf("CCDM image found on %s, %d bytes\n", mmcdev, image_size); + printf("CCDM image found on %s, %lld bytes\n", mmcdev, image_size); hmac_blob = load_key_chunk("mmc", mmcdev, FS_TYPE_EXT, mac_path); if (!hmac_blob) { diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c index f76d968..64d90dd 100644 --- a/board/gdsys/p1022/controlcenterd.c +++ b/board/gdsys/p1022/controlcenterd.c @@ -326,7 +326,7 @@ int board_eth_init(bd_t *bis) } #ifdef CONFIG_OF_BOARD_SETUP -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -343,6 +343,8 @@ void ft_board_setup(void *blob, bd_t *bd) #endif FT_FSL_PCI_SETUP; + + return 0; } #endif diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig new file mode 100644 index 0000000..3a4f557 --- /dev/null +++ b/board/google/chromebook_link/Kconfig @@ -0,0 +1,31 @@ +if TARGET_CHROMEBOOK_LINK + +config SYS_BOARD + default "chromebook_link" + +config SYS_VENDOR + default "google" + +config SYS_SOC + default "ivybridge" + +config SYS_CONFIG_NAME + default "chromebook_link" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SOUTHBRIDGE_INTEL_C216 + select HAVE_ACPI_RESUME + select MARK_GRAPHICS_MEM_WRCOMB + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config EARLY_POST_CROS_EC + bool "Enable early post to Chrome OS EC" + default y + +endif diff --git a/board/google/chromebook_link/MAINTAINERS b/board/google/chromebook_link/MAINTAINERS new file mode 100644 index 0000000..bc253a2 --- /dev/null +++ b/board/google/chromebook_link/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK LINK BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/chromebook_link/ +F: include/configs/chromebook_link.h +F: configs/chromebook_link_defconfig diff --git a/board/google/chromebook_link/Makefile b/board/google/chromebook_link/Makefile new file mode 100644 index 0000000..a133c2e --- /dev/null +++ b/board/google/chromebook_link/Makefile @@ -0,0 +1,15 @@ +# +# Copyright (c) 2011 The Chromium OS Authors. +# (C) Copyright 2008 +# Graeme Russ, graeme.russ@gmail.com. +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += link.o diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c new file mode 100644 index 0000000..1822237 --- /dev/null +++ b/board/google/chromebook_link/link.c @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <cros_ec.h> +#include <asm/gpio.h> + +int arch_early_init_r(void) +{ + if (cros_ec_board_init()) + return -1; + + return 0; +} + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ + .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */ + .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */ + .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ + .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */ + .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */ + .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */ + .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */ + .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */ + .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */ + .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */ + .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */ + .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */ + .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */ +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio1 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ + .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ + .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ + .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ + .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio36 = GPIO_DIR_OUTPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio36 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_map link_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; + +int board_early_init_f(void) +{ + ich_gpio_set_gpio_map(&link_gpio_map); + + return 0; +} diff --git a/board/google/common/Makefile b/board/google/common/Makefile new file mode 100644 index 0000000..b38bc14 --- /dev/null +++ b/board/google/common/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2014 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += early_init.o diff --git a/board/google/common/early_init.S b/board/google/common/early_init.S new file mode 100644 index 0000000..7017185 --- /dev/null +++ b/board/google/common/early_init.S @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + /* Enable post codes to EC */ +#ifdef CONFIG_EARLY_POST_CROS_EC + mov $0x1b, %ecx + rdmsr + and $0x100, %eax + test %eax, %eax + je 1f + + mov $0x8000f8f0, %eax + mov $0xcf8, %dx + out %eax, (%dx) + mov $0xfed1c001, %eax + mov $0xcfc, %dx + out %eax, (%dx) + mov $0xfed1f410, %esp + mov (%esp), %eax + and $0xfffffffb, %eax + mov %eax, (%esp) +1: +#endif + jmp early_board_init_ret diff --git a/board/hermes/Kconfig b/board/hermes/Kconfig deleted file mode 100644 index deb37fd..0000000 --- a/board/hermes/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_HERMES - -config SYS_BOARD - default "hermes" - -config SYS_CONFIG_NAME - default "hermes" - -endif diff --git a/board/hermes/MAINTAINERS b/board/hermes/MAINTAINERS deleted file mode 100644 index a596dad..0000000 --- a/board/hermes/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -HERMES BOARD -M: Wolfgang Denk <wd@denx.de> -S: Maintained -F: board/hermes/ -F: include/configs/hermes.h -F: configs/hermes_defconfig diff --git a/board/hermes/Makefile b/board/hermes/Makefile deleted file mode 100644 index ccca520..0000000 --- a/board/hermes/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = hermes.o flash.o diff --git a/board/hermes/flash.c b/board/hermes/flash.c deleted file mode 100644 index 38d3cd3..0000000 --- a/board/hermes/flash.c +++ /dev/null @@ -1,444 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_byte (flash_info_t *info, ulong dest, uchar data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size<<20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | - (memctl->memc_br0 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - uchar value; - vu_char *caddr = (vu_char *)addr; - ulong base = (ulong)addr; - - - /* Write auto select command: read Manufacturer ID */ - caddr[0x0AAA] = 0xAA; - caddr[0x0555] = 0x55; - caddr[0x0AAA] = 0x90; - - value = caddr[0]; - switch (value) { - case (AMD_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = caddr[2]; /* device ID */ - - switch (value) { - case (AMD_ID_LV400T & 0xFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV400B & 0xFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV800T & 0xFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800B & 0xFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV160T & 0xFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160B & 0xFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV320B & 0xFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection: D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[4] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (vu_char *)info->start[0]; - - *caddr = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_char *addr = (vu_char*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0AAA] = 0xAA; - addr[0x0555] = 0x55; - addr[0x0AAA] = 0x80; - addr[0x0AAA] = 0xAA; - addr[0x0555] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char*)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_char*)(info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr++, *src++)) != 0) { - return (rc); - } - --cnt; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0AAA] = 0xAA; - addr[0x0555] = 0x55; - addr[0x0AAA] = 0xA0; - - *((vu_char *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c deleted file mode 100644 index 6126b73..0000000 --- a/board/hermes/hermes.c +++ /dev/null @@ -1,590 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <commproc.h> -#include <mpc8xx.h> - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -# define SHOW_BOOT_PROGRESS(arg) bootstage_mark(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -static ulong board_init (void); -static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd, - uchar * msg); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1fe77c35, 0xffaffc34, 0x1fa57c35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaebc00, 0x10ad4c00, 0xf0afcc00, - 0xf0afcc00, 0xe1bb8c06, 0x1ff77c47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test ID string (HERMES...) - * - * Return code for board revision and network speed - */ - -int checkboard (void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: "); - - if (l < 0 || strncmp(buf, "HERMES", 6)) { - puts ("### No HW ID - assuming HERMES-PRO"); - } else { - for (i = 0; i < l; i++) { - if (buf[i] == ' ') - break; - putc (buf[i]); - } - } - - gd->board_type = board_init (); - - printf (" Rev. %ld.x\n", (gd->board_type >> 16)); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size, size8, size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = 0x0400; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 1 to the SDRAM banks at preliminary address - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - /* HERMES-PRO boards have only one bank SDRAM */ - - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mamr = 0xD0802114; - memctl->memc_mcr = 0x80002105; - udelay (1); - memctl->memc_mamr = 0xD0802118; - memctl->memc_mcr = 0x80002130; - udelay (1); - memctl->memc_mamr = 0xD0802114; - memctl->memc_mcr = 0x80002106; - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - udelay (10000); - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#define PB_LED_3 0x00020000 /* Status LED's */ -#define PB_LED_2 0x00010000 -#define PB_LED_1 0x00008000 -#define PB_LED_0 0x00004000 - -#define PB_LED_ALL (PB_LED_0 | PB_LED_1 | PB_LED_2 | PB_LED_3) - -#define PC_REP_SPD1 0x00000800 -#define PC_REP_SPD0 0x00000400 - -#define PB_RESET_2081 0x00000020 /* Reset PEB2081 */ - -#define PB_MAI_4 0x00000010 /* Configuration */ -#define PB_MAI_3 0x00000008 -#define PB_MAI_2 0x00000004 -#define PB_MAI_1 0x00000002 -#define PB_MAI_0 0x00000001 - -#define PB_MAI_ALL (PB_MAI_0 | PB_MAI_1 | PB_MAI_2 | PB_MAI_3 | PB_MAI_4) - - -#define PC_REP_MGRPRS 0x0200 -#define PC_REP_SPD 0x0040 /* Select 100 Mbps */ -#define PC_REP_RES 0x0004 -#define PC_BIT14 0x0002 /* ??? */ -#define PC_BIT15 0x0001 /* ??? ENDSL ?? */ - -/* ------------------------------------------------------------------------- */ - -static ulong board_init (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - ulong reg, revision, speed = 100; - int ethspeed; - char *s; - - if ((s = getenv ("ethspeed")) != NULL) { - if (strcmp (s, "100") == 0) { - ethspeed = 100; - } else if (strcmp (s, "10") == 0) { - ethspeed = 10; - } else { - ethspeed = 0; - } - } else { - ethspeed = 0; - } - - /* Configure Port B Output Pins => 0x0003cc3F */ - reg = PB_LED_ALL | PC_REP_SPD1 | PC_REP_SPD0 | PB_RESET_2081 | - PB_MAI_ALL; - immr->im_cpm.cp_pbpar &= ~reg; - immr->im_cpm.cp_pbodr &= ~reg; - immr->im_cpm.cp_pbdat &= ~reg; /* all 0 */ - immr->im_cpm.cp_pbdir |= reg; - - /* Check hardware revision */ - if ((immr->im_ioport.iop_pcdat & 0x0003) == 0x0003) { - /* - * Revision 3.x hardware - */ - revision = 3; - - immr->im_ioport.iop_pcdat = 0x0240; - immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14); /* = 0x0246 */ - immr->im_ioport.iop_pcdat |= PC_REP_RES; - } else { - immr->im_ioport.iop_pcdat = 0x0002; - immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0207 */ - - if ((immr->im_ioport.iop_pcdat & PC_REP_SPD) == 0) { - /* - * Revision 2.x hardware: PC9 connected to PB21 - */ - revision = 2; - - if (ethspeed == 0) { - /* both 10 and 100 Mbps allowed: - * select 10 Mbps and autonegotiation - */ - puts (" [10+100]"); - immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */ - speed = 10; - } else if (ethspeed == 10) { - /* we are asked for 10 Mbps, - * so select 10 Mbps - */ - puts (" [10]"); - immr->im_cpm.cp_pbdat = 0; /* ??? */ - speed = 10; - } else { - /* anything else: - * select 100 Mbps - */ - puts (" [100]"); - immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1; - /* SPD1:SPD0 = 1:1 - 100 Mbps */ - speed = 100; - } - immr->im_ioport.iop_pcdat |= (PC_REP_RES | PC_BIT14); - - /* must be run from RAM */ - /* start_lxt980 (speed); */ - /*************************/ - } else { - /* - * Revision 1.x hardware - */ - revision = 1; - - immr->im_ioport.iop_pcdat = PC_REP_MGRPRS | PC_BIT14; /* = 0x0202 */ - immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0247 */ - - if (ethspeed == 0) { - /* both 10 and 100 Mbps allowed: - * select 100 Mbps and autonegotiation - */ - puts (" [10+100]"); - immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */ - immr->im_ioport.iop_pcdat |= PC_REP_SPD; - } else if (ethspeed == 10) { - /* we are asked for 10 Mbps, - * so select 10 Mbps - */ - puts (" [10]"); - immr->im_cpm.cp_pbdat = PC_REP_SPD0; /* SPD1:SPD0 = 0:1 - 10 Mbps */ - } else { - /* anything else: - * select 100 Mbps - */ - puts (" [100]"); - immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1; - /* SPD1:SPD0 = 1:1 - 100 Mbps */ - immr->im_ioport.iop_pcdat |= PC_REP_SPD; - } - - immr->im_ioport.iop_pcdat |= PC_REP_RES; - } - } - SHOW_BOOT_PROGRESS(BOOTSTAGE_ID_CHECK_MAGIC); - - return ((revision << 16) | (speed & 0xFFFF)); -} - -/* ------------------------------------------------------------------------- */ - -#define SCC_SM 1 /* Index => SCC2 */ -#define PROFF PROFF_SCC2 - -#define SMI_MSGLEN 8 /* Length of SMI Messages */ - -#define PHYGPCR_ADDR 0x109 /* Port Enable */ -#define PHYPCR_ADDR 0x132 /* PHY Port Control Reg. (port 1) */ -#define LEDPCR_ADDR 0x141 /* LED Port Control Reg. */ -#define RPRESET_ADDR 0x144 /* Repeater Reset */ - -#define PHYPCR_SPEED 0x2000 /* on for 100 Mbps, off for 10 Mbps */ -#define PHYPCR_AN 0x1000 /* on to enable Auto-Negotiation */ -#define PHYPCR_REST_AN 0x0200 /* on to restart Auto-Negotiation */ -#define PHYPCR_FDX 0x0100 /* on for Full Duplex, off for HDX */ -#define PHYPCR_COLT 0x0080 /* on to enable COL signal test */ - -/* ------------------------------------------------------------------------- */ - -/* - * Must run from RAM: - * uses parameter RAM area which is used for stack while running from ROM - */ -void hermes_start_lxt980 (int speed) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm); - volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]); - volatile cbd_t *bd; - volatile hdlc_pram_t *hp; - uchar smimsg[SMI_MSGLEN]; - ushort phypcrval; - uint bd_off; - int pnr; - - printf ("LXT9880: %3d Mbps\n", speed); - - immr->im_ioport.iop_paodr |= 0x0008; /* init PAODR: PA12 (TXD2) open drain */ - immr->im_ioport.iop_papar |= 0x400c; /* init PAPAR: TXD2, RXD2, BRGO4 */ - immr->im_ioport.iop_padir &= 0xbff3; /* init PADIR: BRGO4 */ - immr->im_ioport.iop_padir |= 0x4000; - - /* get temporary BD; no need for permanent alloc */ - bd_off = dpram_base_align (8); - - bd = (cbd_t *) (immr->im_cpm.cp_dpmem + bd_off); - - bd->cbd_bufaddr = 0; - bd->cbd_datlen = 0; - bd->cbd_sc = BD_SC_WRAP | BD_SC_LAST | BD_SC_INTRPT | BD_SC_TC; - - /* init. baudrate generator BRG4 */ - cp->cp_brgc4 = (0x00010000 | (50 << 1)); /* output 1 MHz */ - - cp->cp_sicr &= 0xFFFF00FF; /* SICR: mask SCC2 */ - cp->cp_sicr |= 0x00001B00; /* SICR: SCC2 clk BRG4 */ - - /* init SCC_SM register */ - sp->scc_psmr = 0x0000; /* init PSMR: no additional flags */ - sp->scc_todr = 0x0000; - sp->scc_dsr = 0x7e7e; - - /* init. SCC_SM parameter area */ - hp = (hdlc_pram_t *) & cp->cp_dparam[PROFF]; - - hp->tbase = bd_off; /* offset from beginning of DPRAM */ - - hp->rfcr = 0x18; - hp->tfcr = 0x18; - hp->mrblr = 10; - - hp->c_mask = 0x0000f0b8; - hp->c_pres = 0x0000ffff; - - hp->disfc = 0; - hp->crcec = 0; - hp->abtsc = 0; - hp->nmarc = 0; - hp->retrc = 0; - - hp->mflr = 10; - - hp->rfthr = 1; - - hp->hmask = 0; - hp->haddr1 = 0; - hp->haddr2 = 0; - hp->haddr3 = 0; - hp->haddr4 = 0; - - cp->cp_cpcr = SCC_SM << 6 | 0x0001; /* SCC_SM: init TX/RX params */ - while (cp->cp_cpcr & CPM_CR_FLG); - - /* clear all outstanding SCC events */ - sp->scc_scce = ~0; - - /* enable transmitter: GSMR_L: TPL=2(16bits), TPP=3(all ones), ENT */ - sp->scc_gsmrh = 0; - sp->scc_gsmrl |= SCC_GSMRL_TPL_16 | SCC_GSMRL_TPP_ALL1 | - SCC_GSMRL_ENT | SCC_GSMRL_MODE_HDLC; - -#if 0 - smimsg[0] = 0x00; /* CHIP/HUB ID */ - smimsg[1] = 0x38; /* WRITE CMD */ - smimsg[2] = (RPRESET_ADDR << 4) & 0xf0; - smimsg[3] = RPRESET_ADDR >> 4; - smimsg[4] = 0x01; - smimsg[5] = 0x00; - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); -#endif - - smimsg[0] = 0x7f; /* BROADCAST */ - smimsg[1] = 0x34; /* ASSIGN HUB ID */ - smimsg[2] = 0x00; - smimsg[3] = 0x00; - smimsg[4] = 0x00; /* HUB ID = 0 */ - smimsg[5] = 0x00; - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - - smimsg[0] = 0x7f; /* BROADCAST */ - smimsg[1] = 0x3c; /* SET ARBOUT TO 0 */ - smimsg[2] = 0x00; /* ADDRESS = 0 */ - smimsg[3] = 0x00; - smimsg[4] = 0x00; /* DATA = 0 */ - smimsg[5] = 0x00; - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - - if (speed == 100) { - phypcrval = PHYPCR_SPEED; /* 100 MBIT, disable autoneg. */ - } else { - phypcrval = 0; /* 10 MBIT, disable autoneg. */ - } - - /* send MSGs */ - for (pnr = 0; pnr < 8; pnr++) { - smimsg[0] = 0x00; /* CHIP/HUB ID */ - smimsg[1] = 0x38; /* WRITE CMD */ - smimsg[2] = ((PHYPCR_ADDR + pnr) << 4) & 0xf0; - smimsg[3] = (PHYPCR_ADDR + pnr) >> 4; - smimsg[4] = (unsigned char) (phypcrval & 0xff); - smimsg[5] = (unsigned char) (phypcrval >> 8); - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - } - - smimsg[0] = 0x00; /* CHIP/HUB ID */ - smimsg[1] = 0x38; /* WRITE CMD */ - smimsg[2] = (PHYGPCR_ADDR << 4) & 0xf0; - smimsg[3] = PHYGPCR_ADDR >> 4; - smimsg[4] = 0xff; /* enable port 1-8 */ - smimsg[5] = 0x01; /* enable MII1 (0x01) */ - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - - smimsg[0] = 0x00; /* CHIP/HUB ID */ - smimsg[1] = 0x38; /* WRITE CMD */ - smimsg[2] = (LEDPCR_ADDR << 4) & 0xf0; - smimsg[3] = LEDPCR_ADDR >> 4; - smimsg[4] = 0xaa; /* Port 1-8 Conf.bits = 10 (Hardware control) */ - smimsg[5] = 0xaa; - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - - /* - * Disable Transmitter (so that we can free the BD, too) - */ - sp->scc_gsmrl &= ~SCC_GSMRL_ENT; -} - -/* ------------------------------------------------------------------------- */ - -static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd, - uchar * msg) -{ -#ifdef DEBUG - unsigned hub, chip, cmd, length, addr; - - hub = msg[0] & 0x1F; - chip = msg[0] >> 5; - cmd = msg[1] & 0x1F; - length = (msg[1] >> 5) | ((msg[2] & 0x0F) << 3); - addr = (msg[2] >> 4) | (msg[3] << 4); - - printf ("SMI send: Hub %02x Chip %x Cmd %02x Len %d Addr %03x: " - "%02x %02x %02x %02x\n", - hub, chip, cmd, length, addr, msg[4], msg[5], msg[6], msg[7]); -#endif /* DEBUG */ - - bd->cbd_bufaddr = (uint) msg; - bd->cbd_datlen = SMI_MSGLEN; - bd->cbd_sc |= BD_SC_READY; - - /* wait for msg transmitted */ - while ((sp->scc_scce & 0x0002) == 0); - /* clear all events */ - sp->scc_scce = ~0; -} - -/* ------------------------------------------------------------------------- */ - -void show_boot_progress (int status) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* let things compatible */ - if (status < -BOOTSTAGE_ID_POST_FAIL_R) - status = -1; - status ^= 0x0F; - status = (status & 0x0F) << 14; - immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status; -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds deleted file mode 100644 index 0309860..0000000 --- a/board/hermes/u-boot.lds +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - board/hermes/built-in.o (.text*) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug deleted file mode 100644 index f34c07b..0000000 --- a/board/hermes/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - arch/powerpc/cpu/mpc8xx/interrupts.o (.text) - arch/powerpc/lib/time.o (.text) - arch/powerpc/lib/ticks.o (.text) - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index a1b6749..fc2385c 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -94,7 +94,7 @@ void dram_init_banksize(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *fdt, bd_t *bd) +int ft_board_setup(void *fdt, bd_t *bd) { static const char disabled[] = "disabled"; u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); @@ -106,6 +106,8 @@ void ft_board_setup(void *fdt, bd_t *bd) if (!(reg & PWRDOM_STAT_EMMC)) do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status", disabled, sizeof(disabled), 1); + + return 0; } #endif diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index a99416b..f0af24a 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -311,10 +311,11 @@ void ide_set_reset (int idereset) #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c index f742143..e7838dc 100644 --- a/board/ids/ids8313/ids8313.c +++ b/board/ids/ids8313/ids8313.c @@ -138,9 +138,11 @@ phys_size_t initdram(int board_type) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c index 0fbdfdb..5d2ab2f 100644 --- a/board/ifm/ac14xx/ac14xx.c +++ b/board/ifm/ac14xx/ac14xx.c @@ -608,8 +608,10 @@ int checkboard(void) } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c index 6716ffc..ca09767 100644 --- a/board/ifm/o2dnt2/o2dnt2.c +++ b/board/ifm/o2dnt2/o2dnt2.c @@ -364,7 +364,7 @@ int update_flash_size(int flash_size) } #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */ -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int phy_addr = CONFIG_PHY_ADDR; char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0"; @@ -380,5 +380,7 @@ void ft_board_setup(void *blob, bd_t *bd) #endif /* fix up the phy address */ do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index d363e49..78c4bd4 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -37,7 +37,7 @@ static void malta_lcd_puts(const char *str) void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); /* print up to 8 characters of the string */ - for (i = 0; i < min(strlen(str), 8); i++) { + for (i = 0; i < min((int)strlen(str), 8); i++) { __raw_writel(str[i], reg); reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; } diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c index 5843725..4ab7160 100644 --- a/board/intercontrol/digsy_mtc/digsy_mtc.c +++ b/board/intercontrol/digsy_mtc/digsy_mtc.c @@ -454,7 +454,7 @@ int update_flash_size (int flash_size) } #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */ -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int phy_addr = CONFIG_PHY_ADDR; char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0"; @@ -478,5 +478,7 @@ void ft_board_setup(void *blob, bd_t *bd) #endif /* fix up the phy address */ do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c index d44c4bf..2078f53 100644 --- a/board/ipek01/ipek01.c +++ b/board/ipek01/ipek01.c @@ -196,10 +196,12 @@ void pci_init_board (void) #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup (void *blob, bd_t * bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup (blob, bd); fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 7b87cc2..47522f8 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -150,6 +150,13 @@ int board_mmc_init(bd_t *bis) } #endif +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + void set_fdt(void) { switch (gd->bd->bi_arch_number) { diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c index 78e4b5d..8856393 100644 --- a/board/jupiter/jupiter.c +++ b/board/jupiter/jupiter.c @@ -283,9 +283,10 @@ void ide_set_reset (int idereset) #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c index dfbfab8..bf84676 100644 --- a/board/keymile/km82xx/km82xx.c +++ b/board/keymile/km82xx/km82xx.c @@ -300,11 +300,9 @@ phys_size_t initdram(int board_type) out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT); out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); -#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ psize = probe_sdram(memctl); -#endif /* CONFIG_SYS_RAMBOOT */ icache_enable(); @@ -460,8 +458,10 @@ static void setports(int gpio) } #endif #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 0543483..1da0dcb 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -359,9 +359,11 @@ int checkboard(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index 4a73613..a74f75b 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -261,7 +261,7 @@ void fdt_fixup_fman_mac_addresses(void *blob) } #endif -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; @@ -286,6 +286,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); fdt_fixup_fman_mac_addresses(blob); #endif + + return 0; } #if defined(CONFIG_POST) diff --git a/board/korat/korat.c b/board/korat/korat.c index 8b83000..d9ab2fd 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -610,7 +610,7 @@ void pci_target_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { u32 val[4]; int rc; @@ -627,5 +627,7 @@ void ft_board_setup(void *blob, bd_t *bd) if (rc) printf("Unable to update property NOR mapping, err=%s\n", fdt_strerror(rc)); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c index c4155dd..c07735a 100644 --- a/board/kosagi/novena/novena_spl.c +++ b/board/kosagi/novena/novena_spl.c @@ -17,6 +17,7 @@ #include <asm/imx-common/boot_mode.h> #include <asm/imx-common/iomux-v3.h> #include <asm/imx-common/mxc_i2c.h> +#include <asm/arch/crm_regs.h> #include <i2c.h> #include <mmc.h> #include <fsl_esdhc.h> @@ -533,6 +534,30 @@ static struct mx6_ddr3_cfg elpida_4gib_1600 = { .trasmin = 3590, }; +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0xFFFFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + /* * called from C runtime startup code (arch/arm/lib/crt0.S:_main) * - we have a stack and a place to store GD, both in SRAM @@ -543,6 +568,9 @@ void board_init_f(ulong dummy) /* setup AIPS and disable watchdog */ arch_cpu_init(); + ccgr_init(); + gpr_init(); + /* setup GP timer */ timer_init(); diff --git a/board/kosagi/novena/setup.cfg b/board/kosagi/novena/setup.cfg deleted file mode 100644 index 18d139c..0000000 --- a/board/kosagi/novena/setup.cfg +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2014 Marek Vasut <marex@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Refer docs/README.imxmage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* Boot Device : sd */ -BOOT_FROM sd - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ -DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c index a4c1998..71c6a79 100644 --- a/board/kup/kup4k/kup4k.c +++ b/board/kup/kup4k/kup4k.c @@ -280,8 +280,10 @@ static unsigned char swapbyte(unsigned char c) * Device Tree Support */ #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 1fd9f2c..609edf1 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -128,6 +128,13 @@ int board_mmc_init(bd_t *bis) } #endif +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + #ifdef CONFIG_SMC911X /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */ static const u32 gpmc_lan92xx_config[] = { diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 9ef0026..d39203a 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -109,6 +109,11 @@ int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} #endif #ifdef CONFIG_CMD_NET diff --git a/board/manroland/mucmc52/mucmc52.c b/board/manroland/mucmc52/mucmc52.c index c3ce66d..c8ed5b7 100644 --- a/board/manroland/mucmc52/mucmc52.c +++ b/board/manroland/mucmc52/mucmc52.c @@ -385,8 +385,10 @@ void pci_init_board (void) #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/manroland/uc101/uc101.c b/board/manroland/uc101/uc101.c index 5c5afa2..e794c46 100644 --- a/board/manroland/uc101/uc101.c +++ b/board/manroland/uc101/uc101.c @@ -358,8 +358,10 @@ void hw_watchdog_reset(void) #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c index a69359f..c9d615b 100644 --- a/board/matrix_vision/mvblx/mvblx.c +++ b/board/matrix_vision/mvblx/mvblx.c @@ -94,6 +94,12 @@ int board_mmc_init(bd_t *bis) omap_mmc_init(1, 0, 0, -1, -1); return 0; } + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); + twl4030_power_mmc_init(1); +} #endif #if defined(CONFIG_CMD_NET) diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index a6235e5..4d0ebaa 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -185,9 +185,11 @@ int checkboard(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/mpc8308_p1m/mpc8308_p1m.c b/board/mpc8308_p1m/mpc8308_p1m.c index 2009e62..688cc12 100644 --- a/board/mpc8308_p1m/mpc8308_p1m.c +++ b/board/mpc8308_p1m/mpc8308_p1m.c @@ -62,10 +62,12 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); fdt_fixup_dr_usb(blob, bd); + + return 0; } #endif diff --git a/board/mpr2/Kconfig b/board/mpr2/Kconfig index 79a60c2..54176e8 100644 --- a/board/mpr2/Kconfig +++ b/board/mpr2/Kconfig @@ -1,8 +1,5 @@ if TARGET_MPR2 -config SYS_CPU - default "sh3" - config SYS_BOARD default "mpr2" diff --git a/board/ms7720se/Kconfig b/board/ms7720se/Kconfig index d935aff..8331327 100644 --- a/board/ms7720se/Kconfig +++ b/board/ms7720se/Kconfig @@ -1,8 +1,5 @@ if TARGET_MS7720SE -config SYS_CPU - default "sh3" - config SYS_BOARD default "ms7720se" diff --git a/board/ms7722se/Kconfig b/board/ms7722se/Kconfig index 17073e8..39027c9 100644 --- a/board/ms7722se/Kconfig +++ b/board/ms7722se/Kconfig @@ -1,8 +1,5 @@ if TARGET_MS7722SE -config SYS_CPU - default "sh4" - config SYS_BOARD default "ms7722se" diff --git a/board/ms7750se/Kconfig b/board/ms7750se/Kconfig index 07aa024..2c0b88c 100644 --- a/board/ms7750se/Kconfig +++ b/board/ms7750se/Kconfig @@ -1,8 +1,5 @@ if TARGET_MS7750SE -config SYS_CPU - default "sh4" - config SYS_BOARD default "ms7750se" diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c index 08eb5e8..e0c4dba 100644 --- a/board/muas3001/muas3001.c +++ b/board/muas3001/muas3001.c @@ -243,14 +243,11 @@ phys_size_t initdram (int board_type) volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; long psize; -#ifndef CONFIG_SYS_RAMBOOT long sizelittle, sizebig; -#endif memctl->memc_psrt = CONFIG_SYS_PSRT; memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ sizelittle = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE, @@ -263,7 +260,6 @@ phys_size_t initdram (int board_type) psize = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE, (uchar *) CONFIG_SYS_SDRAM_BASE); } -#endif /* CONFIG_SYS_RAMBOOT */ icache_enable (); @@ -329,9 +325,11 @@ void ft_blob_update (void *blob, bd_t *bd) } } -void ft_board_setup (void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup (blob, bd); ft_blob_update (blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/munices/munices.c b/board/munices/munices.c index 319fa8c..23d0f56 100644 --- a/board/munices/munices.c +++ b/board/munices/munices.c @@ -146,9 +146,10 @@ void pci_init_board(void) #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index c2e07db..b6b8ad6 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -659,3 +659,9 @@ int board_mmc_init(bd_t *bis) omap_mmc_init(1, 0, 0, -1, -1); return 0; } + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); + twl4030_power_mmc_init(1); +} diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 51125df..0e4a65a 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <dm.h> #include <ns16550.h> #include <linux/compiler.h> #include <asm/io.h> @@ -43,6 +44,13 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SPL_BUILD +/* TODO(sjg@chromium.org): Remove once SPL supports device tree */ +U_BOOT_DEVICE(tegra_gpios) = { + "gpio_tegra" +}; +#endif + const struct tegra_sysinfo sysinfo = { CONFIG_TEGRA_BOARD_STRING }; diff --git a/board/overo/overo.c b/board/overo/overo.c index dfb8602..b7f85e7 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -493,6 +493,13 @@ int board_mmc_init(bd_t *bis) } #endif +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + #if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index 146dcea..59b5a7e 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -126,4 +126,9 @@ int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} #endif diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c index 15f8f31..81f3024 100644 --- a/board/pdm360ng/pdm360ng.c +++ b/board/pdm360ng/pdm360ng.c @@ -477,7 +477,7 @@ static unsigned char edid_buf[128] = { }; #endif -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { u32 val[8]; int rc, i = 0; @@ -526,6 +526,8 @@ void ft_board_setup(void *blob, bd_t *bd) if (rc) printf("Unable to update flash reg property, err=%s\n", fdt_strerror(rc)); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c index ce515d8..ed41de1 100644 --- a/board/phytec/pcm030/pcm030.c +++ b/board/phytec/pcm030/pcm030.c @@ -164,9 +164,11 @@ void pci_init_board(void) #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t * bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/raspberrypi/rpi_b/Kconfig b/board/raspberrypi/rpi/Kconfig index 501d511..6a538cf 100644 --- a/board/raspberrypi/rpi_b/Kconfig +++ b/board/raspberrypi/rpi/Kconfig @@ -1,7 +1,7 @@ -if TARGET_RPI_B +if TARGET_RPI config SYS_BOARD - default "rpi_b" + default "rpi" config SYS_VENDOR default "raspberrypi" @@ -10,6 +10,6 @@ config SYS_SOC default "bcm2835" config SYS_CONFIG_NAME - default "rpi_b" + default "rpi" endif diff --git a/board/raspberrypi/rpi/MAINTAINERS b/board/raspberrypi/rpi/MAINTAINERS new file mode 100644 index 0000000..6dcb7bd --- /dev/null +++ b/board/raspberrypi/rpi/MAINTAINERS @@ -0,0 +1,6 @@ +RPI BOARD +M: Stephen Warren <swarren@wwwdotorg.org> +S: Maintained +F: board/raspberrypi/rpi/ +F: include/configs/rpi.h +F: configs/rpi_defconfig diff --git a/board/raspberrypi/rpi_b/Makefile b/board/raspberrypi/rpi/Makefile index 7e9bfbf..c53c92b 100644 --- a/board/raspberrypi/rpi_b/Makefile +++ b/board/raspberrypi/rpi/Makefile @@ -12,4 +12,4 @@ # GNU General Public License for more details. # -obj-y := rpi_b.o +obj-y := rpi.o diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi/rpi.c index 7445f53..51a4fa1 100644 --- a/board/raspberrypi/rpi_b/rpi_b.c +++ b/board/raspberrypi/rpi/rpi.c @@ -42,6 +42,12 @@ struct msg_get_arm_mem { u32 end_tag; }; +struct msg_get_board_rev { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_get_board_rev get_board_rev; + u32 end_tag; +}; + struct msg_get_mac_address { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_get_mac_address get_mac_address; @@ -60,6 +66,67 @@ struct msg_get_clock_rate { u32 end_tag; }; +/* See comments in mbox.h for data source */ +static const struct { + const char *name; + const char *fdtfile; +} models[] = { + [BCM2835_BOARD_REV_B_I2C0_2] = { + "Model B (no P5)", + "bcm2835-rpi-b-i2c0.dtb", + }, + [BCM2835_BOARD_REV_B_I2C0_3] = { + "Model B (no P5)", + "bcm2835-rpi-b-i2c0.dtb", + }, + [BCM2835_BOARD_REV_B_I2C1_4] = { + "Model B", + "bcm2835-rpi-b.dtb", + }, + [BCM2835_BOARD_REV_B_I2C1_5] = { + "Model B", + "bcm2835-rpi-b.dtb", + }, + [BCM2835_BOARD_REV_B_I2C1_6] = { + "Model B", + "bcm2835-rpi-b.dtb", + }, + [BCM2835_BOARD_REV_A_7] = { + "Model A", + "bcm2835-rpi-a.dtb", + }, + [BCM2835_BOARD_REV_A_8] = { + "Model A", + "bcm2835-rpi-a.dtb", + }, + [BCM2835_BOARD_REV_A_9] = { + "Model A", + "bcm2835-rpi-a.dtb", + }, + [BCM2835_BOARD_REV_B_REV2_d] = { + "Model B rev2", + "bcm2835-rpi-b-rev2.dtb", + }, + [BCM2835_BOARD_REV_B_REV2_e] = { + "Model B rev2", + "bcm2835-rpi-b-rev2.dtb", + }, + [BCM2835_BOARD_REV_B_REV2_f] = { + "Model B rev2", + "bcm2835-rpi-b-rev2.dtb", + }, + [BCM2835_BOARD_REV_B_PLUS] = { + "Model B+", + "bcm2835-rpi-b-plus.dtb", + }, + [BCM2835_BOARD_REV_CM] = { + "Compute Module", + "bcm2835-rpi-cm.dtb", + }, +}; + +u32 rpi_board_rev = 0; + int dram_init(void) { ALLOC_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1, 16); @@ -79,13 +146,27 @@ int dram_init(void) return 0; } -int misc_init_r(void) +static void set_fdtfile(void) +{ + const char *fdtfile; + + if (getenv("fdtfile")) + return; + + fdtfile = models[rpi_board_rev].fdtfile; + if (!fdtfile) + fdtfile = "bcm2835-rpi-other.dtb"; + + setenv("fdtfile", fdtfile); +} + +static void set_usbethaddr(void) { ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16); int ret; if (getenv("usbethaddr")) - return 0; + return; BCM2835_MBOX_INIT_HDR(msg); BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS); @@ -94,11 +175,18 @@ int misc_init_r(void) if (ret) { printf("bcm2835: Could not query MAC address\n"); /* Ignore error; not critical */ - return 0; + return; } eth_setenv_enetaddr("usbethaddr", msg->get_mac_address.body.resp.mac); + return; +} + +int misc_init_r(void) +{ + set_fdtfile(); + set_usbethaddr(); return 0; } @@ -126,8 +214,36 @@ static int power_on_module(u32 module) return 0; } +static void get_board_rev(void) +{ + ALLOC_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1, 16); + int ret; + const char *name; + + BCM2835_MBOX_INIT_HDR(msg); + BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV); + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); + if (ret) { + printf("bcm2835: Could not query board revision\n"); + /* Ignore error; not critical */ + return; + } + + rpi_board_rev = msg->get_board_rev.body.resp.rev; + if (rpi_board_rev >= ARRAY_SIZE(models)) + rpi_board_rev = 0; + + name = models[rpi_board_rev].name; + if (!name) + name = "Unknown model"; + printf("RPI model: %s\n", name); +} + int board_init(void) { + get_board_rev(); + gd->bd->bi_boot_params = 0x100; return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD); @@ -154,7 +270,7 @@ int board_mmc_init(bd_t *bis) msg_clk->get_clock_rate.body.resp.rate_hz); } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { /* * For now, we simply always add the simplefb DT node. Later, we @@ -162,4 +278,6 @@ void ft_board_setup(void *blob, bd_t *bd) * node exists for the "real" graphics driver. */ lcd_dt_simplefb_add_node(blob); + + return 0; } diff --git a/board/raspberrypi/rpi_b/MAINTAINERS b/board/raspberrypi/rpi_b/MAINTAINERS deleted file mode 100644 index 14f3948..0000000 --- a/board/raspberrypi/rpi_b/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -RPI_B BOARD -M: Stephen Warren <swarren@wwwdotorg.org> -S: Maintained -F: board/raspberrypi/rpi_b/ -F: include/configs/rpi_b.h -F: configs/rpi_b_defconfig diff --git a/board/renesas/MigoR/Kconfig b/board/renesas/MigoR/Kconfig index 10dffed..25b170a 100644 --- a/board/renesas/MigoR/Kconfig +++ b/board/renesas/MigoR/Kconfig @@ -1,8 +1,5 @@ if TARGET_MIGOR -config SYS_CPU - default "sh4" - config SYS_BOARD default "MigoR" diff --git a/board/renesas/alt/Makefile b/board/renesas/alt/Makefile index 9ed12bd..6904e39 100644 --- a/board/renesas/alt/Makefile +++ b/board/renesas/alt/Makefile @@ -6,4 +6,4 @@ # SPDX-License-Identifier: GPL-2.0 # -obj-y := alt.o qos.o +obj-y := alt.o qos.o ../rcar-gen2-common/common.o diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index 5c5a86f..8cc17e9 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -15,6 +15,8 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/mmc.h> #include <netdev.h> #include <miiphy.h> #include <i2c.h> @@ -37,26 +39,11 @@ void s_init(void) qos_init(); } -#define MSTPSR1 0xE6150038 -#define SMSTPCR1 0xE6150134 #define TMU0_MSTP125 (1 << 25) - -#define MSTPSR7 0xE61501C4 -#define SMSTPCR7 0xE615014C #define SCIF2_MSTP719 (1 << 19) - -#define MSTPSR8 0xE61509A0 -#define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 << 13) - -#define mstp_setbits(type, addr, saddr, set) \ - out_##type((saddr), in_##type(addr) | (set)) -#define mstp_clrbits(type, addr, saddr, clear) \ - out_##type((saddr), in_##type(addr) & ~(clear)) -#define mstp_setbits_le32(addr, saddr, set) \ - mstp_setbits(le32, addr, saddr, set) -#define mstp_clrbits_le32(addr, saddr, clear) \ - mstp_clrbits(le32, addr, saddr, clear) +#define IIC1_MSTP323 (1 << 23) +#define MMC0_MSTP315 (1 << 15) int board_early_init_f(void) { @@ -69,19 +56,20 @@ int board_early_init_f(void) /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); - return 0; -} + /* IIC1 / sh-i2c ch1 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); -void arch_preboot_os(void) -{ - /* Disable TMU0 */ - mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); +#ifdef CONFIG_SH_MMCIF + /* MMC */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); +#endif + return 0; } int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = ALT_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; /* Init PFC controller */ r8a7794_pinmux_init(); @@ -138,6 +126,19 @@ int board_eth_init(bd_t *bis) #endif } +int board_mmc_init(bd_t *bis) +{ + int ret = 0; + +#ifdef CONFIG_SH_MMCIF + gpio_request(GPIO_GP_4_31, NULL); + gpio_set_value(GPIO_GP_4_31, 1); + + ret = mmcif_mmc_init(); +#endif + return ret; +} + int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; @@ -149,23 +150,11 @@ const struct rmobile_sysinfo sysinfo = { CONFIG_RMOBILE_BOARD_STRING }; -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = ALT_SDRAM_BASE; - gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE; -} - -int board_late_init(void) -{ - return 0; -} - void reset_cpu(ulong addr) { u8 val; - i2c_set_bus_num(1); /* PowerIC connected to ch3 */ - i2c_init(400000, 0); + i2c_set_bus_num(1); /* PowerIC connected to ch1 */ i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); val |= 0x02; i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); diff --git a/board/renesas/ap325rxa/Kconfig b/board/renesas/ap325rxa/Kconfig index 45bd600..c8f2de2 100644 --- a/board/renesas/ap325rxa/Kconfig +++ b/board/renesas/ap325rxa/Kconfig @@ -1,8 +1,5 @@ if TARGET_AP325RXA -config SYS_CPU - default "sh4" - config SYS_BOARD default "ap325rxa" diff --git a/board/renesas/ecovec/Kconfig b/board/renesas/ecovec/Kconfig index a24fe91..08cde83 100644 --- a/board/renesas/ecovec/Kconfig +++ b/board/renesas/ecovec/Kconfig @@ -1,8 +1,5 @@ if TARGET_ECOVEC -config SYS_CPU - default "sh4" - config SYS_BOARD default "ecovec" diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c index 2804d91..d862d99 100644 --- a/board/renesas/ecovec/ecovec.c +++ b/board/renesas/ecovec/ecovec.c @@ -41,7 +41,7 @@ static void debug_led(u8 led) int board_late_init(void) { u8 mac[6]; - char env_mac[17]; + char env_mac[18]; udelay(1000); diff --git a/board/renesas/gose/Kconfig b/board/renesas/gose/Kconfig new file mode 100644 index 0000000..930a445 --- /dev/null +++ b/board/renesas/gose/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GOSE + +config SYS_BOARD + default "gose" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "gose" + +endif diff --git a/board/renesas/gose/MAINTAINERS b/board/renesas/gose/MAINTAINERS new file mode 100644 index 0000000..cad5be9 --- /dev/null +++ b/board/renesas/gose/MAINTAINERS @@ -0,0 +1,6 @@ +ALT BOARD +M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +S: Maintained +F: board/renesas/gose/ +F: include/configs/gose.h +F: configs/gose_defconfig diff --git a/board/renesas/gose/Makefile b/board/renesas/gose/Makefile new file mode 100644 index 0000000..2dac748 --- /dev/null +++ b/board/renesas/gose/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/alt/Makefile +# +# Copyright (C) 2014 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := gose.o qos.o ../rcar-gen2-common/common.o diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c new file mode 100644 index 0000000..677b976 --- /dev/null +++ b/board/renesas/gose/gose.c @@ -0,0 +1,146 @@ +/* + * board/renesas/gose/gose.c + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <netdev.h> +#include <miiphy.h> +#include <i2c.h> +#include "qos.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + u32 stc; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* CPU frequency setting. Set to 1.5GHz */ + stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); + + /* QoS */ + qos_init(); +} + +#define TMU0_MSTP125 (1 << 25) +#define SCIF0_MSTP721 (1 << 21) +#define ETHER_MSTP813 (1 << 13) + +int board_early_init_f(void) +{ + /* TMU0 */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + + /* SCIF0 */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + + return 0; +} + +#define PUPR5 0xE6060114 +#define PUPR5_ETH 0x3FFC0000 +#define PUPR5_ETH_MAGIC (1 << 27) + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + /* Init PFC controller */ + r8a7793_pinmux_init(); + + /* ETHER Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REFCLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); + gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); + + gpio_direction_output(GPIO_GP_5_22, 0); + mdelay(20); + gpio_set_value(GPIO_GP_5_22, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ + +int board_eth_init(bd_t *bis) +{ + int ret = -ENODEV; + u32 val; + unsigned char enetaddr[6]; + +#ifdef CONFIG_SH_ETHER + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); +#endif + + return ret; +} + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +void reset_cpu(ulong addr) +{ + u8 val; + + i2c_set_bus_num(2); /* PowerIC connected to ch2 */ + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); +} diff --git a/board/renesas/gose/qos.c b/board/renesas/gose/qos.c new file mode 100644 index 0000000..64e52cf --- /dev/null +++ b/board/renesas/gose/qos.c @@ -0,0 +1,1155 @@ +/* + * board/renesas/gose/qos.c + * This file is gose QoS setting. + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <asm/arch/rmobile.h> + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +/* QoS version 0.20 */ +enum { + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, + DBSC3_15, + DBSC3_NR, +}; + +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, +}; + +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, +}; + +void qos_init(void) +{ + int i; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; + + /* DBSC DBADJ2 */ + writel(0x20042004, DBSC3_0_DBADJ2); + + /* S3C -QoS */ + s3c = (struct rcar_s3c *)S3C_BASE; + writel(0x00000000, &s3c->s3cadsplcr); + writel(0x1F0B0908, &s3c->s3crorr); + writel(0x1F0C0A08, &s3c->s3cworr); + + /* QoS Control Registers */ + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20DC, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20DC, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20FA, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20FA, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + /* DBSC -QoS */ + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002032, &qos_addr->dbtmval2); + writel(0x00001FB0, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000201E, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002050, &qos_addr->dbtmval2); + writel(0x0000203A, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000203C, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* CCI-400 -QoS */ + writel(0x20001000, CCI_400_MAXOT_1); + writel(0x20001000, CCI_400_MAXOT_2); + writel(0x0000000C, CCI_400_QOSCNTL_1); + writel(0x0000000C, CCI_400_QOSCNTL_2); + + /* MXI -QoS */ + /* Transaction Control (MXI) */ + mxi = (struct rcar_mxi *)MXI_BASE; + writel(0x00000013, &mxi->mxrtcr); + writel(0x00000013, &mxi->mxwtcr); + writel(0x00200000, &mxi->mxs3cracr); + writel(0x00200000, &mxi->mxs3cwacr); + writel(0x00200000, &mxi->mxaxiracr); + writel(0x00200000, &mxi->mxaxiwacr); + + /* QoS Control (MXI) */ + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; + writel(0x0000000C, &mxi_qos->vspdu0); + writel(0x0000000C, &mxi_qos->vspdu1); + writel(0x0000000E, &mxi_qos->du0); + + /* AXI -QoS */ + /* Transaction Control (MXI) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (RT-AXI) */ + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002299, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (MP-AXI) */ + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000206E, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (SYS-AXI256) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (CCI-AXI) */ + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (Media-AXI) */ + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); +} +#else /* CONFIG_RMOBILE_EXTRAM_BOOT */ +void qos_init(void) +{ +} +#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */ diff --git a/board/renesas/gose/qos.h b/board/renesas/gose/qos.h new file mode 100644 index 0000000..ffd4047 --- /dev/null +++ b/board/renesas/gose/qos.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __QOS_H__ +#define __QOS_H__ + +void qos_init(void); + +#endif diff --git a/board/renesas/koelsch/Makefile b/board/renesas/koelsch/Makefile index b4d0183..c10bba5 100644 --- a/board/renesas/koelsch/Makefile +++ b/board/renesas/koelsch/Makefile @@ -6,4 +6,4 @@ # SPDX-License-Identifier: GPL-2.0 # -obj-y := koelsch.o qos.o +obj-y := koelsch.o qos.o ../rcar-gen2-common/common.o diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 37202f9..10fa571 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -16,6 +16,7 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> #include <netdev.h> #include <miiphy.h> #include <i2c.h> @@ -43,27 +44,10 @@ void s_init(void) qos_init(); } -#define MSTPSR1 0xE6150038 -#define SMSTPCR1 0xE6150134 #define TMU0_MSTP125 (1 << 25) - -#define MSTPSR7 0xE61501C4 -#define SMSTPCR7 0xE615014C #define SCIF0_MSTP721 (1 << 21) - -#define MSTPSR8 0xE61509A0 -#define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 << 13) -#define mstp_setbits(type, addr, saddr, set) \ - out_##type((saddr), in_##type(addr) | (set)) -#define mstp_clrbits(type, addr, saddr, clear) \ - out_##type((saddr), in_##type(addr) & ~(clear)) -#define mstp_setbits_le32(addr, saddr, set) \ - mstp_setbits(le32, addr, saddr, set) -#define mstp_clrbits_le32(addr, saddr, clear) \ - mstp_clrbits(le32, addr, saddr, clear) - int board_early_init_f(void) { mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); @@ -77,12 +61,6 @@ int board_early_init_f(void) return 0; } -void arch_preboot_os(void) -{ - /* Disable TMU0 */ - mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); -} - /* LSI pin pull-up control */ #define PUPR5 0xe6060114 #define PUPR5_ETH 0x3FFC0000 @@ -90,7 +68,7 @@ void arch_preboot_os(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; /* Init PFC controller */ r8a7791_pinmux_init(); @@ -173,17 +151,6 @@ const struct rmobile_sysinfo sysinfo = { CONFIG_RMOBILE_BOARD_STRING }; -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE; - gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE; -} - -int board_late_init(void) -{ - return 0; -} - void reset_cpu(ulong addr) { u8 val; diff --git a/board/renesas/lager/Makefile b/board/renesas/lager/Makefile index 034c6f8..8d03461 100644 --- a/board/renesas/lager/Makefile +++ b/board/renesas/lager/Makefile @@ -6,4 +6,4 @@ # SPDX-License-Identifier: GPL-2.0 # -obj-y := lager.o qos.o +obj-y := lager.o qos.o ../rcar-gen2-common/common.o diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 2bb8710..d1e29d2 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -18,8 +18,11 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/mmc.h> #include <miiphy.h> #include <i2c.h> +#include <mmc.h> #include "qos.h" DECLARE_GLOBAL_DATA_PTR; @@ -50,26 +53,10 @@ void s_init(void) qos_init(); } -#define MSTPSR1 0xE6150038 -#define SMSTPCR1 0xE6150134 #define TMU0_MSTP125 (1 << 25) - -#define MSTPSR7 0xE61501C4 -#define SMSTPCR7 0xE615014C #define SCIF0_MSTP721 (1 << 21) - -#define MSTPSR8 0xE61509A0 -#define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 << 13) - -#define mstp_setbits(type, addr, saddr, set) \ - out_##type((saddr), in_##type(addr) | (set)) -#define mstp_clrbits(type, addr, saddr, clear) \ - out_##type((saddr), in_##type(addr) & ~(clear)) -#define mstp_setbits_le32(addr, saddr, set) \ - mstp_setbits(le32, addr, saddr, set) -#define mstp_clrbits_le32(addr, saddr, clear) \ - mstp_clrbits(le32, addr, saddr, clear) +#define MMC1_MSTP305 (1 << 5) int board_early_init_f(void) { @@ -79,21 +66,17 @@ int board_early_init_f(void) mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + /* eMMC */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305); return 0; } -void arch_preboot_os(void) -{ - /* Disable TMU0 */ - mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); -} - DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; /* Init PFC controller */ r8a7790_pinmux_init(); @@ -163,6 +146,28 @@ int board_phy_config(struct phy_device *phydev) return 0; } +int board_mmc_init(bd_t *bis) +{ + int ret = 0; + +#ifdef CONFIG_SH_MMCIF + gpio_request(GPIO_FN_MMC1_D0, NULL); + gpio_request(GPIO_FN_MMC1_D1, NULL); + gpio_request(GPIO_FN_MMC1_D2, NULL); + gpio_request(GPIO_FN_MMC1_D3, NULL); + gpio_request(GPIO_FN_MMC1_D4, NULL); + gpio_request(GPIO_FN_MMC1_D5, NULL); + gpio_request(GPIO_FN_MMC1_D6, NULL); + gpio_request(GPIO_FN_MMC1_D7, NULL); + gpio_request(GPIO_FN_MMC1_CLK, NULL); + gpio_request(GPIO_FN_MMC1_CMD, NULL); + + ret = mmcif_mmc_init(); +#endif + return ret; +} + + int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; @@ -174,17 +179,6 @@ const struct rmobile_sysinfo sysinfo = { CONFIG_RMOBILE_BOARD_STRING }; -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = LAGER_SDRAM_BASE; - gd->bd->bi_dram[0].size = LAGER_SDRAM_SIZE; -} - -int board_late_init(void) -{ - return 0; -} - void reset_cpu(ulong addr) { u8 val; diff --git a/board/renesas/r0p7734/Kconfig b/board/renesas/r0p7734/Kconfig index bda785d..7f24f41 100644 --- a/board/renesas/r0p7734/Kconfig +++ b/board/renesas/r0p7734/Kconfig @@ -1,8 +1,5 @@ if TARGET_R0P7734 -config SYS_CPU - default "sh4" - config SYS_BOARD default "r0p7734" diff --git a/board/renesas/r2dplus/Kconfig b/board/renesas/r2dplus/Kconfig index c55c109..6597870 100644 --- a/board/renesas/r2dplus/Kconfig +++ b/board/renesas/r2dplus/Kconfig @@ -1,8 +1,5 @@ if TARGET_R2DPLUS -config SYS_CPU - default "sh4" - config SYS_BOARD default "r2dplus" diff --git a/board/renesas/r7780mp/Kconfig b/board/renesas/r7780mp/Kconfig index 2d3cbec..050cc4c 100644 --- a/board/renesas/r7780mp/Kconfig +++ b/board/renesas/r7780mp/Kconfig @@ -1,8 +1,5 @@ if TARGET_R7780MP -config SYS_CPU - default "sh4" - config SYS_BOARD default "r7780mp" diff --git a/board/renesas/rcar-gen2-common/common.c b/board/renesas/rcar-gen2-common/common.c new file mode 100644 index 0000000..0103f42 --- /dev/null +++ b/board/renesas/rcar-gen2-common/common.c @@ -0,0 +1,59 @@ +/* + * board/renesas/rcar-gen2-common/common.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> + +#define TSTR0 0x04 +#define TSTR0_STR0 0x01 + +static struct mstp_ctl mstptbl[] = { + { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA, + RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA }, + { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA, + RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA }, + { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA, + RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA }, + { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA, + RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA }, + { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA, + RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA }, + { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA, + RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA }, + /* No MSTP6 */ + { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA, + RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA }, + { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA, + RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA }, + { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA, + RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA }, + { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA, + RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA }, + { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA, + RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA }, +}; + +void arch_preboot_os(void) +{ + int i; + + /* stop TMU0 */ + mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0); + + /* Stop module clock */ + for (i = 0; i < ARRAY_SIZE(mstptbl); i++) { + mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_dis, + mstptbl[i].s_ena); + mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_dis, + mstptbl[i].r_ena); + } +} diff --git a/board/renesas/rsk7203/Kconfig b/board/renesas/rsk7203/Kconfig index 5eb2923..10b8786 100644 --- a/board/renesas/rsk7203/Kconfig +++ b/board/renesas/rsk7203/Kconfig @@ -1,8 +1,5 @@ if TARGET_RSK7203 -config SYS_CPU - default "sh2" - config SYS_BOARD default "rsk7203" diff --git a/board/renesas/rsk7264/Kconfig b/board/renesas/rsk7264/Kconfig index af71295..755d289 100644 --- a/board/renesas/rsk7264/Kconfig +++ b/board/renesas/rsk7264/Kconfig @@ -1,8 +1,5 @@ if TARGET_RSK7264 -config SYS_CPU - default "sh2" - config SYS_BOARD default "rsk7264" diff --git a/board/renesas/rsk7269/Kconfig b/board/renesas/rsk7269/Kconfig index cc0092c..ab5cd0e 100644 --- a/board/renesas/rsk7269/Kconfig +++ b/board/renesas/rsk7269/Kconfig @@ -1,8 +1,5 @@ if TARGET_RSK7269 -config SYS_CPU - default "sh2" - config SYS_BOARD default "rsk7269" diff --git a/board/renesas/sh7752evb/Kconfig b/board/renesas/sh7752evb/Kconfig index 7c6aae9..7f40888 100644 --- a/board/renesas/sh7752evb/Kconfig +++ b/board/renesas/sh7752evb/Kconfig @@ -1,8 +1,5 @@ if TARGET_SH7752EVB -config SYS_CPU - default "sh4" - config SYS_BOARD default "sh7752evb" diff --git a/board/renesas/sh7753evb/Kconfig b/board/renesas/sh7753evb/Kconfig index 8abdea0..be88924 100644 --- a/board/renesas/sh7753evb/Kconfig +++ b/board/renesas/sh7753evb/Kconfig @@ -1,8 +1,5 @@ if TARGET_SH7753EVB -config SYS_CPU - default "sh4" - config SYS_BOARD default "sh7753evb" diff --git a/board/renesas/sh7757lcr/Kconfig b/board/renesas/sh7757lcr/Kconfig index 97d966f..3fba80d 100644 --- a/board/renesas/sh7757lcr/Kconfig +++ b/board/renesas/sh7757lcr/Kconfig @@ -1,8 +1,5 @@ if TARGET_SH7757LCR -config SYS_CPU - default "sh4" - config SYS_BOARD default "sh7757lcr" diff --git a/board/renesas/sh7763rdp/Kconfig b/board/renesas/sh7763rdp/Kconfig index d512988..101d2b5 100644 --- a/board/renesas/sh7763rdp/Kconfig +++ b/board/renesas/sh7763rdp/Kconfig @@ -1,8 +1,5 @@ if TARGET_SH7763RDP -config SYS_CPU - default "sh4" - config SYS_BOARD default "sh7763rdp" diff --git a/board/renesas/sh7785lcr/Kconfig b/board/renesas/sh7785lcr/Kconfig index 15787e6..e204c76 100644 --- a/board/renesas/sh7785lcr/Kconfig +++ b/board/renesas/sh7785lcr/Kconfig @@ -1,8 +1,5 @@ if TARGET_SH7785LCR -config SYS_CPU - default "sh4" - config SYS_BOARD default "sh7785lcr" diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 33003ee..b7d2381 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -382,6 +382,22 @@ static void board_gpio_init(void) gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP); gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X); gpio_direction_input(EXYNOS4X12_GPIO_X31); + + /* Blue LED (Odroid X2/U2/U3) */ + gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED"); + + gpio_direction_output(EXYNOS4X12_GPIO_C10, 0); + +#ifdef CONFIG_CMD_USB + /* USB3503A Reference frequency */ + gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq"); + + /* USB3503A Connect */ + gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect"); + + /* USB3503A Reset */ + gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset"); +#endif } static int pmic_init_max77686(void) @@ -462,9 +478,39 @@ struct s3c_plat_otg_data s5pc210_otg_data = { .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL, .usb_flags = PHY0_SLEEP, }; +#endif + +#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB) int board_usb_init(int index, enum usb_init_type init) { +#ifdef CONFIG_CMD_USB + struct pmic *p_pmic; + + /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/ + /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */ + if (gd->board_type == ODROID_TYPE_U3) + gpio_direction_output(EXYNOS4X12_GPIO_X30, 0); + else + gpio_direction_output(EXYNOS4X12_GPIO_X30, 1); + + /* Disconnect, Reset, Connect */ + gpio_direction_output(EXYNOS4X12_GPIO_X34, 0); + gpio_direction_output(EXYNOS4X12_GPIO_X35, 0); + gpio_direction_output(EXYNOS4X12_GPIO_X35, 1); + gpio_direction_output(EXYNOS4X12_GPIO_X34, 1); + + /* Power off and on BUCK8 for LAN9730 */ + debug("LAN9730 - Turning power buck 8 OFF and ON.\n"); + + p_pmic = pmic_get("MAX77686_PMIC"); + if (p_pmic && !pmic_probe(p_pmic)) { + max77686_set_buck_voltage(p_pmic, 8, 750000); + max77686_set_buck_voltage(p_pmic, 8, 3300000); + } + +#endif + debug("USB_udc_probe\n"); return s3c_udc_probe(&s5pc210_otg_data); } diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig index d3a5b7f..e7aafe5 100644 --- a/board/samsung/smdk5420/Kconfig +++ b/board/samsung/smdk5420/Kconfig @@ -1,3 +1,19 @@ +if TARGET_PEACH_PI + +config SYS_BOARD + string + default "smdk5420" + +config SYS_VENDOR + string + default "samsung" + +config SYS_CONFIG_NAME + string + default "peach-pi" + +endif + if TARGET_PEACH_PIT config SYS_BOARD diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS index e0f5c7a..1423f83 100644 --- a/board/samsung/smdk5420/MAINTAINERS +++ b/board/samsung/smdk5420/MAINTAINERS @@ -6,3 +6,5 @@ F: include/configs/peach-pit.h F: configs/peach-pit_defconfig F: include/configs/smdk5420.h F: configs/smdk5420_defconfig +F: include/configs/peach-pi.h +F: configs/peach-pi_defconfig diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 89da47e..72786d2 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -214,11 +214,13 @@ void sdram_init(void) #endif #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index d584276..25329e4 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -301,12 +301,14 @@ int last_stage_init(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_FSL_PCI_INIT FT_FSL_PCI_SETUP; #endif + + return 0; } #endif diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 4906be4..6bdf1a2 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -173,11 +173,13 @@ void pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup (void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); FT_FSL_PCI_SETUP; + + return 0; } #endif diff --git a/board/shmin/Kconfig b/board/shmin/Kconfig index a1c383e..467580c 100644 --- a/board/shmin/Kconfig +++ b/board/shmin/Kconfig @@ -1,8 +1,5 @@ if TARGET_SHMIN -config SYS_CPU - default "sh3" - config SYS_BOARD default "shmin" diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 2782bcc..cc0ac6b 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -96,15 +96,6 @@ const struct dpll_params *get_dpll_ddr_params(void) return &dpll_ddr; } -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - omap_nand_switch_ecc(1, 8); - - return 0; -} -#endif - #ifndef CONFIG_SPL_BUILD #if defined(BOARD_DFU_BUTTON_GPIO) /* diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c index 266dbbb..7baac3d 100644 --- a/board/siemens/common/factoryset.c +++ b/board/siemens/common/factoryset.c @@ -86,6 +86,7 @@ int get_factory_record_val(unsigned char *eeprom_buf, int size, uchar *record, int i, nxt = 0; int c; unsigned char end = 0xff; + unsigned char tmp; for (i = 0; fact_get_char(i) != end; i = nxt) { nxt = i + 1; @@ -93,6 +94,7 @@ int get_factory_record_val(unsigned char *eeprom_buf, int size, uchar *record, int pos; int endpos; int z; + int level = 0; c = strncmp((char *)&eeprom_buf[i + 1], (char *)record, strlen((char *)record)); @@ -103,22 +105,30 @@ int get_factory_record_val(unsigned char *eeprom_buf, int size, uchar *record, /* search for "<" */ c = -1; for (z = pos; fact_get_char(z) != end; z++) { - if ((fact_get_char(z) == '<') || - (fact_get_char(z) == '>')) { - endpos = z; - nxt = endpos; - c = 0; - break; + if (fact_get_char(z) == '<') { + if (level == 0) { + endpos = z; + nxt = endpos; + c = 0; + break; + } else { + level--; + } } + if (fact_get_char(z) == '>') + level++; } + } else { + continue; } if (c == 0) { /* end found -> call get_factory_val */ + tmp = eeprom_buf[endpos]; eeprom_buf[endpos] = end; ret = get_factory_val(&eeprom_buf[pos], - size - pos, name, buf, len); + endpos - pos, name, buf, len); /* fix buffer */ - eeprom_buf[endpos] = '<'; + eeprom_buf[endpos] = tmp; debug("%s: %s.%s = %s\n", __func__, record, name, buf); return ret; @@ -210,15 +220,6 @@ int factoryset_read_eeprom(int i2c_addr) printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id, factory_dat.usb_product_id); #endif - if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV", - (uchar *)"id", buf, - MAX_STRING_LENGTH)) { - if (strncmp((const char *)buf, "PXM50", 5) == 0) - factory_dat.pxm50 = 1; - else - factory_dat.pxm50 = 0; - } - debug("PXM50: %d\n", factory_dat.pxm50); #if defined(CONFIG_VIDEO) if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1", (uchar *)"name", factory_dat.disp_name, @@ -238,6 +239,23 @@ int factoryset_read_eeprom(int i2c_addr) NULL, 16); debug("version number: %d\n", factory_dat.version); } + /* Get ASN from factory set if available */ + if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV", + (uchar *)"id", factory_dat.asn, + MAX_STRING_LENGTH)) { + debug("factoryset asn: %s\n", factory_dat.asn); + } else { + factory_dat.asn[0] = 0; + } + /* Get COMP/ver from factory set if available */ + if (0 <= get_factory_record_val(cp, size, (uchar *)"COMP", + (uchar *)"ver", + factory_dat.comp_version, + MAX_STRING_LENGTH)) { + debug("factoryset COMP/ver: %s\n", factory_dat.comp_version); + } else { + strcpy((char *)factory_dat.comp_version, "1.0"); + } return 0; diff --git a/board/siemens/common/factoryset.h b/board/siemens/common/factoryset.h index 4d6de10..3f23d5e 100644 --- a/board/siemens/common/factoryset.h +++ b/board/siemens/common/factoryset.h @@ -20,6 +20,8 @@ struct factorysetcontainer { #endif unsigned char serial[MAX_STRING_LENGTH]; int version; + uchar asn[MAX_STRING_LENGTH]; + uchar comp_version[MAX_STRING_LENGTH]; }; int factoryset_read_eeprom(int i2c_addr); diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index f1e93ef..0a11540 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -31,12 +31,10 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_CMD_NAND static void corvus_nand_hw_init(void) { struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa; /* Enable CS3 */ @@ -63,22 +61,111 @@ static void corvus_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); - writel(1 << ATMEL_ID_PIOC, &pmc->pcer); - - /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_periph_clk_enable(ATMEL_ID_PIOC); /* Enable NandFlash */ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } + +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h> + +void at91_spl_board_init(void) +{ + /* + * For on the sam9m10g45ek board, the chip wm9711 stay in the test + * mode, so it need do some action to exit mode. + */ + at91_set_gpio_output(AT91_PIN_PD7, 0); + at91_set_gpio_output(AT91_PIN_PD8, 0); + at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); + at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); + + corvus_nand_hw_init(); + + /* Configure recovery button PINs */ + at91_set_gpio_input(AT91_PIN_PB7, 1); + + /* check if button is pressed */ + if (at91_get_gpio_value(AT91_PIN_PB7) == 0) { + u32 boot_device; + + debug("Recovery button pressed\n"); + boot_device = spl_boot_device(); + switch (boot_device) { +#ifdef CONFIG_SPL_NAND_SUPPORT + case BOOT_DEVICE_NAND: + nand_init(); + spl_nand_erase_one(0, 0); + break; #endif + } + } +} -#ifdef CONFIG_CMD_USB -static void taurus_usb_hw_init(void) +#include <asm/arch/atmel_mpddrc.h> +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_DIC_DS | + ATMEL_MPDDRC_CR_DQMS_SHARED | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3); + ddr2->rtr = 0x24b; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */ + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ + 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ + 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct atmel_mpddr ddr2; + unsigned long csa; + + ddr2_conf(&ddr2); - writel(1 << ATMEL_ID_PIODE, &pmc->pcer); + /* enable DDR2 clock */ + writel(0x4, &pmc->scer); + + /* Chip select 1 is for DDR2/SDRAM */ + csa = readl(&mat->ebicsa); + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; + csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V; + writel(csa, &mat->ebicsa); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_CS6, &ddr2); +} +#endif + +#ifdef CONFIG_CMD_USB +static void taurus_usb_hw_init(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIODE); at91_set_gpio_output(AT91_PIN_PD1, 0); at91_set_gpio_output(AT91_PIN_PD3, 0); @@ -88,10 +175,8 @@ static void taurus_usb_hw_init(void) #ifdef CONFIG_MACB static void corvus_macb_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - /* Enable clock */ - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC); /* * Disable pull-up on: diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c index 9be2e34..ede73ba 100644 --- a/board/siemens/draco/board.c +++ b/board/siemens/draco/board.c @@ -280,4 +280,13 @@ U_BOOT_CMD( #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + omap_nand_switch_ecc(1, 8); + + return 0; +} +#endif + #include "../common/board.c" diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index 559af0e..264ba02 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -428,4 +428,38 @@ static int board_video_init(void) return 0; } #endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + int ret; + + omap_nand_switch_ecc(1, 8); + +#ifdef CONFIG_FACTORYSET + if (factory_dat.asn[0] != 0) { + char tmp[2 * MAX_STRING_LENGTH + 2]; + + if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0) + factory_dat.pxm50 = 1; + else + factory_dat.pxm50 = 0; + sprintf(tmp, "%s_%s", factory_dat.asn, + factory_dat.comp_version); + ret = setenv("boardid", tmp); + if (ret) + printf("error setting board id\n"); + } else { + factory_dat.pxm50 = 1; + ret = setenv("boardid", "PXM50_1.0"); + if (ret) + printf("error setting board id\n"); + } + debug("PXM50: %d\n", factory_dat.pxm50); +#endif + + return 0; +} +#endif + #include "../common/board.c" diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index 1752df2..fb840f7 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -467,4 +467,27 @@ static int board_video_init(void) return 0; } #endif /* ifdef CONFIG_VIDEO */ + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + int ret; + char tmp[2 * MAX_STRING_LENGTH + 2]; + + omap_nand_switch_ecc(1, 8); + + if (factory_dat.asn[0] != 0) + sprintf(tmp, "%s_%s", factory_dat.asn, + factory_dat.comp_version); + else + sprintf(tmp, "QMX7.E38_4.0"); + + ret = setenv("boardid", tmp); + if (ret) + printf("error setting board id\n"); + + return 0; +} +#endif + #include "../common/board.c" diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 673b302..b8ff478 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -21,14 +21,17 @@ #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/arch/at91sam9_sdramc.h> +#include <asm/arch/clk.h> +#include <linux/mtd/nand.h> #include <atmel_mci.h> +#include <asm/arch/at91_spi.h> +#include <spi.h> #include <net.h> #include <netdev.h> DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_CMD_NAND static void taurus_nand_hw_init(void) { struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; @@ -61,15 +64,77 @@ static void taurus_nand_hw_init(void) /* Enable NandFlash */ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } + +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h> + +void matrix_init(void) +{ + struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; + + writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE)) + | AT91_MATRIX_SLOT_CYCLE_(0x40), + &mat->scfg[3]); +} + +void at91_spl_board_init(void) +{ + taurus_nand_hw_init(); + + /* Configure recovery button PINs */ + at91_set_gpio_input(AT91_PIN_PA31, 1); + + /* check if button is pressed */ + if (at91_get_gpio_value(AT91_PIN_PA31) == 0) { + u32 boot_device; + + debug("Recovery button pressed\n"); + boot_device = spl_boot_device(); + switch (boot_device) { +#ifdef CONFIG_SPL_NAND_SUPPORT + case BOOT_DEVICE_NAND: + nand_init(); + spl_nand_erase_one(0, 0); + break; +#endif + } + } +} + +void mem_init(void) +{ + struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct sdramc_reg setting; + + at91_sdram_hw_init(); + setting.cr = (AT91_SDRAMC_NC_9 | + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_CAS_3 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_DBW_32 | + AT91_SDRAMC_TWR_VAL(3) | + AT91_SDRAMC_TRC_VAL(9) | + AT91_SDRAMC_TRP_VAL(3) | + AT91_SDRAMC_TRCD_VAL(3) | + AT91_SDRAMC_TRAS_VAL(6) | + AT91_SDRAMC_TXSR_VAL(10)); + setting.mdr = AT91_SDRAMC_MD_SDRAM; + setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; + + + writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC | + AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL, + &ma->ebicsa); + sdramc_initialize(ATMEL_BASE_CS1, &setting); +} #endif #ifdef CONFIG_MACB static void taurus_macb_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - /* Enable EMAC clock */ - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC0); /* * Disable pull-up on: @@ -117,28 +182,43 @@ int board_mmc_init(bd_t *bd) int board_early_init_f(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - /* Enable clocks for all PIOs */ - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOC), - &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + + at91_seriald_hw_init(); return 0; } +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1); +} + int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND taurus_nand_hw_init(); #endif #ifdef CONFIG_MACB taurus_macb_hw_init(); #endif + at91_spi0_hw_init(TAURUS_SPI_MASK); return 0; } diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 2caefbb..953a43f 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -218,8 +218,7 @@ int board_early_init_r (void) #endif /* CONFIG_BOARD_EARLY_INIT_R */ #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { u32 val[12]; int rc, i = 0; @@ -251,6 +250,8 @@ ft_board_setup(void *blob, bd_t *bd) if (rc) printf("Unable to update localbus ranges, err=%s\n", fdt_strerror(rc)); + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/solidrun/hummingboard/hummingboard.c b/board/solidrun/hummingboard/hummingboard.c index 6d204b3..52c384b 100644 --- a/board/solidrun/hummingboard/hummingboard.c +++ b/board/solidrun/hummingboard/hummingboard.c @@ -146,7 +146,7 @@ int board_eth_init(bd_t *bis) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - int ret = enable_fec_anatop_clock(ENET_25MHz); + int ret = enable_fec_anatop_clock(ENET_25MHZ); if (ret) return ret; diff --git a/board/st/stv0991/Kconfig b/board/st/stv0991/Kconfig new file mode 100644 index 0000000..8bda349 --- /dev/null +++ b/board/st/stv0991/Kconfig @@ -0,0 +1,23 @@ +if TARGET_STV0991 + +config SYS_CPU + string + default "armv7" + +config SYS_BOARD + string + default "stv0991" + +config SYS_VENDOR + string + default "st" + +config SYS_SOC + string + default "stv0991" + +config SYS_CONFIG_NAME + string + default "stv0991" + +endif diff --git a/board/st/stv0991/MAINTAINERS b/board/st/stv0991/MAINTAINERS new file mode 100644 index 0000000..87221e9 --- /dev/null +++ b/board/st/stv0991/MAINTAINERS @@ -0,0 +1,5 @@ +STV0991 APPLICATION BOARD +M: Vikas Manocha <vikas.manocha@st.com> +S: Maintained +F: board/st/stv0991/ +F: include/configs/stv0991.h diff --git a/board/st/stv0991/Makefile b/board/st/stv0991/Makefile new file mode 100644 index 0000000..fb5169a --- /dev/null +++ b/board/st/stv0991/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 +# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := stv0991.o diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c new file mode 100644 index 0000000..f465699 --- /dev/null +++ b/board/st/stv0991/stv0991.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/stv0991_periph.h> +#include <asm/arch/stv0991_defs.h> +#include <asm/arch/hardware.h> +#include <asm/arch/gpio.h> +#include <netdev.h> +#include <asm/io.h> +#include <dm/platdata.h> +#include <dm/platform_data/serial_pl01x.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct gpio_regs *const gpioa_regs = + (struct gpio_regs *) GPIOA_BASE_ADDR; + +static const struct pl01x_serial_platdata serial_platdata = { + .base = 0x80406000, + .type = TYPE_PL011, + .clock = 2700 * 1000, +}; + +U_BOOT_DEVICE(stv09911_serials) = { + .name = "serial_pl01x", + .platdata = &serial_platdata, +}; + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int progress) +{ + printf("%i\n", progress); +} +#endif + +void enable_eth_phy(void) +{ + /* Set GPIOA_06 pad HIGH (Appli board)*/ + writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir); + writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data); +} +int board_eth_enable(void) +{ + stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4); + clock_setup(ETH_CLOCK_CFG); + enable_eth_phy(); + return 0; +} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + board_eth_enable(); + return 0; +} + +int board_uart_init(void) +{ + stv0991_pinmux_config(UART_GPIOC_30_31); + clock_setup(UART_CLOCK_CFG); + return 0; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + board_uart_init(); + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int ret = 0; + +#if defined(CONFIG_DESIGNWARE_ETH) + u32 interface = PHY_INTERFACE_MODE_MII; + if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0) + ret++; +#endif + return ret; +} +#endif diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index f5c3d75..6e4eed8 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -233,9 +233,11 @@ reset_phy(void) } #ifdef CONFIG_OF_BOARD_SETUP -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup (blob, bd); + + return 0; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index c3f865d..246cd9a 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -21,7 +21,10 @@ config MACH_SUN6I config MACH_SUN7I bool "sun7i (Allwinner A20)" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN8I bool "sun8i (Allwinner A23)" @@ -213,4 +216,18 @@ config USB2_VBUS_PIN ---help--- See USB1_VBUS_PIN help text. +config VIDEO + boolean "Enable graphical uboot console on HDMI" + default y + ---help--- + Say Y here to add support for using a cfb console on the HDMI output + found on most sunxi devices. + +config USB_KEYBOARD + boolean "Enable USB keyboard support" + default y + ---help--- + Say Y here to add support for using a USB keyboard (typically used + in combination with a graphical console on HDMI). + endif diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c index 5e12328..b7f0dda 100644 --- a/board/sunxi/ahci.c +++ b/board/sunxi/ahci.c @@ -76,6 +76,8 @@ void scsi_init(void) #ifdef CONFIG_SATAPWR gpio_request(CONFIG_SATAPWR, "satapwr"); gpio_direction_output(CONFIG_SATAPWR, 1); + /* Give attached sata device time to power-up to avoid link timeouts */ + mdelay(500); #endif if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index e6ec5b8..4c1c69a 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -24,6 +24,7 @@ #endif #include <asm/arch/clock.h> #include <asm/arch/cpu.h> +#include <asm/arch/display.h> #include <asm/arch/dram.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> @@ -237,3 +238,12 @@ int misc_init_r(void) return 0; } #endif + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_VIDEO_DT_SIMPLEFB + return sunxi_simplefb_setup(blob); +#endif +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 051aca0..571bc9e 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -13,7 +13,12 @@ int sunxi_gmac_initialize(bd_t *bis) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; /* Set up clock gating */ +#ifndef CONFIG_MACH_SUN6I setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); +#else + setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC); +#endif /* Set MII clock */ #ifdef CONFIG_RGMII @@ -33,6 +38,7 @@ int sunxi_gmac_initialize(bd_t *bis) setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10); #endif +#ifndef CONFIG_MACH_SUN6I /* Configure pin mux settings for GMAC */ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { #ifdef CONFIG_RGMII @@ -43,9 +49,48 @@ int sunxi_gmac_initialize(bd_t *bis) sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC); sunxi_gpio_set_drv(pin, 3); } +#elif defined CONFIG_RGMII + /* Configure sun6i RGMII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } +#elif defined CONFIG_GMII + /* Configure sun6i GMII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 2); + } +#else + /* Configure sun6i MII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); + for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); +#endif #ifdef CONFIG_RGMII return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII); +#elif defined CONFIG_GMII + return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII); #else return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII); #endif diff --git a/board/tbs/tbs2910/Kconfig b/board/tbs/tbs2910/Kconfig new file mode 100644 index 0000000..84b243e --- /dev/null +++ b/board/tbs/tbs2910/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TBS2910 + +config SYS_BOARD + default "tbs2910" + +config SYS_VENDOR + default "tbs" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "tbs2910" + +endif diff --git a/board/tbs/tbs2910/MAINTAINERS b/board/tbs/tbs2910/MAINTAINERS new file mode 100644 index 0000000..bf17655 --- /dev/null +++ b/board/tbs/tbs2910/MAINTAINERS @@ -0,0 +1,6 @@ +TBS2910 BOARD +M: Soeren Moch <smoch@web.de> +S: Maintained +F: board/tbs/tbs2910/ +F: configs/tbs2910_defconfig +F: include/configs/tbs2910.h diff --git a/board/tbs/tbs2910/Makefile b/board/tbs/tbs2910/Makefile new file mode 100644 index 0000000..9d9eb87 --- /dev/null +++ b/board/tbs/tbs2910/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Soeren Moch <smoch@web.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := tbs2910.o diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c new file mode 100644 index 0000000..dfa430e --- /dev/null +++ b/board/tbs/tbs2910/tbs2910.c @@ -0,0 +1,397 @@ +/* + * Copyright (C) 2014 Soeren Moch <smoch@web.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/sata.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/video.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +DECLARE_GLOBAL_DATA_PTR; + +#define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) + +#ifdef CONFIG_SYS_I2C +/* I2C1, SGTL5000 */ +static struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +/* I2C2 HDMI */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* I2C3, CON11, DS1307, PCIe_SMB */ +static struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD, + .gp = IMX_GPIO_NR(1, 6) + } +}; +#endif /* CONFIG_SYS_I2C */ + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* AR8035 PHY Reset */ + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pcie_pads[] = { + /* W_DISABLE# */ + MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), + /* PERST# */ + MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int dram_init(void) +{ + gd->ram_size = 2048ul * 1024 * 1024; + return 0; +} + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* Reset AR8035 PHY */ + gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(1, 25), 1); +} + +static void setup_pcie(void) +{ + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/uSDHC4 is always present */ + break; + } + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + /* + * (U-boot device node) (Physical Port) + * mmc0 SD2 + * mmc1 SD3 + * mmc2 eMMC + */ + int i, ret; + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + i + 1, CONFIG_SYS_FSL_USDHC_NUM); + return -EINVAL; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + return 0; +} +#endif /* CONFIG_FSL_ESDHC */ + +#ifdef CONFIG_VIDEO_IPUV3 +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + /* 1024x768@60Hz (VESA)*/ + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15384, + .left_margin = 160, + .right_margin = 24, + .upper_margin = 29, + .lower_margin = 3, + .hsync_len = 136, + .vsync_len = 6, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + s32 timeout = 100000; + + enable_ipu_clock(); + imx_setup_hdmi(); + + /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */ + reg = readl(&ccm->analog_pll_video); + reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN; + writel(reg, &ccm->analog_pll_video); + + reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37); + reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1); + writel(reg, &ccm->analog_pll_video); + + writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); + + reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; + writel(reg, &ccm->analog_pll_video); + + while (timeout--) + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) + break; + if (timeout < 0) + printf("Warning: video pll lock timeout!\n"); + + reg = readl(&ccm->analog_pll_video); + reg |= BM_ANADIG_PLL_VIDEO_ENABLE; + reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; + writel(reg, &ccm->analog_pll_video); + + /* select video pll for ldb_di0_clk */ + reg = readl(&ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK); + writel(reg, &ccm->cs2cdr); + + /* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */ + reg = readl(&ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &ccm->cscmr2); + + /* select ldb_di0_ipu_clk for ipu1_di0_clk -> 65MHz pixclock */ + reg = readl(&ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &ccm->chsccdr); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + setup_pcie(); + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + /* 8 bit bus width */ + {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_VIDEO_IPUV3 + setup_display(); +#endif +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif +#ifdef CONFIG_DWC_AHSATA + setup_sata(); +#endif +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} + +int checkboard(void) +{ + puts("Board: TBS2910 Matrix ARM mini PC\n"); + return 0; +} diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c index 44a8240..744ff44 100644 --- a/board/technexion/tao3530/tao3530.c +++ b/board/technexion/tao3530/tao3530.c @@ -188,6 +188,13 @@ int board_mmc_init(bd_t *bis) } #endif +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + #if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) /* Call usb_stop() before starting the kernel */ void show_boot_progress(int val) diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 4c5e381..7b37fbe 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -534,6 +534,13 @@ int board_mmc_init(bd_t *bis) } #endif +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + #if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) /* Call usb_stop() before starting the kernel */ void show_boot_progress(int val) diff --git a/board/ti/beagle_x15/Kconfig b/board/ti/beagle_x15/Kconfig new file mode 100644 index 0000000..a305ff1 --- /dev/null +++ b/board/ti/beagle_x15/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BEAGLE_X15 + +config SYS_BOARD + default "beagle_x15" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "beagle_x15" + +endif diff --git a/board/ti/beagle_x15/Makefile b/board/ti/beagle_x15/Makefile new file mode 100644 index 0000000..5cd6873 --- /dev/null +++ b/board/ti/beagle_x15/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 +# Texas Instruments, <www.ti.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c new file mode 100644 index 0000000..db96e34 --- /dev/null +++ b/board/ti/beagle_x15/board.c @@ -0,0 +1,395 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Felipe Balbi <balbi@ti.com> + * + * Based on board/ti/dra7xx/evm.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <palmas.h> +#include <sata.h> +#include <usb.h> +#include <asm/omap_common.h> +#include <asm/emif.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sata.h> +#include <asm/arch/gpio.h> +#include <environment.h> + +#include "mux_data.h" + +#ifdef CONFIG_DRIVER_TI_CPSW +#include <cpsw.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + "Board: BeagleBoard x15\n" +}; + +static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { + .dmm_lisa_map_3 = 0x80740300, + .is_ma_present = 0x1 +}; + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + *dmm_lisa_regs = &beagle_x15_lisa_regs; +} + +static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { + .sdram_config_init = 0x61851b32, + .sdram_config = 0x61851b32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xceef266b, + .sdram_tim2 = 0x328f7fda, + .sdram_tim3 = 0x027f88a8, + .read_idle_ctrl = 0x00050001, + .zq_config = 0x0007190b, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0e24400a, + .emif_ddr_phy_ctlr_1 = 0x0e24400a, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00740074, + .emif_ddr_ext_phy_ctrl_3 = 0x00780078, + .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, + .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { + 0x00800080, + 0x00360036, + 0x00340034, + 0x00360036, + 0x00350035, + 0x00350035, + + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + + 0x00430043, + 0x003e003e, + 0x004a004a, + 0x00470047, + 0x00400040, + + 0x00000000, + 0x00600020, + 0x40010080, + 0x08102040, + + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040 +}; + +static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { + .sdram_config_init = 0x61851b32, + .sdram_config = 0x61851b32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xceef266b, + .sdram_tim2 = 0x328f7fda, + .sdram_tim3 = 0x027f88a8, + .read_idle_ctrl = 0x00050001, + .zq_config = 0x0007190b, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0e24400a, + .emif_ddr_phy_ctlr_1 = 0x0e24400a, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00820082, + .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, + .emif_ddr_ext_phy_ctrl_4 = 0x00800080, + .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { + 0x00800080, + 0x00370037, + 0x00390039, + 0x00360036, + 0x00370037, + 0x00350035, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x00540054, + 0x00540054, + 0x004e004e, + 0x004c004c, + 0x00400040, + + 0x00000000, + 0x00600020, + 0x40010080, + 0x08102040, + + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040 +}; + +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + switch (emif_nr) { + case 1: + *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; + break; + case 2: + *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; + break; + } +} + +void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) +{ + switch (emif_nr) { + case 1: + *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; + *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); + break; + case 2: + *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; + *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); + break; + } +} + +struct vcores_data beagle_x15_volts = { + .mpu.value = VDD_MPU_DRA752, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, + .mpu.pmic = &tps659038, + + .eve.value = VDD_EVE_DRA752, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS659038_REG_ADDR_SMPS45, + .eve.pmic = &tps659038, + + .gpu.value = VDD_GPU_DRA752, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS659038_REG_ADDR_SMPS45, + .gpu.pmic = &tps659038, + + .core.value = VDD_CORE_DRA752, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS659038_REG_ADDR_SMPS6, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA752, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS659038_REG_ADDR_SMPS45, + .iva.pmic = &tps659038, +}; + +void hw_data_init(void) +{ + *prcm = &dra7xx_prcm; + *dplls_data = &dra7xx_dplls; + *omap_vcores = &beagle_x15_volts; + *ctrl = &dra7xx_ctrl; +} + +int board_init(void) +{ + gpmc_init(); + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + + return 0; +} + +int board_late_init(void) +{ + init_sata(0); + /* + * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds + * This is the POWERHOLD-in-Low behavior. + */ + palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); + return 0; +} + +static void do_set_mux32(u32 base, + struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *)array; + + for (i = 0; i < size; i++, pad++) + writel(pad->val, base + pad->offset); +} + +void set_muxconf_regs_essential(void) +{ + do_set_mux32((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); + return 0; +} +#endif + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + +#ifdef CONFIG_SPL_ENV_SUPPORT + env_init(); + env_relocate_spec(); + if (getenv_yesno("boot_os") != 1) + return 1; +#endif + + return 0; +} +#endif + +#ifdef CONFIG_DRIVER_TI_CPSW + +/* Delay value to add to calibrated value */ +#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) +#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) +#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) +#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) + +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 1, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 2, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int ret; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + uint32_t ctrl_val; + + /* try reading mac address from efuse */ + mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC\n"); + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("eth1addr")) { + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + + ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); + ctrl_val |= 0x22; + writel(ctrl_val, (*ctrl)->control_core_control_io1); + + ret = cpsw_register(&cpsw_data); + if (ret < 0) + printf("Error %d registering CPSW switch\n", ret); + + return ret; +} +#endif + +#ifdef CONFIG_USB_XHCI_OMAP +int board_usb_init(int index, enum usb_init_type init) +{ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, + OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M); + + return 0; +} +#endif diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h new file mode 100644 index 0000000..2294abe --- /dev/null +++ b/board/ti/beagle_x15/mux_data.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Felipe Balbi <balbi@ti.com> + * + * Based on board/ti/dra7xx/evm.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _MUX_DATA_BEAGLE_X15_H_ +#define _MUX_DATA_BEAGLE_X15_H_ + +#include <asm/arch/mux_dra7xx.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ + {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ + {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ + {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ + {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ + {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ + {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ + {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ + {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ + {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ + {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ + {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ + {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ + {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ + {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ + {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ + {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ + {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ + {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */ + {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */ + {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ + {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ + {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ + {RGMII0_TXC, (M0) }, + {RGMII0_TXCTL, (M0) }, + {RGMII0_TXD3, (M0) }, + {RGMII0_TXD2, (M0) }, + {RGMII0_TXD1, (M0) }, + {RGMII0_TXD0, (M0) }, + {RGMII0_RXC, (IEN | M0) }, + {RGMII0_RXCTL, (IEN | M0) }, + {RGMII0_RXD3, (IEN | M0) }, + {RGMII0_RXD2, (IEN | M0) }, + {RGMII0_RXD1, (IEN | M0) }, + {RGMII0_RXD0, (IEN | M0) }, + {USB1_DRVVBUS, (M0 | FSC) }, + {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */ +}; +#endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 37df7b2..6522241 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -96,18 +96,6 @@ int board_late_init(void) return 0; } -/** - * @brief misc_init_r - Configure EVM board specific configurations - * such as power configurations, ethernet initialization as phase2 of - * boot sequence - * - * @return 0 - */ -int misc_init_r(void) -{ - return 0; -} - static void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size) { diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 7276014..4824077 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -130,8 +130,8 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */ {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */ {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */ - {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */ - {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */ + {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[0] */ + {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[1] */ {GPMC_A18, (M1)}, /* QSPI1_SCLK */ {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */ {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */ diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 81dd081..3f93d9c 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -20,6 +20,7 @@ #include <asm/arch/mmc_host_def.h> #include <asm/gpio.h> #include <i2c.h> +#include <twl4030.h> #include <asm/mach-types.h> #include <linux/mtd/nand.h> #include "evm.h" @@ -264,3 +265,10 @@ int board_mmc_init(bd_t *bis) return omap_mmc_init(0, 0, 0, -1, -1); } #endif + +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index ff7bc4b..04ec675 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -114,7 +114,7 @@ u32 spl_boot_device(void) #endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { int lpae; char *env; @@ -217,6 +217,8 @@ void ft_board_setup(void *blob, bd_t *bd) } } } + + return 0; } void ft_board_setup_ex(void *blob, bd_t *bd) diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c index 957940d..7171363 100644 --- a/board/ti/sdp3430/sdp.c +++ b/board/ti/sdp3430/sdp.c @@ -195,4 +195,9 @@ int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} #endif diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index bcbee73..b978044 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -124,6 +124,13 @@ int board_mmc_init(bd_t *bis) } #endif +#if defined(CONFIG_GENERIC_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif + #if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD) /* * Routine: board_eth_init diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c index a1f56cd..e9363ea 100644 --- a/board/tqc/tqm5200/tqm5200.c +++ b/board/tqc/tqm5200/tqm5200.c @@ -863,12 +863,14 @@ int board_get_height (void) #endif /* CONFIG_VIDEO_SM501 */ #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #if defined(CONFIG_VIDEO) fdt_add_edid(blob, "smi,sm501", edid_buf); #endif + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index 814fcb2..d891a38 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -414,12 +414,14 @@ static void set_ddr_config(void) { } #ifdef CONFIG_OF_BOARD_SETUP -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif /* CONFIG_PCI */ + + return 0; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 9ce2a57..3b5230a 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -674,10 +674,12 @@ void ft_blob_update (void *blob, bd_t *bd) } } -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); ft_blob_update(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c index fd1bd59..c9e163e 100644 --- a/board/tqc/tqma6/tqma6.c +++ b/board/tqc/tqma6/tqma6.c @@ -17,6 +17,7 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/spi.h> #include <common.h> #include <fsl_esdhc.h> #include <libfdt.h> @@ -50,7 +51,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = imx_ddr_size(); return 0; } @@ -180,8 +181,14 @@ static struct i2c_pads_info tqma6_i2c3_pads = { static void tqma6_setup_i2c(void) { - /* use logical index for bus, e.g. I2C1 -> 0 */ - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads); + int ret; + /* + * use logical index for bus, e.g. I2C1 -> 0 + * warn on error + */ + ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads); + if (ret) + printf("setup I2C3 failed: %d\n", ret); } int board_early_init_f(void) @@ -259,12 +266,14 @@ int checkboard(void) * Device Tree Support */ #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { /* bring in eMMC dsr settings */ do_fixup_by_path_u32(blob, "/soc/aips-bus@02100000/usdhc@02198000", "dsr", tqma6_emmc_dsr, 2); tqma6_bb_ft_board_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c index fd59287..6f4cffd 100644 --- a/board/tqc/tqma6/tqma6_mba6.c +++ b/board/tqc/tqma6/tqma6_mba6.c @@ -224,8 +224,14 @@ static struct i2c_pads_info mba6_i2c1_pads = { static void mba6_setup_i2c(void) { - /* use logical index for bus, e.g. I2C1 -> 0 */ - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads); + int ret; + /* + * use logical index for bus, e.g. I2C1 -> 0 + * warn on error + */ + ret = setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads); + if (ret) + printf("setup I2C1 failed: %d\n", ret); } diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index c4feef8..7f24a30 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -192,11 +192,13 @@ void pci_init_board(void) #endif #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + + return 0; } #endif diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 3c8b7a5..1075c65 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -144,7 +144,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - s32 status = 0; + int ret; u32 index = 0; /* @@ -173,13 +173,15 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } static int mx6_rgmii_rework(struct phy_device *phydev) diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c index b7ad349..0028870 100644 --- a/board/xes/xpedite517x/xpedite517x.c +++ b/board/xes/xpedite517x/xpedite517x.c @@ -69,11 +69,13 @@ phys_size_t initdram(int board_type) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { #ifdef CONFIG_PCI ft_board_pci_setup(blob, bd); #endif ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/xes/xpedite520x/xpedite520x.c b/board/xes/xpedite520x/xpedite520x.c index aa9e99d..6a3df52 100644 --- a/board/xes/xpedite520x/xpedite520x.c +++ b/board/xes/xpedite520x/xpedite520x.c @@ -70,11 +70,13 @@ int board_early_init_r(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { #ifdef CONFIG_PCI ft_board_pci_setup(blob, bd); #endif ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/xes/xpedite537x/xpedite537x.c b/board/xes/xpedite537x/xpedite537x.c index efd563b..41419fe 100644 --- a/board/xes/xpedite537x/xpedite537x.c +++ b/board/xes/xpedite537x/xpedite537x.c @@ -72,11 +72,13 @@ int board_early_init_r(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { #ifdef CONFIG_PCI ft_board_pci_setup(blob, bd); #endif ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/board/xes/xpedite550x/xpedite550x.c b/board/xes/xpedite550x/xpedite550x.c index e64d682..1f05150 100644 --- a/board/xes/xpedite550x/xpedite550x.c +++ b/board/xes/xpedite550x/xpedite550x.c @@ -72,11 +72,13 @@ int board_early_init_r(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { #ifdef CONFIG_PCI ft_board_pci_setup(blob, bd); #endif ft_cpu_setup(blob, bd); + + return 0; } #endif diff --git a/common/Kconfig b/common/Kconfig index 216a8de..fd84fa0 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1,34 +1,316 @@ menu "Command line interface" depends on !SPL_BUILD +config HUSH_PARSER + bool "Use hush shell" + select SYS_HUSH_PARSER + help + This option enables the "hush" shell (from Busybox) as command line + interpreter, thus enabling powerful command line syntax like + if...then...else...fi conditionals or `&&' and '||' + constructs ("shell scripts"). + + If disabled, you get the old, much simpler behaviour with a somewhat + smaller memory footprint. + +config SYS_HUSH_PARSER + bool + help + Backward compatibility. + +comment "Commands" + +menu "Info commands" + +config CMD_BDI + bool "bdinfo" + help + Print board info + +config CMD_CONSOLE + bool "coninfo" + help + Print console devices and information. + +config CMD_LICENSE + bool "license" + help + Print GPL license text + +endmenu + +menu "Boot commands" + +config CMD_BOOTD + bool "bootd" + help + Run the command stored in the environment "bootcmd", i.e. + "bootd" does the same thing as "run bootcmd". + config CMD_BOOTM - bool "Enable bootm command" + bool "bootm" default y help Boot an application image from the memory. -config CMD_CRC32 - bool "Enable crc32 command" +config CMD_GO + bool "go" default y help - Compute CRC32. + Start an application at a given address. + +config CMD_RUN + bool "run" + help + Run the command in the given environment variable. + +config CMD_IMI + bool "iminfo" + help + Print header information for application image. + +config CMD_IMLS + bool "imls" + help + List all images found in flash + +config CMD_XIMG + bool "imxtract" + help + Extract a part of a multi-image. + +endmenu + +menu "Environment commands" config CMD_EXPORTENV - bool "Enable env export command" + bool "env export" default y help Export environments. config CMD_IMPORTENV - bool "Enable env import command" + bool "env import" default y help Import environments. -config CMD_GO - bool "Enable go command" +config CMD_EDITENV + bool "editenv" + help + Edit environment variable. + +config CMD_SAVEENV + bool "saveenv" + help + Run the command in the given environment variable. + +endmenu + +menu "Memory commands" + +config CMD_MEMORY + bool "md, mm, nm, mw, cp, cmp, base, loop" + help + Memeory commands. + md - memory display + mm - memory modify (auto-incrementing address) + nm - memory modify (constant address) + mw - memory write (fill) + cp - memory copy + cmp - memory compare + base - print or set address offset + loop - initinite loop on address range + +config CMD_CRC32 + bool "crc32" default y help - Start an application at a given address. + Compute CRC32. + +config LOOPW + bool "loopw" + help + Infinite write loop on address range + +config CMD_MEMTEST + bool "crc32" + help + Simple RAM read/write test. + +config CMD_MX_CYCLIC + bool "mdc, mwc" + help + mdc - memory display cyclic + mwc - memory write cyclic + +config CMD_MEMINFO + bool "meminfo" + help + Display memory information. + +endmenu + +menu "Device access commands" + +config CMD_LOADB + bool "loadb" + help + Load a binary file over serial line. + +config CMD_LOADS + bool "loads" + help + Load an S-Record file over serial line + +config CMD_FLASH + bool "flinfo, erase, protect" + help + NOR flash support. + flinfo - print FLASH memory information + erase - FLASH memory + protect - enable or disable FLASH write protection + +config CMD_NAND + bool "nand" + help + NAND support. + +config CMD_SPI + bool "sspi" + help + SPI utility command. + +config CMD_I2C + bool "i2c" + help + I2C support. + +config CMD_USB + bool "usb" + help + USB support. + +config CMD_FPGA + bool "fpga" + help + FPGA support. + +endmenu + + +menu "Shell scripting commands" + +config CMD_ECHO + bool "echo" + help + Echo args to console + +config CMD_ITEST + bool "itest" + help + Return true/false on integer compare. + +config CMD_SOURCE + bool "source" + help + Run script from memory + +endmenu + +menu "Network commands" + +config CMD_NET + bool "bootp, tftpboot" + help + Network commands. + bootp - boot image via network using BOOTP/TFTP protocol + tftpboot - boot image via network using TFTP protocol + +config CMD_TFTPPUT + bool "tftp put" + help + TFTP put command, for uploading files to a server + +config CMD_TFTPSRV + bool "tftpsrv" + help + Act as a TFTP server and boot the first received file + +config CMD_RARP + bool "rarpboot" + help + Boot image via network using RARP/TFTP protocol + +config CMD_DHCP + bool "dhcp" + help + Boot image via network using DHCP/TFTP protocol + +config CMD_NFS + bool "nfs" + help + Boot image via network using NFS protocol. + +config CMD_PING + bool "ping" + help + Send ICMP ECHO_REQUEST to network host + +config CMD_CDP + bool "cdp" + help + Perform CDP network configuration + +config CMD_SNTP + bool "sntp" + help + Synchronize RTC via network + +config CMD_DNS + bool "dns" + help + Lookup the IP of a hostname + +config CMD_DNS + bool "dns" + help + Lookup the IP of a hostname + +config CMD_LINK_LOCAL + bool "linklocal" + help + Acquire a network IP address using the link-local protocol + +endmenu + +menu "Misc commands" + +config CMD_TIME + bool "time" + help + Run commands and summarize execution time. + +# TODO: rename to CMD_SLEEP +config CMD_MISC + bool "sleep" + help + Delay execution for some time + +config CMD_TIMER + bool "timer" + help + Access the system timer. + +config CMD_SETGETDCR + bool "getdcr, setdcr, getidcr, setidcr" + depends on 4xx + help + getdcr - Get an AMCC PPC 4xx DCR's value + setdcr - Set an AMCC PPC 4xx DCR's value + getidcr - Get a register value via indirect DCR addressing + setidcr - Set a register value via indirect DCR addressing + +endmenu endmenu diff --git a/common/Makefile b/common/Makefile index 6cc4de8..c668a2f 100644 --- a/common/Makefile +++ b/common/Makefile @@ -8,22 +8,12 @@ # core ifndef CONFIG_SPL_BUILD obj-y += main.o -obj-y += command.o obj-y += exports.o obj-y += hash.o ifdef CONFIG_SYS_HUSH_PARSER obj-y += cli_hush.o endif -# We always have this since drivers/ddr/fs/interactive.c needs it -obj-y += cli_simple.o - -obj-y += cli.o -obj-y += cli_readline.o -obj-y += s_record.o -obj-y += xyzModem.o -obj-y += cmd_disk.o - # This option is not just y/n - it can have a numeric value ifdef CONFIG_BOOTDELAY obj-y += autoboot.o @@ -188,6 +178,7 @@ obj-y += usb.o usb_hub.o obj-$(CONFIG_USB_STORAGE) += usb_storage.o endif obj-$(CONFIG_CMD_FASTBOOT) += cmd_fastboot.o +obj-$(CONFIG_CMD_FS_UUID) += cmd_fs_uuid.o obj-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o obj-$(CONFIG_CMD_THOR_DOWNLOAD) += cmd_thordown.o @@ -251,6 +242,9 @@ obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o obj-y += console.o obj-$(CONFIG_CROS_EC) += cros_ec.o obj-y += dlmalloc.o +ifdef CONFIG_SYS_MALLOC_F_LEN +obj-y += malloc_simple.o +endif obj-y += image.o obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o obj-$(CONFIG_OF_LIBFDT) += image-fdt.o @@ -268,4 +262,14 @@ endif obj-$(CONFIG_CMD_BLOB) += cmd_blob.o +# We always have this since drivers/ddr/fs/interactive.c needs it +obj-y += cli_simple.o + +obj-y += cli.o +obj-y += cli_readline.o +obj-y += command.o +obj-y += s_record.o +obj-y += xyzModem.o +obj-y += cmd_disk.o + CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null) diff --git a/common/board_f.c b/common/board_f.c index b5bebc9..98c9c72 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -142,17 +142,19 @@ static int init_baud_rate(void) static int display_text_info(void) { #ifndef CONFIG_SANDBOX - ulong bss_start, bss_end; + ulong bss_start, bss_end, text_base; bss_start = (ulong)&__bss_start; bss_end = (ulong)&__bss_end; - debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n", #ifdef CONFIG_SYS_TEXT_BASE - CONFIG_SYS_TEXT_BASE, bss_start, bss_end); + text_base = CONFIG_SYS_TEXT_BASE; #else - CONFIG_SYS_MONITOR_BASE, bss_start, bss_end); + text_base = CONFIG_SYS_MONITOR_BASE; #endif + + debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", + text_base, bss_start, bss_end); #endif #ifdef CONFIG_MODEM_SUPPORT @@ -285,7 +287,7 @@ static int read_fdt_from_file(void) struct sandbox_state *state = state_get_current(); const char *fname = state->fdt_fname; void *blob; - ssize_t size; + loff_t size; int err; int fd; @@ -298,10 +300,10 @@ static int read_fdt_from_file(void) return -EINVAL; } - size = os_get_filesize(fname); - if (size < 0) { + err = os_get_filesize(fname, &size); + if (err < 0) { printf("Failed to file FDT file '%s'\n", fname); - return -ENOENT; + return err; } fd = os_open(fname, OS_O_RDONLY); if (fd < 0) { @@ -812,22 +814,16 @@ static init_fnc_t init_sequence_f[] = { setup_mon_len, setup_fdt, trace_early_init, + initf_malloc, #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) /* TODO: can this go into arch_cpu_init()? */ probecpu, #endif arch_cpu_init, /* basic arch cpu dependent setup */ -#ifdef CONFIG_X86 - cpu_init_f, /* TODO(sjg@chromium.org): remove */ -# ifdef CONFIG_OF_CONTROL - find_fdt, /* TODO(sjg@chromium.org): remove */ -# endif -#endif mark_bootstage, #ifdef CONFIG_OF_CONTROL fdtdec_check_fdt, #endif - initf_malloc, initf_dm, #if defined(CONFIG_BOARD_EARLY_INIT_F) board_early_init_f, @@ -903,13 +899,9 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_HARD_SPI) init_func_spi, #endif -#ifdef CONFIG_X86 - dram_init_f, /* configure available RAM banks */ - calculate_relocation_address, -#endif announce_dram_init, /* TODO: unify all these dram functions? */ -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) || defined(CONFIG_X86) dram_init, /* configure available RAM banks */ #endif #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) diff --git a/common/board_r.c b/common/board_r.c index 7c33900..4eb7a02 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -99,7 +99,8 @@ static int initr_trace(void) static int initr_reloc(void) { - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + /* tell others: relocation done */ + gd->flags |= GD_FLG_RELOC | GD_FLG_FULL_MALLOC_INIT; bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r"); return 0; @@ -290,26 +291,14 @@ static int initr_flash(void) { ulong flash_size = 0; bd_t *bd = gd->bd; - int ok; puts("Flash: "); - if (board_flash_wp_on()) { + if (board_flash_wp_on()) printf("Uninitialized - Write Protect On\n"); - /* Since WP is on, we can't find real size. Set to 0 */ - ok = 1; - } else { + else flash_size = flash_init(); - ok = flash_size > 0; - } - if (!ok) { - puts("*** failed ***\n"); -#ifdef CONFIG_PPC - /* Why does PPC do this? */ - hang(); -#endif - return -1; - } + print_size(flash_size, ""); #ifdef CONFIG_SYS_FLASH_CHECKSUM /* @@ -453,24 +442,6 @@ static int initr_env(void) return 0; } -#ifdef CONFIG_HERMES -static int initr_hermes(void) -{ - if ((gd->board_type >> 16) == 2) - gd->bd->bi_ethspeed = gd->board_type & 0xFFFF; - else - gd->bd->bi_ethspeed = 0xFFFF; - return 0; -} - -static int initr_hermes_start(void) -{ - if (gd->bd->bi_ethspeed != 0xFFFF) - hermes_start_lxt980((int) gd->bd->bi_ethspeed); - return 0; -} -#endif - #ifdef CONFIG_SC3 /* TODO: with new initcalls, move this into the driver */ extern void sc3_read_eeprom(void); @@ -774,7 +745,7 @@ init_fnc_t init_sequence_r[] = { initr_flash, #endif INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_PPC) || defined(CONFIG_X86) +#if defined(CONFIG_PPC) /* initialize higher level parts of CPU like time base and timers */ cpu_init_r, #endif @@ -802,9 +773,6 @@ init_fnc_t init_sequence_r[] = { #ifdef CONFIG_SC3 initr_sc3_read_eeprom, #endif -#ifdef CONFIG_HERMES - initr_hermes, -#endif #if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET) mac_read_from_eeprom, #endif @@ -830,18 +798,12 @@ init_fnc_t init_sequence_r[] = { #ifdef CONFIG_MISC_INIT_R misc_init_r, /* miscellaneous platform-dependent init */ #endif -#ifdef CONFIG_HERMES - initr_hermes_start, -#endif INIT_FUNC_WATCHDOG_RESET #ifdef CONFIG_CMD_KGDB initr_kgdb, #endif -#ifdef CONFIG_X86 - board_early_init_r, -#endif interrupt_init, -#if defined(CONFIG_ARM) || defined(CONFIG_x86) +#if defined(CONFIG_ARM) initr_enable_interrupts, #endif #ifdef CONFIG_X86 diff --git a/common/cli_hush.c b/common/cli_hush.c index d643912..296542f 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -3217,7 +3217,7 @@ static int parse_stream_outer(struct in_str *inp, int flag) } b_free(&temp); /* loop on syntax errors, return on EOF */ - } while (rcode != 1 && !(flag & FLAG_EXIT_FROM_LOOP) && + } while (rcode != -1 && !(flag & FLAG_EXIT_FROM_LOOP) && (inp->peek != static_peek || b_peek(inp))); #ifndef __U_BOOT__ return 0; diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 3d37a86..f0b713c 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -144,9 +144,6 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(5); #endif -#ifdef CONFIG_HERMES - print_mhz("ethspeed", bd->bi_ethspeed); -#endif printf("IP addr = %s\n", getenv("ipaddr")); printf("baudrate = %6u bps\n", gd->baudrate); print_num("relocaddr", gd->relocaddr); diff --git a/common/cmd_elf.c b/common/cmd_elf.c index 42a5296..58b61c2 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -210,9 +210,9 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ bootline = getenv("bootargs"); if (bootline) { - memcpy((void *) bootaddr, bootline, - max(strlen(bootline), 255)); - flush_cache(bootaddr, max(strlen(bootline), 255)); + memcpy((void *)bootaddr, bootline, + max(strlen(bootline), (size_t)255)); + flush_cache(bootaddr, max(strlen(bootline), (size_t)255)); } else { sprintf(build_buf, CONFIG_SYS_VXWORKS_BOOT_DEVICE); tmp = getenv("bootfile"); @@ -240,9 +240,9 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) CONFIG_SYS_VXWORKS_ADD_PARAMS); #endif - memcpy((void *) bootaddr, build_buf, - max(strlen(build_buf), 255)); - flush_cache(bootaddr, max(strlen(build_buf), 255)); + memcpy((void *)bootaddr, build_buf, + max(strlen(build_buf), (size_t)255)); + flush_cache(bootaddr, max(strlen(build_buf), (size_t)255)); } /* diff --git a/common/cmd_ext4.c b/common/cmd_ext4.c index ecfc6d3..19423d1 100644 --- a/common/cmd_ext4.c +++ b/common/cmd_ext4.c @@ -61,61 +61,16 @@ int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) #if defined(CONFIG_CMD_EXT4_WRITE) int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]) + char *const argv[]) { - const char *filename = "/"; - int dev, part; - unsigned long ram_address; - unsigned long file_size; - disk_partition_t info; - block_dev_desc_t *dev_desc; - - if (argc < 6) - return cmd_usage(cmdtp); - - part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); - if (part < 0) - return 1; - - dev = dev_desc->dev; - - /* get the filename */ - filename = argv[4]; - - /* get the address in hexadecimal format (string to int) */ - ram_address = simple_strtoul(argv[3], NULL, 16); - - /* get the filesize in hexadecimal format */ - file_size = simple_strtoul(argv[5], NULL, 16); - - /* set the device as block device */ - ext4fs_set_blk_dev(dev_desc, &info); - - /* mount the filesystem */ - if (!ext4fs_mount(info.size)) { - printf("Bad ext4 partition %s %d:%d\n", argv[1], dev, part); - goto fail; - } - - /* start write */ - if (ext4fs_write(filename, (unsigned char *)ram_address, file_size)) { - printf("** Error ext4fs_write() **\n"); - goto fail; - } - ext4fs_close(); - - return 0; - -fail: - ext4fs_close(); - - return 1; + return do_save(cmdtp, flag, argc, argv, FS_TYPE_EXT); } -U_BOOT_CMD(ext4write, 6, 1, do_ext4_write, - "create a file in the root directory", - "<interface> <dev[:part]> <addr> <absolute filename path> [sizebytes]\n" - " - create a file in / directory"); +U_BOOT_CMD(ext4write, 7, 1, do_ext4_write, + "create a file in the root directory", + "<interface> <dev[:part]> <addr> <absolute filename path>\n" + " [sizebytes] [file offset]\n" + " - create a file in / directory"); #endif @@ -132,7 +87,7 @@ U_BOOT_CMD(ext4ls, 4, 1, do_ext4_ls, "<interface> <dev[:part]> [directory]\n" " - list files from 'dev' on 'interface' in a 'directory'"); -U_BOOT_CMD(ext4load, 6, 0, do_ext4_load, +U_BOOT_CMD(ext4load, 7, 0, do_ext4_load, "load binary file from a Ext4 filesystem", "<interface> [<dev[:part]> [addr [filename [bytes [pos]]]]]\n" " - load binary file 'filename' from 'dev' on 'interface'\n" diff --git a/common/cmd_fat.c b/common/cmd_fat.c index 633fbf1..c00fb28 100644 --- a/common/cmd_fat.c +++ b/common/cmd_fat.c @@ -100,7 +100,8 @@ U_BOOT_CMD( static int do_fat_fswrite(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - long size; + loff_t size; + int ret; unsigned long addr; unsigned long count; block_dev_desc_t *dev_desc = NULL; @@ -127,15 +128,15 @@ static int do_fat_fswrite(cmd_tbl_t *cmdtp, int flag, count = simple_strtoul(argv[5], NULL, 16); buf = map_sysmem(addr, count); - size = file_fat_write(argv[4], buf, count); + ret = file_fat_write(argv[4], buf, 0, count, &size); unmap_sysmem(buf); - if (size == -1) { + if (ret < 0) { printf("\n** Unable to write \"%s\" from %s %d:%d **\n", argv[4], argv[1], dev, part); return 1; } - printf("%ld bytes written\n", size); + printf("%llu bytes written\n", size); return 0; } diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index 5640ded..25b4675 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -566,8 +566,27 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #ifdef CONFIG_OF_BOARD_SETUP /* Call the board-specific fixup routine */ - else if (strncmp(argv[1], "boa", 3) == 0) - ft_board_setup(working_fdt, gd->bd); + else if (strncmp(argv[1], "boa", 3) == 0) { + int err = ft_board_setup(working_fdt, gd->bd); + + if (err) { + printf("Failed to update board information in FDT: %s\n", + fdt_strerror(err)); + return CMD_RET_FAILURE; + } + } +#endif +#ifdef CONFIG_OF_SYSTEM_SETUP + /* Call the board-specific fixup routine */ + else if (strncmp(argv[1], "sys", 3) == 0) { + int err = ft_system_setup(working_fdt, gd->bd); + + if (err) { + printf("Failed to add system information to FDT: %s\n", + fdt_strerror(err)); + return CMD_RET_FAILURE; + } + } #endif /* Create a chosen node */ else if (strncmp(argv[1], "cho", 3) == 0) { @@ -1008,6 +1027,9 @@ static char fdt_help_text[] = #ifdef CONFIG_OF_BOARD_SETUP "fdt boardsetup - Do board-specific set up\n" #endif +#ifdef CONFIG_OF_SYSTEM_SETUP + "fdt systemsetup - Do system-specific set up\n" +#endif "fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr> and make it active\n" "fdt resize - Resize fdt to size + padding to 4k addr\n" "fdt print <path> [<prop>] - Recursive print starting at <path>\n" diff --git a/common/cmd_fpgad.c b/common/cmd_fpgad.c index 1b25ed8..1f1d00f 100644 --- a/common/cmd_fpgad.c +++ b/common/cmd_fpgad.c @@ -31,7 +31,8 @@ int do_fpga_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) unsigned int fpga; ulong addr, length; int rc = 0; - u16 linebuf[DISP_LINE_LEN/sizeof(u16)]; + u16 linebuf[DISP_LINE_LEN/sizeof(u16)]; + ulong nbytes; /* * We use the last specified parameters, unless new ones are @@ -63,13 +64,28 @@ int do_fpga_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) length = simple_strtoul(argv[3], NULL, 16); } - /* Print the lines. */ - for (k = 0; k < DISP_LINE_LEN / sizeof(u16); ++k) - fpga_get_reg(fpga, (u16 *)fpga_ptr[fpga] + k, k * sizeof(u16), - &linebuf[k]); - print_buffer(addr, (void *)linebuf, sizeof(u16), - length, DISP_LINE_LEN / sizeof(u16)); - addr += sizeof(u16)*length; + nbytes = length * sizeof(u16); + do { + ulong linebytes = (nbytes > DISP_LINE_LEN) ? + DISP_LINE_LEN : nbytes; + + for (k = 0; k < linebytes / sizeof(u16); ++k) + fpga_get_reg(fpga, + (u16 *)fpga_ptr[fpga] + addr + / sizeof(u16) + k, + addr + k * sizeof(u16), + &linebuf[k]); + print_buffer(addr, (void *)linebuf, sizeof(u16), + linebytes / sizeof(u16), + DISP_LINE_LEN / sizeof(u16)); + + nbytes -= linebytes; + addr += linebytes; + if (ctrlc()) { + rc = 1; + break; + } + } while (nbytes > 0); dp_last_fpga = fpga; dp_last_addr = addr; diff --git a/common/cmd_fs.c b/common/cmd_fs.c index 6754340..0d9da11 100644 --- a/common/cmd_fs.c +++ b/common/cmd_fs.c @@ -51,6 +51,23 @@ U_BOOT_CMD( " If 'pos' is 0 or omitted, the file is read from the start." ) +static int do_save_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + return do_save(cmdtp, flag, argc, argv, FS_TYPE_ANY); +} + +U_BOOT_CMD( + save, 7, 0, do_save_wrapper, + "save file to a filesystem", + "<interface> <dev[:part]> <addr> <filename> bytes [pos]\n" + " - Save binary file 'filename' to partition 'part' on device\n" + " type 'interface' instance 'dev' from addr 'addr' in memory.\n" + " 'bytes' gives the size to save in bytes and is mandatory.\n" + " 'pos' gives the file byte position to start writing to.\n" + " If 'pos' is 0 or omitted, the file is written from the start." +) + static int do_ls_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/common/cmd_fs_uuid.c b/common/cmd_fs_uuid.c new file mode 100644 index 0000000..613f3a4 --- /dev/null +++ b/common/cmd_fs_uuid.c @@ -0,0 +1,26 @@ +/* + * cmd_fs_uuid.c -- fsuuid command + * + * Copyright (C) 2014, Bachmann electronic GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <fs.h> + +static int do_fs_uuid_wrapper(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + return do_fs_uuid(cmdtp, flag, argc, argv, FS_TYPE_ANY); +} + +U_BOOT_CMD( + fsuuid, 4, 1, do_fs_uuid_wrapper, + "Look up a filesystem UUID", + "<interface> <dev>:<part>\n" + " - print filesystem UUID\n" + "fsuuid <interface> <dev>:<part> <varname>\n" + " - set environment variable to filesystem UUID\n" +); diff --git a/common/cmd_fuse.c b/common/cmd_fuse.c index abab978..d4bc0f6 100644 --- a/common/cmd_fuse.c +++ b/common/cmd_fuse.c @@ -128,7 +128,7 @@ static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) err: puts("ERROR\n"); - return ret; + return CMD_RET_FAILURE; } U_BOOT_CMD( diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 3a75f94..c266b88 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -198,6 +198,19 @@ static uint get_alen(char *arg) return alen; } +enum i2c_err_op { + I2C_ERR_READ, + I2C_ERR_WRITE, +}; + +static int i2c_report_err(int ret, enum i2c_err_op op) +{ + printf("Error %s the chip: %d\n", + op == I2C_ERR_READ ? "reading" : "writing", ret); + + return CMD_RET_FAILURE; +} + /** * do_i2c_read() - Handle the "i2c read" command-line command * @cmdtp: Command data struct pointer @@ -245,7 +258,7 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16); if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) { - puts ("Error reading the chip.\n"); + i2c_report_err(-1, I2C_ERR_READ); return 1; } return 0; @@ -286,8 +299,7 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[ while (length-- > 0) { if (i2c_write(chip, devaddr++, alen, memaddr++, 1) != 0) { - puts("Error writing to the chip.\n"); - return 1; + return i2c_report_err(-1, I2C_ERR_WRITE); } /* * No write delay with FRAM devices. @@ -370,7 +382,7 @@ static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0) - puts ("Error reading the chip.\n"); + i2c_report_err(-1, I2C_ERR_READ); else { printf("%04x:", addr); cp = linebuf; @@ -452,7 +464,7 @@ static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] while (count-- > 0) { if (i2c_write(chip, addr++, alen, &byte, 1) != 0) - puts ("Error writing the chip.\n"); + i2c_report_err(-1, I2C_ERR_WRITE); /* * Wait for the write to complete. The write can take * up to 10mSec (we allow a little more time). @@ -528,7 +540,7 @@ static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] addr++; } if (err > 0) - puts ("Error reading the chip,\n"); + i2c_report_err(-1, I2C_ERR_READ); else printf ("%08lx\n", crc); @@ -601,7 +613,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg do { printf("%08lx:", addr); if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) - puts ("\nError reading the chip,\n"); + i2c_report_err(-1, I2C_ERR_READ); else { data = cpu_to_be32(data); if (size == 1) @@ -644,7 +656,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg */ bootretry_reset_cmd_timeout(); if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) - puts ("Error writing the chip.\n"); + i2c_report_err(-1, I2C_ERR_WRITE); #ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); #endif @@ -783,7 +795,7 @@ static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] */ while (1) { if (i2c_read(chip, addr, alen, bytes, length) != 0) - puts ("Error reading the chip.\n"); + i2c_report_err(-1, I2C_ERR_READ); udelay(delay); } @@ -1341,7 +1353,7 @@ int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) chip = simple_strtoul(argv[1], NULL, 16); if (i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid)) != 0) { - puts("Error reading EDID content.\n"); + i2c_report_err(-1, I2C_ERR_READ); return 1; } diff --git a/common/cmd_md5sum.c b/common/cmd_md5sum.c index 3ac8cc4..d22ace5 100644 --- a/common/cmd_md5sum.c +++ b/common/cmd_md5sum.c @@ -11,6 +11,7 @@ #include <common.h> #include <command.h> #include <u-boot/md5.h> +#include <asm/io.h> /* * Store the resulting sum to an address or variable @@ -79,6 +80,7 @@ int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int verify = 0; int ac; char * const *av; + void *buf; if (argc < 3) return CMD_RET_USAGE; @@ -96,7 +98,9 @@ int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) addr = simple_strtoul(*av++, NULL, 16); len = simple_strtoul(*av++, NULL, 16); - md5_wd((unsigned char *) addr, len, output, CHUNKSZ_MD5); + buf = map_sysmem(addr, len); + md5_wd(buf, len, output, CHUNKSZ_MD5); + unmap_sysmem(buf); if (!verify) { printf("md5 for %08lx ... %08lx ==> ", addr, addr + len - 1); @@ -135,6 +139,7 @@ static int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) unsigned long addr, len; unsigned int i; u8 output[16]; + void *buf; if (argc < 3) return CMD_RET_USAGE; @@ -142,7 +147,10 @@ static int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) addr = simple_strtoul(argv[1], NULL, 16); len = simple_strtoul(argv[2], NULL, 16); - md5_wd((unsigned char *) addr, len, output, CHUNKSZ_MD5); + buf = map_sysmem(addr, len); + md5_wd(buf, len, output, CHUNKSZ_MD5); + unmap_sysmem(buf); + printf("md5 for %08lx ... %08lx ==> ", addr, addr + len - 1); for (i = 0; i < 16; i++) printf("%02x", output[i]); diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 0d50dcf..bcb3ee3 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -19,6 +19,7 @@ #include <dataflash.h> #endif #include <hash.h> +#include <inttypes.h> #include <watchdog.h> #include <asm/io.h> #include <linux/compiler.h> @@ -338,7 +339,8 @@ static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (word1 != word2) { ulong offset = buf1 - base; #ifdef CONFIG_SYS_SUPPORT_64BIT_DATA - printf("%s at 0x%p (%#0*llx) != %s at 0x%p (%#0*llx)\n", + printf("%s at 0x%p (%#0*"PRIx64") != %s at 0x%p (%#0*" + PRIx64 ")\n", type, (void *)(addr1 + offset), size, word1, type, (void *)(addr2 + offset), size, word2); #else @@ -1146,7 +1148,7 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) printf(" %08x", *((u32 *)ptr)); #ifdef CONFIG_SYS_SUPPORT_64BIT_DATA else if (size == 8) - printf(" %016llx", *((u64 *)ptr)); + printf(" %016" PRIx64, *((u64 *)ptr)); #endif else if (size == 2) printf(" %04x", *((u16 *)ptr)); diff --git a/common/cmd_pci.c b/common/cmd_pci.c index a1ba42e..e3a77e3 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -42,12 +42,16 @@ void pci_header_show_brief(pci_dev_t dev); */ void pciinfo(int BusNum, int ShortPCIListing) { + struct pci_controller *hose = pci_bus_to_hose(BusNum); int Device; int Function; unsigned char HeaderType; unsigned short VendorID; pci_dev_t dev; + if (!hose) + return; + printf("Scanning PCI devices on bus %d\n", BusNum); if (ShortPCIListing) { @@ -67,6 +71,9 @@ void pciinfo(int BusNum, int ShortPCIListing) dev = PCI_BDF(BusNum, Device, Function); + if (pci_skip_dev(hose, dev)) + continue; + pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID); if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) continue; diff --git a/common/cmd_sata.c b/common/cmd_sata.c index fc92131..51f6703 100644 --- a/common/cmd_sata.c +++ b/common/cmd_sata.c @@ -48,6 +48,20 @@ int __sata_initialize(void) } int sata_initialize(void) __attribute__((weak,alias("__sata_initialize"))); +__weak int __sata_stop(void) +{ + int i, err = 0; + + for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) + err |= reset_sata(i); + + if (err) + printf("Could not reset some SATA devices\n"); + + return err; +} +int sata_stop(void) __attribute__((weak, alias("__sata_stop"))); + #ifdef CONFIG_PARTITIONS block_dev_desc_t *sata_get_dev(int dev) { @@ -59,8 +73,15 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int rc = 0; - if (argc == 2 && strcmp(argv[1], "init") == 0) + if (argc == 2 && strcmp(argv[1], "stop") == 0) + return sata_stop(); + + if (argc == 2 && strcmp(argv[1], "init") == 0) { + if (sata_curr_device != -1) + sata_stop(); + return sata_initialize(); + } /* If the user has not yet run `sata init`, do it now */ if (sata_curr_device == -1) @@ -185,6 +206,7 @@ U_BOOT_CMD( sata, 5, 1, do_sata, "SATA sub system", "init - init SATA sub system\n" + "sata stop - disable SATA sub system\n" "sata info - show available SATA devices\n" "sata device [dev] - show or set current device\n" "sata part [dev] - print partition table\n" diff --git a/common/cmd_sf.c b/common/cmd_sf.c index 95a6f89..5c788e9 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -18,7 +18,6 @@ static struct spi_flash *flash; - /* * This function computes the length argument for the erase command. * The length on which the command is to operate can be given in two forms: @@ -71,9 +70,9 @@ static ulong bytes_per_second(unsigned int len, ulong start_ms) { /* less accurate but avoids overflow */ if (len >= ((unsigned int) -1) / 1024) - return len / (max(get_timer(start_ms) / 1024, 1)); + return len / (max(get_timer(start_ms) / 1024, 1UL)); else - return 1024 * len / max(get_timer(start_ms), 1); + return 1024 * len / max(get_timer(start_ms), 1UL); } static int do_spi_flash_probe(int argc, char * const argv[]) @@ -223,7 +222,7 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset, ulong last_update = get_timer(0); for (; buf < end && !err_oper; buf += todo, offset += todo) { - todo = min(end - buf, flash->sector_size); + todo = min_t(size_t, end - buf, flash->sector_size); if (get_timer(last_update) > 100) { printf(" \rUpdating, %zu%% %lu B/s", 100 - (end - buf) / scale, @@ -421,7 +420,8 @@ static int spi_flash_test(struct spi_flash *flash, uint8_t *buf, ulong len, for (i = 0; i < len; i++) { if (vbuf[i] != 0xff) { printf("Check failed at %d\n", i); - print_buffer(i, vbuf + i, 1, min(len - i, 0x40), 0); + print_buffer(i, vbuf + i, 1, + min_t(uint, len - i, 0x40), 0); return -1; } } @@ -443,9 +443,11 @@ static int spi_flash_test(struct spi_flash *flash, uint8_t *buf, ulong len, for (i = 0; i < len; i++) { if (buf[i] != vbuf[i]) { printf("Verify failed at %d, good data:\n", i); - print_buffer(i, buf + i, 1, min(len - i, 0x40), 0); + print_buffer(i, buf + i, 1, + min_t(uint, len - i, 0x40), 0); printf("Bad data:\n"); - print_buffer(i, vbuf + i, 1, min(len - i, 0x40), 0); + print_buffer(i, vbuf + i, 1, + min_t(uint, len - i, 0x40), 0); return -1; } } diff --git a/common/console.c b/common/console.c index 4695386..29560c3 100644 --- a/common/console.c +++ b/common/console.c @@ -125,12 +125,12 @@ static int console_setfile(int file, struct stdio_dev * dev) */ switch (file) { case stdin: - gd->jt[XF_getc] = dev->getc; - gd->jt[XF_tstc] = dev->tstc; + gd->jt[XF_getc] = getc; + gd->jt[XF_tstc] = tstc; break; case stdout: - gd->jt[XF_putc] = dev->putc; - gd->jt[XF_puts] = dev->puts; + gd->jt[XF_putc] = putc; + gd->jt[XF_puts] = puts; gd->jt[XF_printf] = printf; break; } diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 991229d..6453ee9 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -2184,17 +2184,8 @@ Void_t* mALLOc(bytes) size_t bytes; INTERNAL_SIZE_T nb; #ifdef CONFIG_SYS_MALLOC_F_LEN - if (gd && !(gd->flags & GD_FLG_RELOC)) { - ulong new_ptr; - void *ptr; - - new_ptr = gd->malloc_ptr + bytes; - if (new_ptr > gd->malloc_limit) - panic("Out of pre-reloc memory"); - ptr = map_sysmem(gd->malloc_base + gd->malloc_ptr, bytes); - gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr)); - return ptr; - } + if (gd && !(gd->flags & GD_FLG_FULL_MALLOC_INIT)) + return malloc_simple(bytes); #endif /* check if mem_malloc_init() was run */ @@ -2462,7 +2453,7 @@ void fREe(mem) Void_t* mem; #ifdef CONFIG_SYS_MALLOC_F_LEN /* free() is a no-op - all the memory will be freed on relocation */ - if (!(gd->flags & GD_FLG_RELOC)) + if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) return; #endif @@ -2618,7 +2609,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; if (oldmem == NULL) return mALLOc(bytes); #ifdef CONFIG_SYS_MALLOC_F_LEN - if (!(gd->flags & GD_FLG_RELOC)) { + if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) { /* This is harder to support and should not be needed */ panic("pre-reloc realloc() is not supported"); } @@ -2970,7 +2961,7 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size; else { #ifdef CONFIG_SYS_MALLOC_F_LEN - if (!(gd->flags & GD_FLG_RELOC)) { + if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) { MALLOC_ZERO(mem, sz); return mem; } diff --git a/common/env_fat.c b/common/env_fat.c index 8db0160..e4c8489 100644 --- a/common/env_fat.c +++ b/common/env_fat.c @@ -41,6 +41,7 @@ int saveenv(void) disk_partition_t info; int dev, part; int err; + loff_t size; err = env_export(&env_new); if (err) @@ -59,7 +60,8 @@ int saveenv(void) return 1; } - err = file_fat_write(FAT_ENV_FILE, (void *)&env_new, sizeof(env_t)); + err = file_fat_write(FAT_ENV_FILE, (void *)&env_new, 0, sizeof(env_t), + &size); if (err == -1) { printf("\n** Unable to write \"%s\" from %s%d:%d **\n", FAT_ENV_FILE, FAT_ENV_INTERFACE, dev, part); diff --git a/common/env_nand.c b/common/env_nand.c index 749605f..9c9bb82 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -132,7 +132,7 @@ static int writeenv(size_t offset, u_char *buf) u_char *char_ptr; blocksize = nand_info[0].erasesize; - len = min(blocksize, CONFIG_ENV_SIZE); + len = min(blocksize, (size_t)CONFIG_ENV_SIZE); while (amount_saved < CONFIG_ENV_SIZE && offset < end) { if (nand_block_isbad(&nand_info[0], offset)) { @@ -244,7 +244,7 @@ static int readenv(size_t offset, u_char *buf) if (!blocksize) return 1; - len = min(blocksize, CONFIG_ENV_SIZE); + len = min(blocksize, (size_t)CONFIG_ENV_SIZE); while (amount_loaded < CONFIG_ENV_SIZE && offset < end) { if (nand_block_isbad(&nand_info[0], offset)) { diff --git a/common/fdt_support.c b/common/fdt_support.c index 3f64156..8266bca 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <inttypes.h> #include <stdio_dev.h> #include <linux/ctype.h> #include <linux/types.h> @@ -16,22 +17,6 @@ #include <fdt_support.h> #include <exports.h> -/* - * Get cells len in bytes - * if #NNNN-cells property is 2 then len is 8 - * otherwise len is 4 - */ -static int get_cells_len(const void *fdt, const char *nr_cells_name) -{ - const fdt32_t *cell; - - cell = fdt_getprop(fdt, 0, nr_cells_name, NULL); - if (cell && fdt32_to_cpu(*cell) == 2) - return 8; - - return 4; -} - /** * fdt_getprop_u32_default_node - Return a node's property or a default * @@ -113,7 +98,8 @@ int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, } /** - * fdt_find_or_add_subnode - find or possibly add a subnode of a given node + * fdt_find_or_add_subnode() - find or possibly add a subnode of a given node + * * @fdt: pointer to the device tree blob * @parentoffset: structure block offset of a node * @name: name of the subnode to locate @@ -121,8 +107,7 @@ int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, * fdt_subnode_offset() finds a subnode of the node with a given name. * If the subnode does not exist, it will be created. */ -static int fdt_find_or_add_subnode(void *fdt, int parentoffset, - const char *name) +int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name) { int offset; @@ -246,7 +231,7 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end) return err; } - is_u64 = (get_cells_len(fdt, "#address-cells") == 8); + is_u64 = (fdt_address_cells(fdt, 0) == 2); err = fdt_setprop_uxx(fdt, nodeoffset, "linux,initrd-start", (uint64_t)initrd_start, is_u64); @@ -382,26 +367,26 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat, /* * fdt_pack_reg - pack address and size array into the "reg"-suitable stream */ -static int fdt_pack_reg(const void *fdt, void *buf, uint64_t *address, - uint64_t *size, int n) +static int fdt_pack_reg(const void *fdt, void *buf, u64 *address, u64 *size, + int n) { int i; - int address_len = get_cells_len(fdt, "#address-cells"); - int size_len = get_cells_len(fdt, "#size-cells"); + int address_cells = fdt_address_cells(fdt, 0); + int size_cells = fdt_size_cells(fdt, 0); char *p = buf; for (i = 0; i < n; i++) { - if (address_len == 8) + if (address_cells == 2) *(fdt64_t *)p = cpu_to_fdt64(address[i]); else *(fdt32_t *)p = cpu_to_fdt32(address[i]); - p += address_len; + p += 4 * address_cells; - if (size_len == 8) + if (size_cells == 2) *(fdt64_t *)p = cpu_to_fdt64(size[i]); else *(fdt32_t *)p = cpu_to_fdt32(size[i]); - p += size_len; + p += 4 * size_cells; } return p - (char *)buf; @@ -930,8 +915,6 @@ void fdt_del_node_and_alias(void *blob, const char *alias) fdt_delprop(blob, off, alias); } -#define PRu64 "%llx" - /* Max address size we deal with */ #define OF_MAX_ADDR_CELLS 4 #define OF_BAD_ADDR ((u64)-1) @@ -968,13 +951,8 @@ void of_bus_default_count_cells(void *blob, int parentoffset, { const fdt32_t *prop; - if (addrc) { - prop = fdt_getprop(blob, parentoffset, "#address-cells", NULL); - if (prop) - *addrc = be32_to_cpup(prop); - else - *addrc = 2; - } + if (addrc) + *addrc = fdt_address_cells(blob, parentoffset); if (sizec) { prop = fdt_getprop(blob, parentoffset, "#size-cells", NULL); @@ -994,8 +972,8 @@ static u64 of_bus_default_map(fdt32_t *addr, const fdt32_t *range, s = of_read_number(range + na + pna, ns); da = of_read_number(addr, na); - debug("OF: default map, cp="PRu64", s="PRu64", da="PRu64"\n", - cp, s, da); + debug("OF: default map, cp=%" PRIu64 ", s=%" PRIu64 + ", da=%" PRIu64 "\n", cp, s, da); if (da < cp || da >= (cp + s)) return OF_BAD_ADDR; @@ -1073,7 +1051,7 @@ static int of_translate_one(void * blob, int parent, struct of_bus *bus, finish: of_dump_addr("OF: parent translation for:", addr, pna); - debug("OF: with offset: "PRu64"\n", offset); + debug("OF: with offset: %" PRIu64 "\n", offset); /* Translate it into parent bus space */ return pbus->translate(addr, offset, pna); @@ -1199,7 +1177,8 @@ int fdt_node_offset_by_compat_reg(void *blob, const char *compat, */ int fdt_alloc_phandle(void *blob) { - int offset, phandle = 0; + int offset; + uint32_t phandle = 0; for (offset = fdt_next_node(blob, -1, NULL); offset >= 0; offset = fdt_next_node(blob, offset, NULL)) { @@ -1401,9 +1380,9 @@ int fdt_verify_alias_address(void *fdt, int anode, const char *alias, u64 addr) dt_addr = fdt_translate_address(fdt, node, reg); if (addr != dt_addr) { - printf("Warning: U-Boot configured device %s at address %llx,\n" - " but the device tree has it address %llx.\n", - alias, addr, dt_addr); + printf("Warning: U-Boot configured device %s at address %" + PRIx64 ",\n but the device tree has it address %" + PRIx64 ".\n", alias, addr, dt_addr); return 0; } @@ -1419,11 +1398,7 @@ u64 fdt_get_base_address(void *fdt, int node) u32 naddr; const fdt32_t *prop; - prop = fdt_getprop(fdt, node, "#address-cells", &size); - if (prop && size == 4) - naddr = be32_to_cpup(prop); - else - naddr = 2; + naddr = fdt_address_cells(fdt, node); prop = fdt_getprop(fdt, node, "ranges", &size); @@ -1523,3 +1498,65 @@ int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr, return 0; } + +/** + * fdt_setup_simplefb_node - Fill and enable a simplefb node + * + * @fdt: ptr to device tree + * @node: offset of the simplefb node + * @base_address: framebuffer base address + * @width: width in pixels + * @height: height in pixels + * @stride: bytes per line + * @format: pixel format string + * + * Convenience function to fill and enable a simplefb node. + */ +int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width, + u32 height, u32 stride, const char *format) +{ + char name[32]; + fdt32_t cells[4]; + int i, addrc, sizec, ret; + + of_bus_default_count_cells(fdt, fdt_parent_offset(fdt, node), + &addrc, &sizec); + i = 0; + if (addrc == 2) + cells[i++] = cpu_to_fdt32(base_address >> 32); + cells[i++] = cpu_to_fdt32(base_address); + if (sizec == 2) + cells[i++] = 0; + cells[i++] = cpu_to_fdt32(height * stride); + + ret = fdt_setprop(fdt, node, "reg", cells, sizeof(cells[0]) * i); + if (ret < 0) + return ret; + + snprintf(name, sizeof(name), "framebuffer@%llx", base_address); + ret = fdt_set_name(fdt, node, name); + if (ret < 0) + return ret; + + ret = fdt_setprop_u32(fdt, node, "width", width); + if (ret < 0) + return ret; + + ret = fdt_setprop_u32(fdt, node, "height", height); + if (ret < 0) + return ret; + + ret = fdt_setprop_u32(fdt, node, "stride", stride); + if (ret < 0) + return ret; + + ret = fdt_setprop_string(fdt, node, "format", format); + if (ret < 0) + return ret; + + ret = fdt_setprop_string(fdt, node, "status", "okay"); + if (ret < 0) + return ret; + + return 0; +} diff --git a/common/image-fdt.c b/common/image-fdt.c index a39ae1b..e3f06cd 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -237,6 +237,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, int fdt_noffset; #endif const char *select = NULL; + int ok_no_fdt = 0; *of_flat_tree = NULL; *of_size = 0; @@ -309,7 +310,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, fdt_addr); fdt_hdr = image_get_fdt(fdt_addr); if (!fdt_hdr) - goto error; + goto no_fdt; /* * move image data to the load address, @@ -379,7 +380,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, break; default: puts("ERROR: Did not find a cmdline Flattened Device Tree\n"); - goto error; + goto no_fdt; } printf(" Booting using the fdt blob at %#08lx\n", fdt_addr); @@ -413,11 +414,11 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, } } else { debug("## No Flattened Device Tree\n"); - goto error; + goto no_fdt; } } else { debug("## No Flattened Device Tree\n"); - goto error; + goto no_fdt; } *of_flat_tree = fdt_blob; @@ -427,9 +428,15 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, return 0; +no_fdt: + ok_no_fdt = 1; error: *of_flat_tree = NULL; *of_size = 0; + if (!select && ok_no_fdt) { + debug("Continuing to boot without FDT\n"); + return 0; + } return 1; } @@ -460,19 +467,32 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, { ulong *initrd_start = &images->initrd_start; ulong *initrd_end = &images->initrd_end; - int ret; + int ret = -EPERM; + int fdt_ret; if (fdt_chosen(blob) < 0) { - puts("ERROR: /chosen node create failed"); - puts(" - must RESET the board to recover.\n"); - return -1; + printf("ERROR: /chosen node create failed\n"); + goto err; } if (arch_fixup_fdt(blob) < 0) { - puts("ERROR: arch specific fdt fixup failed"); - return -1; + printf("ERROR: arch-specific fdt fixup failed\n"); + goto err; + } + if (IMAGE_OF_BOARD_SETUP) { + fdt_ret = ft_board_setup(blob, gd->bd); + if (fdt_ret) { + printf("ERROR: board-specific fdt fixup failed: %s\n", + fdt_strerror(fdt_ret)); + goto err; + } + } + if (IMAGE_OF_SYSTEM_SETUP) { + if (ft_system_setup(blob, gd->bd)) { + printf("ERROR: system-specific fdt fixup failed: %s\n", + fdt_strerror(fdt_ret)); + goto err; + } } - if (IMAGE_OF_BOARD_SETUP) - ft_board_setup(blob, gd->bd); fdt_fixup_ethernet(blob); /* Delete the old LMB reservation */ @@ -481,7 +501,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, ret = fdt_shrink_to_minimum(blob); if (ret < 0) - return ret; + goto err; of_size = ret; if (*initrd_start && *initrd_end) { @@ -493,7 +513,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, fdt_initrd(blob, *initrd_start, *initrd_end); if (!ft_verify_fdt(blob)) - return -1; + goto err; #if defined(CONFIG_SOC_KEYSTONE) if (IMAGE_OF_BOARD_SETUP) @@ -501,4 +521,8 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, #endif return 0; +err: + printf(" - must RESET the board to recover.\n\n"); + + return ret; } diff --git a/common/lcd.c b/common/lcd.c index 37147af..3ed504d 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -30,6 +30,7 @@ #include <splash.h> #include <asm/io.h> #include <asm/unaligned.h> +#include <fdt_support.h> #if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ defined(CONFIG_CPU_MONAHANS) @@ -529,7 +530,7 @@ static int lcd_init(void *lcdbase) lcd_ctrl_init(lcdbase); /* - * lcd_ctrl_init() of some drivers (i.e. bcm2835 on rpi_b) ignores + * lcd_ctrl_init() of some drivers (i.e. bcm2835 on rpi) ignores * the 'lcdbase' argument and uses custom lcd base address * by setting up gd->fb_base. Check for this condition and fixup * 'lcd_base' address. @@ -746,7 +747,7 @@ static void splash_align_axis(int *axis, unsigned long panel_size, else return; - *axis = max(0, axis_alignment); + *axis = max(0, (int)axis_alignment); } #endif @@ -1145,8 +1146,8 @@ U_BOOT_ENV_CALLBACK(splashimage, on_splashimage); void lcd_position_cursor(unsigned col, unsigned row) { - console_col = min(col, CONSOLE_COLS - 1); - console_row = min(row, CONSOLE_ROWS - 1); + console_col = min_t(short, col, CONSOLE_COLS - 1); + console_row = min_t(short, row, CONSOLE_ROWS - 1); } int lcd_get_pixel_width(void) @@ -1172,51 +1173,13 @@ int lcd_get_screen_columns(void) #if defined(CONFIG_LCD_DT_SIMPLEFB) static int lcd_dt_simplefb_configure_node(void *blob, int off) { - u32 stride; - fdt32_t cells[2]; - int ret; - static const char format[] = #if LCD_BPP == LCD_COLOR16 - "r5g6b5"; + return fdt_setup_simplefb_node(blob, off, gd->fb_base, + panel_info.vl_col, panel_info.vl_row, + panel_info.vl_col * 2, "r5g6b5"); #else - ""; + return -1; #endif - - if (!format[0]) - return -1; - - stride = panel_info.vl_col * 2; - - cells[0] = cpu_to_fdt32(gd->fb_base); - cells[1] = cpu_to_fdt32(stride * panel_info.vl_row); - ret = fdt_setprop(blob, off, "reg", cells, sizeof(cells[0]) * 2); - if (ret < 0) - return -1; - - cells[0] = cpu_to_fdt32(panel_info.vl_col); - ret = fdt_setprop(blob, off, "width", cells, sizeof(cells[0])); - if (ret < 0) - return -1; - - cells[0] = cpu_to_fdt32(panel_info.vl_row); - ret = fdt_setprop(blob, off, "height", cells, sizeof(cells[0])); - if (ret < 0) - return -1; - - cells[0] = cpu_to_fdt32(stride); - ret = fdt_setprop(blob, off, "stride", cells, sizeof(cells[0])); - if (ret < 0) - return -1; - - ret = fdt_setprop(blob, off, "format", format, strlen(format) + 1); - if (ret < 0) - return -1; - - ret = fdt_delprop(blob, off, "status"); - if (ret < 0) - return -1; - - return 0; } int lcd_dt_simplefb_add_node(void *blob) diff --git a/common/malloc_simple.c b/common/malloc_simple.c new file mode 100644 index 0000000..afdacff --- /dev/null +++ b/common/malloc_simple.c @@ -0,0 +1,39 @@ +/* + * Simple malloc implementation + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void *malloc_simple(size_t bytes) +{ + ulong new_ptr; + void *ptr; + + new_ptr = gd->malloc_ptr + bytes; + if (new_ptr > gd->malloc_limit) + panic("Out of pre-reloc memory"); + ptr = map_sysmem(gd->malloc_base + gd->malloc_ptr, bytes); + gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr)); + return ptr; +} + +#ifdef CONFIG_SYS_MALLOC_SIMPLE +void *calloc(size_t nmemb, size_t elem_size) +{ + size_t size = nmemb * elem_size; + void *ptr; + + ptr = malloc(size); + memset(ptr, '\0', size); + + return ptr; +} +#endif diff --git a/common/spl/spl.c b/common/spl/spl.c index d85bab3..1826c47 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -7,6 +7,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> #include <spl.h> #include <asm/u-boot.h> #include <nand.h> @@ -15,6 +16,7 @@ #include <i2c.h> #include <image.h> #include <malloc.h> +#include <dm/root.h> #include <linux/compiler.h> DECLARE_GLOBAL_DATA_PTR; @@ -62,6 +64,15 @@ __weak void spl_board_prepare_for_linux(void) /* Nothing to do! */ } +void spl_set_header_raw_uboot(void) +{ + spl_image.size = CONFIG_SYS_MONITOR_LEN; + spl_image.entry_point = CONFIG_SYS_UBOOT_START; + spl_image.load_addr = CONFIG_SYS_TEXT_BASE; + spl_image.os = IH_OS_U_BOOT; + spl_image.name = "U-Boot"; +} + void spl_parse_image_header(const struct image_header *header) { u32 header_size = sizeof(struct image_header); @@ -93,11 +104,7 @@ void spl_parse_image_header(const struct image_header *header) /* Signature not found - assume u-boot.bin */ debug("mkimage signature not found - ih_magic = %x\n", header->ih_magic); - spl_image.size = CONFIG_SYS_MONITOR_LEN; - spl_image.entry_point = CONFIG_SYS_UBOOT_START; - spl_image.load_addr = CONFIG_SYS_TEXT_BASE; - spl_image.os = IH_OS_U_BOOT; - spl_image.name = "U-Boot"; + spl_set_header_raw_uboot(); } } @@ -134,9 +141,16 @@ void board_init_r(gd_t *dummy1, ulong dummy2) u32 boot_device; debug(">>spl:board_init_r()\n"); -#ifdef CONFIG_SYS_SPL_MALLOC_START +#if defined(CONFIG_SYS_SPL_MALLOC_START) mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; +#elif defined(CONFIG_SYS_MALLOC_F_LEN) + gd->malloc_limit = gd->malloc_base + CONFIG_SYS_MALLOC_F_LEN; + gd->malloc_ptr = 0; +#endif +#ifdef CONFIG_SPL_DM + dm_init_and_scan(true); #endif #ifndef CONFIG_PPC @@ -216,7 +230,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2) break; #endif default: - debug("SPL: Un-supported Boot Device\n"); +#if defined(CONFIG_SPL_SERIAL_SUPPORT) && defined(CONFIG_SPL_LIBCOMMON_SUPPORT) + printf("SPL: Unsupported Boot Device %d\n", boot_device); +#endif hang(); } @@ -233,6 +249,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2) default: debug("Unsupported OS image.. Jumping nevertheless..\n"); } +#if defined(CONFIG_SYS_MALLOC_F_LEN) && !defined(CONFIG_SYS_SPL_MALLOC_SIZE) + debug("SPL malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr, + gd->malloc_ptr / 1024); +#endif + jump_to_image_no_args(&spl_image); } diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c index d9eba5a..9d37fd3 100644 --- a/common/spl/spl_ext.c +++ b/common/spl/spl_ext.c @@ -15,7 +15,7 @@ int spl_load_image_ext(block_dev_desc_t *block_dev, { s32 err; struct image_header *header; - int filelen; + loff_t filelen, actlen; disk_partition_t part_info = {}; header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - @@ -37,36 +37,36 @@ int spl_load_image_ext(block_dev_desc_t *block_dev, goto end; } - filelen = err = ext4fs_open(filename); + err = ext4fs_open(filename, &filelen); if (err < 0) { puts("spl: ext4fs_open failed\n"); goto end; } - err = ext4fs_read((char *)header, sizeof(struct image_header)); - if (err <= 0) { + err = ext4fs_read((char *)header, sizeof(struct image_header), &actlen); + if (err < 0) { puts("spl: ext4fs_read failed\n"); goto end; } spl_parse_image_header(header); - err = ext4fs_read((char *)spl_image.load_addr, filelen); + err = ext4fs_read((char *)spl_image.load_addr, filelen, &actlen); end: #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - if (err <= 0) + if (err < 0) printf("%s: error reading image %s, err - %d\n", __func__, filename, err); #endif - return err <= 0; + return err < 0; } #ifdef CONFIG_SPL_OS_BOOT int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition) { int err; - int filelen; + __maybe_unused loff_t filelen, actlen; disk_partition_t part_info = {}; __maybe_unused char *file; @@ -89,13 +89,13 @@ int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition) #if defined(CONFIG_SPL_ENV_SUPPORT) && defined(CONFIG_SPL_OS_BOOT) file = getenv("falcon_args_file"); if (file) { - filelen = err = ext4fs_open(file); + err = ext4fs_open(file, &filelen); if (err < 0) { puts("spl: ext4fs_open failed\n"); goto defaults; } - err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen); - if (err <= 0) { + err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, &actlen); + if (err < 0) { printf("spl: error reading image %s, err - %d, falling back to default\n", file, err); goto defaults; @@ -119,12 +119,12 @@ int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition) defaults: #endif - filelen = err = ext4fs_open(CONFIG_SPL_FS_LOAD_ARGS_NAME); + err = ext4fs_open(CONFIG_SPL_FS_LOAD_ARGS_NAME, &filelen); if (err < 0) puts("spl: ext4fs_open failed\n"); - err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen); - if (err <= 0) { + err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, &actlen); + if (err < 0) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT printf("%s: error reading image %s, err - %d\n", __func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err); diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index ee71f79..7bae16b 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -15,7 +15,7 @@ DECLARE_GLOBAL_DATA_PTR; -static int mmc_load_image_raw(struct mmc *mmc, unsigned long sector) +static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector) { unsigned long err; u32 image_size_sectors; @@ -51,6 +51,22 @@ end: return (err == 0); } +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION +static int mmc_load_image_raw_partition(struct mmc *mmc, int partition) +{ + disk_partition_t info; + + if (get_partition_info(&mmc->block_dev, partition, &info)) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("spl: partition error\n"); +#endif + return -1; + } + + return mmc_load_image_raw_sector(mmc, info.start); +} +#endif + #ifdef CONFIG_SPL_OS_BOOT static int mmc_load_image_raw_os(struct mmc *mmc) { @@ -64,7 +80,8 @@ static int mmc_load_image_raw_os(struct mmc *mmc) return -1; } - return mmc_load_image_raw(mmc, CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR); + return mmc_load_image_raw_sector(mmc, + CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR); } #endif @@ -98,18 +115,24 @@ void spl_mmc_load_image(void) #ifdef CONFIG_SPL_OS_BOOT if (spl_start_uboot() || mmc_load_image_raw_os(mmc)) #endif - err = mmc_load_image_raw(mmc, +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION + err = mmc_load_image_raw_partition(mmc, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION); +#else + err = mmc_load_image_raw_sector(mmc, CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); +#endif #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) - } else if (boot_mode == MMCSD_MODE_FS) { + } + if (err || boot_mode == MMCSD_MODE_FS) { debug("boot mode - FS\n"); #ifdef CONFIG_SPL_FAT_SUPPORT #ifdef CONFIG_SPL_OS_BOOT if (spl_start_uboot() || spl_load_image_fat_os(&mmc->block_dev, - CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION)) + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION)) #endif err = spl_load_image_fat(&mmc->block_dev, - CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION, + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); if(err) #endif /* CONFIG_SPL_FAT_SUPPORT */ @@ -117,10 +140,10 @@ void spl_mmc_load_image(void) #ifdef CONFIG_SPL_EXT_SUPPORT #ifdef CONFIG_SPL_OS_BOOT if (spl_start_uboot() || spl_load_image_ext_os(&mmc->block_dev, - CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION)) + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION)) #endif err = spl_load_image_ext(&mmc->block_dev, - CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION, + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); #endif /* CONFIG_SPL_EXT_SUPPORT */ } @@ -146,7 +169,7 @@ void spl_mmc_load_image(void) #ifdef CONFIG_SPL_OS_BOOT if (spl_start_uboot() || mmc_load_image_raw_os(mmc)) #endif - err = mmc_load_image_raw(mmc, + err = mmc_load_image_raw_sector(mmc, CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); #endif } else { diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 9b200bc..b7801cb 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -10,6 +10,18 @@ #include <asm/io.h> #include <nand.h> +#if defined(CONFIG_SPL_NAND_RAW_ONLY) +void spl_nand_load_image(void) +{ + nand_init(); + + nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_U_BOOT_SIZE, + (void *)CONFIG_SYS_NAND_U_BOOT_DST); + spl_set_header_raw_uboot(); + nand_deselect(); +} +#else void spl_nand_load_image(void) { struct image_header *header; @@ -82,3 +94,4 @@ void spl_nand_load_image(void) spl_image.size, (void *)spl_image.load_addr); nand_deselect(); } +#endif diff --git a/common/usb.c b/common/usb.c index 7d33a0f..736cd9f 100644 --- a/common/usb.c +++ b/common/usb.c @@ -33,7 +33,6 @@ #include <linux/ctype.h> #include <asm/byteorder.h> #include <asm/unaligned.h> -#include <compiler.h> #include <errno.h> #include <usb.h> #ifdef CONFIG_4xx diff --git a/common/usb_hub.c b/common/usb_hub.c index 0f1eab4..66b4a72 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -300,7 +300,8 @@ static int usb_hub_configure(struct usb_device *dev) } descriptor = (struct usb_hub_descriptor *)buffer; - length = min(descriptor->bLength, sizeof(struct usb_hub_descriptor)); + length = min_t(int, descriptor->bLength, + sizeof(struct usb_hub_descriptor)); if (usb_get_hub_descriptor(dev, buffer, length) < 0) { debug("usb_hub_configure: failed to get hub " \ diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index 8517203..be8652b 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -2,6 +2,8 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI" CONFIG_FDTFILE="sun5i-a13-olinuxino-micro.dtb" CONFIG_USB1_VBUS_PIN="PG11" +CONFIG_VIDEO=n +CONFIG_USB_KEYBOARD=n +S:CONFIG_ARM=y +S:CONFIG_ARCH_SUNXI=y +S:CONFIG_MACH_SUN5I=y diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 61f5466..654e12a 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -2,6 +2,8 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI" CONFIG_FDTFILE="sun5i-a13-olinuxino.dtb" CONFIG_USB1_VBUS_PIN="PG11" +CONFIG_VIDEO=n +CONFIG_USB_KEYBOARD=n +S:CONFIG_ARM=y +S:CONFIG_ARCH_SUNXI=y +S:CONFIG_MACH_SUN5I=y diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index bef568d..de78a01 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -1,5 +1,6 @@ CONFIG_SPL=y CONFIG_FDTFILE="sun6i-a31-colombus.dtb" +CONFIG_USB_KEYBOARD=n +S:CONFIG_ARM=y +S:CONFIG_ARCH_SUNXI=y +S:CONFIG_MACH_SUN6I=y diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig index fc67bd9..50c2f93 100644 --- a/configs/Ippo_q8h_v5_defconfig +++ b/configs/Ippo_q8h_v5_defconfig @@ -4,3 +4,5 @@ CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN8I=y CONFIG_TARGET_IPPO_Q8H_V5=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5.dtb" +CONFIG_VIDEO=n +CONFIG_USB_KEYBOARD=n diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index f46439f..ac3cd36 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -1,5 +1,5 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI" +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC" CONFIG_FDTFILE="sun6i-a31-m9.dtb" +S:CONFIG_ARM=y +S:CONFIG_ARCH_SUNXI=y @@ -14,5 +14,7 @@ CONFIG_FDTFILE="sun6i-a31-m9.dtb" # HDMI power ? +S:CONFIG_AXP221_ALDO2_VOLT=1800 +S:CONFIG_AXP221_ALDO3_VOLT=3000 -# No Vbus gpio for usb1 -+S:CONFIG_USB1_VBUS_PIN="" +# Vbus gpio for usb1 ++S:CONFIG_USB1_VBUS_PIN="PC27" +# No Vbus gpio for usb2 ++S:CONFIG_USB2_VBUS_PIN="" diff --git a/configs/T1024QDS_D4_SECURE_BOOT_defconfig b/configs/T1024QDS_D4_SECURE_BOOT_defconfig new file mode 100644 index 0000000..d86ae05 --- /dev/null +++ b/configs/T1024QDS_D4_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T102XQDS=y diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig new file mode 100644 index 0000000..acbbe43 --- /dev/null +++ b/configs/T1024QDS_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XQDS=y diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig new file mode 100644 index 0000000..82c6e19 --- /dev/null +++ b/configs/T1024QDS_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XQDS=y diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig new file mode 100644 index 0000000..b932619 --- /dev/null +++ b/configs/T1024QDS_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T102XQDS=y diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig new file mode 100644 index 0000000..52aeac7 --- /dev/null +++ b/configs/T1024QDS_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XQDS=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig new file mode 100644 index 0000000..73d14ab --- /dev/null +++ b/configs/T1024RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig new file mode 100644 index 0000000..3599f1d --- /dev/null +++ b/configs/T1024RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig new file mode 100644 index 0000000..8377260 --- /dev/null +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig new file mode 100644 index 0000000..c8ea985 --- /dev/null +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig new file mode 100644 index 0000000..e19e404 --- /dev/null +++ b/configs/T1024RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T102XRDB=y diff --git a/configs/alt_defconfig b/configs/alt_defconfig index 0655e60..d722306 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -1,3 +1,3 @@ CONFIG_ARM=y -+S:CONFIG_RMOBILE=y +CONFIG_RMOBILE=y CONFIG_TARGET_ALT=y diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig new file mode 100644 index 0000000..f8c9f03 --- /dev/null +++ b/configs/bcm11130_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0" +CONFIG_ARM=y +CONFIG_TARGET_BCM28155_AP=y diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig new file mode 100644 index 0000000..39cb709 --- /dev/null +++ b/configs/bcm11130_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="NAND" +CONFIG_ARM=y +CONFIG_TARGET_BCM28155_AP=y diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig new file mode 100644 index 0000000..6f5c154 --- /dev/null +++ b/configs/bcm911360_entphn-ns_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC" +CONFIG_ARM=y +CONFIG_TARGET_BCMCYGNUS=y diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig new file mode 100644 index 0000000..37b5846 --- /dev/null +++ b/configs/bcm911360_entphn_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000" +CONFIG_ARM=y +CONFIG_TARGET_BCMCYGNUS=y diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig new file mode 100644 index 0000000..527e407 --- /dev/null +++ b/configs/bcm911360k_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" +CONFIG_ARM=y +CONFIG_TARGET_BCMCYGNUS=y diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig new file mode 100644 index 0000000..0e3aaa7 --- /dev/null +++ b/configs/bcm958300k-ns_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC" +CONFIG_ARM=y +CONFIG_TARGET_BCMCYGNUS=y diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig index 066739d..527e407 100644 --- a/configs/bcm958300k_defconfig +++ b/configs/bcm958300k_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000" +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" CONFIG_ARM=y -CONFIG_TARGET_BCM958300K=y +CONFIG_TARGET_BCMCYGNUS=y diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig new file mode 100644 index 0000000..527e407 --- /dev/null +++ b/configs/bcm958305k_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" +CONFIG_ARM=y +CONFIG_TARGET_BCMCYGNUS=y diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig index 8a45e51..7c86300 100644 --- a/configs/bcm958622hr_defconfig +++ b/configs/bcm958622hr_defconfig @@ -1,3 +1,3 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000" CONFIG_ARM=y -CONFIG_TARGET_BCM958622HR=y +CONFIG_TARGET_BCMNSP=y diff --git a/configs/beagle_x15_defconfig b/configs/beagle_x15_defconfig new file mode 100644 index 0000000..872ab63 --- /dev/null +++ b/configs/beagle_x15_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP54XX=y ++S:CONFIG_TARGET_BEAGLE_X15=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig new file mode 100644 index 0000000..b83803e --- /dev/null +++ b/configs/chromebook_link_defconfig @@ -0,0 +1,10 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" +CONFIG_X86=y +CONFIG_TARGET_CHROMEBOOK_LINK=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" +CONFIG_HAVE_MRC=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 50c06f7..3c0d64f 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -1,4 +1,4 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/cm_fx6/imximage.cfg,MX6QDL,SPL" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL" +S:CONFIG_ARM=y +S:CONFIG_TARGET_CM_FX6=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index 3fc8edb..5d60847 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -1,3 +1,4 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH" -CONFIG_ARM=y -CONFIG_TARGET_CORVUS=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_CORVUS=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig new file mode 100644 index 0000000..54a56f5 --- /dev/null +++ b/configs/gose_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_RMOBILE=y +CONFIG_TARGET_GOSE=y diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig index f185329..4cddbdd 100644 --- a/configs/gwventana_defconfig +++ b/configs/gwventana_defconfig @@ -1,4 +1,4 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6QDL" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" +S:CONFIG_ARM=y +S:CONFIG_TARGET_GW_VENTANA=y diff --git a/configs/hermes_defconfig b/configs/hermes_defconfig deleted file mode 100644 index a923a61..0000000 --- a/configs/hermes_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_HERMES=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig new file mode 100644 index 0000000..69c65ba --- /dev/null +++ b/configs/hrcon_defconfig @@ -0,0 +1,3 @@ +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_HRCON=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index d59ff3d..35f605c 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -1,3 +1,3 @@ CONFIG_ARM=y -+S:CONFIG_RMOBILE=y +CONFIG_RMOBILE=y CONFIG_TARGET_KOELSCH=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 9a32d6b..8b4aeea 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -1,3 +1,3 @@ CONFIG_ARM=y -+S:CONFIG_RMOBILE=y +CONFIG_RMOBILE=y CONFIG_TARGET_LAGER=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig new file mode 100644 index 0000000..dad5274 --- /dev/null +++ b/configs/ls1021aqds_nand_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig new file mode 100644 index 0000000..05ec8e6 --- /dev/null +++ b/configs/ls1021aqds_qspi_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021aqds_sdcard_defconfig b/configs/ls1021aqds_sdcard_defconfig new file mode 100644 index 0000000..e03c3b4 --- /dev/null +++ b/configs/ls1021aqds_sdcard_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig new file mode 100644 index 0000000..611f6e8 --- /dev/null +++ b/configs/ls1021atwr_qspi_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021ATWR=y diff --git a/configs/ls1021atwr_sdcard_defconfig b/configs/ls1021atwr_sdcard_defconfig new file mode 100644 index 0000000..0eb556a --- /dev/null +++ b/configs/ls1021atwr_sdcard_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021ATWR=y diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig new file mode 100644 index 0000000..12e7844 --- /dev/null +++ b/configs/mx6sabresd_spl_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_MX6SABRESD=y + diff --git a/configs/novena_defconfig b/configs/novena_defconfig index cadf461..b8fd97f 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -1,4 +1,4 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kosagi/novena/setup.cfg,MX6Q" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" +S:CONFIG_ARM=y +S:CONFIG_TARGET_KOSAGI_NOVENA=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig new file mode 100644 index 0000000..8ada0db --- /dev/null +++ b/configs/peach-pi_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_EXYNOS=y ++S:CONFIG_TARGET_PEACH_PI=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi" diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index f54b15f..3155340 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -1,7 +1,34 @@ CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +S:CONFIG_ARM=y +S:CONFIG_ARCH_UNIPHIER=y +S:CONFIG_MACH_PH1_LD4=y ++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BDI=y +CONFIG_CMD_CONSOLE=y +CONFIG_CMD_BOOTD=y +CONFIG_CMD_RUN=y +CONFIG_CMD_IMI=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_EDITENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_MEMORY=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_NAND=y +CONFIG_CMD_USB=y +CONFIG_CMD_ECHO=y +CONFIG_CMD_ITEST=y +CONFIG_CMD_SOURCE=y +CONFIG_CMD_NET=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_NFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" CONFIG_DM=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index e795752..7ea4e6e 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -1,7 +1,34 @@ CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +S:CONFIG_ARM=y +S:CONFIG_ARCH_UNIPHIER=y +S:CONFIG_MACH_PH1_PRO4=y ++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BDI=y +CONFIG_CMD_CONSOLE=y +CONFIG_CMD_BOOTD=y +CONFIG_CMD_RUN=y +CONFIG_CMD_IMI=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_EDITENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_MEMORY=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_NAND=y +CONFIG_CMD_USB=y +CONFIG_CMD_ECHO=y +CONFIG_CMD_ITEST=y +CONFIG_CMD_SOURCE=y +CONFIG_CMD_NET=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_NFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref" CONFIG_DM=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index 6510937..ddf210c 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -1,7 +1,34 @@ CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +S:CONFIG_ARM=y +S:CONFIG_ARCH_UNIPHIER=y +S:CONFIG_MACH_PH1_SLD8=y ++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BDI=y +CONFIG_CMD_CONSOLE=y +CONFIG_CMD_BOOTD=y +CONFIG_CMD_RUN=y +CONFIG_CMD_IMI=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_EDITENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_MEMORY=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_NAND=y +CONFIG_CMD_USB=y +CONFIG_CMD_ECHO=y +CONFIG_CMD_ITEST=y +CONFIG_CMD_SOURCE=y +CONFIG_CMD_NET=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_NFS=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref" CONFIG_DM=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y diff --git a/configs/rpi_b_defconfig b/configs/rpi_b_defconfig deleted file mode 100644 index 9a4705e..0000000 --- a/configs/rpi_b_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_RPI_B=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig new file mode 100644 index 0000000..9379cf0 --- /dev/null +++ b/configs/rpi_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_RPI=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig new file mode 100644 index 0000000..3720f3c --- /dev/null +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D4_XPLAINED=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig new file mode 100644 index 0000000..5e13da7 --- /dev/null +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D4_XPLAINED=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig new file mode 100644 index 0000000..3a4607c --- /dev/null +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D4_XPLAINED=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig new file mode 100644 index 0000000..16a5ed7 --- /dev/null +++ b/configs/sama5d4ek_mmc_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D4EK=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig new file mode 100644 index 0000000..8b7fbc3 --- /dev/null +++ b/configs/sama5d4ek_nandflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D4EK=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig new file mode 100644 index 0000000..63e9b6c --- /dev/null +++ b/configs/sama5d4ek_spiflash_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SAMA5D4EK=y diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig index 124154c..1f7c6d0 100644 --- a/configs/sh7752evb_defconfig +++ b/configs/sh7752evb_defconfig @@ -1,2 +1,3 @@ CONFIG_SH=y +CONFIG_SH_32BIT=y CONFIG_TARGET_SH7752EVB=y diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig index 9ff4121..35809e9 100644 --- a/configs/sh7753evb_defconfig +++ b/configs/sh7753evb_defconfig @@ -1,2 +1,3 @@ CONFIG_SH=y +CONFIG_SH_32BIT=y CONFIG_TARGET_SH7753EVB=y diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig index 3066d97..ffcf961 100644 --- a/configs/sh7757lcr_defconfig +++ b/configs/sh7757lcr_defconfig @@ -1,2 +1,3 @@ CONFIG_SH=y +CONFIG_SH_32BIT=y CONFIG_TARGET_SH7757LCR=y diff --git a/configs/sh7785lcr_32bit_defconfig b/configs/sh7785lcr_32bit_defconfig index 7cf93b4..31b84ff 100644 --- a/configs/sh7785lcr_32bit_defconfig +++ b/configs/sh7785lcr_32bit_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SH_32BIT=1" CONFIG_SH=y +CONFIG_SH_32BIT=y CONFIG_TARGET_SH7785LCR=y diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig new file mode 100644 index 0000000..a05e991 --- /dev/null +++ b/configs/stv0991_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="stv0991" +CONFIG_ARM=y +CONFIG_TARGET_STV0991=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 9870048..438e25d 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -1,3 +1,4 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS" -CONFIG_ARM=y -CONFIG_TARGET_TAURUS=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TAURUS=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig new file mode 100644 index 0000000..602d691 --- /dev/null +++ b/configs/tbs2910_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q" +CONFIG_ARM=y +CONFIG_TARGET_TBS2910=y diff --git a/disk/part_efi.c b/disk/part_efi.c index 612f092..efed58f 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -14,6 +14,7 @@ #include <common.h> #include <command.h> #include <ide.h> +#include <inttypes.h> #include <malloc.h> #include <part_efi.h> #include <linux/ctype.h> @@ -553,28 +554,28 @@ static int is_gpt_valid(block_dev_desc_t *dev_desc, u64 lba, /* Check that the my_lba entry points to the LBA that contains the GPT */ if (le64_to_cpu(pgpt_head->my_lba) != lba) { - printf("GPT: my_lba incorrect: %llX != %llX\n", - le64_to_cpu(pgpt_head->my_lba), - lba); + printf("GPT: my_lba incorrect: %llX != %" PRIX64 "\n", + le64_to_cpu(pgpt_head->my_lba), + lba); return 0; } /* Check the first_usable_lba and last_usable_lba are within the disk. */ lastlba = (u64)dev_desc->lba; if (le64_to_cpu(pgpt_head->first_usable_lba) > lastlba) { - printf("GPT: first_usable_lba incorrect: %llX > %llX\n", - le64_to_cpu(pgpt_head->first_usable_lba), lastlba); + printf("GPT: first_usable_lba incorrect: %llX > %" PRIX64 "\n", + le64_to_cpu(pgpt_head->first_usable_lba), lastlba); return 0; } if (le64_to_cpu(pgpt_head->last_usable_lba) > lastlba) { - printf("GPT: last_usable_lba incorrect: %llX > %llX\n", - le64_to_cpu(pgpt_head->last_usable_lba), lastlba); + printf("GPT: last_usable_lba incorrect: %llX > %" PRIX64 "\n", + le64_to_cpu(pgpt_head->last_usable_lba), lastlba); return 0; } - debug("GPT: first_usable_lba: %llX last_usable_lba %llX last lba %llX\n", - le64_to_cpu(pgpt_head->first_usable_lba), - le64_to_cpu(pgpt_head->last_usable_lba), lastlba); + debug("GPT: first_usable_lba: %llX last_usable_lba %llX last lba %" + PRIX64 "\n", le64_to_cpu(pgpt_head->first_usable_lba), + le64_to_cpu(pgpt_head->last_usable_lba), lastlba); /* Read and allocate Partition Table Entries */ *pgpt_pte = alloc_read_gpt_entries(dev_desc, pgpt_head); diff --git a/doc/README.clang b/doc/README.clang index 52495d3..fe36909 100644 --- a/doc/README.clang +++ b/doc/README.clang @@ -28,7 +28,7 @@ sudo apt-get install clang To compile U-Boot with clang on linux without IAS use e.g.: export TRIPLET=arm-linux-gnueabi && export CROSS_COMPILE="$TRIPLET-" -make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" rpi_b_defconfig +make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" rpi_defconfig make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as" all V=1 -j8 FreeBSD 11 (Current): @@ -42,7 +42,7 @@ ln -s /usr/local/bin/arm-gnueabi-freebsd-as /usr/bin/arm-freebsd-eabi-as # The following commands compile U-Boot using the clang xdev toolchain. # NOTE: CROSS_COMPILE and target differ on purpose! export CROSS_COMPILE=arm-gnueabi-freebsd- -gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" rpi_b_defconfig +gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" rpi_defconfig gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" -j8 Given that u-boot will default to gcc, above commands can be diff --git a/doc/README.fsl-dpaa b/doc/README.fsl-dpaa new file mode 100644 index 0000000..0d8d4f6 --- /dev/null +++ b/doc/README.fsl-dpaa @@ -0,0 +1,10 @@ +This file documents Freescale DPAA-specific options. + +FMan (Frame Manager) + - CONFIG_FSL_FM_10GEC_REGULAR_NOTATION + on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: + 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 + on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: + 10GEC1->MAC1, 10GEC2->MAC2 + so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on + which 10GEC enumeration is consistent with MAC enumeration. diff --git a/doc/README.mxsimage b/doc/README.mxsimage index 0d31cba..c3975ee 100644 --- a/doc/README.mxsimage +++ b/doc/README.mxsimage @@ -27,7 +27,7 @@ These semantics and rules will be outlined now. - Each line of the configuration file contains exactly one instruction. - Every numeric value must be encoded in hexadecimal and in format 0xabcdef12 . - The configuration file is a concatenation of blocks called "sections" and - optionally "DCD blocks" (see below). + optionally "DCD blocks" (see below), and optional flags lines. - Each "section" is started by the "SECTION" instruction. - The "SECTION" instruction has the following semantics: @@ -139,9 +139,14 @@ These semantics and rules will be outlined now. NOOP - This instruction does nothing. -- If the verbose output from the BootROM is enabled, the BootROM will produce a - letter on the Debug UART for each instruction it started processing. Here is a - mapping between the above instructions and the BootROM verbose output: + - An optional flags lines can be one of the following: + + DISPLAYPROGRESS + - Enable boot progress output form the BootROM. + +- If the boot progress output from the BootROM is enabled, the BootROM will + produce a letter on the Debug UART for each instruction it started processing. + Here is a mapping between the above instructions and the BootROM output: H -- SB Image header loaded T -- TAG instruction diff --git a/doc/README.odroid b/doc/README.odroid index 528bb95..25b962b 100644 --- a/doc/README.odroid +++ b/doc/README.odroid @@ -141,3 +141,172 @@ And the boot sequence is: - boot_fit - if "Image.itb" exists - boot_zimg - if "zImage" exists - boot_uimg - if "uImage" exists + +11. USB host support +==================== + +The ethernet can be accessed after starting the USB subsystem in U-Boot. +The adapter does not come with a preconfigured MAC address, and hence it needs +to be set before starting USB. +setenv usbethaddr 02:DE:AD:BE:EF:FF + +Note that in this example a locally managed MAC address is chosen. Care should +be taken to make these MAC addresses unique within the same subnet. + +Start the USB subsystem: +Odroid # setenv usbethaddr 02:DE:AD:BE:EF:FF +Odroid # usb start +(Re)start USB... +USB0: USB EHCI 1.00 +scanning bus 0 for devices... 4 USB Device(s) found + scanning usb for storage devices... 1 Storage Device(s) found + scanning usb for ethernet devices... 1 Ethernet Device(s) found +Odroid # + +Automatic IP assignment: +------------------------ +If the ethernet is connected to a DHCP server (router maybe with DHCP enabled), +then the below will automatically assign an ip address through DHCP. +setenv autoload no +dhcp + +Odroid # setenv autoload no +Odroid # dhcp +Waiting for Ethernet connection... done. +BOOTP broadcast 1 +DHCP client bound to address 192.168.1.10 (524 ms) +Odroid # + +Note that this automatically sets the many IP address related variables in +U-Boot that is obtained from the DHCP server. + +Odroid # printenv ipaddr netmask gatewayip dnsip +ipaddr=192.168.1.10 +netmask=255.255.255.0 +gatewayip=192.168.1.1 +dnsip=192.168.1.1 + +Ping example: +The ping command can be used a test to check connectivity. In this example, +192.168.1.27 is a pingable server in the network. +Odroid # ping 192.168.1.27 +Waiting for Ethernet connection... done. +Using sms0 device +host 192.168.1.27 is alive +Odroid # + +Static IP assignment: +--------------------- +In the case where there are no DHCP servers in the network, or you want to +set the IP address statically, it can be done by: +Odroid # setenv ipaddr 192.168.1.10 +Odroid # ping 192.168.1.27 +Waiting for Ethernet connection... done. +Using sms0 device +host 192.168.1.27 is alive + +TFTP booting: +------------- +Say there exists a tftp server in the network with address 192.168.1.27 and +it serves a kernel image (zImage.3.17) and a DTB blob (exynos4412-odroidu3.dtb) +that needs to be loaded and booted. It can be accomplished as below: +(Assumes that you have setenv usbethaddr, and have not set autoload to no) + +Odroid # setenv serverip 192.168.1.27 +Odroid # tftpboot 0x40080000 zImage.3.17 +Waiting for Ethernet connection... done. +Using sms0 device +TFTP from server 192.168.1.27; our IP address is 192.168.1.10 +Filename 'zImage.3.17'. +Load address: 0x40080000 +Loading: ################################################################# + ################################################################# + ################################################################# + ####################### + 52.7 KiB/s +done +Bytes transferred = 3194200 (30bd58 hex) +Odroid # tftpboot 0x42000000 exynos4412-odroidu3.dtb +Waiting for Ethernet connection... done. +Using sms0 device +TFTP from server 192.168.1.27; our IP address is 192.168.1.10 +Filename 'exynos4412-odroidu3.dtb'. +Load address: 0x42000000 +Loading: #### + 40 KiB/s +done +Bytes transferred = 46935 (b757 hex) +Odroid # printenv bootargs +bootargs=Please use defined boot +Odroid # setenv bootargs console=ttySAC1,115200n8 root=/dev/mmcblk0p2 rootwait +Odroid # bootz 40080000 - 42000000 +Kernel image @ 0x40080000 [ 0x000000 - 0x30bd58 ] +## Flattened Device Tree blob at 42000000 + Booting using the fdt blob at 0x42000000 + Loading Device Tree to 4fff1000, end 4ffff756 ... OK + +Starting kernel ... + +[ 0.000000] Booting Linux on physical CPU 0xa00 +... etc ... + +In the above example you can substitute 'dhcp' for 'tftpboot' as well. + +USB Storage booting: +-------------------- +Similarly we can use the USB storage to load the kernel image/initrd/fdt etc +and boot. For this example, there is a USB drive plugged in. It has a FAT +1st partition and an EXT 2nd partition. Using the generic FS (ls/load) makes +it even easier to work with FAT/EXT file systems. +For this example the second EXT partition is used for booting and as rootfs. +The boot files - kernel and the dtb are present in the /boot directory of the +second partition. + +Odroid # usb start +(Re)start USB... +USB0: USB EHCI 1.00 +scanning bus 0 for devices... 4 USB Device(s) found + scanning usb for storage devices... 1 Storage Device(s) found + scanning usb for ethernet devices... +Error: sms0 address not set. <----- Note the error as usbethaddr +Warning: failed to set MAC address <----- is not set. +1 Ethernet Device(s) found +Odroid # usb part 0 + +Partition Map for USB device 0 -- Partition Type: DOS + +Part Start Sector Num Sectors UUID Type + 1 3072 263168 000c4046-01 06 + 2 266240 13457408 000c4046-02 83 + +Odroid # ls usb 0:2 /boot +<DIR> 4096 . +<DIR> 4096 .. + 353 boot.scr + 281 boot.txt + 101420 config-3.8.13.23 + 2127254 initrd.img-3.8.13.23 + 2194825 uInitrd + 2194825 uInitrd-3.8.13.23 + 2453112 zImage + 101448 config-3.8.13.26 + 2127670 uInitrd-3.8.13.26 + 2127606 initrd.img-3.8.13.26 + 3194200 zImage.3.17 <--- Kernel + 46935 exynos4412-odroidu3.dtb <--- DTB +Odroid # load usb 0:2 40080000 /boot/zImage.3.17 +3194200 bytes read in 471 ms (6.5 MiB/s) +Odroid # load usb 0:2 42000000 /boot/exynos4412-odroidu3.dtb +46935 bytes read in 233 ms (196.3 KiB/s) +Odroid # setenv bootargs console=ttySAC1,115200n8 root=/dev/sda2 rootwait +Odroid # bootz 40080000 - 42000000 +Kernel image @ 0x40080000 [ 0x000000 - 0x30bd58 ] +## Flattened Device Tree blob at 42000000 + Booting using the fdt blob at 0x42000000 + Loading Device Tree to 4fff1000, end 4ffff756 ... OK + +Starting kernel ... + +[ 0.000000] Booting Linux on physical CPU 0xa00 + +Please refer to README.usb for additional information. diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 8ba6e0a..deb4af4 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,8 +12,9 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -PRS200 powerpc mpc5200 - - -MCC200 powerpc mpc5200 - - +hermes powerpc mpc8xx - - Wolfgang Denk <wd@denx.de> +PRS200 powerpc mpc5200 ecfdcee 2014-11-12 +MCC200 powerpc mpc5200 ecfdcee 2014-11-12 TOP5200 powerpc mpc5200 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> TOP860 powerpc mpc860 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> TOP9000 arm at91sam9xeXXX d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> diff --git a/doc/device-tree-bindings/ata/intel-sata.txt b/doc/device-tree-bindings/ata/intel-sata.txt new file mode 100644 index 0000000..5e4da83 --- /dev/null +++ b/doc/device-tree-bindings/ata/intel-sata.txt @@ -0,0 +1,26 @@ +Intel Pantherpoint SATA Device Binding +====================================== + +The device tree node which describes the operation of the Intel Pantherpoint +SATA device is as follows: + +Required properties : +- compatible = "intel,pantherpoint-ahci" +- intel,sata-mode : string, one of: + "ahci" : Use AHCI mode (default) + "combined" : Use combined IDE + legacy mode + "plain-ide" : Use plain IDE mode +- intel,sata-port-map : Which SATA ports are enabled, bit 0=enable first port, + bit 1=enable second port, etc. +- intel,sata-port0-gen3-tx : Value for the IOBP_SP0G3IR register +- intel,sata-port1-gen3-tx : Value for the IOBP_SP1G3IR register + +Example +------- + +sata { + compatible = "intel,pantherpoint-ahci"; + intel,sata-mode = "ahci"; + intel,sata-port-map = <1>; + intel,sata-port0-gen3-tx = <0x00880a7f>; +}; diff --git a/doc/device-tree-bindings/misc/intel-lpc.txt b/doc/device-tree-bindings/misc/intel-lpc.txt new file mode 100644 index 0000000..ba6ca9d --- /dev/null +++ b/doc/device-tree-bindings/misc/intel-lpc.txt @@ -0,0 +1,64 @@ +Intel LPC Device Binding +======================== + +The device tree node which describes the operation of the Intel Low Pin +Count device is as follows: + +Required properties : +- compatible = "intel,lpc" +- intel,alt-gp-smi-enable : Enable SMI sources. This cell is written to the + ALT_GP_SMI_EN register +- intel,gen-dec : Specifies the values for the gen-dec registers. Up to four + cell pairs can be provided - the first of each pair is the base address and + the second is the size. These are written into the GENx_DEC registers of + the LPC device +- intel,gpi-routing : Specifies the GPI routing. There are 16 cells, valid + values are: + 0 No effect (default) + 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + 2 SCI (if corresponding GPIO_EN bit is also set) +- intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H, + one cell for each. + 0x00 - 0000 = Reserved + 0x01 - 0001 = Reserved + 0x02 - 0010 = Reserved + 0x03 - 0011 = IRQ3 + 0x04 - 0100 = IRQ4 + 0x05 - 0101 = IRQ5 + 0x06 - 0110 = IRQ6 + 0x07 - 0111 = IRQ7 + 0x08 - 1000 = Reserved + 0x09 - 1001 = IRQ9 + 0x0A - 1010 = IRQ10 + 0x0B - 1011 = IRQ11 + 0x0C - 1100 = IRQ12 + 0x0D - 1101 = Reserved + 0x0E - 1110 = IRQ14 + 0x0F - 1111 = IRQ15 + PIRQ[n]_ROUT[7] - PIRQ Routing Control + 0x80 - The PIRQ is not routed. + + +Example +------- + +lpc { + compatible = "intel,lpc"; + #address-cells = <1>; + #size-cells = <1>; + intel,gen-dec = <0x800 0xfc 0x900 0xfc>; + + intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b + 0x80 0x80 0x80 0x80>; + /* + * GPI routing + * 0 No effect (default) + * 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is + * also set) + * 2 SCI (if corresponding GPIO_EN bit is also set) + */ + intel,gpi-routing = <0 0 0 0 0 0 0 2 + 1 0 0 0 0 0 0 0>; + /* Enable EC SMI source */ + intel,alt-gp-smi-enable = <0x0100>; +}; diff --git a/doc/device-tree-bindings/video/intel-gma.txt b/doc/device-tree-bindings/video/intel-gma.txt new file mode 100644 index 0000000..914be4f --- /dev/null +++ b/doc/device-tree-bindings/video/intel-gma.txt @@ -0,0 +1,40 @@ +Intel GMA Bindings +================== + +This is the Intel Graphics Media Accelerator. This binding supports selection +of display parameters only. + + +Required properties: + - compatible : "intel,gma"; + +Optional properties: + - intel,dp-hotplug : values for digital port hotplug, one cell per value for + ports B, C and D + - intel,panel-port-select : output port to use: 0=LVDS 1=DP_B 2=DP_C 3=DP_D + - intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms) + + The following delays are in units of 0.1ms: + - intel,panel-power-up-delay : T1+T2 time sequence + - intel,panel-power-down-delay : T3 time sequence + - intel,panel-power-backlight-on-delay : T5 time sequence + - intel,panel-power-backlight-off-delay : Tx time sequence + + - intel,cpu-backlight : Value for CPU Backlight PWM + - intel,pch-backlight : Value for PCH Backlight PWM + +Example +------- + +gma { + compatible = "intel,gma"; + intel,dp_hotplug = <0 0 0x06>; + intel,panel-port-select = <1>; + intel,panel-power-cycle-delay = <6>; + intel,panel-power-up-delay = <2000>; + intel,panel-power-down-delay = <500>; + intel,panel-power-backlight-on-delay = <2000>; + intel,panel-power-backlight-off-delay = <2000>; + intel,cpu-backlight = <0x00000200>; + intel,pch-backlight = <0x04000000>; +}; diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt index 0278dda..3e2f622 100644 --- a/doc/driver-model/README.txt +++ b/doc/driver-model/README.txt @@ -750,19 +750,43 @@ device pointers, but this is not currently implemented (the root device pointer is saved but not made available through the driver model API). -Things to punt for later ------------------------- +SPL Support +----------- + +Driver model can operate in SPL. Its efficient implementation and small code +size provide for a small overhead which is acceptable for all but the most +constrained systems. + +To enable driver model in SPL, define CONFIG_SPL_DM. You might want to +consider the following option also. See the main README for more details. + + - CONFIG_SYS_MALLOC_SIMPLE + - CONFIG_DM_WARN + - CONFIG_DM_DEVICE_REMOVE + - CONFIG_DM_STDIO -- SPL support - this will have to be present before many drivers can be -converted, but it seems like we can add it once we are happy with the -core implementation. -That is not to say that no thinking has gone into this - in fact there -is quite a lot there. However, getting these right is non-trivial and -there is a high cost associated with going down the wrong path. +Enabling Driver Model +--------------------- -For SPL, it may be possible to fit in a simplified driver model with only -bind and probe methods, to reduce size. +Driver model is being brought into U-Boot gradually. As each subsystems gets +support, a uclass is created and a CONFIG to enable use of driver model for +that subsystem. + +For example CONFIG_DM_SERIAL enables driver model for serial. With that +defined, the old serial support is not enabled, and your serial driver must +conform to driver model. With that undefined, the old serial support is +enabled and driver model is not available for serial. This means that when +you convert a driver, you must either convert all its boards, or provide for +the driver to be compiled both with and without driver model (generally this +is not very hard). + +See the main README for full details of the available driver model CONFIG +options. + + +Things to punt for later +------------------------ Uclasses are statically numbered at compile time. It would be possible to change this to dynamic numbering, but then we would require some sort of diff --git a/doc/git-mailrc b/doc/git-mailrc index ad22763..6c79a6d 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -14,6 +14,9 @@ alias aaribaud Albert Aribaud <albert.u.boot@aribaud.net> alias abiessmann Andreas Bießmann <andreas.devel@googlemail.com> alias afleming Andy Fleming <afleming@gmail.com> alias ag Anatolij Gustschin <agust@denx.de> +alias alisonwang Alison Wang <alison.wang@freescale.com> +alias angelo_ts Angelo Dureghello <angelo@sysam.it> +alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com> alias galak Kumar Gala <galak@kernel.crashing.org> alias gruss Graeme Russ <graeme.russ@gmail.com> alias hs Heiko Schocher <hs@denx.de> @@ -72,13 +75,13 @@ alias avr32 uboot, abiessmann alias bfin uboot, vapier, sonic alias blackfin bfin -alias m68k uboot, jasonjin +alias m68k uboot, alisonwang, angelo_ts alias coldfire m68k alias microblaze uboot, monstr alias mb microblaze -alias mips uboot, Shinya Kuribayashi <skuribay@pobox.com> +alias mips uboot, danielschwierzeck alias nds32 uboot, macpaul @@ -119,6 +122,7 @@ alias mmc uboot, panto alias nand uboot, scottwood alias net uboot, jhersh alias spi uboot, jagan +alias ubi uboot, hs alias usb uboot, marex alias video uboot, ag alias patman uboot, sjg diff --git a/drivers/Makefile b/drivers/Makefile index 33227c8..5ef58c0 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -16,8 +16,10 @@ obj-y += twserial/ obj-y += video/ obj-y += watchdog/ obj-$(CONFIG_QE) += qe/ +obj-$(CONFIG_U_QE) += qe/ obj-y += memory/ obj-y += pwm/ obj-y += input/ # SOC specific infrastructure drivers. obj-y += soc/ +obj-y += thermal/ diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index e56356e..2ba43ac 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -9,4 +9,4 @@ obj-y = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/debug.o ccflags-y := -I$(srctree)/$(src) -I$(srctree)/$(src)/include \ - -D__PPC__ -D__BIG_ENDIAN__ + $(if $(CONFIG_PPC),-D__PPC__ -D__BIG_ENDIAN__) diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index 3b2ed6e..93b815c 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -46,8 +46,11 @@ * BIOS in u-boot. ****************************************************************************/ #include <common.h> -#include "biosemui.h" +#include <bios_emul.h> +#include <errno.h> #include <malloc.h> +#include <vbe.h> +#include "biosemui.h" /* Length of the BIOS image */ #define MAX_BIOSLEN (128 * 1024L) @@ -59,17 +62,54 @@ static u32 saveBaseAddress14; static u32 saveBaseAddress18; static u32 saveBaseAddress20; +static void atibios_set_vesa_mode(RMREGS *regs, int vesa_mode, + struct vbe_mode_info *mode_info) +{ + debug("VBE: Setting VESA mode %#04x\n", vesa_mode); + /* request linear framebuffer mode */ + vesa_mode |= (1 << 14); + /* request clearing of framebuffer */ + vesa_mode &= ~(1 << 15); + regs->e.eax = VESA_SET_MODE; + regs->e.ebx = vesa_mode; + BE_int86(0x10, regs, regs); + + int offset = 0x2000; + void *buffer = (void *)(M.mem_base + offset); + + u16 buffer_seg = (((unsigned long)offset) >> 4) & 0xff00; + u16 buffer_adr = ((unsigned long)offset) & 0xffff; + regs->e.eax = VESA_GET_MODE_INFO; + regs->e.ebx = 0; + regs->e.ecx = vesa_mode; + regs->e.edx = 0; + regs->e.esi = buffer_seg; + regs->e.edi = buffer_adr; + BE_int86(0x10, regs, regs); + memcpy(mode_info->mode_info_block, buffer, + sizeof(struct vbe_mode_info)); + mode_info->valid = true; + + vesa_mode |= (1 << 14); + /* request clearing of framebuffer */ + vesa_mode &= ~(1 << 15); + regs->e.eax = VESA_SET_MODE; + regs->e.ebx = vesa_mode; + BE_int86(0x10, regs, regs); +} + /**************************************************************************** PARAMETERS: pcidev - PCI device info for the video card on the bus to boot -VGAInfo - BIOS emulator VGA info structure +vga_info - BIOS emulator VGA info structure REMARKS: This function executes the BIOS POST code on the controller. We assume that at this stage the controller has its I/O and memory space enabled and that all other controllers are in a disabled state. ****************************************************************************/ -static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo * VGAInfo) +static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info, + int vesa_mode, struct vbe_mode_info *mode_info) { RMREGS regs; RMSREGS sregs; @@ -84,13 +124,16 @@ static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo * VGAInfo) ((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev); /*Setup the X86 emulator for the VGA BIOS*/ - BE_setVGA(VGAInfo); + BE_setVGA(vga_info); /*Execute the BIOS POST code*/ BE_callRealMode(0xC000, 0x0003, ®s, &sregs); /*Cleanup and exit*/ - BE_getVGA(VGAInfo); + BE_getVGA(vga_info); + + if (vesa_mode != -1) + atibios_set_vesa_mode(®s, vesa_mode, mode_info); } /**************************************************************************** @@ -244,60 +287,61 @@ REMARKS: Loads and POST's the display controllers BIOS, directly from the BIOS image we can extract over the PCI bus. ****************************************************************************/ -static int PCI_postController(pci_dev_t pcidev, BE_VGAInfo * VGAInfo) +static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len, + BE_VGAInfo *vga_info, int vesa_mode, + struct vbe_mode_info *mode_info) { - u32 BIOSImageLen; - uchar *mappedBIOS; - uchar *copyOfBIOS; - - /*Allocate memory to store copy of BIOS from display controller*/ - if ((mappedBIOS = PCI_mapBIOSImage(pcidev)) == NULL) { - printf("videoboot: Video ROM failed to map!\n"); - return false; - } + u32 bios_image_len; + uchar *mapped_bios; + uchar *copy_of_bios; + + if (bios_rom) { + copy_of_bios = bios_rom; + bios_image_len = bios_len; + } else { + /* + * Allocate memory to store copy of BIOS from display + * controller + */ + mapped_bios = PCI_mapBIOSImage(pcidev); + if (mapped_bios == NULL) { + printf("videoboot: Video ROM failed to map!\n"); + return false; + } - BIOSImageLen = mappedBIOS[2] * 512; + bios_image_len = mapped_bios[2] * 512; - if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL) { - printf("videoboot: Out of memory!\n"); - return false; + copy_of_bios = malloc(bios_image_len); + if (copy_of_bios == NULL) { + printf("videoboot: Out of memory!\n"); + return false; + } + memcpy(copy_of_bios, mapped_bios, bios_image_len); + PCI_unmapBIOSImage(pcidev, mapped_bios); } - memcpy(copyOfBIOS, mappedBIOS, BIOSImageLen); - PCI_unmapBIOSImage(pcidev, mappedBIOS); - - /*Save information in VGAInfo structure*/ - VGAInfo->function = PCI_FUNC(pcidev); - VGAInfo->device = PCI_DEV(pcidev); - VGAInfo->bus = PCI_BUS(pcidev); - VGAInfo->pcidev = pcidev; - VGAInfo->BIOSImage = copyOfBIOS; - VGAInfo->BIOSImageLen = BIOSImageLen; + /*Save information in vga_info structure*/ + vga_info->function = PCI_FUNC(pcidev); + vga_info->device = PCI_DEV(pcidev); + vga_info->bus = PCI_BUS(pcidev); + vga_info->pcidev = pcidev; + vga_info->BIOSImage = copy_of_bios; + vga_info->BIOSImageLen = bios_image_len; /*Now execute the BIOS POST for the device*/ - if (copyOfBIOS[0] != 0x55 || copyOfBIOS[1] != 0xAA) { + if (copy_of_bios[0] != 0x55 || copy_of_bios[1] != 0xAA) { printf("videoboot: Video ROM image is invalid!\n"); return false; } - PCI_doBIOSPOST(pcidev, VGAInfo); + PCI_doBIOSPOST(pcidev, vga_info, vesa_mode, mode_info); /*Reset the size of the BIOS image to the final size*/ - VGAInfo->BIOSImageLen = copyOfBIOS[2] * 512; + vga_info->BIOSImageLen = copy_of_bios[2] * 512; return true; } -/**************************************************************************** -PARAMETERS: -pcidev - PCI device info for the video card on the bus to boot -pVGAInfo - Place to return VGA info structure is requested -cleanUp - true to clean up on exit, false to leave emulator active - -REMARKS: -Boots the PCI/AGP video card on the bus using the Video ROM BIOS image -and the X86 BIOS emulator module. -****************************************************************************/ -int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp) +int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **vga_infop) { BE_VGAInfo *VGAInfo; @@ -307,28 +351,70 @@ int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp) /*Initialise the x86 BIOS emulator*/ if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) { printf("videoboot: Out of memory!\n"); - return false; + return -ENOMEM; } memset(VGAInfo, 0, sizeof(*VGAInfo)); BE_init(0, 65536, VGAInfo, 0); + *vga_infop = VGAInfo; - /*Post all the display controller BIOS'es*/ - if (!PCI_postController(pcidev, VGAInfo)) - return false; + return 0; +} - /*Cleanup and exit the emulator if requested. If the BIOS emulator - is needed after booting the card, we will not call BE_exit and - leave it enabled for further use (ie: VESA driver etc). +void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void)) +{ + X86EMU_setupIntrFunc(intnum, (X86EMU_intrFuncs)int_func); +} + +int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len, + BE_VGAInfo *vga_info, int clean_up, int vesa_mode, + struct vbe_mode_info *mode_info) +{ + /*Post all the display controller BIOS'es*/ + if (!PCI_postController(pcidev, bios_rom, bios_len, vga_info, + vesa_mode, mode_info)) + return -EINVAL; + + /* + * Cleanup and exit the emulator if requested. If the BIOS emulator + * is needed after booting the card, we will not call BE_exit and + * leave it enabled for further use (ie: VESA driver etc). */ - if (cleanUp) { + if (clean_up) { BE_exit(); - if (VGAInfo->BIOSImage) - free(VGAInfo->BIOSImage); - free(VGAInfo); - VGAInfo = NULL; + if (vga_info->BIOSImage) + free(vga_info->BIOSImage); + free(vga_info); + vga_info = NULL; } - /*Return VGA info pointer if the caller requested it*/ + + return 0; +} + +/**************************************************************************** +PARAMETERS: +pcidev - PCI device info for the video card on the bus to boot +pVGAInfo - Place to return VGA info structure is requested +cleanUp - true to clean up on exit, false to leave emulator active + +REMARKS: +Boots the PCI/AGP video card on the bus using the Video ROM BIOS image +and the X86 BIOS emulator module. +****************************************************************************/ +int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up) +{ + BE_VGAInfo *VGAInfo; + int ret; + + ret = biosemu_setup(pcidev, &VGAInfo); + if (ret) + return false; + ret = biosemu_run(pcidev, NULL, 0, VGAInfo, clean_up, -1, NULL); + if (ret) + return false; + + /* Return VGA info pointer if the caller requested it*/ if (pVGAInfo) *pVGAInfo = VGAInfo; + return true; } diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c index ad88a53..752a928 100644 --- a/drivers/bios_emulator/besys.c +++ b/drivers/bios_emulator/besys.c @@ -54,12 +54,20 @@ /*------------------------- Global Variables ------------------------------*/ -#ifndef __i386__ +#ifndef CONFIG_X86EMU_RAW_IO static char *BE_biosDate = "08/14/99"; static u8 BE_model = 0xFC; static u8 BE_submodel = 0x00; #endif +#undef DEBUG_IO_ACCESS + +#ifdef DEBUG_IO_ACCESS +#define debug_io(fmt, ...) printf(fmt, ##__VA_ARGS__) +#else +#define debug_io(x, b...) +#endif + /*----------------------------- Implementation ----------------------------*/ /**************************************************************************** @@ -80,38 +88,40 @@ static u8 *BE_memaddr(u32 addr) if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { return (u8*)(_BE_env.biosmem_base + addr - 0xC0000); } else if (addr > _BE_env.biosmem_limit && addr < 0xD0000) { - DB(printf("BE_memaddr: address %#lx may be invalid!\n", addr);) - return M.mem_base; + DB(printf("BE_memaddr: address %#lx may be invalid!\n", + (ulong)addr);) + return (u8 *)M.mem_base; } else if (addr >= 0xA0000 && addr <= 0xBFFFF) { return (u8*)(_BE_env.busmem_base + addr - 0xA0000); } -#ifdef __i386__ +#ifdef CONFIG_X86EMU_RAW_IO else if (addr >= 0xD0000 && addr <= 0xFFFFF) { /* We map the real System BIOS directly on real PC's */ - DB(printf("BE_memaddr: System BIOS address %#lx\n", addr);) - return _BE_env.busmem_base + addr - 0xA0000; + DB(printf("BE_memaddr: System BIOS address %#lx\n", + (ulong)addr);) + return (u8 *)_BE_env.busmem_base + addr - 0xA0000; } #else else if (addr >= 0xFFFF5 && addr < 0xFFFFE) { /* Return a faked BIOS date string for non-x86 machines */ - DB(printf("BE_memaddr - Returning BIOS date\n");) + debug_io("BE_memaddr - Returning BIOS date\n"); return (u8 *)(BE_biosDate + addr - 0xFFFF5); } else if (addr == 0xFFFFE) { /* Return system model identifier for non-x86 machines */ - DB(printf("BE_memaddr - Returning model\n");) + debug_io("BE_memaddr - Returning model\n"); return &BE_model; } else if (addr == 0xFFFFF) { /* Return system submodel identifier for non-x86 machines */ - DB(printf("BE_memaddr - Returning submodel\n");) + debug_io("BE_memaddr - Returning submodel\n"); return &BE_submodel; } #endif else if (addr > M.mem_size - 1) { HALT_SYS(); - return M.mem_base; + return (u8 *)M.mem_base; } - return M.mem_base + addr; + return (u8 *)(M.mem_base + addr); } /**************************************************************************** @@ -230,7 +240,7 @@ void X86API BE_wrl(u32 addr, u32 val) } } -#if defined(DEBUG) || !defined(__i386__) +#if !defined(CONFIG_X86EMU_RAW_IO) /* For Non-Intel machines we may need to emulate some I/O port accesses that * the BIOS may try to access, such as the PCI config registers. @@ -258,6 +268,7 @@ static u8 VGA_inpb (const int port) { u8 val = 0xff; + debug_io("vga_inb.%04X -> ", (u16) port); switch (port) { case 0x3C0: /* 3C0 has funky characteristics because it can act as either @@ -560,7 +571,7 @@ u8 X86API BE_inb(X86EMU_pioAddr port) { u8 val = 0; -#if defined(DEBUG) || !defined(__i386__) +#if !defined(CONFIG_X86EMU_RAW_IO) if (IS_VGA_PORT(port)){ /*seems reading port 0x3c3 return the high 16 bit of io port*/ if(port == 0x3c3) @@ -581,7 +592,12 @@ u8 X86API BE_inb(X86EMU_pioAddr port) val = LOG_inpb(port); } else #endif + { + debug_io("inb.%04X -> ", (u16) port); val = LOG_inpb(port); + debug_io("%02X\n", val); + } + return val; } @@ -601,7 +617,7 @@ u16 X86API BE_inw(X86EMU_pioAddr port) { u16 val = 0; -#if defined(DEBUG) || !defined(__i386__) +#if !defined(CONFIG_X86EMU_RAW_IO) if (IS_PCI_PORT(port)) val = PCI_inp(port, REG_READ_WORD); else if (port < 0x100) { @@ -609,7 +625,12 @@ u16 X86API BE_inw(X86EMU_pioAddr port) val = LOG_inpw(port); } else #endif + { + debug_io("inw.%04X -> ", (u16) port); val = LOG_inpw(port); + debug_io("%04X\n", val); + } + return val; } @@ -629,14 +650,19 @@ u32 X86API BE_inl(X86EMU_pioAddr port) { u32 val = 0; -#if defined(DEBUG) || !defined(__i386__) +#if !defined(CONFIG_X86EMU_RAW_IO) if (IS_PCI_PORT(port)) val = PCI_inp(port, REG_READ_DWORD); else if (port < 0x100) { val = LOG_inpd(port); } else #endif + { + debug_io("inl.%04X -> ", (u16) port); val = LOG_inpd(port); + debug_io("%08X\n", val); + } + return val; } @@ -652,7 +678,7 @@ through to the real hardware if we don't need to special case it. ****************************************************************************/ void X86API BE_outb(X86EMU_pioAddr port, u8 val) { -#if defined(DEBUG) || !defined(__i386__) +#if !defined(CONFIG_X86EMU_RAW_IO) if (IS_VGA_PORT(port)) VGA_outpb(port, val); else if (IS_TIMER_PORT(port)) @@ -668,7 +694,11 @@ void X86API BE_outb(X86EMU_pioAddr port, u8 val) LOG_outpb(port, val); } else #endif + { + debug_io("outb.%04X <- %02X", (u16) port, val); LOG_outpb(port, val); + debug_io("\n"); + } } /**************************************************************************** @@ -683,19 +713,23 @@ through to the real hardware if we don't need to special case it. ****************************************************************************/ void X86API BE_outw(X86EMU_pioAddr port, u16 val) { -#if defined(DEBUG) || !defined(__i386__) - if (IS_VGA_PORT(port)) { - VGA_outpb(port, val); - VGA_outpb(port + 1, val >> 8); - } else if (IS_PCI_PORT(port)) - PCI_outp(port, val, REG_WRITE_WORD); - else if (port < 0x100) { - DB(printf("WARN: MAybe INVALID outw.%04X <- %04X\n", (u16) port, - val);) - LOG_outpw(port, val); - } else +#if !defined(CONFIG_X86EMU_RAW_IO) + if (IS_VGA_PORT(port)) { + VGA_outpb(port, val); + VGA_outpb(port + 1, val >> 8); + } else if (IS_PCI_PORT(port)) { + PCI_outp(port, val, REG_WRITE_WORD); + } else if (port < 0x100) { + DB(printf("WARN: MAybe INVALID outw.%04X <- %04X\n", (u16)port, + val);) + LOG_outpw(port, val); + } else #endif - LOG_outpw(port, val); + { + debug_io("outw.%04X <- %04X", (u16) port, val); + LOG_outpw(port, val); + debug_io("\n"); + } } /**************************************************************************** @@ -710,13 +744,17 @@ through to the real hardware if we don't need to special case it. ****************************************************************************/ void X86API BE_outl(X86EMU_pioAddr port, u32 val) { -#if defined(DEBUG) || !defined(__i386__) - if (IS_PCI_PORT(port)) +#if !defined(CONFIG_X86EMU_RAW_IO) + if (IS_PCI_PORT(port)) { PCI_outp(port, val, REG_WRITE_DWORD); - else if (port < 0x100) { + } else if (port < 0x100) { DB(printf("WARN: INVALID outl.%04X <- %08X\n", (u16) port,val);) LOG_outpd(port, val); } else #endif + { + debug_io("outl.%04X <- %08X", (u16) port, val); LOG_outpd(port, val); + debug_io("\n"); + } } diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c index bcc192f..152d70a 100644 --- a/drivers/bios_emulator/bios.c +++ b/drivers/bios_emulator/bios.c @@ -84,14 +84,14 @@ static void X86API int42(int intno) PM_outpb(0x3c2, PM_inpb(0x3cc) & (u8) ~ 0x02); return; } -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG else { printf("int42: unknown function AH=0x12, BL=0x32, AL=%#02x\n", M.x86.R_AL); } #endif } -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG else { printf("int42: unknown function AH=%#02x, AL=%#02x, BL=%#02x\n", M.x86.R_AH, M.x86.R_AL, M.x86.R_BL); diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h index 8c1f111..7853015 100644 --- a/drivers/bios_emulator/biosemui.h +++ b/drivers/bios_emulator/biosemui.h @@ -48,7 +48,7 @@ #include <asm/io.h> /*---------------------- Macros and type definitions ----------------------*/ -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG #define DB(x) x #else #define DB(x) do{}while(0); diff --git a/drivers/bios_emulator/include/biosemu.h b/drivers/bios_emulator/include/biosemu.h index e92e96e..124d79d 100644 --- a/drivers/bios_emulator/include/biosemu.h +++ b/drivers/bios_emulator/include/biosemu.h @@ -43,6 +43,8 @@ #ifndef __BIOSEMU_H #define __BIOSEMU_H +#include <bios_emul.h> + #ifdef __KERNEL__ #include "x86emu.h" #else @@ -55,57 +57,6 @@ #pragma pack(1) -#ifndef __KERNEL__ -/**************************************************************************** -REMARKS: -Data structure used to describe the details specific to a particular VGA -controller. This information is used to allow the VGA controller to be -swapped on the fly within the BIOS emulator. - -HEADER: -biosemu.h - -MEMBERS: -pciInfo - PCI device information block for the controller -BIOSImage - Pointer to a read/write copy of the BIOS image -BIOSImageLen - Length of the BIOS image -LowMem - Copy of key low memory areas -****************************************************************************/ -typedef struct { - PCIDeviceInfo *pciInfo; - void *BIOSImage; - ulong BIOSImageLen; - uchar LowMem[1536]; -} BE_VGAInfo; -#else -/**************************************************************************** -REMARKS: -Data structure used to describe the details for the BIOS emulator system -environment as used by the X86 emulator library. - -HEADER: -biosemu.h - -MEMBERS: -vgaInfo - VGA BIOS information structure -biosmem_base - Base of the BIOS image -biosmem_limit - Limit of the BIOS image -busmem_base - Base of the VGA bus memory -****************************************************************************/ -typedef struct { - int function; - int device; - int bus; - u32 VendorID; - u32 DeviceID; - pci_dev_t pcidev; - void *BIOSImage; - u32 BIOSImageLen; - u8 LowMem[1536]; -} BE_VGAInfo; - -#endif /* __KERNEL__ */ - #define CRT_C 24 /* 24 CRT Controller Registers */ #define ATT_C 21 /* 21 Attribute Controller Registers */ #define GRA_C 9 /* 9 Graphics Controller Registers */ diff --git a/drivers/bios_emulator/include/x86emu.h b/drivers/bios_emulator/include/x86emu.h index a70a768..b28cdc6 100644 --- a/drivers/bios_emulator/include/x86emu.h +++ b/drivers/bios_emulator/include/x86emu.h @@ -53,9 +53,9 @@ typedef u16 X86EMU_pioAddr; /*---------------------- Macros and type definitions ----------------------*/ -#if defined (CONFIG_ARM) +#if defined(CONFIG_ARM) #define GAS_LINE_COMMENT "@" -#elif defined(CONFIG_MIPS) || defined(CONFIG_PPC) +#elif defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_X86) #define GAS_LINE_COMMENT "#" #elif defined (CONFIG_SH) #define GAS_LINE_COMMENT "!" @@ -153,6 +153,7 @@ extern "C" { /* Use "C" linkage when in C++ mode */ void X86EMU_setupMemFuncs(X86EMU_memFuncs * funcs); void X86EMU_setupPioFuncs(X86EMU_pioFuncs * funcs); void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]); + void X86EMU_setupIntrFunc(int intnum, X86EMU_intrFuncs func); void X86EMU_prepareForInt(int num); /* decode.c */ @@ -160,7 +161,7 @@ extern "C" { /* Use "C" linkage when in C++ mode */ void X86EMU_exec(void); void X86EMU_halt_sys(void); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG #define HALT_SYS() \ printf("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \ X86EMU_halt_sys() diff --git a/drivers/bios_emulator/include/x86emu/debug.h b/drivers/bios_emulator/include/x86emu/debug.h index 268c9d3..304b2bf 100644 --- a/drivers/bios_emulator/include/x86emu/debug.h +++ b/drivers/bios_emulator/include/x86emu/debug.h @@ -48,7 +48,7 @@ #define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ #define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset */ -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG # define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) # define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) # define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) @@ -60,7 +60,7 @@ # define CHECK_DATA_ACCESS() #endif -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG # define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) # define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) # define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) @@ -99,7 +99,11 @@ # define DEBUG_DECODE_NOPRINT() 0 #endif -#ifdef DEBUG +# define ERR_PRINTF(x) printf(x) +# define ERR_PRINTF2(x, y) printf(x, y) + +#ifdef CONFIG_X86EMU_DEBUG103 + # define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ x86emu_decode_printf(x) @@ -129,7 +133,7 @@ # define SAVE_IP_CS(x,y) #endif -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG #define TRACE_REGS() \ if (DEBUG_DISASSEMBLE()) { \ x86emu_just_disassemble(); \ @@ -140,7 +144,7 @@ # define TRACE_REGS() #endif -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG # define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() #else # define SINGLE_STEP() @@ -150,7 +154,7 @@ TRACE_REGS(); \ SINGLE_STEP() -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG # define START_OF_INSTR() # define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); # define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); @@ -160,7 +164,7 @@ # define END_OF_INSTR_NO_TRACE() #endif -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG # define CALL_TRACE(u,v,w,x,s) \ if (DEBUG_TRACECALLREGS()) \ x86emu_dump_regs(); \ @@ -176,7 +180,7 @@ # define RETURN_TRACE(n,u,v) #endif -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG #define DB(x) x #else #define DB(x) diff --git a/drivers/bios_emulator/include/x86emu/regs.h b/drivers/bios_emulator/include/x86emu/regs.h index a7fedd2..2934129 100644 --- a/drivers/bios_emulator/include/x86emu/regs.h +++ b/drivers/bios_emulator/include/x86emu/regs.h @@ -282,7 +282,7 @@ typedef struct { u8 intno; volatile int intr; /* mask of pending interrupts */ int debug; -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG int check; u16 saved_ip; u16 saved_cs; diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c index 2fa8050..27e90e4 100644 --- a/drivers/bios_emulator/x86emu/debug.c +++ b/drivers/bios_emulator/x86emu/debug.c @@ -44,7 +44,7 @@ /*----------------------------- Implementation ----------------------------*/ -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG static void print_encoded_bytes(u16 s, u16 o); static void print_decoded_instruction(void); @@ -211,9 +211,7 @@ void X86EMU_dump_memory(u16 seg, u16 off, u32 amt) u32 start = off & 0xfffffff0; u32 end = (off + 16) & 0xfffffff0; u32 i; - u32 current; - current = start; while (end <= off + amt) { printk("%04x:%04x ", seg, start); for (i = start; i < off; i++) @@ -229,7 +227,7 @@ void X86EMU_dump_memory(u16 seg, u16 off, u32 amt) void x86emu_single_step(void) { char s[1024]; - int ps[10]; + int ps[10]; int ntok; int cmd; int done; @@ -238,8 +236,6 @@ void x86emu_single_step(void) static int breakpoint; static int noDecode = 1; - char *p; - if (DEBUG_BREAK()) { if (M.x86.saved_ip != breakpoint) { return; @@ -255,6 +251,8 @@ void x86emu_single_step(void) offset = M.x86.saved_ip; while (!done) { printk("-"); + ps[1] = 0; /* Avoid dodgy compiler warnings */ + ps[2] = 0; cmd = x86emu_parse_line(s, ps, &ntok); switch (cmd) { case 'u': diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c index a782b81..da44c3d 100644 --- a/drivers/bios_emulator/x86emu/decode.c +++ b/drivers/bios_emulator/x86emu/decode.c @@ -303,7 +303,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline! u8 fetch_data_byte( uint offset) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -322,7 +322,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline! u16 fetch_data_word( uint offset) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -341,7 +341,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline! u32 fetch_data_long( uint offset) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -362,7 +362,7 @@ u8 fetch_data_byte_abs( uint segment, uint offset) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -383,7 +383,7 @@ u16 fetch_data_word_abs( uint segment, uint offset) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -404,7 +404,7 @@ u32 fetch_data_long_abs( uint segment, uint offset) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -426,7 +426,7 @@ void store_data_byte( uint offset, u8 val) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -448,7 +448,7 @@ void store_data_word( uint offset, u16 val) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -470,7 +470,7 @@ void store_data_long( uint offset, u32 val) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -493,7 +493,7 @@ void store_data_byte_abs( uint offset, u8 val) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -516,7 +516,7 @@ void store_data_word_abs( uint offset, u16 val) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -539,7 +539,7 @@ void store_data_long_abs( uint offset, u32 val) { -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index f8e093d..2bb5e2d 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -79,7 +79,7 @@ /* constant arrays to do several instructions in just one function */ -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG static char *x86emu_GenOpName[8] = { "ADD", "OR", "ADC", "SBB", "AND", "SUB", "XOR", "CMP"}; #endif @@ -160,7 +160,7 @@ static u32 (*opcD1_long_operation[])(u32 s, u8 d) = sar_long, }; -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG static char *opF6_names[8] = { "TEST\t", "", "NOT\t", "NEG\t", "MUL\t", "IMUL\t", "DIV\t", "IDIV\t" }; @@ -179,7 +179,7 @@ void x86emuOp_illegal_op( { START_OF_INSTR(); if (M.x86.R_SP != 0) { - DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); + ERR_PRINTF("ILLEGAL X86 OPCODE\n"); TRACE_REGS(); DB( printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", M.x86.R_CS, M.x86.R_IP-1,op1)); @@ -1281,7 +1281,7 @@ void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1359,7 +1359,7 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1475,7 +1475,7 @@ void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1551,7 +1551,7 @@ void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -2148,7 +2148,7 @@ void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("POP\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + ERR_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); HALT_SYS(); } if (mod < 3) { @@ -3083,7 +3083,7 @@ void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3158,7 +3158,7 @@ void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3347,7 +3347,7 @@ void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); + ERR_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); HALT_SYS(); } if (mod < 3) { @@ -3381,7 +3381,7 @@ void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + ERR_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); HALT_SYS(); } if (mod < 3) { @@ -3630,7 +3630,7 @@ void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3701,7 +3701,7 @@ void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3803,7 +3803,7 @@ void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3876,7 +3876,7 @@ void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3968,7 +3968,7 @@ void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("AAM\n"); a = fetch_byte_imm(); /* this is a stupid encoding. */ if (a != 10) { - DECODE_PRINTF("ERROR DECODING AAM\n"); + ERR_PRINTF("ERROR DECODING AAM\n"); TRACE_REGS(); HALT_SYS(); } @@ -4443,7 +4443,7 @@ void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) test_byte(destval, srcval); break; case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: @@ -4490,7 +4490,7 @@ void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) test_byte(*destreg, srcval); break; case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: @@ -4559,7 +4559,7 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) test_long(destval, srcval); break; case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); HALT_SYS(); break; case 2: @@ -4611,7 +4611,7 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) test_word(destval, srcval); break; case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); HALT_SYS(); break; case 2: @@ -4666,7 +4666,7 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) test_long(*destreg, srcval); break; case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: @@ -4715,7 +4715,7 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) test_word(*destreg, srcval); break; case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + ERR_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); HALT_SYS(); break; case 2: @@ -4859,7 +4859,7 @@ void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) /* Yet another special case instruction. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -4879,7 +4879,7 @@ void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) case 5: case 6: case 7: - DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); + ERR_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x\n", mod); HALT_SYS(); break; } @@ -4923,7 +4923,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) /* Yet another special case instruction. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_X86EMU_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -4961,7 +4961,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("PUSH\t"); break; case 7: - DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); + ERR_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); HALT_SYS(); break; } @@ -5092,7 +5092,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) M.x86.R_IP = *destreg; break; case 3: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + ERR_PRINTF("OPERATION UNDEFINED 0XFF\n"); TRACE_AND_STEP(); HALT_SYS(); break; @@ -5104,7 +5104,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) M.x86.R_IP = (u16) (*destreg); break; case 5: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + ERR_PRINTF("OPERATION UNDEFINED 0XFF\n"); TRACE_AND_STEP(); HALT_SYS(); break; diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index 59dbb42..be4ef36 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -58,7 +58,7 @@ void x86emuOp2_illegal_op( u8 op2) { START_OF_INSTR(); - DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + ERR_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); TRACE_REGS(); printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", M.x86.R_CS, M.x86.R_IP-2,op2); @@ -1089,7 +1089,7 @@ void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BTC\t"); break; default: - DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + ERR_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); TRACE_REGS(); printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl); diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c index 21f9730..0ba9c0c 100644 --- a/drivers/bios_emulator/x86emu/sys.c +++ b/drivers/bios_emulator/x86emu/sys.c @@ -273,6 +273,11 @@ void X86EMU_setupPioFuncs(X86EMU_pioFuncs * funcs) sys_outl = funcs->outl; } +void X86EMU_setupIntrFunc(int intnum, X86EMU_intrFuncs func) +{ + _X86EMU_intrTab[intnum] = func; +} + /**************************************************************************** PARAMETERS: funcs - New interrupt vector table to make active diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index a93a8e1..c9a3beb 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -730,7 +730,7 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) u16 now_blocks; /* number of blocks per iteration */ u32 transfer_size; /* number of bytes per iteration */ - now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks); + now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks); transfer_size = ATA_SECT_SIZE * now_blocks; if (transfer_size > user_buffer_size) { diff --git a/drivers/block/ata_piix.c b/drivers/block/ata_piix.c index 5cf91ad..3042684 100644 --- a/drivers/block/ata_piix.c +++ b/drivers/block/ata_piix.c @@ -192,6 +192,11 @@ int init_sata(int dev) return 0; } +int reset_sata(int dev) +{ + return 0; +} + static inline u8 sata_inb(unsigned long ioaddr) { return inb(ioaddr); diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c index c68fd2f..01a4148 100644 --- a/drivers/block/dwc_ahsata.c +++ b/drivers/block/dwc_ahsata.c @@ -592,6 +592,29 @@ int init_sata(int dev) return 0; } +int reset_sata(int dev) +{ + struct ahci_probe_ent *probe_ent; + struct sata_host_regs *host_mmio; + + if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { + printf("The sata index %d is out of ranges\n\r", dev); + return -1; + } + + probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + if (NULL == probe_ent) + /* not initialized, so nothing to reset */ + return 0; + + host_mmio = (struct sata_host_regs *)probe_ent->mmio_base; + setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); + while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) + udelay(100); + + return 0; +} + static void dwc_ahsata_print_info(int dev) { block_dev_desc_t *pdev = &(sata_dev_desc[dev]); diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index ebd6261..71d7cec 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -255,6 +255,11 @@ int init_sata(int dev) return 0; } +int reset_sata(int dev) +{ + return 0; +} + static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg) { printf("\n\rSATA: %08x\n\r", (u32)reg); diff --git a/drivers/block/pata_bfin.c b/drivers/block/pata_bfin.c index b7fd1cd..c2673bd 100644 --- a/drivers/block/pata_bfin.c +++ b/drivers/block/pata_bfin.c @@ -1009,6 +1009,11 @@ int init_sata(int dev) return res; } +int reset_sata(int dev) +{ + return 0; +} + /* Read up to 255 sectors * * Returns sectors read diff --git a/drivers/block/pata_bfin.h b/drivers/block/pata_bfin.h index 2093cf0..b678f60 100644 --- a/drivers/block/pata_bfin.h +++ b/drivers/block/pata_bfin.h @@ -43,7 +43,6 @@ struct ata_port { #define DRV_NAME "pata-bfin" #define DRV_VERSION "0.9" -#define __iomem #define ATA_REG_CTRL 0x0E #define ATA_REG_ALTSTATUS ATA_REG_CTRL diff --git a/drivers/block/sata_dwc.c b/drivers/block/sata_dwc.c index efca5ea..9e8b067 100644 --- a/drivers/block/sata_dwc.c +++ b/drivers/block/sata_dwc.c @@ -423,6 +423,11 @@ int init_sata(int dev) return rc; } +int reset_sata(int dev) +{ + return 0; +} + static u8 ata_check_altstatus(struct ata_port *ap) { u8 val = 0; diff --git a/drivers/block/sata_sil.c b/drivers/block/sata_sil.c index 1f510cd..daff7d4 100644 --- a/drivers/block/sata_sil.c +++ b/drivers/block/sata_sil.c @@ -519,7 +519,7 @@ int init_sata(int dev) u16 word; if (init_done == 1 && dev < sata_info.maxport) - return 1; + return 0; init_done = 1; @@ -571,6 +571,11 @@ int init_sata(int dev) return 0; } +int reset_sata(int dev) +{ + return 0; +} + /* * SATA interface between low level driver and command layer */ diff --git a/drivers/block/sata_sil3114.c b/drivers/block/sata_sil3114.c index 3aa6fc9..61ffb66 100644 --- a/drivers/block/sata_sil3114.c +++ b/drivers/block/sata_sil3114.c @@ -702,6 +702,11 @@ int init_sata (int dev) return res; } +int reset_sata(int dev) +{ + return 0; +} + /* Check if device is connected to port */ int sata_bus_probe (int portno) { diff --git a/drivers/core/Makefile b/drivers/core/Makefile index 151c239..f14695b 100644 --- a/drivers/core/Makefile +++ b/drivers/core/Makefile @@ -4,5 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := device.o lists.o root.o uclass.o util.o +obj-$(CONFIG_DM) += device.o lists.o root.o uclass.o util.o obj-$(CONFIG_OF_CONTROL) += simple-bus.o +obj-$(CONFIG_DM_DEVICE_REMOVE) += device-remove.o diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c new file mode 100644 index 0000000..8fc6b71 --- /dev/null +++ b/drivers/core/device-remove.c @@ -0,0 +1,187 @@ +/* + * Device manager + * + * Copyright (c) 2014 Google, Inc + * + * (C) Copyright 2012 + * Pavel Herrmann <morpheus.ibis@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <malloc.h> +#include <dm/device.h> +#include <dm/device-internal.h> +#include <dm/uclass.h> +#include <dm/uclass-internal.h> +#include <dm/util.h> + +/** + * device_chld_unbind() - Unbind all device's children from the device + * + * On error, the function continues to unbind all children, and reports the + * first error. + * + * @dev: The device that is to be stripped of its children + * @return 0 on success, -ve on error + */ +static int device_chld_unbind(struct udevice *dev) +{ + struct udevice *pos, *n; + int ret, saved_ret = 0; + + assert(dev); + + list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) { + ret = device_unbind(pos); + if (ret && !saved_ret) + saved_ret = ret; + } + + return saved_ret; +} + +/** + * device_chld_remove() - Stop all device's children + * @dev: The device whose children are to be removed + * @return 0 on success, -ve on error + */ +static int device_chld_remove(struct udevice *dev) +{ + struct udevice *pos, *n; + int ret; + + assert(dev); + + list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) { + ret = device_remove(pos); + if (ret) + return ret; + } + + return 0; +} + +int device_unbind(struct udevice *dev) +{ + struct driver *drv; + int ret; + + if (!dev) + return -EINVAL; + + if (dev->flags & DM_FLAG_ACTIVATED) + return -EINVAL; + + drv = dev->driver; + assert(drv); + + if (drv->unbind) { + ret = drv->unbind(dev); + if (ret) + return ret; + } + + ret = device_chld_unbind(dev); + if (ret) + return ret; + + ret = uclass_unbind_device(dev); + if (ret) + return ret; + + if (dev->parent) + list_del(&dev->sibling_node); + free(dev); + + return 0; +} + +/** + * device_free() - Free memory buffers allocated by a device + * @dev: Device that is to be started + */ +void device_free(struct udevice *dev) +{ + int size; + + if (dev->driver->priv_auto_alloc_size) { + free(dev->priv); + dev->priv = NULL; + } + if (dev->flags & DM_FLAG_ALLOC_PDATA) { + free(dev->platdata); + dev->platdata = NULL; + } + size = dev->uclass->uc_drv->per_device_auto_alloc_size; + if (size) { + free(dev->uclass_priv); + dev->uclass_priv = NULL; + } + if (dev->parent) { + size = dev->parent->driver->per_child_auto_alloc_size; + if (size) { + free(dev->parent_priv); + dev->parent_priv = NULL; + } + } +} + +int device_remove(struct udevice *dev) +{ + struct driver *drv; + int ret; + + if (!dev) + return -EINVAL; + + if (!(dev->flags & DM_FLAG_ACTIVATED)) + return 0; + + drv = dev->driver; + assert(drv); + + ret = uclass_pre_remove_device(dev); + if (ret) + return ret; + + ret = device_chld_remove(dev); + if (ret) + goto err; + + if (drv->remove) { + ret = drv->remove(dev); + if (ret) + goto err_remove; + } + + if (dev->parent && dev->parent->driver->child_post_remove) { + ret = dev->parent->driver->child_post_remove(dev); + if (ret) { + dm_warn("%s: Device '%s' failed child_post_remove()", + __func__, dev->name); + } + } + + device_free(dev); + + dev->seq = -1; + dev->flags &= ~DM_FLAG_ACTIVATED; + + return ret; + +err_remove: + /* We can't put the children back */ + dm_warn("%s: Device '%s' failed to remove, but children are gone\n", + __func__, dev->name); +err: + ret = uclass_post_probe_device(dev); + if (ret) { + dm_warn("%s: Device '%s' failed to post_probe on error path\n", + __func__, dev->name); + } + + return ret; +} diff --git a/drivers/core/device.c b/drivers/core/device.c index 49faa29..6793e1c 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -24,52 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; -/** - * device_chld_unbind() - Unbind all device's children from the device - * - * On error, the function continues to unbind all children, and reports the - * first error. - * - * @dev: The device that is to be stripped of its children - * @return 0 on success, -ve on error - */ -static int device_chld_unbind(struct udevice *dev) -{ - struct udevice *pos, *n; - int ret, saved_ret = 0; - - assert(dev); - - list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) { - ret = device_unbind(pos); - if (ret && !saved_ret) - saved_ret = ret; - } - - return saved_ret; -} - -/** - * device_chld_remove() - Stop all device's children - * @dev: The device whose children are to be removed - * @return 0 on success, -ve on error - */ -static int device_chld_remove(struct udevice *dev) -{ - struct udevice *pos, *n; - int ret; - - assert(dev); - - list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) { - ret = device_remove(pos); - if (ret) - return ret; - } - - return 0; -} - int device_bind(struct udevice *parent, struct driver *drv, const char *name, void *platdata, int of_offset, struct udevice **devp) { @@ -167,71 +121,6 @@ int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, -1, devp); } -int device_unbind(struct udevice *dev) -{ - struct driver *drv; - int ret; - - if (!dev) - return -EINVAL; - - if (dev->flags & DM_FLAG_ACTIVATED) - return -EINVAL; - - drv = dev->driver; - assert(drv); - - if (drv->unbind) { - ret = drv->unbind(dev); - if (ret) - return ret; - } - - ret = device_chld_unbind(dev); - if (ret) - return ret; - - ret = uclass_unbind_device(dev); - if (ret) - return ret; - - if (dev->parent) - list_del(&dev->sibling_node); - free(dev); - - return 0; -} - -/** - * device_free() - Free memory buffers allocated by a device - * @dev: Device that is to be started - */ -static void device_free(struct udevice *dev) -{ - int size; - - if (dev->driver->priv_auto_alloc_size) { - free(dev->priv); - dev->priv = NULL; - } - if (dev->flags & DM_FLAG_ALLOC_PDATA) { - free(dev->platdata); - dev->platdata = NULL; - } - size = dev->uclass->uc_drv->per_device_auto_alloc_size; - if (size) { - free(dev->uclass_priv); - dev->uclass_priv = NULL; - } - if (dev->parent) { - size = dev->parent->driver->per_child_auto_alloc_size; - if (size) { - free(dev->parent_priv); - dev->parent_priv = NULL; - } - } -} - int device_probe_child(struct udevice *dev, void *parent_priv) { struct driver *drv; @@ -342,63 +231,6 @@ int device_probe(struct udevice *dev) return device_probe_child(dev, NULL); } -int device_remove(struct udevice *dev) -{ - struct driver *drv; - int ret; - - if (!dev) - return -EINVAL; - - if (!(dev->flags & DM_FLAG_ACTIVATED)) - return 0; - - drv = dev->driver; - assert(drv); - - ret = uclass_pre_remove_device(dev); - if (ret) - return ret; - - ret = device_chld_remove(dev); - if (ret) - goto err; - - if (drv->remove) { - ret = drv->remove(dev); - if (ret) - goto err_remove; - } - - if (dev->parent && dev->parent->driver->child_post_remove) { - ret = dev->parent->driver->child_post_remove(dev); - if (ret) { - dm_warn("%s: Device '%s' failed child_post_remove()", - __func__, dev->name); - } - } - - device_free(dev); - - dev->seq = -1; - dev->flags &= ~DM_FLAG_ACTIVATED; - - return ret; - -err_remove: - /* We can't put the children back */ - dm_warn("%s: Device '%s' failed to remove, but children are gone\n", - __func__, dev->name); -err: - ret = uclass_post_probe_device(dev); - if (ret) { - dm_warn("%s: Device '%s' failed to post_probe on error path\n", - __func__, dev->name); - } - - return ret; -} - void *dev_get_platdata(struct udevice *dev) { if (!dev) { @@ -548,3 +380,13 @@ int device_find_next_child(struct udevice **devp) return 0; } + +struct udevice *dev_get_parent(struct udevice *child) +{ + return child->parent; +} + +ulong dev_get_of_data(struct udevice *dev) +{ + return dev->of_id->data; +} diff --git a/drivers/core/lists.c b/drivers/core/lists.c index 3a1ea85..ff115c4 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -25,9 +25,6 @@ struct driver *lists_driver_lookup_name(const char *name) const int n_ents = ll_entry_count(struct driver, driver); struct driver *entry; - if (!drv || !n_ents) - return NULL; - for (entry = drv; entry != drv + n_ents; entry++) { if (!strcmp(name, entry->name)) return entry; @@ -44,9 +41,6 @@ struct uclass_driver *lists_uclass_lookup(enum uclass_id id) const int n_ents = ll_entry_count(struct uclass_driver, uclass); struct uclass_driver *entry; - if ((id == UCLASS_INVALID) || !uclass) - return NULL; - for (entry = uclass; entry != uclass + n_ents; entry++) { if (entry->id == id) return entry; @@ -77,34 +71,60 @@ int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only) return result; } +int device_bind_driver(struct udevice *parent, const char *drv_name, + const char *dev_name, struct udevice **devp) +{ + struct driver *drv; + int ret; + + drv = lists_driver_lookup_name(drv_name); + if (!drv) { + printf("Cannot find driver '%s'\n", drv_name); + return -ENOENT; + } + ret = device_bind(parent, drv, dev_name, NULL, -1, devp); + if (ret) { + printf("Cannot create device named '%s' (err=%d)\n", + dev_name, ret); + return ret; + } + + return 0; +} + #ifdef CONFIG_OF_CONTROL /** * driver_check_compatible() - Check if a driver is compatible with this node * * @param blob: Device tree pointer * @param offset: Offset of node in device tree - * @param of_matchL List of compatible strings to match + * @param of_match: List of compatible strings to match + * @param of_idp: Returns the match that was found * @return 0 if there is a match, -ENOENT if no match, -ENODEV if the node * does not have a compatible string, other error <0 if there is a device * tree error */ static int driver_check_compatible(const void *blob, int offset, - const struct udevice_id *of_match) + const struct udevice_id *of_match, + const struct udevice_id **of_idp) { int ret; + *of_idp = NULL; if (!of_match) return -ENOENT; while (of_match->compatible) { ret = fdt_node_check_compatible(blob, offset, of_match->compatible); - if (!ret) + if (!ret) { + *of_idp = of_match; return 0; - else if (ret == -FDT_ERR_NOTFOUND) + } else if (ret == -FDT_ERR_NOTFOUND) { return -ENODEV; - else if (ret < 0) + } else if (ret < 0) { return -EINVAL; + } of_match++; } @@ -116,6 +136,7 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, { struct driver *driver = ll_entry_start(struct driver, driver); const int n_ents = ll_entry_count(struct driver, driver); + const struct udevice_id *id; struct driver *entry; struct udevice *dev; bool found = false; @@ -127,7 +148,8 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, if (devp) *devp = NULL; for (entry = driver; entry != driver + n_ents; entry++) { - ret = driver_check_compatible(blob, offset, entry->of_match); + ret = driver_check_compatible(blob, offset, entry->of_match, + &id); name = fdt_get_name(blob, offset, NULL); if (ret == -ENOENT) { continue; @@ -136,8 +158,7 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, break; } else if (ret) { dm_warn("Device tree error at offset %d\n", offset); - if (!result || ret != -ENOENT) - result = ret; + result = ret; break; } @@ -147,6 +168,7 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, dm_warn("Error binding driver '%s'\n", entry->name); return ret; } else { + dev->of_id = id; found = true; if (devp) *devp = dev; diff --git a/drivers/core/root.c b/drivers/core/root.c index a328a48..47b3acf 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -73,10 +73,8 @@ int dm_scan_platdata(bool pre_reloc_only) dm_warn("Some drivers were not found\n"); ret = 0; } - if (ret) - return ret; - return 0; + return ret; } #ifdef CONFIG_OF_CONTROL diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index 59f2fd6..c139da6 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -92,7 +92,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); - ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); @@ -105,9 +104,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - ddr_out32(&ddr->init_addr, regs->ddr_init_addr); - ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); @@ -128,7 +124,24 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); - ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + ddr_out32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); + ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); + + /* DRAM VRef will not be trained */ + ddr_out32(&ddr->ddr_cdr2, + regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); + } else +#endif + { + ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + ddr_out32(&ddr->init_addr, regs->ddr_init_addr); + ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); + } ddr_out32(&ddr->err_disable, regs->err_disable); ddr_out32(&ddr->err_int_en, regs->err_int_en); for (i = 0; i < 32; i++) { @@ -167,8 +180,20 @@ step2: udelay(500); asm volatile("dsb sy;isb"); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* enter self-refresh */ + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); + temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); + /* do board specific memory setup */ + board_mem_sleep_setup(); + + temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); + } else +#endif + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; /* Let the controller go */ - temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); asm volatile("dsb sy;isb"); @@ -211,4 +236,12 @@ step2: if (timeout <= 0) printf("Waiting for D_INIT timeout. Memory may not work.\n"); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* exit self-refresh */ + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); + temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); + } +#endif } diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 9a156bf..fe8aa98 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -253,22 +253,30 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ #if !defined(CONFIG_SYS_FSL_DDR1) +/* + * Check DIMM configuration, return 2 if quad-rank or two dual-rank + * Return 1 if other two slots configuration. Return 0 if single slot. + */ static inline int avoid_odt_overlap(const dimm_params_t *dimm_params) { #if CONFIG_DIMM_SLOTS_PER_CTLR == 1 if (dimm_params[0].n_ranks == 4) - return 1; + return 2; #endif #if CONFIG_DIMM_SLOTS_PER_CTLR == 2 if ((dimm_params[0].n_ranks == 2) && (dimm_params[1].n_ranks == 2)) - return 1; + return 2; #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE if (dimm_params[0].n_ranks == 4) - return 1; + return 2; #endif + + if ((dimm_params[0].n_ranks != 0) && + (dimm_params[2].n_ranks != 0)) + return 1; #endif return 0; } @@ -303,7 +311,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, #ifdef CONFIG_SYS_FSL_DDR4 /* tXP=max(4nCK, 6ns) */ - int txp = max(mclk_ps * 4, 6000); /* unit=ps */ + int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */ trwt_mclk = 2; twrt_mclk = 1; act_pd_exit_mclk = picos_to_mclk(txp); @@ -312,10 +320,11 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, * MRS_CYC = max(tMRD, tMOD) * tMRD = 8nCK, tMOD = max(24nCK, 15ns) */ - tmrd_mclk = max(24, picos_to_mclk(15000)); + tmrd_mclk = max(24U, picos_to_mclk(15000)); #elif defined(CONFIG_SYS_FSL_DDR3) unsigned int data_rate = get_ddr_freq(0); int txp; + int odt_overlap; /* * (tXARD and tXARDS). Empirical? * The DDR3 spec has not tXARD, @@ -325,19 +334,29 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, * spec has not the tAXPD, we use * tAXPD=1, need design to confirm. */ - txp = max(mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000)); + txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000)); tmrd_mclk = 4; /* set the turnaround time */ /* - * for single quad-rank DIMM and two dual-rank DIMMs + * for single quad-rank DIMM and two-slot DIMMs * to avoid ODT overlap */ - if (avoid_odt_overlap(dimm_params)) { + odt_overlap = avoid_odt_overlap(dimm_params); + switch (odt_overlap) { + case 2: twwt_mclk = 2; trrt_mclk = 1; + break; + case 1: + twwt_mclk = 1; + trrt_mclk = 0; + break; + default: + break; } + /* for faster clock, need more time for data setup */ trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1; @@ -383,7 +402,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, ); debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); } -#endif /* defined(CONFIG_SYS_FSL_DDR2) */ +#endif /* !defined(CONFIG_SYS_FSL_DDR1) */ /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, @@ -511,8 +530,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, #ifdef CONFIG_SYS_FSL_DDR4 refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8; wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); - acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4); - wrtord_mclk = max(2, picos_to_mclk(2500)); + acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U); + wrtord_mclk = max(2U, picos_to_mclk(2500)); if ((wrrec_mclk < 1) || (wrrec_mclk > 24)) printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); else @@ -627,14 +646,14 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, wr_data_delay = popts->write_data_delay; #ifdef CONFIG_SYS_FSL_DDR4 cpo = 0; - cke_pls = max(3, picos_to_mclk(5000)); + cke_pls = max(3U, picos_to_mclk(5000)); #elif defined(CONFIG_SYS_FSL_DDR3) /* * cke pulse = max(3nCK, 7.5ns) for DDR3-800 * max(3nCK, 5.625ns) for DDR3-1066, 1333 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133 */ - cke_pls = max(3, picos_to_mclk(mclk_ps > 1870 ? 7500 : + cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 : (mclk_ps > 1245 ? 5625 : 5000))); #else cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR; @@ -1810,9 +1829,9 @@ static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr, unsigned int txpr, tcksre, tcksrx; unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd; - txpr = max(5, picos_to_mclk(common_dimm->trfc1_ps + 10000)); - tcksre = max(5, picos_to_mclk(10000)); - tcksrx = max(5, picos_to_mclk(10000)); + txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000)); + tcksre = max(5U, picos_to_mclk(10000)); + tcksrx = max(5U, picos_to_mclk(10000)); par_lat = 0; cs_to_cmd = 0; @@ -1877,7 +1896,7 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr, } acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps); - wrtord_bg = max(4, picos_to_mclk(7500)); + wrtord_bg = max(4U, picos_to_mclk(7500)); if (popts->otf_burst_chop_en) wrtord_bg += 2; diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c index 2418dca..aaddc8f 100644 --- a/drivers/ddr/fsl/ddr4_dimm_params.c +++ b/drivers/ddr/fsl/ddr4_dimm_params.c @@ -126,6 +126,12 @@ ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd, { unsigned int retval; int i; + const u8 udimm_rc_e_dq[18] = { + 0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15, + 0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36 + }; + int spd_error = 0; + u8 *ptr; if (spd->mem_type) { if (spd->mem_type != SPD_MEMTYPE_DDR4) { @@ -179,6 +185,22 @@ ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd, /* Unbuffered DIMMs */ if (spd->mod_section.unbuffered.addr_mapping & 0x1) pdimm->mirrored_dimm = 1; + if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 && + (spd->mod_section.unbuffered.ref_raw_card == 0x04)) { + /* Fix SPD error found on DIMMs with raw card E0 */ + for (i = 0; i < 18; i++) { + if (spd->mapping[i] == udimm_rc_e_dq[i]) + continue; + spd_error = 1; + debug("SPD byte %d: 0x%x, should be 0x%x\n", + 60 + i, spd->mapping[i], + udimm_rc_e_dq[i]); + ptr = (u8 *)&spd->mapping[i]; + *ptr = udimm_rc_e_dq[i]; + } + if (spd_error) + puts("SPD DQ mapping error fixed\n"); + } break; default: diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index e024db9..a3c01e7 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -103,7 +103,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->dq_map_1, regs->dq_map_1); ddr_out32(&ddr->dq_map_2, regs->dq_map_2); ddr_out32(&ddr->dq_map_3, regs->dq_map_3); - ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); @@ -124,8 +123,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); - ddr_out32(&ddr->init_addr, regs->ddr_init_addr); - ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); #ifndef CONFIG_SYS_FSL_DDR_EMU /* @@ -147,7 +144,24 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); - ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + ddr_out32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); + ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); + + /* DRAM VRef will not be trained */ + ddr_out32(&ddr->ddr_cdr2, + regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); + } else +#endif + { + ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + ddr_out32(&ddr->init_addr, regs->ddr_init_addr); + ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); + } ddr_out32(&ddr->err_disable, regs->err_disable); ddr_out32(&ddr->err_int_en, regs->err_int_en); for (i = 0; i < 32; i++) { @@ -187,8 +201,20 @@ step2: mb(); isb(); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* enter self-refresh */ + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); + temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); + /* do board specific memory setup */ + board_mem_sleep_setup(); + + temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); + } else +#endif + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; /* Let the controller go */ - temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); mb(); isb(); @@ -233,4 +259,12 @@ step2: if (timeout <= 0) printf("Waiting for D_INIT timeout. Memory may not work.\n"); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* exit self-refresh */ + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); + temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); + } +#endif } diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c index 05a24dd..73db444 100644 --- a/drivers/ddr/fsl/lc_common_dimm_params.c +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -289,48 +289,58 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, * Find minimum tckmax_ps to find fastest slow speed, * i.e., this is the slowest the whole system can go. */ - tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps); + tckmax_ps = min(tckmax_ps, + (unsigned int)dimm_params[i].tckmax_ps); #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) - taamin_ps = max(taamin_ps, dimm_params[i].taa_ps); + taamin_ps = max(taamin_ps, + (unsigned int)dimm_params[i].taa_ps); #endif - tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps); - trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps); - trp_ps = max(trp_ps, dimm_params[i].trp_ps); - tras_ps = max(tras_ps, dimm_params[i].tras_ps); + tckmin_x_ps = max(tckmin_x_ps, + (unsigned int)dimm_params[i].tckmin_x_ps); + trcd_ps = max(trcd_ps, (unsigned int)dimm_params[i].trcd_ps); + trp_ps = max(trp_ps, (unsigned int)dimm_params[i].trp_ps); + tras_ps = max(tras_ps, (unsigned int)dimm_params[i].tras_ps); #ifdef CONFIG_SYS_FSL_DDR4 - trfc1_ps = max(trfc1_ps, dimm_params[i].trfc1_ps); - trfc2_ps = max(trfc2_ps, dimm_params[i].trfc2_ps); - trfc4_ps = max(trfc4_ps, dimm_params[i].trfc4_ps); - trrds_ps = max(trrds_ps, dimm_params[i].trrds_ps); - trrdl_ps = max(trrdl_ps, dimm_params[i].trrdl_ps); - tccdl_ps = max(tccdl_ps, dimm_params[i].tccdl_ps); + trfc1_ps = max(trfc1_ps, + (unsigned int)dimm_params[i].trfc1_ps); + trfc2_ps = max(trfc2_ps, + (unsigned int)dimm_params[i].trfc2_ps); + trfc4_ps = max(trfc4_ps, + (unsigned int)dimm_params[i].trfc4_ps); + trrds_ps = max(trrds_ps, + (unsigned int)dimm_params[i].trrds_ps); + trrdl_ps = max(trrdl_ps, + (unsigned int)dimm_params[i].trrdl_ps); + tccdl_ps = max(tccdl_ps, + (unsigned int)dimm_params[i].tccdl_ps); #else - twr_ps = max(twr_ps, dimm_params[i].twr_ps); - twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps); - trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps); - trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps); - trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps); + twr_ps = max(twr_ps, (unsigned int)dimm_params[i].twr_ps); + twtr_ps = max(twtr_ps, (unsigned int)dimm_params[i].twtr_ps); + trfc_ps = max(trfc_ps, (unsigned int)dimm_params[i].trfc_ps); + trrd_ps = max(trrd_ps, (unsigned int)dimm_params[i].trrd_ps); + trtp_ps = max(trtp_ps, (unsigned int)dimm_params[i].trtp_ps); #endif - trc_ps = max(trc_ps, dimm_params[i].trc_ps); + trc_ps = max(trc_ps, (unsigned int)dimm_params[i].trc_ps); #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) - tis_ps = max(tis_ps, dimm_params[i].tis_ps); - tih_ps = max(tih_ps, dimm_params[i].tih_ps); - tds_ps = max(tds_ps, dimm_params[i].tds_ps); - tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps); - tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps); + tis_ps = max(tis_ps, (unsigned int)dimm_params[i].tis_ps); + tih_ps = max(tih_ps, (unsigned int)dimm_params[i].tih_ps); + tds_ps = max(tds_ps, (unsigned int)dimm_params[i].tds_ps); + tdh_ps = max(tdh_ps, (unsigned int)dimm_params[i].tdh_ps); + tqhs_ps = max(tqhs_ps, (unsigned int)dimm_params[i].tqhs_ps); /* * Find maximum tdqsq_max_ps to find slowest. * * FIXME: is finding the slowest value the correct * strategy for this parameter? */ - tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps); + tdqsq_max_ps = max(tdqsq_max_ps, + (unsigned int)dimm_params[i].tdqsq_max_ps); #endif refresh_rate_ps = max(refresh_rate_ps, - dimm_params[i].refresh_rate_ps); + (unsigned int)dimm_params[i].refresh_rate_ps); /* extended_op_srt is either 0 or 1, 0 having priority */ extended_op_srt = min(extended_op_srt, - dimm_params[i].extended_op_srt); + (unsigned int)dimm_params[i].extended_op_srt); } outpdimm->ndimms_present = number_of_dimms - temp1; diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index b43b669..6f291eb 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -106,7 +106,8 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1); ret = i2c_read(i2c_address, 0, 1, (uchar *)((ulong)spd + 256), - min(256, sizeof(generic_spd_eeprom_t) - 256)); + min(256, + (int)sizeof(generic_spd_eeprom_t) - 256)); } #else ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 4d5572e..8f4d01a 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -15,8 +15,6 @@ #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL #endif -DECLARE_GLOBAL_DATA_PTR; - /* * regs has the to-be-set values for DDR controller registers * ctrl_num is the DDR controller number @@ -44,16 +42,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 save1, save2; #endif -#ifdef CONFIG_DEEP_SLEEP - const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - bool sleep_flag = 0; -#endif - -#ifdef CONFIG_DEEP_SLEEP - if (in_be32(&gur->scrtsr[0]) & (1 << 3)) - sleep_flag = 1; -#endif - switch (ctrl_num) { case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; @@ -130,13 +118,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); -#ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) - out_be32(&ddr->sdram_cfg_2, - regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); - else -#endif - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); @@ -149,17 +130,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); out_be32(&ddr->sdram_data_init, regs->ddr_data_init); out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); -#ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) { - out_be32(&ddr->init_addr, 0); - out_be32(&ddr->init_ext_addr, (1 << 31)); - } else -#endif - { - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - } - out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); @@ -180,7 +150,24 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); - out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + out_be32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); + out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); + + /* DRAM VRef will not be trained */ + out_be32(&ddr->ddr_cdr2, + regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); + } else +#endif + { + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + out_be32(&ddr->init_addr, regs->ddr_init_addr); + out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); + } out_be32(&ddr->err_disable, regs->err_disable); out_be32(&ddr->err_int_en, regs->err_int_en); for (i = 0; i < 32; i++) { @@ -400,21 +387,17 @@ step2: asm volatile("sync;isync"); #ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) { + if (is_warm_boot()) { /* enter self-refresh */ - setbits_be32(&ddr->sdram_cfg_2, (1 << 31)); + setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); /* do board specific memory setup */ board_mem_sleep_setup(); - } -#endif - - /* Let the controller go */ -#ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI); - else + } else #endif temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI); + + /* Let the controller go */ out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); asm volatile("sync;isync"); @@ -566,8 +549,8 @@ step2: } #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ #ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) + if (is_warm_boot()) /* exit self-refresh */ - clrbits_be32(&ddr->sdram_cfg_2, (1 << 31)); + clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); #endif } diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index deafda2..14cb366 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -289,7 +289,7 @@ static int dfu_read_buffer_fill(struct dfu_entity *dfu, void *buf, int size) readn = 0; while (size > 0) { /* get chunk that can be read */ - chunk = min(size, dfu->b_left); + chunk = min((long)size, dfu->b_left); /* consume */ if (chunk > 0) { memcpy(buf, dfu->i_buf, chunk); diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 68fe0f3..6a74f89 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -406,8 +406,8 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, unsigned long ts; /* Timestamp */ u32 isr_status, swap; u32 partialbit = 0; - u32 blocksize; - u32 pos = 0; + loff_t blocksize, actread; + loff_t pos = 0; int fstype; char *interface, *dev_part, *filename; @@ -420,7 +420,7 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, if (fs_set_blk_dev(interface, dev_part, fstype)) return FPGA_FAIL; - if (fs_read(filename, (u32) buf, pos, blocksize) < 0) + if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0) return FPGA_FAIL; if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap, @@ -443,10 +443,10 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, return FPGA_FAIL; if (bsize > blocksize) { - if (fs_read(filename, (u32) buf, pos, blocksize) < 0) + if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0) return FPGA_FAIL; } else { - if (fs_read(filename, (u32) buf, pos, bsize) < 0) + if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0) return FPGA_FAIL; } } while (bsize > blocksize); diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 6517af1..6129c02 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -10,11 +10,14 @@ #include <config.h> #include <common.h> +#include <dm.h> #include <asm/io.h> #include <linux/sizes.h> +#include <asm/gpio.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pio.h> -#include <asm/arch/gpio.h> + +#define GPIO_PER_BANK 32 static struct at91_port *at91_pio_get_port(unsigned port) { @@ -39,19 +42,25 @@ static struct at91_port *at91_pio_get_port(unsigned port) } } +static void at91_set_port_pullup(struct at91_port *at91_port, unsigned offset, + int use_pullup) +{ + u32 mask; + + mask = 1 << offset; + if (use_pullup) + writel(mask, &at91_port->puer); + else + writel(mask, &at91_port->pudr); + writel(mask, &at91_port->per); +} + int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) { struct at91_port *at91_port = at91_pio_get_port(port); - u32 mask; - if (at91_port && (pin < 32)) { - mask = 1 << pin; - if (use_pullup) - writel(1 << pin, &at91_port->puer); - else - writel(1 << pin, &at91_port->pudr); - writel(mask, &at91_port->per); - } + if (at91_port && (pin < GPIO_PER_BANK)) + at91_set_port_pullup(at91_port, pin, use_pullup); return 0; } @@ -64,7 +73,7 @@ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; - if (at91_port && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; writel(mask, &at91_port->idr); at91_set_pio_pullup(port, pin, use_pullup); @@ -82,7 +91,7 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; - if (at91_port && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; writel(mask, &at91_port->idr); at91_set_pio_pullup(port, pin, use_pullup); @@ -108,7 +117,7 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; - if (at91_port && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; writel(mask, &at91_port->idr); at91_set_pio_pullup(port, pin, use_pullup); @@ -135,7 +144,7 @@ int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup) struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; - if (at91_port && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; writel(mask, &at91_port->idr); at91_set_pio_pullup(port, pin, use_pullup); @@ -157,7 +166,7 @@ int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup) struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; - if (at91_port && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; writel(mask, &at91_port->idr); at91_set_pio_pullup(port, pin, use_pullup); @@ -172,6 +181,29 @@ int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup) } #endif +#ifdef CONFIG_DM_GPIO +static bool at91_get_port_output(struct at91_port *at91_port, int offset) +{ + u32 mask, val; + + mask = 1 << offset; + val = readl(&at91_port->osr); + return val & mask; +} +#endif + +static void at91_set_port_input(struct at91_port *at91_port, int offset, + int use_pullup) +{ + u32 mask; + + mask = 1 << offset; + writel(mask, &at91_port->idr); + at91_set_port_pullup(at91_port, offset, use_pullup); + writel(mask, &at91_port->odr); + writel(mask, &at91_port->per); +} + /* * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and * configure it for an input. @@ -179,19 +211,29 @@ int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup) int at91_set_pio_input(unsigned port, u32 pin, int use_pullup) { struct at91_port *at91_port = at91_pio_get_port(port); - u32 mask; - if (at91_port && (pin < 32)) { - mask = 1 << pin; - writel(mask, &at91_port->idr); - at91_set_pio_pullup(port, pin, use_pullup); - writel(mask, &at91_port->odr); - writel(mask, &at91_port->per); - } + if (at91_port && (pin < GPIO_PER_BANK)) + at91_set_port_input(at91_port, pin, use_pullup); return 0; } +static void at91_set_port_output(struct at91_port *at91_port, int offset, + int value) +{ + u32 mask; + + mask = 1 << offset; + writel(mask, &at91_port->idr); + writel(mask, &at91_port->pudr); + if (value) + writel(mask, &at91_port->sodr); + else + writel(mask, &at91_port->codr); + writel(mask, &at91_port->oer); + writel(mask, &at91_port->per); +} + /* * mux the pin to the gpio controller (instead of "A" or "B" peripheral), * and configure it for an output. @@ -199,19 +241,9 @@ int at91_set_pio_input(unsigned port, u32 pin, int use_pullup) int at91_set_pio_output(unsigned port, u32 pin, int value) { struct at91_port *at91_port = at91_pio_get_port(port); - u32 mask; - if (at91_port && (port < ATMEL_PIO_PORTS) && (pin < 32)) { - mask = 1 << pin; - writel(mask, &at91_port->idr); - writel(mask, &at91_port->pudr); - if (value) - writel(mask, &at91_port->sodr); - else - writel(mask, &at91_port->codr); - writel(mask, &at91_port->oer); - writel(mask, &at91_port->per); - } + if (at91_port && (pin < GPIO_PER_BANK)) + at91_set_port_output(at91_port, pin, value); return 0; } @@ -224,7 +256,7 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; - if (at91_port && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; if (is_on) { #if defined(CPU_HAS_PIO3) @@ -248,7 +280,7 @@ int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; - if (at91_port && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; if (is_on) { writel(mask, &at91_port->ifscer); @@ -271,7 +303,7 @@ int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on) struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; - if (at91_port && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; writel(mask, &at91_port->pudr); if (is_on) @@ -291,7 +323,7 @@ int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin) struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; - if (at91_port && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; writel(readl(&at91_port->schmitt) | mask, &at91_port->schmitt); @@ -310,7 +342,7 @@ int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on) struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; - if (at91_port && (pin < 32)) { + if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; if (is_on) writel(mask, &at91_port->mder); @@ -321,41 +353,54 @@ int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on) return 0; } +static void at91_set_port_value(struct at91_port *at91_port, int offset, + int value) +{ + u32 mask; + + mask = 1 << offset; + if (value) + writel(mask, &at91_port->sodr); + else + writel(mask, &at91_port->codr); +} + /* * assuming the pin is muxed as a gpio output, set its value. */ int at91_set_pio_value(unsigned port, unsigned pin, int value) { struct at91_port *at91_port = at91_pio_get_port(port); - u32 mask; - if (at91_port && (pin < 32)) { - mask = 1 << pin; - if (value) - writel(mask, &at91_port->sodr); - else - writel(mask, &at91_port->codr); - } + if (at91_port && (pin < GPIO_PER_BANK)) + at91_set_port_value(at91_port, pin, value); return 0; } +static int at91_get_port_value(struct at91_port *at91_port, int offset) +{ + u32 pdsr = 0, mask; + + mask = 1 << offset; + pdsr = readl(&at91_port->pdsr) & mask; + + return pdsr != 0; +} /* * read the pin's value (works even if it's not muxed as a gpio). */ int at91_get_pio_value(unsigned port, unsigned pin) { struct at91_port *at91_port = at91_pio_get_port(port); - u32 pdsr = 0, mask; - if (at91_port && (pin < 32)) { - mask = 1 << pin; - pdsr = readl(&at91_port->pdsr) & mask; - } + if (at91_port && (pin < GPIO_PER_BANK)) + return at91_get_port_value(at91_port, pin); - return pdsr != 0; + return 0; } +#ifndef CONFIG_DM_GPIO /* Common GPIO API */ int gpio_request(unsigned gpio, const char *label) @@ -395,3 +440,91 @@ int gpio_set_value(unsigned gpio, int value) return 0; } +#endif + +#ifdef CONFIG_DM_GPIO + +struct at91_port_priv { + struct at91_port *regs; +}; + +/* set GPIO pin 'gpio' as an input */ +static int at91_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + struct at91_port_priv *port = dev_get_platdata(dev); + + at91_set_port_input(port->regs, offset, 0); + + return 0; +} + +/* set GPIO pin 'gpio' as an output, with polarity 'value' */ +static int at91_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + struct at91_port_priv *port = dev_get_platdata(dev); + + at91_set_port_output(port->regs, offset, value); + + return 0; +} + +/* read GPIO IN value of pin 'gpio' */ +static int at91_gpio_get_value(struct udevice *dev, unsigned offset) +{ + struct at91_port_priv *port = dev_get_platdata(dev); + + return at91_get_port_value(port->regs, offset); +} + +/* write GPIO OUT value to pin 'gpio' */ +static int at91_gpio_set_value(struct udevice *dev, unsigned offset, + int value) +{ + struct at91_port_priv *port = dev_get_platdata(dev); + + at91_set_port_value(port->regs, offset, value); + + return 0; +} + +static int at91_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct at91_port_priv *port = dev_get_platdata(dev); + + /* GPIOF_FUNC is not implemented yet */ + if (at91_get_port_output(port->regs, offset)) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + +static const struct dm_gpio_ops gpio_at91_ops = { + .direction_input = at91_gpio_direction_input, + .direction_output = at91_gpio_direction_output, + .get_value = at91_gpio_get_value, + .set_value = at91_gpio_set_value, + .get_function = at91_gpio_get_function, +}; + +static int at91_gpio_probe(struct udevice *dev) +{ + struct at91_port_priv *port = dev_get_priv(dev); + struct at91_port_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + + uc_priv->bank_name = plat->bank_name; + uc_priv->gpio_count = GPIO_PER_BANK; + port->regs = (struct at91_port *)plat->base_addr; + + return 0; +} + +U_BOOT_DRIVER(gpio_at91) = { + .name = "gpio_at91", + .id = UCLASS_GPIO, + .ops = &gpio_at91_ops, + .probe = at91_gpio_probe, + .priv_auto_alloc_size = sizeof(struct at91_port_priv), +}; +#endif diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 45e9a5a..255700a 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -390,6 +390,25 @@ int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize) return 0; } +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned gpio_get_values_as_int(const int *gpio_num_array) +{ + int gpio; + unsigned bitmask = 1; + unsigned vector = 0; + + while (bitmask && + ((gpio = *gpio_num_array++) != -1)) { + if (gpio_get_value(gpio)) + vector |= bitmask; + bitmask <<= 1; + } + return vector; +} + /* We need to renumber the GPIOs when any driver is probed/removed */ static int gpio_renumber(struct udevice *removed_dev) { diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index d3381b0..b095d17 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -33,6 +33,11 @@ #include <pci.h> #include <asm/gpio.h> #include <asm/io.h> +#include <asm/pci.h> +#ifdef CONFIG_X86_RESET_VECTOR +#include <asm/arch/pch.h> +#define SUPPORT_GPIO_SETUP +#endif #define GPIO_PER_BANK 32 @@ -46,6 +51,53 @@ struct ich6_bank_priv { uint32_t lvl; }; +#ifdef SUPPORT_GPIO_SETUP +static void setup_pch_gpios(const struct pch_gpio_map *gpio) +{ + u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + + /* GPIO Set 1 */ + if (gpio->set1.level) + outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); + if (gpio->set1.mode) + outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); + if (gpio->set1.direction) + outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); + if (gpio->set1.reset) + outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); + if (gpio->set1.invert) + outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV); + if (gpio->set1.blink) + outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK); + + /* GPIO Set 2 */ + if (gpio->set2.level) + outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); + if (gpio->set2.mode) + outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); + if (gpio->set2.direction) + outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); + if (gpio->set2.reset) + outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); + + /* GPIO Set 3 */ + if (gpio->set3.level) + outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); + if (gpio->set3.mode) + outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); + if (gpio->set3.direction) + outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); + if (gpio->set3.reset) + outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); +} + +/* TODO: Move this to device tree, or platform data */ +void ich_gpio_set_gpio_map(const struct pch_gpio_map *map) +{ + gd->arch.gpio_map = map; +} +#endif /* SUPPORT_GPIO_SETUP */ + static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) { struct ich6_bank_platdata *plat = dev_get_platdata(dev); @@ -60,13 +112,13 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) pci_dev = PCI_BDF(0, 0x1f, 0); /* Is the device present? */ - pci_read_config_word(pci_dev, PCI_VENDOR_ID, &tmpword); + tmpword = pci_read_config16(pci_dev, PCI_VENDOR_ID); if (tmpword != PCI_VENDOR_ID_INTEL) { debug("%s: wrong VendorID\n", __func__); return -ENODEV; } - pci_read_config_word(pci_dev, PCI_DEVICE_ID, &tmpword); + tmpword = pci_read_config16(pci_dev, PCI_DEVICE_ID); debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword); /* * We'd like to validate the Device ID too, but pretty much any @@ -76,34 +128,34 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) */ /* I/O should already be enabled (it's a RO bit). */ - pci_read_config_word(pci_dev, PCI_COMMAND, &tmpword); + tmpword = pci_read_config16(pci_dev, PCI_COMMAND); if (!(tmpword & PCI_COMMAND_IO)) { debug("%s: device IO not enabled\n", __func__); return -ENODEV; } /* Header Type must be normal (bits 6-0 only; see spec.) */ - pci_read_config_byte(pci_dev, PCI_HEADER_TYPE, &tmpbyte); + tmpbyte = pci_read_config8(pci_dev, PCI_HEADER_TYPE); if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) { debug("%s: invalid Header type\n", __func__); return -ENODEV; } /* Base Class must be a bridge device */ - pci_read_config_byte(pci_dev, PCI_CLASS_CODE, &tmpbyte); + tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_CODE); if (tmpbyte != PCI_CLASS_CODE_BRIDGE) { debug("%s: invalid class\n", __func__); return -ENODEV; } /* Sub Class must be ISA */ - pci_read_config_byte(pci_dev, PCI_CLASS_SUB_CODE, &tmpbyte); + tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE); if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) { debug("%s: invalid subclass\n", __func__); return -ENODEV; } /* Programming Interface must be 0x00 (no others exist) */ - pci_read_config_byte(pci_dev, PCI_CLASS_PROG, &tmpbyte); + tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_PROG); if (tmpbyte != 0x00) { debug("%s: invalid interface type\n", __func__); return -ENODEV; @@ -114,7 +166,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) * that it was unused (or undocumented). Check that it looks * okay: not all ones or zeros, and mapped to I/O space (bit 0). */ - pci_read_config_dword(pci_dev, PCI_CFG_GPIOBASE, &tmplong); + tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE); if (tmplong == 0x00000000 || tmplong == 0xffffffff || !(tmplong & 0x00000001)) { debug("%s: unexpected GPIOBASE value\n", __func__); @@ -140,12 +192,18 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) return 0; } -int ich6_gpio_probe(struct udevice *dev) +static int ich6_gpio_probe(struct udevice *dev) { struct ich6_bank_platdata *plat = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev->uclass_priv; struct ich6_bank_priv *bank = dev_get_priv(dev); +#ifdef SUPPORT_GPIO_SETUP + if (gd->arch.gpio_map) { + setup_pch_gpios(gd->arch.gpio_map); + gd->arch.gpio_map = NULL; + } +#endif uc_priv->gpio_count = GPIO_PER_BANK; uc_priv->bank_name = plat->bank_name; bank->use_sel = plat->base_addr; @@ -155,7 +213,8 @@ int ich6_gpio_probe(struct udevice *dev) return 0; } -int ich6_gpio_request(struct udevice *dev, unsigned offset, const char *label) +static int ich6_gpio_request(struct udevice *dev, unsigned offset, + const char *label) { struct ich6_bank_priv *bank = dev_get_priv(dev); u32 tmplong; diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index d067897..dae3d71 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o +obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o obj-$(CONFIG_I2C_MV) += mv_i2c.o obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c new file mode 100644 index 0000000..20495b1 --- /dev/null +++ b/drivers/i2c/adi_i2c.c @@ -0,0 +1,305 @@ +/* + * i2c.c - driver for ADI TWI/I2C + * + * Copyright (c) 2006-2014 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/clock.h> +#include <asm/twi.h> +#include <asm/io.h> + +static struct twi_regs *i2c_get_base(struct i2c_adapter *adap); + +/* Every register is 32bit aligned, but only 16bits in size */ +#define ureg(name) u16 name; u16 __pad_##name; +struct twi_regs { + ureg(clkdiv); + ureg(control); + ureg(slave_ctl); + ureg(slave_stat); + ureg(slave_addr); + ureg(master_ctl); + ureg(master_stat); + ureg(master_addr); + ureg(int_stat); + ureg(int_mask); + ureg(fifo_ctl); + ureg(fifo_stat); + char __pad[0x50]; + ureg(xmt_data8); + ureg(xmt_data16); + ureg(rcv_data8); + ureg(rcv_data16); +}; +#undef ureg + +#ifdef TWI_CLKDIV +#define TWI0_CLKDIV TWI_CLKDIV +# ifdef CONFIG_SYS_MAX_I2C_BUS +# undef CONFIG_SYS_MAX_I2C_BUS +# endif +#define CONFIG_SYS_MAX_I2C_BUS 1 +#endif + +/* + * The way speed is changed into duty often results in integer truncation + * with 50% duty, so we'll force rounding up to the next duty by adding 1 + * to the max. In practice this will get us a speed of something like + * 385 KHz. The other limit is easy to handle as it is only 8 bits. + */ +#define I2C_SPEED_MAX 400000 +#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed)) +#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1) +#define I2C_DUTY_MIN 0xff /* 8 bit limited */ +#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED) +/* Note: duty is inverse of speed, so the comparisons below are correct */ +#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN +# error "The I2C hardware can only operate 20KHz - 400KHz" +#endif + +/* All transfers are described by this data structure */ +struct i2c_msg { + u8 flags; +#define I2C_M_COMBO 0x4 +#define I2C_M_STOP 0x2 +#define I2C_M_READ 0x1 + int len; /* msg length */ + u8 *buf; /* pointer to msg data */ + int alen; /* addr length */ + u8 *abuf; /* addr buffer */ +}; + +/* Allow msec timeout per ~byte transfer */ +#define I2C_TIMEOUT 10 + +/** + * wait_for_completion - manage the actual i2c transfer + * @msg: the i2c msg + */ +static int wait_for_completion(struct twi_regs *twi, struct i2c_msg *msg) +{ + u16 int_stat, ctl; + ulong timebase = get_timer(0); + + do { + int_stat = readw(&twi->int_stat); + + if (int_stat & XMTSERV) { + writew(XMTSERV, &twi->int_stat); + if (msg->alen) { + writew(*(msg->abuf++), &twi->xmt_data8); + --msg->alen; + } else if (!(msg->flags & I2C_M_COMBO) && msg->len) { + writew(*(msg->buf++), &twi->xmt_data8); + --msg->len; + } else { + ctl = readw(&twi->master_ctl); + if (msg->flags & I2C_M_COMBO) + writew(ctl | RSTART | MDIR, + &twi->master_ctl); + else + writew(ctl | STOP, &twi->master_ctl); + } + } + if (int_stat & RCVSERV) { + writew(RCVSERV, &twi->int_stat); + if (msg->len) { + *(msg->buf++) = readw(&twi->rcv_data8); + --msg->len; + } else if (msg->flags & I2C_M_STOP) { + ctl = readw(&twi->master_ctl); + writew(ctl | STOP, &twi->master_ctl); + } + } + if (int_stat & MERR) { + writew(MERR, &twi->int_stat); + return msg->len; + } + if (int_stat & MCOMP) { + writew(MCOMP, &twi->int_stat); + if (msg->flags & I2C_M_COMBO && msg->len) { + ctl = readw(&twi->master_ctl); + ctl = (ctl & ~RSTART) | + (min(msg->len, 0xff) << 6) | MEN | MDIR; + writew(ctl, &twi->master_ctl); + } else + break; + } + + /* If we were able to do something, reset timeout */ + if (int_stat) + timebase = get_timer(0); + + } while (get_timer(timebase) < I2C_TIMEOUT); + + return msg->len; +} + +static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr, + int alen, uint8_t *buffer, int len, uint8_t flags) +{ + struct twi_regs *twi = i2c_get_base(adap); + int ret; + u16 ctl; + uchar addr_buffer[] = { + (addr >> 0), + (addr >> 8), + (addr >> 16), + }; + struct i2c_msg msg = { + .flags = flags | (len >= 0xff ? I2C_M_STOP : 0), + .buf = buffer, + .len = len, + .abuf = addr_buffer, + .alen = alen, + }; + + /* wait for things to settle */ + while (readw(&twi->master_stat) & BUSBUSY) + if (ctrlc()) + return 1; + + /* Set Transmit device address */ + writew(chip, &twi->master_addr); + + /* Clear the FIFO before starting things */ + writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl); + writew(0, &twi->fifo_ctl); + + /* prime the pump */ + if (msg.alen) { + len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; + writew(*(msg.abuf++), &twi->xmt_data8); + --msg.alen; + } else if (!(msg.flags & I2C_M_READ) && msg.len) { + writew(*(msg.buf++), &twi->xmt_data8); + --msg.len; + } + + /* clear int stat */ + writew(-1, &twi->master_stat); + writew(-1, &twi->int_stat); + writew(0, &twi->int_mask); + + /* Master enable */ + ctl = readw(&twi->master_ctl); + ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN | + ((msg.flags & I2C_M_READ) ? MDIR : 0); + writew(ctl, &twi->master_ctl); + + /* process the rest */ + ret = wait_for_completion(twi, &msg); + + if (ret) { + ctl = readw(&twi->master_ctl) & ~MEN; + writew(ctl, &twi->master_ctl); + ctl = readw(&twi->control) & ~TWI_ENA; + writew(ctl, &twi->control); + ctl = readw(&twi->control) | TWI_ENA; + writew(ctl, &twi->control); + } + + return ret; +} + +static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed) +{ + struct twi_regs *twi = i2c_get_base(adap); + u16 clkdiv = I2C_SPEED_TO_DUTY(speed); + + /* Set TWI interface clock */ + if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) + return -1; + clkdiv = (clkdiv << 8) | (clkdiv & 0xff); + writew(clkdiv, &twi->clkdiv); + + /* Don't turn it on */ + writew(speed > 100000 ? FAST : 0, &twi->master_ctl); + + return 0; +} + +static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) +{ + struct twi_regs *twi = i2c_get_base(adap); + u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F; + + /* Set TWI internal clock as 10MHz */ + writew(prescale, &twi->control); + + /* Set TWI interface clock as specified */ + i2c_set_bus_speed(speed); + + /* Enable it */ + writew(TWI_ENA | prescale, &twi->control); +} + +static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip, + uint addr, int alen, uint8_t *buffer, int len) +{ + return i2c_transfer(adap, chip, addr, alen, buffer, + len, alen ? I2C_M_COMBO : I2C_M_READ); +} + +static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip, + uint addr, int alen, uint8_t *buffer, int len) +{ + return i2c_transfer(adap, chip, addr, alen, buffer, len, 0); +} + +static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip) +{ + u8 byte; + return adi_i2c_read(adap, chip, 0, 0, &byte, 1); +} + +static struct twi_regs *i2c_get_base(struct i2c_adapter *adap) +{ + switch (adap->hwadapnr) { +#if CONFIG_SYS_MAX_I2C_BUS > 2 + case 2: + return (struct twi_regs *)TWI2_CLKDIV; +#endif +#if CONFIG_SYS_MAX_I2C_BUS > 1 + case 1: + return (struct twi_regs *)TWI1_CLKDIV; +#endif + case 0: + return (struct twi_regs *)TWI0_CLKDIV; + + default: + printf("wrong hwadapnr: %d\n", adap->hwadapnr); + } + + return NULL; +} + +U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe, + adi_i2c_read, adi_i2c_write, + adi_i2c_setspeed, + CONFIG_SYS_I2C_SPEED, + 0, + 0) + +#if CONFIG_SYS_MAX_I2C_BUS > 1 +U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe, + adi_i2c_read, adi_i2c_write, + adi_i2c_setspeed, + CONFIG_SYS_I2C_SPEED, + 0, + 1) +#endif + +#if CONFIG_SYS_MAX_I2C_BUS > 2 +U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe, + adi_i2c_read, adi_i2c_write, + adi_i2c_setspeed, + CONFIG_SYS_I2C_SPEED, + 0, + 2) +#endif diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c deleted file mode 100644 index cfab064..0000000 --- a/drivers/i2c/bfin-twi_i2c.c +++ /dev/null @@ -1,379 +0,0 @@ -/* - * i2c.c - driver for Blackfin on-chip TWI/I2C - * - * Copyright (c) 2006-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <i2c.h> - -#include <asm/blackfin.h> -#include <asm/clock.h> -#include <asm/mach-common/bits/twi.h> - -/* Every register is 32bit aligned, but only 16bits in size */ -#define ureg(name) u16 name; u16 __pad_##name; -struct twi_regs { - ureg(clkdiv); - ureg(control); - ureg(slave_ctl); - ureg(slave_stat); - ureg(slave_addr); - ureg(master_ctl); - ureg(master_stat); - ureg(master_addr); - ureg(int_stat); - ureg(int_mask); - ureg(fifo_ctl); - ureg(fifo_stat); - char __pad[0x50]; - ureg(xmt_data8); - ureg(xmt_data16); - ureg(rcv_data8); - ureg(rcv_data16); -}; -#undef ureg - -/* U-Boot I2C framework allows only one active device at a time. */ -#ifdef TWI_CLKDIV -#define TWI0_CLKDIV TWI_CLKDIV -#endif -static volatile struct twi_regs *twi = (void *)TWI0_CLKDIV; - -#ifdef DEBUG -# define dmemset(s, c, n) memset(s, c, n) -#else -# define dmemset(s, c, n) -#endif -#define debugi(fmt, args...) \ - debug( \ - "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \ - twi->master_stat, twi->fifo_stat, twi->int_stat, \ - __func__, __LINE__, ## args) - -#ifdef CONFIG_TWICLK_KHZ -# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED -#endif - -/* - * The way speed is changed into duty often results in integer truncation - * with 50% duty, so we'll force rounding up to the next duty by adding 1 - * to the max. In practice this will get us a speed of something like - * 385 KHz. The other limit is easy to handle as it is only 8 bits. - */ -#define I2C_SPEED_MAX 400000 -#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed)) -#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1) -#define I2C_DUTY_MIN 0xff /* 8 bit limited */ -#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED) -/* Note: duty is inverse of speed, so the comparisons below are correct */ -#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN -# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz" -#endif - -/* All transfers are described by this data structure */ -struct i2c_msg { - u8 flags; -#define I2C_M_COMBO 0x4 -#define I2C_M_STOP 0x2 -#define I2C_M_READ 0x1 - int len; /* msg length */ - u8 *buf; /* pointer to msg data */ - int alen; /* addr length */ - u8 *abuf; /* addr buffer */ -}; - -/* Allow msec timeout per ~byte transfer */ -#define I2C_TIMEOUT 10 - -/** - * wait_for_completion - manage the actual i2c transfer - * @msg: the i2c msg - */ -static int wait_for_completion(struct i2c_msg *msg) -{ - uint16_t int_stat; - ulong timebase = get_timer(0); - - do { - int_stat = twi->int_stat; - - if (int_stat & XMTSERV) { - debugi("processing XMTSERV"); - twi->int_stat = XMTSERV; - SSYNC(); - if (msg->alen) { - twi->xmt_data8 = *(msg->abuf++); - --msg->alen; - } else if (!(msg->flags & I2C_M_COMBO) && msg->len) { - twi->xmt_data8 = *(msg->buf++); - --msg->len; - } else { - twi->master_ctl |= (msg->flags & I2C_M_COMBO) ? RSTART | MDIR : STOP; - SSYNC(); - } - } - if (int_stat & RCVSERV) { - debugi("processing RCVSERV"); - twi->int_stat = RCVSERV; - SSYNC(); - if (msg->len) { - *(msg->buf++) = twi->rcv_data8; - --msg->len; - } else if (msg->flags & I2C_M_STOP) { - twi->master_ctl |= STOP; - SSYNC(); - } - } - if (int_stat & MERR) { - debugi("processing MERR"); - twi->int_stat = MERR; - SSYNC(); - return msg->len; - } - if (int_stat & MCOMP) { - debugi("processing MCOMP"); - twi->int_stat = MCOMP; - SSYNC(); - if (msg->flags & I2C_M_COMBO && msg->len) { - twi->master_ctl = (twi->master_ctl & ~RSTART) | - (min(msg->len, 0xff) << 6) | MEN | MDIR; - SSYNC(); - } else - break; - } - - /* If we were able to do something, reset timeout */ - if (int_stat) - timebase = get_timer(0); - - } while (get_timer(timebase) < I2C_TIMEOUT); - - return msg->len; -} - -/** - * i2c_transfer - setup an i2c transfer - * @return: 0 if things worked, non-0 if things failed - * - * Here we just get the i2c stuff all prepped and ready, and then tail off - * into wait_for_completion() for all the bits to go. - */ -static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags) -{ - uchar addr_buffer[] = { - (addr >> 0), - (addr >> 8), - (addr >> 16), - }; - struct i2c_msg msg = { - .flags = flags | (len >= 0xff ? I2C_M_STOP : 0), - .buf = buffer, - .len = len, - .abuf = addr_buffer, - .alen = alen, - }; - int ret; - - dmemset(buffer, 0xff, len); - debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ", - chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr")); - - /* wait for things to settle */ - while (twi->master_stat & BUSBUSY) - if (ctrlc()) - return 1; - - /* Set Transmit device address */ - twi->master_addr = chip; - - /* Clear the FIFO before starting things */ - twi->fifo_ctl = XMTFLUSH | RCVFLUSH; - SSYNC(); - twi->fifo_ctl = 0; - SSYNC(); - - /* prime the pump */ - if (msg.alen) { - len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; - debugi("first byte=0x%02x", *msg.abuf); - twi->xmt_data8 = *(msg.abuf++); - --msg.alen; - } else if (!(msg.flags & I2C_M_READ) && msg.len) { - debugi("first byte=0x%02x", *msg.buf); - twi->xmt_data8 = *(msg.buf++); - --msg.len; - } - - /* clear int stat */ - twi->master_stat = -1; - twi->int_stat = -1; - twi->int_mask = 0; - SSYNC(); - - /* Master enable */ - twi->master_ctl = - (twi->master_ctl & FAST) | - (min(len, 0xff) << 6) | MEN | - ((msg.flags & I2C_M_READ) ? MDIR : 0); - SSYNC(); - debugi("CTL=0x%04x", twi->master_ctl); - - /* process the rest */ - ret = wait_for_completion(&msg); - debugi("ret=%d", ret); - - if (ret) { - twi->master_ctl &= ~MEN; - twi->control &= ~TWI_ENA; - SSYNC(); - twi->control |= TWI_ENA; - SSYNC(); - } - - return ret; -} - -/** - * i2c_set_bus_speed - set i2c bus speed - * @speed: bus speed (in HZ) - */ -int i2c_set_bus_speed(unsigned int speed) -{ - u16 clkdiv = I2C_SPEED_TO_DUTY(speed); - - /* Set TWI interface clock */ - if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) - return -1; - twi->clkdiv = (clkdiv << 8) | (clkdiv & 0xff); - - /* Don't turn it on */ - twi->master_ctl = (speed > 100000 ? FAST : 0); - - return 0; -} - -/** - * i2c_get_bus_speed - get i2c bus speed - * @speed: bus speed (in HZ) - */ -unsigned int i2c_get_bus_speed(void) -{ - /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */ - return 5000000 / (twi->clkdiv & 0xff); -} - -/** - * i2c_init - initialize the i2c bus - * @speed: bus speed (in HZ) - * @slaveaddr: address of device in slave mode (0 - not slave) - * - * Slave mode isn't actually implemented. It'll stay that way until - * we get a real request for it. - */ -void i2c_init(int speed, int slaveaddr) -{ - uint8_t prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F; - - /* Set TWI internal clock as 10MHz */ - twi->control = prescale; - - /* Set TWI interface clock as specified */ - i2c_set_bus_speed(speed); - - /* Enable it */ - twi->control = TWI_ENA | prescale; - SSYNC(); - - debugi("CONTROL:0x%04x CLKDIV:0x%04x", twi->control, twi->clkdiv); - -#if CONFIG_SYS_I2C_SLAVE -# error I2C slave support not tested/supported - /* If they want us as a slave, do it */ - if (slaveaddr) { - twi->slave_addr = slaveaddr; - twi->slave_ctl = SEN; - } -#endif -} - -/** - * i2c_probe - test if a chip exists at a given i2c address - * @chip: i2c chip addr to search for - * @return: 0 if found, non-0 if not found - */ -int i2c_probe(uchar chip) -{ - u8 byte; - return i2c_read(chip, 0, 0, &byte, 1); -} - -/** - * i2c_read - read data from an i2c device - * @chip: i2c chip addr - * @addr: memory (register) address in the chip - * @alen: byte size of address - * @buffer: buffer to store data read from chip - * @len: how many bytes to read - * @return: 0 on success, non-0 on failure - */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - return i2c_transfer(chip, addr, alen, buffer, len, (alen ? I2C_M_COMBO : I2C_M_READ)); -} - -/** - * i2c_write - write data to an i2c device - * @chip: i2c chip addr - * @addr: memory (register) address in the chip - * @alen: byte size of address - * @buffer: buffer holding data to write to chip - * @len: how many bytes to write - * @return: 0 on success, non-0 on failure - */ -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - return i2c_transfer(chip, addr, alen, buffer, len, 0); -} - -/** - * i2c_set_bus_num - change active I2C bus - * @bus: bus index, zero based - * @returns: 0 on success, non-0 on failure - */ -int i2c_set_bus_num(unsigned int bus) -{ - switch (bus) { -#if CONFIG_SYS_MAX_I2C_BUS > 0 - case 0: twi = (void *)TWI0_CLKDIV; return 0; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 1 - case 1: twi = (void *)TWI1_CLKDIV; return 0; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 2 - case 2: twi = (void *)TWI2_CLKDIV; return 0; -#endif - default: return -1; - } -} - -/** - * i2c_get_bus_num - returns index of active I2C bus - */ -unsigned int i2c_get_bus_num(void) -{ - switch ((unsigned long)twi) { -#if CONFIG_SYS_MAX_I2C_BUS > 0 - case TWI0_CLKDIV: return 0; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 1 - case TWI1_CLKDIV: return 1; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 2 - case TWI2_CLKDIV: return 2; -#endif - default: return -1; - } -} diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 7bb1702..ff7f25a 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -127,7 +127,7 @@ static const struct { static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, unsigned int i2c_clk, unsigned int speed) { - unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); + unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX); /* * We want to choose an FDR/DFSR that generates an I2C bus speed that diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index d34b749..41cc3b8 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -174,11 +174,11 @@ static int i2c_mux_set_all(void) return 0; } -static int i2c_mux_disconnet_all(void) +static int i2c_mux_disconnect_all(void) { struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS]; int i; - uint8_t buf; + uint8_t buf = 0; if (I2C_ADAP->init_done == 0) return 0; @@ -197,7 +197,7 @@ static int i2c_mux_disconnet_all(void) ret = I2C_ADAP->write(I2C_ADAP, chip, 0, 0, &buf, 1); if (ret != 0) { - printf("i2c: mux diconnect error\n"); + printf("i2c: mux disconnect error\n"); return ret; } } while (i > 0); @@ -293,7 +293,7 @@ int i2c_set_bus_num(unsigned int bus) } #ifndef CONFIG_SYS_I2C_DIRECT_BUS - i2c_mux_disconnet_all(); + i2c_mux_disconnect_all(); #endif gd->cur_i2c_bus = bus; diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index 521edfd..9b4effb 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -701,6 +701,7 @@ static int cros_ec_check_version(struct cros_ec_dev *dev) /* Try sending a version 3 packet */ dev->protocol_version = 3; + req.in_data = 0; if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req, sizeof(req), (uint8_t **)&resp, sizeof(*resp)) > 0) { return 0; diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c index e403664..e6dba29 100644 --- a/drivers/misc/cros_ec_spi.c +++ b/drivers/misc/cros_ec_spi.c @@ -143,7 +143,7 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, return -1; } - len = min(p[1], din_len); + len = min((int)p[1], din_len); cros_ec_dump_data("in", -1, p, len + 3); /* Response code is first byte of message */ diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 3de1245..d92044e 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -81,8 +81,6 @@ static int finish_access(struct ocotp_regs *regs, const char *caller) err = !!(readl(®s->ctrl) & BM_CTRL_ERROR); clear_error(regs); - enable_ocotp_clk(0); - if (err) { printf("mxc_ocotp %s(): Access protect error\n", caller); return -EIO; @@ -122,8 +120,8 @@ static void set_timing(struct ocotp_regs *regs) relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1; strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS, 1000000000) + 2 * (relax + 1) - 1; - strobe_prog = DIV_ROUND(ipg_clk * BV_TIMING_STROBE_PROG_US, 1000000) + - 2 * (relax + 1) - 1; + strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US, + 1000000) + 2 * (relax + 1) - 1; timing = BF(strobe_read, TIMING_STROBE_READ) | BF(relax, TIMING_RELAX) | diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c index 545d3eb..6f0a1d3 100644 --- a/drivers/misc/mxs_ocotp.c +++ b/drivers/misc/mxs_ocotp.c @@ -187,6 +187,8 @@ static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask) uint32_t hclk_val, vddio_val; int ret; + mxs_ocotp_clear_error(); + /* Make sure the banks are closed for reading. */ ret = mxs_ocotp_read_bank_open(0); if (ret) { @@ -221,13 +223,17 @@ static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask) goto fail; } + /* Check for errors */ + if (readl(&ocotp_regs->hw_ocotp_ctrl) & OCOTP_CTRL_ERROR) { + puts("Failed writing fuses!\n"); + ret = -EPERM; + goto fail; + } + fail: mxs_ocotp_scale_vddio(0, &vddio_val); - ret = mxs_ocotp_scale_hclk(0, &hclk_val); - if (ret) { + if (mxs_ocotp_scale_hclk(0, &hclk_val)) puts("Failed scaling up the HCLK!\n"); - return ret; - } return ret; } diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 2640607..c55eb28 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -23,6 +23,13 @@ DECLARE_GLOBAL_DATA_PTR; +#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ + IRQSTATEN_CINT | \ + IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ + IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ + IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ + IRQSTATEN_DINT) + struct fsl_esdhc { uint dsaddr; /* SDMA system address register */ uint blkattr; /* Block attributes register */ @@ -558,6 +565,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); + writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); memset(&cfg->cfg, 0, sizeof(cfg->cfg)); voltage_caps = 0; @@ -610,7 +618,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) #endif cfg->cfg.f_min = 400000; - cfg->cfg.f_max = min(gd->arch.sdhc_clk, 52000000); + cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000); cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 44a4feb..8436bc7 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1277,6 +1277,11 @@ block_dev_desc_t *mmc_get_dev(int dev) } #endif +/* board-specific MMC power initializations. */ +__weak void board_mmc_power_init(void) +{ +} + int mmc_start_init(struct mmc *mmc) { int err; @@ -1293,6 +1298,8 @@ int mmc_start_init(struct mmc *mmc) if (mmc->has_init) return 0; + board_mmc_power_init(); + /* made sure it's not NULL earlier */ err = mmc->cfg->ops->init(mmc); diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index ffb5284..c880ced 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -135,12 +135,7 @@ static unsigned char mmc_board_init(struct mmc *mmc) pbias_lite = readl(&t2_base->pbias_lite); pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); writel(pbias_lite, &t2_base->pbias_lite); -#endif -#if defined(CONFIG_TWL4030_POWER) - twl4030_power_mmc_init(); - mdelay(100); /* ramp-up delay from Linux code */ -#endif -#if defined(CONFIG_OMAP34XX) + writel(pbias_lite | PBIASLITEPWRDNZ1 | PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, &t2_base->pbias_lite); @@ -663,7 +658,8 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, case 1: priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ - defined(CONFIG_DRA7XX)) && defined(CONFIG_HSMMC2_8BIT) + defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && \ + defined(CONFIG_HSMMC2_8BIT) /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ host_caps_val |= MMC_MODE_8BIT; #endif @@ -672,7 +668,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, #ifdef OMAP_HSMMC3_BASE case 2: priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; -#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT) +#if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT) /* Enable 8-bit interface for eMMC on DRA7XX */ host_caps_val |= MMC_MODE_8BIT; #endif diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c index 1f29757..25ab0b1 100644 --- a/drivers/mmc/pxa_mmc_gen.c +++ b/drivers/mmc/pxa_mmc_gen.c @@ -197,7 +197,7 @@ static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data) while (len) { /* The controller has data ready */ if (readl(®s->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) { - size = min(len, PXAMMC_FIFO_SIZE); + size = min(len, (uint32_t)PXAMMC_FIFO_SIZE); len -= size; size /= 4; @@ -233,14 +233,14 @@ static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data) while (len) { /* The controller is ready to receive data */ if (readl(®s->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) { - size = min(len, PXAMMC_FIFO_SIZE); + size = min(len, (uint32_t)PXAMMC_FIFO_SIZE); len -= size; size /= 4; while (size--) writel(*buf++, ®s->txfifo); - if (min(len, PXAMMC_FIFO_SIZE) < 32) + if (min(len, (uint32_t)PXAMMC_FIFO_SIZE) < 32) writel(MMC_PRTBUF_BUF_PART_FULL, ®s->prtbuf); } diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index ed83a14..76ba93b 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -103,20 +103,18 @@ static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host) static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) { - int i; - sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); if (!clk) return; - if (clk == CLKDEV_EMMC_DATA) { + + if (clk == CLKDEV_EMMC_DATA) sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); - } else { - for (i = 1; (unsigned int)host->clk / (1 << i) >= clk; i++) - ; - sh_mmcif_bitset((i - 1) << 16, &host->regs->ce_clk_ctrl); - } + else + sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk, + clk) - 1) - 1) << 16, + &host->regs->ce_clk_ctrl); sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); } @@ -581,8 +579,6 @@ static struct mmc_config sh_mmcif_cfg = { .host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC, .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .f_min = CLKDEV_MMC_INIT, - .f_max = CLKDEV_EMMC_DATA, .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, }; @@ -599,6 +595,9 @@ int mmcif_mmc_init(void) host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR; host->clk = CONFIG_SH_MMCIF_CLK; + sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk); + sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk); + mmc = mmc_create(&sh_mmcif_cfg, host); if (mmc == NULL) { free(host); diff --git a/drivers/mmc/sh_mmcif.h b/drivers/mmc/sh_mmcif.h index bd6fbf7..4b6752f 100644 --- a/drivers/mmc/sh_mmcif.h +++ b/drivers/mmc/sh_mmcif.h @@ -199,7 +199,13 @@ struct sh_mmcif_regs { #define SOFT_RST_OFF (0 << 31) #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ -#define CLKDEV_MMC_INIT 400000 /* 100 - 400 KHz */ +#ifdef CONFIG_RMOBILE +#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 9)) +#define MMC_CLK_DIV_MAX(clk) (clk / (1 << 1)) +#else +#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 8)) +#define MMC_CLK_DIV_MAX(clk) CLKDEV_EMMC_DATA +#endif #define MMC_BUS_WIDTH_1 0 #define MMC_BUS_WIDTH_4 2 diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c index ac805ff..709a486 100644 --- a/drivers/mtd/cfi_mtd.c +++ b/drivers/mtd/cfi_mtd.c @@ -226,6 +226,7 @@ int cfi_mtd_init(void) mtd->flags = MTD_CAP_NORFLASH; mtd->size = fi->size; mtd->writesize = 1; + mtd->writebufsize = mtd->writesize; mtd->_erase = cfi_mtd_erase; mtd->_read = cfi_mtd_read; diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c index 593b9b8..ce9af8f 100644 --- a/drivers/mtd/jedec_flash.c +++ b/drivers/mtd/jedec_flash.c @@ -333,6 +333,57 @@ static const struct amd_flash_info jedec_table[] = { } }, { + .mfr_id = (u16)AMD_MANUFACT, + .dev_id = AM29LV800BT, + .name = "AMD AM29LV800BT", + .uaddr = { + [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ + }, + .DevSize = SIZE_1MiB, + .CmdSet = CFI_CMDSET_AMD_LEGACY, + .NumEraseRegions= 4, + .regions = { + ERASEINFO(0x10000, 15), + ERASEINFO(0x08000, 1), + ERASEINFO(0x02000, 2), + ERASEINFO(0x04000, 1), + } + }, + { + .mfr_id = (u16)MX_MANUFACT, + .dev_id = AM29LV800BT, + .name = "MXIC MX29LV800BT", + .uaddr = { + [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ + }, + .DevSize = SIZE_1MiB, + .CmdSet = CFI_CMDSET_AMD_LEGACY, + .NumEraseRegions= 4, + .regions = { + ERASEINFO(0x10000, 15), + ERASEINFO(0x08000, 1), + ERASEINFO(0x02000, 2), + ERASEINFO(0x04000, 1), + } + }, + { + .mfr_id = (u16)EON_ALT_MANU, + .dev_id = AM29LV800BT, + .name = "EON EN29LV800BT", + .uaddr = { + [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ + }, + .DevSize = SIZE_1MiB, + .CmdSet = CFI_CMDSET_AMD_LEGACY, + .NumEraseRegions= 4, + .regions = { + ERASEINFO(0x10000, 15), + ERASEINFO(0x08000, 1), + ERASEINFO(0x02000, 2), + ERASEINFO(0x04000, 1), + } + }, + { .mfr_id = (u16)STM_MANUFACT, .dev_id = STM29F400BB, .name = "ST Micro M29F400BB", diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 75c2c06..c242214 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -1,9 +1,16 @@ menu "NAND Device Support" +config SYS_NAND_SELF_INIT + bool + help + This option, if enabled, provides more flexible and linux-like + NAND initialization process. + if !SPL_BUILD config NAND_DENALI bool "Support Denali NAND controller" + select SYS_NAND_SELF_INIT help Enable support for the Denali NAND controller. diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 9114a86..620b6e8 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -18,6 +18,7 @@ #include <malloc.h> #include <nand.h> #include <watchdog.h> +#include <linux/mtd/nand_ecc.h> #ifdef CONFIG_ATMEL_NAND_HWECC @@ -762,6 +763,62 @@ static int pmecc_choose_ecc(struct atmel_nand_host *host, } #endif +#if defined(NO_GALOIS_TABLE_IN_ROM) +static uint16_t *pmecc_galois_table; +static inline int deg(unsigned int poly) +{ + /* polynomial degree is the most-significant bit index */ + return fls(poly) - 1; +} + +static int build_gf_tables(int mm, unsigned int poly, + int16_t *index_of, int16_t *alpha_to) +{ + unsigned int i, x = 1; + const unsigned int k = 1 << deg(poly); + unsigned int nn = (1 << mm) - 1; + + /* primitive polynomial must be of degree m */ + if (k != (1u << mm)) + return -EINVAL; + + for (i = 0; i < nn; i++) { + alpha_to[i] = x; + index_of[x] = i; + if (i && (x == 1)) + /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */ + return -EINVAL; + x <<= 1; + if (x & k) + x ^= poly; + } + + alpha_to[nn] = 1; + index_of[0] = 0; + + return 0; +} + +static uint16_t *create_lookup_table(int sector_size) +{ + int degree = (sector_size == 512) ? + PMECC_GF_DIMENSION_13 : + PMECC_GF_DIMENSION_14; + unsigned int poly = (sector_size == 512) ? + PMECC_GF_13_PRIMITIVE_POLY : + PMECC_GF_14_PRIMITIVE_POLY; + int table_size = (sector_size == 512) ? + PMECC_INDEX_TABLE_SIZE_512 : + PMECC_INDEX_TABLE_SIZE_1024; + + int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL); + if (addr && build_gf_tables(degree, poly, addr, addr + table_size)) + return NULL; + + return (uint16_t *)addr; +} +#endif + static int atmel_pmecc_nand_init_params(struct nand_chip *nand, struct mtd_info *mtd) { @@ -809,11 +866,18 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, sector_size = host->pmecc_sector_size; /* TODO: need check whether cap & sector_size is validate */ - +#if defined(NO_GALOIS_TABLE_IN_ROM) + /* + * As pmecc_rom_base is the begin of the gallois field table, So the + * index offset just set as 0. + */ + host->pmecc_index_table_offset = 0; +#else if (host->pmecc_sector_size == 512) host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512; else host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024; +#endif MTDDEBUG(MTD_DEBUG_LEVEL1, "Initialize PMECC params, cap: %d, sector: %d\n", @@ -822,7 +886,17 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC; host->pmerrloc = (struct pmecc_errloc_regs __iomem *) ATMEL_BASE_PMERRLOC; +#if defined(NO_GALOIS_TABLE_IN_ROM) + pmecc_galois_table = create_lookup_table(host->pmecc_sector_size); + if (!pmecc_galois_table) { + dev_err(host->dev, "out of memory\n"); + return -ENOMEM; + } + + host->pmecc_rom_base = (void __iomem *)pmecc_galois_table; +#else host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM; +#endif /* ECC is calculated for the whole page (1 step) */ nand->ecc.size = mtd->writesize; @@ -1187,7 +1261,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; - while (this->dev_ready(&mtd)) + while (!this->dev_ready(&mtd)) ; if (cmd == NAND_CMD_READOOB) { @@ -1212,7 +1286,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); - while (this->dev_ready(&mtd)) + while (!this->dev_ready(&mtd)) ; return 0; @@ -1273,6 +1347,39 @@ static int nand_read_page(int block, int page, void *dst) return 0; } + +int spl_nand_erase_one(int block, int page) +{ + struct nand_chip *this = mtd.priv; + void (*hwctrl)(struct mtd_info *mtd, int cmd, + unsigned int ctrl) = this->cmd_ctrl; + int page_addr; + + if (nand_chip.select_chip) + nand_chip.select_chip(&mtd, 0); + + page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + /* Row address */ + hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE); + hwctrl(&mtd, ((page_addr >> 8) & 0xff), + NAND_CTRL_ALE | NAND_CTRL_CHANGE); +#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE + /* One more address cycle for devices > 128MiB */ + hwctrl(&mtd, (page_addr >> 16) & 0x0f, + NAND_CTRL_ALE | NAND_CTRL_CHANGE); +#endif + + hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + udelay(2000); + + while (!this->dev_ready(&mtd)) + ; + + nand_deselect(); + + return 0; +} #else static int nand_read_page(int block, int page, void *dst) { @@ -1319,7 +1426,7 @@ int at91_nand_wait_ready(struct mtd_info *mtd) udelay(this->chip_delay); - return 0; + return 1; } int board_nand_init(struct nand_chip *nand) diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h index 92d4ec5..eac860d 100644 --- a/drivers/mtd/nand/atmel_nand_ecc.h +++ b/drivers/mtd/nand/atmel_nand_ecc.h @@ -141,6 +141,10 @@ struct pmecc_errloc_regs { #define PMECC_GF_DIMENSION_13 13 #define PMECC_GF_DIMENSION_14 14 +/* Primitive Polynomial used by PMECC */ +#define PMECC_GF_13_PRIMITIVE_POLY 0x201b +#define PMECC_GF_14_PRIMITIVE_POLY 0x4443 + #define PMECC_INDEX_TABLE_SIZE_512 0x2000 #define PMECC_INDEX_TABLE_SIZE_1024 0x4000 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 308b784..9e0429a 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -44,7 +44,7 @@ static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; * this macro allows us to convert from an MTD structure to our own * device context (denali) structure. */ -#define mtd_to_denali(m) (((struct nand_chip *)mtd->priv)->priv) +#define mtd_to_denali(m) container_of(m->priv, struct denali_nand_info, nand) /* These constants are defined by the driver to enable common driver * configuration options. */ @@ -1144,70 +1144,128 @@ static void denali_hw_init(struct denali_nand_info *denali) static struct nand_ecclayout nand_oob; -static int denali_nand_init(struct nand_chip *nand) +static int denali_init(struct denali_nand_info *denali) { - struct denali_nand_info *denali; + int ret; - denali = malloc(sizeof(*denali)); - if (!denali) - return -ENOMEM; + denali_hw_init(denali); - nand->priv = denali; + denali->mtd->name = "denali-nand"; + denali->mtd->owner = THIS_MODULE; + denali->mtd->priv = &denali->nand; - denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; - denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE; + /* register the driver with the NAND core subsystem */ + denali->nand.select_chip = denali_select_chip; + denali->nand.cmdfunc = denali_cmdfunc; + denali->nand.read_byte = denali_read_byte; + denali->nand.read_buf = denali_read_buf; + denali->nand.waitfunc = denali_waitfunc; + + /* + * scan for NAND devices attached to the controller + * this is the first stage in a two step process to register + * with the nand subsystem + */ + if (nand_scan_ident(denali->mtd, denali->max_banks, NULL)) { + ret = -ENXIO; + goto fail; + } #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT /* check whether flash got BBT table (located at end of flash). As we * use NAND_BBT_NO_OOB, the BBT page will start with * bbt_pattern. We will have mirror pattern too */ - nand->bbt_options |= NAND_BBT_USE_FLASH; + denali->nand.bbt_options |= NAND_BBT_USE_FLASH; /* * We are using main + spare with ECC support. As BBT need ECC support, * we need to ensure BBT code don't write to OOB for the BBT pattern. * All BBT info will be stored into data area with ECC support. */ - nand->bbt_options |= NAND_BBT_NO_OOB; + denali->nand.bbt_options |= NAND_BBT_NO_OOB; #endif - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.size = CONFIG_NAND_DENALI_ECC_SIZE; - nand->ecc.read_oob = denali_read_oob; - nand->ecc.write_oob = denali_write_oob; - nand->ecc.read_page = denali_read_page; - nand->ecc.read_page_raw = denali_read_page_raw; - nand->ecc.write_page = denali_write_page; - nand->ecc.write_page_raw = denali_write_page_raw; + denali->nand.ecc.mode = NAND_ECC_HW; + denali->nand.ecc.size = CONFIG_NAND_DENALI_ECC_SIZE; + /* * Tell driver the ecc strength. This register may be already set * correctly. So we read this value out. */ - nand->ecc.strength = readl(denali->flash_reg + ECC_CORRECTION); - switch (nand->ecc.size) { + denali->nand.ecc.strength = readl(denali->flash_reg + ECC_CORRECTION); + switch (denali->nand.ecc.size) { case 512: - nand->ecc.bytes = (nand->ecc.strength * 13 + 15) / 16 * 2; + denali->nand.ecc.bytes = + (denali->nand.ecc.strength * 13 + 15) / 16 * 2; break; case 1024: - nand->ecc.bytes = (nand->ecc.strength * 14 + 15) / 16 * 2; + denali->nand.ecc.bytes = + (denali->nand.ecc.strength * 14 + 15) / 16 * 2; break; default: pr_err("Unsupported ECC size\n"); - return -EINVAL; + ret = -EINVAL; + goto fail; } - nand_oob.eccbytes = nand->ecc.bytes; - nand->ecc.layout = &nand_oob; - - /* Set address of hardware control function */ - nand->cmdfunc = denali_cmdfunc; - nand->read_byte = denali_read_byte; - nand->read_buf = denali_read_buf; - nand->select_chip = denali_select_chip; - nand->waitfunc = denali_waitfunc; - denali_hw_init(denali); - return 0; + nand_oob.eccbytes = denali->nand.ecc.bytes; + denali->nand.ecc.layout = &nand_oob; + + writel(denali->mtd->erasesize / denali->mtd->writesize, + denali->flash_reg + PAGES_PER_BLOCK); + writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0, + denali->flash_reg + DEVICE_WIDTH); + writel(denali->mtd->writesize, + denali->flash_reg + DEVICE_MAIN_AREA_SIZE); + writel(denali->mtd->oobsize, + denali->flash_reg + DEVICE_SPARE_AREA_SIZE); + if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0) + writel(1, denali->flash_reg + DEVICES_CONNECTED); + + /* override the default operations */ + denali->nand.ecc.read_page = denali_read_page; + denali->nand.ecc.read_page_raw = denali_read_page_raw; + denali->nand.ecc.write_page = denali_write_page; + denali->nand.ecc.write_page_raw = denali_write_page_raw; + denali->nand.ecc.read_oob = denali_read_oob; + denali->nand.ecc.write_oob = denali_write_oob; + + if (nand_scan_tail(denali->mtd)) { + ret = -ENXIO; + goto fail; + } + + ret = nand_register(0); + +fail: + return ret; +} + +static int __board_nand_init(void) +{ + struct denali_nand_info *denali; + + denali = kzalloc(sizeof(*denali), GFP_KERNEL); + if (!denali) + return -ENOMEM; + + /* + * If CONFIG_SYS_NAND_SELF_INIT is defined, each driver is responsible + * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c + * still provides a "struct mtd_info nand_info" instance. + */ + denali->mtd = &nand_info[0]; + + /* + * In the future, these base addresses should be taken from + * Device Tree or platform data. + */ + denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; + denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE; + + return denali_init(denali); } -int board_nand_init(struct nand_chip *chip) +void board_nand_init(void) { - return denali_nand_init(chip); + if (__board_nand_init() < 0) + pr_warn("Failed to initialize Denali NAND controller.\n"); } diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 3277da7..a258df0 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -434,9 +434,8 @@ struct nand_buf { #define DT 3 struct denali_nand_info { - struct mtd_info mtd; - struct nand_chip *nand; - + struct mtd_info *mtd; + struct nand_chip nand; int flash_bank; /* currently selected chip */ int status; int platform; diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c index 65fdde8..e98f537 100644 --- a/drivers/mtd/nand/denali_spl.c +++ b/drivers/mtd/nand/denali_spl.c @@ -203,7 +203,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) if (ret < 0) return ret; - readlen = min(page_size - column, size); + readlen = min(page_size - column, (int)size); memcpy(dst, page_buffer, readlen); column = 0; diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 81b5070..b283eae 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -292,7 +292,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) struct fsl_ifc *ifc = ctrl->regs; u32 timeo = (CONFIG_SYS_HZ * 10) / 1000; u32 time_start; - u32 eccstat[4]; + u32 eccstat[4] = {0}; int i; /* set the chip select for NAND Transaction */ diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index e336cb1..fb827c5 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -254,3 +254,13 @@ void nand_boot(void) uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; uboot(); } + +#ifndef CONFIG_SPL_NAND_INIT +void nand_init(void) +{ +} + +void nand_deselect(void) +{ +} +#endif diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 0b6e7ee..70e780c 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -634,6 +634,11 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, { struct nand_chip *chip = mtd->priv; + if (!(chip->options & NAND_BBT_SCANNED)) { + chip->scan_bbt(mtd); + chip->options |= NAND_BBT_SCANNED; + } + if (!chip->bbt) return chip->block_bad(mtd, ofs, getchip); @@ -4322,10 +4327,9 @@ int nand_scan_tail(struct mtd_info *mtd) /* Check, if we should skip the bad block table scan */ if (chip->options & NAND_SKIP_BBTSCAN) - return 0; + chip->options |= NAND_BBT_SCANNED; - /* Build bad block table */ - return chip->scan_bbt(mtd); + return 0; } EXPORT_SYMBOL(nand_scan_tail); diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 40d6705..93829a4 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -73,14 +73,11 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, writeb(cmd, this->IO_ADDR_W); } -#ifdef CONFIG_SPL_BUILD /* Check wait pin as dev ready indicator */ -static int omap_spl_dev_ready(struct mtd_info *mtd) +static int omap_dev_ready(struct mtd_info *mtd) { return gpmc_cfg->status & (1 << 8); } -#endif - /* * gen_true_ecc - This function will generate true ECC value, which @@ -887,7 +884,9 @@ int board_nand_init(struct nand_chip *nand) nand->read_buf = nand_read_buf16; else nand->read_buf = nand_read_buf; - nand->dev_ready = omap_spl_dev_ready; #endif + + nand->dev_ready = omap_dev_ready; + return 0; } diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index db87d07..b3a2a60 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -38,10 +38,10 @@ static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) } #endif -static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +static void s3c24x0_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *chip = mtd->priv; - struct s3c2410_nand *nand = s3c2410_get_base_nand(); + struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl); @@ -67,35 +67,35 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) writeb(cmd, chip->IO_ADDR_W); } -static int s3c2410_dev_ready(struct mtd_info *mtd) +static int s3c24x0_dev_ready(struct mtd_info *mtd) { - struct s3c2410_nand *nand = s3c2410_get_base_nand(); + struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); debug("dev_ready\n"); return readl(&nand->nfstat) & 0x01; } #ifdef CONFIG_S3C2410_NAND_HWECC -void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) +void s3c24x0_nand_enable_hwecc(struct mtd_info *mtd, int mode) { - struct s3c2410_nand *nand = s3c2410_get_base_nand(); - debug("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); + struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); + debug("s3c24x0_nand_enable_hwecc(%p, %d)\n", mtd, mode); writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf); } -static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, +static int s3c24x0_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { - struct s3c2410_nand *nand = s3c2410_get_base_nand(); + struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); ecc_code[0] = readb(&nand->nfecc); ecc_code[1] = readb(&nand->nfecc + 1); ecc_code[2] = readb(&nand->nfecc + 2); - debug("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", - mtd , ecc_code[0], ecc_code[1], ecc_code[2]); + debug("s3c24x0_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", + mtd , ecc_code[0], ecc_code[1], ecc_code[2]); return 0; } -static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, +static int s3c24x0_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) { if (read_ecc[0] == calc_ecc[0] && @@ -103,7 +103,7 @@ static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, read_ecc[2] == calc_ecc[2]) return 0; - printf("s3c2410_nand_correct_data: not implemented\n"); + printf("s3c24x0_nand_correct_data: not implemented\n"); return -1; } #endif @@ -113,7 +113,7 @@ int board_nand_init(struct nand_chip *nand) u_int32_t cfg; u_int8_t tacls, twrph0, twrph1; struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - struct s3c2410_nand *nand_reg = s3c2410_get_base_nand(); + struct s3c24x0_nand *nand_reg = s3c24x0_get_base_nand(); debug("board_nand_init()\n"); @@ -149,14 +149,14 @@ int board_nand_init(struct nand_chip *nand) #endif /* hwcontrol always must be implemented */ - nand->cmd_ctrl = s3c2410_hwcontrol; + nand->cmd_ctrl = s3c24x0_hwcontrol; - nand->dev_ready = s3c2410_dev_ready; + nand->dev_ready = s3c24x0_dev_ready; #ifdef CONFIG_S3C2410_NAND_HWECC - nand->ecc.hwctl = s3c2410_nand_enable_hwecc; - nand->ecc.calculate = s3c2410_nand_calculate_ecc; - nand->ecc.correct = s3c2410_nand_correct_data; + nand->ecc.hwctl = s3c24x0_nand_enable_hwecc; + nand->ecc.calculate = s3c24x0_nand_calculate_ecc; + nand->ecc.correct = s3c24x0_nand_correct_data; nand->ecc.mode = NAND_ECC_HW; nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c index 7feb3a7..928d58b 100644 --- a/drivers/mtd/nand/vf610_nfc.c +++ b/drivers/mtd/nand/vf610_nfc.c @@ -611,6 +611,9 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); } + /* Disable subpage writes as we do not provide ecc->hwctl */ + chip->options |= NAND_NO_SUBPAGE_WRITE; + chip->dev_ready = vf610_nfc_dev_ready; chip->cmdfunc = vf610_nfc_command; chip->read_byte = vf610_nfc_read_byte; diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c index 1cf2f98..3024b98 100644 --- a/drivers/mtd/spi/sandbox.c +++ b/drivers/mtd/spi/sandbox.c @@ -315,7 +315,7 @@ int sandbox_erase_part(struct sandbox_spi_flash *sbsf, int size) int ret; while (size > 0) { - todo = min(size, sizeof(sandbox_sf_0xff)); + todo = min(size, (int)sizeof(sandbox_sf_0xff)); ret = os_write(sbsf->fd, sandbox_sf_0xff, todo); if (ret != todo) return ret; @@ -602,14 +602,14 @@ static int sandbox_sf_bind_bus_cs(struct sandbox_state *state, int busnum, spec, ret); return ret; } - ret = device_find_child_by_seq(bus, cs, true, &slave); + ret = spi_find_chip_select(bus, cs, &slave); if (!ret) { printf("Chip select %d already exists for spec '%s'\n", cs, spec); return -EEXIST; } - ret = spi_bind_device(bus, cs, "spi_flash_std", spec, &slave); + ret = device_bind_driver(bus, "spi_flash_std", spec, &slave); if (ret) return ret; diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 85cf22d..759231f 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -313,10 +313,11 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, return ret; #endif byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = min(len - actual, (size_t)(page_size - byte_addr)); if (flash->spi->max_write_size) - chunk_len = min(chunk_len, flash->spi->max_write_size); + chunk_len = min(chunk_len, + (size_t)flash->spi->max_write_size); spi_flash_addr(write_addr, cmd); diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 5ae3b16..d052fcb 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -28,6 +28,8 @@ obj-$(CONFIG_PPC_T1040) += t1040.o obj-$(CONFIG_PPC_T1042) += t1040.o obj-$(CONFIG_PPC_T1020) += t1040.o obj-$(CONFIG_PPC_T1022) += t1040.o +obj-$(CONFIG_PPC_T1023) += t1024.o +obj-$(CONFIG_PPC_T1024) += t1024.o obj-$(CONFIG_PPC_T2080) += t2080.o obj-$(CONFIG_PPC_T2081) += t2080.o obj-$(CONFIG_PPC_T4240) += t4240.o diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c index 373cc4f..eb058c9 100644 --- a/drivers/net/fm/b4860.c +++ b/drivers/net/fm/b4860.c @@ -10,6 +10,7 @@ #include <asm/io.h> #include <asm/immap_85xx.h> #include <asm/fsl_serdes.h> +#include <hwconfig.h> u32 port_to_devdisr[] = { [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, @@ -46,15 +47,76 @@ void fman_enable_port(enum fm_port port) phy_interface_t fman_port_enet_if(enum fm_port port) { +#if defined(CONFIG_B4860QDS) + u32 serdes2_prtcl; + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif + if (is_device_disabled(port)) return PHY_INTERFACE_MODE_NONE; /*B4860 has two 10Gig Mac*/ if ((port == FM1_10GEC1 || port == FM1_10GEC2) && ((is_serdes_configured(XAUI_FM1_MAC9)) || - (is_serdes_configured(XAUI_FM1_MAC10)))) + #if !defined(CONFIG_B4860QDS) + (is_serdes_configured(XFI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC10)) || + #endif + (is_serdes_configured(XAUI_FM1_MAC10)) + )) return PHY_INTERFACE_MODE_XGMII; +#if defined(CONFIG_B4860QDS) + serdes2_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + + if (serdes2_prtcl) { + serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + switch (serdes2_prtcl) { + case 0x80: + case 0x81: + case 0x82: + case 0x83: + case 0x84: + case 0x85: + case 0x86: + case 0x87: + case 0x88: + case 0x89: + case 0x8a: + case 0x8b: + case 0x8c: + case 0x8d: + case 0x8e: + case 0xb1: + case 0xb2: + /* + * Extract hwconfig from environment since environment + * is not setup yet + */ + getenv_f("hwconfig", buffer, sizeof(buffer)); + buf = buffer; + + /* check if XFI interface enable in hwconfig for 10g */ + if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2", + "sfp_amc", "sfp", buf)) { + if ((port == FM1_10GEC1 || + port == FM1_10GEC2) && + ((is_serdes_configured(XFI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC10)))) + return PHY_INTERFACE_MODE_XGMII; + else if ((port == FM1_DTSEC1) || + (port == FM1_DTSEC2) || + (port == FM1_DTSEC3) || + (port == FM1_DTSEC4)) + return PHY_INTERFACE_MODE_NONE; + } + } + } +#endif + /* Fix me need to handle RGMII here first */ switch (port) { diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 218a5ed..f1e39b9 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -39,9 +39,14 @@ static void dtsec_configure_serdes(struct fm_eth *priv) u32 value; struct mii_dev bus; bus.priv = priv->mac->phyregs; + bool sgmii_2500 = (priv->enet_if == + PHY_INTERFACE_MODE_SGMII_2500) ? true : false; + + /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */ + value = PHY_SGMII_IF_MODE_SGMII; + if (!sgmii_2500) + value |= PHY_SGMII_IF_MODE_AN; - /* SGMII IF mode + AN enable */ - value = PHY_SGMII_IF_MODE_AN | PHY_SGMII_IF_MODE_SGMII; memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value); /* Dev ability according to SGMII specification */ @@ -54,7 +59,9 @@ static void dtsec_configure_serdes(struct fm_eth *priv) memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40); /* Restart AN */ - value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN; + value = PHY_SGMII_CR_DEF_VAL; + if (!sgmii_2500) + value |= PHY_SGMII_CR_RESET_AN; memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value); #else struct dtsec *regs = priv->mac->base; @@ -83,7 +90,8 @@ static void dtsec_init_phy(struct eth_device *dev) out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); #endif - if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) + if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII || + fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) dtsec_configure_serdes(fm_eth); } @@ -557,9 +565,11 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) num = fm_eth->num; #ifdef CONFIG_SYS_FMAN_V3 +#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION if (fm_eth->type == FM_ETH_10G_E) { - /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 - * 10GEC3/10GEC4 use mEMAC1/mEMAC2 + /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240. + * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080. + * 10GEC1 uses mEMAC1 on T1024. * so it needs to change the num. */ if (fm_eth->num >= 2) @@ -567,6 +577,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) else num += 8; } +#endif base = ®->memac[num].fm_memac; phyregs = ®->memac[num].fm_memac_mdio; #else diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 6cf21c6..5d82f29 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -254,8 +254,10 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) */ if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) || ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) || + ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) || ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) || ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) || + ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) || ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) || ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) || ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) || diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index 9499290..60e898c 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -37,7 +37,8 @@ static void memac_enable_mac(struct fsl_enet_mac *mac) { struct memac *regs = mac->base; - setbits_be32(®s->command_config, MEMAC_CMD_CFG_RXTX_EN); + setbits_be32(®s->command_config, + MEMAC_CMD_CFG_RXTX_EN | MEMAC_CMD_CFG_NO_LEN_CHK); } static void memac_disable_mac(struct fsl_enet_mac *mac) @@ -93,11 +94,16 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, if_mode &= ~IF_MODE_MASK; if_mode |= (IF_MODE_GMII); break; + case PHY_INTERFACE_MODE_XGMII: + if_mode &= ~IF_MODE_MASK; + if_mode |= IF_MODE_XGMII; + break; default: break; } - /* Enable automatic speed selection */ - if_mode |= IF_MODE_EN_AUTO; + /* Enable automatic speed selection for Non-XGMII */ + if (type != PHY_INTERFACE_MODE_XGMII) + if_mode |= IF_MODE_EN_AUTO; if (type == PHY_INTERFACE_MODE_RGMII) { if_mode &= ~IF_MODE_EN_AUTO; diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 5f910c2..a155d89 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -71,6 +71,8 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, u32 c45 = 1; if (dev_addr == MDIO_DEVAD_NONE) { + if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME)) + return 0xffff; c45 = 0; /* clause 22 */ dev_addr = regnum & 0x1f; clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC); @@ -137,9 +139,12 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info) * is zero, so MDIO clock is disabled. * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to * be properly initialized. + * NEG bit default should be '1' as per FMAN-v3 RM, but on platform + * like T2080QDS, this bit default is '0', which leads to MDIO failure + * on XAUI PHY, so set this bit definitely. */ setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat, - MDIO_STAT_CLKDIV(258)); + MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG); return mdio_register(bus); } diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c new file mode 100644 index 0000000..9b31173 --- /dev/null +++ b/drivers/net/fm/t1024.c @@ -0,0 +1,88 @@ +/* Copyright 2014 Freescale Semiconductor, Inc. + * + * Shengzhou Liu <Shengzhou.Liu@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <phy.h> +#include <fm_eth.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */ +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_RGMII) && + (!is_serdes_configured(QSGMII_FM1_A))) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_RGMII) && + (!is_serdes_configured(QSGMII_FM1_A))) + return PHY_INTERFACE_MODE_RGMII; + + /* handle SGMII */ + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1 + + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII_2500; + break; + default: + break; + } + + /* handle QSGMII */ + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + /* check lane A on SerDes1 */ + if (is_serdes_configured(QSGMII_FM1_A)) + return PHY_INTERFACE_MODE_QSGMII; + break; + default: + break; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c index 4cce46d..d2a097e 100644 --- a/drivers/net/fm/t1040.c +++ b/drivers/net/fm/t1040.c @@ -25,8 +25,6 @@ phy_interface_t fman_port_enet_if(enum fm_port port) else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) return PHY_INTERFACE_MODE_MII; - else - return PHY_INTERFACE_MODE_NONE; } if ((port == FM1_DTSEC4) && @@ -38,8 +36,6 @@ phy_interface_t fman_port_enet_if(enum fm_port port) else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) return PHY_INTERFACE_MODE_MII; - else - return PHY_INTERFACE_MODE_NONE; } if (port == FM1_DTSEC5) { diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 375c8a4..9c2ff48 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -525,6 +525,7 @@ static int macb_phy_init(struct macb_device *macb) return 1; } +static int macb_write_hwaddr(struct eth_device *dev); static int macb_init(struct eth_device *netdev, bd_t *bd) { struct macb_device *macb = to_macb(netdev); @@ -565,7 +566,13 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) macb_writel(macb, TBQP, macb->tx_ring_dma); if (macb_is_gem(macb)) { -#ifdef CONFIG_RGMII + /* + * When the GMAC IP with GE feature, this bit is used to + * select interface between RGMII and GMII. + * When the GMAC IP without GE feature, this bit is used + * to select interface between RMII and MII. + */ +#if defined(CONFIG_RGMII) || defined(CONFIG_RMII) gem_writel(macb, UR, GEM_BIT(RGMII)); #else gem_writel(macb, UR, 0); @@ -587,6 +594,14 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) #endif /* CONFIG_RMII */ } + /* update the ethaddr */ + if (is_valid_ether_addr(netdev->enetaddr)) { + macb_write_hwaddr(netdev); + } else { + printf("%s: mac address is not valid\n", netdev->name); + return -1; + } + if (!macb_phy_init(macb)) return -1; diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index 623f749..677c89f 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -256,7 +256,7 @@ static void nc_puts(struct stdio_dev *dev, const char *s) len = strlen(s); while (len) { - int send_len = min(len, sizeof(input_buffer)); + int send_len = min(len, (int)sizeof(input_buffer)); nc_send_packet(s, send_len); len -= send_len; s += send_len; diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 9556536..f46bf00 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_PHYLIB) += phy.o obj-$(CONFIG_PHYLIB_10G) += generic_10g.o obj-$(CONFIG_PHY_ATHEROS) += atheros.o obj-$(CONFIG_PHY_BROADCOM) += broadcom.o +obj-$(CONFIG_PHY_CORTINA) += cortina.o obj-$(CONFIG_PHY_DAVICOM) += davicom.o obj-$(CONFIG_PHY_ET1011C) += et1011c.o obj-$(CONFIG_PHY_LXT) += lxt.o diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c new file mode 100644 index 0000000..254f056 --- /dev/null +++ b/drivers/net/phy/cortina.c @@ -0,0 +1,333 @@ +/* + * Cortina CS4315/CS4340 10G PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2014 Freescale Semiconductor, Inc. + * + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <linux/ctype.h> +#include <linux/string.h> +#include <linux/err.h> +#include <phy.h> +#include <cortina.h> +#ifdef CONFIG_SYS_CORTINA_FW_IN_NAND +#include <nand.h> +#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH) +#include <spi_flash.h> +#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) +#include <mmc.h> +#endif + +#ifndef CONFIG_PHYLIB_10G +#error The Cortina PHY needs 10G support +#endif + +struct cortina_reg_config cortina_reg_cfg[] = { + /* CS4315_enable_sr_mode */ + {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, + {VILLA_MSEQ_OPTIONS, 0xf}, + {VILLA_MSEQ_PC, 0x0}, + {VILLA_MSEQ_BANKSELECT, 0x4}, + {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55}, + {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30}, + {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1}, + {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2}, + {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003}, + {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047}, + {VILLA_MSEQ_ENABLE_MSB, 0x0000}, + {VILLA_MSEQ_SPARE21_LSB, 0x6}, + {VILLA_MSEQ_RESET_COUNT_LSB, 0x0}, + {VILLA_MSEQ_SPARE12_MSB, 0x0000}, + /* + * to invert the receiver path, uncomment the next line + * write (VILLA_MSEQ_SPARE12_MSB, 0x4000) + * + * SPARE2_LSB is used to configure the device while in sr mode to + * enable power savings and to use the optical module LOS signal. + * in power savings mode, the internal prbs checker can not be used. + * if the optical module LOS signal is used as an input to the micro + * code, then the micro code will wait until the optical module + * LOS = 0 before turning on the adaptive equalizer. + * Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode + * while setting bit 0 to 0 disables power savings mode. + * Setting SPARE2_LSB bit 2 to 0 configures the device to use the + * optical module LOS signal while setting bit 2 to 1 configures the + * device so that it will ignore the optical module LOS SPARE2_LSB = 0 + */ + + /* enable power savings, ignore optical module LOS */ + {VILLA_MSEQ_SPARE2_LSB, 0x5}, + + {VILLA_MSEQ_SPARE7_LSB, 0x1e}, + {VILLA_MSEQ_BANKSELECT, 0x4}, + {VILLA_MSEQ_SPARE9_LSB, 0x2}, + {VILLA_MSEQ_SPARE3_LSB, 0x0F53}, + {VILLA_MSEQ_SPARE3_MSB, 0x2006}, + {VILLA_MSEQ_SPARE8_LSB, 0x3FF7}, + {VILLA_MSEQ_SPARE8_MSB, 0x0A46}, + {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500}, + {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200}, + {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00}, + {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100}, + {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300}, + {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300}, + {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700}, + {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00}, + {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00}, + {VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2}, + {VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000}, + {VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF}, + {VILLA_MSEQ_POWER_DOWN_MSB, 0x0}, + {VILLA_MSEQ_CAL_RX_SLICER, 0x80}, + {VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f}, + {VILLA_GLOBAL_MSEQCLKCTRL, 0x4}, + {VILLA_MSEQ_OPTIONS, 0x7}, + + /* set up min value for ffe1 */ + {VILLA_MSEQ_COEF_INIT_SEL, 0x2}, + {VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41}, + + /* CS4315_sr_rx_pre_eq_set_4in */ + {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, + {VILLA_MSEQ_OPTIONS, 0xf}, + {VILLA_MSEQ_BANKSELECT, 0x4}, + {VILLA_MSEQ_PC, 0x0}, + + /* for lengths from 3.5 to 4.5inches */ + {VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306}, + {VILLA_MSEQ_SPARE25_LSB, 0x0306}, + {VILLA_MSEQ_SPARE21_LSB, 0x2}, + {VILLA_MSEQ_SPARE23_LSB, 0x2}, + {VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0}, + + {VILLA_GLOBAL_MSEQCLKCTRL, 0x4}, + {VILLA_MSEQ_OPTIONS, 0x7}, + + /* CS4315_rx_drive_4inch */ + /* for length 4inches */ + {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000}, + {VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023}, + {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E}, + + /* CS4315_tx_drive_4inch */ + /* for length 4inches */ + {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000}, + {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023}, + {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E}, +}; + +void cs4340_upload_firmware(struct phy_device *phydev) +{ + char line_temp[0x50] = {0}; + char reg_addr[0x50] = {0}; + char reg_data[0x50] = {0}; + int i, line_cnt = 0, column_cnt = 0; + struct cortina_reg_config fw_temp; + char *addr = NULL; + +#if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \ + defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE) + + addr = (char *)CONFIG_CORTINA_FW_ADDR; +#elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND) + int ret; + size_t fw_length = CONFIG_CORTINA_FW_LENGTH; + + addr = malloc(CONFIG_CORTINA_FW_LENGTH); + ret = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR, + &fw_length, (u_char *)addr); + if (ret == -EUCLEAN) { + printf("NAND read of Cortina firmware at 0x%x failed %d\n", + CONFIG_CORTINA_FW_ADDR, ret); + } +#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH) + int ret; + struct spi_flash *ucode_flash; + + addr = malloc(CONFIG_CORTINA_FW_LENGTH); + ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (!ucode_flash) { + puts("SF: probe for Cortina ucode failed\n"); + } else { + ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR, + CONFIG_CORTINA_FW_LENGTH, addr); + if (ret) + puts("SF: read for Cortina ucode failed\n"); + spi_flash_free(ucode_flash); + } +#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) + int dev = CONFIG_SYS_MMC_ENV_DEV; + u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512; + u32 blk = CONFIG_CORTINA_FW_ADDR / 512; + struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + + if (!mmc) { + puts("Failed to find MMC device for Cortina ucode\n"); + } else { + addr = malloc(CONFIG_CORTINA_FW_LENGTH); + printf("MMC read: dev # %u, block # %u, count %u ...\n", + dev, blk, cnt); + mmc_init(mmc); + (void)mmc->block_dev.block_read(dev, blk, cnt, addr); + /* flush cache after read */ + flush_cache((ulong)addr, cnt * 512); + } +#endif + + while (*addr != 'Q') { + i = 0; + + while (*addr != 0x0a) { + line_temp[i++] = *addr++; + if (0x50 < i) { + printf("Not found Cortina PHY ucode at 0x%x\n", + CONFIG_CORTINA_FW_ADDR); + return; + } + } + + addr++; /* skip '\n' */ + line_cnt++; + column_cnt = i; + line_temp[column_cnt] = '\0'; + + if (CONFIG_CORTINA_FW_LENGTH < line_cnt) + return; + + for (i = 0; i < column_cnt; i++) { + if (isspace(line_temp[i++])) + break; + } + + memcpy(reg_addr, line_temp, i); + memcpy(reg_data, &line_temp[i], column_cnt - i); + strim(reg_addr); + strim(reg_data); + fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff; + fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & + 0xffff; + phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); + } +} + +int cs4340_phy_init(struct phy_device *phydev) +{ + int timeout = 100; /* 100ms */ + int reg_value; + + /* step1: BIST test */ + phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); + phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); + phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001); + while (--timeout) { + reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); + if (reg_value & mseq_edc_bist_done) { + if (0 == (reg_value & mseq_edc_bist_fail)) + break; + } + udelay(1000); + } + + if (!timeout) { + printf("%s BIST mseq_edc_bist_done timeout!\n", __func__); + return -1; + } + + /* setp2: upload ucode */ + cs4340_upload_firmware(phydev); + reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); + if (reg_value) { + debug("%s checksum status failed.\n", __func__); + return -1; + } + + return 0; +} + +int cs4340_config(struct phy_device *phydev) +{ + cs4340_phy_init(phydev); + return 0; +} + +int cs4340_startup(struct phy_device *phydev) +{ + phydev->link = 1; + + /* For now just lie and say it's 10G all the time */ + phydev->speed = SPEED_10000; + phydev->duplex = DUPLEX_FULL; + return 0; +} + +struct phy_driver cs4340_driver = { + .name = "Cortina CS4315/CS4340", + .uid = PHY_UID_CS4340, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | + MDIO_DEVS_PHYXS | MDIO_DEVS_AN | + MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2), + .config = &cs4340_config, + .startup = &cs4340_startup, + .shutdown = &gen10g_shutdown, +}; + +int phy_cortina_init(void) +{ + phy_register(&cs4340_driver); + return 0; +} + +int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) +{ + int phy_reg; + bool is_cortina_phy = false; + + switch (addr) { +#ifdef CORTINA_PHY_ADDR1 + case CORTINA_PHY_ADDR1: +#endif +#ifdef CORTINA_PHY_ADDR2 + case CORTINA_PHY_ADDR2: +#endif +#ifdef CORTINA_PHY_ADDR3 + case CORTINA_PHY_ADDR3: +#endif +#ifdef CORTINA_PHY_ADDR4 + case CORTINA_PHY_ADDR4: +#endif + is_cortina_phy = true; + break; + default: + break; + } + + /* Cortina PHY has non-standard offset of PHY ID registers */ + if (is_cortina_phy) + phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB); + else + phy_reg = bus->read(bus, addr, devad, MII_PHYSID1); + + if (phy_reg < 0) + return -EIO; + + *phy_id = (phy_reg & 0xffff) << 16; + if (is_cortina_phy) + phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB); + else + phy_reg = bus->read(bus, addr, devad, MII_PHYSID2); + + if (phy_reg < 0) + return -EIO; + + *phy_id |= (phy_reg & 0xffff); + + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 467c972..5b04c85 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -448,6 +448,9 @@ int phy_init(void) #ifdef CONFIG_PHY_BROADCOM phy_broadcom_init(); #endif +#ifdef CONFIG_PHY_CORTINA + phy_cortina_init(); +#endif #ifdef CONFIG_PHY_DAVICOM phy_davicom_init(); #endif diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 2b29cd8..20a6746 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -1,8 +1,8 @@ /* * Vitesse PHY drivers * - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * Author: Andy Fleming + * Copyright 2010-2014 Freescale Semiconductor, Inc. + * Original Author: Andy Fleming * Add vsc8662 phy support - Priyanka Jain * SPDX-License-Identifier: GPL-2.0+ */ @@ -50,6 +50,7 @@ #define MIIM_VSC8574_18G_CMDSTAT 0x8000 /* Vitesse VSC8514 control register */ +#define MIIM_VSC8514_MAC_SERDES_CON 0x10 #define MIIM_VSC8514_GENERAL18 0x12 #define MIIM_VSC8514_GENERAL19 0x13 #define MIIM_VSC8514_GENERAL23 0x17 @@ -246,6 +247,14 @@ static int vsc8514_config(struct phy_device *phydev) val = (val & 0xf8ff); phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23, val); + /* Enable Serdes Auto-negotiation */ + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, + PHY_EXT_PAGE_ACCESS_EXTENDED3); + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON); + val = val | MIIM_VSC8574_MAC_SERDES_ANEG; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON, val); + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + genphy_config_aneg(phydev); return 0; diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index e73a498..85e82bd 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -6,7 +6,7 @@ # obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o -obj-$(CONFIG_PCI) += pci.o pci_auto.o +obj-$(CONFIG_PCI) += pci.o pci_auto.o pci_rom.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o obj-$(CONFIG_PCI_MSC01) += pci_msc01.o @@ -17,3 +17,4 @@ obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o obj-$(CONFIG_WINBOND_83C553) += w83c553f.o +obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 60c333e..3daf73c 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -195,6 +195,9 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) bdf < PCI_BDF(bus + 1, 0, 0); #endif bdf += PCI_BDF(0, 0, 1)) { + if (pci_skip_dev(hose, bdf)) + continue; + if (!PCI_FUNC(bdf)) { pci_read_config_byte(bdf, PCI_HEADER_TYPE, @@ -363,9 +366,27 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, return phys_addr; } -/* - * - */ +void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, + u32 addr_and_ctrl) +{ + int bar; + + bar = PCI_BASE_ADDRESS_0 + barnum * 4; + pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl); +} + +u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum) +{ + u32 addr; + int bar; + + bar = PCI_BASE_ADDRESS_0 + barnum * 4; + pci_hose_read_config_dword(hose, dev, bar, &addr); + if (addr & PCI_BASE_ADDRESS_SPACE_IO) + return addr & PCI_BASE_ADDRESS_IO_MASK; + else + return addr & PCI_BASE_ADDRESS_MEM_MASK; +} int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev, @@ -662,13 +683,15 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) #endif #ifdef CONFIG_PCI_PNP - sub_bus = max(pciauto_config_device(hose, dev), sub_bus); + sub_bus = max((unsigned int)pciauto_config_device(hose, dev), + sub_bus); #else cfg = pci_find_config(hose, class, vendor, device, PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); if (cfg) { cfg->config_device(hose, dev, cfg); - sub_bus = max(sub_bus, hose->current_busno); + sub_bus = max(sub_bus, + (unsigned int)hose->current_busno); } #endif diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 86ba6b5..44470fa 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -387,7 +387,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) n = pci_hose_scan_bus(hose, hose->current_busno); /* figure out the deepest we've gone for this leg */ - sub_bus = max(n, sub_bus); + sub_bus = max((unsigned int)n, sub_bus); pciauto_postscan_setup_bridge(hose, dev, sub_bus); sub_bus = hose->current_busno; diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c new file mode 100644 index 0000000..af6a3ae --- /dev/null +++ b/drivers/pci/pci_rom.c @@ -0,0 +1,278 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * From coreboot, originally based on the Linux kernel (drivers/pci/pci.c). + * + * Modifications are: + * Copyright (C) 2003-2004 Linux Networx + * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx) + * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com> + * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov> + * Copyright (C) 2005-2006 Tyan + * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan) + * Copyright (C) 2005-2009 coresystems GmbH + * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH) + * + * PCI Bus Services, see include/linux/pci.h for further explanation. + * + * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, + * David Mosberger-Tang + * + * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz> + + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <bios_emul.h> +#include <errno.h> +#include <malloc.h> +#include <pci.h> +#include <pci_rom.h> +#include <vbe.h> +#include <video_fb.h> + +#ifdef CONFIG_HAVE_ACPI_RESUME +#include <asm/acpi.h> +#endif + +__weak bool board_should_run_oprom(pci_dev_t dev) +{ + return true; +} + +static bool should_load_oprom(pci_dev_t dev) +{ +#ifdef CONFIG_HAVE_ACPI_RESUME + if (acpi_get_slp_type() == 3) + return false; +#endif + if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) + return 1; + if (board_should_run_oprom(dev)) + return 1; + + return 0; +} + +__weak uint32_t board_map_oprom_vendev(uint32_t vendev) +{ + return vendev; +} + +static int pci_rom_probe(pci_dev_t dev, uint class, + struct pci_rom_header **hdrp) +{ + struct pci_rom_header *rom_header; + struct pci_rom_data *rom_data; + u16 vendor, device; + u32 vendev; + u32 mapped_vendev; + u32 rom_address; + + pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); + pci_read_config_word(dev, PCI_DEVICE_ID, &device); + vendev = vendor << 16 | device; + mapped_vendev = board_map_oprom_vendev(vendev); + if (vendev != mapped_vendev) + debug("Device ID mapped to %#08x\n", mapped_vendev); + +#ifdef CONFIG_X86_OPTION_ROM_ADDR + rom_address = CONFIG_X86_OPTION_ROM_ADDR; +#else + pci_write_config_dword(dev, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK); + pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address); + if (rom_address == 0x00000000 || rom_address == 0xffffffff) { + debug("%s: rom_address=%x\n", __func__, rom_address); + return -ENOENT; + } + + /* Enable expansion ROM address decoding. */ + pci_write_config_dword(dev, PCI_ROM_ADDRESS, + rom_address | PCI_ROM_ADDRESS_ENABLE); +#endif + debug("Option ROM address %x\n", rom_address); + rom_header = (struct pci_rom_header *)rom_address; + + debug("PCI expansion ROM, signature %#04x, INIT size %#04x, data ptr %#04x\n", + le32_to_cpu(rom_header->signature), + rom_header->size * 512, le32_to_cpu(rom_header->data)); + + if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) { + printf("Incorrect expansion ROM header signature %04x\n", + le32_to_cpu(rom_header->signature)); + return -EINVAL; + } + + rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data)); + + debug("PCI ROM image, vendor ID %04x, device ID %04x,\n", + rom_data->vendor, rom_data->device); + + /* If the device id is mapped, a mismatch is expected */ + if ((vendor != rom_data->vendor || device != rom_data->device) && + (vendev == mapped_vendev)) { + printf("ID mismatch: vendor ID %04x, device ID %04x\n", + rom_data->vendor, rom_data->device); + return -EPERM; + } + + debug("PCI ROM image, Class Code %04x%02x, Code Type %02x\n", + rom_data->class_hi, rom_data->class_lo, rom_data->type); + + if (class != ((rom_data->class_hi << 8) | rom_data->class_lo)) { + debug("Class Code mismatch ROM %08x, dev %08x\n", + (rom_data->class_hi << 8) | rom_data->class_lo, + class); + } + *hdrp = rom_header; + + return 0; +} + +int pci_rom_load(uint16_t class, struct pci_rom_header *rom_header, + struct pci_rom_header **ram_headerp) +{ + struct pci_rom_data *rom_data; + unsigned int rom_size; + unsigned int image_size = 0; + void *target; + + do { + /* Get next image, until we see an x86 version */ + rom_header = (struct pci_rom_header *)((void *)rom_header + + image_size); + + rom_data = (struct pci_rom_data *)((void *)rom_header + + le32_to_cpu(rom_header->data)); + + image_size = le32_to_cpu(rom_data->ilen) * 512; + } while ((rom_data->type != 0) && (rom_data->indicator != 0)); + + if (rom_data->type != 0) + return -EACCES; + + rom_size = rom_header->size * 512; + + target = (void *)PCI_VGA_RAM_IMAGE_START; + if (target != rom_header) { + debug("Copying VGA ROM Image from %p to %p, 0x%x bytes\n", + rom_header, target, rom_size); + memcpy(target, rom_header, rom_size); + if (memcmp(target, rom_header, rom_size)) { + printf("VGA ROM copy failed\n"); + return -EFAULT; + } + } + *ram_headerp = target; + + return 0; +} + +static struct vbe_mode_info mode_info; + +int vbe_get_video_info(struct graphic_device *gdev) +{ +#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE + struct vesa_mode_info *vesa = &mode_info.vesa; + + gdev->winSizeX = vesa->x_resolution; + gdev->winSizeY = vesa->y_resolution; + + gdev->plnSizeX = vesa->x_resolution; + gdev->plnSizeY = vesa->y_resolution; + + gdev->gdfBytesPP = vesa->bits_per_pixel / 8; + + switch (vesa->bits_per_pixel) { + case 24: + gdev->gdfIndex = GDF_32BIT_X888RGB; + break; + case 16: + gdev->gdfIndex = GDF_16BIT_565RGB; + break; + default: + gdev->gdfIndex = GDF__8BIT_INDEX; + break; + } + + gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; + gdev->pciBase = vesa->phys_base_ptr; + + gdev->frameAdrs = vesa->phys_base_ptr; + gdev->memSize = vesa->bytes_per_scanline * vesa->y_resolution; + + gdev->vprBase = vesa->phys_base_ptr; + gdev->cprBase = vesa->phys_base_ptr; + + return 0; +#else + return -ENOSYS; +#endif +} + +int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate) +{ + struct pci_rom_header *rom, *ram; + int vesa_mode = -1; + uint16_t class; + int ret; + + /* Only execute VGA ROMs */ + pci_read_config_word(dev, PCI_CLASS_DEVICE, &class); + if ((class ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) { + debug("%s: Class %#x, should be %#x\n", __func__, class, + PCI_CLASS_DISPLAY_VGA); + return -ENODEV; + } + + if (!should_load_oprom(dev)) + return -ENXIO; + + ret = pci_rom_probe(dev, class, &rom); + if (ret) + return ret; + + ret = pci_rom_load(class, rom, &ram); + if (ret) + return ret; + + if (!board_should_run_oprom(dev)) + return -ENXIO; + +#if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \ + defined(CONFIG_FRAMEBUFFER_VESA_MODE) + vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE; +#endif + debug("Selected vesa mode %d\b", vesa_mode); + if (emulate) { +#ifdef CONFIG_BIOSEMU + BE_VGAInfo *info; + + ret = biosemu_setup(dev, &info); + if (ret) + return ret; + biosemu_set_interrupt_handler(0x15, int15_handler); + ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, true, + vesa_mode, &mode_info); + if (ret) + return ret; +#else + printf("BIOS emulation not available - see CONFIG_BIOSEMU\n"); + return -ENOSYS; +#endif + } else { +#ifdef CONFIG_X86 + bios_set_interrupt_handler(0x15, int15_handler); + + bios_run_on_x86(dev, (unsigned long)ram, vesa_mode, + &mode_info); +#else + printf("BIOS native execution is only available on x86\n"); + return -ENOSYS; +#endif + } + debug("Final vesa mode %d\n", mode_info.video_mode); + + return 0; +} diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c new file mode 100644 index 0000000..291c249 --- /dev/null +++ b/drivers/pci/pcie_layerscape.c @@ -0,0 +1,51 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Layerscape PCIe driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/fsl_serdes.h> +#include <pci.h> +#include <asm/io.h> +#include <asm/pcie_layerscape.h> + +#ifdef CONFIG_OF_BOARD_SETUP +#include <libfdt.h> +#include <fdt_support.h> + +static void ft_pcie_ls_setup(void *blob, const char *pci_compat, + unsigned long ctrl_addr, enum srds_prtcl dev) +{ + int off; + + off = fdt_node_offset_by_compat_reg(blob, pci_compat, + (phys_addr_t)ctrl_addr); + if (off < 0) + return; + + if (!is_serdes_configured(dev)) + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +} + +void ft_pcie_setup(void *blob, bd_t *bd) +{ + #ifdef CONFIG_PCIE1 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1); + #endif + + #ifdef CONFIG_PCIE2 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2); + #endif +} + +#else +void ft_pcie_setup(void *blob, bd_t *bd) +{ +} +#endif + +void pci_init_board(void) +{ +} diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index cfbc9dc..6430fe0 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -27,7 +27,7 @@ int palmas_mmc1_poweron_ldo(void) { u8 val = 0; -#if defined(CONFIG_DRA7XX) +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) /* * Currently valid for the dra7xx_evm board: * Set TPS659038 LDO1 to 3.0 V diff --git a/drivers/power/pmic/pmic_max77686.c b/drivers/power/pmic/pmic_max77686.c index df1fd91..95b1a57 100644 --- a/drivers/power/pmic/pmic_max77686.c +++ b/drivers/power/pmic/pmic_max77686.c @@ -42,11 +42,30 @@ static unsigned int max77686_ldo_volt2hex(int ldo, ulong uV) return 0; } +static int max77686_buck_volt2hex(int buck, ulong uV) +{ + int hex = 0; + + if (buck < 5 || buck > 9) { + debug("%s: buck %d is not supported\n", __func__, buck); + return -EINVAL; + } + + hex = (uV - 750000) / 50000; + + if (hex >= 0 && hex <= MAX77686_BUCK_VOLT_MAX_HEX) + return hex; + + debug("%s: %ld is wrong voltage value for BUCK%d\n", + __func__, uV, buck); + return -EINVAL; +} + int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV) { unsigned int val, ret, hex, adr; - if (ldo < 1 && ldo > 26) { + if (ldo < 1 || ldo > 26) { printf("%s: %d is wrong ldo number\n", __func__, ldo); return -1; } @@ -68,11 +87,38 @@ int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV) return ret; } +int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV) +{ + unsigned int val, adr; + int hex, ret; + + if (buck < 5 || buck > 9) { + printf("%s: %d is an unsupported bucket number\n", + __func__, buck); + return -EINVAL; + } + + adr = max77686_buck_addr[buck] + 1; + hex = max77686_buck_volt2hex(buck, uV); + + if (hex < 0) + return hex; + + ret = pmic_reg_read(p, adr, &val); + if (ret) + return ret; + + val &= ~MAX77686_BUCK_VOLT_MASK; + ret |= pmic_reg_write(p, adr, val | hex); + + return ret; +} + int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode) { unsigned int val, ret, adr, mode; - if (ldo < 1 && 26 < ldo) { + if (ldo < 1 || 26 < ldo) { printf("%s: %d is wrong ldo number\n", __func__, ldo); return -1; } @@ -157,7 +203,7 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode) /* mode */ switch (opmode) { case OPMODE_OFF: - mode = MAX77686_BUCK_MODE_OFF; + mode = MAX77686_BUCK_MODE_OFF << mode_shift; break; case OPMODE_STANDBY: switch (buck) { diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c index 594cd11..0dcf9fe 100644 --- a/drivers/power/power_i2c.c +++ b/drivers/power/power_i2c.c @@ -14,7 +14,7 @@ #include <linux/types.h> #include <power/pmic.h> #include <i2c.h> -#include <compiler.h> +#include <linux/compiler.h> int pmic_reg_write(struct pmic *p, u32 reg, u32 val) { diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c index e578ae6..7f1fdd1 100644 --- a/drivers/power/twl4030.c +++ b/drivers/power/twl4030.c @@ -91,17 +91,23 @@ void twl4030_power_init(void) TWL4030_PM_RECEIVER_DEV_GRP_P1); } -void twl4030_power_mmc_init(void) +void twl4030_power_mmc_init(int dev_index) { - /* Set VMMC1 to 3.15 Volts */ - twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED, - TWL4030_PM_RECEIVER_VMMC1_VSEL_32, - TWL4030_PM_RECEIVER_VMMC1_DEV_GRP, - TWL4030_PM_RECEIVER_DEV_GRP_P1); + if (dev_index == 0) { + /* Set VMMC1 to 3.15 Volts */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED, + TWL4030_PM_RECEIVER_VMMC1_VSEL_32, + TWL4030_PM_RECEIVER_VMMC1_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); - /* Set VMMC2 to 3.15 Volts */ - twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED, - TWL4030_PM_RECEIVER_VMMC2_VSEL_32, - TWL4030_PM_RECEIVER_VMMC2_DEV_GRP, - TWL4030_PM_RECEIVER_DEV_GRP_P1); + mdelay(100); /* ramp-up delay from Linux code */ + } else if (dev_index == 1) { + /* Set VMMC2 to 3.15 Volts */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED, + TWL4030_PM_RECEIVER_VMMC2_VSEL_32, + TWL4030_PM_RECEIVER_VMMC2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + + mdelay(100); /* ramp-up delay from Linux code */ + } } diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile index 7f1bd06..8fa4866 100644 --- a/drivers/qe/Makefile +++ b/drivers/qe/Makefile @@ -4,5 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := qe.o uccf.o uec.o uec_phy.o +obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o +obj-$(CONFIG_U_QE) += qe.o obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c index d9a7d82..dfae4bf 100644 --- a/drivers/qe/fdt.c +++ b/drivers/qe/fdt.c @@ -12,6 +12,7 @@ #include <fdt_support.h> #include "qe.h" +#ifdef CONFIG_QE DECLARE_GLOBAL_DATA_PTR; /* @@ -72,3 +73,4 @@ void ft_qe_setup(void *blob) "clock-frequency", gd->arch.qe_clk / 2, 1); fdt_fixup_qe_firmware(blob); } +#endif diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 4358a91..bc94673 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -40,6 +40,7 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) return; } +#ifdef CONFIG_QE uint qe_muram_alloc(uint size, uint align) { uint retloc; @@ -70,6 +71,7 @@ uint qe_muram_alloc(uint size, uint align) return retloc; } +#endif void *qe_muram_addr(uint offset) { @@ -180,6 +182,17 @@ void qe_init(uint qe_base) qe_snums_init(); } +#ifdef CONFIG_U_QE +void u_qe_init(void) +{ + uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */ + qe_immr = (qe_map_t *)qe_base; + + u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); + out_be32(&qe_immr->iram.iready, QE_IRAM_READY); +} +#endif + void qe_reset(void) { qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID, @@ -212,6 +225,7 @@ void qe_assign_page(uint snum, uint para_ram_base) #define BRG_CLK (gd->arch.brg_clk) +#ifdef CONFIG_QE int qe_set_brg(uint brg, uint rate) { volatile uint *bp; @@ -239,6 +253,7 @@ int qe_set_brg(uint brg, uint rate) return 0; } +#endif /* Set ethernet MII clock master */ @@ -429,6 +444,131 @@ int qe_upload_firmware(const struct qe_firmware *firmware) return 0; } +#ifdef CONFIG_U_QE +/* + * Upload a microcode to the I-RAM at a specific address. + * + * See docs/README.qe_firmware for information on QE microcode uploading. + * + * Currently, only version 1 is supported, so the 'version' field must be + * set to 1. + * + * The SOC model and revision are not validated, they are only displayed for + * informational purposes. + * + * 'calc_size' is the calculated size, in bytes, of the firmware structure and + * all of the microcode structures, minus the CRC. + * + * 'length' is the size that the structure says it is, including the CRC. + */ +int u_qe_upload_firmware(const struct qe_firmware *firmware) +{ + unsigned int i; + unsigned int j; + u32 crc; + size_t calc_size = sizeof(struct qe_firmware); + size_t length; + const struct qe_header *hdr; +#ifdef CONFIG_DEEP_SLEEP + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif + if (!firmware) { + printf("Invalid address\n"); + return -EINVAL; + } + + hdr = &firmware->header; + length = be32_to_cpu(hdr->length); + + /* Check the magic */ + if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || + (hdr->magic[2] != 'F')) { + printf("Not a microcode\n"); +#ifdef CONFIG_DEEP_SLEEP + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); +#endif + return -EPERM; + } + + /* Check the version */ + if (hdr->version != 1) { + printf("Unsupported version\n"); + return -EPERM; + } + + /* Validate some of the fields */ + if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) { + printf("Invalid data\n"); + return -EINVAL; + } + + /* Validate the length and check if there's a CRC */ + calc_size += (firmware->count - 1) * sizeof(struct qe_microcode); + + for (i = 0; i < firmware->count; i++) + /* + * For situations where the second RISC uses the same microcode + * as the first, the 'code_offset' and 'count' fields will be + * zero, so it's okay to add those. + */ + calc_size += sizeof(u32) * + be32_to_cpu(firmware->microcode[i].count); + + /* Validate the length */ + if (length != calc_size + sizeof(u32)) { + printf("Invalid length\n"); + return -EPERM; + } + + /* + * Validate the CRC. We would normally call crc32_no_comp(), but that + * function isn't available unless you turn on JFFS support. + */ + crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size)); + if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) { + printf("Firmware CRC is invalid\n"); + return -EIO; + } + + /* + * If the microcode calls for it, split the I-RAM. + */ + if (!firmware->split) { + out_be16(&qe_immr->cp.cercr, + in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR); + } + + if (firmware->soc.model) + printf("Firmware '%s' for %u V%u.%u\n", + firmware->id, be16_to_cpu(firmware->soc.model), + firmware->soc.major, firmware->soc.minor); + else + printf("Firmware '%s'\n", firmware->id); + + /* Loop through each microcode. */ + for (i = 0; i < firmware->count; i++) { + const struct qe_microcode *ucode = &firmware->microcode[i]; + + /* Upload a microcode if it's present */ + if (ucode->code_offset) + qe_upload_microcode(firmware, ucode); + + /* Program the traps for this processor */ + for (j = 0; j < 16; j++) { + u32 trap = be32_to_cpu(ucode->traps[j]); + + if (trap) + out_be32(&qe_immr->rsp[i].tibcr[j], trap); + } + + /* Enable traps */ + out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr)); + } + + return 0; +} +#endif + struct qe_firmware_info *qe_get_firmware_info(void) { return qe_firmware_uploaded ? &qe_firmware_info : NULL; diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index ebb7c5f..33878f8 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -285,4 +285,9 @@ void ft_qe_setup(void *blob); void qe_init(uint qe_base); void qe_reset(void); +#ifdef CONFIG_U_QE +void u_qe_init(void); +int u_qe_upload_firmware(const struct qe_firmware *firmware); +#endif + #endif /* __QE_H__ */ diff --git a/drivers/rtc/bfin_rtc.c b/drivers/rtc/bfin_rtc.c index 21a2189..4cf2d83 100644 --- a/drivers/rtc/bfin_rtc.c +++ b/drivers/rtc/bfin_rtc.c @@ -27,7 +27,7 @@ #define NUM_SECS_IN_DAY DAYS_TO_SECS(1) /* Enable the RTC prescaler enable register */ -static void rtc_init(void) +void rtc_init(void) { if (!(bfin_read_RTC_PREN() & 0x1)) bfin_write_RTC_PREN(0x1); diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index f7cf106..39e6041 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -14,6 +14,7 @@ #include <common.h> #include <command.h> #include <rtc.h> +#include <version.h> #if defined(__I386__) || defined(CONFIG_MALTA) #include <asm/io.h> @@ -23,6 +24,9 @@ #if defined(CONFIG_CMD_DATE) +/* Set this to 1 to clear the CMOS RAM */ +#define CLEAR_CMOS 0 + static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); @@ -41,7 +45,14 @@ static void rtc_write (uchar reg, uchar val); #define RTC_CONFIG_B 0x0B #define RTC_CONFIG_C 0x0C #define RTC_CONFIG_D 0x0D +#define RTC_REG_SIZE 0x80 + +#define RTC_CONFIG_A_REF_CLCK_32KHZ (1 << 5) +#define RTC_CONFIG_A_RATE_1024HZ 6 +#define RTC_CONFIG_B_24H (1 << 1) + +#define RTC_CONFIG_D_VALID_RAM_AND_TIME 0x80 /* ------------------------------------------------------------------------- */ @@ -128,25 +139,49 @@ void rtc_reset (void) */ static uchar rtc_read (uchar reg) { - return(in8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg)); + return in8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg); } static void rtc_write (uchar reg, uchar val) { - out8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg, val); + out8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg, val); } #else static uchar rtc_read (uchar reg) { out8(RTC_PORT_MC146818,reg); - return(in8(RTC_PORT_MC146818+1)); + return in8(RTC_PORT_MC146818 + 1); } static void rtc_write (uchar reg, uchar val) { out8(RTC_PORT_MC146818,reg); - out8(RTC_PORT_MC146818+1,val); + out8(RTC_PORT_MC146818+1, val); } #endif +void rtc_init(void) +{ +#if CLEAR_CMOS + int i; + + rtc_write(RTC_SECONDS_ALARM, 0); + rtc_write(RTC_MINUTES_ALARM, 0); + rtc_write(RTC_HOURS_ALARM, 0); + for (i = RTC_CONFIG_A; i < RTC_REG_SIZE; i++) + rtc_write(i, 0); + printf("RTC: zeroing CMOS RAM\n"); +#endif + + /* Setup the real time clock */ + rtc_write(RTC_CONFIG_B, RTC_CONFIG_B_24H); + /* Setup the frequency it operates at */ + rtc_write(RTC_CONFIG_A, RTC_CONFIG_A_REF_CLCK_32KHZ | + RTC_CONFIG_A_RATE_1024HZ); + /* Ensure all reserved bits are 0 in register D */ + rtc_write(RTC_CONFIG_D, RTC_CONFIG_D_VALID_RAM_AND_TIME); + + /* Clear any pending interrupts */ + rtc_read(RTC_CONFIG_C); +} #endif diff --git a/drivers/rtc/mvrtc.h b/drivers/rtc/mvrtc.h index ebddc12..424743c 100644 --- a/drivers/rtc/mvrtc.h +++ b/drivers/rtc/mvrtc.h @@ -13,7 +13,7 @@ #define _MVRTC_H_ #include <asm/arch/soc.h> -#include <compiler.h> +#include <linux/compiler.h> /* RTC registers */ struct mvrtc_registers { diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 8f0e348..4fe992b 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -7,11 +7,16 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> +#include <errno.h> #include <watchdog.h> #include <serial.h> #include <linux/compiler.h> #include <asm/io.h> +#ifdef CONFIG_DM_SERIAL +#include <asm/arch/atmel_serial.h> +#endif #include <asm/arch/clk.h> #include <asm/arch/hardware.h> @@ -19,9 +24,9 @@ DECLARE_GLOBAL_DATA_PTR; -static void atmel_serial_setbrg(void) +static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id, + int baudrate) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; unsigned long divisor; unsigned long usart_hz; @@ -30,15 +35,13 @@ static void atmel_serial_setbrg(void) * Baud Rate = -------------- * 16 * CD */ - usart_hz = get_usart_clk_rate(CONFIG_USART_ID); - divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate; + usart_hz = get_usart_clk_rate(id); + divisor = (usart_hz / 16 + baudrate / 2) / baudrate; writel(USART3_BF(CD, divisor), &usart->brgr); } -static int atmel_serial_init(void) +static void atmel_serial_init_internal(atmel_usart3_t *usart) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; - /* * Just in case: drain transmitter register * 1000us is enough for baudrate >= 9600 @@ -47,9 +50,10 @@ static int atmel_serial_init(void) __udelay(1000); writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr); +} - serial_setbrg(); - +static void atmel_serial_activate(atmel_usart3_t *usart) +{ writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) | USART3_BF(USCLKS, USART3_USCLKS_MCK) | USART3_BF(CHRL, USART3_CHRL_8) @@ -59,6 +63,22 @@ static int atmel_serial_init(void) writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr); /* 100us is enough for the new settings to be settled */ __udelay(100); +} + +#ifndef CONFIG_DM_SERIAL +static void atmel_serial_setbrg(void) +{ + atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE, + CONFIG_USART_ID, gd->baudrate); +} + +static int atmel_serial_init(void) +{ + atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + + atmel_serial_init_internal(usart); + serial_setbrg(); + atmel_serial_activate(usart); return 0; } @@ -109,3 +129,81 @@ __weak struct serial_device *default_serial_console(void) { return &atmel_serial_drv; } +#endif + +#ifdef CONFIG_DM_SERIAL + +struct atmel_serial_priv { + atmel_usart3_t *usart; +}; + +int atmel_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct atmel_serial_priv *priv = dev_get_priv(dev); + + atmel_serial_setbrg_internal(priv->usart, 0 /* ignored */, baudrate); + atmel_serial_activate(priv->usart); + + return 0; +} + +static int atmel_serial_getc(struct udevice *dev) +{ + struct atmel_serial_priv *priv = dev_get_priv(dev); + + if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY))) + return -EAGAIN; + + return readl(&priv->usart->rhr); +} + +static int atmel_serial_putc(struct udevice *dev, const char ch) +{ + struct atmel_serial_priv *priv = dev_get_priv(dev); + + if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY))) + return -EAGAIN; + + writel(ch, &priv->usart->thr); + + return 0; +} + +static int atmel_serial_pending(struct udevice *dev, bool input) +{ + struct atmel_serial_priv *priv = dev_get_priv(dev); + uint32_t csr = readl(&priv->usart->csr); + + if (input) + return csr & USART3_BIT(RXRDY) ? 1 : 0; + else + return csr & USART3_BIT(TXEMPTY) ? 0 : 1; +} + +static const struct dm_serial_ops atmel_serial_ops = { + .putc = atmel_serial_putc, + .pending = atmel_serial_pending, + .getc = atmel_serial_getc, + .setbrg = atmel_serial_setbrg, +}; + +static int atmel_serial_probe(struct udevice *dev) +{ + struct atmel_serial_platdata *plat = dev->platdata; + struct atmel_serial_priv *priv = dev_get_priv(dev); + + priv->usart = (atmel_usart3_t *)plat->base_addr; + atmel_serial_init_internal(priv->usart); + + return 0; +} + +U_BOOT_DRIVER(serial_atmel) = { + .name = "serial_atmel", + .id = UCLASS_SERIAL, + .probe = atmel_serial_probe, + .ops = &atmel_serial_ops, + .flags = DM_FLAG_PRE_RELOC, + .priv_auto_alloc_size = sizeof(struct atmel_serial_priv), +}; +#endif diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 8f05191..af5beba 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -132,11 +132,12 @@ static void NS16550_setbrg(NS16550_t com_port, int baud_divisor) void NS16550_init(NS16550_t com_port, int baud_divisor) { -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX)) +#if (defined(CONFIG_SPL_BUILD) && \ + (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX))) /* - * On some OMAP3 devices when UART3 is configured for boot mode before - * SPL starts only THRE bit is set. We have to empty the transmitter - * before initialization starts. + * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode + * before SPL starts only THRE bit is set. We have to empty the + * transmitter before initialization starts. */ if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE)) == UART_LSR_THRE) { diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 71f1a5c..d1b5777 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -6,6 +6,7 @@ #include <common.h> #include <dm.h> +#include <environment.h> #include <errno.h> #include <fdtdec.h> #include <os.h> @@ -19,8 +20,10 @@ DECLARE_GLOBAL_DATA_PTR; -/* The currently-selected console serial device */ -struct udevice *cur_dev __attribute__ ((section(".data"))); +/* + * Table with supported baudrates (defined in config_xyz.h) + */ +static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; #ifndef CONFIG_SYS_MALLOC_F_LEN #error "Serial is required before relocation - define CONFIG_SYS_MALLOC_F_LEN to make this work" @@ -28,25 +31,30 @@ struct udevice *cur_dev __attribute__ ((section(".data"))); static void serial_find_console_or_panic(void) { + struct udevice *dev; + #ifdef CONFIG_OF_CONTROL int node; /* Check for a chosen console */ node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path"); if (node < 0) - node = fdtdec_get_alias_node(gd->fdt_blob, "console"); - if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &cur_dev)) + node = fdt_path_offset(gd->fdt_blob, "console"); + if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &dev)) { + gd->cur_serial_dev = dev; return; + } /* * If the console is not marked to be bound before relocation, bind * it anyway. */ if (node > 0 && - !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &cur_dev)) { - if (!device_probe(cur_dev)) + !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &dev)) { + if (!device_probe(dev)) { + gd->cur_serial_dev = dev; return; - cur_dev = NULL; + } } #endif /* @@ -61,11 +69,12 @@ static void serial_find_console_or_panic(void) #else #define INDEX 0 #endif - if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &cur_dev) && - uclass_get_device(UCLASS_SERIAL, INDEX, &cur_dev) && - (uclass_first_device(UCLASS_SERIAL, &cur_dev) || !cur_dev)) + if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &dev) && + uclass_get_device(UCLASS_SERIAL, INDEX, &dev) && + (uclass_first_device(UCLASS_SERIAL, &dev) || !dev)) panic("No serial driver found"); #undef INDEX + gd->cur_serial_dev = dev; } /* Called prior to relocation */ @@ -127,40 +136,42 @@ static int _serial_tstc(struct udevice *dev) void serial_putc(char ch) { - _serial_putc(cur_dev, ch); + _serial_putc(gd->cur_serial_dev, ch); } void serial_puts(const char *str) { - _serial_puts(cur_dev, str); + _serial_puts(gd->cur_serial_dev, str); } int serial_getc(void) { - return _serial_getc(cur_dev); + return _serial_getc(gd->cur_serial_dev); } int serial_tstc(void) { - return _serial_tstc(cur_dev); + return _serial_tstc(gd->cur_serial_dev); } void serial_setbrg(void) { - struct dm_serial_ops *ops = serial_get_ops(cur_dev); + struct dm_serial_ops *ops = serial_get_ops(gd->cur_serial_dev); if (ops->setbrg) - ops->setbrg(cur_dev, gd->baudrate); + ops->setbrg(gd->cur_serial_dev, gd->baudrate); } void serial_stdio_init(void) { } +#ifdef CONFIG_DM_STDIO static void serial_stub_putc(struct stdio_dev *sdev, const char ch) { _serial_putc(sdev->priv, ch); } +#endif void serial_stub_puts(struct stdio_dev *sdev, const char *str) { @@ -177,11 +188,74 @@ int serial_stub_tstc(struct stdio_dev *sdev) return _serial_tstc(sdev->priv); } +/** + * on_baudrate() - Update the actual baudrate when the env var changes + * + * This will check for a valid baudrate and only apply it if valid. + */ +static int on_baudrate(const char *name, const char *value, enum env_op op, + int flags) +{ + int i; + int baudrate; + + switch (op) { + case env_op_create: + case env_op_overwrite: + /* + * Switch to new baudrate if new baudrate is supported + */ + baudrate = simple_strtoul(value, NULL, 10); + + /* Not actually changing */ + if (gd->baudrate == baudrate) + return 0; + + for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) { + if (baudrate == baudrate_table[i]) + break; + } + if (i == ARRAY_SIZE(baudrate_table)) { + if ((flags & H_FORCE) == 0) + printf("## Baudrate %d bps not supported\n", + baudrate); + return 1; + } + if ((flags & H_INTERACTIVE) != 0) { + printf("## Switch baudrate to %d bps and press ENTER ...\n", + baudrate); + udelay(50000); + } + + gd->baudrate = baudrate; + + serial_setbrg(); + + udelay(50000); + + if ((flags & H_INTERACTIVE) != 0) + while (1) { + if (getc() == '\r') + break; + } + + return 0; + case env_op_delete: + printf("## Baudrate may not be deleted\n"); + return 1; + default: + return 0; + } +} +U_BOOT_ENV_CALLBACK(baudrate, on_baudrate); + static int serial_post_probe(struct udevice *dev) { - struct stdio_dev sdev; struct dm_serial_ops *ops = serial_get_ops(dev); +#ifdef CONFIG_DM_STDIO struct serial_dev_priv *upriv = dev->uclass_priv; + struct stdio_dev sdev; +#endif int ret; /* Set the baud rate */ @@ -191,9 +265,9 @@ static int serial_post_probe(struct udevice *dev) return ret; } +#ifdef CONFIG_DM_STDIO if (!(gd->flags & GD_FLG_RELOC)) return 0; - memset(&sdev, '\0', sizeof(sdev)); strncpy(sdev.name, dev->name, sizeof(sdev.name)); @@ -204,7 +278,7 @@ static int serial_post_probe(struct udevice *dev) sdev.getc = serial_stub_getc; sdev.tstc = serial_stub_tstc; stdio_register_dev(&sdev, &upriv->sdev); - +#endif return 0; } diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 38dda91..e1bf496 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -72,30 +72,39 @@ static int pl01x_tstc(struct pl01x_regs *regs) static int pl01x_generic_serial_init(struct pl01x_regs *regs, enum pl01x_type type) { - unsigned int lcr; - + switch (type) { + case TYPE_PL010: + /* disable everything */ + writel(0, ®s->pl010_cr); + break; + case TYPE_PL011: #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT - if (type == TYPE_PL011) { /* Empty RX fifo if necessary */ if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) { while (!(readl(®s->fr) & UART_PL01x_FR_RXFE)) readl(®s->dr); } - } #endif + /* disable everything */ + writel(0, ®s->pl011_cr); + break; + default: + return -EINVAL; + } - /* First, disable everything */ - writel(0, ®s->pl010_cr); + return 0; +} - /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ +static int set_line_control(struct pl01x_regs *regs) +{ + unsigned int lcr; + /* + * Internal update of baud rate register require line + * control register write + */ lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN; - writel(lcr, ®s->pl011_lcrh); - - switch (type) { - case TYPE_PL010: - break; - case TYPE_PL011: { #ifdef CONFIG_PL011_SERIAL_RLCR + { int i; /* @@ -107,15 +116,9 @@ static int pl01x_generic_serial_init(struct pl01x_regs *regs, writel(lcr, ®s->fr); writel(lcr, ®s->pl011_rlcr); - /* lcrh needs to be set again for change to be effective */ - writel(lcr, ®s->pl011_lcrh); -#endif - break; - } - default: - return -EINVAL; } - +#endif + writel(lcr, ®s->pl011_lcrh); return 0; } @@ -175,6 +178,7 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, writel(divider, ®s->pl011_ibrd); writel(fraction, ®s->pl011_fbrd); + set_line_control(regs); /* Finally, enable the UART */ writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr); @@ -201,7 +205,7 @@ static void pl01x_serial_init_baud(int baudrate) base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX]; pl01x_generic_serial_init(base_regs, pl01x_type); - pl01x_generic_setbrg(base_regs, TYPE_PL010, clock, baudrate); + pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate); } /* diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 53406e5..ef88c8f 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -433,7 +433,7 @@ static inline void sci_##name##_out(struct uart_port *port,\ SCI_OUT(sci_size, sci_offset, value);\ } -#if defined(CONFIG_SH3) || \ +#if defined(CONFIG_CPU_SH3) || \ defined(CONFIG_ARCH_SH7367) || \ defined(CONFIG_ARCH_SH7377) || \ defined(CONFIG_ARCH_SH7372) || \ diff --git a/drivers/serial/serial_tegra.c b/drivers/serial/serial_tegra.c index 7eb70e1..b9227f0 100644 --- a/drivers/serial/serial_tegra.c +++ b/drivers/serial/serial_tegra.c @@ -9,6 +9,7 @@ #include <ns16550.h> #include <serial.h> +#ifdef CONFIG_OF_CONTROL static const struct udevice_id tegra_serial_ids[] = { { .compatible = "nvidia,tegra20-uart" }, { } @@ -26,13 +27,28 @@ static int tegra_serial_ofdata_to_platdata(struct udevice *dev) return 0; } +#else +struct ns16550_platdata tegra_serial = { + .base = CONFIG_SYS_NS16550_COM1, + .reg_shift = 2, + .clock = V_NS16550_CLK, +}; + +U_BOOT_DEVICE(ns16550_serial) = { + "serial_tegra20", &tegra_serial +}; +#endif + U_BOOT_DRIVER(serial_ns16550) = { .name = "serial_tegra20", .id = UCLASS_SERIAL, +#ifdef CONFIG_OF_CONTROL .of_match = tegra_serial_ids, .ofdata_to_platdata = tegra_serial_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), +#endif .priv_auto_alloc_size = sizeof(struct NS16550), .probe = ns16550_serial_probe, .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index 6046efb..e8a1608 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -11,6 +11,7 @@ #include <dm/device.h> #include <dm/platform_data/serial-uniphier.h> #include <serial.h> +#include <fdtdec.h> #define UART_REG(x) \ u8 x; \ @@ -113,19 +114,21 @@ static int uniphier_serial_remove(struct udevice *dev) } #ifdef CONFIG_OF_CONTROL -static const struct udevice_id uniphier_uart_of_match = { - { .compatible = "panasonic,uniphier-uart"}, +static const struct udevice_id uniphier_uart_of_match[] = { + { .compatible = "panasonic,uniphier-uart" }, {}, }; static int uniphier_serial_ofdata_to_platdata(struct udevice *dev) { - /* - * TODO: Masahiro Yamada (yamada.m@jp.panasonic.com) - * - * Implement conversion code from DTB to platform data - * when supporting CONFIG_OF_CONTROL on UniPhir platform. - */ + struct uniphier_serial_platform_data *plat = dev_get_platdata(dev); + DECLARE_GLOBAL_DATA_PTR; + + plat->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); + plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", 0); + + return 0; } #endif diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c index 7fb0b92..75f0ec3 100644 --- a/drivers/serial/usbtty.c +++ b/drivers/serial/usbtty.c @@ -882,7 +882,7 @@ static int write_buffer (circbuf_t * buf) space_avail = current_urb->buffer_length - current_urb->actual_length; - popnum = min(space_avail, buf->size); + popnum = min(space_avail, (int)buf->size); if (popnum == 0) break; diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h index d240945..1538a23 100644 --- a/drivers/spi/atmel_spi.h +++ b/drivers/spi/atmel_spi.h @@ -94,3 +94,7 @@ static inline struct atmel_spi_slave *to_atmel_spi(struct spi_slave *slave) readl(as->regs + ATMEL_SPI_##reg) #define spi_writel(as, reg, value) \ writel(value, as->regs + ATMEL_SPI_##reg) + +#if !defined(CONFIG_SYS_SPI_WRITE_TOUT) +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +#endif diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index ae0fe58..375dc07 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -273,7 +273,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, spi_cs_deactivate(slave); return 0; } - buf_len = 2 * cmd_len + min(data_len, max_tran_len); + buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len); len = cmd_len + data_len; rx_offset = cmd_len; buffer = (unsigned char *)malloc(buf_len); @@ -306,7 +306,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, if (data_in) din = buffer + rx_offset; dout = buffer; - tran_len = min(data_len , max_tran_len); + tran_len = min(data_len, (size_t)max_tran_len); num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4); num_bytes = (tran_len + cmd_len) % 4; fsl->data_len = tran_len + cmd_len; diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 23f2ba6..0881599 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -315,7 +315,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, tmp = reg_read(®s->rxdata); data = cpu_to_be32(tmp); debug("SPI Rx: 0x%x 0x%x\n", tmp, data); - cnt = min(nbytes, sizeof(data)); + cnt = min_t(u32, nbytes, sizeof(data)); if (din) { memcpy(din, &data, cnt); din += cnt; diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 13c6b77..7a57bce 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -57,7 +57,7 @@ int spi_claim_bus(struct spi_slave *slave) speed = slave->max_hz; if (spi->max_hz) { if (speed) - speed = min(speed, spi->max_hz); + speed = min(speed, (int)spi->max_hz); else speed = spi->max_hz; } @@ -115,16 +115,7 @@ int spi_chip_select(struct udevice *dev) return slave ? slave->cs : -ENOENT; } -/** - * spi_find_chip_select() - Find the slave attached to chip select - * - * @bus: SPI bus to search - * @cs: Chip select to look for - * @devp: Returns the slave device if found - * @return 0 if found, -ENODEV on error - */ -static int spi_find_chip_select(struct udevice *bus, int cs, - struct udevice **devp) +int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp) { struct udevice *dev; @@ -197,27 +188,6 @@ int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info) return -ENODEV; } -int spi_bind_device(struct udevice *bus, int cs, const char *drv_name, - const char *dev_name, struct udevice **devp) -{ - struct driver *drv; - int ret; - - drv = lists_driver_lookup_name(drv_name); - if (!drv) { - printf("Cannot find driver '%s'\n", drv_name); - return -ENOENT; - } - ret = device_bind(bus, drv, dev_name, NULL, -1, devp); - if (ret) { - printf("Cannot create device named '%s' (err=%d)\n", - dev_name, ret); - return ret; - } - - return 0; -} - int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp, struct udevice **devp) { @@ -264,7 +234,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, if (ret == -ENODEV && drv_name) { debug("%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n", __func__, dev_name, busnum, cs, drv_name); - ret = spi_bind_device(bus, cs, drv_name, dev_name, &dev); + ret = device_bind_driver(bus, drv_name, dev_name, &dev); if (ret) return ret; created = true; diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index fd7fea8..857b604 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -102,7 +102,7 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) struct spi_slave *slave = &qslave->slave; u32 memval = 0; -#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) slave->memory_map = (void *)MMAP_START_ADDR_DRA; #else slave->memory_map = (void *)MMAP_START_ADDR_AM43x; @@ -244,7 +244,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, uint status; int timeout; -#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) int val; #endif @@ -254,7 +254,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, /* Setup mmap flags */ if (flags & SPI_XFER_MMAP) { writel(MM_SWITCH, &qslave->base->memswitch); -#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) val = readl(CORE_CTRL_IO); val |= MEM_CS; writel(val, CORE_CTRL_IO); @@ -262,7 +262,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, return 0; } else if (flags & SPI_XFER_MMAP_END) { writel(~MM_SWITCH, &qslave->base->memswitch); -#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) val = readl(CORE_CTRL_IO); val &= MEM_CS_UNSELECT; writel(val, CORE_CTRL_IO); diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile new file mode 100644 index 0000000..6d4cacd --- /dev/null +++ b/drivers/thermal/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# Author: Nitin Garg <nitin.garg@freescale.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o +obj-$(CONFIG_IMX6_THERMAL) += imx_thermal.o diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c new file mode 100644 index 0000000..0bd9cfd --- /dev/null +++ b/drivers/thermal/imx_thermal.c @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2014 Freescale Semiconductor, Inc. + * Author: Nitin Garg <nitin.garg@freescale.com> + * Ye Li <Ye.Li@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <div64.h> +#include <fuse.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <dm.h> +#include <errno.h> +#include <malloc.h> +#include <thermal.h> +#include <imx_thermal.h> + +#define TEMPERATURE_MIN -40 +#define TEMPERATURE_HOT 80 +#define TEMPERATURE_MAX 125 +#define FACTOR0 10000000 +#define FACTOR1 15976 +#define FACTOR2 4297157 +#define MEASURE_FREQ 327 + +#define TEMPSENSE0_TEMP_CNT_SHIFT 8 +#define TEMPSENSE0_TEMP_CNT_MASK (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT) +#define TEMPSENSE0_FINISHED (1 << 2) +#define TEMPSENSE0_MEASURE_TEMP (1 << 1) +#define TEMPSENSE0_POWER_DOWN (1 << 0) +#define MISC0_REFTOP_SELBIASOFF (1 << 3) +#define TEMPSENSE1_MEASURE_FREQ 0xffff + +static int read_cpu_temperature(struct udevice *dev) +{ + int temperature; + unsigned int reg, n_meas; + const struct imx_thermal_plat *pdata = dev_get_platdata(dev); + struct anatop_regs *anatop = (struct anatop_regs *)pdata->regs; + unsigned int *priv = dev_get_priv(dev); + u32 fuse = *priv; + int t1, n1; + u32 c1, c2; + u64 temp64; + + /* + * Sensor data layout: + * [31:20] - sensor value @ 25C + * We use universal formula now and only need sensor value @ 25C + * slope = 0.4297157 - (0.0015976 * 25C fuse) + */ + n1 = fuse >> 20; + t1 = 25; /* t1 always 25C */ + + /* + * Derived from linear interpolation: + * slope = 0.4297157 - (0.0015976 * 25C fuse) + * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0 + * (Nmeas - n1) / (Tmeas - t1) = slope + * We want to reduce this down to the minimum computation necessary + * for each temperature read. Also, we want Tmeas in millicelsius + * and we don't want to lose precision from integer division. So... + * Tmeas = (Nmeas - n1) / slope + t1 + * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1 + * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1 + * Let constant c1 = (-1000 / slope) + * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1 + * Let constant c2 = n1 *c1 + 1000 * t1 + * milli_Tmeas = c2 - Nmeas * c1 + */ + temp64 = FACTOR0; + temp64 *= 1000; + do_div(temp64, FACTOR1 * n1 - FACTOR2); + c1 = temp64; + c2 = n1 * c1 + 1000 * t1; + + /* + * now we only use single measure, every time we read + * the temperature, we will power on/down anadig thermal + * module + */ + writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr); + writel(MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); + + /* setup measure freq */ + reg = readl(&anatop->tempsense1); + reg &= ~TEMPSENSE1_MEASURE_FREQ; + reg |= MEASURE_FREQ; + writel(reg, &anatop->tempsense1); + + /* start the measurement process */ + writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr); + writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); + writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set); + + /* make sure that the latest temp is valid */ + while ((readl(&anatop->tempsense0) & + TEMPSENSE0_FINISHED) == 0) + udelay(10000); + + /* read temperature count */ + reg = readl(&anatop->tempsense0); + n_meas = (reg & TEMPSENSE0_TEMP_CNT_MASK) + >> TEMPSENSE0_TEMP_CNT_SHIFT; + writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); + + /* milli_Tmeas = c2 - Nmeas * c1 */ + temperature = (c2 - n_meas * c1)/1000; + + /* power down anatop thermal sensor */ + writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set); + writel(MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr); + + return temperature; +} + +int imx_thermal_get_temp(struct udevice *dev, int *temp) +{ + int cpu_tmp = 0; + + cpu_tmp = read_cpu_temperature(dev); + while (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) { + if (cpu_tmp >= TEMPERATURE_HOT) { + printf("CPU Temperature is %d C, too hot to boot, waiting...\n", + cpu_tmp); + udelay(5000000); + cpu_tmp = read_cpu_temperature(dev); + } else { + break; + } + } + + *temp = cpu_tmp; + + return 0; +} + +static const struct dm_thermal_ops imx_thermal_ops = { + .get_temp = imx_thermal_get_temp, +}; + +static int imx_thermal_probe(struct udevice *dev) +{ + unsigned int fuse = ~0; + + const struct imx_thermal_plat *pdata = dev_get_platdata(dev); + unsigned int *priv = dev_get_priv(dev); + + /* Read Temperature calibration data fuse */ + fuse_read(pdata->fuse_bank, pdata->fuse_word, &fuse); + + /* Check for valid fuse */ + if (fuse == 0 || fuse == ~0) { + printf("CPU: Thermal invalid data, fuse: 0x%x\n", fuse); + return -EPERM; + } + + *priv = fuse; + + enable_thermal_clk(); + + return 0; +} + +U_BOOT_DRIVER(imx_thermal) = { + .name = "imx_thermal", + .id = UCLASS_THERMAL, + .ops = &imx_thermal_ops, + .probe = imx_thermal_probe, + .priv_auto_alloc_size = sizeof(unsigned int), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/thermal/thermal-uclass.c b/drivers/thermal/thermal-uclass.c new file mode 100644 index 0000000..3bee1a7 --- /dev/null +++ b/drivers/thermal/thermal-uclass.c @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2014 Freescale Semiconductor, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <thermal.h> +#include <errno.h> +#include <fdtdec.h> +#include <malloc.h> +#include <asm/io.h> +#include <linux/list.h> + + +int thermal_get_temp(struct udevice *dev, int *temp) +{ + const struct dm_thermal_ops *ops = device_get_ops(dev); + + if (!ops->get_temp) + return -ENOSYS; + + return ops->get_temp(dev, temp); +} + +UCLASS_DRIVER(thermal) = { + .id = UCLASS_THERMAL, + .name = "thermal", +}; diff --git a/drivers/tpm/tpm.c b/drivers/tpm/tpm.c index bc0f964..31761ec 100644 --- a/drivers/tpm/tpm.c +++ b/drivers/tpm/tpm.c @@ -34,7 +34,7 @@ #include <config.h> #include <common.h> -#include <compiler.h> +#include <linux/compiler.h> #include <fdtdec.h> #include <i2c.h> #include <tpm.h> diff --git a/drivers/tpm/tpm_tis_i2c.c b/drivers/tpm/tpm_tis_i2c.c index 2dd8501..c1bbed4 100644 --- a/drivers/tpm/tpm_tis_i2c.c +++ b/drivers/tpm/tpm_tis_i2c.c @@ -38,7 +38,7 @@ #include <common.h> #include <fdtdec.h> -#include <compiler.h> +#include <linux/compiler.h> #include <i2c.h> #include <tpm.h> #include <asm-generic/errno.h> diff --git a/drivers/tpm/tpm_tis_lpc.c b/drivers/tpm/tpm_tis_lpc.c index eecf18c..d09f8ce 100644 --- a/drivers/tpm/tpm_tis_lpc.c +++ b/drivers/tpm/tpm_tis_lpc.c @@ -274,7 +274,7 @@ static u32 tis_senddata(const u8 * const data, u32 len) * changes to zero exactly after the last byte is fed into the * FIFO. */ - count = min(burst, len - offset - 1); + count = min((u32)burst, len - offset - 1); while (count--) tpm_write_byte(data[offset++], &lpc_tpm_dev[locality].data); diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index 7bd2562..a4c5606 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -743,8 +743,8 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) if (!gadget_is_dualspeed(gadget)) break; device_qual(cdev); - value = min(w_length, - sizeof(struct usb_qualifier_descriptor)); + value = min_t(int, w_length, + sizeof(struct usb_qualifier_descriptor)); break; case USB_DT_OTHER_SPEED_CONFIG: if (!gadget_is_dualspeed(gadget)) diff --git a/drivers/usb/gadget/designware_udc.c b/drivers/usb/gadget/designware_udc.c index 3559400..0db7a3b 100644 --- a/drivers/usb/gadget/designware_udc.c +++ b/drivers/usb/gadget/designware_udc.c @@ -269,8 +269,8 @@ static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d", urb->buffer, urb->buffer_length, urb->actual_length); - last = min(urb->actual_length - endpoint->sent, - endpoint->tx_packetSize); + last = min_t(u32, urb->actual_length - endpoint->sent, + endpoint->tx_packetSize); if (last) { u8 *cp = urb->buffer + endpoint->sent; diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c index efd5c7f..9423555 100644 --- a/drivers/usb/gadget/pxa27x_udc.c +++ b/drivers/usb/gadget/pxa27x_udc.c @@ -65,7 +65,8 @@ static int udc_write_urb(struct usb_endpoint_instance *endpoint) if (!urb || !urb->actual_length) return -1; - n = min(urb->actual_length - endpoint->sent, endpoint->tx_packetSize); + n = min_t(unsigned int, urb->actual_length - endpoint->sent, + endpoint->tx_packetSize); if (n <= 0) return -1; diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c index 9c54b46..7e7a2c2 100644 --- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c @@ -97,8 +97,8 @@ static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req) u32 ep_num = ep_index(ep); buf = req->req.buf + req->req.actual; - length = min(req->req.length - req->req.actual, - ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket); + length = min_t(u32, req->req.length - req->req.actual, + ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket); ep->len = length; ep->dma_buf = buf; diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 2a5bbf5..e8142ac 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -503,23 +503,23 @@ static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, case 0: switch (wValue & 0xff00) { case 0x0100: /* device descriptor */ - len = min3(txlen, sizeof(root_hub_dev_des), wLength); + len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength); memcpy(buffer, root_hub_dev_des, len); break; case 0x0200: /* configuration descriptor */ - len = min3(txlen, sizeof(root_hub_config_des), wLength); + len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength); memcpy(buffer, root_hub_config_des, len); break; case 0x0300: /* string descriptors */ switch (wValue & 0xff) { case 0x00: - len = min3(txlen, sizeof(root_hub_str_index0), - wLength); + len = min3(txlen, (int)sizeof(root_hub_str_index0), + (int)wLength); memcpy(buffer, root_hub_str_index0, len); break; case 0x01: - len = min3(txlen, sizeof(root_hub_str_index1), - wLength); + len = min3(txlen, (int)sizeof(root_hub_str_index1), + (int)wLength); memcpy(buffer, root_hub_str_index1, len); break; } @@ -556,7 +556,7 @@ static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, data[10] = data[9]; } - len = min3(txlen, data[0], wLength); + len = min3(txlen, (int)data[0], (int)wLength); memcpy(buffer, data, len); break; default: diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index edd91a8..6fdbf57 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -85,15 +85,10 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos) } #endif -/* Setup the EHCI host controller. */ -static void setup_usb_phy(struct exynos_usb_phy *usb) +static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb) { u32 hsic_ctrl; - set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN); - - set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN); - clrbits_le32(&usb->usbphyctrl0, HOST_CTRL0_FSEL_MASK | HOST_CTRL0_COMMONON_N | @@ -150,8 +145,34 @@ static void setup_usb_phy(struct exynos_usb_phy *usb) EHCICTRL_ENAINCR16); } -/* Reset the EHCI host controller. */ -static void reset_usb_phy(struct exynos_usb_phy *usb) +static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb) +{ + writel(CLK_24MHZ, &usb->usbphyclk); + + clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 | + PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 | + PHYPWR_NORMAL_MASK_PHY0)); + + setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST)); + udelay(10); + clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST)); +} + +static void setup_usb_phy(struct exynos_usb_phy *usb) +{ + set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN); + + set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN); + + if (cpu_is_exynos5()) + exynos5_setup_usb_phy(usb); + else if (cpu_is_exynos4()) + if (proid_is_exynos4412()) + exynos4412_setup_usb_phy((struct exynos4412_usb_phy *) + usb); +} + +static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb) { u32 hsic_ctrl; @@ -171,6 +192,24 @@ static void reset_usb_phy(struct exynos_usb_phy *usb) setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); +} + +static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb) +{ + setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 | + PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 | + PHYPWR_NORMAL_MASK_PHY0)); +} + +/* Reset the EHCI host controller. */ +static void reset_usb_phy(struct exynos_usb_phy *usb) +{ + if (cpu_is_exynos5()) + exynos5_reset_usb_phy(usb); + else if (cpu_is_exynos4()) + if (proid_is_exynos4412()) + exynos4412_reset_usb_phy((struct exynos4412_usb_phy *) + usb); set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE); } diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 45062e6..5d4288d 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -14,10 +14,15 @@ #include <asm/io.h> #include <usb/ehci-fsl.h> #include <hwconfig.h> -#include <asm/fsl_errata.h> +#include <fsl_usb.h> +#include <fdt_support.h> #include "ehci.h" +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + static void set_txfifothresh(struct usb_ehci *, u32); /* Check USB PHY clock valid */ @@ -130,8 +135,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, in_le32(&ehci->usbmode); - if (SVR_SOC_VER(get_svr()) == SVR_T4240 && - IS_SVR_REV(get_svr(), 2, 0)) + if (has_erratum_a007798()) set_txfifothresh(ehci, TXFIFOTHRESH); return 0; @@ -159,3 +163,184 @@ static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh) cmd |= TXFIFO_THRESH(txfifo_thresh); ehci_writel(&ehci->txfilltuning, cmd); } + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) +static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, + const char *phy_type, int start_offset) +{ + const char *compat_dr = "fsl-usb2-dr"; + const char *compat_mph = "fsl-usb2-mph"; + const char *prop_mode = "dr_mode"; + const char *prop_type = "phy_type"; + const char *node_type = NULL; + int node_offset; + int err; + + node_offset = fdt_node_offset_by_compatible(blob, + start_offset, compat_mph); + if (node_offset < 0) { + node_offset = fdt_node_offset_by_compatible(blob, + start_offset, + compat_dr); + if (node_offset < 0) { + printf("WARNING: could not find compatible node: %s", + fdt_strerror(node_offset)); + return -1; + } + node_type = compat_dr; + } else { + node_type = compat_mph; + } + + if (mode) { + err = fdt_setprop(blob, node_offset, prop_mode, mode, + strlen(mode) + 1); + if (err < 0) + printf("WARNING: could not set %s for %s: %s.\n", + prop_mode, node_type, fdt_strerror(err)); + } + + if (phy_type) { + err = fdt_setprop(blob, node_offset, prop_type, phy_type, + strlen(phy_type) + 1); + if (err < 0) + printf("WARNING: could not set %s for %s: %s.\n", + prop_type, node_type, fdt_strerror(err)); + } + + return node_offset; +} + +static const char *fdt_usb_get_node_type(void *blob, int start_offset, + int *node_offset) +{ + const char *compat_dr = "fsl-usb2-dr"; + const char *compat_mph = "fsl-usb2-mph"; + const char *node_type = NULL; + + *node_offset = fdt_node_offset_by_compatible(blob, start_offset, + compat_mph); + if (*node_offset < 0) { + *node_offset = fdt_node_offset_by_compatible(blob, + start_offset, + compat_dr); + if (*node_offset < 0) { + printf("ERROR: could not find compatible node: %s\n", + fdt_strerror(*node_offset)); + } else { + node_type = compat_dr; + } + } else { + node_type = compat_mph; + } + + return node_type; +} + +static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum, + int start_offset) +{ + int node_offset, err; + const char *node_type = NULL; + + node_type = fdt_usb_get_node_type(blob, start_offset, &node_offset); + if (!node_type) + return -1; + + err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0); + if (err < 0) { + printf("ERROR: could not set %s for %s: %s.\n", + prop_erratum, node_type, fdt_strerror(err)); + } + + return node_offset; +} + +void fdt_fixup_dr_usb(void *blob, bd_t *bd) +{ + static const char * const modes[] = { "host", "peripheral", "otg" }; + static const char * const phys[] = { "ulpi", "utmi" }; + int usb_erratum_a006261_off = -1; + int usb_erratum_a007075_off = -1; + int usb_erratum_a007792_off = -1; + int usb_mode_off = -1; + int usb_phy_off = -1; + char str[5]; + int i, j; + + for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) { + const char *dr_mode_type = NULL; + const char *dr_phy_type = NULL; + int mode_idx = -1, phy_idx = -1; + + snprintf(str, 5, "%s%d", "usb", i); + if (hwconfig(str)) { + for (j = 0; j < ARRAY_SIZE(modes); j++) { + if (hwconfig_subarg_cmp(str, "dr_mode", + modes[j])) { + mode_idx = j; + break; + } + } + + for (j = 0; j < ARRAY_SIZE(phys); j++) { + if (hwconfig_subarg_cmp(str, "phy_type", + phys[j])) { + phy_idx = j; + break; + } + } + + if (mode_idx < 0 && phy_idx < 0) { + printf("WARNING: invalid phy or mode\n"); + return; + } + + if (mode_idx > -1) + dr_mode_type = modes[mode_idx]; + + if (phy_idx > -1) + dr_phy_type = phys[phy_idx]; + } + + usb_mode_off = fdt_fixup_usb_mode_phy_type(blob, + dr_mode_type, NULL, + usb_mode_off); + + if (usb_mode_off < 0) + return; + + usb_phy_off = fdt_fixup_usb_mode_phy_type(blob, + NULL, dr_phy_type, + usb_phy_off); + + if (usb_phy_off < 0) + return; + + if (has_erratum_a006261()) { + usb_erratum_a006261_off = fdt_fixup_usb_erratum + (blob, + "fsl,usb-erratum-a006261", + usb_erratum_a006261_off); + if (usb_erratum_a006261_off < 0) + return; + } + if (has_erratum_a007075()) { + usb_erratum_a007075_off = fdt_fixup_usb_erratum + (blob, + "fsl,usb-erratum-a007075", + usb_erratum_a007075_off); + if (usb_erratum_a007075_off < 0) + return; + } + if (has_erratum_a007792()) { + usb_erratum_a007792_off = fdt_fixup_usb_erratum + (blob, + "fsl,usb-erratum-a007792", + usb_erratum_a007792_off); + if (usb_erratum_a007792_off < 0) + return; + } + } +} +#endif diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 54e948a..bc76066 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -910,7 +910,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, } mdelay(1); - len = min3(srclen, le16_to_cpu(req->length), length); + len = min3(srclen, (int)le16_to_cpu(req->length), length); if (srcptr != NULL && len > 0) memcpy(buffer, srcptr, len); else diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c index 77f6c9d..32a4375 100644 --- a/drivers/usb/host/ehci-uniphier.c +++ b/drivers/usb/host/ehci-uniphier.c @@ -6,10 +6,43 @@ */ #include <common.h> +#include <linux/err.h> #include <usb.h> #include <asm/arch/ehci-uniphier.h> #include "ehci.h" +#ifdef CONFIG_OF_CONTROL +#include <fdtdec.h> +DECLARE_GLOBAL_DATA_PTR; + +#define FDT gd->fdt_blob +#define COMPAT "panasonic,uniphier-ehci" + +static int get_uniphier_ehci_base(int index, struct ehci_hccr **base) +{ + int offset; + + for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT); + offset >= 0; + offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) { + if (index == 0) { + *base = (struct ehci_hccr *) + fdtdec_get_addr(FDT, offset, "reg"); + return 0; + } + index--; + } + + return -ENODEV; /* not found */ +} +#else +static int get_uniphier_ehci_base(int index, struct ehci_hccr **base) +{ + *base = (struct ehci_hccr *)uniphier_ehci_platdata[index].base; + return 0; +} +#endif + /* * Create the appropriate control structures to manage * a new EHCI host controller. @@ -17,12 +50,15 @@ int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { + int ret; struct ehci_hccr *cr; struct ehci_hcor *or; uniphier_ehci_reset(index, 0); - cr = (struct ehci_hccr *)(uniphier_ehci_platdata[index].base); + ret = get_uniphier_ehci_base(index, &cr); + if (ret < 0) + return ret; or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase)); *hccr = cr; diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c index 46e4cee..0556f32 100644 --- a/drivers/usb/host/isp116x-hcd.c +++ b/drivers/usb/host/isp116x-hcd.c @@ -103,12 +103,6 @@ static int rh_devnum; /* address of Root Hub endpoint */ /* ------------------------------------------------------------------------- */ -#define ALIGN(x,a) (((x)+(a)-1UL)&~((a)-1UL)) -#define min_t(type,x,y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; }) - -/* ------------------------------------------------------------------------- */ - static int isp116x_reset(struct isp116x *isp116x); /* --- Debugging functions ------------------------------------------------- */ diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index dc0a4e3..97a7ede 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -47,7 +47,7 @@ #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */ #endif -#if defined(CONFIG_ARM920T) || \ +#if defined(CONFIG_CPU_ARM920T) || \ defined(CONFIG_S3C24X0) || \ defined(CONFIG_440EP) || \ defined(CONFIG_PCI_OHCI) || \ @@ -65,9 +65,6 @@ #define OHCI_CONTROL_INIT \ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE -#define min_t(type, x, y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - #ifdef CONFIG_PCI_OHCI static struct pci_device_id ohci_pci_ids[] = { {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ diff --git a/drivers/usb/host/ohci-s3c24xx.c b/drivers/usb/host/ohci-s3c24xx.c index 3c659c6..8bb2275 100644 --- a/drivers/usb/host/ohci-s3c24xx.c +++ b/drivers/usb/host/ohci-s3c24xx.c @@ -35,9 +35,6 @@ #define OHCI_CONTROL_INIT \ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE -#define min_t(type, x, y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; }) - #undef DEBUG #ifdef DEBUG #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index 5114544..6f33456 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -550,9 +550,6 @@ static int check_usb_device_connecting(struct r8a66597 *r8a66597) return -1; /* fail */ } -/* based on usb_ohci.c */ -#define min_t(type, x, y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; }) /*-------------------------------------------------------------------------* * Virtual Root Hub *-------------------------------------------------------------------------*/ diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 19c3ec6..b5aade9 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -511,7 +511,7 @@ static void record_transfer_result(struct usb_device *udev, union xhci_trb *event, int length) { udev->act_len = min(length, length - - EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len))); + (int)EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len))); switch (GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len))) { case COMP_SUCCESS: diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 59dc096..87f2972 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -829,7 +829,7 @@ static int xhci_submit_root(struct usb_device *udev, unsigned long pipe, debug("scrlen = %d\n req->length = %d\n", srclen, le16_to_cpu(req->length)); - len = min(srclen, le16_to_cpu(req->length)); + len = min(srclen, (int)le16_to_cpu(req->length)); if (srcptr != NULL && len > 0) memcpy(buffer, srcptr, len); diff --git a/drivers/usb/musb/musb_hcd.h b/drivers/usb/musb/musb_hcd.h index 02b9adc..0c8e75d 100644 --- a/drivers/usb/musb/musb_hcd.h +++ b/drivers/usb/musb/musb_hcd.h @@ -37,9 +37,6 @@ extern unsigned char new[]; ((readb(&musbr->power) & MUSB_POWER_HSMODE) \ >> MUSB_POWER_HSMODE_SHIFT) -#define min_t(type, x, y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; }) - /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ /* destination of request */ diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c index f78d532..52a3664 100644 --- a/drivers/usb/phy/omap_usb_phy.c +++ b/drivers/usb/phy/omap_usb_phy.c @@ -118,7 +118,6 @@ void usb_phy_power(int on) void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs) { omap_usb_dpll_lock(phy_regs); - usb3_phy_partial_powerup(phy_regs); /* * Give enough time for the PHY to partially power-up before @@ -126,7 +125,6 @@ void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs) * team. */ mdelay(100); - usb3_phy_power(1); } static void omap_enable_usb3_phy(struct omap_xhci *omap) diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 14a6781..00b563f 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -39,8 +39,10 @@ obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o obj-$(CONFIG_VIDEO_SED13806) += sed13806.o obj-$(CONFIG_VIDEO_SM501) += sm501.o obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o +obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o obj-$(CONFIG_VIDEO_TEGRA) += tegra.o obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o +obj-$(CONFIG_VIDEO_X86) += x86_fb.o obj-$(CONFIG_FORMIKE) += formike.o obj-$(CONFIG_AM335X_LCD) += am335x-fb.o obj-$(CONFIG_VIDEO_PARADE) += parade.o diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c index 38d2eb1..5748951 100644 --- a/drivers/video/ati_radeon_fb.c +++ b/drivers/video/ati_radeon_fb.c @@ -19,6 +19,7 @@ #include <common.h> #include <command.h> +#include <bios_emul.h> #include <pci.h> #include <asm/processor.h> #include <asm/errno.h> @@ -39,11 +40,6 @@ #define DPRINT(x...) do{}while(0) #endif -#ifndef min_t -#define min_t(type,x,y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) -#endif - #define MAX_MAPPED_VRAM (2048*2048*4) #define MIN_MAPPED_VRAM (1024*768*1) @@ -549,7 +545,6 @@ void radeon_setmode_9200(int vesa_idx, int bpp) } #include "../bios_emulator/include/biosemu.h" -extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp); int radeon_probe(struct radeonfb_info *rinfo) { diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 6aa50cb..a653bb4 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -1160,10 +1160,19 @@ static void video_putc(struct stdio_dev *dev, const char c) static void video_puts(struct stdio_dev *dev, const char *s) { + int flush = cfb_do_flush_cache; int count = strlen(s); + /* temporarily disable cache flush */ + cfb_do_flush_cache = 0; + while (count--) video_putc(dev, *s++); + + if (flush) { + cfb_do_flush_cache = flush; + flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); + } } /* @@ -1532,14 +1541,14 @@ int video_display_bitmap(ulong bmp_image, int x, int y) #ifdef CONFIG_SPLASH_SCREEN_ALIGN if (x == BMP_ALIGN_CENTER) - x = max(0, (VIDEO_VISIBLE_COLS - width) / 2); + x = max(0, (int)(VIDEO_VISIBLE_COLS - width) / 2); else if (x < 0) - x = max(0, VIDEO_VISIBLE_COLS - width + x + 1); + x = max(0, (int)(VIDEO_VISIBLE_COLS - width + x + 1)); if (y == BMP_ALIGN_CENTER) - y = max(0, (VIDEO_VISIBLE_ROWS - height) / 2); + y = max(0, (int)(VIDEO_VISIBLE_ROWS - height) / 2); else if (y < 0) - y = max(0, VIDEO_VISIBLE_ROWS - height + y + 1); + y = max(0, (int)(VIDEO_VISIBLE_ROWS - height + y + 1)); #endif /* CONFIG_SPLASH_SCREEN_ALIGN */ /* @@ -1865,14 +1874,14 @@ static void plot_logo_or_black(void *screen, int width, int x, int y, int black) #ifdef CONFIG_SPLASH_SCREEN_ALIGN if (x == BMP_ALIGN_CENTER) - x = max(0, (VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH) / 2); + x = max(0, (int)(VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH) / 2); else if (x < 0) - x = max(0, VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH + x + 1); + x = max(0, (int)(VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH + x + 1)); if (y == BMP_ALIGN_CENTER) - y = max(0, (VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT) / 2); + y = max(0, (int)(VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT) / 2); else if (y < 0) - y = max(0, VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT + y + 1); + y = max(0, (int)(VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT + y + 1)); #endif /* CONFIG_SPLASH_SCREEN_ALIGN */ dest = (unsigned char *)screen + (y * width + x) * VIDEO_PIXEL_SIZE; @@ -2019,7 +2028,7 @@ static void *video_logo(void) * we need to adjust the logo height */ if (video_logo_ypos == BMP_ALIGN_CENTER) - video_logo_height += max(0, (VIDEO_VISIBLE_ROWS - \ + video_logo_height += max(0, (int)(VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT) / 2); else if (video_logo_ypos > 0) video_logo_height += video_logo_ypos; diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c new file mode 100644 index 0000000..d241397 --- /dev/null +++ b/drivers/video/sunxi_display.c @@ -0,0 +1,451 @@ +/* + * Display driver for Allwinner SoCs. + * + * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be> + * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#include <asm/arch/clock.h> +#include <asm/arch/display.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <fdtdec.h> +#include <fdt_support.h> +#include <linux/fb.h> +#include <video_fb.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct sunxi_display { + GraphicDevice graphic_device; + bool enabled; +} sunxi_display; + +static int sunxi_hdmi_hpd_detect(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_hdmi_reg * const hdmi = + (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; + + /* Set pll3 to 300MHz */ + clock_set_pll3(300000000); + + /* Set hdmi parent to pll3 */ + clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK, + CCM_HDMI_CTRL_PLL3); + + /* Set ahb gating to pass */ +#ifdef CONFIG_MACH_SUN6I + setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); +#endif + setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); + + /* Clock on */ + setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); + + writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl); + writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0); + + udelay(1000); + + if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT) + return 1; + + /* No need to keep these running */ + clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE); + clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); + clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); +#ifdef CONFIG_MACH_SUN6I + clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); +#endif + clock_set_pll3(0); + + return 0; +} + +/* + * This is the entity that mixes and matches the different layers and inputs. + * Allwinner calls it the back-end, but i like composer better. + */ +static void sunxi_composer_init(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_de_be_reg * const de_be = + (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE; + int i; + +#ifdef CONFIG_MACH_SUN6I + /* Reset off */ + setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0); +#endif + + /* Clocks on */ + setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0); + setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0); + clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000); + + /* Engine bug, clear registers after reset */ + for (i = 0x0800; i < 0x1000; i += 4) + writel(0, SUNXI_DE_BE0_BASE + i); + + setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE); +} + +static void sunxi_composer_mode_set(struct fb_videomode *mode, + unsigned int address) +{ + struct sunxi_de_be_reg * const de_be = + (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE; + + writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres), + &de_be->disp_size); + writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres), + &de_be->layer0_size); + writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride); + writel(address << 3, &de_be->layer0_addr_low32b); + writel(address >> 29, &de_be->layer0_addr_high4b); + writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl); + + setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE); +} + +/* + * LCDC, what allwinner calls a CRTC, so timing controller and serializer. + */ +static void sunxi_lcdc_pll_set(int dotclock, int *clk_div, int *clk_double) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + int value, n, m, diff; + int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF; + int best_double = 0; + + /* + * Find the lowest divider resulting in a matching clock, if there + * is no match, pick the closest lower clock, as monitors tend to + * not sync to higher frequencies. + */ + for (m = 15; m > 0; m--) { + n = (m * dotclock) / 3000; + + if ((n >= 9) && (n <= 127)) { + value = (3000 * n) / m; + diff = dotclock - value; + if (diff < best_diff) { + best_diff = diff; + best_m = m; + best_n = n; + best_double = 0; + } + } + + /* These are just duplicates */ + if (!(m & 1)) + continue; + + n = (m * dotclock) / 6000; + if ((n >= 9) && (n <= 127)) { + value = (6000 * n) / m; + diff = dotclock - value; + if (diff < best_diff) { + best_diff = diff; + best_m = m; + best_n = n; + best_double = 1; + } + } + } + + debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n", + dotclock, (best_double + 1) * 3000 * best_n / best_m, + best_double + 1, best_n, best_m); + + clock_set_pll3(best_n * 3000000); + + writel(CCM_LCD_CH1_CTRL_GATE | + (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : CCM_LCD_CH1_CTRL_PLL3) | + CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg); + + *clk_div = best_m; + *clk_double = best_double; +} + +static void sunxi_lcdc_init(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_lcdc_reg * const lcdc = + (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; + + /* Reset off */ +#ifdef CONFIG_MACH_SUN6I + setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); +#else + setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST); +#endif + + /* Clock on */ + setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0); + + /* Init lcdc */ + writel(0, &lcdc->ctrl); /* Disable tcon */ + writel(0, &lcdc->int0); /* Disable all interrupts */ + + /* Disable tcon0 dot clock */ + clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE); + + /* Set all io lines to tristate */ + writel(0xffffffff, &lcdc->tcon0_io_tristate); + writel(0xffffffff, &lcdc->tcon1_io_tristate); +} + +static void sunxi_lcdc_mode_set(struct fb_videomode *mode, + int *clk_div, int *clk_double) +{ + struct sunxi_lcdc_reg * const lcdc = + (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; + int bp, total; + + /* Use tcon1 */ + clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK, + SUNXI_LCDC_CTRL_IO_MAP_TCON1); + + /* Enabled, 0x1e start delay */ + writel(SUNXI_LCDC_TCON1_CTRL_ENABLE | + SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl); + + writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres), + &lcdc->tcon1_timing_source); + writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres), + &lcdc->tcon1_timing_scale); + writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres), + &lcdc->tcon1_timing_out); + + bp = mode->hsync_len + mode->left_margin; + total = mode->xres + mode->right_margin + bp; + writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) | + SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h); + + bp = mode->vsync_len + mode->upper_margin; + total = mode->yres + mode->lower_margin + bp; + writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) | + SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v); + + writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len), + &lcdc->tcon1_timing_sync); + + sunxi_lcdc_pll_set(mode->pixclock, clk_div, clk_double); +} + +#ifdef CONFIG_MACH_SUN6I +static void sunxi_drc_init(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* On sun6i the drc must be clocked even when in pass-through mode */ + setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0); + clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000); +} +#endif + +static void sunxi_hdmi_mode_set(struct fb_videomode *mode, + int clk_div, int clk_double) +{ + struct sunxi_hdmi_reg * const hdmi = + (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; + int x, y; + + /* Write clear interrupt status bits */ + writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq); + + /* Init various registers, select pll3 as clock source */ + writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity); + writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0); + writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1); + writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl); + writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0); + + /* Setup clk div and doubler */ + clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK, + SUNXI_HDMI_PLL_CTRL_DIV(clk_div)); + if (!clk_double) + setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE); + + /* Setup timing registers */ + writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres), + &hdmi->video_size); + + x = mode->hsync_len + mode->left_margin; + y = mode->vsync_len + mode->upper_margin; + writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp); + + x = mode->right_margin; + y = mode->lower_margin; + writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp); + + x = mode->hsync_len; + y = mode->vsync_len; + writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw); + + if (mode->sync & FB_SYNC_HOR_HIGH_ACT) + setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR); + + if (mode->sync & FB_SYNC_VERT_HIGH_ACT) + setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER); +} + +static void sunxi_engines_init(void) +{ + sunxi_composer_init(); + sunxi_lcdc_init(); +#ifdef CONFIG_MACH_SUN6I + sunxi_drc_init(); +#endif +} + +static void sunxi_mode_set(struct fb_videomode *mode, unsigned int address) +{ + struct sunxi_de_be_reg * const de_be = + (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE; + struct sunxi_lcdc_reg * const lcdc = + (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; + struct sunxi_hdmi_reg * const hdmi = + (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE; + int clk_div, clk_double; + int retries = 3; + +retry: + clrbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE); + clrbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE); + clrbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START); + + sunxi_composer_mode_set(mode, address); + sunxi_lcdc_mode_set(mode, &clk_div, &clk_double); + sunxi_hdmi_mode_set(mode, clk_div, clk_double); + + setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS); + setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START); + + udelay(1000000 / mode->refresh + 500); + + setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE); + + udelay(1000000 / mode->refresh + 500); + + setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE); + + udelay(1000000 / mode->refresh + 500); + + /* + * Sometimes the display pipeline does not sync up properly, if + * this happens the hdmi fifo underrun or overrun bits are set. + */ + if (readl(&hdmi->irq) & + (SUNXI_HDMI_IRQ_STATUS_FIFO_UF | SUNXI_HDMI_IRQ_STATUS_FIFO_OF)) { + if (retries--) + goto retry; + printf("HDMI fifo under or overrun\n"); + } +} + +void *video_hw_init(void) +{ + static GraphicDevice *graphic_device = &sunxi_display.graphic_device; + /* + * Vesa standard 1024x768@60 + * 65.0 1024 1048 1184 1344 768 771 777 806 -hsync -vsync + */ + struct fb_videomode mode = { + .name = "1024x768", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 65000, + .left_margin = 160, + .right_margin = 24, + .upper_margin = 29, + .lower_margin = 3, + .hsync_len = 136, + .vsync_len = 6, + .sync = 0, + .vmode = 0, + .flag = 0, + }; + int ret; + + memset(&sunxi_display, 0, sizeof(struct sunxi_display)); + + printf("Reserved %dkB of RAM for Framebuffer.\n", + CONFIG_SUNXI_FB_SIZE >> 10); + gd->fb_base = gd->ram_top; + + ret = sunxi_hdmi_hpd_detect(); + if (!ret) + return NULL; + + printf("HDMI connected.\n"); + sunxi_display.enabled = true; + + printf("Setting up a %s console.\n", mode.name); + sunxi_engines_init(); + sunxi_mode_set(&mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE); + + /* + * These are the only members of this structure that are used. All the + * others are driver specific. There is nothing to decribe pitch or + * stride, but we are lucky with our hw. + */ + graphic_device->frameAdrs = gd->fb_base; + graphic_device->gdfIndex = GDF_32BIT_X888RGB; + graphic_device->gdfBytesPP = 4; + graphic_device->winSizeX = mode.xres; + graphic_device->winSizeY = mode.yres; + + return graphic_device; +} + +/* + * Simplefb support. + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB) +int sunxi_simplefb_setup(void *blob) +{ + static GraphicDevice *graphic_device = &sunxi_display.graphic_device; + int offset, ret; + + if (!sunxi_display.enabled) + return 0; + + /* Find a framebuffer node, with pipeline == "de_be0-lcd0-hdmi" */ + offset = fdt_node_offset_by_compatible(blob, -1, + "allwinner,simple-framebuffer"); + while (offset >= 0) { + ret = fdt_find_string(blob, offset, "allwinner,pipeline", + "de_be0-lcd0-hdmi"); + if (ret == 0) + break; + offset = fdt_node_offset_by_compatible(blob, offset, + "allwinner,simple-framebuffer"); + } + if (offset < 0) { + eprintf("Cannot setup simplefb: node not found\n"); + return 0; /* Keep older kernels working */ + } + + ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base, + graphic_device->winSizeX, graphic_device->winSizeY, + graphic_device->winSizeX * graphic_device->gdfBytesPP, + "x8r8g8b8"); + if (ret) + eprintf("Cannot setup simplefb: Error setting properties\n"); + + return ret; +} +#endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */ diff --git a/drivers/video/x86_fb.c b/drivers/video/x86_fb.c new file mode 100644 index 0000000..8743a8c --- /dev/null +++ b/drivers/video/x86_fb.c @@ -0,0 +1,37 @@ +/* + * + * Vesa frame buffer driver for x86 + * + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <video_fb.h> +#include <vbe.h> +#include "videomodes.h" + +/* + * The Graphic Device + */ +GraphicDevice ctfb; + +void *video_hw_init(void) +{ + GraphicDevice *gdev = &ctfb; + int bits_per_pixel; + + printf("Video: "); + if (vbe_get_video_info(gdev)) { + printf("No video mode configured\n"); + return NULL; + } + + bits_per_pixel = gdev->gdfBytesPP * 8; + sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY, + bits_per_pixel); + printf("%s\n", gdev->modeIdent); + + return (void *)gdev; +} diff --git a/fs/ext4/dev.c b/fs/ext4/dev.c index e0b513a..c77c02c 100644 --- a/fs/ext4/dev.c +++ b/fs/ext4/dev.c @@ -73,6 +73,7 @@ int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf) debug(" <" LBAFU ", %d, %d>\n", sector, byte_offset, byte_len); if (byte_offset != 0) { + int readlen; /* read first part which isn't aligned with start of sector */ if (ext4fs_block_dev_desc-> block_read(ext4fs_block_dev_desc->dev, @@ -81,13 +82,11 @@ int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf) printf(" ** ext2fs_devread() read error **\n"); return 0; } - memcpy(buf, sec_buf + byte_offset, - min(ext4fs_block_dev_desc->blksz - - byte_offset, byte_len)); - buf += min(ext4fs_block_dev_desc->blksz - - byte_offset, byte_len); - byte_len -= min(ext4fs_block_dev_desc->blksz - - byte_offset, byte_len); + readlen = min((int)ext4fs_block_dev_desc->blksz - byte_offset, + byte_len); + memcpy(buf, sec_buf + byte_offset, readlen); + buf += readlen; + byte_len -= readlen; sector++; } diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index cccc06a..cab5465 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -1892,6 +1892,7 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, { unsigned int fpos = 0; int status; + loff_t actread; struct ext2fs_node *diro = (struct ext2fs_node *) dir; #ifdef DEBUG @@ -1909,8 +1910,8 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, status = ext4fs_read_file(diro, fpos, sizeof(struct ext2_dirent), - (char *) &dirent); - if (status < 1) + (char *)&dirent, &actread); + if (status < 0) return 0; if (dirent.namelen != 0) { @@ -1921,8 +1922,9 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, status = ext4fs_read_file(diro, fpos + sizeof(struct ext2_dirent), - dirent.namelen, filename); - if (status < 1) + dirent.namelen, filename, + &actread); + if (status < 0) return 0; fdiro = zalloc(sizeof(struct ext2fs_node)); @@ -2004,8 +2006,8 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, printf("< ? > "); break; } - printf("%10d %s\n", - __le32_to_cpu(fdiro->inode.size), + printf("%10u %s\n", + __le32_to_cpu(fdiro->inode.size), filename); } free(fdiro); @@ -2020,6 +2022,7 @@ static char *ext4fs_read_symlink(struct ext2fs_node *node) char *symlink; struct ext2fs_node *diro = node; int status; + loff_t actread; if (!diro->inode_read) { status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode); @@ -2036,7 +2039,7 @@ static char *ext4fs_read_symlink(struct ext2fs_node *node) } else { status = ext4fs_read_file(diro, 0, __le32_to_cpu(diro->inode.size), - symlink); + symlink, &actread); if (status == 0) { free(symlink); return 0; @@ -2170,11 +2173,10 @@ int ext4fs_find_file(const char *path, struct ext2fs_node *rootnode, return 1; } -int ext4fs_open(const char *filename) +int ext4fs_open(const char *filename, loff_t *len) { struct ext2fs_node *fdiro = NULL; int status; - int len; if (ext4fs_root == NULL) return -1; @@ -2191,10 +2193,10 @@ int ext4fs_open(const char *filename) if (status == 0) goto fail; } - len = __le32_to_cpu(fdiro->inode.size); + *len = __le32_to_cpu(fdiro->inode.size); ext4fs_file = fdiro; - return len; + return 0; fail: ext4fs_free_node(fdiro, &ext4fs_root->diropen); diff --git a/fs/ext4/ext4_common.h b/fs/ext4/ext4_common.h index 5fa1719..48fd2ac 100644 --- a/fs/ext4/ext4_common.h +++ b/fs/ext4/ext4_common.h @@ -50,8 +50,8 @@ static inline void *zalloc(size_t size) int ext4fs_read_inode(struct ext2_data *data, int ino, struct ext2_inode *inode); -int ext4fs_read_file(struct ext2fs_node *node, int pos, - unsigned int len, char *buf); +int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, loff_t len, + char *buf, loff_t *actread); int ext4fs_find_file(const char *path, struct ext2fs_node *rootnode, struct ext2fs_node **foundnode, int expecttype); int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c index 648a596..f7c52cc 100644 --- a/fs/ext4/ext4_write.c +++ b/fs/ext4/ext4_write.c @@ -975,3 +975,35 @@ fail: return -1; } + +int ext4_write_file(const char *filename, void *buf, loff_t offset, + loff_t len, loff_t *actwrite) +{ + int ret; + + if (offset != 0) { + printf("** Cannot support non-zero offset **\n"); + return -1; + } + + /* mount the filesystem */ + if (!ext4fs_mount(0)) { + printf("** Error Bad ext4 partition **\n"); + goto fail; + } + + ret = ext4fs_write(filename, buf, len); + + if (ret) { + printf("** Error ext4fs_write() **\n"); + goto fail; + } + ext4fs_close(); + + return 0; + +fail: + ext4fs_close(); + + return -1; +} diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index cbdc220..258b937 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -25,6 +25,7 @@ #include <ext_common.h> #include <ext4fs.h> #include "ext4_common.h" +#include <div64.h> int ext4fs_symlinknest; struct ext_filesystem ext_fs; @@ -45,8 +46,8 @@ void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot) * Optimized read file API : collects and defers contiguous sector * reads into one potentially more efficient larger sequential read action */ -int ext4fs_read_file(struct ext2fs_node *node, int pos, - unsigned int len, char *buf) +int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, + loff_t len, char *buf, loff_t *actread) { struct ext_filesystem *fs = get_fs(); int i; @@ -67,11 +68,11 @@ int ext4fs_read_file(struct ext2fs_node *node, int pos, if (len > filesize) len = filesize; - blockcnt = ((len + pos) + blocksize - 1) / blocksize; + blockcnt = lldiv(((len + pos) + blocksize - 1), blocksize); - for (i = pos / blocksize; i < blockcnt; i++) { + for (i = lldiv(pos, blocksize); i < blockcnt; i++) { lbaint_t blknr; - int blockoff = pos % blocksize; + int blockoff = pos - (blocksize * i); int blockend = blocksize; int skipfirst = 0; blknr = read_allocated_block(&(node->inode), i); @@ -82,7 +83,7 @@ int ext4fs_read_file(struct ext2fs_node *node, int pos, /* Last block. */ if (i == blockcnt - 1) { - blockend = (len + pos) % blocksize; + blockend = (len + pos) - (blocksize * i); /* The last portion is exactly blocksize. */ if (!blockend) @@ -90,7 +91,7 @@ int ext4fs_read_file(struct ext2fs_node *node, int pos, } /* First block. */ - if (i == pos / blocksize) { + if (i == lldiv(pos, blocksize)) { skipfirst = blockoff; blockend -= skipfirst; } @@ -150,7 +151,8 @@ int ext4fs_read_file(struct ext2fs_node *node, int pos, previous_block_number = -1; } - return len; + *actread = len; + return 0; } int ext4fs_ls(const char *dirname) @@ -176,23 +178,24 @@ int ext4fs_ls(const char *dirname) int ext4fs_exists(const char *filename) { - int file_len; + loff_t file_len; + int ret; - file_len = ext4fs_open(filename); - return file_len >= 0; + ret = ext4fs_open(filename, &file_len); + return ret == 0; } -int ext4fs_size(const char *filename) +int ext4fs_size(const char *filename, loff_t *size) { - return ext4fs_open(filename); + return ext4fs_open(filename, size); } -int ext4fs_read(char *buf, unsigned len) +int ext4fs_read(char *buf, loff_t len, loff_t *actread) { if (ext4fs_root == NULL || ext4fs_file == NULL) return 0; - return ext4fs_read_file(ext4fs_file, 0, len, buf); + return ext4fs_read_file(ext4fs_file, 0, len, buf, actread); } int ext4fs_probe(block_dev_desc_t *fs_dev_desc, @@ -208,18 +211,19 @@ int ext4fs_probe(block_dev_desc_t *fs_dev_desc, return 0; } -int ext4_read_file(const char *filename, void *buf, int offset, int len) +int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *len_read) { - int file_len; - int len_read; + loff_t file_len; + int ret; if (offset != 0) { printf("** Cannot support non-zero offset **\n"); return -1; } - file_len = ext4fs_open(filename); - if (file_len < 0) { + ret = ext4fs_open(filename, &file_len); + if (ret < 0) { printf("** File not found %s **\n", filename); return -1; } @@ -227,7 +231,20 @@ int ext4_read_file(const char *filename, void *buf, int offset, int len) if (len == 0) len = file_len; - len_read = ext4fs_read(buf, len); + return ext4fs_read(buf, len, len_read); +} - return len_read; +int ext4fs_uuid(char *uuid_str) +{ + if (ext4fs_root == NULL) + return -1; + +#ifdef CONFIG_LIB_UUID + uuid_bin_to_str((unsigned char *)ext4fs_root->sblock.unique_id, + uuid_str, UUID_STR_FORMAT_STD); + + return 0; +#else + return -ENOSYS; +#endif } diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 561921f..04a51db 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -317,32 +317,32 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) /* * Read at most 'maxsize' bytes from 'pos' in the file associated with 'dentptr' * into 'buffer'. - * Return the number of bytes read or -1 on fatal errors. + * Update the number of bytes read in *gotsize or return -1 on fatal errors. */ __u8 get_contents_vfatname_block[MAX_CLUSTSIZE] __aligned(ARCH_DMA_MINALIGN); -static long -get_contents(fsdata *mydata, dir_entry *dentptr, unsigned long pos, - __u8 *buffer, unsigned long maxsize) +static int get_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos, + __u8 *buffer, loff_t maxsize, loff_t *gotsize) { - unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0; + loff_t filesize = FAT2CPU32(dentptr->size); unsigned int bytesperclust = mydata->clust_size * mydata->sect_size; __u32 curclust = START(dentptr); __u32 endclust, newclust; - unsigned long actsize; + loff_t actsize; - debug("Filesize: %ld bytes\n", filesize); + *gotsize = 0; + debug("Filesize: %llu bytes\n", filesize); if (pos >= filesize) { - debug("Read position past EOF: %lu\n", pos); - return gotsize; + debug("Read position past EOF: %llu\n", pos); + return 0; } if (maxsize > 0 && filesize > pos + maxsize) filesize = pos + maxsize; - debug("%ld bytes\n", filesize); + debug("%llu bytes\n", filesize); actsize = bytesperclust; @@ -352,7 +352,7 @@ get_contents(fsdata *mydata, dir_entry *dentptr, unsigned long pos, if (CHECK_CLUST(curclust, mydata->fatsize)) { debug("curclust: 0x%x\n", curclust); debug("Invalid FAT entry\n"); - return gotsize; + return 0; } actsize += bytesperclust; } @@ -364,7 +364,7 @@ get_contents(fsdata *mydata, dir_entry *dentptr, unsigned long pos, /* align to beginning of next cluster if any */ if (pos) { - actsize = min(filesize, bytesperclust); + actsize = min(filesize, (loff_t)bytesperclust); if (get_cluster(mydata, curclust, get_contents_vfatname_block, (int)actsize) != 0) { printf("Error reading cluster\n"); @@ -373,16 +373,16 @@ get_contents(fsdata *mydata, dir_entry *dentptr, unsigned long pos, filesize -= actsize; actsize -= pos; memcpy(buffer, get_contents_vfatname_block + pos, actsize); - gotsize += actsize; + *gotsize += actsize; if (!filesize) - return gotsize; + return 0; buffer += actsize; curclust = get_fatent(mydata, curclust); if (CHECK_CLUST(curclust, mydata->fatsize)) { debug("curclust: 0x%x\n", curclust); debug("Invalid FAT entry\n"); - return gotsize; + return 0; } } @@ -398,7 +398,7 @@ get_contents(fsdata *mydata, dir_entry *dentptr, unsigned long pos, if (CHECK_CLUST(newclust, mydata->fatsize)) { debug("curclust: 0x%x\n", newclust); debug("Invalid FAT entry\n"); - return gotsize; + return 0; } endclust = newclust; actsize += bytesperclust; @@ -410,14 +410,14 @@ get_contents(fsdata *mydata, dir_entry *dentptr, unsigned long pos, printf("Error reading cluster\n"); return -1; } - gotsize += actsize; - return gotsize; + *gotsize += actsize; + return 0; getit: if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) { printf("Error reading cluster\n"); return -1; } - gotsize += (int)actsize; + *gotsize += (int)actsize; filesize -= actsize; buffer += actsize; @@ -425,7 +425,7 @@ getit: if (CHECK_CLUST(curclust, mydata->fatsize)) { debug("curclust: 0x%x\n", curclust); printf("Invalid FAT entry\n"); - return gotsize; + return 0; } actsize = bytesperclust; endclust = curclust; @@ -633,8 +633,8 @@ static dir_entry *get_dentfromdir(fsdata *mydata, int startsect, } if (doit) { if (dirc == ' ') { - printf(" %8ld %s%c\n", - (long)FAT2CPU32(dentptr->size), + printf(" %8u %s%c\n", + FAT2CPU32(dentptr->size), l_name, dirc); } else { @@ -690,8 +690,8 @@ static dir_entry *get_dentfromdir(fsdata *mydata, int startsect, if (doit) { if (dirc == ' ') { - printf(" %8ld %s%c\n", - (long)FAT2CPU32(dentptr->size), + printf(" %8u %s%c\n", + FAT2CPU32(dentptr->size), s_name, dirc); } else { printf(" %s%c\n", @@ -806,9 +806,8 @@ exit: __u8 do_fat_read_at_block[MAX_CLUSTSIZE] __aligned(ARCH_DMA_MINALIGN); -long -do_fat_read_at(const char *filename, unsigned long pos, void *buffer, - unsigned long maxsize, int dols, int dogetsize) +int do_fat_read_at(const char *filename, loff_t pos, void *buffer, + loff_t maxsize, int dols, int dogetsize, loff_t *size) { char fnamecopy[2048]; boot_sector bs; @@ -821,7 +820,7 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, __u32 cursect; int idx, isdir = 0; int files = 0, dirs = 0; - long ret = -1; + int ret = -1; int firsttime; __u32 root_cluster = 0; int rootdir_size = 0; @@ -974,8 +973,8 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, } if (doit) { if (dirc == ' ') { - printf(" %8ld %s%c\n", - (long)FAT2CPU32(dentptr->size), + printf(" %8u %s%c\n", + FAT2CPU32(dentptr->size), l_name, dirc); } else { @@ -1032,8 +1031,8 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, } if (doit) { if (dirc == ' ') { - printf(" %8ld %s%c\n", - (long)FAT2CPU32(dentptr->size), + printf(" %8u %s%c\n", + FAT2CPU32(dentptr->size), s_name, dirc); } else { printf(" %s%c\n", @@ -1102,7 +1101,7 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, if (dols == LS_ROOT) { printf("\n%d file(s), %d dir(s)\n\n", files, dirs); - ret = 0; + *size = 0; } goto exit; } @@ -1141,7 +1140,7 @@ rootdir_done: if (get_dentfromdir(mydata, startsect, subname, dentptr, isdir ? 0 : dols) == NULL) { if (dols && !isdir) - ret = 0; + *size = 0; goto exit; } @@ -1152,21 +1151,23 @@ rootdir_done: subname = nextname; } - if (dogetsize) - ret = FAT2CPU32(dentptr->size); - else - ret = get_contents(mydata, dentptr, pos, buffer, maxsize); - debug("Size: %d, got: %ld\n", FAT2CPU32(dentptr->size), ret); + if (dogetsize) { + *size = FAT2CPU32(dentptr->size); + ret = 0; + } else { + ret = get_contents(mydata, dentptr, pos, buffer, maxsize, size); + } + debug("Size: %u, got: %llu\n", FAT2CPU32(dentptr->size), *size); exit: free(mydata->fatbuf); return ret; } -long -do_fat_read(const char *filename, void *buffer, unsigned long maxsize, int dols) +int do_fat_read(const char *filename, void *buffer, loff_t maxsize, int dols, + loff_t *actread) { - return do_fat_read_at(filename, 0, buffer, maxsize, dols, 0); + return do_fat_read_at(filename, 0, buffer, maxsize, dols, 0, actread); } int file_fat_detectfs(void) @@ -1233,44 +1234,55 @@ int file_fat_detectfs(void) int file_fat_ls(const char *dir) { - return do_fat_read(dir, NULL, 0, LS_YES); + loff_t size; + + return do_fat_read(dir, NULL, 0, LS_YES, &size); } int fat_exists(const char *filename) { - int sz; - sz = do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1); - return sz >= 0; + int ret; + loff_t size; + + ret = do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1, &size); + return ret == 0; } -int fat_size(const char *filename) +int fat_size(const char *filename, loff_t *size) { - return do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1); + return do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1, size); } -long file_fat_read_at(const char *filename, unsigned long pos, void *buffer, - unsigned long maxsize) +int file_fat_read_at(const char *filename, loff_t pos, void *buffer, + loff_t maxsize, loff_t *actread) { printf("reading %s\n", filename); - return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO, 0); + return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO, 0, + actread); } -long file_fat_read(const char *filename, void *buffer, unsigned long maxsize) +int file_fat_read(const char *filename, void *buffer, int maxsize) { - return file_fat_read_at(filename, 0, buffer, maxsize); + loff_t actread; + int ret; + + ret = file_fat_read_at(filename, 0, buffer, maxsize, &actread); + if (ret) + return ret; + else + return actread; } -int fat_read_file(const char *filename, void *buf, int offset, int len) +int fat_read_file(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread) { - int len_read; + int ret; - len_read = file_fat_read_at(filename, offset, buf, len); - if (len_read == -1) { + ret = file_fat_read_at(filename, offset, buf, len, actread); + if (ret) printf("** Unable to read file %s **\n", filename); - return -1; - } - return len_read; + return ret; } void fat_close(void) diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index 24ed5d3..98b88ad 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -13,6 +13,8 @@ #include <asm/byteorder.h> #include <part.h> #include <linux/ctype.h> +#include <div64.h> +#include <linux/math64.h> #include "fat.c" static void uppercase(char *str, int len) @@ -660,24 +662,26 @@ static int clear_fatent(fsdata *mydata, __u32 entry) /* * Write at most 'maxsize' bytes from 'buffer' into * the file associated with 'dentptr' - * Return the number of bytes read or -1 on fatal errors. + * Update the number of bytes written in *gotsize and return 0 + * or return -1 on fatal errors. */ static int set_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, - unsigned long maxsize) + loff_t maxsize, loff_t *gotsize) { - unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0; + loff_t filesize = FAT2CPU32(dentptr->size); unsigned int bytesperclust = mydata->clust_size * mydata->sect_size; __u32 curclust = START(dentptr); __u32 endclust = 0, newclust = 0; - unsigned long actsize; + loff_t actsize; - debug("Filesize: %ld bytes\n", filesize); + *gotsize = 0; + debug("Filesize: %llu bytes\n", filesize); if (maxsize > 0 && filesize > maxsize) filesize = maxsize; - debug("%ld bytes\n", filesize); + debug("%llu bytes\n", filesize); actsize = bytesperclust; endclust = curclust; @@ -692,7 +696,7 @@ set_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, if (CHECK_CLUST(newclust, mydata->fatsize)) { debug("curclust: 0x%x\n", newclust); debug("Invalid FAT entry\n"); - return gotsize; + return 0; } endclust = newclust; actsize += bytesperclust; @@ -706,7 +710,7 @@ set_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, } /* set remaining bytes */ - gotsize += (int)actsize; + *gotsize += actsize; filesize -= actsize; buffer += actsize; actsize = filesize; @@ -715,7 +719,7 @@ set_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, debug("error: writing cluster\n"); return -1; } - gotsize += actsize; + *gotsize += actsize; /* Mark end of file in FAT */ if (mydata->fatsize == 16) @@ -724,20 +728,20 @@ set_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, newclust = 0xfffffff; set_fatent_value(mydata, endclust, newclust); - return gotsize; + return 0; getit: if (set_cluster(mydata, curclust, buffer, (int)actsize) != 0) { debug("error: writing cluster\n"); return -1; } - gotsize += (int)actsize; + *gotsize += actsize; filesize -= actsize; buffer += actsize; if (CHECK_CLUST(curclust, mydata->fatsize)) { debug("curclust: 0x%x\n", curclust); debug("Invalid FAT entry\n"); - return gotsize; + return 0; } actsize = bytesperclust; curclust = endclust = newclust; @@ -766,9 +770,9 @@ static void fill_dentry(fsdata *mydata, dir_entry *dentptr, * exceed the size of the block device * Return -1 when overflow occurs, otherwise return 0 */ -static int check_overflow(fsdata *mydata, __u32 clustnum, unsigned long size) +static int check_overflow(fsdata *mydata, __u32 clustnum, loff_t size) { - __u32 startsect, sect_num; + __u32 startsect, sect_num, offset; if (clustnum > 0) { startsect = mydata->data_begin + @@ -777,13 +781,13 @@ static int check_overflow(fsdata *mydata, __u32 clustnum, unsigned long size) startsect = mydata->rootdir_sect; } - sect_num = size / mydata->sect_size; - if (size % mydata->sect_size) + sect_num = div_u64_rem(size, mydata->sect_size, &offset); + + if (offset != 0) sect_num++; if (startsect + sect_num > cur_part_info.start + total_sector) return -1; - return 0; } @@ -923,8 +927,8 @@ static dir_entry *find_directory_entry(fsdata *mydata, int startsect, return NULL; } -static int do_fat_write(const char *filename, void *buffer, - unsigned long size) +static int do_fat_write(const char *filename, void *buffer, loff_t size, + loff_t *actwrite) { dir_entry *dentptr, *retdent; __u32 startsect; @@ -936,8 +940,8 @@ static int do_fat_write(const char *filename, void *buffer, int cursect; int ret = -1, name_len; char l_filename[VFAT_MAXLEN_BYTES]; - int write_size = size; + *actwrite = size; dir_curclust = 0; if (read_bootsectandvi(&bs, &volinfo, &mydata->fatsize)) { @@ -1015,7 +1019,7 @@ static int do_fat_write(const char *filename, void *buffer, ret = check_overflow(mydata, start_cluster, size); if (ret) { - printf("Error: %ld overflow\n", size); + printf("Error: %llu overflow\n", size); goto exit; } @@ -1025,13 +1029,12 @@ static int do_fat_write(const char *filename, void *buffer, goto exit; } - ret = set_contents(mydata, retdent, buffer, size); + ret = set_contents(mydata, retdent, buffer, size, actwrite); if (ret < 0) { printf("Error: writing contents\n"); goto exit; } - write_size = ret; - debug("attempt to write 0x%x bytes\n", write_size); + debug("attempt to write 0x%llx bytes\n", *actwrite); /* Flush fat buffer */ ret = flush_fat_buffer(mydata); @@ -1061,7 +1064,7 @@ static int do_fat_write(const char *filename, void *buffer, ret = check_overflow(mydata, start_cluster, size); if (ret) { - printf("Error: %ld overflow\n", size); + printf("Error: %llu overflow\n", size); goto exit; } @@ -1069,13 +1072,13 @@ static int do_fat_write(const char *filename, void *buffer, fill_dentry(mydata, empty_dentptr, filename, start_cluster, size, 0x20); - ret = set_contents(mydata, empty_dentptr, buffer, size); + ret = set_contents(mydata, empty_dentptr, buffer, size, + actwrite); if (ret < 0) { printf("Error: writing contents\n"); goto exit; } - write_size = ret; - debug("attempt to write 0x%x bytes\n", write_size); + debug("attempt to write 0x%llx bytes\n", *actwrite); /* Flush fat buffer */ ret = flush_fat_buffer(mydata); @@ -1096,11 +1099,17 @@ static int do_fat_write(const char *filename, void *buffer, exit: free(mydata->fatbuf); - return ret < 0 ? ret : write_size; + return ret; } -int file_fat_write(const char *filename, void *buffer, unsigned long maxsize) +int file_fat_write(const char *filename, void *buffer, loff_t offset, + loff_t maxsize, loff_t *actwrite) { + if (offset != 0) { + printf("Error: non zero offset is currently not suported.\n"); + return -1; + } + printf("writing %s\n", filename); - return do_fat_write(filename, buffer, maxsize); + return do_fat_write(filename, buffer, maxsize, actwrite); } diff --git a/fs/fat/file.c b/fs/fat/file.c index d910c46..8970611 100644 --- a/fs/fat/file.c +++ b/fs/fat/file.c @@ -162,8 +162,7 @@ file_ls(const char *dir) return filesystems[current_filesystem].ls(arg); } -long -file_read(const char *filename, void *buffer, unsigned long maxsize) +int file_read(const char *filename, void *buffer, int maxsize) { char fullpath[1024]; const char *arg; @@ -15,6 +15,7 @@ */ #include <config.h> +#include <errno.h> #include <common.h> #include <part.h> #include <ext4fs.h> @@ -22,6 +23,8 @@ #include <fs.h> #include <sandboxfs.h> #include <asm/io.h> +#include <div64.h> +#include <linux/math64.h> DECLARE_GLOBAL_DATA_PTR; @@ -46,19 +49,21 @@ static inline int fs_exists_unsupported(const char *filename) return 0; } -static inline int fs_size_unsupported(const char *filename) +static inline int fs_size_unsupported(const char *filename, loff_t *size) { return -1; } static inline int fs_read_unsupported(const char *filename, void *buf, - int offset, int len) + loff_t offset, loff_t len, + loff_t *actread) { return -1; } static inline int fs_write_unsupported(const char *filename, void *buf, - int offset, int len) + loff_t offset, loff_t len, + loff_t *actwrite) { return -1; } @@ -67,6 +72,11 @@ static inline void fs_close_unsupported(void) { } +static inline int fs_uuid_unsupported(char *uuid_str) +{ + return -1; +} + struct fstype_info { int fstype; /* @@ -82,10 +92,13 @@ struct fstype_info { disk_partition_t *fs_partition); int (*ls)(const char *dirname); int (*exists)(const char *filename); - int (*size)(const char *filename); - int (*read)(const char *filename, void *buf, int offset, int len); - int (*write)(const char *filename, void *buf, int offset, int len); + int (*size)(const char *filename, loff_t *size); + int (*read)(const char *filename, void *buf, loff_t offset, + loff_t len, loff_t *actread); + int (*write)(const char *filename, void *buf, loff_t offset, + loff_t len, loff_t *actwrite); void (*close)(void); + int (*uuid)(char *uuid_str); }; static struct fstype_info fstypes[] = { @@ -99,7 +112,12 @@ static struct fstype_info fstypes[] = { .exists = fat_exists, .size = fat_size, .read = fat_read_file, +#ifdef CONFIG_FAT_WRITE + .write = file_fat_write, +#else .write = fs_write_unsupported, +#endif + .uuid = fs_uuid_unsupported, }, #endif #ifdef CONFIG_FS_EXT4 @@ -112,7 +130,12 @@ static struct fstype_info fstypes[] = { .exists = ext4fs_exists, .size = ext4fs_size, .read = ext4_read_file, +#ifdef CONFIG_CMD_EXT4_WRITE + .write = ext4_write_file, +#else .write = fs_write_unsupported, +#endif + .uuid = ext4fs_uuid, }, #endif #ifdef CONFIG_SANDBOX @@ -126,6 +149,7 @@ static struct fstype_info fstypes[] = { .size = sandbox_fs_size, .read = fs_read_sandbox, .write = fs_write_sandbox, + .uuid = fs_uuid_unsupported, }, #endif { @@ -138,6 +162,7 @@ static struct fstype_info fstypes[] = { .size = fs_size_unsupported, .read = fs_read_unsupported, .write = fs_write_unsupported, + .uuid = fs_uuid_unsupported, }, }; @@ -206,6 +231,13 @@ static void fs_close(void) fs_type = FS_TYPE_ANY; } +int fs_uuid(char *uuid_str) +{ + struct fstype_info *info = fs_get_info(fs_type); + + return info->uuid(uuid_str); +} + int fs_ls(const char *dirname) { int ret; @@ -233,20 +265,21 @@ int fs_exists(const char *filename) return ret; } -int fs_size(const char *filename) +int fs_size(const char *filename, loff_t *size) { int ret; struct fstype_info *info = fs_get_info(fs_type); - ret = info->size(filename); + ret = info->size(filename, size); fs_close(); return ret; } -int fs_read(const char *filename, ulong addr, int offset, int len) +int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len, + loff_t *actread) { struct fstype_info *info = fs_get_info(fs_type); void *buf; @@ -257,11 +290,11 @@ int fs_read(const char *filename, ulong addr, int offset, int len) * means read the whole file. */ buf = map_sysmem(addr, len); - ret = info->read(filename, buf, offset, len); + ret = info->read(filename, buf, offset, len, actread); unmap_sysmem(buf); /* If we requested a specific number of bytes, check we got it */ - if (ret >= 0 && len && ret != len) { + if (ret == 0 && len && *actread != len) { printf("** Unable to read file %s **\n", filename); ret = -1; } @@ -270,17 +303,18 @@ int fs_read(const char *filename, ulong addr, int offset, int len) return ret; } -int fs_write(const char *filename, ulong addr, int offset, int len) +int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len, + loff_t *actwrite) { struct fstype_info *info = fs_get_info(fs_type); void *buf; int ret; buf = map_sysmem(addr, len); - ret = info->write(filename, buf, offset, len); + ret = info->write(filename, buf, offset, len, actwrite); unmap_sysmem(buf); - if (ret >= 0 && ret != len) { + if (ret < 0 && len != *actwrite) { printf("** Unable to write file %s **\n", filename); ret = -1; } @@ -292,7 +326,7 @@ int fs_write(const char *filename, ulong addr, int offset, int len) int do_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype) { - int size; + loff_t size; if (argc != 4) return CMD_RET_USAGE; @@ -300,8 +334,7 @@ int do_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], if (fs_set_blk_dev(argv[1], argv[2], fstype)) return 1; - size = fs_size(argv[3]); - if (size < 0) + if (fs_size(argv[3], &size) < 0) return CMD_RET_FAILURE; setenv_hex("filesize", size); @@ -315,9 +348,10 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], unsigned long addr; const char *addr_str; const char *filename; - unsigned long bytes; - unsigned long pos; - int len_read; + loff_t bytes; + loff_t pos; + loff_t len_read; + int ret; unsigned long time; char *ep; @@ -359,15 +393,15 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], pos = 0; time = get_timer(0); - len_read = fs_read(filename, addr, pos, bytes); + ret = fs_read(filename, addr, pos, bytes, &len_read); time = get_timer(time); - if (len_read <= 0) + if (ret < 0) return 1; - printf("%d bytes read in %lu ms", len_read, time); + printf("%llu bytes read in %lu ms", len_read, time); if (time > 0) { puts(" ("); - print_size(len_read / time * 1000, "/s"); + print_size(div_u64(len_read, time) * 1000, "/s"); puts(")"); } puts("\n"); @@ -408,9 +442,10 @@ int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], { unsigned long addr; const char *filename; - unsigned long bytes; - unsigned long pos; - int len; + loff_t bytes; + loff_t pos; + loff_t len; + int ret; unsigned long time; if (argc < 6 || argc > 7) @@ -419,8 +454,8 @@ int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], if (fs_set_blk_dev(argv[1], argv[2], fstype)) return 1; - filename = argv[3]; - addr = simple_strtoul(argv[4], NULL, 16); + addr = simple_strtoul(argv[3], NULL, 16); + filename = argv[4]; bytes = simple_strtoul(argv[5], NULL, 16); if (argc >= 7) pos = simple_strtoul(argv[6], NULL, 16); @@ -428,18 +463,43 @@ int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], pos = 0; time = get_timer(0); - len = fs_write(filename, addr, pos, bytes); + ret = fs_write(filename, addr, pos, bytes, &len); time = get_timer(time); - if (len <= 0) + if (ret < 0) return 1; - printf("%d bytes written in %lu ms", len, time); + printf("%llu bytes written in %lu ms", len, time); if (time > 0) { puts(" ("); - print_size(len / time * 1000, "/s"); + print_size(div_u64(len, time) * 1000, "/s"); puts(")"); } puts("\n"); return 0; } + +int do_fs_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int fstype) +{ + int ret; + char uuid[37]; + memset(uuid, 0, sizeof(uuid)); + + if (argc < 3 || argc > 4) + return CMD_RET_USAGE; + + if (fs_set_blk_dev(argv[1], argv[2], fstype)) + return 1; + + ret = fs_uuid(uuid); + if (ret) + return CMD_RET_FAILURE; + + if (argc == 4) + setenv(argv[3], uuid); + else + printf("%s\n", uuid); + + return CMD_RET_SUCCESS; +} diff --git a/fs/sandbox/sandboxfs.c b/fs/sandbox/sandboxfs.c index ba6402c..a920bc0 100644 --- a/fs/sandbox/sandboxfs.c +++ b/fs/sandbox/sandboxfs.c @@ -13,10 +13,10 @@ int sandbox_fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info) return 0; } -long sandbox_fs_read_at(const char *filename, unsigned long pos, - void *buffer, unsigned long maxsize) +int sandbox_fs_read_at(const char *filename, loff_t pos, void *buffer, + loff_t maxsize, loff_t *actread) { - ssize_t size; + loff_t size; int fd, ret; fd = os_open(filename, OS_O_RDONLY); @@ -27,16 +27,31 @@ long sandbox_fs_read_at(const char *filename, unsigned long pos, os_close(fd); return ret; } - if (!maxsize) - maxsize = os_get_filesize(filename); + if (!maxsize) { + ret = os_get_filesize(filename, &size); + if (ret) { + os_close(fd); + return ret; + } + + maxsize = size; + } + size = os_read(fd, buffer, maxsize); os_close(fd); - return size; + if (size < 0) { + ret = -1; + } else { + ret = 0; + *actread = size; + } + + return ret; } -long sandbox_fs_write_at(const char *filename, unsigned long pos, - void *buffer, unsigned long towrite) +int sandbox_fs_write_at(const char *filename, loff_t pos, void *buffer, + loff_t towrite, loff_t *actwrite) { ssize_t size; int fd, ret; @@ -52,7 +67,14 @@ long sandbox_fs_write_at(const char *filename, unsigned long pos, size = os_write(fd, buffer, towrite); os_close(fd); - return size; + if (size == -1) { + ret = -1; + } else { + ret = 0; + *actwrite = size; + } + + return ret; } int sandbox_fs_ls(const char *dirname) @@ -74,43 +96,42 @@ int sandbox_fs_ls(const char *dirname) int sandbox_fs_exists(const char *filename) { - ssize_t sz; + loff_t size; + int ret; - sz = os_get_filesize(filename); - return sz >= 0; + ret = os_get_filesize(filename, &size); + return ret == 0; } -int sandbox_fs_size(const char *filename) +int sandbox_fs_size(const char *filename, loff_t *size) { - return os_get_filesize(filename); + return os_get_filesize(filename, size); } void sandbox_fs_close(void) { } -int fs_read_sandbox(const char *filename, void *buf, int offset, int len) +int fs_read_sandbox(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread) { - int len_read; + int ret; - len_read = sandbox_fs_read_at(filename, offset, buf, len); - if (len_read == -1) { + ret = sandbox_fs_read_at(filename, offset, buf, len, actread); + if (ret) printf("** Unable to read file %s **\n", filename); - return -1; - } - return len_read; + return ret; } -int fs_write_sandbox(const char *filename, void *buf, int offset, int len) +int fs_write_sandbox(const char *filename, void *buf, loff_t offset, + loff_t len, loff_t *actwrite) { - int len_written; + int ret; - len_written = sandbox_fs_write_at(filename, offset, buf, len); - if (len_written == -1) { + ret = sandbox_fs_write_at(filename, offset, buf, len, actwrite); + if (ret) printf("** Unable to write file %s **\n", filename); - return -1; - } - return len_written; + return ret; } diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index 0ce2475..c120261 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -476,10 +476,6 @@ struct file { #define MAX_LFS_FILESIZE 0x7fffffffffffffffUL #endif -#define INT_MAX ((int)(~0U>>1)) -#define INT_MIN (-INT_MAX - 1) -#define LLONG_MAX ((long long)(~0ULL>>1)) - /* * These are the fs-independent mount-flags: up to 32 flags are supported */ diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 74df210..9c5a1e1 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -91,6 +91,7 @@ typedef struct global_data { unsigned long malloc_limit; /* limit address */ unsigned long malloc_ptr; /* current address */ #endif + struct udevice *cur_serial_dev; /* current serial device */ struct arch_global_data arch; /* architecture-specific data */ } gd_t; #endif @@ -107,5 +108,6 @@ typedef struct global_data { #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ #define GD_FLG_ENV_READY 0x00080 /* Env. imported into hash table */ #define GD_FLG_SERIAL_READY 0x00100 /* Pre-reloc serial console ready */ +#define GD_FLG_FULL_MALLOC_INIT 0x00200 /* Full malloc() is ready */ #endif /* __ASM_GENERIC_GBL_DATA_H */ diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index f81b51a..36a36c6 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -257,6 +257,15 @@ const char *gpio_get_bank_info(struct udevice *dev, int *offset_count); int gpio_lookup_name(const char *name, struct udevice **devp, unsigned int *offsetp, unsigned int *gpiop); -int name_to_gpio(const char *name); +/** + * get_gpios() - Turn the values of a list of GPIOs into an integer + * + * This puts the value of the first GPIO into bit 0, the second into bit 1, + * etc. then returns the resulting integer. + * + * @gpio_list: List of GPIOs to collect + * @return resulting integer value + */ +unsigned gpio_get_values_as_int(const int *gpio_list); #endif /* _ASM_GENERIC_GPIO_H_ */ diff --git a/include/bios_emul.h b/include/bios_emul.h new file mode 100644 index 0000000..3643b82 --- /dev/null +++ b/include/bios_emul.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 1996-1999 SciTech Software, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _BIOS_EMUL_H +#define _BIOS_EMUL_H + +/* Include the register header directly here */ +#include "../drivers/bios_emulator/include/x86emu/regs.h" +#include <pci.h> + +/**************************************************************************** +REMARKS: +Data structure used to describe the details for the BIOS emulator system +environment as used by the X86 emulator library. + +HEADER: +biosemu.h + +MEMBERS: +vgaInfo - VGA BIOS information structure +biosmem_base - Base of the BIOS image +biosmem_limit - Limit of the BIOS image +busmem_base - Base of the VGA bus memory +****************************************************************************/ +typedef struct { + int function; + int device; + int bus; + u32 VendorID; + u32 DeviceID; + pci_dev_t pcidev; + void *BIOSImage; + u32 BIOSImageLen; + u8 LowMem[1536]; +} BE_VGAInfo; + +struct vbe_mode_info; + +int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int cleanUp); + +/* Run a BIOS ROM natively (only supported on x86 machines) */ +void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode, + struct vbe_mode_info *mode_info); + +/** + * bios_set_interrupt_handler() - Install an interrupt handler for the BIOS + * + * This installs an interrupt handler that the BIOS will call when needed. + * + * @intnum: Interrupt number to install a handler for + * @int_handler_func: Function to call to handle interrupt + */ +void bios_set_interrupt_handler(int intnum, int (*int_handler_func)(void)); + +void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void)); + +int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo); + +int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len, + BE_VGAInfo *vga_info, int clean_up, int vesa_mode, + struct vbe_mode_info *mode_info); + +#endif diff --git a/include/common.h b/include/common.h index ecf7fca..46f07fe 100644 --- a/include/common.h +++ b/include/common.h @@ -23,6 +23,7 @@ typedef volatile unsigned char vu_char; #include <linux/stringify.h> #include <asm/ptrace.h> #include <stdarg.h> +#include <linux/kernel.h> #if defined(CONFIG_PCI) && defined(CONFIG_4xx) #include <pci.h> #endif @@ -72,6 +73,9 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_ARM #define asmlinkage /* nothing */ #endif +#ifdef CONFIG_X86 +#define asmlinkage __attribute__((regparm(0))) +#endif #ifdef CONFIG_BLACKFIN #include <asm/blackfin.h> #endif @@ -96,15 +100,19 @@ typedef volatile unsigned char vu_char; #define _DEBUG 0 #endif +#ifndef pr_fmt +#define pr_fmt(fmt) fmt +#endif + /* * Output a debug text when condition "cond" is met. The "cond" should be * computed by a preprocessor in the best case, allowing for the best * optimization. */ -#define debug_cond(cond, fmt, args...) \ - do { \ - if (cond) \ - printf(fmt, ##args); \ +#define debug_cond(cond, fmt, args...) \ + do { \ + if (cond) \ + printf(pr_fmt(fmt), ##args); \ } while (0) #define debug(fmt, args...) \ @@ -126,7 +134,7 @@ void __assert_fail(const char *assertion, const char *file, unsigned line, __assert_fail(#x, __FILE__, __LINE__, __func__); }) #define error(fmt, args...) do { \ - printf("ERROR: " fmt "\nat %s:%d/%s()\n", \ + printf("ERROR: " pr_fmt(fmt) "\nat %s:%d/%s()\n", \ ##args, __FILE__, __LINE__, __func__); \ } while (0) @@ -168,58 +176,6 @@ typedef void (interrupt_handler_t)(void *); # endif #endif -/* - * General Purpose Utilities - */ -#define min(X, Y) \ - ({ typeof(X) __x = (X); \ - typeof(Y) __y = (Y); \ - (__x < __y) ? __x : __y; }) - -#define max(X, Y) \ - ({ typeof(X) __x = (X); \ - typeof(Y) __y = (Y); \ - (__x > __y) ? __x : __y; }) - -#define min3(X, Y, Z) \ - ({ typeof(X) __x = (X); \ - typeof(Y) __y = (Y); \ - typeof(Z) __z = (Z); \ - __x < __y ? (__x < __z ? __x : __z) : \ - (__y < __z ? __y : __z); }) - -#define max3(X, Y, Z) \ - ({ typeof(X) __x = (X); \ - typeof(Y) __y = (Y); \ - typeof(Z) __z = (Z); \ - __x > __y ? (__x > __z ? __x : __z) : \ - (__y > __z ? __y : __z); }) - -/* - * Return the absolute value of a number. - * - * This handles unsigned and signed longs, ints, shorts and chars. For all - * input types abs() returns a signed long. - * - * For 64-bit types, use abs64() - */ -#define abs(x) ({ \ - long ret; \ - if (sizeof(x) == sizeof(long)) { \ - long __x = (x); \ - ret = (__x < 0) ? -__x : __x; \ - } else { \ - int __x = (x); \ - ret = (__x < 0) ? -__x : __x; \ - } \ - ret; \ - }) - -#define abs64(x) ({ \ - s64 __x = (x); \ - (__x < 0) ? -__x : __x; \ - }) - #if defined(CONFIG_ENV_IS_EMBEDDED) #define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN #elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \ @@ -230,17 +186,6 @@ typedef void (interrupt_handler_t)(void *); #define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN #endif -/** - * container_of - cast a member of a structure out to the containing structure - * @ptr: the pointer to the member. - * @type: the type of the container struct this is embedded in. - * @member: the name of the member within the struct. - * - */ -#define container_of(ptr, type, member) ({ \ - const typeof( ((type *)0)->member ) *__mptr = (ptr); \ - (type *)( (char *)__mptr - offsetof(type,member) );}) - /* * Function Prototypes */ @@ -500,11 +445,6 @@ extern ssize_t spi_read (uchar *, int, uchar *, int); extern ssize_t spi_write (uchar *, int, uchar *, int); #endif -#ifdef CONFIG_HERMES -/* $(BOARD)/hermes.c */ -void hermes_start_lxt980 (int speed); -#endif - #ifdef CONFIG_EVB64260 void evb64260_init(void); void debug_led(int, int); @@ -947,31 +887,7 @@ static inline phys_addr_t map_to_sysmem(const void *ptr) #error Read section CONFIG_SKIP_LOWLEVEL_INIT in README. #endif -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - #define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1)) -#define DIV_ROUND(n,d) (((n) + ((d)/2)) / (d)) -#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) -#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) - -/* - * Divide positive or negative dividend by positive divisor and round - * to closest integer. Result is undefined for negative divisors and - * for negative dividends if the divisor variable type is unsigned. - */ -#define DIV_ROUND_CLOSEST(x, divisor)( \ -{ \ - typeof(x) __x = x; \ - typeof(divisor) __d = divisor; \ - (((typeof(x))-1) > 0 || \ - ((typeof(divisor))-1) > 0 || (__x) > 0) ? \ - (((__x) + ((__d) / 2)) / (__d)) : \ - (((__x) - ((__d) / 2)) / (__d)); \ -} \ -) - -#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) /* * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It @@ -1053,7 +969,7 @@ static inline phys_addr_t map_to_sysmem(const void *ptr) * Usage of this macro shall be avoided or used with extreme care! */ #define DEFINE_ALIGN_BUFFER(type, name, size, align) \ - static char __##name[roundup(size * sizeof(type), align)] \ + static char __##name[ALIGN(size * sizeof(type), align)] \ __aligned(align); \ \ static type *name = (type *)__##name diff --git a/include/commproc.h b/include/commproc.h index d78ab00..6875c4c 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -535,34 +535,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002600) #endif /* CONFIG_FPS850L, CONFIG_FPS860L */ -/*** HERMES-PRO ******************************************************/ - -/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */ - -#ifdef CONFIG_HERMES - -#define FEC_ENET /* use FEC for EThernet */ -#undef SCC_ENET - - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -#endif /* CONFIG_HERMES */ - /*** IP860 **********************************************************/ #if defined(CONFIG_IP860) diff --git a/include/config_defaults.h b/include/config_defaults.h index ad08c1d..4d49315 100644 --- a/include/config_defaults.h +++ b/include/config_defaults.h @@ -20,4 +20,10 @@ #define CONFIG_ZLIB 1 #define CONFIG_PARTITIONS 1 +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM_WARN +#define CONFIG_DM_DEVICE_REMOVE +#define CONFIG_DM_STDIO +#endif + #endif diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index 7d8daa2..508db56 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -79,6 +79,10 @@ #define CONFIG_SYS_PROMPT "=> " #endif +#ifndef CONFIG_SYS_PBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 128) +#endif + #ifndef CONFIG_FIT_SIGNATURE #define CONFIG_IMAGE_FORMAT_LEGACY #endif diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index dc1a9bc..9e8e319 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -713,8 +713,8 @@ unsigned long get_board_ddr_clk(void); #endif /* CONFIG_PCI */ #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 -#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 +#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 +#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ @@ -731,6 +731,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif +#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR + /* * Environment */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index bc5af52..adb8146 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -400,6 +400,23 @@ extern unsigned long get_sdram_size(void); #endif /* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nand0=ff800000.flash," +#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \ + "8m(kernel),512k(dtb),-(fs)" +/* + * Override partitions in device tree using info + * in "mtdparts" environment variable + */ +#ifdef CONFIG_CMD_MTDPARTS +#define CONFIG_FDT_FIXUP_PARTITIONS +#endif + +/* * Environment Configuration */ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 989363c..2722a32 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -637,6 +637,27 @@ combinations. this should be removed later #endif /* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," +#define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ + "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ + "8m(kernel),512k(dtb),-(fs)" +#endif +/* + * Override partitions in device tree using info + * in "mtdparts" environment variable + */ +#ifdef CONFIG_CMD_MTDPARTS +#define CONFIG_FDT_FIXUP_PARTITIONS +#endif + +/* * Environment Configuration */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 5d11278..ecb3d7b 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -12,6 +12,8 @@ #define __CONFIG_H #define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_C29XPCIE #define CONFIG_PPC_C29X diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 695e47b..832c10f 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -387,6 +387,11 @@ extern int board_pci_host_broken(void); #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_PCI_PNP /* do pci plug-and-play */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 1d1f4c0..8ed0f7c 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -685,6 +685,11 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_HAS_FSL_DR_USB +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_NETDEV "eth1" diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index d378dbd..cd6a39c 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -14,6 +14,8 @@ #ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT #endif +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_P1010 #define CONFIG_E500 /* BOOKE e500 family */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 54e2569..4371110 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -11,6 +11,9 @@ #include "../board/freescale/common/ics307_clk.h" +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT #endif @@ -616,6 +619,25 @@ #endif /* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#ifdef CONFIG_PHYS_64BIT +#define MTDIDS_DEFAULT "nor0=fe8000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ + "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ + "512k(dtb),768k(u-boot)" +#else +#define MTDIDS_DEFAULT "nor0=e8000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ + "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ + "512k(dtb),768k(u-boot)" +#endif + +/* * Environment */ #ifdef CONFIG_SPIFLASH diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index ba3da06..2ce186e 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -10,6 +10,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif @@ -374,6 +377,49 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "loadaddr=1000000\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off $ubootaddr +$filesize; " \ + "erase $ubootaddr +$filesize; " \ + "cp.b $loadaddr $ubootaddr $filesize; " \ + "protect on $ubootaddr +$filesize; " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs.ext2.gz.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=p1023rdb.dtb\0" \ + "othbootargs=ramdisk_size=600000\0" \ + "bdev=sda1\0" \ "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + #endif /* __CONFIG_H */ diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h index 371485f..e4a031a 100644 --- a/include/configs/P5040DS.h +++ b/include/configs/P5040DS.h @@ -17,6 +17,7 @@ #define CONFIG_MMC #define CONFIG_NAND_FSL_ELBC #define CONFIG_PCIE3 +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h new file mode 100644 index 0000000..78ed243 --- /dev/null +++ b/include/configs/T102xQDS.h @@ -0,0 +1,939 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * T1024/T1023 QDS board configuration file + */ + +#ifndef __T1024QDS_H +#define __T1024QDS_H + +/* High Level Configuration Options */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ +#define CONFIG_PHYS_64BIT +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_DEEP_SLEEP +#define CONFIG_SILENT_CONSOLE + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_SPI_BOOT +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + +#endif /* CONFIG_RAMBOOT_PBL */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +/* PCIe Boot - Master */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#else +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 +#endif +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#else +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 +#endif +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* PCIe Boot - Slave */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +/* Set 1M boot space for PCIe boot */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 0x800) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (256 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_DDR_SPD +#ifndef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDR3 +#endif + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x51 + +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_BASE 0xffdf0000 +#ifdef CONFIG_PHYS_64BIT +#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) +#else +#define QIXIS_BASE_PHYS QIXIS_BASE +#endif +#define QIXIS_LBMAP_SWITCH 0x06 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RST_FORCE_MEM 0x01 + +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_CSOR3 0x0 +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Video */ +#ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ +#define CONFIG_FSL_DIU_FB +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_FSL_DIU_CH7301 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +/* + * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so + * disable empty flash sector detection, which is I/O-intensive. + */ +#undef CONFIG_SYS_FLASH_EMPTY_INFO +#endif +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 + +#define I2C_MUX_PCA_ADDR 0x77 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ +#define I2C_RETIMER_ADDR 0x18 + +/* I2C bus multiplexer */ +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_DIU 0xC +#define I2C_MUX_CH5 0xD +#define I2C_MUX_CH7 0xF + +/* LDI/DVI Encoder for display */ +#define CONFIG_SYS_I2C_LDI_ADDR 0x38 +#define CONFIG_SYS_I2C_DVI_ADDR 0x75 + +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS3231 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_EON +#endif +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCIe + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +#define CONFIG_PCI_INDIRECT_BRIDGE + +#ifdef CONFIG_PCI +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#ifdef CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#ifdef CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* + *SATA + */ +#define CONFIG_FSL_SATA_V2 +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#endif + +/* + * SDHC + */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 25 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#else +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#endif +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 25 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 + +#define CONFIG_SYS_DPAA_FMAN + +#define CONFIG_QE +#define CONFIG_U_QE +/* Default address of microcode for the Linux FMan driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_QE_FW_ADDR 0x130000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_TERANETICS +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 +#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 +#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 +#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC4" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ + "spi0=spife110000.0" +#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ + "128k(dtb),96m(fs),-(user);"\ + "fff800000.flash:2m(uboot),9m(kernel),"\ + "128k(dtb),96m(fs),-(user);spife110000.0:" \ + "2m(uboot),9m(kernel),128k(dtb),-(user)" +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ +#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define CONFIG_BAUDRATE 115200 +#define __USB_PHY_TYPE utmi + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ + "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ + "ramdiskfile=t1024qds/ramdisk.uboot\0" \ + "fdtfile=t1024qds/t1024qds.dtb\0" \ + "netdev=eth0\0" \ + "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "fdtaddr=d00000\0" \ + "bdev=sda3\0" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include <asm/fsl_secure_boot.h> +#endif + +#endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h new file mode 100644 index 0000000..6f1fcd6 --- /dev/null +++ b/include/configs/T102xRDB.h @@ -0,0 +1,896 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * T1024/T1023 RDB board configuration file + */ + +#ifndef __T1024RDB_H +#define __T1024RDB_H + +/* High Level Configuration Options */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ +#define CONFIG_PHYS_64BIT +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_ENV_OVERWRITE + +/* support deep sleep */ +#define CONFIG_DEEP_SLEEP +#define CONFIG_SILENT_CONSOLE + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_SPI_BOOT +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + +#endif /* CONFIG_RAMBOOT_PBL */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +/* PCIe Boot - Master */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#else +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 +#endif +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#else +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 +#endif +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* PCIe Boot - Slave */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +/* Set 1M boot space for PCIe boot */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 0x800) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 66660000 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (256 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR3 + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x51 + +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +/* CPLD on IFC */ +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR2 0x0 + +/* CPLD Timing parameters for IFC CS2 */ +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS2_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Video */ +#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +/* + * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so + * disable empty flash sector detection, which is I/O-intensive. + */ +#undef CONFIG_SYS_FLASH_EMPTY_INFO +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 + +#define I2C_MUX_PCA_ADDR 0x77 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ + + +/* I2C bus multiplexer */ +#define I2C_MUX_CH_DEFAULT 0x8 + +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS1337 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCIe + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#ifdef CONFIG_PPC_T1040 +#define CONFIG_PCIE4 /* PCIE controler 4 */ +#endif +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +#define CONFIG_PCI_INDIRECT_BRIDGE + +#ifdef CONFIG_PCI +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#ifdef CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#ifdef CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 4, Base address 203000, to be removed */ +#ifdef CONFIG_PCIE4 +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull +#else +#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 +#endif +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#else +#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 +#endif +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#endif + +/* + * SDHC + */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 25 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#else +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#endif +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 25 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 + +#define CONFIG_SYS_DPAA_FMAN + +#define CONFIG_QE +#define CONFIG_U_QE +/* Default address of microcode for the Linux FMan driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_QE_FW_ADDR 0x130000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_REALTEK +#define RGMII_PHY1_ADDR 0x2 +#define RGMII_PHY2_ADDR 0x6 +#define FM1_10GEC1_PHY_ADDR 0x1 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC4" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ + "spi0=spife110000.1" +#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ + "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ + "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ + "1m(uboot),5m(kernel),128k(dtb),-(user)" +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_BDI + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ +#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define CONFIG_BAUDRATE 115200 +#define __USB_PHY_TYPE utmi + +#ifdef CONFIG_PPC_T1024 +#define CONFIG_BOARDNAME "t1024rdb" +#else +#define CONFIG_BOARDNAME "t1023rdb" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=cs0_cs1\0" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ + "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ + "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ + __stringify(CONFIG_BOARDNAME) ".dtb\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ + "netdev=eth0\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "fdtaddr=c00000\0" \ + "bdev=sda3\0" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include <asm/fsl_secure_boot.h> +#endif + +#endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 1d0664d..6b396bb 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -28,6 +28,8 @@ */ #define CONFIG_T1040QDS #define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE @@ -176,8 +178,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DDR_SPD #ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDR3 -#define CONFIG_FSL_DDR_INTERACTIVE #endif +#define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 @@ -730,7 +732,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -769,8 +770,7 @@ unsigned long get_board_ddr_clk(void); #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1;" \ + "hwconfig=fsl_ddr:bank_intlv=auto;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 2bb86e4..1eb1371 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -12,6 +12,11 @@ */ #define CONFIG_T104xRDB #define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_E500 /* BOOKE e500 family */ +#include <asm/config_mpc85xx.h> #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg @@ -93,7 +98,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ @@ -386,6 +390,12 @@ #define CONFIG_SYS_RAMBOOT #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A008044 +#if defined(CONFIG_NAND) +#define CONFIG_A008044_WORKAROUND +#endif +#endif + #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R @@ -745,7 +755,6 @@ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 2733358..d1fe78e 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -234,7 +234,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR3 -#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 @@ -494,6 +494,23 @@ unsigned long get_board_ddr_clk(void); #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ #define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_VOL_MONITOR 0xa + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +#define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_VID +#endif +#define CONFIG_VOL_MONITOR_IR36021_SET +#define CONFIG_VOL_MONITOR_IR36021_READ +/* The lowest and highest voltage allowed for T208xQDS */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 /* * RapidIO @@ -791,7 +808,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 400d979..47b3bd5 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -750,7 +750,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 13f4bd3..db03993 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -514,6 +514,29 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +/* CPLD on IFC */ +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) + +#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_CSOR3 0x0 + +/* CPLD Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + #if defined(CONFIG_RAMBOOT_PBL) #define CONFIG_SYS_RAMBOOT #endif @@ -667,6 +690,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #endif /* Hash command with SHA acceleration supported in hardware */ diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index a97f5fa..94078f5 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -20,8 +20,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */ #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ #define CONFIG_VCMA9 /* on a MPL VCMA9 Board */ #define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */ diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index a4050f3..d23d2c4 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -14,6 +14,8 @@ #define CONFIG_MPC5200 #define CONFIG_A3M071 /* A3M071 board */ +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */ @@ -416,8 +418,6 @@ #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NOR_SUPPORT #define CONFIG_SPL_TEXT_BASE 0xfc000000 -#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx" -#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ #define CONFIG_SPL_SERIAL_SUPPORT diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h index cc88ac1..3c67655 100644 --- a/include/configs/a4m072.h +++ b/include/configs/a4m072.h @@ -19,6 +19,8 @@ #define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_A4M072 1 /* ... on A4M072 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_TEXT_BASE 0xFE000000 diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index 14bac15..932a309 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -77,7 +77,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ diff --git a/include/configs/alt.h b/include/configs/alt.h index 7bd649f..58eac31 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -11,60 +11,16 @@ #define __ALT_H #undef DEBUG -#define CONFIG_ARMV7 #define CONFIG_R8A7794 #define CONFIG_RMOBILE_BOARD_STRING "Alt" -#define CONFIG_SH_GPIO_PFC - -#include <asm/arch/rmobile.h> - -#define CONFIG_CMD_EDITENV -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_DFL -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_RUN -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI + +#include "rcar-gen2-common.h" #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) #define CONFIG_SYS_TEXT_BASE 0x70000000 #else #define CONFIG_SYS_TEXT_BASE 0xE6304000 #endif -#define CONFIG_SYS_THUMB_BUILD -#define CONFIG_SYS_GENERIC_BOARD - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_OF_LIBFDT -#define BOARD_LATE_INIT - -#define CONFIG_BAUDRATE 38400 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "" - -#define CONFIG_VERSION_VARIABLE -#undef CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_TMU_TIMER #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC @@ -76,40 +32,14 @@ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ -#define ALT_SDRAM_BASE 0x40000000 -#define ALT_SDRAM_SIZE (1024u * 1024 * 1024) -#define ALT_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE 512 -#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SCIF */ #define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF2 -#undef CONFIG_SYS_CONSOLE_INFO_QUIET -#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE - -#define CONFIG_SYS_MEMTEST_START (ALT_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 504 * 1024 * 1024) -#undef CONFIG_SYS_ALT_MEMTEST -#undef CONFIG_SYS_MEMTEST_SCRATCH -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (ALT_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (ALT_UBOOT_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) +#define CONFIG_SCIF_USE_EXT_CLK /* FLASH */ #define CONFIG_SPI @@ -120,17 +50,6 @@ #define CONFIG_SPI_FLASH_QUAD #define CONFIG_SYS_NO_FLASH -/* ENV setting */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SECT_SIZE (256 * 1024) -#define CONFIG_ENV_ADDR 0xC0000 -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootm_low=0x40e00000\0" \ - "bootm_size=0x100000\0" \ - /* SH Ether */ #define CONFIG_NET_MULTI #define CONFIG_SH_ETHER @@ -151,7 +70,7 @@ #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_P_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ #define CONFIG_SYS_TMU_CLK_DIV 4 @@ -161,11 +80,8 @@ #define CONFIG_SYS_I2C_SH #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 -#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 #define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 #define CONFIG_SYS_I2C_SH_SPEED1 400000 -#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 #define CONFIG_SYS_I2C_SH_SPEED2 400000 #define CONFIG_SH_I2C_DATA_HIGH 4 #define CONFIG_SH_I2C_DATA_LOW 5 @@ -173,14 +89,29 @@ #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ -/* Filesystems */ -#define CONFIG_DOS_PARTITION -#define CONFIG_SUPPORT_VFAT - /* USB */ #define CONFIG_USB_STORAGE #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_RMOBILE #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +/* MMCIF */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_SH_MMCIF +#define CONFIG_SH_MMCIF_ADDR 0xee200000 +#define CONFIG_SH_MMCIF_CLK 48000000 + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF */ +#define CONFIG_SMSTP2_ENA 0x00002000 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 +/* SCIF2 */ +#define CONFIG_SMSTP7_ENA 0x00080000 + #endif /* __ALT_H */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 0fbfa3f..09ee10c 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -304,7 +304,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_LIBCOMMON_SUPPORT diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 8719f76..190ef0e 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -313,7 +313,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_LIBCOMMON_SUPPORT diff --git a/include/configs/apf27.h b/include/configs/apf27.h index 4424c30..403692d 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -18,8 +18,7 @@ /* * SoC configurations */ -#define CONFIG_ARM926EJS /* this is an ARM926EJS CPU */ -#define CONFIG_MX27 /* in a Freescale i.MX27 Chip */ +#define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */ #define CONFIG_MACH_TYPE 1698 /* APF27 */ #define CONFIG_SYS_GENERIC_BOARD diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index b073b97..72469f3 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -10,7 +10,6 @@ #define __ARMADILLO_800EVA_H #undef DEBUG -#define CONFIG_ARMV7 #define CONFIG_R8A7740 #define CONFIG_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n" #define CONFIG_SH_GPIO_PFC diff --git a/include/configs/arndale.h b/include/configs/arndale.h index f9ee40f..81e8a7c 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -9,6 +9,9 @@ #ifndef __CONFIG_ARNDALE_H #define __CONFIG_ARNDALE_H +#define EXYNOS_FDTFILE_SETTING \ + "fdtfile=exynos5250-arndale.dtb\0" + #include "exynos5250-common.h" /* SD/MMC configuration */ @@ -17,8 +20,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_CMD_EXT2 - /* USB */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_EXYNOS @@ -60,6 +61,4 @@ /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 -#define CONFIG_ARMV7_VIRT - #endif /* __CONFIG_H */ diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index a30c016..735c82a 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -61,6 +61,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory Configuration */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 73917b0..a6a80de 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -48,6 +48,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO @@ -135,7 +137,6 @@ #ifndef CONFIG_AT91SAM9G20EK_2MMC #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 226f8c1..407a53e 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -33,6 +33,8 @@ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_ATMEL_LEGACY #define CONFIG_SYS_TEXT_BASE 0x21f00000 @@ -107,7 +109,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index b666d94..fa19e8b 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -119,7 +119,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define AT91_SPI_CLK 15000000 diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index b8d5dd1..d5f0197 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -100,7 +100,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define AT91_SPI_CLK 15000000 diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h index bf09939..1045779 100644 --- a/include/configs/bcm28155_ap.h +++ b/include/configs/bcm28155_ap.h @@ -10,8 +10,7 @@ #include <linux/sizes.h> #include <asm/arch/sysmap.h> -/* Architecture, CPU, chip, mach, etc */ -#define CONFIG_ARMV7 +/* CPU, chip, mach, etc */ #define CONFIG_KONA #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_GENERIC_BOARD diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h index 827844e..fb85c72 100644 --- a/include/configs/bcm_ep_board.h +++ b/include/configs/bcm_ep_board.h @@ -9,8 +9,6 @@ #include <asm/arch/configs.h> -/* Architecture, CPU, chip, etc */ -#define CONFIG_ARMV7 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_GENERIC_BOARD diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h index d0828d5..39982ef 100644 --- a/include/configs/bct-brettl2.h +++ b/include/configs/bct-brettl2.h @@ -122,8 +122,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h new file mode 100644 index 0000000..cc36330 --- /dev/null +++ b/include/configs/beagle_x15.h @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2014 + * Texas Instruments Incorporated. + * Felipe Balbi <balbi@ti.com> + * + * Configuration settings for the TI Beagle x15 board. + * See ti_omap5_common.h for omap5 common settings. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BEAGLE_X15_H +#define __CONFIG_BEAGLE_X15_H + +#define CONFIG_AM57XX + +#define CONFIG_NR_DRAM_BANKS 2 + +#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" + +#define CONFIG_CMD_SAVEENV + +#define CONSOLEDEV "ttyO2" +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_OMAP_ABE_SYSCK + +/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" + +#include <configs/ti_omap5_common.h> + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +/* CPSW Ethernet */ +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_PHY_GIGE /* per-board part of CPSW */ +#define CONFIG_PHYLIB + +#define CONFIG_SUPPORT_EMMC_BOOT + +/* USB xHCI HOST */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_OMAP_USB_PHY +#define CONFIG_OMAP_USB3PHY1_HOST + +/* SATA */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#endif /* __CONFIG_BEAGLE_X5_H */ diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index 20f6ed1..50e85ca 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -134,8 +134,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index c33d035..7fc882a 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -131,8 +131,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h index b497f26..c2958e8 100644 --- a/include/configs/bf527-ad7160-eval.h +++ b/include/configs/bf527-ad7160-eval.h @@ -119,8 +119,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index 0bca53f..79e440a 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -134,8 +134,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h index 9d43b81..b374ab5 100644 --- a/include/configs/bf527-sdp.h +++ b/include/configs/bf527-sdp.h @@ -103,8 +103,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h index 3bc364c..6df89af 100644 --- a/include/configs/bf537-minotaur.h +++ b/include/configs/bf537-minotaur.h @@ -121,8 +121,8 @@ /* * I2C settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI #define CONFIG_SYS_I2C_SPEED 50000 #define CONFIG_SYS_I2C_SLAVE 0 diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index ba74a69..4f2b2cb 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -142,8 +142,8 @@ /* * I2C settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h index 0b723cf..d01d88f 100644 --- a/include/configs/bf537-srv1.h +++ b/include/configs/bf537-srv1.h @@ -120,8 +120,8 @@ /* * I2C settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI #define CONFIG_SYS_I2C_SPEED 50000 #define CONFIG_SYS_I2C_SLAVE 0 diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 29f9316..7b5a5a7 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -128,8 +128,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index a655282..e60558e 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -126,8 +126,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index da5f029..e71e6d3 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -134,8 +134,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 12192ff..878009f 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -81,8 +81,8 @@ #define CONFIG_PHYLIB /* i2c Settings */ -#define CONFIG_BFIN_TWI_I2C -#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* * Flash Settings diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 07ec5f2..143d3dd 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -73,7 +73,7 @@ # ifdef CONFIG_SPI_FLASH # define CONFIG_CMD_SF # endif -# if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) +# if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT) # define CONFIG_CMD_I2C # define CONFIG_SOFT_I2C_READ_REPEATED_START # endif @@ -301,7 +301,7 @@ /* * I2C Settings */ -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) +#if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT) # ifndef CONFIG_SYS_I2C_SPEED # define CONFIG_SYS_I2C_SPEED 50000 # endif diff --git a/include/configs/br4.h b/include/configs/br4.h index 3f24008..48cf184 100644 --- a/include/configs/br4.h +++ b/include/configs/br4.h @@ -102,8 +102,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C -#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/calimain.h b/include/configs/calimain.h index b27f973..44c947f 100644 --- a/include/configs/calimain.h +++ b/include/configs/calimain.h @@ -24,7 +24,6 @@ * SoC Configuration */ #define CONFIG_MACH_DAVINCI_CALIMAIN -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index 5f30279..f8785db 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -14,7 +14,6 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ #define CONFIG_SOC_DM365 diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h new file mode 100644 index 0000000..645b31c --- /dev/null +++ b/include/configs/chromebook_link.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_CAR_ADDR 0xff7e0000 +#define CONFIG_SYS_CAR_SIZE (128 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 +#define CONFIG_SYS_X86_START16 0xfffff800 +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_X86_RESET_VECTOR +#define CONFIG_NR_DRAM_BANKS 8 +#define CONFIG_X86_MRC_START 0xfffa0000 +#define CONFIG_CACHE_MRC_SIZE_KB 512 + +#define CONFIG_COREBOOT_SERIAL + +#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} + +#define CONFIG_X86_OPTION_ROM_FILENAME pci8086,0166.bin +#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 +#define CONFIG_VIDEO_X86 + +#define CONFIG_PCI_MEM_BUS 0xe0000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_PREF_BUS 0xd0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x1000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xefff + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP + +#define CONFIG_BIOSEMU +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#define CONFIG_CROS_EC +#define CONFIG_CROS_EC_LPC +#define CONFIG_CMD_CROS_EC +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ + "stdout=vga,serial\0" \ + "stderr=vga,serial\0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h index f5351ad..643c837 100644 --- a/include/configs/cm-bf527.h +++ b/include/configs/cm-bf527.h @@ -113,8 +113,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index 1729b44..e059568 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -122,8 +122,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index 272aa74..1f26457 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -120,8 +120,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h index 7f27eda..72eafc5 100644 --- a/include/configs/cm-bf548.h +++ b/include/configs/cm-bf548.h @@ -104,8 +104,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 1919cde..ccd9b88 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -321,7 +321,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_BOARD_INIT diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h index 641ab48..92ce1e1 100644 --- a/include/configs/cm_t54.h +++ b/include/configs/cm_t54.h @@ -16,7 +16,6 @@ #include <configs/ti_omap5_common.h> -#undef CONFIG_MISC_INIT_R #undef CONFIG_SPL_OS_BOOT /* Enable Generic board */ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index fef267f..2581380 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -6,7 +6,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <asm/ibmpc.h> /* * board/config.h - configuration options, board specific */ @@ -14,27 +13,23 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <configs/x86-common.h> + /* * High Level Configuration Options * (easy to change) */ #define CONFIG_SYS_COREBOOT -#define CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_LAST_STAGE_INIT -#define CONFIG_SYS_VSNPRINTF -#define CONFIG_ZBOOT_32 -#define CONFIG_PHYSMEM #define CONFIG_SYS_EARLY_PCI_INIT -#define CONFIG_DISPLAY_BOARDINFO_LATE -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DM -#define CONFIG_CMD_DM -#define CONFIG_DM_GPIO -#define CONFIG_DM_SERIAL +#define CONFIG_SYS_CAR_ADDR 0x19200000 +#define CONFIG_SYS_CAR_SIZE (16 * 1024) +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_LMB -#define CONFIG_OF_LIBFDT +#define CONFIG_TRACE_EARLY_SIZE (8 << 20) +#define CONFIG_TRACE_EARLY +#define CONFIG_TRACE_EARLY_ADDR 0x01400000 #define CONFIG_BOOTSTAGE #define CONFIG_BOOTSTAGE_REPORT @@ -45,26 +40,6 @@ #define CONFIG_BOOTSTAGE_STASH_SIZE 0x7fc #define CONFIG_BOOTSTAGE_USER_COUNT 60 -#define CONFIG_LZO -#define CONFIG_FIT -#undef CONFIG_ZLIB -#undef CONFIG_GZIP -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - -/*----------------------------------------------------------------------- - * Watchdog Configuration - */ -#undef CONFIG_WATCHDOG -#undef CONFIG_HW_WATCHDOG - -/* SATA AHCI storage */ - -#define CONFIG_SCSI_AHCI - -#ifdef CONFIG_SCSI_AHCI -#define CONFIG_LIBATA -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_SATA_INTEL 1 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ {PCI_VENDOR_ID_INTEL, \ @@ -74,249 +49,27 @@ {PCI_VENDOR_ID_INTEL, \ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#endif - -/* Generic TPM interfaced through LPC bus */ -#define CONFIG_TPM -#define CONFIG_TPM_TIS_LPC -#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 - -/*----------------------------------------------------------------------- - * Real Time Clock Configuration - */ -#define CONFIG_RTC_MC146818 -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 -#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS - -/*----------------------------------------------------------------------- - * Serial Configuration - */ #define CONFIG_COREBOOT_SERIAL -#define CONFIG_SYS_NS16550 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \ - 9600, 19200, 38400, 115200} -#define CONFIG_SYS_NS16550_PORT_MAPPED #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ "stdout=vga,serial,cbmem\0" \ "stderr=vga,serial,cbmem\0" -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_STDIO_DEREGISTER #define CONFIG_CBMEM_CONSOLE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_COMMAND_HISTORY -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER - -#define CONFIG_SUPPORT_VFAT -/************************************************************ - * ATAPI support (experimental) - ************************************************************/ -#define CONFIG_ATAPI - -/************************************************************ - * DISK Partition support - ************************************************************/ -#define CONFIG_EFI_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION /* Experimental */ - -#define CONFIG_CMD_PART -#define CONFIG_CMD_CBFS -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE -#define CONFIG_PARTITION_UUIDS - -/*----------------------------------------------------------------------- - * Video Configuration - */ -#define CONFIG_VIDEO #define CONFIG_VIDEO_COREBOOT -#define CONFIG_VIDEO_SW_CURSOR -#define VIDEO_FB_16BPP_WORD_SWAP -#define CONFIG_I8042_KBD -#define CONFIG_CFB_CONSOLE -#define CONFIG_SYS_CONSOLE_INFO_QUIET -/* x86 GPIOs are accessed through a PCI device */ -#define CONFIG_INTEL_ICH6_GPIO - -/*----------------------------------------------------------------------- - * Command line configuration. - */ -#include <config_cmd_default.h> +#define CONFIG_NR_DRAM_BANKS 4 #define CONFIG_TRACE #define CONFIG_CMD_TRACE #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x01400000 - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ECHO -#undef CONFIG_CMD_FLASH -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_GPIO -#define CONFIG_CMD_IMI -#undef CONFIG_CMD_IMLS -#define CONFIG_CMD_IO -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ITEST -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_SETGETDCR -#define CONFIG_CMD_SOURCE -#define CONFIG_CMD_TIME -#define CONFIG_CMD_GETTIME -#define CONFIG_CMD_XIMG -#define CONFIG_CMD_SCSI - -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - -#define CONFIG_CMD_ZBOOT -#define CONFIG_CMD_ELF #define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS \ - "root=/dev/sdb3 init=/sbin/init rootwait ro" -#define CONFIG_BOOTCOMMAND \ - "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000" - - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + \ - 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x01000000 -#define CONFIG_SYS_LOAD_ADDR 0x20000000 - -/*----------------------------------------------------------------------- - * SDRAM Configuration - */ -#define CONFIG_NR_DRAM_BANKS 4 - -/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/ -#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY -#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T - -/*----------------------------------------------------------------------- - * CPU Features - */ - -#define CONFIG_SYS_X86_TSC_TIMER -#define CONFIG_SYS_PCAT_INTERRUPTS -#define CONFIG_SYS_PCAT_TIMER -#define CONFIG_SYS_NUM_IRQS 16 - -/*----------------------------------------------------------------------- - * Memory organization: - * 32kB Stack - * 16kB Cache-As-RAM @ 0x19200000 - * 256kB Monitor - * (128kB + Environment Sector Size) malloc pool - */ -#define CONFIG_SYS_STACK_SIZE (32 * 1024) -#define CONFIG_SYS_CAR_ADDR 0x19200000 -#define CONFIG_SYS_CAR_SIZE (16 * 1024) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (0x20000 + 128 * 1024) -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/*----------------------------------------------------------------------- - * FLASH configuration - */ -#define CONFIG_ICH_SPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SPI_FLASH_GIGADEVICE -#define CONFIG_SYS_NO_FLASH -#define CONFIG_CMD_SF -#define CONFIG_CMD_SF_TEST -#define CONFIG_CMD_SPI -#define CONFIG_SPI - -/*----------------------------------------------------------------------- - * Environment configuration - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x01000 - -/*----------------------------------------------------------------------- - * PCI configuration - */ -#define CONFIG_PCI #define CONFIG_CROS_EC #define CONFIG_CROS_EC_LPC #define CONFIG_CMD_CROS_EC #define CONFIG_ARCH_EARLY_INIT_R -/*----------------------------------------------------------------------- - * USB configuration - */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_PCI -#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_USB_STORAGE -#define CONFIG_USB_KEYBOARD -#define CONFIG_SYS_USB_EVENT_POLL - -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_SMSC95XX -#define CONFIG_TFTP_TSIZE -#define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -#define CONFIG_CMD_USB - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_STD_DEVICES_SETTINGS - #endif /* __CONFIG_H */ diff --git a/include/configs/corvus.h b/include/configs/corvus.h index eb1584d..5b50c1d 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -19,7 +19,6 @@ #define MACH_TYPE_CORVUS 2066 #define CONFIG_SYS_GENERIC_BOARD - /* * Warning: changing CONFIG_SYS_TEXT_BASE requires * adapting the initial boot program. @@ -27,7 +26,7 @@ * hex number here! */ -#define CONFIG_SYS_TEXT_BASE 0x73f00000 +#define CONFIG_SYS_TEXT_BASE 0x72000000 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ @@ -107,8 +106,6 @@ /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 - #endif /* Ethernet */ @@ -159,5 +156,54 @@ */ #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ 128*1024, 0x1000) +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE (12 * 1024) +#define CONFIG_SPL_STACK (16 * 1024) + +#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_BSS_MAX_SIZE (2 * 1024) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_NAND_RAW_ONLY +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +#define CONFIG_SYS_NAND_SIZE (256*1024*1024) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } + +#define CONFIG_SPL_ATMEL_SIZE +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define AT91_PLL_LOCK_TIMEOUT 1000000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0 #endif diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index ce52101..8c7d97a 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -26,7 +26,6 @@ #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3) #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) -#define CONFIG_ARM920T #define CONFIG_AT91RM9200 #define CONFIG_CPUAT91 #define USE_920T_MMU diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index 2717195..0bdcef7 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -21,7 +21,6 @@ * SoC Configuration */ #define CONFIG_MACH_DAVINCI_DA830_EVM -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA830 /* TI DA830 SoC */ #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 5f85755..e5f8afe 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -25,7 +25,6 @@ * SoC Configuration */ #define CONFIG_MACH_DAVINCI_DA850_EVM -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h index c2e187e..16b901b 100644 --- a/include/configs/davinci_dm355evm.h +++ b/include/configs/davinci_dm355evm.h @@ -15,7 +15,6 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ #define CONFIG_SOC_DM355 diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h index 5188fdf..4eed722 100644 --- a/include/configs/davinci_dm355leopard.h +++ b/include/configs/davinci_dm355leopard.h @@ -14,7 +14,6 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ #define CONFIG_SOC_DM355 /* DM355 based board */ diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index c4fccfd..c50c059 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -15,7 +15,6 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ #define CONFIG_SOC_DM365 diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h index b1b18ad..2c5a837 100644 --- a/include/configs/davinci_dm6467evm.h +++ b/include/configs/davinci_dm6467evm.h @@ -15,7 +15,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT /* SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU */ /* Clock rates detection */ #ifndef __ASSEMBLY__ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 9b3d0fe..2467f70 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -41,7 +41,6 @@ /*===================*/ /* SoC Configuration */ /*===================*/ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CONFIG_SOC_DM644X diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 96c8fe2..2505465 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -19,7 +19,6 @@ /*===================*/ /* SoC Configuration */ /*===================*/ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CONFIG_SOC_DM644X diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 6e07cce..e773835 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_USE_NAND #define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */ /* SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CONFIG_SOC_DM644X diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index cd23aaca..dae37cd 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -43,7 +43,6 @@ /*===================*/ /* SoC Configuration */ /*===================*/ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CONFIG_SOC_DM644X diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index e0bf3dc..8a7447d 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -15,6 +15,9 @@ #define CONFIG_DBAU1X00 1 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifdef CONFIG_DBAU1000 /* Also known as Merlot */ #define CONFIG_SOC_AU1000 1 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index ca62461..930b08e 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -299,7 +299,7 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h index af0d602..a9cfc10 100644 --- a/include/configs/dlvision.h +++ b/include/configs/dlvision.h @@ -35,6 +35,7 @@ /* new uImage format support */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ +#define CONFIG_FIT_DISABLE_SHA256 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ @@ -59,8 +60,14 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DTT +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 2eaabde..174a711 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -50,6 +50,7 @@ #define CONFIG_EFI_PARTITION #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART +#define CONFIG_HSMMC2_8BIT /* CPSW Ethernet */ #define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ diff --git a/include/configs/ea20.h b/include/configs/ea20.h index 1d50a37..ae89368 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -28,7 +28,6 @@ * SoC Configuration */ #define CONFIG_MACH_DAVINCI_DA850_EVM -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h index 47a8420..a82e8bc 100644 --- a/include/configs/edb93xx.h +++ b/include/configs/edb93xx.h @@ -85,8 +85,7 @@ #endif /* High-level configuration options */ -#define CONFIG_ARM920T 1 /* This is an ARM920T core... */ -#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */ +#define CONFIG_EP93XX 1 /* This is a Cirrus Logic 93xx SoC */ #define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ #undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 1df4fc1..70a698a 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -23,7 +23,6 @@ */ #define CONFIG_MARVELL 1 -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_FEROCEON 1 /* CPU Core subversion */ #define CONFIG_88F5182 1 /* SOC Name */ #define CONFIG_MACH_EDMINIV2 1 /* Machine type */ diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h index 30ca95f..cdea4a8 100644 --- a/include/configs/enbw_cmc.h +++ b/include/configs/enbw_cmc.h @@ -25,7 +25,6 @@ /* * SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 4c69af6..ce61a16 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -78,7 +78,6 @@ /* SPI */ #define CONFIG_ATMEL_SPI -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define AT91_SPI_CLK 15000000 /* Serial port */ diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index b258cb9..1f3ee55 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -30,9 +30,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F -/* Enable fdt support */ -#define CONFIG_OF_LIBFDT - /* Keep L2 Cache Disabled */ #define CONFIG_CMD_CACHE @@ -42,7 +39,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING #define CONFIG_ENV_OVERWRITE /* Size of malloc() pool before and after relocation */ @@ -61,7 +57,6 @@ #define CONFIG_EXYNOS_DWMMC #define CONFIG_BOUNCE_BUFFER -#define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* PWM */ @@ -71,22 +66,16 @@ #include <config_cmd_default.h> #define CONFIG_CMD_MMC -#define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE -#define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE #define CONFIG_CMD_FS_GENERIC -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION #define CONFIG_CMD_PART #define CONFIG_PARTITION_UUIDS /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ @@ -96,4 +85,6 @@ #define CONFIG_SYS_NO_FLASH #undef CONFIG_CMD_IMLS +#include <config_distro_defaults.h> + #endif /* __CONFIG_H */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ba591e7..8f9b780 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -47,17 +47,6 @@ #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_CONSOLE_MUX -#define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS - -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NET #define CONFIG_CMD_HASH /* Thermal Management Unit */ @@ -174,12 +163,6 @@ #define CONFIG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ -/* Enable PXE Support */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#endif - /* SHA hashing */ #define CONFIG_CMD_HASH #define CONFIG_HASH_VERIFY @@ -189,8 +172,6 @@ /* Enable Time Command */ #define CONFIG_CMD_TIME -#define CONFIG_CMD_BOOTZ - #define CONFIG_CMD_GPIO /* USB boot mode */ @@ -203,4 +184,41 @@ #define CONFIG_FIT #define CONFIG_FIT_BEST_MATCH + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#ifndef MEM_LAYOUT_ENV_SETTINGS +/* 2GB RAM, bootm size of 256M, load scripts after that */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x42000000\0" \ + "fdt_addr_r=0x43000000\0" \ + "ramdisk_addr_r=0x43300000\0" \ + "scriptaddr=0x50000000\0" \ + "pxefile_addr_r=0x51000000\0" +#endif + +#ifndef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" +#endif + +#ifndef EXYNOS_FDTFILE_SETTING +#define EXYNOS_FDTFILE_SETTING +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS \ + EXYNOS_FDTFILE_SETTING \ + MEM_LAYOUT_ENV_SETTINGS \ + BOOTENV + #endif /* __CONFIG_EXYNOS5_COMMON_H */ diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index 66547fa..9cef0b0 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -9,6 +9,13 @@ #ifndef __CONFIG_EXYNOS5_DT_COMMON_H #define __CONFIG_EXYNOS5_DT_COMMON_H +/* Console configuration */ +#undef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" + #include "exynos5-common.h" /* PMIC */ @@ -22,14 +29,4 @@ #define CONFIG_CMD_CROS_EC #define CONFIG_KEYBOARD -/* Console configuration */ -#undef EXYNOS_DEVICE_SETTINGS -#define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,lcd\0" \ - "stderr=serial,lcd\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS - #endif diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 713614f..a0107e8 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -29,8 +29,6 @@ #define CONFIG_SPL_TEXT_BASE 0x02023400 -#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" - #define CONFIG_IRAM_STACK 0x02050000 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index b0f940c..ef6e155 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -10,6 +10,8 @@ #define __CONFIG_EXYNOS5420_H #define CONFIG_EXYNOS5420 +/* A variant of Exynos5420 (Exynos5 Family) */ +#define CONFIG_EXYNOS5800 #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_SPI_FLASH @@ -38,14 +40,13 @@ #define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) -#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420" +#define CONFIG_DEVICE_TREE_LIST "exynos5800-peach-pi" \ + "exynos5420-peach-pit exynos5420-smdk5420" #define CONFIG_MAX_I2C_NUM 11 #define CONFIG_BOARD_REV_GPIO_COUNT 2 -#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" - #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 /* @@ -54,10 +55,6 @@ */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) -/* DRAM Memory Banks */ -#define CONFIG_NR_DRAM_BANKS 7 -#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ - /* Miscellaneous configurable options */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" diff --git a/include/configs/flea3.h b/include/configs/flea3.h index 8417567..bf02829 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -16,7 +16,6 @@ #include <asm/arch/imx-regs.h> /* High Level Configuration Options */ -#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX35 #define CONFIG_SYS_DCACHE_OFF diff --git a/include/configs/gose.h b/include/configs/gose.h new file mode 100644 index 0000000..44c8a30 --- /dev/null +++ b/include/configs/gose.h @@ -0,0 +1,104 @@ +/* + * include/configs/gose.h + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __GOSE_H +#define __GOSE_H + +#undef DEBUG +#define CONFIG_R8A7793 +#define CONFIG_RMOBILE_BOARD_STRING "Gose" + +#include "rcar-gen2-common.h" + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x70000000 +#else +#define CONFIG_SYS_TEXT_BASE 0xE6304000 +#endif + +/* STACK */ +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC +#endif + +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE 0x40000000 +#define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000 + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF0 +#define CONFIG_SCIF_USE_EXT_CLK + +/* FLASH */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SPI +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SPI_FLASH_SPANSION + +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) +#define CONFIG_SH_SCIF_CLK_FREQ 14745600 +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 +#define CONFIG_SYS_I2C_SH_SPEED0 400000 +#define CONFIG_SYS_I2C_SH_SPEED1 400000 +#define CONFIG_SYS_I2C_SH_SPEED2 400000 +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 10000000 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +/* USB */ +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF */ +#define CONFIG_SMSTP2_ENA 0x00002000 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 +/* SCIF0 */ +#define CONFIG_SMSTP7_ENA 0x00200000 + +#endif /* __GOSE_H */ diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h index 8188c7b..1d78e72 100644 --- a/include/configs/hawkboard.h +++ b/include/configs/hawkboard.h @@ -20,7 +20,6 @@ * SoC Configuration */ #define CONFIG_MACH_DAVINCI_HAWK -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH diff --git a/include/configs/hermes.h b/include/configs/hermes.h deleted file mode 100644 index 736ffb61..0000000 --- a/include/configs/hermes.h +++ /dev/null @@ -1,315 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860T CPU */ -#define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */ - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */ -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 /* Non-Standard value! */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - * +0x0004 - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * +0x0000 => 0x000000C0 - */ -#define CONFIG_SYS_SIUMCR 0 - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - * +0x0200 => 0x00C2 - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - * +0x0240 => 0x0082 - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* +0x0286 => 0x00B0D0C0 */ -#define CONFIG_SYS_PLPRCR \ - ( (11 << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* +0x0282 => 0x03800000 */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/* +0x0220 => 0x00C3 */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* +0x09C4 => TIMEP=1 */ -#define CONFIG_SYS_RCCR 0x0100 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMDS 0 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */ - -/* used to re-map FLASH - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -/* allow for max 4 MB of Flash */ -#define CONFIG_SYS_REMAP_OR_AM 0xFFC00000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \ - OR_SCY_5_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -/* 8 bit, bank valid */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR1/OR1 - SDRAM - * - * Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ -#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */ - -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#define CONFIG_SYS_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide - */ -#define HPRO2_BASE 0xE0000000 -#define HPRO2_OR_AM 0xFFFF8000 -#define HPRO2_TIMING 0x00000934 - -#define CONFIG_SYS_OR2 (HPRO2_OR_AM | HPRO2_TIMING) -#define CONFIG_SYS_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR3/OR3: not used - * BR4/OR4: not used - * BR5/OR5: not used - * BR6/OR6: not used - * BR7/OR7: not used - */ - -/* - * MAMR settings for SDRAM - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -#endif /* __CONFIG_H */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h new file mode 100644 index 0000000..e7df9ad --- /dev/null +++ b/include/configs/hrcon.h @@ -0,0 +1,614 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC830x 1 /* MPC830x family */ +#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ +#define CONFIG_HRCON 1 /* HRCON board specific */ + +#define CONFIG_SYS_TEXT_BASE 0xFE000000 + +#define CONFIG_IDENT_STRING " hrcon 0.01" + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_LAST_STAGE_INIT + +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 + +#define CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 + +#define CONFIG_CMD_FPGAD +#define CONFIG_CMD_IOLOOP + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66.66MHz, then + * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz + * We choose the A type silicon as default, so the core is 400Mhz. + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_SVCOD_DIV_2 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_CORE_TO_CSB_3X1) +/* + * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits + * in 8308's HRCWH according to the manual, but original Freescale's + * code has them and I've expirienced some problems using the board + * with BDI3000 attached when I've tried to set these bits to zero + * (UART doesn't work after the 'reset run' command). + */ +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN) + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH (\ + SICRH_ESDHC_A_SD |\ + SICRH_ESDHC_B_SD |\ + SICRH_ESDHC_C_SD |\ + SICRH_GPIO_A_GPIO |\ + SICRH_GPIO_B_GPIO |\ + SICRH_IEEE1588_A_GPIO |\ + SICRH_USB |\ + SICRH_GTM_GPIO |\ + SICRH_IEEE1588_B_GPIO |\ + SICRH_ETSEC2_GPIO |\ + SICRH_GPIOSEL_1 |\ + SICRH_TMROBI_V3P3 |\ + SICRH_TSOBI1_V2P5 |\ + SICRH_TSOBI2_V2P5) /* 0x0037f103 */ +#define CONFIG_SYS_SICRL (\ + SICRL_SPI_PF0 |\ + SICRL_UART_PF0 |\ + SICRL_IRQ_PF0 |\ + SICRL_I2C2_PF0 |\ + SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */ + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * SERDES + */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 + +/* + * Arbiter Setup + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ +#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ + | DDRCDR_PZ_LOZ \ + | DDRCDR_NZ_LOZ \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x7b880001 */ +/* + * Manually set up DDR parameters + * consist of one chip NT5TU64M16HG from NANYA + */ + +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ + +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ + | CSCONFIG_BANK_BIT_3 \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) + /* 0x80010102 */ +#define CONFIG_SYS_DDR_TIMING_3 0 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00260802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (7 << TIMING_CFG1_CASLAT_SHIFT) \ + | (9 << TIMING_CFG1_REFREC_SHIFT) \ + | (2 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x26279222 */ +#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (4 << TIMING_CFG2_CPO_SHIFT) \ + | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x021848c5 */ +#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x08240100 */ +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_16) + /* 0x43100000 */ + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ +#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0242 << SDRAM_MODE_SD_SHIFT)) + /* ODT 150ohm CL=4, AL=0 on SDRAM */ +#define CONFIG_SYS_DDR_MODE2 0x00000000 + +/* + * Memory test + */ +#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x07f00000 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 +#define CONFIG_SYS_LBC_LBCR 0x00040000 + +/* + * FLASH on the Local Bus + */ +#if 1 +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 +#else +#define CONFIG_SYS_NO_FLASH +#endif + +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ + +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * FPGA + */ +#define CONFIG_SYS_FPGA0_BASE 0xE0600000 +#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ + +/* Window base at FPGA base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET) + +#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE +#define CONFIG_SYS_FPGA_DONE(k) 0x0010 + +#define CONFIG_SYS_FPGA_COUNT 1 + +#define CONFIG_SYS_MCLINK_MAX 3 + +#define CONFIG_SYS_FPGA_PTR \ + { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 + +#define CONFIG_PCA953X /* NXP PCA9554 */ +#define CONFIG_PCA9698 /* NXP PCA9698 */ + +#define CONFIG_SYS_I2C_IHS +#define CONFIG_SYS_I2C_IHS_CH0 +#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F +#define CONFIG_SYS_I2C_IHS_CH1 +#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH2 +#define CONFIG_SYS_I2C_IHS_SPEED_2 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F +#define CONFIG_SYS_I2C_IHS_CH3 +#define CONFIG_SYS_I2C_IHS_SPEED_3 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F + +/* + * Software (bit-bang) I2C driver configuration + */ +#define CONFIG_SYS_I2C_SOFT +#define CONFIG_SYS_I2C_SOFT_SPEED 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F +#define I2C_SOFT_DECLARATIONS2 +#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F +#define I2C_SOFT_DECLARATIONS3 +#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F +#define I2C_SOFT_DECLARATIONS4 +#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F + +#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} +#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} +#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} + +#ifndef __ASSEMBLY__ +void fpga_gpio_set(unsigned int bus, int pin); +void fpga_gpio_clear(unsigned int bus, int pin); +int fpga_gpio_get(unsigned int bus, int pin); +#endif + +#define I2C_ACTIVE { } +#define I2C_TRISTATE { } +#define I2C_READ \ + (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0) +#define I2C_SDA(bit) \ + do { \ + if (bit) \ + fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \ + else \ + fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \ + } while (0) +#define I2C_SCL(bit) \ + do { \ + if (bit) \ + fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \ + else \ + fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \ + } while (0) +#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ + +/* + * Software (bit-bang) MII driver configuration + */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +#define CONFIG_BITBANGMII_MULTI + +/* + * OSD Setup + */ +#define CONFIG_SYS_OSD_SCREENS 1 +#define CONFIG_SYS_DP501_DIFFERENTIAL +#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +/* enable PCIE clock */ +#define CONFIG_SYS_SCCR_PCIEXP1CM 1 + +#define CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCIE + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT + +/* Options are: eTSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC0" + +/* + * Environment + */ +#if 1 +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#else +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ +#define CONFIG_AUTOBOOT_STOP_STR " " + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ + +#define CONFIG_HOSTNAME hrcon +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS1\0" \ + "u-boot=u-boot.bin\0" \ + "kernel_addr=1000000\0" \ + "fdt_addr=C00000\0" \ + "fdtfile=hrcon.dtb\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ + " +${filesize};cp.b ${fileaddr} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp ${kernel_addr} $bootfile;" \ + "tftp ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_MMCBOOTCOMMAND \ + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ + "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND + + +#endif /* __CONFIG_H */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 3e55247..f084834 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -484,7 +484,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + sizeof(CONFIG_SYS_PROMPT)+16) diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 9c25efe..386dbd8 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -13,7 +13,6 @@ /* * SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_MX27 #define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 8428d84..0f22032 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -15,8 +15,7 @@ #include <asm/arch/imx-regs.h> /* High Level Configuration Options */ -#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ -#define CONFIG_MX31 1 /* in a mx31 */ +#define CONFIG_MX31 1 /* This is a mx31 */ #define CONFIG_MX31_CLK32 32000 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index ffb67c2..4195fa3 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -15,8 +15,7 @@ #include <asm/arch/imx-regs.h> /* High Level Configuration Options */ -#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ -#define CONFIG_MX31 /* in a mx31 */ +#define CONFIG_MX31 /* This is a mx31 */ #define CONFIG_MX31_CLK32 32000 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 5a5f940..1b9c277 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -28,7 +28,6 @@ #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x00908000 #define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7" #define CONFIG_SPL_STACK 0x0091FFB8 #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT @@ -46,7 +45,7 @@ #if defined(CONFIG_SPL_MMC_SUPPORT) #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 138 /* offset 69KB */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024) #endif diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h index 98e819b..310d5e2 100644 --- a/include/configs/ipam390.h +++ b/include/configs/ipam390.h @@ -25,7 +25,6 @@ * SoC Configuration */ #define CONFIG_MACH_DAVINCI_DA850_EVM -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h index 759e112..8175621 100644 --- a/include/configs/jadecpu.h +++ b/include/configs/jadecpu.h @@ -14,7 +14,6 @@ #define CONFIG_MB86R0x_IOCLK get_bus_freq(0) #define CONFIG_SYS_TEXT_BASE 0x10000000 -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_USE_ARCH_MEMCPY #define CONFIG_USE_ARCH_MEMSET diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index ae6b6dc..940000e 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -8,6 +8,9 @@ #ifndef __CONFIG_KM83XX_H #define __CONFIG_KM83XX_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* include common defines/options for all Keymile boards */ #include "keymile-common.h" #include "km-powerpc.h" diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index a0f9d29..864e5f1 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -11,7 +11,7 @@ #define CONFIG_PHYS_64BIT #define CONFIG_PPC_P2041 -#define CONFIG_SYS_TEXT_BASE 0xfff80000 +#define CONFIG_SYS_TEXT_BASE 0xfff40000 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" @@ -21,6 +21,9 @@ #define CONFIG_NAND_ECC_BCH +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* common KM defines */ #include "keymile-common.h" @@ -235,7 +238,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Serial Port - controlled on board with jumper J8 diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h index 029c348..14fd290 100644 --- a/include/configs/km82xx.h +++ b/include/configs/km82xx.h @@ -29,6 +29,9 @@ #error ("Board unsupported") #endif +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #define CONFIG_SYS_TEXT_BASE 0xFE000000 /* include common defines/options for all Keymile boards */ @@ -204,9 +207,6 @@ "" #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif #define CONFIG_SYS_MONITOR_LEN (768 << 10) diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 3ccadd0..c14889c 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -10,33 +10,10 @@ #define __KOELSCH_H #undef DEBUG -#define CONFIG_ARMV7 #define CONFIG_R8A7791 #define CONFIG_RMOBILE_BOARD_STRING "Koelsch" -#define CONFIG_SH_GPIO_PFC - -#include <asm/arch/rmobile.h> - -#define CONFIG_CMD_EDITENV -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_DFL -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_RUN -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI - -#define CONFIG_FAT_WRITE -#define CONFIG_EXT4_WRITE + +#include "rcar-gen2-common.h" #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) #define CONFIG_SYS_TEXT_BASE 0x70000000 @@ -44,35 +21,6 @@ #define CONFIG_SYS_TEXT_BASE 0xE6304000 #endif -#define CONFIG_SYS_THUMB_BUILD -#define CONFIG_SYS_GENERIC_BOARD - -/* Support File sytems */ -#define CONFIG_DOS_PARTITION -#define CONFIG_SUPPORT_VFAT - - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_OF_LIBFDT -#define BOARD_LATE_INIT - -#define CONFIG_BAUDRATE 38400 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "" - -#define CONFIG_VERSION_VARIABLE -#undef CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_TMU_TIMER - /* STACK */ #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC @@ -85,41 +33,14 @@ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ -#define KOELSCH_SDRAM_BASE 0x40000000 -#define KOELSCH_SDRAM_SIZE (2048u * 1024 * 1024) -#define KOELSCH_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE 512 -#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SCIF */ #define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF0 #define CONFIG_SCIF_USE_EXT_CLK -#undef CONFIG_SYS_CONSOLE_INFO_QUIET -#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE - -#define CONFIG_SYS_MEMTEST_START (KOELSCH_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 504 * 1024 * 1024) -#undef CONFIG_SYS_ALT_MEMTEST -#undef CONFIG_SYS_MEMTEST_SCRATCH -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (KOELSCH_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (KOELSCH_UBOOT_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ #define CONFIG_SYS_NO_FLASH @@ -128,16 +49,6 @@ #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_BAR #define CONFIG_SPI_FLASH_SPANSION -/* ENV setting */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_ADDR 0xC0000 - -/* Common ENV setting */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_SECT_SIZE (256 * 1024) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) /* SH Ether */ #define CONFIG_NET_MULTI @@ -166,11 +77,8 @@ #define CONFIG_SYS_I2C_SH #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 -#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 #define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 #define CONFIG_SYS_I2C_SH_SPEED1 400000 -#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 #define CONFIG_SYS_I2C_SH_SPEED2 400000 #define CONFIG_SH_I2C_DATA_HIGH 4 #define CONFIG_SH_I2C_DATA_LOW 5 @@ -184,4 +92,15 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USB_STORAGE + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF*/ +#define CONFIG_SMSTP2_ENA 0x00002000 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 +/* SCIF0 */ +#define CONFIG_SMSTP7_ENA 0x00200000 + #endif /* __KOELSCH_H */ diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index dd5050f..42280ca 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -20,7 +20,6 @@ #define CONFIG_SYS_THUMB_BUILD /* SoC Configuration */ -#define CONFIG_ARMV7 #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_ARCH_TIMER #define CONFIG_SYS_TEXT_BASE 0x0c001000 diff --git a/include/configs/lager.h b/include/configs/lager.h index a814b4c..291267f 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -2,7 +2,7 @@ * include/configs/lager.h * This file is lager board configuration. * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013, 2014 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0 */ @@ -11,67 +11,16 @@ #define __LAGER_H #undef DEBUG -#define CONFIG_ARMV7 #define CONFIG_R8A7790 #define CONFIG_RMOBILE_BOARD_STRING "Lager" -#define CONFIG_SH_GPIO_PFC - -#include <asm/arch/rmobile.h> - -#define CONFIG_CMD_EDITENV -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_DFL -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_RUN -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI - -#define CONFIG_FAT_WRITE -#define CONFIG_EXT4_WRITE + +#include "rcar-gen2-common.h" #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) #define CONFIG_SYS_TEXT_BASE 0xB0000000 #else #define CONFIG_SYS_TEXT_BASE 0xE8080000 #endif -#define CONFIG_SYS_THUMB_BUILD -#define CONFIG_SYS_GENERIC_BOARD - -/* Support File sytems */ -#define CONFIG_DOS_PARTITION -#define CONFIG_SUPPORT_VFAT - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING -#define CONFIG_OF_LIBFDT - -/* #define CONFIG_OF_LIBFDT */ -#define BOARD_LATE_INIT - -#define CONFIG_BAUDRATE 38400 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "" - -#define CONFIG_VERSION_VARIABLE -#undef CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_TMU_TIMER /* STACK */ #if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) @@ -84,43 +33,16 @@ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ -#define LAGER_SDRAM_BASE 0x40000000 -#define LAGER_SDRAM_SIZE (2048u * 1024 * 1024) -#define LAGER_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE 512 -#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SCIF */ #define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF0 #define CONFIG_SCIF_USE_EXT_CLK -#undef CONFIG_SYS_CONSOLE_INFO_QUIET -#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE - -#define CONFIG_SYS_MEMTEST_START (LAGER_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 504 * 1024 * 1024) -#undef CONFIG_SYS_ALT_MEMTEST -#undef CONFIG_SYS_MEMTEST_SCRATCH -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (LAGER_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (LAGER_UBOOT_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* USE SPI */ + +/* SPI */ #define CONFIG_SPI #define CONFIG_SPI_FLASH_BAR #define CONFIG_SH_QSPI @@ -128,17 +50,6 @@ #define CONFIG_SPI_FLASH_SPANSION #define CONFIG_SYS_NO_FLASH -/* ENV setting */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_ADDR 0xC0000 - -/* Common ENV setting */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_SECT_SIZE (256 * 1024) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) - /* SH Ether */ #define CONFIG_NET_MULTI #define CONFIG_SH_ETHER @@ -156,13 +67,9 @@ /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_RCAR -#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 #define CONFIG_SYS_RCAR_I2C0_SPEED 400000 -#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 #define CONFIG_SYS_RCAR_I2C1_SPEED 400000 -#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000 #define CONFIG_SYS_RCAR_I2C2_SPEED 400000 -#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000 #define CONFIG_SYS_RCAR_I2C3_SPEED 400000 #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 @@ -186,4 +93,23 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_USB_STORAGE +/* MMC */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC + +#define CONFIG_SH_MMCIF +#define CONFIG_SH_MMCIF_ADDR 0xEE220000 +#define CONFIG_SH_MMCIF_CLK 97500000 + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF */ +#define CONFIG_SMSTP2_ENA 0x00002000 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 +/* SCIF0 */ +#define CONFIG_SMSTP7_ENA 0x00200000 + #endif /* __LAGER_H */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d1f6ea7..8dc04f2 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -37,8 +37,85 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define CONFIG_QIXIS_I2C_ACCESS +#else #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#endif + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x40010000 +#define CONFIG_SYS_NO_FLASH +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 @@ -70,9 +147,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_HAS_SERDES #define CONFIG_FSL_CAAM /* Enable CAAM */ + +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ + !defined(CONFIG_QSPI_BOOT) +#define CONFIG_U_QE +#endif + /* * IFC Definitions */ +#ifndef CONFIG_QSPI_BOOT #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -110,6 +194,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ @@ -164,6 +249,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif /* * QIXIS Definitions @@ -208,6 +294,40 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FPGA_FTIM3 0x0 #endif +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK @@ -240,6 +360,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#endif /* * Serial Port @@ -273,6 +394,38 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_ESDHC #define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* QSPI */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_FSL_QSPI +#define QSPI0_AMBA_BASE 0x40000000 +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#endif + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#endif +#endif + /* * eTSEC */ @@ -318,6 +471,14 @@ unsigned long get_board_ddr_clk(void); #endif #endif + +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII @@ -325,13 +486,28 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING + +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_CMD_IMLS +#else #define CONFIG_CMD_IMLS +#endif + +#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_LS102XA_NS_ACCESS +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CONFIG_TIMER_CLK_FREQ 12500000 +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #define CONFIG_BOOTDELAY 3 +#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 + #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "fdt_high=0xcfffffff\0" \ @@ -344,7 +520,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE \ @@ -361,6 +536,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_LOAD_ADDR 0x82000000 +#define CONFIG_LS102XA_STREAM_ID + /* * Stack sizes * The stack sizes are set up in start.S using the settings below @@ -372,17 +549,37 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif /* * Environment */ #define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_NAND_BOOT) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 3c73af8..66954d0 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -35,6 +35,43 @@ #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x40010000 +#define CONFIG_SYS_NO_FLASH +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -50,9 +87,15 @@ #define CONFIG_FSL_CAAM /* Enable CAAM */ +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ + !defined(CONFIG_QSPI_BOOT) +#define CONFIG_U_QE +#endif + /* * IFC Definitions */ +#ifndef CONFIG_QSPI_BOOT #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -95,6 +138,8 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA +#endif /* CPLD */ @@ -156,6 +201,17 @@ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +/* EEPROM */ +#ifndef CONFIG_SD_BOOT +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#endif + /* * MMC */ @@ -164,6 +220,21 @@ #define CONFIG_FSL_ESDHC #define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* QSPI */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_FSL_QSPI +#define QSPI0_AMBA_BASE 0x40000000 +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#endif + /* * Video */ @@ -220,6 +291,13 @@ #define CONFIG_HAS_ETH2 #endif +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII @@ -227,7 +305,20 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING + +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_CMD_IMLS +#else #define CONFIG_CMD_IMLS +#endif + +#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_LS102XA_NS_ACCESS +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CONFIG_TIMER_CLK_FREQ 12500000 +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 @@ -245,7 +336,6 @@ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE \ @@ -262,6 +352,8 @@ #define CONFIG_SYS_LOAD_ADDR 0x82000000 +#define CONFIG_LS102XA_STREAM_ID + /* * Stack sizes * The stack sizes are set up in start.S using the settings below @@ -273,17 +365,35 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 /* * Environment */ #define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x20000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 58e7295..d43db52 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -671,8 +671,6 @@ #define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */ #define CONFIG_SYS_SPL_MAX_LEN (64 << 10) #define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */ -#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/ppc4xx" -#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/ppc4xx/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ #define CONFIG_SPL_SERIAL_SUPPORT diff --git a/include/configs/mcx.h b/include/configs/mcx.h index b775ebd..26eb220 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -369,7 +369,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" /* NAND boot config */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 86ce5f2..955d0e2 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -124,7 +124,6 @@ #ifdef CONFIG_SYS_USE_DATAFLASH # define CONFIG_ATMEL_DATAFLASH_SPI # define CONFIG_HAS_DATAFLASH -# define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) # define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 # define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ # define AT91_SPI_CLK 15000000 diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h index 7343c94..df2ecc1 100644 --- a/include/configs/muas3001.h +++ b/include/configs/muas3001.h @@ -206,10 +206,6 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */ #define CONFIG_ENV_IS_IN_FLASH diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 51b1a14..0f4bd91 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -12,8 +12,7 @@ #include <asm/arch/imx-regs.h> /* High Level Configuration Options */ -#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ -#define CONFIG_MX31 1 /* in a mx31 */ +#define CONFIG_MX31 1 /* This is a mx31 */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index bc4583b..2a3e53c 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -17,8 +17,7 @@ #include <asm/arch/imx-regs.h> /* High Level Configuration Options */ -#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ -#define CONFIG_MX31 /* in a mx31 */ +#define CONFIG_MX31 /* This is a mx31 */ #define CONFIG_SYS_GENERIC_BOARD diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index ab48144..a145f08 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -16,7 +16,6 @@ #include <asm/arch/imx-regs.h> /* High Level Configuration Options */ -#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX35 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index a74508c..42bc3c8 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -94,6 +94,7 @@ /* Command definition */ #include <config_cmd_default.h> #define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD #undef CONFIG_CMD_IMLS @@ -107,7 +108,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ - "fdt_file=imx53-qsb.dtb\0" \ "fdt_addr=0x71000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 235dd6d..51042ca 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -37,6 +37,16 @@ #include "mx6sabre_common.h" +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO + #define CONFIG_SYS_FSL_USDHC_NUM 2 #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 0 @@ -48,4 +58,26 @@ #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 +/* NAND flash command */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + #endif /* __MX6QSABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index c81e9e9..f0f721e 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -25,6 +25,11 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_DM +#define CONFIG_DM_THERMAL +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_IMX6_THERMAL + #define CONFIG_SYS_GENERIC_BOARD /* Size of malloc() pool */ @@ -37,7 +42,7 @@ #define CONFIG_MXC_UART #define CONFIG_CMD_FUSE -#ifdef CONFIG_CMD_FUSE +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL) #define CONFIG_MXC_OCOTP #endif @@ -215,9 +220,6 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE @@ -251,7 +253,7 @@ #define CONFIG_ENV_IS_IN_MMC #if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_OFFSET (8 * 64 * 1024) #endif #define CONFIG_OF_LIBFDT diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 938030d..a346542 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -12,6 +12,12 @@ #include <asm/arch/imx-regs.h> #include <asm/imx-common/gpio.h> +#ifdef CONFIG_SPL +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#include "imx6_spl.h" +#endif + #define CONFIG_MACH_TYPE 3980 #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONSOLE_DEV "ttymxc0" diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index bd57159..e3e7f76 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -87,7 +87,7 @@ "fdt_addr=0x88000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=0\0" \ + "mmcdev=1\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 8edf187..61a7a7a 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -59,7 +59,7 @@ "fdt_addr=0x88000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=0\0" \ + "mmcdev=2\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ @@ -222,13 +222,22 @@ #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif +#define CONFIG_DM +#define CONFIG_DM_THERMAL +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_IMX6_THERMAL + +#define CONFIG_CMD_FUSE +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL) +#define CONFIG_MXC_OCOTP +#endif + /* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_OFFSET (6 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ @@ -237,4 +246,9 @@ #define CONFIG_CMD_CACHE #endif +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/ +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h index 5419f55..52cde41 100644 --- a/include/configs/nhk8815.h +++ b/include/configs/nhk8815.h @@ -12,7 +12,6 @@ #include <nomadik.h> -#define CONFIG_ARM926EJS #define CONFIG_NOMADIK_8815 /* cpu variant */ #define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index b928af8..807e96b 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -198,6 +198,19 @@ #define CONFIG_CMD_GPIO +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_EXYNOS +#define CONFIG_USB_STORAGE + +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX + /* * Supported Odroid boards: X3, U3 * TODO: Add Odroid X support diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 27bf89c..8bdc08f 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -75,7 +75,7 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" /* Partition tables */ diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h index 2daf13c..1185f42 100644 --- a/include/configs/omap3_evm_quick_mmc.h +++ b/include/configs/omap3_evm_quick_mmc.h @@ -87,7 +87,7 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif /* __OMAP3_EVM_QUICK_MMC_H */ diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index f3c21c4..bf1d34d 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -18,7 +18,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */ #define CONFIG_MACH_TYPE MACH_TYPE_MVBLX diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index e8dc462..e07795f 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -23,6 +23,7 @@ #define CONFIG_SYS_NS16550_COM3 UART3_BASE #define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R /* MMC ENV related defines */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ diff --git a/include/configs/origen.h b/include/configs/origen.h index da9d6a1..8f1e256 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -56,6 +56,10 @@ #undef CONFIG_CMD_PING #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS @@ -63,7 +67,36 @@ #define COPY_BL2_FNPTR_ADDR 0x02020030 #define CONFIG_SPL_TEXT_BASE 0x02021410 -#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x40007000\0" \ + "rdaddr=0x48000000\0" \ + "kerneladdr=0x40007000\0" \ + "ramdiskaddr=0x48000000\0" \ + "console=ttySAC2,115200n8\0" \ + "mmcdev=0\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "fi; " \ + "fi;" \ + "load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} " #define CONFIG_IDENT_STRING " for ORIGEN" diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index d7696bd..9512b1e 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -83,6 +83,13 @@ #define CONFIG_GENERIC_MMC #define CONFIG_BOUNCE_BUFFER +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + #ifdef CONFIG_MX6Q #define CONFIG_CMD_SATA #endif diff --git a/include/configs/otc570.h b/include/configs/otc570.h index 629967d..2390beb 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -174,7 +174,6 @@ #ifdef CONFIG_SYS_USE_DATAFLASH # define CONFIG_ATMEL_DATAFLASH_SPI # define CONFIG_HAS_DATAFLASH -# define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) # define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 # define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ # define AT91_SPI_CLK 15000000 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 9b58950..5f27c2a 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -80,6 +80,16 @@ #define __SW_BOOT_NAND 0x44 #define __SW_BOOT_PCIE 0x74 #define CONFIG_SYS_L2_SIZE (256 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=ec000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ + "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" #endif #if defined(CONFIG_P1021RDB) @@ -98,6 +108,24 @@ #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c #define CONFIG_SYS_L2_SIZE (256 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#ifdef CONFIG_PHYS_64BIT +#define MTDIDS_DEFAULT "nor0=fef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9728k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" +#else +#define MTDIDS_DEFAULT "nor0=ef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9728k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" +#endif #endif #if defined(CONFIG_P1024RDB) @@ -145,6 +173,22 @@ #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 #define CONFIG_SYS_L2_SIZE (512 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#ifdef CONFIG_PHYS_64BIT +#define MTDIDS_DEFAULT "nor0=fef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +#else +#define MTDIDS_DEFAULT "nor0=ef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +#endif #endif #ifdef CONFIG_SDCARD diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 911203d..9864c15 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -10,6 +10,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #if defined(CONFIG_TWR_P1025) #define CONFIG_BOARDNAME "TWR-P1025" #define CONFIG_P1025 @@ -389,6 +391,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_TWR-P1025 */ /* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=ec000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),5632k(kernel),57856k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" + +/* * Environment */ #ifdef CONFIG_SYS_RAMBOOT diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 1c04a58..61e6af3 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -15,6 +15,9 @@ #define CONFIG_PB1X00 1 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifdef CONFIG_PB1000 #define CONFIG_SOC_AU1000 1 #else diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h new file mode 100644 index 0000000..8a82402 --- /dev/null +++ b/include/configs/peach-pi.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * + * Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PEACH_PI_H +#define __CONFIG_PEACH_PI_H + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) + +#include <configs/exynos5420-common.h> +#include <configs/exynos5-dt-common.h> + +#define CONFIG_BOARD_COMMON + +/* select serial console configuration */ +#define CONFIG_SERIAL3 /* use SERIAL 3 */ + +#define CONFIG_SYS_PROMPT "Peach-Pi # " +#define CONFIG_IDENT_STRING " for Peach-Pi" + +#define CONFIG_VIDEO_PARADE + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPP LCD_COLOR16 +#endif + +#define CONFIG_POWER_TPS65090_EC +#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ +#define CONFIG_DM_CROS_EC + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + +#endif /* __CONFIG_PEACH_PI_H */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 91bd37d..ad5db57 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -23,8 +23,8 @@ /* select serial console configuration */ #define CONFIG_SERIAL3 /* use SERIAL 3 */ -#define CONFIG_SYS_PROMPT "Peach # " -#define CONFIG_IDENT_STRING " for Peach" +#define CONFIG_SYS_PROMPT "Peach-Pit # " +#define CONFIG_IDENT_STRING " for Peach-Pit" #define CONFIG_VIDEO_PARADE @@ -43,4 +43,8 @@ #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 4 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + #endif /* __CONFIG_PEACH_PIT_H */ diff --git a/include/configs/ph1_ld4.h b/include/configs/ph1_ld4.h deleted file mode 100644 index 73a95e6..0000000 --- a/include/configs/ph1_ld4.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PH1_XXX_H -#define __PH1_XXX_H - -/* - * Support Card Select - * - * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC. - * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card. - * CPLD is re-programmed for ARIMA board compatibility. - * No define - No support card. - */ - -#if 0 -#define CONFIG_PFC_MICRO_SUPPORT_CARD -#else -#define CONFIG_DCC_MICRO_SUPPORT_CARD -#endif - -/* - * Serial Configuration - * SoC UART : enable CONFIG_UNIPHIER_SERIAL - * On-board UART: enable CONFIG_SYS_NS16550_SERIAL - */ -#if 0 -#define CONFIG_SYS_NS16550_SERIAL -#endif - -#define CONFIG_SMC911X - -#define CONFIG_DDR_NUM_CH0 1 -#define CONFIG_DDR_NUM_CH1 1 - -/* - * Memory Size & Mapping - */ -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x10000000 -#define CONFIG_SDRAM1_BASE 0x90000000 -#define CONFIG_SDRAM1_SIZE 0x10000000 - -#define CONFIG_SPL_TEXT_BASE 0x40000 - -#include "uniphier-common.h" - -#endif /* __PH1_XXX_H */ diff --git a/include/configs/ph1_pro4.h b/include/configs/ph1_pro4.h deleted file mode 100644 index fc5132d..0000000 --- a/include/configs/ph1_pro4.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PH1_XXX_H -#define __PH1_XXX_H - -/* - * Support Card Select - * - * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC. - * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card. - * CPLD is re-programmed for ARIMA board compatibility. - * No define - No support card. - */ - -#if 0 -#define CONFIG_PFC_MICRO_SUPPORT_CARD -#else -#define CONFIG_DCC_MICRO_SUPPORT_CARD -#endif - -/* - * Serial Configuration - * SoC UART : enable CONFIG_UNIPHIER_SERIAL - * On-board UART: enable CONFIG_SYS_NS16550_SERIAL - */ -#if 0 -#define CONFIG_SYS_NS16550_SERIAL -#endif - -#define CONFIG_SMC911X - -#define CONFIG_DDR_NUM_CH0 2 -#define CONFIG_DDR_NUM_CH1 2 - -#define CONFIG_UNIPHIER_SMP - -/* - * Memory Size & Mapping - */ -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x20000000 -#define CONFIG_SDRAM1_BASE 0xa0000000 -#define CONFIG_SDRAM1_SIZE 0x20000000 - -#define CONFIG_SPL_TEXT_BASE 0x100000 - -#include "uniphier-common.h" - -#endif /* __PH1_XXX_H */ diff --git a/include/configs/ph1_sld8.h b/include/configs/ph1_sld8.h deleted file mode 100644 index e2f1102..0000000 --- a/include/configs/ph1_sld8.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PH1_XXX_H -#define __PH1_XXX_H - -/* - * Support Card Select - * - * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC. - * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card. - * CPLD is re-programmed for ARIMA board compatibility. - * No define - No support card. - */ - -#if 0 -#define CONFIG_PFC_MICRO_SUPPORT_CARD -#else -#define CONFIG_DCC_MICRO_SUPPORT_CARD -#endif - -/* - * Serial Configuration - * SoC UART : enable CONFIG_UNIPHIER_SERIAL - * On-board UART: enable CONFIG_SYS_NS16550_SERIAL - */ -#if 0 -#define CONFIG_SYS_NS16550_SERIAL -#endif - -#define CONFIG_SMC911X - -#define CONFIG_DDR_NUM_CH0 1 -#define CONFIG_DDR_NUM_CH1 1 - -/* #define CONFIG_DDR_STANDARD */ - -/* - * Memory Size & Mapping - */ -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x10000000 -#define CONFIG_SDRAM1_BASE 0x90000000 -#define CONFIG_SDRAM1_SIZE 0x10000000 - -#define CONFIG_SPL_TEXT_BASE 0x40000 - -#include "uniphier-common.h" - -#endif /* __PH1_XXX_H */ diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 4a71927..0746056 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -202,7 +202,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index d9c04d1..f0f12af 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -216,7 +216,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define AT91_SPI_CLK 15000000 diff --git a/include/configs/pr1.h b/include/configs/pr1.h index 0f57e86..13fb675 100644 --- a/include/configs/pr1.h +++ b/include/configs/pr1.h @@ -102,8 +102,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C -#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index d75d562..946b2c8 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -150,4 +150,8 @@ #define CONFIG_SYS_CONSOLE_FG_COL 0x00 #endif +#ifndef CONFIG_SPL_BUILD +#define CONFIG_FIT +#endif + #endif /* ! __CONFIG_PXM2_H */ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 98ed8bc..1548d3e 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -13,6 +13,9 @@ #define __CONFIG_H #define CONFIG_QEMU_MIPS + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_R #define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index e8f5a4c..61cafad 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -13,6 +13,9 @@ #define __CONFIG_H #define CONFIG_QEMU_MIPS + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_R #define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ diff --git a/include/configs/qong.h b/include/configs/qong.h index f9d6642..d383fe8 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -12,8 +12,7 @@ #include <asm/arch/imx-regs.h> /* High Level Configuration Options */ -#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ -#define CONFIG_MX31 /* in a mx31 */ +#define CONFIG_MX31 /* This is a mx31 */ #define CONFIG_QONG #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h new file mode 100644 index 0000000..c33f1cb --- /dev/null +++ b/include/configs/rcar-gen2-common.h @@ -0,0 +1,99 @@ +/* + * include/configs/rcar-gen2-common.h + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __RCAR_GEN2_COMMON_H +#define __RCAR_GEN2_COMMON_H + +#include <asm/arch/rmobile.h> + +#define CONFIG_CMD_EDITENV +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_DFL +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_RUN +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE + +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_SYS_GENERIC_BOARD + +/* Support File sytems */ +#define CONFIG_FAT_WRITE +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT +#define CONFIG_FS_EXT4 +#define CONFIG_EXT4_WRITE + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING +#define CONFIG_OF_LIBFDT + +#define CONFIG_BAUDRATE 38400 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "" + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_TMU_TIMER +#define CONFIG_SH_GPIO_PFC + +/* console */ +#undef CONFIG_SYS_CONSOLE_INFO_QUIET +#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE 512 +#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } + +#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) +#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + +/* ENV setting */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_ADDR 0xC0000 + +/* Common ENV setting */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SECT_SIZE (256 * 1024) +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) + +#endif /* __RCAR_GEN2_COMMON_H */ diff --git a/include/configs/rpi_b.h b/include/configs/rpi.h index ca27f9a..4d5426e 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi.h @@ -21,7 +21,6 @@ /* Architecture, CPU, etc.*/ #define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_ARM1176 #define CONFIG_BCM2835 #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_DCACHE_OFF @@ -106,15 +105,15 @@ /* Environment */ #define CONFIG_ENV_SIZE SZ_16K -#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_FAT_WRITE #define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_SYS_LOAD_ADDR 0x1000000 #define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_PREBOOT \ - "if load mmc 0:1 ${loadaddr} /uEnv.txt; then " \ - "env import -t -r ${loadaddr} ${filesize}; " \ - "fi" /* Shell */ #define CONFIG_SYS_MAXARGS 8 @@ -139,7 +138,6 @@ /* Some things don't make sense on this HW or yet */ #undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_SAVEENV /* Environment */ #define ENV_DEVICE_SETTINGS \ @@ -176,7 +174,6 @@ "pxefile_addr_r=0x00100000\0" \ "kernel_addr_r=0x01000000\0" \ "fdt_addr_r=0x02000000\0" \ - "fdtfile=bcm2835-rpi-b.dtb\0" \ "ramdisk_addr_r=0x02100000\0" \ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h index 5436324..e7f7387 100644 --- a/include/configs/rsk7203.h +++ b/include/configs/rsk7203.h @@ -11,7 +11,6 @@ #define __RSK7203_H #undef DEBUG -#define CONFIG_SH2A 1 #define CONFIG_CPU_SH7203 1 #define CONFIG_RSK7203 1 diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h index 4aaa3ef..2ecf785 100644 --- a/include/configs/rsk7264.h +++ b/include/configs/rsk7264.h @@ -12,7 +12,6 @@ #define __RSK7264_H #undef DEBUG -#define CONFIG_SH2A 1 #define CONFIG_CPU_SH7264 1 #define CONFIG_RSK7264 1 diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h index 11fc231..14c1da7 100644 --- a/include/configs/rsk7269.h +++ b/include/configs/rsk7269.h @@ -11,7 +11,6 @@ #define __RSK7269_H #undef DEBUG -#define CONFIG_SH2A 1 #define CONFIG_CPU_SH7269 1 #define CONFIG_RSK7269 1 diff --git a/include/configs/rut.h b/include/configs/rut.h index 6bddede..0067ea4 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -154,4 +154,8 @@ #define CONFIG_SYS_CONSOLE_FG_COL 0x00 #endif +#ifndef CONFIG_SPL_BUILD +#define CONFIG_FIT +#endif + #endif /* ! __CONFIG_RUT_H */ diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 5b77db2..d5588b1 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -230,7 +230,7 @@ #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index dfbf3cb..f2849d7 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -276,7 +276,7 @@ #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h new file mode 100644 index 0000000..104edef --- /dev/null +++ b/include/configs/sama5d4_xplained.h @@ -0,0 +1,216 @@ +/* + * Configuration settings for the SAMA5D4 Xplained ultra board. + * + * Copyright (C) 2014 Atmel + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/hardware.h> + +#define CONFIG_SYS_TEXT_BASE 0x26f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT /* Device Tree support */ + +#define CONFIG_SYS_GENERIC_BOARD + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_USART3 +#define CONFIG_USART_ID ATMEL_ID_USART3 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SETEXPR + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* SerialFlash */ +#define CONFIG_CMD_SF + +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI +#define CONFIG_ATMEL_SPI0 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#endif + +/* NAND flash */ +#define CONFIG_CMD_NAND + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#endif + +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1 +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE +#endif + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +/* LCD */ +/* #define CONFIG_LCD */ +#ifdef CONFIG_LCD +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP 24 +#define CONFIG_LCD_LOGO +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_HLCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#endif + +#ifdef CONFIG_SYS_USE_SERIALFLASH +/* bootstrap + u-boot + env + linux in serial flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x21000000 0xa0000 0x60000; " \ + "sf read 0x22000000 0x100000 0x300000; " \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_NANDFLASH +/* bootstrap + u-boot + env in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET_REDUND 0x100000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ + "nand read 0x22000000 0x200000 0x600000;" \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_MMC +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define FAT_ENV_INTERFACE "mmc" +/* + * We don't specify the part number, if device 0 has partition table, it means + * the first partition; it no partition table, then take whole device as a + * FAT file system. + */ +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d4_xplained.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#endif + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "root=/dev/mmcblk0p2 rw rootwait" +#else +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256K(env),256k(evn_redundent),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#endif diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h new file mode 100644 index 0000000..cbdb3a2 --- /dev/null +++ b/include/configs/sama5d4ek.h @@ -0,0 +1,214 @@ +/* + * Configuration settings for the SAMA5D4EK board. + * + * Copyright (C) 2014 Atmel + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/hardware.h> + +#define CONFIG_SYS_TEXT_BASE 0x26f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT /* Device Tree support */ + +#define CONFIG_SYS_GENERIC_BOARD + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_USART3 +#define CONFIG_USART_ID ATMEL_ID_USART3 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SETEXPR + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* SerialFlash */ +#define CONFIG_CMD_SF + +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI +#define CONFIG_ATMEL_SPI0 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#endif + +/* NAND flash */ +#define CONFIG_CMD_NAND + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#endif + +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1 +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE +#endif + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +/* LCD */ +#define CONFIG_LCD +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP 18 +#define CONFIG_LCD_LOGO +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_HLCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#ifdef CONFIG_SYS_USE_SERIALFLASH +/* bootstrap + u-boot + env + linux in serial flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x21000000 0xa0000 0x60000; " \ + "sf read 0x22000000 0x100000 0x300000; " \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_NANDFLASH +/* bootstrap + u-boot + env in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET_REDUND 0x100000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ + "nand read 0x22000000 0x200000 0x600000;" \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_MMC +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define FAT_ENV_INTERFACE "mmc" +/* + * We don't specify the part number, if device 0 has partition table, it means + * the first partition; it no partition table, then take whole device as a + * FAT file system. + */ +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 sama5d4ek.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#endif + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "root=/dev/mmcblk0p2 rw rootwait" +#else +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256K(env),256k(evn_redundent),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index ee4b244..2b03841 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -48,6 +48,7 @@ #define CONFIG_ANDROID_BOOT_IMAGE #define CONFIG_FS_FAT +#define CONFIG_FAT_WRITE #define CONFIG_FS_EXT4 #define CONFIG_EXT4_WRITE #define CONFIG_CMD_FAT @@ -57,6 +58,7 @@ #define CONFIG_DOS_PARTITION #define CONFIG_HOST_MAX_DEVICES 4 #define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_MD5SUM #define CONFIG_SYS_VSNPRINTF diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h index a1b5751..e7c35ec 100644 --- a/include/configs/sbc35_a9g20.h +++ b/include/configs/sbc35_a9g20.h @@ -80,7 +80,6 @@ #define CONFIG_SPI #define CONFIG_CMD_SPI #define CONFIG_ATMEL_SPI -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_CMD_EEPROM #define CONFIG_SPI_M95XXX diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index f28f350..aee0d9e 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -13,6 +13,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Top level Makefile configuration choices */ diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index e6d272d..f4a40bb 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -10,8 +10,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */ -#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */ +#define CONFIG_IMX 1 /* This is a Motorola MC9328MXL Chip */ #define CONFIG_SCB9328 1 /* on a scb9328tronix board */ #define CONFIG_IMX_SERIAL diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index f06abbc..2d509a9 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -10,7 +10,6 @@ #define __SH7752EVB_H #undef DEBUG -#define CONFIG_SH_32BIT 1 #define CONFIG_CPU_SH7752 1 #define CONFIG_SH7752EVB 1 diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index e400db0..c31dd7a 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -10,7 +10,6 @@ #define __SH7753EVB_H #undef DEBUG -#define CONFIG_SH_32BIT 1 #define CONFIG_CPU_SH7753 1 #define CONFIG_SH7753EVB 1 diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index 08bff1d..36afd5f 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -10,7 +10,6 @@ #define __SH7757LCR_H #undef DEBUG -#define CONFIG_SH_32BIT 1 #define CONFIG_CPU_SH7757 1 #define CONFIG_SH7757LCR 1 #define CONFIG_SH7757LCR_DDR_ECC 1 diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 0d5dba1..21e13e5 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -148,7 +148,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index d4ae19f..71eb81c 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -17,13 +17,14 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */ #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ #define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */ #define CONFIG_SYS_TEXT_BASE 0x0 +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH /* input clock of PLL (the SMDK2410 has 12MHz input clock) */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index fd2d482..5c9a3c0 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -23,4 +23,8 @@ #define CONFIG_IDENT_STRING " for SMDK5420" #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + #endif /* __CONFIG_SMDK5420_H */ diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 1ebee71..942af2e 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -15,11 +15,17 @@ #include <asm/hardware.h> #include <linux/sizes.h> -#define CONFIG_SYS_TEXT_BASE 0x20000000 +#define CONFIG_SYS_TEXT_BASE 0x21f00000 /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) /* CPU */ #define CONFIG_ARCH_CPU_INIT @@ -84,8 +90,10 @@ /* UARTs/Serial console */ #define CONFIG_ATMEL_USART +#ifndef CONFIG_DM_SERIAL #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS +#endif #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_PROMPT "Snapper> " @@ -159,7 +167,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_FAT #define CONFIG_CMD_I2C -#undef CONFIG_CMD_GPIO +#define CONFIG_CMD_GPIO #define CONFIG_CMD_USB #define CONFIG_CMD_MII #define CONFIG_CMD_NAND diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c436fda..c4ac94d 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -11,7 +11,6 @@ /* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_ARMV7 #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SOCFPGA diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h new file mode 100644 index 0000000..fd9bd63 --- /dev/null +++ b/include/configs/stv0991.h @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2014 + * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_STV0991_H +#define __CONFIG_STV0991_H +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_CORTEX_R4 + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_NO_FLASH + +/* ram memory-related information */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define PHYS_SDRAM_1_SIZE 0x00198000 + +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR \ + (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) +#define CONFIG_SYS_MALLOC_F_LEN 0x2000 + +#define CONFIG_DM +/* serial port (PL011) configuration */ +#define CONFIG_BAUDRATE 115200 +#ifdef CONFIG_DM +#define CONFIG_DM_SERIAL +#define CONFIG_PL01X_SERIAL +#else +#define CONFIG_SYS_SERIAL0 0x80406000 +#define CONFIG_CONS_INDEX 0 +#define CONFIG_PL011_SERIAL +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} +#define CONFIG_PL011_CLOCK (2700 * 1000) +#endif + +/* user interface */ +#define CONFIG_SYS_PROMPT "STV0991> " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) + +/* MISC */ +#define CONFIG_SYS_LOAD_ADDR 0x00000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +/* U-boot Load Address */ +#define CONFIG_SYS_TEXT_BASE 0x00010000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* GMAC related configs */ + +#define CONFIG_MII +#define CONFIG_PHYLIB +#define CONFIG_CMD_NET +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_PHY_MICREL + +/* Command support defines */ +#define CONFIG_CMD_PING +#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ + +#include "config_cmd_default.h" +#undef CONFIG_CMD_SAVEENV + +#define CONFIG_SYS_MEMTEST_START 0x0000 +#define CONFIG_SYS_MEMTEST_END 1024*1024 +#define CONFIG_CMD_MEMTEST + +/* Misc configuration */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTCOMMAND "go 0x40040000" +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_PROMPT \ + "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay + +#endif /* __CONFIG_H */ diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index ea40790..ccec50c 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -22,12 +22,10 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif -#define CONFIG_ARMV7_VIRT 1 -#define CONFIG_ARMV7_NONSEC 1 #define CONFIG_ARMV7_PSCI 1 -#define CONFIG_ARMV7_PSCI_NR_CPUS 2 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE #define CONFIG_SYS_CLK_FREQ 24000000 +#define CONFIG_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ /* * Include common sunxi configuration where most the settings are diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index ce038ed..3f890b2 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -197,6 +197,36 @@ #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_CMD_GPIO +#ifdef CONFIG_VIDEO +/* + * The amount of RAM that is reserved for the FB. This will not show up as + * RAM to the kernel, but will be reclaimed by a KMS driver in future. + */ +#define CONFIG_SUNXI_FB_SIZE (8 << 20) + +/* Do we want to initialize a simple FB? */ +#define CONFIG_VIDEO_DT_SIMPLEFB + +#define CONFIG_VIDEO_SUNXI + +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VIDEO_LOGO + +/* allow both serial and cfb console. */ +#define CONFIG_CONSOLE_MUX +/* stop x86 thinking in cfbconsole from trying to init a pc keyboard */ +#define CONFIG_VGA_AS_SINGLE_DEVICE + +#define CONFIG_SYS_MEM_TOP_HIDE ((CONFIG_SUNXI_FB_SIZE + 0xFFF) & ~0xFFF) + +/* To be able to hook simplefb into dt */ +#ifdef CONFIG_VIDEO_DT_SIMPLEFB +#define CONFIG_OF_BOARD_SETUP +#endif + +#endif /* CONFIG_VIDEO */ + /* Ethernet support */ #ifdef CONFIG_SUNXI_EMAC #define CONFIG_MII /* MII PHY management */ @@ -217,6 +247,13 @@ #define CONFIG_USB_STORAGE #endif +#ifdef CONFIG_USB_KEYBOARD +#define CONFIG_CONSOLE_MUX +#define CONFIG_PREBOOT +#define CONFIG_SYS_STDIO_DEREGISTER +#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE +#endif + #if !defined CONFIG_ENV_IS_IN_MMC && \ !defined CONFIG_ENV_IS_IN_NAND && \ !defined CONFIG_ENV_IS_IN_FAT && \ @@ -225,6 +262,7 @@ #endif #define CONFIG_MISC_INIT_R +#define CONFIG_SYS_CONSOLE_IS_IN_ENV #ifndef CONFIG_SPL_BUILD #include <config_distro_defaults.h> @@ -266,7 +304,31 @@ #include <config_distro_bootcmd.h> +#ifdef CONFIG_USB_KEYBOARD +#define CONSOLE_STDIN_SETTINGS \ + "preboot=usb start\0" \ + "stdin=serial,usbkbd\0" +#else +#define CONSOLE_STDIN_SETTINGS \ + "stdin=serial\0" +#endif + +#ifdef CONFIG_VIDEO +#define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" +#else +#define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial\0" \ + "stderr=serial\0" +#endif + +#define CONSOLE_ENV_SETTINGS \ + CONSOLE_STDIN_SETTINGS \ + CONSOLE_STDOUT_SETTINGS + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONSOLE_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "fdtfile=" CONFIG_FDTFILE "\0" \ "console=ttyS0,115200\0" \ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index d687717..7d2c0d2 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -16,7 +16,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP_GPIO @@ -305,7 +304,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_BOARD_INIT diff --git a/include/configs/taurus.h b/include/configs/taurus.h index aadf4cd..20194ae 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -34,7 +34,7 @@ */ -#define CONFIG_SYS_TEXT_BASE 0x23f00000 +#define CONFIG_SYS_TEXT_BASE 0x21000000 /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ @@ -127,6 +127,16 @@ #define CONFIG_USB_STORAGE #endif +/* SPI EEPROM */ +#define CONFIG_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_ATMEL_SPI +#define CONFIG_SPI_FLASH_STMICRO +#define TAURUS_SPI_MASK (1 << 4) +#define TAURUS_SPI_CS_PIN AT91_PIN_PA3 + /* load address */ #define CONFIG_SYS_LOAD_ADDR 0x22000000 @@ -158,4 +168,54 @@ #define CONFIG_SYS_MALLOC_LEN \ ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (11 * 1024) +#define CONFIG_SPL_STACK (16 * 1024) + +#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_BSS_MAX_SIZE (3 * 1024) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_USE_NANDFLASH 1 +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_NAND_RAW_ONLY +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +#define CONFIG_SYS_NAND_SIZE (256*1024*1024) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } + + +#define CONFIG_SPL_ATMEL_SIZE +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define AT91_PLL_LOCK_TIMEOUT 1000000 +#define CONFIG_SYS_AT91_PLLA 0x202A3F01 +#define CONFIG_SYS_MCKR 0x1300 +#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) +#define CONFIG_SYS_AT91_PLLB 0x10193F05 #endif diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h new file mode 100644 index 0000000..c097b98 --- /dev/null +++ b/include/configs/tbs2910.h @@ -0,0 +1,242 @@ +/* + * Copyright (C) 2014 Soeren Moch <smoch@web.de> + * + * Configuration settings for the TBS2910 MatrixARM board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TBS2910_CONFIG_H +#define __TBS2910_CONFIG_H + +#include "mx6_common.h" +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> + +/* General configuration */ +#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_SYS_THUMB_BUILD + +#define CONFIG_MACH_TYPE 3980 + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO +#define CONFIG_CMD_GPIO + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "Matrix U-Boot> " +#define CONFIG_BOOTDELAY 3 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END \ + (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024) + +#define CONFIG_SYS_TEXT_BASE 0x80000000 +#define CONFIG_SYS_BOOTMAPSZ 0x6C000000 +#define CONFIG_SYS_LOAD_ADDR 0x10800000 + +/* Serial console */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_CONSOLE_MUX +#define CONFIG_CONS_INDEX 1 + +/* *** Command definition *** */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_MEMTEST +#define CONFIG_CMD_TIME + +/* Filesystems / image support */ +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_FS_GENERIC + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_FIT + +/* MMC */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER + +/* Ethernet */ +#define CONFIG_FEC_MXC +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 4 +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* Framebuffer */ +#define CONFIG_VIDEO +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CFB_CONSOLE +#define CONFIG_CFB_CONSOLE_ANSI +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_CMD_HDMIDETECT +#endif + +/* PCI */ +#define CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) +#endif + +/* SATA */ +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + +/* USB */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_STORAGE +#define CONFIG_USB_KEYBOARD +#ifdef CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE +#define CONFIG_SYS_STDIO_DEREGISTER +#define CONFIG_PREBOOT "if hdmidet; then usb start; fi" +#endif /* CONFIG_USB_KEYBOARD */ +#endif /* CONFIG_CMD_USB */ + +/* RTC */ +#define CONFIG_CMD_DATE +#ifdef CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_RTC_DS1307 +#define CONFIG_SYS_RTC_BUS_NUM 2 +#endif + +/* I2C */ +#define CONFIG_CMD_I2C +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_I2C_EDID +#endif + +/* Fuses */ +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +/* Flash and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 2 +#define CONFIG_SYS_MMC_ENV_PART 1 +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET (384 * 1024) +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ + "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \ + "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \ + "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \ + "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \ + "${bootargs_mmc3}\0" \ + "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \ + "rdinit=/sbin/init enable_wait_mode=off\0" \ + "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \ + "mmc read 0x10800000 0x800 0x4000; bootm\0" \ + "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \ + "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \ + "run bootargs_upd; " \ + "bootm 0x10800000 0x10d00000\0" \ + "console=ttymxc0\0" \ + "fan=gpio set 92\0" \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc rescan; " \ + "if run bootcmd_up1; then " \ + "run bootcmd_up2; " \ + "else " \ + "run bootcmd_mmc; " \ + "fi" + +#endif /* __TBS2910_CONFIG_H * */ diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h index 6673026..e96a742 100644 --- a/include/configs/tcm-bf518.h +++ b/include/configs/tcm-bf518.h @@ -103,8 +103,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 9998343..42129fb 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -122,8 +122,8 @@ /* * I2C Settings */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_ADI /* diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 5d2b12a..d690045 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -118,7 +118,9 @@ #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) +#ifndef CONFIG_SPL_BUILD #define CONFIG_USE_ARCH_MEMCPY +#endif /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 2fddef3..deb6bb2 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -178,7 +178,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index aeabb1b..87a4efc 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -144,7 +144,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index a8790c2..bc75172 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -233,7 +233,7 @@ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ /* FAT sd card locations. */ -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #ifdef CONFIG_SPL_OS_BOOT diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 3166392..c47651d 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -19,7 +19,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_MISC_INIT_R #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -79,7 +78,7 @@ "partitions=" PARTS_DEFAULT "\0" \ "optargs=\0" \ "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk1p2 rw\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ "mmcrootfstype=ext4 rootwait\0" \ "mmcargs=setenv bootargs console=${console} " \ "${optargs} " \ @@ -118,6 +117,8 @@ "setenv fdtfile dra7-evm.dtb; fi;" \ "if test $board_name = dra72x; then " \ "setenv fdtfile dra72-evm.dtb; fi;" \ + "if test $board_name = beagle_x15; then " \ + "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \ diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h index 162826f..00a1a9e 100644 --- a/include/configs/tnetv107x_evm.h +++ b/include/configs/tnetv107x_evm.h @@ -16,7 +16,6 @@ #include <asm/arch/clock.h> /* Architecture, CPU, etc */ -#define CONFIG_ARM1176 #define CONFIG_TNETV107X #define CONFIG_TNETV107X_EVM #define CONFIG_TNETV107X_WATCHDOG diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h index 32f6b00..79c7fc5 100644 --- a/include/configs/tny_a9260.h +++ b/include/configs/tny_a9260.h @@ -85,7 +85,6 @@ #define CONFIG_SPI #define CONFIG_CMD_SPI #define CONFIG_ATMEL_SPI -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_CMD_EEPROM #define CONFIG_SPI_M95XXX diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index c94eee1..a099687 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -68,6 +68,8 @@ #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO +#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K + #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 @@ -275,12 +277,10 @@ #elif defined(CONFIG_TQMA6X_SPI_BOOT) -#define CONFIG_FLASH_SECTOR_SIZE 0x10000 - #define TQMA6_UBOOT_OFFSET 0x400 #define TQMA6_UBOOT_SECTOR_START 0x0 /* max u-boot size: 512k */ -#define TQMA6_UBOOT_SECTOR_SIZE CONFIG_FLASH_SECTOR_SIZE +#define TQMA6_UBOOT_SECTOR_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE #define TQMA6_UBOOT_SECTOR_COUNT 0x8 #define TQMA6_UBOOT_SIZE (TQMA6_UBOOT_SECTOR_SIZE * \ TQMA6_UBOOT_SECTOR_COUNT) @@ -288,7 +288,7 @@ #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET (TQMA6_UBOOT_SIZE) -#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE +#define CONFIG_ENV_SECT_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ CONFIG_ENV_SECT_SIZE) @@ -299,7 +299,7 @@ #define TQMA6_FDT_OFFSET (CONFIG_ENV_OFFSET_REDUND + \ CONFIG_ENV_SECT_SIZE) -#define TQMA6_FDT_SECT_SIZE (CONFIG_FLASH_SECTOR_SIZE) +#define TQMA6_FDT_SECT_SIZE (TQMA6_SPI_FLASH_SECTOR_SIZE) #define TQMA6_FDT_SECTOR_START 0x0a /* 8 Sector u-boot, 2 Sector env */ #define TQMA6_FDT_SECTOR_COUNT 0x01 @@ -320,7 +320,7 @@ "setexpr blkc ${filesize} + " \ __stringify(TQMA6_UBOOT_OFFSET) "; " \ "setexpr size ${uboot_sectors} * " \ - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ "if itest ${blkc} <= ${size}; then " \ "sf probe; " \ "sf erase 0 ${size}; " \ @@ -332,9 +332,9 @@ "update_kernel=run kernel_name; if tftp ${kernel}; then " \ "if itest ${filesize} > 0; then " \ "setexpr size ${kernel_sectors} * " \ - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ "setexpr offset ${kernel_start} * " \ - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ "if itest ${filesize} <= ${size}; then " \ "sf probe; " \ "sf erase ${offset} ${size}; " \ @@ -346,9 +346,9 @@ "update_fdt=if tftp ${fdt_file}; then " \ "if itest ${filesize} > 0; then " \ "setexpr size ${fdt_sectors} * " \ - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ "setexpr offset ${fdt_start} * " \ - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ "if itest ${filesize} <= ${size}; then " \ "sf probe; " \ "sf erase ${offset} ${size}; " \ @@ -359,16 +359,16 @@ "setenv filesize 0; setenv size ; setenv offset\0" \ "loadimage=sf probe; " \ "setexpr size ${kernel_sectors} * " \ - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ "setexpr offset ${kernel_start} * " \ - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ "sf read ${loadaddr} ${offset} ${size}; " \ "setenv size ; setenv offset\0" \ "loadfdt=sf probe; " \ "setexpr size ${fdt_sectors} * " \ - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ "setexpr offset ${fdt_start} * " \ - __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ "sf read ${${fdt_addr}} ${offset} ${size}; " \ "setenv size ; setenv offset\0" \ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 6e7a7fb..36621a5 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -349,7 +349,7 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ diff --git a/include/configs/tt01.h b/include/configs/tt01.h index 0937653..cf169a4 100644 --- a/include/configs/tt01.h +++ b/include/configs/tt01.h @@ -13,7 +13,6 @@ #include <asm/arch/imx-regs.h> /* High Level Configuration Options */ -#define CONFIG_ARM1136 #define CONFIG_MX31 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 700e9c1..b4a6245 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -191,7 +191,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 diff --git a/include/configs/uniphier-common.h b/include/configs/uniphier.h index 7c4dba0..dd022fb 100644 --- a/include/configs/uniphier-common.h +++ b/include/configs/uniphier.h @@ -10,10 +10,37 @@ #ifndef __CONFIG_UNIPHIER_COMMON_H__ #define __CONFIG_UNIPHIER_COMMON_H__ -#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) && \ - defined(CONFIG_DCC_MICRO_SUPPORT_CARD) -# error "Both CONFIG_PFC_MICRO_SUPPORT_CARD and CONFIG_DCC_MICRO_SUPPORT_CARD \ -are defined. Select only one of them." +#if defined(CONFIG_MACH_PH1_PRO4) +#define CONFIG_DDR_NUM_CH0 2 +#define CONFIG_DDR_NUM_CH1 2 + +/* Physical start address of SDRAM */ +#define CONFIG_SDRAM0_BASE 0x80000000 +#define CONFIG_SDRAM0_SIZE 0x20000000 +#define CONFIG_SDRAM1_BASE 0xa0000000 +#define CONFIG_SDRAM1_SIZE 0x20000000 +#endif + +#if defined(CONFIG_MACH_PH1_LD4) +#define CONFIG_DDR_NUM_CH0 1 +#define CONFIG_DDR_NUM_CH1 1 + +/* Physical start address of SDRAM */ +#define CONFIG_SDRAM0_BASE 0x80000000 +#define CONFIG_SDRAM0_SIZE 0x10000000 +#define CONFIG_SDRAM1_BASE 0x90000000 +#define CONFIG_SDRAM1_SIZE 0x10000000 +#endif + +#if defined(CONFIG_MACH_PH1_SLD8) +#define CONFIG_DDR_NUM_CH0 1 +#define CONFIG_DDR_NUM_CH1 1 + +/* Physical start address of SDRAM */ +#define CONFIG_SDRAM0_BASE 0x80000000 +#define CONFIG_SDRAM0_SIZE 0x10000000 +#define CONFIG_SDRAM1_BASE 0x90000000 +#define CONFIG_SDRAM1_SIZE 0x10000000 #endif /* @@ -40,6 +67,13 @@ are defined. Select only one of them." #define CONFIG_SYS_NS16550_REG_SIZE -2 #endif +/* TODO: move to Kconfig and device tree */ +#if 0 +#define CONFIG_SYS_NS16550_SERIAL +#endif + +#define CONFIG_SMC911X + #define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE #define CONFIG_SMC911X_32_BIT @@ -58,6 +92,7 @@ are defined. Select only one of them." #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) @@ -87,17 +122,7 @@ are defined. Select only one of them." #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) -# define CONFIG_SYS_MAX_FLASH_BANKS 1 -# define CONFIG_SYS_FLASH_BANKS_LIST {0x00000000} -# define CONFIG_SYS_FLASH_BANKS_SIZES {0x02000000} -#endif - -#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) -# define CONFIG_SYS_MAX_FLASH_BANKS 1 -# define CONFIG_SYS_FLASH_BANKS_LIST {0x04000000} -# define CONFIG_SYS_FLASH_BANKS_SIZES {0x04000000} -#endif +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* serial console configuration */ #define CONFIG_BAUDRATE 115200 @@ -112,7 +137,6 @@ are defined. Select only one of them." #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_CMDLINE_EDITING /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) @@ -143,15 +167,6 @@ are defined. Select only one of them." */ #define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */ -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_PING -#define CONFIG_CMD_TIME -#define CONFIG_CMD_NAND /* NAND flash suppport */ - #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 2 #define CONFIG_SYS_NAND_ONFI_DETECTION @@ -167,7 +182,6 @@ are defined. Select only one of them." #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 /* USB */ -#define CONFIG_CMD_USB #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE @@ -216,7 +230,6 @@ are defined. Select only one of them." "image_offset=0x00080000\0" \ "image_size=0x00f00000\0" \ "verify=n\0" \ - "autostart=yes\0" \ "norboot=run add_default_bootargs;" \ "bootm $image_offset\0" \ "nandboot=run add_default_bootargs;" \ @@ -225,10 +238,6 @@ are defined. Select only one of them." "add_default_bootargs=setenv bootargs $bootargs" \ " console=ttyS0,$baudrate\0" \ -/* FIT support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ - /* Open Firmware flat tree */ #define CONFIG_OF_LIBFDT @@ -248,6 +257,13 @@ are defined. Select only one of them." #define CONFIG_SYS_TEXT_BASE 0x84000000 +#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +#define CONFIG_SPL_TEXT_BASE 0x00040000 +#endif +#if defined(CONFIG_MACH_PH1_PRO4) +#define CONFIG_SPL_TEXT_BASE 0x00100000 +#endif + #define CONFIG_BOARD_POSTCLK_INIT #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 3c54870..84571f6 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -85,7 +85,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 #define AT91_SPI_CLK 8000000 diff --git a/include/configs/vct.h b/include/configs/vct.h index 217ba2f..83e4163 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -25,6 +25,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */ #define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) diff --git a/include/configs/versatile.h b/include/configs/versatile.h index 29c32fe..900b89c 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -19,8 +19,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */ +#define CONFIG_VERSATILE 1 /* This is Versatile Platform Board */ #define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */ #define CONFIG_SYS_MEMTEST_START 0x100000 diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h index 982f4a7..b43afa2 100644 --- a/include/configs/vexpress_ca15_tc2.h +++ b/include/configs/vexpress_ca15_tc2.h @@ -18,6 +18,4 @@ #define CONFIG_SYSFLAGS_ADDR 0x1c010030 #define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR -#define CONFIG_ARMV7_VIRT - #endif diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index d3d3e69..c7a17f7 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -14,7 +14,6 @@ #include <asm/arch/imx-regs.h> /* High Level Configuration Options */ -#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX35 #define CONFIG_MX35_HCLK_FREQ 24000000 diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h new file mode 100644 index 0000000..f16ae32 --- /dev/null +++ b/include/configs/x86-common.h @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/ibmpc.h> + +#ifndef __CONFIG_X86_COMMON_H +#define __CONFIG_X86_COMMON_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SHOW_BOOT_PROGRESS +#define CONFIG_SYS_VSNPRINTF +#define CONFIG_ZBOOT_32 +#define CONFIG_PHYSMEM +#define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL + +#define CONFIG_LMB +#define CONFIG_OF_LIBFDT + +#define CONFIG_LZO +#define CONFIG_FIT +#undef CONFIG_ZLIB +#undef CONFIG_GZIP +#define CONFIG_SYS_BOOTM_LEN (16 << 20) + +/* SATA AHCI storage */ + +#define CONFIG_SCSI_AHCI +#define CONFIG_SATA_INTEL +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_LIBATA +#define CONFIG_SYS_64BIT_LBA + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif + +/* Generic TPM interfaced through LPC bus */ +#define CONFIG_TPM +#define CONFIG_TPM_TIS_LPC +#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 + +/*----------------------------------------------------------------------- + * Real Time Clock Configuration + */ +#define CONFIG_RTC_MC146818 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 +#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS + +/*----------------------------------------------------------------------- + * Serial Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \ + 9600, 19200, 38400, 115200} +#define CONFIG_SYS_NS16550_PORT_MAPPED + +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_STDIO_DEREGISTER + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_COMMAND_HISTORY +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +#define CONFIG_SUPPORT_VFAT +/************************************************************ + * ATAPI support (experimental) + ************************************************************/ +#define CONFIG_ATAPI + +/************************************************************ + * DISK Partition support + ************************************************************/ +#define CONFIG_EFI_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION /* Experimental */ + +#define CONFIG_CMD_PART +#define CONFIG_CMD_CBFS +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_PARTITION_UUIDS + +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* x86 GPIOs are accessed through a PCI device */ +#define CONFIG_INTEL_ICH6_GPIO + +/*----------------------------------------------------------------------- + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ECHO +#undef CONFIG_CMD_FLASH +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_IO +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ITEST +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_SETGETDCR +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_TIME +#define CONFIG_CMD_GETTIME +#define CONFIG_CMD_XIMG +#define CONFIG_CMD_SCSI + +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +#define CONFIG_CMD_ZBOOT +#define CONFIG_CMD_ELF + +#define CONFIG_BOOTARGS \ + "root=/dev/sdb3 init=/sbin/init rootwait ro" +#define CONFIG_BOOTCOMMAND \ + "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000" + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + \ + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x01000000 +#define CONFIG_SYS_LOAD_ADDR 0x20000000 + +/*----------------------------------------------------------------------- + * Video Configuration + */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_SW_CURSOR +#define VIDEO_FB_16BPP_WORD_SWAP +#define CONFIG_I8042_KBD +#define CONFIG_CFB_CONSOLE + +/*----------------------------------------------------------------------- + * CPU Features + */ + +#define CONFIG_SYS_X86_TSC_TIMER +#define CONFIG_SYS_PCAT_INTERRUPTS +#define CONFIG_SYS_PCAT_TIMER +#define CONFIG_SYS_NUM_IRQS 16 + +#define CONFIG_SYS_STACK_SIZE (32 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MALLOC_LEN 0x200000 +#define CONFIG_SYS_MALLOC_F_LEN (2 << 10) + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/*----------------------------------------------------------------------- + * FLASH configuration + */ +#define CONFIG_ICH_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_SF +#define CONFIG_CMD_SF_TEST +#define CONFIG_CMD_SPI +#define CONFIG_SPI + +/*----------------------------------------------------------------------- + * Environment configuration + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x01000 + +/*----------------------------------------------------------------------- + * PCI configuration + */ +#define CONFIG_PCI + +/*----------------------------------------------------------------------- + * USB configuration + */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_PCI +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_TFTP_TSIZE +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +#define CONFIG_CMD_USB + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_STD_DEVICES_SETTINGS + +#endif /* __CONFIG_H */ diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 8ffe6f1..356ac88 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -12,7 +12,6 @@ #include <asm/arch/imx-regs.h> -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_MX25 #define CONFIG_SYS_TEXT_BASE 0xA0000000 diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 2bc1562..87b4fff 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -10,9 +10,6 @@ #ifndef __CONFIG_ZYNQ_COMMON_H #define __CONFIG_ZYNQ_COMMON_H -/* High Level configuration Options */ -#define CONFIG_ARMV7 - /* CPU clock */ #ifndef CONFIG_CPU_FREQ_HZ # define CONFIG_CPU_FREQ_HZ 800000000 @@ -268,7 +265,7 @@ #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" diff --git a/include/cortina.h b/include/cortina.h new file mode 100644 index 0000000..6cadd28 --- /dev/null +++ b/include/cortina.h @@ -0,0 +1,75 @@ +/* + * Cortina PHY drivers + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef _CORTINA_H_ +#define _CORTINA_H_ + +#define VILLA_GLOBAL_CHIP_ID_LSB 0x000 +#define VILLA_GLOBAL_CHIP_ID_MSB 0x001 +#define VILLA_GLOBAL_BIST_CONTROL 0x002 +#define VILLA_GLOBAL_BIST_STATUS 0x003 +#define VILLA_GLOBAL_LINE_SOFT_RESET 0x007 +#define VILLA_GLOBAL_HOST_SOFT_RESET 0x008 +#define VILLA_GLOBAL_DWNLD_CHECKSUM_CTRL 0x00A +#define VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS 0x00B +#define VILLA_GLOBAL_MSEQCLKCTRL 0x00E +#define VILLA_MSEQ_OPTIONS 0x1D0 +#define VILLA_MSEQ_PC 0x1D3 +#define VILLA_MSEQ_BANKSELECT 0x1DF +#define VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT 0x2DB +#define VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT 0x36E +#define VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER 0x403 +#define VILLA_LINE_SDS_COMMON_SRX0_RX_CPA 0x404 +#define VILLA_LINE_SDS_COMMON_SRX0_RX_CPB 0x405 +#define VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL 0x369 +#define VILLA_MSEQ_ENABLE_MSB 0x194 +#define VILLA_MSEQ_SPARE21_LSB 0x226 +#define VILLA_MSEQ_RESET_COUNT_LSB 0x1E0 +#define VILLA_MSEQ_SPARE12_MSB 0x215 +#define VILLA_MSEQ_SPARE2_LSB 0x200 +#define VILLA_MSEQ_SPARE7_LSB 0x20A +#define VILLA_MSEQ_SPARE9_LSB 0x20E +#define VILLA_MSEQ_SPARE3_LSB 0x202 +#define VILLA_MSEQ_SPARE3_MSB 0x203 +#define VILLA_MSEQ_SPARE8_LSB 0x20C +#define VILLA_MSEQ_SPARE8_MSB 0x20D +#define VILLA_MSEQ_COEF8_FFE0_LSB 0x1E2 +#define VILLA_MSEQ_COEF8_FFE1_LSB 0x1E4 +#define VILLA_MSEQ_COEF8_FFE2_LSB 0x1E6 +#define VILLA_MSEQ_COEF8_FFE3_LSB 0x1E8 +#define VILLA_MSEQ_COEF8_FFE4_LSB 0x1EA +#define VILLA_MSEQ_COEF8_FFE5_LSB 0x1EC +#define VILLA_MSEQ_COEF8_DFE0_LSB 0x1F0 +#define VILLA_MSEQ_COEF8_DFE0N_LSB 0x1EE +#define VILLA_MSEQ_COEF8_DFE1_LSB 0x1F2 +#define VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK 0x2E2 +#define VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB 0x360 +#define VILLA_MSEQ_POWER_DOWN_LSB 0x198 +#define VILLA_MSEQ_POWER_DOWN_MSB 0x199 +#define VILLA_MSEQ_CAL_RX_SLICER 0x1B8 +#define VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB 0x365 +#define VILLA_MSEQ_COEF_INIT_SEL 0x1AE +#define VILLA_DSP_SDS_DSP_PRECODEDINITFFE21 0x26A +#define VILLA_MSEQ_SERDES_PARAM_LSB 0x195 +#define VILLA_MSEQ_SPARE25_LSB 0x22E +#define VILLA_MSEQ_SPARE23_LSB 0x22A +#define VILLA_MSEQ_CAL_RX_DFE_EQ 0x1BA +#define VILLA_GLOBAL_VILLA2_COMPATIBLE 0x030 +#define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x812 +#define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x813 +#define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x427 +#define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x428 + +#define mseq_edc_bist_done (0x1<<0) +#define mseq_edc_bist_fail (0x1<<8) + +struct cortina_reg_config { + unsigned short reg_addr; + unsigned short reg_value; +}; +#endif diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index 44cb7ef..f0cc794 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -87,7 +87,11 @@ int device_probe_child(struct udevice *dev, void *parent_priv); * @dev: Pointer to device to remove * @return 0 if OK, -ve on error (an error here is normally a very bad thing) */ +#ifdef CONFIG_DM_DEVICE_REMOVE int device_remove(struct udevice *dev); +#else +static inline int device_remove(struct udevice *dev) { return 0; } +#endif /** * device_unbind() - Unbind a device, destroying it @@ -99,6 +103,12 @@ int device_remove(struct udevice *dev); */ int device_unbind(struct udevice *dev); +#ifdef CONFIG_DM_DEVICE_REMOVE +void device_free(struct udevice *dev); +#else +static inline void device_free(struct udevice *dev) {} +#endif + /* Cast away any volatile pointer */ #define DM_ROOT_NON_CONST (((gd_t *)gd)->dm_root) #define DM_UCLASS_ROOT_NON_CONST (((gd_t *)gd)->uclass_root) diff --git a/include/dm/device.h b/include/dm/device.h index 9ce95a8..13598a1 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -47,6 +47,7 @@ struct driver_info; * @name: Name of device, typically the FDT node name * @platdata: Configuration data for this device * @of_offset: Device tree node offset for this device (- for none) + * @of_id: Pointer to the udevice_id structure which created the device * @parent: Parent of this device, or NULL for the top level device * @priv: Private data for this device * @uclass: Pointer to uclass for this device @@ -65,6 +66,7 @@ struct udevice { const char *name; void *platdata; int of_offset; + const struct udevice_id *of_id; struct udevice *parent; void *priv; struct uclass *uclass; @@ -206,6 +208,23 @@ void *dev_get_parentdata(struct udevice *dev); void *dev_get_priv(struct udevice *dev); /** + * struct dev_get_parent() - Get the parent of a device + * + * @child: Child to check + * @return parent of child, or NULL if this is the root device + */ +struct udevice *dev_get_parent(struct udevice *child); + +/** + * dev_get_of_data() - get the device tree data used to bind a device + * + * When a device is bound using a device tree node, it matches a + * particular compatible string as in struct udevice_id. This function + * returns the associated data value for that compatible string + */ +ulong dev_get_of_data(struct udevice *dev); + +/** * device_get_child() - Get the child of a device by index * * Returns the numbered child, 0 being the first. This does not use diff --git a/include/dm/lists.h b/include/dm/lists.h index 704e33e..1b50af9 100644 --- a/include/dm/lists.h +++ b/include/dm/lists.h @@ -60,4 +60,17 @@ int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only); int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, struct udevice **devp); +/** + * device_bind_driver() - bind a device to a driver + * + * This binds a new device to a driver. + * + * @parent: Parent device + * @drv_name: Name of driver to attach to this parent + * @dev_name: Name of the new device thus created + * @devp: Returns the newly bound device + */ +int device_bind_driver(struct udevice *parent, const char *drv_name, + const char *dev_name, struct udevice **devp); + #endif diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index a8944c9..202f59b 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -28,6 +28,7 @@ enum uclass_id { UCLASS_SPI_GENERIC, /* Generic SPI flash target */ UCLASS_SPI_FLASH, /* SPI flash */ UCLASS_CROS_EC, /* Chrome OS EC */ + UCLASS_THERMAL, /* Thermal sensor */ UCLASS_COUNT, UCLASS_INVALID = -1, diff --git a/include/dm/util.h b/include/dm/util.h index 6ac3a38..0cec17b 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -7,7 +7,13 @@ #ifndef __DM_UTIL_H #define __DM_UTIL_H +#ifdef CONFIG_DM_WARN void dm_warn(const char *fmt, ...); +#else +static inline void dm_warn(const char *fmt, ...) +{ +} +#endif #ifdef DEBUG void dm_dbg(const char *fmt, ...); diff --git a/include/ext4fs.h b/include/ext4fs.h index 6c419f3..6888adc 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -125,24 +125,28 @@ int ext4fs_init(void); void ext4fs_deinit(void); int ext4fs_filename_check(char *filename); int ext4fs_write(const char *fname, unsigned char *buffer, - unsigned long sizebytes); + unsigned long sizebytes); +int ext4_write_file(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actwrite); #endif struct ext_filesystem *get_fs(void); -int ext4fs_open(const char *filename); -int ext4fs_read(char *buf, unsigned len); +int ext4fs_open(const char *filename, loff_t *len); +int ext4fs_read(char *buf, loff_t len, loff_t *actread); int ext4fs_mount(unsigned part_length); void ext4fs_close(void); void ext4fs_reinit_global(void); int ext4fs_ls(const char *dirname); int ext4fs_exists(const char *filename); -int ext4fs_size(const char *filename); +int ext4fs_size(const char *filename, loff_t *size); void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot); int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf); void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); long int read_allocated_block(struct ext2_inode *inode, int fileblock); int ext4fs_probe(block_dev_desc_t *fs_dev_desc, disk_partition_t *fs_partition); -int ext4_read_file(const char *filename, void *buf, int offset, int len); +int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread); int ext4_read_superblock(char *buffer); +int ext4fs_uuid(char *uuid_str); #endif diff --git a/include/fat.h b/include/fat.h index 20ca3f3..3038bd7 100644 --- a/include/fat.h +++ b/include/fat.h @@ -178,8 +178,8 @@ typedef struct { typedef int (file_detectfs_func)(void); typedef int (file_ls_func)(const char *dir); -typedef long (file_read_func)(const char *filename, void *buffer, - unsigned long maxsize); +typedef int (file_read_func)(const char *filename, void *buffer, + int maxsize); struct filesystem { file_detectfs_func *detect; @@ -198,15 +198,17 @@ int file_cd(const char *path); int file_fat_detectfs(void); int file_fat_ls(const char *dir); int fat_exists(const char *filename); -int fat_size(const char *filename); -long file_fat_read_at(const char *filename, unsigned long pos, void *buffer, - unsigned long maxsize); -long file_fat_read(const char *filename, void *buffer, unsigned long maxsize); +int fat_size(const char *filename, loff_t *size); +int file_fat_read_at(const char *filename, loff_t pos, void *buffer, + loff_t maxsize, loff_t *actread); +int file_fat_read(const char *filename, void *buffer, int maxsize); const char *file_getfsname(int idx); int fat_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); int fat_register_device(block_dev_desc_t *dev_desc, int part_no); -int file_fat_write(const char *filename, void *buffer, unsigned long maxsize); -int fat_read_file(const char *filename, void *buf, int offset, int len); +int file_fat_write(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actwrite); +int fat_read_file(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread); void fat_close(void); #endif /* _FAT_H_ */ diff --git a/include/fdt_support.h b/include/fdt_support.h index 55cef94..1f19fe4 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -64,7 +64,20 @@ static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {} int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose); #endif -void ft_board_setup(void *blob, bd_t *bd); +int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name); + +/** + * Add board-specific data to the FDT before booting the OS. + * + * Use CONFIG_SYS_FDT_PAD to ensure there is sufficient space. + * This function is called if CONFIG_OF_BOARD_SETUP is defined + * + * @param blob FDT blob to update + * @param bd_t Pointer to board data + * @return 0 if ok, or -FDT_ERR_... on error + */ +int ft_board_setup(void *blob, bd_t *bd); + /* * The keystone2 SOC requires all 32 bit aliased addresses to be converted * to their 36 physical format. This has to happen after all fdt nodes @@ -75,6 +88,18 @@ void ft_board_setup_ex(void *blob, bd_t *bd); void ft_cpu_setup(void *blob, bd_t *bd); void ft_pci_setup(void *blob, bd_t *bd); +/** + * Add system-specific data to the FDT before booting the OS. + * + * Use CONFIG_SYS_FDT_PAD to ensure there is sufficient space. + * This function is called if CONFIG_OF_SYSTEM_SETUP is defined + * + * @param blob FDT blob to update + * @param bd_t Pointer to board data + * @return 0 if ok, or -FDT_ERR_... on error + */ +int ft_system_setup(void *blob, bd_t *bd); + void set_working_fdt_addr(void *addr); int fdt_shrink_to_minimum(void *blob); int fdt_increase_size(void *fdt, int add_len); @@ -147,6 +172,9 @@ void of_bus_default_count_cells(void *blob, int parentoffset, int ft_verify_fdt(void *fdt); int arch_fixup_memory_node(void *blob); +int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width, + u32 height, u32 stride, const char *format); + #endif /* ifdef CONFIG_OF_LIBFDT */ #ifdef USE_HOSTCC diff --git a/include/fdtdec.h b/include/fdtdec.h index 4ae77be..d2b665c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -118,6 +118,11 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */ COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */ + COMPAT_INTEL_MICROCODE, /* Intel microcode update */ + COMPAT_MEMORY_SPD, /* Memory SPD information */ + COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */ + COMPAT_INTEL_MODEL_206AX, /* Intel Model 206AX CPU */ + COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */ COMPAT_COUNT, }; @@ -388,17 +393,6 @@ int fdtdec_get_alias_seq(const void *blob, const char *base, int node, int *seqp); /** - * Get the offset of the given alias node - * - * This looks up an alias in /aliases then finds the offset of that node. - * - * @param blob Device tree blob (if NULL, then error is returned) - * @param name Alias name, e.g. "console" - * @return Node offset referred to by that alias, or -ve FDT_ERR_... - */ -int fdtdec_get_alias_node(const void *blob, const char *name); - -/** * Get the offset of the given chosen node * * This looks up a property in /chosen containing the path to another node, @@ -445,6 +439,22 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, u32 *array, int count); /** + * Look up a property in a node and return its contents in an integer + * array of given length. The property must exist but may have less data that + * expected (4*count bytes). It may have more, but this will be ignored. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param array array to fill with data + * @param count number of array elements + * @return number of array elements if ok, or -FDT_ERR_NOTFOUND if the + * property is not found + */ +int fdtdec_get_int_array_count(const void *blob, int node, + const char *prop_name, u32 *array, int count); + +/** * Look up a property in a node and return a pointer to its contents as a * unsigned int array of given length. The property must have at least enough * data for the array ('count' cells). It may have more, but this will be @@ -595,17 +605,33 @@ const u8 *fdtdec_locate_byte_array(const void *blob, int node, * @param blob FDT blob * @param node node to examine * @param prop_name name of property to find - * @param ptrp returns pointer to region, or NULL if no address - * @param size returns size of region - * @return 0 if ok, -1 on error (propery not found) + * @param basep Returns base address of region + * @param size Returns size of region + * @return 0 if ok, -1 on error (property not found) */ -int fdtdec_decode_region(const void *blob, int node, - const char *prop_name, void **ptrp, size_t *size); +int fdtdec_decode_region(const void *blob, int node, const char *prop_name, + fdt_addr_t *basep, fdt_size_t *sizep); + +enum fmap_compress_t { + FMAP_COMPRESS_NONE, + FMAP_COMPRESS_LZO, +}; + +enum fmap_hash_t { + FMAP_HASH_NONE, + FMAP_HASH_SHA1, + FMAP_HASH_SHA256, +}; /* A flash map entry, containing an offset and length */ struct fmap_entry { uint32_t offset; uint32_t length; + uint32_t used; /* Number of bytes used in region */ + enum fmap_compress_t compress_algo; /* Compression type */ + enum fmap_hash_t hash_algo; /* Hash algorithm */ + const uint8_t *hash; /* Hash value */ + int hash_size; /* Hash size */ }; /** @@ -661,4 +687,31 @@ int fdt_get_named_resource(const void *fdt, int node, const char *property, */ int fdtdec_pci_get_bdf(const void *fdt, int node, int *bdf); +/** + * Decode a named region within a memory bank of a given type. + * + * This function handles selection of a memory region. The region is + * specified as an offset/size within a particular type of memory. + * + * The properties used are: + * + * <mem_type>-memory<suffix> for the name of the memory bank + * <mem_type>-offset<suffix> for the offset in that bank + * + * The property value must have an offset and a size. The function checks + * that the region is entirely within the memory bank.5 + * + * @param blob FDT blob + * @param node Node containing the properties (-1 for /config) + * @param mem_type Type of memory to use, which is a name, such as + * "u-boot" or "kernel". + * @param suffix String to append to the memory/offset + * property names + * @param basep Returns base of region + * @param sizep Returns size of region + * @return 0 if OK, -ive on error + */ +int fdtdec_decode_memory_region(const void *blob, int node, + const char *mem_type, const char *suffix, + fdt_addr_t *basep, fdt_size_t *sizep); #endif diff --git a/include/flash.h b/include/flash.h index 5454c9e..30aa080 100644 --- a/include/flash.h +++ b/include/flash.h @@ -158,6 +158,7 @@ extern flash_info_t *flash_get_info(ulong base); #define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */ #define AMIC_MANUFACT 0x00370037 /* AMIC manuf. ID in D23..D16, D7..D0 */ #define WINB_MANUFACT 0x00DA00DA /* Winbond manuf. ID in D23..D16, D7..D0 */ +#define EON_ALT_MANU 0x001C001C /* EON manuf. ID in D23..D16, D7..D0 */ /* Manufacturers inside bank 1 have ids like 0x01xx01xx */ #define EON_MANUFACT 0x011C011C /* EON manuf. ID in D23..D16, D7..D0 */ diff --git a/include/fm_eth.h b/include/fm_eth.h index e46a684..3e1b9f4 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -75,6 +75,20 @@ enum fm_eth_type { offsetof(struct ccsr_fman, memac[n-1]),\ } +#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION +#define FM_TGEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE2 + n - 1, \ + .tx_port_id = TX_PORT_10G_BASE2 + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1]),\ +} +#else #define FM_TGEC_INFO_INITIALIZER(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \ @@ -87,6 +101,7 @@ enum fm_eth_type { .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, memac[n-1+8]),\ } +#endif #if (CONFIG_SYS_NUM_FM1_10GEC >= 3) #define FM_TGEC_INFO_INITIALIZER2(idx, n) \ diff --git a/include/fs.h b/include/fs.h index 06a45f2..ffb6ce7 100644 --- a/include/fs.h +++ b/include/fs.h @@ -51,32 +51,41 @@ int fs_ls(const char *dirname); int fs_exists(const char *filename); /* - * Determine a file's size + * fs_size - Determine a file's size * - * Returns the file's size in bytes, or a negative value if it doesn't exist. + * @filename: Name of the file + * @size: Size of file + * @return 0 if ok with valid *size, negative on error */ -int fs_size(const char *filename); +int fs_size(const char *filename, loff_t *size); /* - * Read file "filename" from the partition previously set by fs_set_blk_dev(), - * to address "addr", starting at byte offset "offset", and reading "len" - * bytes. "offset" may be 0 to read from the start of the file. "len" may be - * 0 to read the entire file. Note that not all filesystem types support - * either/both offset!=0 or len!=0. + * fs_read - Read file from the partition previously set by fs_set_blk_dev() + * Note that not all filesystem types support either/both offset!=0 or len!=0. * - * Returns number of bytes read on success. Returns <= 0 on error. + * @filename: Name of file to read from + * @addr: The address to read into + * @offset: The offset in file to read from + * @len: The number of bytes to read. Maybe 0 to read entire file + * @actread: Returns the actual number of bytes read + * @return 0 if ok with valid *actread, -1 on error conditions */ -int fs_read(const char *filename, ulong addr, int offset, int len); +int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len, + loff_t *actread); /* - * Write file "filename" to the partition previously set by fs_set_blk_dev(), - * from address "addr", starting at byte offset "offset", and writing "len" - * bytes. "offset" may be 0 to write to the start of the file. Note that not - * all filesystem types support offset!=0. + * fs_write - Write file to the partition previously set by fs_set_blk_dev() + * Note that not all filesystem types support offset!=0. * - * Returns number of bytes read on success. Returns <= 0 on error. + * @filename: Name of file to read from + * @addr: The address to read into + * @offset: The offset in file to read from. Maybe 0 to write to start of file + * @len: The number of bytes to write + * @actwrite: Returns the actual number of bytes written + * @return 0 if ok with valid *actwrite, -1 on error conditions */ -int fs_write(const char *filename, ulong addr, int offset, int len); +int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len, + loff_t *actwrite); /* * Common implementation for various filesystem commands, optionally limited @@ -93,4 +102,11 @@ int file_exists(const char *dev_type, const char *dev_part, const char *file, int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype); +/* + * Determine the UUID of the specified filesystem and print it. Optionally it is + * possible to store the UUID directly in env. + */ +int do_fs_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int fstype); + #endif /* _FS_H */ diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 5b03c14..095b33e 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -114,6 +114,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define SDRAM_CFG_2T_EN 0x00008000 #define SDRAM_CFG_BI 0x00000001 +#define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG2_D_INIT 0x00000010 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 #define SDRAM_CFG2_ODT_NEVER 0 @@ -163,6 +164,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8)) +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) @@ -202,6 +204,8 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_CDR_ODT_120ohm 0x6 #endif +#define DDR_INIT_ADDR_EXT_UIA (1 << 31) + /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { struct { @@ -414,9 +418,11 @@ static int __board_need_mem_reset(void) int board_need_mem_reset(void) __attribute__((weak, alias("__board_need_mem_reset"))); -void __weak board_mem_sleep_setup(void) -{ -} +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void); +bool is_warm_boot(void); +int fsl_dp_resume(void); +#endif /* * The 85xx boards have a common prototype for fixed_sdram so put the diff --git a/include/fsl_usb.h b/include/fsl_usb.h index 1a6c9c1..d251f5d 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -85,4 +85,104 @@ struct ccsr_usb_phy { #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07 #endif +/* USB Erratum Checking code */ +#ifdef CONFIG_PPC +static inline bool has_erratum_a006261(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P2041: + case SVR_P2040: + return IS_SVR_REV(svr, 1, 0) || + IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1); + case SVR_P3041: + return IS_SVR_REV(svr, 1, 0) || + IS_SVR_REV(svr, 1, 1) || + IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1); + case SVR_P5010: + case SVR_P5020: + case SVR_P5021: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_T4240: + case SVR_T4160: + case SVR_T4080: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_T1040: + return IS_SVR_REV(svr, 1, 0); + case SVR_T2080: + case SVR_T2081: + return IS_SVR_REV(svr, 1, 0); + case SVR_P5040: + return IS_SVR_REV(svr, 1, 0); + } + + return false; +} + +static inline bool has_erratum_a007075(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_B4860: + case SVR_B4420: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0); + case SVR_P4080: + return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0); + } + return false; +} + +static inline bool has_erratum_a007798(void) +{ + return SVR_SOC_VER(get_svr()) == SVR_T4240 && + IS_SVR_REV(get_svr(), 2, 0); +} + +static inline bool has_erratum_a007792(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_T4240: + case SVR_T4160: + return IS_SVR_REV(svr, 2, 0); + case SVR_T1040: + return IS_SVR_REV(svr, 1, 0); + case SVR_T2080: + case SVR_T2081: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); + } + return false; +} + +#else +static inline bool has_erratum_a006261(void) +{ + return false; +} + +static inline bool has_erratum_a007075(void) +{ + return false; +} + +static inline bool has_erratum_a007798(void) +{ + return false; +} + +static inline bool has_erratum_a007792(void) +{ + return false; +} +#endif #endif /*_ASM_FSL_USB_H_ */ diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index 276a01e..8a5efe7 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -61,6 +61,22 @@ struct ihs_osd { u16 y_pos; }; +struct ihs_mdio { + u16 control; + u16 address_data; + u16 rx_data; +}; + +struct ihs_io_ep { + u16 transmit_data; + u16 rx_tx_control; + u16 receive_data; + u16 rx_tx_status; + u16 reserved; + u16 device_address; + u16 target_address; +}; + #ifdef CONFIG_NEO struct ihs_fpga { u16 reflection_low; /* 0x0000 */ @@ -119,12 +135,50 @@ struct ihs_fpga { u16 versions; /* 0x0002 */ u16 fpga_version; /* 0x0004 */ u16 fpga_features; /* 0x0006 */ - u16 reserved_0[6]; /* 0x0008 */ + u16 reserved_0[1]; /* 0x0008 */ + u16 top_interrupt; /* 0x000a */ + u16 reserved_1[4]; /* 0x000c */ + struct ihs_gpio gpio; /* 0x0014 */ + u16 mpc3w_control; /* 0x001a */ + u16 reserved_2[2]; /* 0x001c */ + struct ihs_io_ep ep; /* 0x0020 */ + u16 reserved_3[9]; /* 0x002e */ + struct ihs_i2c i2c; /* 0x0040 */ + u16 reserved_4[10]; /* 0x004c */ + u16 mc_int; /* 0x0060 */ + u16 mc_int_en; /* 0x0062 */ + u16 mc_status; /* 0x0064 */ + u16 mc_control; /* 0x0066 */ + u16 mc_tx_data; /* 0x0068 */ + u16 mc_tx_address; /* 0x006a */ + u16 mc_tx_cmd; /* 0x006c */ + u16 mc_res; /* 0x006e */ + u16 mc_rx_cmd_status; /* 0x0070 */ + u16 mc_rx_data; /* 0x0072 */ + u16 reserved_5[69]; /* 0x0074 */ + u16 reflection_high; /* 0x00fe */ + struct ihs_osd osd; /* 0x0100 */ + u16 reserved_6[889]; /* 0x010e */ + u16 videomem[31736]; /* 0x0800 */ +}; +#endif + +#ifdef CONFIG_HRCON +struct ihs_fpga { + u16 reflection_low; /* 0x0000 */ + u16 versions; /* 0x0002 */ + u16 fpga_version; /* 0x0004 */ + u16 fpga_features; /* 0x0006 */ + u16 reserved_0[1]; /* 0x0008 */ + u16 top_interrupt; /* 0x000a */ + u16 reserved_1[4]; /* 0x000c */ struct ihs_gpio gpio; /* 0x0014 */ u16 mpc3w_control; /* 0x001a */ - u16 reserved_1[18]; /* 0x001c */ + u16 reserved_2[2]; /* 0x001c */ + struct ihs_io_ep ep; /* 0x0020 */ + u16 reserved_3[9]; /* 0x002e */ struct ihs_i2c i2c; /* 0x0040 */ - u16 reserved_2[10]; /* 0x004c */ + u16 reserved_4[10]; /* 0x004c */ u16 mc_int; /* 0x0060 */ u16 mc_int_en; /* 0x0062 */ u16 mc_status; /* 0x0064 */ @@ -135,10 +189,10 @@ struct ihs_fpga { u16 mc_res; /* 0x006e */ u16 mc_rx_cmd_status; /* 0x0070 */ u16 mc_rx_data; /* 0x0072 */ - u16 reserved_3[69]; /* 0x0074 */ + u16 reserved_5[69]; /* 0x0074 */ u16 reflection_high; /* 0x00fe */ struct ihs_osd osd; /* 0x0100 */ - u16 reserved_4[889]; /* 0x010e */ + u16 reserved_6[889]; /* 0x010e */ u16 videomem[31736]; /* 0x0800 */ }; #endif diff --git a/include/image.h b/include/image.h index 07e9aed..af30d60 100644 --- a/include/image.h +++ b/include/image.h @@ -119,6 +119,12 @@ struct lmb; # define IMAGE_OF_BOARD_SETUP 0 #endif +#ifdef CONFIG_OF_SYSTEM_SETUP +# define IMAGE_OF_SYSTEM_SETUP 1 +#else +# define IMAGE_OF_SYSTEM_SETUP 0 +#endif + /* * Operating System Codes */ diff --git a/include/imx_thermal.h b/include/imx_thermal.h new file mode 100644 index 0000000..be13652 --- /dev/null +++ b/include/imx_thermal.h @@ -0,0 +1,17 @@ +/* + * + * (C) Copyright 2014 Freescale Semiconductor, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IMX_THERMAL_H_ +#define _IMX_THERMAL_H_ + +struct imx_thermal_plat { + void *regs; + int fuse_bank; + int fuse_word; +}; + +#endif /* _IMX_THERMAL_H_ */ diff --git a/include/linux/compat.h b/include/linux/compat.h index 7ff6064..b40133c 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -57,17 +57,6 @@ void *kmem_cache_alloc(struct kmem_cache *obj, int flag); #define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) -/* - * ..and if you can't take the strict - * types, you can specify one yourself. - * - * Or not use min/max at all, of course. - */ -#define min_t(type,x,y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) -#define max_t(type,x,y) \ - ({ type __x = (x); type __y = (y); __x > __y ? __x: __y; }) - #ifndef BUG #define BUG() do { \ printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \ @@ -81,24 +70,6 @@ void *kmem_cache_alloc(struct kmem_cache *obj, int flag); #define PAGE_SIZE 4096 -/** - * upper_32_bits - return MSB bits 32-63 of a number if little endian, or - * return MSB bits 0-31 of a number if big endian. - * @n: the number we're accessing - * - * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress - * the "right shift count >= width of type" warning when that quantity is - * 32-bits. - */ -#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) - -/** - * lower_32_bits - return LSB bits 0-31 of a number if little endian, or - * return LSB bits 32-63 of a number if big endian. - * @n: the number we're accessing - */ -#define lower_32_bits(n) ((u32)(n)) - /* drivers/char/random.c */ #define get_random_bytes(...) @@ -152,17 +123,6 @@ typedef unsigned long blkcnt_t; #define ENOTSUPP 524 /* Operation is not supported */ -/* from include/linux/kernel.h */ -/* - * This looks more complex than it should be. But we need to - * get the type for the ~ right in round_down (it needs to be - * as wide as the result!), and we want to evaluate the macro - * arguments just once each. - */ -#define __round_mask(x, y) ((__typeof__(x))((y)-1)) -#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1) -#define round_down(x, y) ((x) & ~__round_mask(x, y)) - /* module */ #define THIS_MODULE 0 #define try_module_get(...) 1 @@ -198,18 +158,6 @@ typedef unsigned long blkcnt_t; #define blocking_notifier_call_chain(...) 0 -/* - * Multiplies an integer by a fraction, while avoiding unnecessary - * overflow or loss of precision. - */ -#define mult_frac(x, numer, denom)( \ -{ \ - typeof(x) quot = (x) / (denom); \ - typeof(x) rem = (x) % (denom); \ - (quot * (numer)) + ((rem * (numer)) / (denom)); \ -} \ -) - #define __initdata #define late_initcall(...) @@ -267,15 +215,11 @@ typedef int wait_queue_head_t; #define cond_resched() do { } while (0) #define yield() do { } while (0) -#define INT_MAX ((int)(~0U>>1)) - -#define __user #define __init #define __exit #define __devinit #define __devinitdata #define __devinitconst -#define __iomem #define kthread_create(...) __builtin_return_address(0) #define kthread_stop(...) do { } while (0) @@ -306,8 +250,6 @@ struct cdev { #define cdev_add(...) 0 #define cdev_del(...) do { } while (0) -#define MAX_ERRNO 4095 - #define prandom_u32(...) 0 typedef struct { diff --git a/include/linux/kernel.h b/include/linux/kernel.h new file mode 100644 index 0000000..0b61671 --- /dev/null +++ b/include/linux/kernel.h @@ -0,0 +1,247 @@ +#ifndef _LINUX_KERNEL_H +#define _LINUX_KERNEL_H + + +#include <linux/types.h> + +#define USHRT_MAX ((u16)(~0U)) +#define SHRT_MAX ((s16)(USHRT_MAX>>1)) +#define SHRT_MIN ((s16)(-SHRT_MAX - 1)) +#define INT_MAX ((int)(~0U>>1)) +#define INT_MIN (-INT_MAX - 1) +#define UINT_MAX (~0U) +#define LONG_MAX ((long)(~0UL>>1)) +#define LONG_MIN (-LONG_MAX - 1) +#define ULONG_MAX (~0UL) +#define LLONG_MAX ((long long)(~0ULL>>1)) +#define LLONG_MIN (-LLONG_MAX - 1) +#define ULLONG_MAX (~0ULL) +#ifndef SIZE_MAX +#define SIZE_MAX (~(size_t)0) +#endif + +#define U8_MAX ((u8)~0U) +#define S8_MAX ((s8)(U8_MAX>>1)) +#define S8_MIN ((s8)(-S8_MAX - 1)) +#define U16_MAX ((u16)~0U) +#define S16_MAX ((s16)(U16_MAX>>1)) +#define S16_MIN ((s16)(-S16_MAX - 1)) +#define U32_MAX ((u32)~0U) +#define S32_MAX ((s32)(U32_MAX>>1)) +#define S32_MIN ((s32)(-S32_MAX - 1)) +#define U64_MAX ((u64)~0ULL) +#define S64_MAX ((s64)(U64_MAX>>1)) +#define S64_MIN ((s64)(-S64_MAX - 1)) + +#define STACK_MAGIC 0xdeadbeef + +#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x)) + +#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) +#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) +#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) +#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +/* + * This looks more complex than it should be. But we need to + * get the type for the ~ right in round_down (it needs to be + * as wide as the result!), and we want to evaluate the macro + * arguments just once each. + */ +#define __round_mask(x, y) ((__typeof__(x))((y)-1)) +#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1) +#define round_down(x, y) ((x) & ~__round_mask(x, y)) + +#define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f)) +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) + +#if BITS_PER_LONG == 32 +# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP_ULL(ll, d) +#else +# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP(ll,d) +#endif + +/* The `const' in roundup() prevents gcc-3.3 from calling __divdi3 */ +#define roundup(x, y) ( \ +{ \ + const typeof(y) __y = y; \ + (((x) + (__y - 1)) / __y) * __y; \ +} \ +) +#define rounddown(x, y) ( \ +{ \ + typeof(x) __x = (x); \ + __x - (__x % (y)); \ +} \ +) + +/* + * Divide positive or negative dividend by positive divisor and round + * to closest integer. Result is undefined for negative divisors and + * for negative dividends if the divisor variable type is unsigned. + */ +#define DIV_ROUND_CLOSEST(x, divisor)( \ +{ \ + typeof(x) __x = x; \ + typeof(divisor) __d = divisor; \ + (((typeof(x))-1) > 0 || \ + ((typeof(divisor))-1) > 0 || (__x) > 0) ? \ + (((__x) + ((__d) / 2)) / (__d)) : \ + (((__x) - ((__d) / 2)) / (__d)); \ +} \ +) + +/* + * Multiplies an integer by a fraction, while avoiding unnecessary + * overflow or loss of precision. + */ +#define mult_frac(x, numer, denom)( \ +{ \ + typeof(x) quot = (x) / (denom); \ + typeof(x) rem = (x) % (denom); \ + (quot * (numer)) + ((rem * (numer)) / (denom)); \ +} \ +) + +/** + * upper_32_bits - return bits 32-63 of a number + * @n: the number we're accessing + * + * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress + * the "right shift count >= width of type" warning when that quantity is + * 32-bits. + */ +#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) + +/** + * lower_32_bits - return bits 0-31 of a number + * @n: the number we're accessing + */ +#define lower_32_bits(n) ((u32)(n)) + +/* + * abs() handles unsigned and signed longs, ints, shorts and chars. For all + * input types abs() returns a signed long. + * abs() should not be used for 64-bit types (s64, u64, long long) - use abs64() + * for those. + */ +#define abs(x) ({ \ + long ret; \ + if (sizeof(x) == sizeof(long)) { \ + long __x = (x); \ + ret = (__x < 0) ? -__x : __x; \ + } else { \ + int __x = (x); \ + ret = (__x < 0) ? -__x : __x; \ + } \ + ret; \ + }) + +#define abs64(x) ({ \ + s64 __x = (x); \ + (__x < 0) ? -__x : __x; \ + }) + +/* + * min()/max()/clamp() macros that also do + * strict type-checking.. See the + * "unnecessary" pointer comparison. + */ +#define min(x, y) ({ \ + typeof(x) _min1 = (x); \ + typeof(y) _min2 = (y); \ + (void) (&_min1 == &_min2); \ + _min1 < _min2 ? _min1 : _min2; }) + +#define max(x, y) ({ \ + typeof(x) _max1 = (x); \ + typeof(y) _max2 = (y); \ + (void) (&_max1 == &_max2); \ + _max1 > _max2 ? _max1 : _max2; }) + +#define min3(x, y, z) min((typeof(x))min(x, y), z) +#define max3(x, y, z) max((typeof(x))max(x, y), z) + +/** + * min_not_zero - return the minimum that is _not_ zero, unless both are zero + * @x: value1 + * @y: value2 + */ +#define min_not_zero(x, y) ({ \ + typeof(x) __x = (x); \ + typeof(y) __y = (y); \ + __x == 0 ? __y : ((__y == 0) ? __x : min(__x, __y)); }) + +/** + * clamp - return a value clamped to a given range with strict typechecking + * @val: current value + * @lo: lowest allowable value + * @hi: highest allowable value + * + * This macro does strict typechecking of lo/hi to make sure they are of the + * same type as val. See the unnecessary pointer comparisons. + */ +#define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi) + +/* + * ..and if you can't take the strict + * types, you can specify one yourself. + * + * Or not use min/max/clamp at all, of course. + */ +#define min_t(type, x, y) ({ \ + type __min1 = (x); \ + type __min2 = (y); \ + __min1 < __min2 ? __min1: __min2; }) + +#define max_t(type, x, y) ({ \ + type __max1 = (x); \ + type __max2 = (y); \ + __max1 > __max2 ? __max1: __max2; }) + +/** + * clamp_t - return a value clamped to a given range using a given type + * @type: the type of variable to use + * @val: current value + * @lo: minimum allowable value + * @hi: maximum allowable value + * + * This macro does no typechecking and uses temporary variables of type + * 'type' to make all the comparisons. + */ +#define clamp_t(type, val, lo, hi) min_t(type, max_t(type, val, lo), hi) + +/** + * clamp_val - return a value clamped to a given range using val's type + * @val: current value + * @lo: minimum allowable value + * @hi: maximum allowable value + * + * This macro does no typechecking and uses temporary variables of whatever + * type the input argument 'val' is. This is useful when val is an unsigned + * type and min and max are literals that will otherwise be assigned a signed + * integer type. + */ +#define clamp_val(val, lo, hi) clamp_t(typeof(val), val, lo, hi) + + +/* + * swap - swap value of @a and @b + */ +#define swap(a, b) \ + do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0) + +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + +#endif diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h index 82630ad..cb166e6 100644 --- a/include/linux/usb/xhci-omap.h +++ b/include/linux/usb/xhci-omap.h @@ -14,6 +14,10 @@ #define OMAP_XHCI_BASE 0x488d0000 #define OMAP_OCP1_SCP_BASE 0x4A081000 #define OMAP_OTG_WRAPPER_BASE 0x488c0000 +#elif defined CONFIG_AM57XX +#define OMAP_XHCI_BASE 0x48890000 +#define OMAP_OCP1_SCP_BASE 0x4A084c00 +#define OMAP_OTG_WRAPPER_BASE 0x48880000 #elif defined CONFIG_AM43XX #define OMAP_XHCI_BASE 0x483d0000 #define OMAP_OCP1_SCP_BASE 0x483E8000 diff --git a/include/malloc.h b/include/malloc.h index c33f3b4..5df6348 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -872,33 +872,46 @@ extern Void_t* sbrk(); #else -#ifdef USE_DL_PREFIX -#define cALLOc dlcalloc -#define fREe dlfree -#define mALLOc dlmalloc -#define mEMALIGn dlmemalign -#define rEALLOc dlrealloc -#define vALLOc dlvalloc -#define pvALLOc dlpvalloc -#define mALLINFo dlmallinfo -#define mALLOPt dlmallopt -#else /* USE_DL_PREFIX */ -#define cALLOc calloc -#define fREe free -#define mALLOc malloc -#define mEMALIGn memalign -#define rEALLOc realloc -#define vALLOc valloc -#define pvALLOc pvalloc -#define mALLINFo mallinfo -#define mALLOPt mallopt -#endif /* USE_DL_PREFIX */ +#ifdef CONFIG_SYS_MALLOC_SIMPLE +#define malloc malloc_simple +#define realloc realloc_simple +#define memalign memalign_simple +static inline void free(void *ptr) {} +void *calloc(size_t nmemb, size_t size); +void *memalign_simple(size_t alignment, size_t bytes); +void *realloc_simple(void *ptr, size_t size); +#else + +# ifdef USE_DL_PREFIX +# define cALLOc dlcalloc +# define fREe dlfree +# define mALLOc dlmalloc +# define mEMALIGn dlmemalign +# define rEALLOc dlrealloc +# define vALLOc dlvalloc +# define pvALLOc dlpvalloc +# define mALLINFo dlmallinfo +# define mALLOPt dlmallopt +# else /* USE_DL_PREFIX */ +# define cALLOc calloc +# define fREe free +# define mALLOc malloc +# define mEMALIGn memalign +# define rEALLOc realloc +# define vALLOc valloc +# define pvALLOc pvalloc +# define mALLINFo mallinfo +# define mALLOPt mallopt +# endif /* USE_DL_PREFIX */ #endif /* Public routines */ -#if __STD_C +/* Simple versions which can be used when space is tight */ +void *malloc_simple(size_t size); + +# if __STD_C Void_t* mALLOc(size_t); void fREe(Void_t*); @@ -913,7 +926,7 @@ size_t malloc_usable_size(Void_t*); void malloc_stats(void); int mALLOPt(int, int); struct mallinfo mALLINFo(void); -#else +# else Void_t* mALLOc(); void fREe(); Void_t* rEALLOc(); @@ -927,6 +940,7 @@ size_t malloc_usable_size(); void malloc_stats(); int mALLOPt(); struct mallinfo mALLINFo(); +# endif #endif /* diff --git a/include/mmc.h b/include/mmc.h index d74a190..adffc35 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -385,6 +385,7 @@ struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); int mmc_legacy_init(int verbose); #endif +void board_mmc_power_init(void); int board_mmc_init(bd_t *bis); int cpu_mmc_init(bd_t *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); diff --git a/include/nand.h b/include/nand.h index fc735d1..15e31ab 100644 --- a/include/nand.h +++ b/include/nand.h @@ -167,3 +167,4 @@ __attribute__((noreturn)) void nand_boot(void); #define ENV_OFFSET_SIZE 8 int get_nand_env_oob(nand_info_t *nand, unsigned long *result); #endif +int spl_nand_erase_one(int block, int page); diff --git a/include/os.h b/include/os.h index 0230a7f..e3645e0 100644 --- a/include/os.h +++ b/include/os.h @@ -217,9 +217,10 @@ const char *os_dirent_get_typename(enum os_dirent_t type); * Get the size of a file * * @param fname Filename to check - * @return size of file, or -1 if an error ocurred + * @param size size of file is returned if no error + * @return 0 on success or -1 if an error ocurred */ -ssize_t os_get_filesize(const char *fname); +int os_get_filesize(const char *fname, loff_t *size); /** * Write a character to the controlling OS terminal diff --git a/include/pci.h b/include/pci.h index 2ff7365..216f448 100644 --- a/include/pci.h +++ b/include/pci.h @@ -623,6 +623,7 @@ extern void pci_register_hose(struct pci_controller* hose); extern struct pci_controller* pci_bus_to_hose(int bus); extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); +extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); extern int pci_hose_scan(struct pci_controller *hose); extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); @@ -677,5 +678,28 @@ extern void pci_mpc824x_init (struct pci_controller *hose); extern void pci_mpc85xx_init (struct pci_controller *hose); #endif +/** + * pci_write_bar32() - Write the address of a BAR including control bits + * + * This writes a raw address (with control bits) to a bar + * + * @hose: PCI hose to use + * @dev: PCI device to update + * @barnum: BAR number (0-5) + * @addr: BAR address with control bits + */ +void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, + u32 addr_and_ctrl); + +/** + * pci_read_bar32() - read the address of a bar + * + * @hose: PCI hose to use + * @dev: PCI device to inspect + * @barnum: BAR number (0-5) + * @return address of the bar, masking out any control bits + * */ +u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); + #endif /* __ASSEMBLY__ */ #endif /* _PCI_H */ diff --git a/include/pci_ids.h b/include/pci_ids.h index f84c13a..ee98bee 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -526,7 +526,19 @@ #define PCI_DEVICE_ID_AMD_11H_NB_DRAM 0x1302 #define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303 #define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304 -#define PCI_DEVICE_ID_AMD_15H_NB_MISC 0x1603 +#define PCI_DEVICE_ID_AMD_15H_M10H_F3 0x1403 +#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F3 0x141d +#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F4 0x141e +#define PCI_DEVICE_ID_AMD_15H_NB_F0 0x1600 +#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 +#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 +#define PCI_DEVICE_ID_AMD_15H_NB_F3 0x1603 +#define PCI_DEVICE_ID_AMD_15H_NB_F4 0x1604 +#define PCI_DEVICE_ID_AMD_15H_NB_F5 0x1605 +#define PCI_DEVICE_ID_AMD_16H_NB_F3 0x1533 +#define PCI_DEVICE_ID_AMD_16H_NB_F4 0x1534 +#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583 +#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584 #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703 #define PCI_DEVICE_ID_AMD_LANCE 0x2000 #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 @@ -569,8 +581,9 @@ #define PCI_DEVICE_ID_AMD_CS5536_IDE 0x209A #define PCI_DEVICE_ID_AMD_LX_VIDEO 0x2081 #define PCI_DEVICE_ID_AMD_LX_AES 0x2082 -#define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c #define PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE 0x7800 +#define PCI_DEVICE_ID_AMD_HUDSON2_SMBUS 0x780b +#define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c #define PCI_VENDOR_ID_TRIDENT 0x1023 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 @@ -616,6 +629,8 @@ #define PCI_DEVICE_ID_MATROX_G550 0x2527 #define PCI_DEVICE_ID_MATROX_VIA 0x4536 +#define PCI_VENDOR_ID_MOBILITY_ELECTRONICS 0x14f2 + #define PCI_VENDOR_ID_CT 0x102c #define PCI_DEVICE_ID_CT_69000 0x00c0 #define PCI_DEVICE_ID_CT_65545 0x00d8 @@ -724,6 +739,7 @@ #define PCI_DEVICE_ID_SI_7018 0x7018 #define PCI_VENDOR_ID_HP 0x103c +#define PCI_VENDOR_ID_HP_3PAR 0x1590 #define PCI_DEVICE_ID_HP_VISUALIZE_EG 0x1005 #define PCI_DEVICE_ID_HP_VISUALIZE_FX6 0x1006 #define PCI_DEVICE_ID_HP_VISUALIZE_FX4 0x1008 @@ -755,6 +771,8 @@ #define PCI_DEVICE_ID_HP_CISSD 0x3238 #define PCI_DEVICE_ID_HP_CISSE 0x323a #define PCI_DEVICE_ID_HP_CISSF 0x323b +#define PCI_DEVICE_ID_HP_CISSH 0x323c +#define PCI_DEVICE_ID_HP_CISSI 0x3239 #define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031 #define PCI_VENDOR_ID_PCTECH 0x1042 @@ -779,6 +797,29 @@ #define PCI_DEVICE_ID_ELSA_QS3000 0x3000 #define PCI_VENDOR_ID_STMICRO 0x104A +#define PCI_DEVICE_ID_STMICRO_USB_HOST 0xCC00 +#define PCI_DEVICE_ID_STMICRO_USB_OHCI 0xCC01 +#define PCI_DEVICE_ID_STMICRO_USB_OTG 0xCC02 +#define PCI_DEVICE_ID_STMICRO_UART_HWFC 0xCC03 +#define PCI_DEVICE_ID_STMICRO_UART_NO_HWFC 0xCC04 +#define PCI_DEVICE_ID_STMICRO_SOC_DMA 0xCC05 +#define PCI_DEVICE_ID_STMICRO_SATA 0xCC06 +#define PCI_DEVICE_ID_STMICRO_I2C 0xCC07 +#define PCI_DEVICE_ID_STMICRO_SPI_HS 0xCC08 +#define PCI_DEVICE_ID_STMICRO_MAC 0xCC09 +#define PCI_DEVICE_ID_STMICRO_SDIO_EMMC 0xCC0A +#define PCI_DEVICE_ID_STMICRO_SDIO 0xCC0B +#define PCI_DEVICE_ID_STMICRO_GPIO 0xCC0C +#define PCI_DEVICE_ID_STMICRO_VIP 0xCC0D +#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_DMA 0xCC0E +#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_SRCS 0xCC0F +#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_MSPS 0xCC10 +#define PCI_DEVICE_ID_STMICRO_CAN 0xCC11 +#define PCI_DEVICE_ID_STMICRO_MLB 0xCC12 +#define PCI_DEVICE_ID_STMICRO_DBP 0xCC13 +#define PCI_DEVICE_ID_STMICRO_SATA_PHY 0xCC14 +#define PCI_DEVICE_ID_STMICRO_ESRAM 0xCC15 +#define PCI_DEVICE_ID_STMICRO_VIC 0xCC16 #define PCI_VENDOR_ID_BUSLOGIC 0x104B #define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 @@ -1294,6 +1335,8 @@ #define PCI_VENDOR_ID_TUNDRA 0x10e3 #define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000 +#define PCI_VENDOR_ID_AMCC 0x10e8 + #define PCI_VENDOR_ID_INTERG 0x10ea #define PCI_DEVICE_ID_INTERG_1682 0x1682 #define PCI_DEVICE_ID_INTERG_2000 0x2000 @@ -1322,6 +1365,7 @@ #define PCI_SUBDEVICE_ID_CREATIVE_SB08801 0x0041 #define PCI_SUBDEVICE_ID_CREATIVE_SB08802 0x0042 #define PCI_SUBDEVICE_ID_CREATIVE_SB08803 0x0043 +#define PCI_SUBDEVICE_ID_CREATIVE_SB1270 0x0062 #define PCI_SUBDEVICE_ID_CREATIVE_HENDRIX 0x6000 #define PCI_VENDOR_ID_ECTIVA 0x1102 /* duplicate: CREATIVE */ @@ -1411,6 +1455,7 @@ #define PCI_DEVICE_ID_VIA_CX700_IDE 0x0581 #define PCI_DEVICE_ID_VIA_VX800 0x8353 #define PCI_DEVICE_ID_VIA_VX855 0x8409 +#define PCI_DEVICE_ID_VIA_VX900 0x8410 #define PCI_DEVICE_ID_VIA_8371_1 0x8391 #define PCI_DEVICE_ID_VIA_82C598_1 0x8598 #define PCI_DEVICE_ID_VIA_838X_1 0xB188 @@ -1551,6 +1596,8 @@ #define PCI_DEVICE_ID_RICOH_RL5C476 0x0476 #define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 #define PCI_DEVICE_ID_RICOH_R5C822 0x0822 +#define PCI_DEVICE_ID_RICOH_R5CE822 0xe822 +#define PCI_DEVICE_ID_RICOH_R5CE823 0xe823 #define PCI_DEVICE_ID_RICOH_R5C832 0x0832 #define PCI_DEVICE_ID_RICOH_R5C843 0x0843 @@ -1586,6 +1633,7 @@ #define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334 #define PCI_VENDOR_ID_MARVELL 0x11ab +#define PCI_VENDOR_ID_MARVELL_EXT 0x1b4b #define PCI_DEVICE_ID_MARVELL_GT64111 0x4146 #define PCI_DEVICE_ID_MARVELL_GT64260 0x6430 #define PCI_DEVICE_ID_MARVELL_MV64360 0x6460 @@ -1798,6 +1846,8 @@ #define PCI_VENDOR_ID_ESDGMBH 0x12fe #define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111 +#define PCI_VENDOR_ID_CB 0x1307 /* Measurement Computing */ + #define PCI_VENDOR_ID_SIIG 0x131f #define PCI_SUBVENDOR_ID_SIIG 0x131f #define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000 @@ -1860,8 +1910,23 @@ #define PCI_VENDOR_ID_QUATECH 0x135C #define PCI_DEVICE_ID_QUATECH_QSC100 0x0010 #define PCI_DEVICE_ID_QUATECH_DSC100 0x0020 +#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030 +#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040 #define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050 #define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060 +#define PCI_DEVICE_ID_QUATECH_QSCP100 0x0120 +#define PCI_DEVICE_ID_QUATECH_DSCP100 0x0130 +#define PCI_DEVICE_ID_QUATECH_QSCP200 0x0140 +#define PCI_DEVICE_ID_QUATECH_DSCP200 0x0150 +#define PCI_DEVICE_ID_QUATECH_QSCLP100 0x0170 +#define PCI_DEVICE_ID_QUATECH_DSCLP100 0x0180 +#define PCI_DEVICE_ID_QUATECH_DSC100E 0x0181 +#define PCI_DEVICE_ID_QUATECH_SSCLP100 0x0190 +#define PCI_DEVICE_ID_QUATECH_QSCLP200 0x01A0 +#define PCI_DEVICE_ID_QUATECH_DSCLP200 0x01B0 +#define PCI_DEVICE_ID_QUATECH_DSC200E 0x01B1 +#define PCI_DEVICE_ID_QUATECH_SSCLP200 0x01C0 +#define PCI_DEVICE_ID_QUATECH_ESCLP100 0x01E0 #define PCI_DEVICE_ID_QUATECH_SPPXP_100 0x0278 #define PCI_VENDOR_ID_SEALEVEL 0x135e @@ -1978,6 +2043,9 @@ #define PCI_DEVICE_ID_EXAR_XR17C152 0x0152 #define PCI_DEVICE_ID_EXAR_XR17C154 0x0154 #define PCI_DEVICE_ID_EXAR_XR17C158 0x0158 +#define PCI_DEVICE_ID_EXAR_XR17V352 0x0352 +#define PCI_DEVICE_ID_EXAR_XR17V354 0x0354 +#define PCI_DEVICE_ID_EXAR_XR17V358 0x0358 #define PCI_VENDOR_ID_MICROGATE 0x13c0 #define PCI_DEVICE_ID_MICROGATE_USC 0x0010 @@ -2002,6 +2070,10 @@ #define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112 +#define PCI_VENDOR_ID_ADVANTECH 0x13fe + +#define PCI_VENDOR_ID_MEILHAUS 0x1402 + #define PCI_VENDOR_ID_LAVA 0x1407 #define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */ #define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */ @@ -2047,6 +2119,8 @@ #define PCI_VENDOR_ID_CHELSIO 0x1425 +#define PCI_VENDOR_ID_ADLINK 0x144a + #define PCI_VENDOR_ID_SAMSUNG 0x144d #define PCI_VENDOR_ID_GIGABYTE 0x1458 @@ -2080,6 +2154,8 @@ #define PCI_DEVICE_ID_AFAVLAB_P030 0x2182 #define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150 +#define PCI_VENDOR_ID_AMPLICON 0x14dc + #define PCI_VENDOR_ID_BCM_GVC 0x14a4 #define PCI_VENDOR_ID_BROADCOM 0x14e4 #define PCI_DEVICE_ID_TIGON3_5752 0x1600 @@ -2100,19 +2176,25 @@ #define PCI_DEVICE_ID_NX2_57711E 0x1650 #define PCI_DEVICE_ID_TIGON3_5705 0x1653 #define PCI_DEVICE_ID_TIGON3_5705_2 0x1654 +#define PCI_DEVICE_ID_TIGON3_5719 0x1657 #define PCI_DEVICE_ID_TIGON3_5721 0x1659 #define PCI_DEVICE_ID_TIGON3_5722 0x165a #define PCI_DEVICE_ID_TIGON3_5723 0x165b #define PCI_DEVICE_ID_TIGON3_5705M 0x165d #define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e +#define PCI_DEVICE_ID_NX2_57712 0x1662 +#define PCI_DEVICE_ID_NX2_57712E 0x1663 +#define PCI_DEVICE_ID_NX2_57712_MF 0x1663 #define PCI_DEVICE_ID_TIGON3_5714 0x1668 #define PCI_DEVICE_ID_TIGON3_5714S 0x1669 #define PCI_DEVICE_ID_TIGON3_5780 0x166a #define PCI_DEVICE_ID_TIGON3_5780S 0x166b #define PCI_DEVICE_ID_TIGON3_5705F 0x166e +#define PCI_DEVICE_ID_NX2_57712_VF 0x166f #define PCI_DEVICE_ID_TIGON3_5754M 0x1672 #define PCI_DEVICE_ID_TIGON3_5755M 0x1673 #define PCI_DEVICE_ID_TIGON3_5756 0x1674 +#define PCI_DEVICE_ID_TIGON3_5750 0x1676 #define PCI_DEVICE_ID_TIGON3_5751 0x1677 #define PCI_DEVICE_ID_TIGON3_5715 0x1678 #define PCI_DEVICE_ID_TIGON3_5715S 0x1679 @@ -2124,6 +2206,9 @@ #define PCI_DEVICE_ID_TIGON3_5761E 0x1680 #define PCI_DEVICE_ID_TIGON3_5761 0x1681 #define PCI_DEVICE_ID_TIGON3_5764 0x1684 +#define PCI_DEVICE_ID_NX2_57800 0x168a +#define PCI_DEVICE_ID_NX2_57840 0x168d +#define PCI_DEVICE_ID_NX2_57810 0x168e #define PCI_DEVICE_ID_TIGON3_5787M 0x1693 #define PCI_DEVICE_ID_TIGON3_5782 0x1696 #define PCI_DEVICE_ID_TIGON3_5784 0x1698 @@ -2131,11 +2216,19 @@ #define PCI_DEVICE_ID_TIGON3_5787 0x169b #define PCI_DEVICE_ID_TIGON3_5788 0x169c #define PCI_DEVICE_ID_TIGON3_5789 0x169d +#define PCI_DEVICE_ID_NX2_57840_4_10 0x16a1 +#define PCI_DEVICE_ID_NX2_57840_2_20 0x16a2 +#define PCI_DEVICE_ID_NX2_57840_MF 0x16a4 +#define PCI_DEVICE_ID_NX2_57800_MF 0x16a5 #define PCI_DEVICE_ID_TIGON3_5702X 0x16a6 #define PCI_DEVICE_ID_TIGON3_5703X 0x16a7 #define PCI_DEVICE_ID_TIGON3_5704S 0x16a8 +#define PCI_DEVICE_ID_NX2_57800_VF 0x16a9 #define PCI_DEVICE_ID_NX2_5706S 0x16aa #define PCI_DEVICE_ID_NX2_5708S 0x16ac +#define PCI_DEVICE_ID_NX2_57840_VF 0x16ad +#define PCI_DEVICE_ID_NX2_57810_MF 0x16ae +#define PCI_DEVICE_ID_NX2_57810_VF 0x16af #define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6 #define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7 #define PCI_DEVICE_ID_TIGON3_5781 0x16dd @@ -2307,6 +2400,8 @@ #define PCI_VENDOR_ID_TOPSPIN 0x1867 +#define PCI_VENDOR_ID_COMMTECH 0x18f7 + #define PCI_VENDOR_ID_SILAN 0x1904 #define PCI_VENDOR_ID_RENESAS 0x1912 @@ -2316,6 +2411,11 @@ #define PCI_DEVICE_ID_RENESAS_SH7785 0x0007 #define PCI_DEVICE_ID_RENESAS_SH7786 0x0010 +#define PCI_VENDOR_ID_SOLARFLARE 0x1924 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0 0x0703 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1 0x6703 +#define PCI_DEVICE_ID_SOLARFLARE_SFC4000B 0x0710 + #define PCI_VENDOR_ID_TDI 0x192E #define PCI_DEVICE_ID_TDI_EHCI 0x0101 @@ -2414,6 +2514,11 @@ #define PCI_VENDOR_ID_AZWAVE 0x1a3b +#define PCI_VENDOR_ID_ASMEDIA 0x1b21 + +#define PCI_VENDOR_ID_CIRCUITCO 0x1cc8 +#define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD 0x0001 + #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 @@ -2463,6 +2568,9 @@ #define PCI_VENDOR_ID_INTEL 0x8086 #define PCI_DEVICE_ID_INTEL_EESSC 0x0008 +#define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100 +#define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154 +#define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00 #define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320 #define PCI_DEVICE_ID_INTEL_PXHD_1 0x0321 #define PCI_DEVICE_ID_INTEL_PXH_0 0x0329 @@ -2485,6 +2593,7 @@ #define PCI_DEVICE_ID_INTEL_MRST_SD2 0x084F #define PCI_DEVICE_ID_INTEL_I960 0x0960 #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 +#define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60 #define PCI_DEVICE_ID_INTEL_82541ER 0x1078 #define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c #define PCI_DEVICE_ID_INTEL_82542 0x1000 @@ -2564,13 +2673,50 @@ #define PCI_DEVICE_ID_INTEL_COUGARPOINT_HDA 0x1c20 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Z68 0x1c44 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_P67 0x1c46 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_UM67 0x1c47 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM65 0x1c49 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H67 0x1c4a +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM67 0x1c4b +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q65 0x1c4c +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QS67 0x1c4d +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q67 0x1c4e +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QM67 0x1c4f +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_B65 0x1c50 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C202 0x1c52 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C204 0x1c54 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C206 0x1c56 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H61 0x1c5c #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f -#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03 -#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA 0x1e20 -#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41 -#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 #define PCI_DEVICE_ID_INTEL_PATSBURG_LPC 0x1d40 +#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0 0x1d40 +#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1 0x1d41 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA 0x1e20 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI 0x1e31 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_B75 0x1e49 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_C216 0x1e53 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_H77 0x1e4A +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM70 0x1e5e +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM75 0x1e5d +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM76 0x1e59 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM77 0x1e57 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MBL_SAMPLE 0x1e42 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_NM70 0x1e5f +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Q75 0x1e48 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Q77 0x1e47 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_QM77 0x1e55 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_QS77 0x1e56 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_SFF_SAMPLE 0x1e43 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_UM77 0x1e58 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Z75 0x1e46 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Z77 0x1e44 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f +#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN 0x2310 +#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX 0x231f #define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410 #define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411 #define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413 @@ -2783,8 +2929,30 @@ #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN 0x3b00 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX 0x3b1f #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB0 0x3c20 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB1 0x3c21 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB2 0x3c22 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB3 0x3c23 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB4 0x3c24 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB5 0x3c25 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB6 0x3c26 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 0x3c27 +#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 0x3c2e +#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 0x3c2f +#define PCI_DEVICE_ID_INTEL_UNC_HA 0x3c46 +#define PCI_DEVICE_ID_INTEL_UNC_IMC0 0x3cb0 +#define PCI_DEVICE_ID_INTEL_UNC_IMC1 0x3cb1 +#define PCI_DEVICE_ID_INTEL_UNC_IMC2 0x3cb4 +#define PCI_DEVICE_ID_INTEL_UNC_IMC3 0x3cb5 +#define PCI_DEVICE_ID_INTEL_UNC_QPI0 0x3c41 +#define PCI_DEVICE_ID_INTEL_UNC_QPI1 0x3c42 +#define PCI_DEVICE_ID_INTEL_UNC_R2PCIE 0x3c43 +#define PCI_DEVICE_ID_INTEL_UNC_R3QPI0 0x3c44 +#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45 +#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0 #define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f #define PCI_DEVICE_ID_INTEL_5100_16 0x65f0 +#define PCI_DEVICE_ID_INTEL_5100_19 0x65f3 #define PCI_DEVICE_ID_INTEL_5100_21 0x65f5 #define PCI_DEVICE_ID_INTEL_5100_22 0x65f6 #define PCI_DEVICE_ID_INTEL_5400_ERR 0x4030 @@ -2823,6 +2991,7 @@ #define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601 #define PCI_DEVICE_ID_INTEL_SCH_LPC 0x8119 #define PCI_DEVICE_ID_INTEL_SCH_IDE 0x811a +#define PCI_DEVICE_ID_INTEL_ITC_LPC 0x8186 #define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 #define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 #define PCI_DEVICE_ID_INTEL_82451NX 0x84ca @@ -2905,7 +3074,11 @@ #define PCI_DEVICE_ID_NETMOS_9845 0x9845 #define PCI_DEVICE_ID_NETMOS_9855 0x9855 #define PCI_DEVICE_ID_NETMOS_9865 0x9865 +#define PCI_DEVICE_ID_NETMOS_9900 0x9900 #define PCI_DEVICE_ID_NETMOS_9901 0x9901 +#define PCI_DEVICE_ID_NETMOS_9904 0x9904 +#define PCI_DEVICE_ID_NETMOS_9912 0x9912 +#define PCI_DEVICE_ID_NETMOS_9922 0x9922 #define PCI_VENDOR_ID_3COM_2 0xa727 @@ -2927,3 +3100,5 @@ #define PCI_VENDOR_ID_XEN 0x5853 #define PCI_DEVICE_ID_XEN_PLATFORM 0x0001 + +#define PCI_VENDOR_ID_OCZ 0x1b85 diff --git a/include/pci_rom.h b/include/pci_rom.h new file mode 100644 index 0000000..8b2674c --- /dev/null +++ b/include/pci_rom.h @@ -0,0 +1,58 @@ +/* + * From coreboot file of same name + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PCI_ROM_H +#define _PCI_ROM_H + +#define PCI_ROM_HDR 0xaa55 +#define PCI_VGA_RAM_IMAGE_START 0xc0000 + +struct pci_rom_header { + uint16_t signature; + uint8_t size; + uint8_t init[3]; + uint8_t reserved[0x12]; + uint16_t data; +}; + +struct pci_rom_data { + uint32_t signature; + uint16_t vendor; + uint16_t device; + uint16_t reserved_1; + uint16_t dlen; + uint8_t drevision; + uint8_t class_lo; + uint16_t class_hi; + uint16_t ilen; + uint16_t irevision; + uint8_t type; + uint8_t indicator; + uint16_t reserved_2; +}; + + /** + * pci_run_vga_bios() - Run the VGA BIOS in an x86 PC + * + * @dev: Video device containing the BIOS + * @int15_handler: Function to call to handle int 0x15 + * @emulate: true to use the x86 emulator, false to run native + */ +int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate); + +/** + * board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects + * + * Some VGA option roms are used for several chipsets but they only have one + * PCI ID in their header. If we encounter such an option rom, we need to do + * the mapping ourselves. + * + * @vendev: Vendor and device for the video device + * @return standard vendor and device expected by the ROM + */ +uint32_t board_map_oprom_vendev(uint32_t vendev); + +#endif diff --git a/include/phy.h b/include/phy.h index b495077..1e282e2 100644 --- a/include/phy.h +++ b/include/phy.h @@ -41,6 +41,7 @@ typedef enum { PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_SGMII_2500, PHY_INTERFACE_MODE_QSGMII, PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RMII, @@ -57,6 +58,7 @@ static const char *phy_interface_strings[] = { [PHY_INTERFACE_MODE_MII] = "mii", [PHY_INTERFACE_MODE_GMII] = "gmii", [PHY_INTERFACE_MODE_SGMII] = "sgmii", + [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", [PHY_INTERFACE_MODE_TBI] = "tbi", [PHY_INTERFACE_MODE_RMII] = "rmii", @@ -225,6 +227,7 @@ int gen10g_discover_mmds(struct phy_device *phydev); int phy_atheros_init(void); int phy_broadcom_init(void); +int phy_cortina_init(void); int phy_davicom_init(void); int phy_et1011c_init(void); int phy_lxt_init(void); @@ -239,6 +242,7 @@ int phy_vitesse_init(void); int board_phy_config(struct phy_device *phydev); /* PHY UIDs for various PHYs that are referenced in external code */ +#define PHY_UID_CS4340 0x13e51002 #define PHY_UID_TN2020 0x00a19410 #endif diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h index c2a772a..b0e4255 100644 --- a/include/power/max77686_pmic.h +++ b/include/power/max77686_pmic.h @@ -150,6 +150,7 @@ enum { int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV); int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode); +int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV); int max77686_set_buck_mode(struct pmic *p, int buck, char opmode); #define MAX77686_LDO_VOLT_MAX_HEX 0x3f @@ -159,6 +160,8 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode); #define MAX77686_LDO_MODE_STANDBY (0x01 << 0x06) #define MAX77686_LDO_MODE_LPM (0x02 << 0x06) #define MAX77686_LDO_MODE_ON (0x03 << 0x06) +#define MAX77686_BUCK_VOLT_MAX_HEX 0x3f +#define MAX77686_BUCK_VOLT_MASK 0x3f #define MAX77686_BUCK_MODE_MASK 0x03 #define MAX77686_BUCK_MODE_SHIFT_1 0x00 #define MAX77686_BUCK_MODE_SHIFT_2 0x04 diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h index 0002f1e..1118489 100644 --- a/include/power/pfuze100_pmic.h +++ b/include/power/pfuze100_pmic.h @@ -38,6 +38,86 @@ enum { }; /* + * Buck Regulators + */ + +/* SW1A/B/C Output Voltage Configuration */ +#define SW1x_0_300V 0 +#define SW1x_0_325V 1 +#define SW1x_0_350V 2 +#define SW1x_0_375V 3 +#define SW1x_0_400V 4 +#define SW1x_0_425V 5 +#define SW1x_0_450V 6 +#define SW1x_0_475V 7 +#define SW1x_0_500V 8 +#define SW1x_0_525V 9 +#define SW1x_0_550V 10 +#define SW1x_0_575V 11 +#define SW1x_0_600V 12 +#define SW1x_0_625V 13 +#define SW1x_0_650V 14 +#define SW1x_0_675V 15 +#define SW1x_0_700V 16 +#define SW1x_0_725V 17 +#define SW1x_0_750V 18 +#define SW1x_0_775V 19 +#define SW1x_0_800V 20 +#define SW1x_0_825V 21 +#define SW1x_0_850V 22 +#define SW1x_0_875V 23 +#define SW1x_0_900V 24 +#define SW1x_0_925V 25 +#define SW1x_0_950V 26 +#define SW1x_0_975V 27 +#define SW1x_1_000V 28 +#define SW1x_1_025V 29 +#define SW1x_1_050V 30 +#define SW1x_1_075V 31 +#define SW1x_1_100V 32 +#define SW1x_1_125V 33 +#define SW1x_1_150V 34 +#define SW1x_1_175V 35 +#define SW1x_1_200V 36 +#define SW1x_1_225V 37 +#define SW1x_1_250V 38 +#define SW1x_1_275V 39 +#define SW1x_1_300V 40 +#define SW1x_1_325V 41 +#define SW1x_1_350V 42 +#define SW1x_1_375V 43 +#define SW1x_1_400V 44 +#define SW1x_1_425V 45 +#define SW1x_1_450V 46 +#define SW1x_1_475V 47 +#define SW1x_1_500V 48 +#define SW1x_1_525V 49 +#define SW1x_1_550V 50 +#define SW1x_1_575V 51 +#define SW1x_1_600V 52 +#define SW1x_1_625V 53 +#define SW1x_1_650V 54 +#define SW1x_1_675V 55 +#define SW1x_1_700V 56 +#define SW1x_1_725V 57 +#define SW1x_1_750V 58 +#define SW1x_1_775V 59 +#define SW1x_1_800V 60 +#define SW1x_1_825V 61 +#define SW1x_1_850V 62 +#define SW1x_1_875V 63 + +#define SW1x_NORMAL_MASK 0x3f +#define SW1x_STBY_MASK 0x3f +#define SW1x_OFF_MASK 0x3f + +#define SW1xCONF_DVSSPEED_MASK 0xc0 +#define SW1xCONF_DVSSPEED_2US 0x00 +#define SW1xCONF_DVSSPEED_4US 0x40 +#define SW1xCONF_DVSSPEED_8US 0x80 +#define SW1xCONF_DVSSPEED_16US 0xc0 + +/* * LDO Configuration */ diff --git a/include/rtc.h b/include/rtc.h index c034966..d11aa8b 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -50,4 +50,9 @@ void to_tm (int, struct rtc_time *); unsigned long mktime (unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); +/** + * rtc_init() - Set up the real time clock ready for use + */ +void rtc_init(void); + #endif /* _RTC_H_ */ diff --git a/include/sandboxfs.h b/include/sandboxfs.h index e7c3262..4c7745d 100644 --- a/include/sandboxfs.h +++ b/include/sandboxfs.h @@ -20,14 +20,18 @@ int sandbox_fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); -long sandbox_fs_read_at(const char *filename, unsigned long pos, - void *buffer, unsigned long maxsize); +int sandbox_fs_read_at(const char *filename, loff_t pos, void *buffer, + loff_t maxsize, loff_t *actread); +int sandbox_fs_write_at(const char *filename, loff_t pos, void *buffer, + loff_t maxsize, loff_t *actwrite); void sandbox_fs_close(void); int sandbox_fs_ls(const char *dirname); int sandbox_fs_exists(const char *filename); -int sandbox_fs_size(const char *filename); -int fs_read_sandbox(const char *filename, void *buf, int offset, int len); -int fs_write_sandbox(const char *filename, void *buf, int offset, int len); +int sandbox_fs_size(const char *filename, loff_t *size); +int fs_read_sandbox(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread); +int fs_write_sandbox(const char *filename, void *buf, loff_t offset, + loff_t len, loff_t *actwrite); #endif diff --git a/include/sata.h b/include/sata.h index 38f4b4a..fa61da8 100644 --- a/include/sata.h +++ b/include/sata.h @@ -3,12 +3,15 @@ #include <part.h> int init_sata(int dev); +int reset_sata(int dev); int scan_sata(int dev); ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer); ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer); int sata_initialize(void); int __sata_initialize(void); +int sata_stop(void); +int __sata_stop(void); int sata_port_status(int dev, int port); extern block_dev_desc_t sata_dev_desc[]; diff --git a/include/sh_tmu.h b/include/sh_tmu.h index 61afc71..97d578d 100644 --- a/include/sh_tmu.h +++ b/include/sh_tmu.h @@ -25,7 +25,7 @@ #include <asm/types.h> -#if defined(CONFIG_SH3) +#if defined(CONFIG_CPU_SH3) struct tmu_regs { u8 tocr; u8 reserved0; @@ -45,9 +45,9 @@ struct tmu_regs { u16 reserved4; u32 tcpr2; }; -#endif /* CONFIG_SH3 */ +#endif /* CONFIG_CPU_SH3 */ -#if defined(CONFIG_SH4) || defined(CONFIG_RMOBILE) +#if defined(CONFIG_CPU_SH4) || defined(CONFIG_RMOBILE) struct tmu_regs { u32 reserved; u8 tstr; @@ -65,7 +65,7 @@ struct tmu_regs { u16 tcr2; u16 reserved5; }; -#endif /* CONFIG_SH4 */ +#endif /* CONFIG_CPU_SH4 */ static inline unsigned long get_tmu0_clk_rate(void) { diff --git a/include/spi.h b/include/spi.h index aa0a48e..5b78271 100644 --- a/include/spi.h +++ b/include/spi.h @@ -534,18 +534,14 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, int spi_chip_select(struct udevice *slave); /** - * spi_bind_device() - bind a device to a bus's chip select - * - * This binds a new device to an given chip select (which must be unused). + * spi_find_chip_select() - Find the slave attached to chip select * * @bus: SPI bus to search - * @cs: Chip select to attach to - * @drv_name: Name of driver to attach to this chip select - * @dev_name: Name of the new device thus created - * @devp: Returns the newly bound device + * @cs: Chip select to look for + * @devp: Returns the slave device if found + * @return 0 if found, -ENODEV on error */ -int spi_bind_device(struct udevice *bus, int cs, const char *drv_name, - const char *dev_name, struct udevice **devp); +int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp); /** * spi_ofdata_to_platdata() - decode standard SPI platform data diff --git a/include/spl.h b/include/spl.h index 16b3566..b2e5bf7 100644 --- a/include/spl.h +++ b/include/spl.h @@ -35,6 +35,7 @@ extern struct spl_image_info spl_image; void preloader_console_init(void); u32 spl_boot_device(void); u32 spl_boot_mode(void); +void spl_set_header_raw_uboot(void); void spl_parse_image_header(const struct image_header *header); void spl_board_prepare_for_linux(void); void __noreturn jump_to_image_linux(void *arg); diff --git a/include/thermal.h b/include/thermal.h new file mode 100644 index 0000000..5d6101b --- /dev/null +++ b/include/thermal.h @@ -0,0 +1,42 @@ +/* + * + * (C) Copyright 2014 Freescale Semiconductor, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _THERMAL_H_ +#define _THERMAL_H_ + +#include <dm.h> + +int thermal_get_temp(struct udevice *dev, int *temp); + +/** + * struct struct dm_thermal_ops - Driver model Thermal operations + * + * The uclass interface is implemented by all Thermal devices which use + * driver model. + */ +struct dm_thermal_ops { + /** + * Get the current temperature + * + * The device provided is the slave device. It's parent controller + * will be used to provide the communication. + * + * This must be called before doing any transfers with a Thermal slave. + * It will enable and initialize any Thermal hardware as necessary, + * and make sure that the SCK line is in the correct idle state. It is + * not allowed to claim the same bus for several slaves without + * releasing the bus in between. + * + * @dev: The Thermal device + * + * Returns: 0 if the bus was claimed successfully, or a negative value + * if it wasn't. + */ + int (*get_temp)(struct udevice *dev, int *temp); +}; + +#endif /* _THERMAL_H_ */ diff --git a/include/twl4030.h b/include/twl4030.h index f33cd1e..50f8da8 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -651,7 +651,7 @@ void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, /* For initializing power device */ void twl4030_power_init(void); /* For initializing mmc power */ -void twl4030_power_mmc_init(void); +void twl4030_power_mmc_init(int dev_index); /* * LED diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index 1fd15f4..324fe72 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -51,6 +51,14 @@ #undef CONFIG_MTD_UBI_BLOCK +/* ubi_init() disables returning error codes when built into the Linux + * kernel so that it doesn't hang the Linux kernel boot process. Since + * the U-Boot driver code depends on getting valid error codes from this + * function we just tell the UBI layer that we are building as a module + * (which only enables the additional error reporting). + */ +#define CONFIG_MTD_UBI_MODULE + #if !defined(CONFIG_MTD_UBI_BEB_LIMIT) #define CONFIG_MTD_UBI_BEB_LIMIT 20 #endif diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index 22114c1..e9349b5 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -163,6 +163,9 @@ #elif defined(CONFIG_MPC512X) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 +#elif defined(CONFIG_LS102XA) +#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR +#define CONFIG_SYS_FSL_USB2_ADDR 0 #endif /* diff --git a/include/vbe.h b/include/vbe.h new file mode 100644 index 0000000..d405691 --- /dev/null +++ b/include/vbe.h @@ -0,0 +1,103 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * Copyright (c) 2009 Pattrick Hueper <phueper@hueper.net> + * All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ +#ifndef _VBE_H +#define _VBE_H + +/* these structs are for input from and output to OF */ +struct __packed screen_info { + u8 display_type; /* 0=NONE, 1= analog, 2=digital */ + u16 screen_width; + u16 screen_height; + /* bytes per line in framebuffer, may be more than screen_width */ + u16 screen_linebytes; + u8 color_depth; /* color depth in bits per pixel */ + u32 framebuffer_address; + u8 edid_block_zero[128]; +}; + +struct __packed screen_info_input { + u8 signature[4]; + u16 size_reserved; + u8 monitor_number; + u16 max_screen_width; + u8 color_depth; +}; + +/* these structs only store the required a subset of the VBE-defined fields */ +struct __packed vbe_info { + char signature[4]; + u16 version; + u8 *oem_string_ptr; + u32 capabilities; + u16 video_mode_list[256]; + u16 total_memory; +}; + +struct __packed vesa_mode_info { + u16 mode_attributes; /* 00 */ + u8 win_a_attributes; /* 02 */ + u8 win_b_attributes; /* 03 */ + u16 win_granularity; /* 04 */ + u16 win_size; /* 06 */ + u16 win_a_segment; /* 08 */ + u16 win_b_segment; /* 0a */ + u32 win_func_ptr; /* 0c */ + u16 bytes_per_scanline; /* 10 */ + u16 x_resolution; /* 12 */ + u16 y_resolution; /* 14 */ + u8 x_charsize; /* 16 */ + u8 y_charsize; /* 17 */ + u8 number_of_planes; /* 18 */ + u8 bits_per_pixel; /* 19 */ + u8 number_of_banks; /* 20 */ + u8 memory_model; /* 21 */ + u8 bank_size; /* 22 */ + u8 number_of_image_pages; /* 23 */ + u8 reserved_page; + u8 red_mask_size; + u8 red_mask_pos; + u8 green_mask_size; + u8 green_mask_pos; + u8 blue_mask_size; + u8 blue_mask_pos; + u8 reserved_mask_size; + u8 reserved_mask_pos; + u8 direct_color_mode_info; + u32 phys_base_ptr; + u32 offscreen_mem_offset; + u16 offscreen_mem_size; + u8 reserved[206]; +}; + +struct vbe_mode_info { + u16 video_mode; + bool valid; + union { + struct vesa_mode_info vesa; + u8 mode_info_block[256]; + }; +}; + +struct vbe_ddc_info { + u8 port_number; /* i.e. monitor number */ + u8 edid_transfer_time; + u8 ddc_level; + u8 edid_block_zero[128]; +}; + +#define VESA_GET_INFO 0x4f00 +#define VESA_GET_MODE_INFO 0x4f01 +#define VESA_SET_MODE 0x4f02 + +struct graphic_device; +int vbe_get_video_info(struct graphic_device *gdev); + +#endif diff --git a/include/video_fb.h b/include/video_fb.h index 6cd4e37..55ec24d 100644 --- a/include/video_fb.h +++ b/include/video_fb.h @@ -40,7 +40,7 @@ /* Export Graphic Driver Control */ /******************************************************************************/ -typedef struct { +typedef struct graphic_device { unsigned int isaBase; unsigned int pciBase; unsigned int dprBase; diff --git a/lib/Makefile b/lib/Makefile index 320197a..3ceb697 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -11,14 +11,12 @@ obj-$(CONFIG_RSA) += rsa/ obj-$(CONFIG_LZMA) += lzma/ obj-$(CONFIG_LZO) += lzo/ obj-$(CONFIG_ZLIB) += zlib/ +obj-$(CONFIG_BZIP2) += bzip2/ obj-$(CONFIG_TIZEN) += tizen/ +obj-$(CONFIG_OF_LIBFDT) += libfdt/ +obj-$(CONFIG_FIT) += libfdt/ obj-$(CONFIG_AES) += aes.o -obj-$(CONFIG_BZIP2) += bzlib.o -obj-$(CONFIG_BZIP2) += bzlib_crctable.o -obj-$(CONFIG_BZIP2) += bzlib_decompress.o -obj-$(CONFIG_BZIP2) += bzlib_randtable.o -obj-$(CONFIG_BZIP2) += bzlib_huffman.o obj-$(CONFIG_USB_TTY) += circbuf.o obj-y += crc7.o obj-y += crc8.o diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c index 129bc3e..580f763 100644 --- a/lib/asm-offsets.c +++ b/lib/asm-offsets.c @@ -31,6 +31,9 @@ int main(void) #ifdef CONFIG_SYS_MALLOC_F_LEN DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base)); #endif +#ifdef CONFIG_X86 + DEFINE(GD_BIST, offsetof(struct global_data, arch.bist)); +#endif #if defined(CONFIG_ARM) diff --git a/lib/bzip2/Makefile b/lib/bzip2/Makefile new file mode 100644 index 0000000..929c24e --- /dev/null +++ b/lib/bzip2/Makefile @@ -0,0 +1,2 @@ +obj-y += bzlib.o bzlib_crctable.o bzlib_decompress.o \ + bzlib_randtable.o bzlib_huffman.o diff --git a/lib/bzlib.c b/lib/bzip2/bzlib.c index 5844e18..5844e18 100644 --- a/lib/bzlib.c +++ b/lib/bzip2/bzlib.c diff --git a/lib/bzlib_crctable.c b/lib/bzip2/bzlib_crctable.c index 325b966..325b966 100644 --- a/lib/bzlib_crctable.c +++ b/lib/bzip2/bzlib_crctable.c diff --git a/lib/bzlib_decompress.c b/lib/bzip2/bzlib_decompress.c index 4412b8a..4412b8a 100644 --- a/lib/bzlib_decompress.c +++ b/lib/bzip2/bzlib_decompress.c diff --git a/lib/bzlib_huffman.c b/lib/bzip2/bzlib_huffman.c index 801b8ec..801b8ec 100644 --- a/lib/bzlib_huffman.c +++ b/lib/bzip2/bzlib_huffman.c diff --git a/lib/bzlib_private.h b/lib/bzip2/bzlib_private.h index 87d8f94..87d8f94 100644 --- a/lib/bzlib_private.h +++ b/lib/bzip2/bzlib_private.h diff --git a/lib/bzlib_randtable.c b/lib/bzip2/bzlib_randtable.c index c3dc7e4..c3dc7e4 100644 --- a/lib/bzlib_randtable.c +++ b/lib/bzip2/bzlib_randtable.c diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 9714620..9d86dba 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -73,6 +73,11 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"), COMPAT(PARADE_PS8625, "parade,ps8625"), COMPAT(COMPAT_INTEL_LPC, "intel,lpc"), + COMPAT(INTEL_MICROCODE, "intel,microcode"), + COMPAT(MEMORY_SPD, "memory-spd"), + COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"), + COMPAT(INTEL_MODEL_206AX, "intel,model-206ax"), + COMPAT(INTEL_GMA, "intel,gma"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) @@ -355,9 +360,9 @@ int fdtdec_get_alias_seq(const void *blob, const char *base, int offset, slash = strrchr(prop, '/'); if (strcmp(slash + 1, find_name)) continue; - for (p = name; *p; p++) { - if (isdigit(*p)) { - *seqp = simple_strtoul(p, NULL, 10); + for (p = name + strlen(name) - 1; p > name; p--) { + if (!isdigit(*p)) { + *seqp = simple_strtoul(p + 1, NULL, 10); debug("Found seq %d\n", *seqp); return 0; } @@ -368,21 +373,6 @@ int fdtdec_get_alias_seq(const void *blob, const char *base, int offset, return -ENOENT; } -int fdtdec_get_alias_node(const void *blob, const char *name) -{ - const char *prop; - int alias_node; - int len; - - if (!blob) - return -FDT_ERR_NOTFOUND; - alias_node = fdt_path_offset(blob, "/aliases"); - prop = fdt_getprop(blob, alias_node, name, &len); - if (!prop) - return -FDT_ERR_NOTFOUND; - return fdt_path_offset(blob, prop); -} - int fdtdec_get_chosen_node(const void *blob, const char *name) { const char *prop; @@ -485,6 +475,26 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, return err; } +int fdtdec_get_int_array_count(const void *blob, int node, + const char *prop_name, u32 *array, int count) +{ + const u32 *cell; + int len, elems; + int i; + + debug("%s: %s\n", __func__, prop_name); + cell = fdt_getprop(blob, node, prop_name, &len); + if (!cell) + return -FDT_ERR_NOTFOUND; + elems = len / sizeof(u32); + if (count > elems) + count = elems; + for (i = 0; i < count; i++) + array[i] = fdt32_to_cpu(cell[i]); + + return count; +} + const u32 *fdtdec_locate_array(const void *blob, int node, const char *prop_name, int count) { @@ -669,20 +679,25 @@ char *fdtdec_get_config_string(const void *blob, const char *prop_name) return (char *)nodep; } -int fdtdec_decode_region(const void *blob, int node, - const char *prop_name, void **ptrp, size_t *size) +int fdtdec_decode_region(const void *blob, int node, const char *prop_name, + fdt_addr_t *basep, fdt_size_t *sizep) { const fdt_addr_t *cell; int len; - debug("%s: %s\n", __func__, prop_name); + debug("%s: %s: %s\n", __func__, fdt_get_name(blob, node, NULL), + prop_name); cell = fdt_getprop(blob, node, prop_name, &len); - if (!cell || (len != sizeof(fdt_addr_t) * 2)) + if (!cell || (len < sizeof(fdt_addr_t) * 2)) { + debug("cell=%p, len=%d\n", cell, len); return -1; + } + + *basep = fdt_addr_to_cpu(*cell); + *sizep = fdt_size_to_cpu(cell[1]); + debug("%s: base=%08lx, size=%lx\n", __func__, (ulong)*basep, + (ulong)*sizep); - *ptrp = map_sysmem(fdt_addr_to_cpu(*cell), *size); - *size = fdt_size_to_cpu(cell[1]); - debug("%s: size=%zx\n", __func__, *size); return 0; } @@ -698,6 +713,7 @@ int fdtdec_decode_region(const void *blob, int node, int fdtdec_read_fmap_entry(const void *blob, int node, const char *name, struct fmap_entry *entry) { + const char *prop; u32 reg[2]; if (fdtdec_get_int_array(blob, node, "reg", reg, 2)) { @@ -706,6 +722,13 @@ int fdtdec_read_fmap_entry(const void *blob, int node, const char *name, } entry->offset = reg[0]; entry->length = reg[1]; + entry->used = fdtdec_get_int(blob, node, "used", entry->length); + prop = fdt_getprop(blob, node, "compress", NULL); + entry->compress_algo = prop && !strcmp(prop, "lzo") ? + FMAP_COMPRESS_LZO : FMAP_COMPRESS_NONE; + prop = fdt_getprop(blob, node, "hash", &entry->hash_size); + entry->hash_algo = prop ? FMAP_HASH_SHA256 : FMAP_HASH_NONE; + entry->hash = (uint8_t *)prop; return 0; } @@ -780,4 +803,65 @@ int fdtdec_pci_get_bdf(const void *fdt, int node, int *bdf) return 0; } + +int fdtdec_decode_memory_region(const void *blob, int config_node, + const char *mem_type, const char *suffix, + fdt_addr_t *basep, fdt_size_t *sizep) +{ + char prop_name[50]; + const char *mem; + fdt_size_t size, offset_size; + fdt_addr_t base, offset; + int node; + + if (config_node == -1) { + config_node = fdt_path_offset(blob, "/config"); + if (config_node < 0) { + debug("%s: Cannot find /config node\n", __func__); + return -ENOENT; + } + } + if (!suffix) + suffix = ""; + + snprintf(prop_name, sizeof(prop_name), "%s-memory%s", mem_type, + suffix); + mem = fdt_getprop(blob, config_node, prop_name, NULL); + if (!mem) { + debug("%s: No memory type for '%s', using /memory\n", __func__, + prop_name); + mem = "/memory"; + } + + node = fdt_path_offset(blob, mem); + if (node < 0) { + debug("%s: Failed to find node '%s': %s\n", __func__, mem, + fdt_strerror(node)); + return -ENOENT; + } + + /* + * Not strictly correct - the memory may have multiple banks. We just + * use the first + */ + if (fdtdec_decode_region(blob, node, "reg", &base, &size)) { + debug("%s: Failed to decode memory region %s\n", __func__, + mem); + return -EINVAL; + } + + snprintf(prop_name, sizeof(prop_name), "%s-offset%s", mem_type, + suffix); + if (fdtdec_decode_region(blob, config_node, prop_name, &offset, + &offset_size)) { + debug("%s: Failed to decode memory region '%s'\n", __func__, + prop_name); + return -EINVAL; + } + + *basep = base + offset; + *sizep = offset_size; + + return 0; +} #endif diff --git a/lib/libfdt/Makefile b/lib/libfdt/Makefile index 6fe79e0..2f5413f 100644 --- a/lib/libfdt/Makefile +++ b/lib/libfdt/Makefile @@ -5,8 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -COBJS-libfdt += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o \ +obj-y += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o \ fdt_empty_tree.o fdt_addresses.o - -obj-$(CONFIG_OF_LIBFDT) += $(COBJS-libfdt) -obj-$(CONFIG_FIT) += $(COBJS-libfdt) diff --git a/lib/strmhz.c b/lib/strmhz.c index f9a1772..5c16cc4 100644 --- a/lib/strmhz.c +++ b/lib/strmhz.c @@ -11,11 +11,11 @@ char *strmhz (char *buf, unsigned long hz) long l, n; long m; - n = DIV_ROUND(hz, 1000) / 1000L; + n = DIV_ROUND_CLOSEST(hz, 1000) / 1000L; l = sprintf (buf, "%ld", n); hz -= n * 1000000L; - m = DIV_ROUND(hz, 1000L); + m = DIV_ROUND_CLOSEST(hz, 1000L); if (m != 0) sprintf (buf + l, ".%03ld", m); return (buf); diff --git a/lib/vsprintf.c b/lib/vsprintf.c index b585713..e0f2648 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -25,9 +25,6 @@ #include <div64.h> #define noinline __attribute__((noinline)) -/* some reluctance to put this into a new limits.h, so it is here */ -#define INT_MAX ((int)(~0U>>1)) - unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base) { @@ -518,6 +515,8 @@ static char *ip4_addr_string(char *buf, char *end, u8 *addr, int field_width, static char *pointer(const char *fmt, char *buf, char *end, void *ptr, int field_width, int precision, int flags) { + u64 num = (uintptr_t)ptr; + /* * Being a boot loader, we explicitly allow pointers to * (physical) address null. @@ -530,6 +529,17 @@ static char *pointer(const char *fmt, char *buf, char *end, void *ptr, #ifdef CONFIG_CMD_NET switch (*fmt) { + case 'a': + flags |= SPECIAL | ZEROPAD; + + switch (fmt[1]) { + case 'p': + default: + field_width = sizeof(phys_addr_t) * 2 + 2; + num = *(phys_addr_t *)ptr; + break; + } + break; case 'm': flags |= SPECIAL; /* Fallthrough */ @@ -555,8 +565,7 @@ static char *pointer(const char *fmt, char *buf, char *end, void *ptr, field_width = 2*sizeof(void *); flags |= ZEROPAD; } - return number(buf, end, (unsigned long)ptr, 16, field_width, - precision, flags); + return number(buf, end, num, 16, field_width, precision, flags); } static int vsnprintf_internal(char *buf, size_t size, const char *fmt, diff --git a/lib/zlib/zlib.h b/lib/zlib/zlib.h index 556be32..af3703e 100644 --- a/lib/zlib/zlib.h +++ b/lib/zlib/zlib.h @@ -3,7 +3,7 @@ #define __GLUE_ZLIB_H__ #include <common.h> -#include <compiler.h> +#include <linux/compiler.h> #include <asm/unaligned.h> #include <watchdog.h> #include "u-boot/zlib.h" diff --git a/net/bootp.c b/net/bootp.c index d4c86cf..8106601 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -145,8 +145,6 @@ static void BootpCopyNetParams(struct Bootp_t *bp) if (tmp_ip != 0) NetCopyIP(&NetServerIP, &bp->bp_siaddr); memcpy(NetServerEther, ((struct ethernet_hdr *)NetRxPacket)->et_src, 6); -#endif - NetCopyIP(&NetOurIP, &bp->bp_yiaddr); if (strlen(bp->bp_file) > 0) copy_filename(BootFile, bp->bp_file, sizeof(BootFile)); @@ -158,6 +156,8 @@ static void BootpCopyNetParams(struct Bootp_t *bp) */ if (*BootFile) setenv("bootfile", BootFile); +#endif + NetCopyIP(&NetOurIP, &bp->bp_yiaddr); } static int truncate_sz(const char *name, int maxlen, int curlen) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 9d1383a..13af604 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -260,11 +260,13 @@ quiet_cmd_dt_S_dtb= DTB $@ cmd_dt_S_dtb= \ ( \ echo '.section .dtb.init.rodata,"a"'; \ + echo '.balign 16'; \ echo '.global __dtb_$(*F)_begin'; \ echo '__dtb_$(*F)_begin:'; \ echo '.incbin "$<" '; \ echo '__dtb_$(*F)_end:'; \ echo '.global __dtb_$(*F)_end'; \ + echo '.balign 16'; \ ) > $@ $(obj)/%.dtb.S: $(obj)/%.dtb diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 7afe437..ecf3037 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -34,6 +34,7 @@ SPL_BIN := u-boot-spl endif include $(srctree)/config.mk +include $(srctree)/arch/$(ARCH)/Makefile # Enable garbage collection of un-used sections for SPL KBUILD_CFLAGS += -ffunction-sections -fdata-sections @@ -45,30 +46,13 @@ cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \ HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n) -ifdef CONFIG_SPL_START_S_PATH -START_PATH := $(CONFIG_SPL_START_S_PATH:"%"=%) -else -START_PATH := $(CPUDIR) -endif - -head-y := $(START_PATH)/start.o -head-$(CONFIG_X86) += $(START_PATH)/start16.o $(START_PATH)/resetvec.o -head-$(CONFIG_4xx) += $(START_PATH)/resetvec.o -head-$(CONFIG_MPC85xx) += $(START_PATH)/resetvec.o - -libs-y += arch/$(ARCH)/lib/ - -libs-y += $(CPUDIR)/ - -ifdef SOC -libs-y += $(CPUDIR)/$(SOC)/ -endif libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/) libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ libs-$(CONFIG_SPL_FRAMEWORK) += common/spl/ libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/ libs-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/ +libs-$(CONFIG_SPL_DM) += drivers/core/ libs-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/ libs-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/ libs-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/ @@ -80,7 +64,7 @@ libs-y += fs/ libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/ libs-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ drivers/power/pmic/ libs-$(CONFIG_SPL_MTD_SUPPORT) += drivers/mtd/ -libs-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/ +libs-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/ libs-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/ libs-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/ libs-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/ @@ -96,13 +80,6 @@ libs-$(CONFIG_SPL_USB_HOST_SUPPORT) += drivers/usb/host/ libs-$(CONFIG_OMAP_USB_PHY) += drivers/usb/phy/ libs-$(CONFIG_SPL_SATA_SUPPORT) += drivers/block/ -ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) -libs-y += arch/$(ARCH)/imx-common/ -endif - -libs-$(CONFIG_ARM) += arch/arm/cpu/ -libs-$(CONFIG_PPC) += arch/powerpc/cpu/ - head-y := $(addprefix $(obj)/,$(head-y)) libs-y := $(addprefix $(obj)/,$(libs-y)) u-boot-spl-dirs := $(patsubst %/,%,$(filter %/, $(libs-y))) @@ -181,6 +158,10 @@ ALL-y += $(obj)/sunxi-spl.bin endif endif +ifeq ($(CONFIG_SYS_SOC),"at91") +ALL-y += boot.bin +endif + all: $(ALL-y) ifdef CONFIG_SAMSUNG diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.pl index 7717d68..368a20e 100755 --- a/scripts/get_maintainer.pl +++ b/scripts/get_maintainer.pl @@ -835,8 +835,7 @@ sub top_of_kernel_tree { if ($lk_path ne "" && substr($lk_path,length($lk_path)-1,1) ne "/") { $lk_path .= "/"; } - if ( (-f "${lk_path}CREDITS") - && (-f "${lk_path}Kbuild") + if ( (-f "${lk_path}Kbuild") && (-f "${lk_path}MAINTAINERS") && (-f "${lk_path}Makefile") && (-f "${lk_path}README") diff --git a/scripts/kconfig/menu.c b/scripts/kconfig/menu.c index a26cc5d..72c9dba 100644 --- a/scripts/kconfig/menu.c +++ b/scripts/kconfig/menu.c @@ -548,7 +548,7 @@ static void get_prompt_str(struct gstr *r, struct property *prop, { int i, j; struct menu *submenu[8], *menu, *location = NULL; - struct jump_key *jump; + struct jump_key *jump = NULL; str_printf(r, _("Prompt: %s\n"), _(prop->text)); menu = prop->menu->parent; @@ -586,7 +586,7 @@ static void get_prompt_str(struct gstr *r, struct property *prop, str_printf(r, _(" Location:\n")); for (j = 4; --i >= 0; j += 2) { menu = submenu[i]; - if (head && location && menu == location) + if (jump && menu == location) jump->offset = strlen(r->s); str_printf(r, "%*c-> %s", j, ' ', _(menu_get_prompt(menu))); diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh new file mode 100755 index 0000000..a4fb055 --- /dev/null +++ b/test/fs/fs-test.sh @@ -0,0 +1,561 @@ +#!/bin/bash +# +# (C) Copyright 2014 Suriyan Ramasami +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# Invoke this test script from U-Boot base directory as ./test/fs/fs-test.sh +# It currently tests the fs/sb and native commands for ext4 and fat partitions +# Expected results are as follows: +# EXT4 tests: +# fs-test.sb.ext4.out: Summary: PASS: 17 FAIL: 2 +# fs-test.ext4.out: Summary: PASS: 11 FAIL: 8 +# fs-test.fs.ext4.out: Summary: PASS: 11 FAIL: 8 +# FAT tests: +# fs-test.sb.fat.out: Summary: PASS: 17 FAIL: 2 +# fs-test.fat.out: Summary: PASS: 19 FAIL: 0 +# fs-test.fs.fat.out: Summary: PASS: 19 FAIL: 0 +# Total Summary: TOTAL PASS: 94 TOTAL FAIL: 20 + +# pre-requisite binaries list. +PREREQ_BINS="md5sum mkfs mount umount dd fallocate mkdir" + +# All generated output files from this test will be in $OUT_DIR +# Hence everything is sandboxed. +OUT_DIR="sandbox/test/fs" + +# Location of generated sandbox u-boot +UBOOT="./sandbox/u-boot" + +# Our mount directory will be in the sandbox +MOUNT_DIR="${OUT_DIR}/mnt" + +# The file system image we create will have the $IMG prefix. +IMG="${OUT_DIR}/3GB" + +# $SMALL_FILE is the name of the 1MB file in the file system image +SMALL_FILE="1MB.file" + +# $BIG_FILE is the name of the 2.5GB file in the file system image +BIG_FILE="2.5GB.file" + +# $MD5_FILE will have the expected md5s when we do the test +# They shall have a suffix which represents their file system (ext4/fat) +MD5_FILE="${OUT_DIR}/md5s.list" + +# $OUT shall be the prefix of the test output. Their suffix will be .out +OUT="${OUT_DIR}/fs-test" + +# Full Path of the 1 MB file that shall be created in the fs image. +MB1="${MOUNT_DIR}/${SMALL_FILE}" +GB2p5="${MOUNT_DIR}/${BIG_FILE}" + +# ************************ +# * Functions start here * +# ************************ + +# Check if the prereq binaries exist, or exit +function check_prereq() { + for prereq in $PREREQ_BINS; do + if [ ! -x `which $prereq` ]; then + echo "Missing $prereq binary. Exiting!" + exit + fi + done + + # We use /dev/urandom to create files. Check if it exists. + if [ ! -c /dev/urandom ]; then + echo "Missing character special /dev/urandom. Exiting!" + exit + fi +} + +# If 1st param is "clean", then clean out the generated files and exit +function check_clean() { + if [ "$1" = "clean" ]; then + rm -rf "$OUT_DIR" + echo "Cleaned up generated files. Exiting" + exit + fi +} + +# Generate sandbox U-Boot - gleaned from /test/dm/test-dm.sh +function compile_sandbox() { + unset CROSS_COMPILE + NUM_CPUS=$(cat /proc/cpuinfo |grep -c processor) + make O=sandbox sandbox_config + make O=sandbox -s -j${NUM_CPUS} + + # Check if U-Boot exists + if [ ! -x "$UBOOT" ]; then + echo "$UBOOT does not exist or is not executable" + echo "Build error?" + echo "Please run this script as ./test/fs/`basename $0`" + exit + fi +} + +# Clean out all generated files other than the file system images +# We save time by not deleting and recreating the file system images +function prepare_env() { + rm -f ${MD5_FILE}.* ${OUT}.* + mkdir ${OUT_DIR} +} + +# 1st parameter is the name of the image file to be created +# 2nd parameter is the filesystem - fat ext4 etc +# -F cant be used with fat as it means something else. +function create_image() { + # Create image if not already present - saves time, while debugging + if [ "$2" = "ext4" ]; then + MKFS_OPTION="-F" + else + MKFS_OPTION="" + fi + if [ ! -f "$1" ]; then + fallocate -l 3G "$1" &> /dev/null + mkfs -t "$2" $MKFS_OPTION "$1" &> /dev/null + if [ $? -ne 0 -a "$2" = "fat" ]; then + # If we fail and we did fat, try vfat. + mkfs -t vfat $MKFS_OPTION "$1" &> /dev/null + fi + fi +} + +# 1st parameter is the FS type: fat/ext4 +# 2nd parameter is the name of small file +# Returns filename which can be used for fat or ext4 for writing +function fname_for_write() { + case $1 in + ext4) + # ext4 needs absolute path name of file + echo /${2}.w + ;; + + *) + echo ${2}.w + ;; + esac +} + +# 1st parameter is image file +# 2nd parameter is file system type - fat/ext4 +# 3rd parameter is name of small file +# 4th parameter is name of big file +# 5th parameter is fs/nonfs/sb - to dictate generic fs commands or +# otherwise or sb hostfs +# 6th parameter is the directory path for the files. Its "" for generic +# fs and ext4/fat and full patch for sb hostfs +# UBOOT is set in env +function test_image() { + addr="0x01000008" + length="0x00100000" + + case "$2" in + fat) + PREFIX="fat" + WRITE="write" + ;; + + ext4) + PREFIX="ext4" + WRITE="write" + ;; + + *) + echo "Unhandled filesystem $2. Exiting!" + exit + ;; + esac + + case "$5" in + fs) + PREFIX="" + WRITE="save" + SUFFIX=" 0:0" + ;; + + nonfs) + SUFFIX=" 0:0" + ;; + + sb) + PREFIX="sb " + WRITE="save" + SUFFIX="fs -" + ;; + + *) + echo "Unhandled mode $5. Exiting!" + exit + ;; + + esac + + if [ -z "$6" ]; then + FILE_WRITE=`fname_for_write $2 $3` + FILE_SMALL=$3 + FILE_BIG=$4 + else + FILE_WRITE=$6/`fname_for_write $2 $3` + FILE_SMALL=$6/$3 + FILE_BIG=$6/$4 + fi + + # In u-boot commands, <interface> stands for host or hostfs + # hostfs maps to the host fs. + # host maps to the "sb bind" that we do + + $UBOOT << EOF +sb=$5 +setenv bind 'if test "\$sb" != sb; then sb bind 0 "$1"; fi' +run bind +# Test Case 1 - ls +${PREFIX}ls host${SUFFIX} $6 +# +# We want ${PREFIX}size host 0:0 $3 for host commands and +# sb size hostfs - $3 for hostfs commands. +# 1MB is 0x0010 0000 +# Test Case 2 - size of small file +${PREFIX}size host${SUFFIX} $FILE_SMALL +printenv filesize +setenv filesize + +# 2.5GB (1024*1024*2500) is 0x9C40 0000 +# Test Case 3 - size of big file +${PREFIX}size host${SUFFIX} $FILE_BIG +printenv filesize +setenv filesize + +# Notes about load operation +# If I use 0x01000000 I get DMA misaligned error message +# Last two parameters are size and offset. + +# Test Case 4a - Read full 1MB of small file +${PREFIX}load host${SUFFIX} $addr $FILE_SMALL +printenv filesize +# Test Case 4b - Read full 1MB of small file +md5sum $addr \$filesize +setenv filesize + +# Test Case 5a - First 1MB of big file +${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x0 +printenv filesize +# Test Case 5b - First 1MB of big file +md5sum $addr \$filesize +setenv filesize + +# fails for ext as no offset support +# Test Case 6a - Last 1MB of big file +${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x9C300000 +printenv filesize +# Test Case 6b - Last 1MB of big file +md5sum $addr \$filesize +setenv filesize + +# fails for ext as no offset support +# Test Case 7a - One from the last 1MB chunk of 2GB +${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x7FF00000 +printenv filesize +# Test Case 7b - One from the last 1MB chunk of 2GB +md5sum $addr \$filesize +setenv filesize + +# fails for ext as no offset support +# Test Case 8a - One from the start 1MB chunk from 2GB +${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x80000000 +printenv filesize +# Test Case 8b - One from the start 1MB chunk from 2GB +md5sum $addr \$filesize +setenv filesize + +# fails for ext as no offset support +# Test Case 9a - One 1MB chunk crossing the 2GB boundary +${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x7FF80000 +printenv filesize +# Test Case 9b - One 1MB chunk crossing the 2GB boundary +md5sum $addr \$filesize +setenv filesize + +# Generic failure case +# Test Case 10 - 2MB chunk from the last 1MB of big file +${PREFIX}load host${SUFFIX} $addr $FILE_BIG 0x00200000 0x9C300000 +printenv filesize +# + +# Read 1MB from small file +${PREFIX}load host${SUFFIX} $addr $FILE_SMALL +# Write it back to test the writes +# Test Case 11a - Check that the write succeeded +${PREFIX}${WRITE} host${SUFFIX} $addr $FILE_WRITE \$filesize +mw.b $addr 00 100 +${PREFIX}load host${SUFFIX} $addr $FILE_WRITE +# Test Case 11b - Check md5 of written to is same as the one read from +md5sum $addr \$filesize +setenv filesize +# +reset + +EOF +} + +# 1st argument is the name of the image file. +# 2nd argument is the file where we generate the md5s of the files +# generated with the appropriate start and length that we use to test. +# It creates the necessary files in the image to test. +# $GB2p5 is the path of the big file (2.5 GB) +# $MB1 is the path of the small file (1 MB) +# $MOUNT_DIR is the path we can use to mount the image file. +function create_files() { + # Mount the image so we can populate it. + mkdir -p "$MOUNT_DIR" + sudo mount -o loop,rw "$1" "$MOUNT_DIR" + + # Create big file in this image. + # Note that we work only on the start 1MB, couple MBs in the 2GB range + # and the last 1 MB of the huge 2.5GB file. + # So, just put random values only in those areas. + if [ ! -f "${GB2p5}" ]; then + sudo dd if=/dev/urandom of="${GB2p5}" bs=1M count=1 \ + &> /dev/null + sudo dd if=/dev/urandom of="${GB2p5}" bs=1M count=2 seek=2047 \ + &> /dev/null + sudo dd if=/dev/urandom of="${GB2p5}" bs=1M count=1 seek=2499 \ + &> /dev/null + fi + + # Create a small file in this image. + if [ ! -f "${MB1}" ]; then + sudo dd if=/dev/urandom of="${MB1}" bs=1M count=1 \ + &> /dev/null + fi + + # Delete the small file which possibly is written as part of a + # previous test. + sudo rm -f "${MB1}.w" + + # Generate the md5sums of reads that we will test against small file + dd if="${MB1}" bs=1M skip=0 count=1 2> /dev/null | md5sum > "$2" + + # Generate the md5sums of reads that we will test against big file + # One from beginning of file. + dd if="${GB2p5}" bs=1M skip=0 count=1 \ + 2> /dev/null | md5sum >> "$2" + + # One from end of file. + dd if="${GB2p5}" bs=1M skip=2499 count=1 \ + 2> /dev/null | md5sum >> "$2" + + # One from the last 1MB chunk of 2GB + dd if="${GB2p5}" bs=1M skip=2047 count=1 \ + 2> /dev/null | md5sum >> "$2" + + # One from the start 1MB chunk from 2GB + dd if="${GB2p5}" bs=1M skip=2048 count=1 \ + 2> /dev/null | md5sum >> "$2" + + # One 1MB chunk crossing the 2GB boundary + dd if="${GB2p5}" bs=512K skip=4095 count=2 \ + 2> /dev/null | md5sum >> "$2" + + sync + sudo umount "$MOUNT_DIR" + rmdir "$MOUNT_DIR" +} + +# 1st parameter is the text to print +# if $? is 0 its a pass, else a fail +# As a side effect it shall update env variable PASS and FAIL +function pass_fail() { + if [ $? -eq 0 ]; then + echo pass - "$1" + PASS=$((PASS + 1)) + else + echo FAIL - "$1" + FAIL=$((FAIL + 1)) + fi +} + +# 1st parameter is the string which leads to an md5 generation +# 2nd parameter is the file we grep, for that string +# 3rd parameter is the name of the file which has md5s in it +# 4th parameter is the line # in the md5 file that we match it against +# This function checks if the md5 of the file in the sandbox matches +# that calculated while generating the file +# 5th parameter is the string to print with the result +check_md5() { + # md5sum in u-boot has output of form: + # md5 for 01000008 ... 01100007 ==> <md5> + # the 7th field is the actual md5 + md5_src=`grep -A3 "$1" "$2" | grep "md5 for"` + md5_src=($md5_src) + md5_src=${md5_src[6]} + + # The md5 list, each line is of the form: + # - <md5> + # the 2nd field is the actual md5 + md5_dst=`sed -n $4p $3` + md5_dst=($md5_dst) + md5_dst=${md5_dst[0]} + + # For a pass they should match. + [ "$md5_src" = "$md5_dst" ] + pass_fail "$5" +} + +# 1st parameter is the name of the output file to check +# 2nd parameter is the name of the file containing the md5 expected +# 3rd parameter is the name of the small file +# 4th parameter is the name of the big file +# 5th paramter is the name of the written file +# This function checks the output file for correct results. +function check_results() { + echo "** Start $1" + + PASS=0 + FAIL=0 + + # Check if the ls is showing correct results for 2.5 gb file + grep -A6 "Test Case 1 " "$1" | egrep -iq "2621440000 *$4" + pass_fail "TC1: ls of $4" + + # Check if the ls is showing correct results for 1 mb file + grep -A6 "Test Case 1 " "$1" | egrep -iq "1048576 *$3" + pass_fail "TC1: ls of $3" + + # Check size command on 1MB.file + egrep -A3 "Test Case 2 " "$1" | grep -q "filesize=100000" + pass_fail "TC2: size of $3" + + # Check size command on 2.5GB.file + egrep -A3 "Test Case 3 " "$1" | grep -q "filesize=9c400000" + pass_fail "TC3: size of $4" + + # Check read full mb of 1MB.file + grep -A6 "Test Case 4a " "$1" | grep -q "filesize=100000" + pass_fail "TC4: load of $3 size" + check_md5 "Test Case 4b " "$1" "$2" 1 "TC4: load from $3" + + # Check first mb of 2.5GB.file + grep -A6 "Test Case 5a " "$1" | grep -q "filesize=100000" + pass_fail "TC5: load of 1st MB from $4 size" + check_md5 "Test Case 5b " "$1" "$2" 2 "TC5: load of 1st MB from $4" + + # Check last mb of 2.5GB.file + grep -A6 "Test Case 6a " "$1" | grep -q "filesize=100000" + pass_fail "TC6: load of last MB from $4 size" + check_md5 "Test Case 6b " "$1" "$2" 3 "TC6: load of last MB from $4" + + # Check last 1mb chunk of 2gb from 2.5GB file + grep -A6 "Test Case 7a " "$1" | grep -q "filesize=100000" + pass_fail "TC7: load of last 1mb chunk of 2GB from $4 size" + check_md5 "Test Case 7b " "$1" "$2" 4 \ + "TC7: load of last 1mb chunk of 2GB from $4" + + # Check first 1mb chunk after 2gb from 2.5GB file + grep -A6 "Test Case 8a " "$1" | grep -q "filesize=100000" + pass_fail "TC8: load 1st MB chunk after 2GB from $4 size" + check_md5 "Test Case 8b " "$1" "$2" 5 \ + "TC8: load 1st MB chunk after 2GB from $4" + + # Check 1mb chunk crossing the 2gb boundary from 2.5GB file + grep -A6 "Test Case 9a " "$1" | grep -q "filesize=100000" + pass_fail "TC9: load 1MB chunk crossing 2GB boundary from $4 size" + check_md5 "Test Case 9b " "$1" "$2" 6 \ + "TC9: load 1MB chunk crossing 2GB boundary from $4" + + # Check 2mb chunk from the last 1MB of 2.5GB file - generic failure case + grep -A6 "Test Case 10 " "$1" | grep -q 'Error: "filesize" not defined' + pass_fail "TC10: load 2MB from the last 1MB of $4 - generic fail case" + + # Check 1mb chunk write + grep -A3 "Test Case 11a " "$1" | \ + egrep -q '1048576 bytes written|update journal' + pass_fail "TC11: 1MB write to $5 - write succeeded" + check_md5 "Test Case 11b " "$1" "$2" 1 \ + "TC11: 1MB write to $5 - content verified" + echo "** End $1" +} + +# Takes in one parameter which is "fs" or "nonfs", which then dictates +# if a fs test (size/load/save) or a nonfs test (fatread/extread) needs to +# be performed. +function test_fs_nonfs() { + echo "Creating files in $fs image if not already present." + create_files $IMAGE $MD5_FILE_FS + + OUT_FILE="${OUT}.fs.${fs}.out" + test_image $IMAGE $fs $SMALL_FILE $BIG_FILE $1 "" \ + > ${OUT_FILE} + check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE \ + $WRITE_FILE + TOTAL_FAIL=$((TOTAL_FAIL + FAIL)) + TOTAL_PASS=$((TOTAL_PASS + PASS)) + echo "Summary: PASS: $PASS FAIL: $FAIL" + echo "--------------------------------------------" +} + +# ******************** +# * End of functions * +# ******************** + +check_clean "$1" +check_prereq +compile_sandbox +prepare_env + +# Track TOTAL_FAIL and TOTAL_PASS +TOTAL_FAIL=0 +TOTAL_PASS=0 + +# In each loop, for a given file system image, we test both the +# fs command, like load/size/write, the file system specific command +# like: ext4load/ext4size/ext4write and the sb load/ls/save commands. +for fs in ext4 fat; do + + echo "Creating $fs image if not already present." + IMAGE=${IMG}.${fs}.img + MD5_FILE_FS="${MD5_FILE}.${fs}" + create_image $IMAGE $fs + + # sb commands test + echo "Creating files in $fs image if not already present." + create_files $IMAGE $MD5_FILE_FS + + # Lets mount the image and test sb hostfs commands + mkdir -p "$MOUNT_DIR" + if [ "$fs" = "fat" ]; then + uid="uid=`id -u`" + else + uid="" + fi + sudo mount -o loop,rw,$uid "$IMAGE" "$MOUNT_DIR" + sudo chmod 777 "$MOUNT_DIR" + + OUT_FILE="${OUT}.sb.${fs}.out" + test_image $IMAGE $fs $SMALL_FILE $BIG_FILE sb `pwd`/$MOUNT_DIR \ + > ${OUT_FILE} + sudo umount "$MOUNT_DIR" + rmdir "$MOUNT_DIR" + + check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE \ + $WRITE_FILE + TOTAL_FAIL=$((TOTAL_FAIL + FAIL)) + TOTAL_PASS=$((TOTAL_PASS + PASS)) + echo "Summary: PASS: $PASS FAIL: $FAIL" + echo "--------------------------------------------" + + test_fs_nonfs nonfs + test_fs_nonfs fs +done + +echo "Total Summary: TOTAL PASS: $TOTAL_PASS TOTAL FAIL: $TOTAL_FAIL" +echo "--------------------------------------------" +if [ $TOTAL_FAIL -eq 0 ]; then + echo "PASSED" + exit 0 +else + echo "FAILED" + exit 1 +fi diff --git a/tools/.gitignore b/tools/.gitignore index e7f0f8f..9bc9fec 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -4,6 +4,7 @@ /fit_check_sign /fit_info /gen_eth_addr +/ifdtool /img2srec /kwboot /dumpimage diff --git a/tools/Makefile b/tools/Makefile index c422b76..a4216a1 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -126,6 +126,8 @@ hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl HOSTCFLAGS_mkexynosspl.o := -pedantic +hostprogs-$(CONFIG_X86) += ifdtool + hostprogs-$(CONFIG_MX23) += mxsboot hostprogs-$(CONFIG_MX28) += mxsboot HOSTCFLAGS_mxsboot.o := -pedantic diff --git a/tools/buildman/README b/tools/buildman/README index 8ba19ec..bfb2f18 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -85,10 +85,10 @@ branch. Put all your commits in a branch, set the branch's upstream to a valid value, and all will be well. Otherwise buildman will perform random actions. Use -n to check what the random actions might be. -If you just want to build the current source tree, leave off the -b flag. -This will display results and errors as they happen. You can still look -at them later using -s. Note that buildman will assume that the source -has changed, and will build all specified boards in this case. +If you just want to build the current source tree, leave off the -b flag +and add -e. This will display results and errors as they happen. You can +still look at them later using -se. Note that buildman will assume that the +source has changed, and will build all specified boards in this case. Buildman is optimised for building many commits at once, for many boards. On multi-core machines, Buildman is fast because it uses most of the @@ -693,9 +693,9 @@ Quick Sanity Check ================== If you have made changes and want to do a quick sanity check of the -currently-checked-out source, run buildman without the -b flag. This will -build the selected boards and display build status and errors as it runs -(i.e. -v amd -e are enabled automatically). +currently checked-out source, run buildman without the -b flag. This will +build the selected boards and display build status as it runs (i.e. -v is +enabled automatically). Use -e to see errors/warnings as well. Other options @@ -752,7 +752,7 @@ an error and green indicating that a commit fixed an error. Use the -e flag to see the full errors and -l to see which boards caused which errors. If you really want to see build results as they happen, use -v when doing a -build (-e will be enabled automatically). +build (and -e to see the errors/warnings too). You don't need to stick around on that branch while buildman is running. It checks out its own copy of the source code, so you can change branches, @@ -816,11 +816,10 @@ TODO This has mostly be written in my spare time as a response to my difficulties in testing large series of patches. Apart from tidying up there is quite a -bit of scope for improvement. Things like better error diffs, easier access -to log files, error display while building. Also it would be nice it buildman -could 'hunt' for problems, perhaps by building a few boards for each arch, -or checking commits for changed files and building only boards which use -those files. +bit of scope for improvement. Things like better error diffs and easier +access to log files. Also it would be nice it buildman could 'hunt' for +problems, perhaps by building a few boards for each arch, or checking +commits for changed files and building only boards which use those files. Credits diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index 8155c16..7002034 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -918,7 +918,8 @@ class Builder: if self._list_error_boards: names = [] for board in line_boards[line]: - names.append(board.target) + if not board.target in names: + names.append(board.target) names_str = '(%s) ' % ','.join(names) else: names_str = '' diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py index a9cf68a..bc4541c 100644 --- a/tools/buildman/builderthread.py +++ b/tools/buildman/builderthread.py @@ -332,7 +332,7 @@ class BuilderThread(threading.Thread): # Now write the actual build output if keep_outputs: - patterns = ['u-boot', '*.bin', 'u-boot.dtb', '*.map', + patterns = ['u-boot', '*.bin', 'u-boot.dtb', '*.map', '*.img', 'include/autoconf.mk', 'spl/u-boot-spl', 'spl/u-boot-spl.bin'] for pattern in patterns: diff --git a/tools/buildman/control.py b/tools/buildman/control.py index 8b8c826..2c3ba8b 100644 --- a/tools/buildman/control.py +++ b/tools/buildman/control.py @@ -70,7 +70,7 @@ def ShowActions(series, why_selected, boards_selected, builder, options): if commits: for upto in range(0, len(series.commits), options.step): commit = series.commits[upto] - print ' ', col.Color(col.YELLOW, commit.hash, bright=False), + print ' ', col.Color(col.YELLOW, commit.hash[:8], bright=False), print commit.subject print for arg in why_selected: @@ -188,7 +188,6 @@ def DoBuildman(options, args, toolchains=None, make_func=None, boards=None, else: series = None options.verbose = True - options.show_errors = True # By default we have one thread per CPU. But if there are not enough jobs # we can have fewer threads and use a high '-j' value for make. diff --git a/tools/ifdtool.c b/tools/ifdtool.c new file mode 100644 index 0000000..a4b481f --- /dev/null +++ b/tools/ifdtool.c @@ -0,0 +1,1039 @@ +/* + * ifdtool - Manage Intel Firmware Descriptor information + * + * Copyright 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + * + * From Coreboot project, but it got a serious code clean-up + * and a few new features + */ + +#include <assert.h> +#include <fcntl.h> +#include <getopt.h> +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <unistd.h> +#include <sys/types.h> +#include <sys/stat.h> +#include "ifdtool.h" + +#undef DEBUG + +#ifdef DEBUG +#define debug(fmt, args...) printf(fmt, ##args) +#else +#define debug(fmt, args...) +#endif + +#define FD_SIGNATURE 0x0FF0A55A +#define FLREG_BASE(reg) ((reg & 0x00000fff) << 12); +#define FLREG_LIMIT(reg) (((reg & 0x0fff0000) >> 4) | 0xfff); + +/** + * find_fd() - Find the flash description in the ROM image + * + * @image: Pointer to image + * @size: Size of image in bytes + * @return pointer to structure, or NULL if not found + */ +static struct fdbar_t *find_fd(char *image, int size) +{ + uint32_t *ptr, *end; + + /* Scan for FD signature */ + for (ptr = (uint32_t *)image, end = ptr + size / 4; ptr < end; ptr++) { + if (*ptr == FD_SIGNATURE) + break; + } + + if (ptr == end) { + printf("No Flash Descriptor found in this image\n"); + return NULL; + } + + debug("Found Flash Descriptor signature at 0x%08x\n", i); + + return (struct fdbar_t *)ptr; +} + +/** + * get_region() - Get information about the selected region + * + * @frba: Flash region list + * @region_type: Type of region (0..MAX_REGIONS-1) + * @region: Region information is written here + * @return 0 if OK, else -ve + */ +static int get_region(struct frba_t *frba, int region_type, + struct region_t *region) +{ + if (region_type >= MAX_REGIONS) { + fprintf(stderr, "Invalid region type.\n"); + return -1; + } + + region->base = FLREG_BASE(frba->flreg[region_type]); + region->limit = FLREG_LIMIT(frba->flreg[region_type]); + region->size = region->limit - region->base + 1; + + return 0; +} + +static const char *region_name(int region_type) +{ + static const char *const regions[] = { + "Flash Descriptor", + "BIOS", + "Intel ME", + "GbE", + "Platform Data" + }; + + assert(region_type < MAX_REGIONS); + + return regions[region_type]; +} + +static const char *region_filename(int region_type) +{ + static const char *const region_filenames[] = { + "flashregion_0_flashdescriptor.bin", + "flashregion_1_bios.bin", + "flashregion_2_intel_me.bin", + "flashregion_3_gbe.bin", + "flashregion_4_platform_data.bin" + }; + + assert(region_type < MAX_REGIONS); + + return region_filenames[region_type]; +} + +static int dump_region(int num, struct frba_t *frba) +{ + struct region_t region; + int ret; + + ret = get_region(frba, num, ®ion); + if (ret) + return ret; + + printf(" Flash Region %d (%s): %08x - %08x %s\n", + num, region_name(num), region.base, region.limit, + region.size < 1 ? "(unused)" : ""); + + return ret; +} + +static void dump_frba(struct frba_t *frba) +{ + int i; + + printf("Found Region Section\n"); + for (i = 0; i < MAX_REGIONS; i++) { + printf("FLREG%d: 0x%08x\n", i, frba->flreg[i]); + dump_region(i, frba); + } +} + +static void decode_spi_frequency(unsigned int freq) +{ + switch (freq) { + case SPI_FREQUENCY_20MHZ: + printf("20MHz"); + break; + case SPI_FREQUENCY_33MHZ: + printf("33MHz"); + break; + case SPI_FREQUENCY_50MHZ: + printf("50MHz"); + break; + default: + printf("unknown<%x>MHz", freq); + } +} + +static void decode_component_density(unsigned int density) +{ + switch (density) { + case COMPONENT_DENSITY_512KB: + printf("512KiB"); + break; + case COMPONENT_DENSITY_1MB: + printf("1MiB"); + break; + case COMPONENT_DENSITY_2MB: + printf("2MiB"); + break; + case COMPONENT_DENSITY_4MB: + printf("4MiB"); + break; + case COMPONENT_DENSITY_8MB: + printf("8MiB"); + break; + case COMPONENT_DENSITY_16MB: + printf("16MiB"); + break; + default: + printf("unknown<%x>MiB", density); + } +} + +static void dump_fcba(struct fcba_t *fcba) +{ + printf("\nFound Component Section\n"); + printf("FLCOMP 0x%08x\n", fcba->flcomp); + printf(" Dual Output Fast Read Support: %ssupported\n", + (fcba->flcomp & (1 << 30)) ? "" : "not "); + printf(" Read ID/Read Status Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 27) & 7); + printf("\n Write/Erase Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 24) & 7); + printf("\n Fast Read Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 21) & 7); + printf("\n Fast Read Support: %ssupported", + (fcba->flcomp & (1 << 20)) ? "" : "not "); + printf("\n Read Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 17) & 7); + printf("\n Component 2 Density: "); + decode_component_density((fcba->flcomp >> 3) & 7); + printf("\n Component 1 Density: "); + decode_component_density(fcba->flcomp & 7); + printf("\n"); + printf("FLILL 0x%08x\n", fcba->flill); + printf(" Invalid Instruction 3: 0x%02x\n", + (fcba->flill >> 24) & 0xff); + printf(" Invalid Instruction 2: 0x%02x\n", + (fcba->flill >> 16) & 0xff); + printf(" Invalid Instruction 1: 0x%02x\n", + (fcba->flill >> 8) & 0xff); + printf(" Invalid Instruction 0: 0x%02x\n", + fcba->flill & 0xff); + printf("FLPB 0x%08x\n", fcba->flpb); + printf(" Flash Partition Boundary Address: 0x%06x\n\n", + (fcba->flpb & 0xfff) << 12); +} + +static void dump_fpsba(struct fpsba_t *fpsba) +{ + int i; + + printf("Found PCH Strap Section\n"); + for (i = 0; i < MAX_STRAPS; i++) + printf("PCHSTRP%-2d: 0x%08x\n", i, fpsba->pchstrp[i]); +} + +static const char *get_enabled(int flag) +{ + return flag ? "enabled" : "disabled"; +} + +static void decode_flmstr(uint32_t flmstr) +{ + printf(" Platform Data Region Write Access: %s\n", + get_enabled(flmstr & (1 << 28))); + printf(" GbE Region Write Access: %s\n", + get_enabled(flmstr & (1 << 27))); + printf(" Intel ME Region Write Access: %s\n", + get_enabled(flmstr & (1 << 26))); + printf(" Host CPU/BIOS Region Write Access: %s\n", + get_enabled(flmstr & (1 << 25))); + printf(" Flash Descriptor Write Access: %s\n", + get_enabled(flmstr & (1 << 24))); + + printf(" Platform Data Region Read Access: %s\n", + get_enabled(flmstr & (1 << 20))); + printf(" GbE Region Read Access: %s\n", + get_enabled(flmstr & (1 << 19))); + printf(" Intel ME Region Read Access: %s\n", + get_enabled(flmstr & (1 << 18))); + printf(" Host CPU/BIOS Region Read Access: %s\n", + get_enabled(flmstr & (1 << 17))); + printf(" Flash Descriptor Read Access: %s\n", + get_enabled(flmstr & (1 << 16))); + + printf(" Requester ID: 0x%04x\n\n", + flmstr & 0xffff); +} + +static void dump_fmba(struct fmba_t *fmba) +{ + printf("Found Master Section\n"); + printf("FLMSTR1: 0x%08x (Host CPU/BIOS)\n", fmba->flmstr1); + decode_flmstr(fmba->flmstr1); + printf("FLMSTR2: 0x%08x (Intel ME)\n", fmba->flmstr2); + decode_flmstr(fmba->flmstr2); + printf("FLMSTR3: 0x%08x (GbE)\n", fmba->flmstr3); + decode_flmstr(fmba->flmstr3); +} + +static void dump_fmsba(struct fmsba_t *fmsba) +{ + int i; + + printf("Found Processor Strap Section\n"); + for (i = 0; i < 4; i++) + printf("????: 0x%08x\n", fmsba->data[0]); +} + +static void dump_jid(uint32_t jid) +{ + printf(" SPI Component Device ID 1: 0x%02x\n", + (jid >> 16) & 0xff); + printf(" SPI Component Device ID 0: 0x%02x\n", + (jid >> 8) & 0xff); + printf(" SPI Component Vendor ID: 0x%02x\n", + jid & 0xff); +} + +static void dump_vscc(uint32_t vscc) +{ + printf(" Lower Erase Opcode: 0x%02x\n", + vscc >> 24); + printf(" Lower Write Enable on Write Status: 0x%02x\n", + vscc & (1 << 20) ? 0x06 : 0x50); + printf(" Lower Write Status Required: %s\n", + vscc & (1 << 19) ? "Yes" : "No"); + printf(" Lower Write Granularity: %d bytes\n", + vscc & (1 << 18) ? 64 : 1); + printf(" Lower Block / Sector Erase Size: "); + switch ((vscc >> 16) & 0x3) { + case 0: + printf("256 Byte\n"); + break; + case 1: + printf("4KB\n"); + break; + case 2: + printf("8KB\n"); + break; + case 3: + printf("64KB\n"); + break; + } + + printf(" Upper Erase Opcode: 0x%02x\n", + (vscc >> 8) & 0xff); + printf(" Upper Write Enable on Write Status: 0x%02x\n", + vscc & (1 << 4) ? 0x06 : 0x50); + printf(" Upper Write Status Required: %s\n", + vscc & (1 << 3) ? "Yes" : "No"); + printf(" Upper Write Granularity: %d bytes\n", + vscc & (1 << 2) ? 64 : 1); + printf(" Upper Block / Sector Erase Size: "); + switch (vscc & 0x3) { + case 0: + printf("256 Byte\n"); + break; + case 1: + printf("4KB\n"); + break; + case 2: + printf("8KB\n"); + break; + case 3: + printf("64KB\n"); + break; + } +} + +static void dump_vtba(struct vtba_t *vtba, int vtl) +{ + int i; + int num = (vtl >> 1) < 8 ? (vtl >> 1) : 8; + + printf("ME VSCC table:\n"); + for (i = 0; i < num; i++) { + printf(" JID%d: 0x%08x\n", i, vtba->entry[i].jid); + dump_jid(vtba->entry[i].jid); + printf(" VSCC%d: 0x%08x\n", i, vtba->entry[i].vscc); + dump_vscc(vtba->entry[i].vscc); + } + printf("\n"); +} + +static void dump_oem(uint8_t *oem) +{ + int i, j; + printf("OEM Section:\n"); + for (i = 0; i < 4; i++) { + printf("%02x:", i << 4); + for (j = 0; j < 16; j++) + printf(" %02x", oem[(i<<4)+j]); + printf("\n"); + } + printf("\n"); +} + +/** + * dump_fd() - Display a dump of the full flash description + * + * @image: Pointer to image + * @size: Size of image in bytes + * @return 0 if OK, -1 on error + */ +static int dump_fd(char *image, int size) +{ + struct fdbar_t *fdb = find_fd(image, size); + + if (!fdb) + return -1; + + printf("FLMAP0: 0x%08x\n", fdb->flmap0); + printf(" NR: %d\n", (fdb->flmap0 >> 24) & 7); + printf(" FRBA: 0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4); + printf(" NC: %d\n", ((fdb->flmap0 >> 8) & 3) + 1); + printf(" FCBA: 0x%x\n", ((fdb->flmap0) & 0xff) << 4); + + printf("FLMAP1: 0x%08x\n", fdb->flmap1); + printf(" ISL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff); + printf(" FPSBA: 0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4); + printf(" NM: %d\n", (fdb->flmap1 >> 8) & 3); + printf(" FMBA: 0x%x\n", ((fdb->flmap1) & 0xff) << 4); + + printf("FLMAP2: 0x%08x\n", fdb->flmap2); + printf(" PSL: 0x%04x\n", (fdb->flmap2 >> 8) & 0xffff); + printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4); + + printf("FLUMAP1: 0x%08x\n", fdb->flumap1); + printf(" Intel ME VSCC Table Length (VTL): %d\n", + (fdb->flumap1 >> 8) & 0xff); + printf(" Intel ME VSCC Table Base Address (VTBA): 0x%06x\n\n", + (fdb->flumap1 & 0xff) << 4); + dump_vtba((struct vtba_t *) + (image + ((fdb->flumap1 & 0xff) << 4)), + (fdb->flumap1 >> 8) & 0xff); + dump_oem((uint8_t *)image + 0xf00); + dump_frba((struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff) + << 4))); + dump_fcba((struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4))); + dump_fpsba((struct fpsba_t *) + (image + (((fdb->flmap1 >> 16) & 0xff) << 4))); + dump_fmba((struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4))); + dump_fmsba((struct fmsba_t *)(image + (((fdb->flmap2) & 0xff) << 4))); + + return 0; +} + +/** + * write_regions() - Write each region from an image to its own file + * + * The filename to use in each case is fixed - see region_filename() + * + * @image: Pointer to image + * @size: Size of image in bytes + * @return 0 if OK, -ve on error + */ +static int write_regions(char *image, int size) +{ + struct fdbar_t *fdb; + struct frba_t *frba; + int ret = 0; + int i; + + fdb = find_fd(image, size); + if (!fdb) + return -1; + + frba = (struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff) << 4)); + + for (i = 0; i < MAX_REGIONS; i++) { + struct region_t region; + int region_fd; + + ret = get_region(frba, i, ®ion); + if (ret) + return ret; + dump_region(i, frba); + if (region.size == 0) + continue; + region_fd = open(region_filename(i), + O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR | + S_IWUSR | S_IRGRP | S_IROTH); + if (write(region_fd, image + region.base, region.size) != + region.size) { + perror("Error while writing"); + ret = -1; + } + close(region_fd); + } + + return ret; +} + +/** + * write_image() - Write the image to a file + * + * @filename: Filename to use for the image + * @image: Pointer to image + * @size: Size of image in bytes + * @return 0 if OK, -ve on error + */ +static int write_image(char *filename, char *image, int size) +{ + int new_fd; + + debug("Writing new image to %s\n", filename); + + new_fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR | + S_IWUSR | S_IRGRP | S_IROTH); + if (write(new_fd, image, size) != size) { + perror("Error while writing"); + return -1; + } + close(new_fd); + + return 0; +} + +/** + * set_spi_frequency() - Set the SPI frequency to use when booting + * + * Several frequencies are supported, some of which work with fast devices. + * For SPI emulators, the slowest (SPI_FREQUENCY_20MHZ) is often used. The + * Intel boot system uses this information somehow on boot. + * + * The image is updated with the supplied value + * + * @image: Pointer to image + * @size: Size of image in bytes + * @freq: SPI frequency to use + */ +static void set_spi_frequency(char *image, int size, enum spi_frequency freq) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct fcba_t *fcba; + + fcba = (struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4)); + + /* clear bits 21-29 */ + fcba->flcomp &= ~0x3fe00000; + /* Read ID and Read Status Clock Frequency */ + fcba->flcomp |= freq << 27; + /* Write and Erase Clock Frequency */ + fcba->flcomp |= freq << 24; + /* Fast Read Clock Frequency */ + fcba->flcomp |= freq << 21; +} + +/** + * set_em100_mode() - Set a SPI frequency that will work with Dediprog EM100 + * + * @image: Pointer to image + * @size: Size of image in bytes + */ +static void set_em100_mode(char *image, int size) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct fcba_t *fcba; + + fcba = (struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4)); + fcba->flcomp &= ~(1 << 30); + set_spi_frequency(image, size, SPI_FREQUENCY_20MHZ); +} + +/** + * lock_descriptor() - Lock the NE descriptor so it cannot be updated + * + * @image: Pointer to image + * @size: Size of image in bytes + */ +static void lock_descriptor(char *image, int size) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct fmba_t *fmba; + + /* + * TODO: Dynamically take Platform Data Region and GbE Region into + * account. + */ + fmba = (struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4)); + fmba->flmstr1 = 0x0a0b0000; + fmba->flmstr2 = 0x0c0d0000; + fmba->flmstr3 = 0x08080118; +} + +/** + * unlock_descriptor() - Lock the NE descriptor so it can be updated + * + * @image: Pointer to image + * @size: Size of image in bytes + */ +static void unlock_descriptor(char *image, int size) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct fmba_t *fmba; + + fmba = (struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4)); + fmba->flmstr1 = 0xffff0000; + fmba->flmstr2 = 0xffff0000; + fmba->flmstr3 = 0x08080118; +} + +/** + * open_for_read() - Open a file for reading + * + * @fname: Filename to open + * @sizep: Returns file size in bytes + * @return 0 if OK, -1 on error + */ +int open_for_read(const char *fname, int *sizep) +{ + int fd = open(fname, O_RDONLY); + struct stat buf; + + if (fd == -1) { + perror("Could not open file"); + return -1; + } + if (fstat(fd, &buf) == -1) { + perror("Could not stat file"); + return -1; + } + *sizep = buf.st_size; + debug("File %s is %d bytes\n", fname, *sizep); + + return fd; +} + +/** + * inject_region() - Add a file to an image region + * + * This puts a file into a particular region of the flash. Several pre-defined + * regions are used. + * + * @image: Pointer to image + * @size: Size of image in bytes + * @region_type: Region where the file should be added + * @region_fname: Filename to add to the image + * @return 0 if OK, -ve on error + */ +int inject_region(char *image, int size, int region_type, char *region_fname) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct region_t region; + struct frba_t *frba; + int region_size; + int offset = 0; + int region_fd; + int ret; + + if (!fdb) + exit(EXIT_FAILURE); + frba = (struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff) << 4)); + + ret = get_region(frba, region_type, ®ion); + if (ret) + return -1; + if (region.size <= 0xfff) { + fprintf(stderr, "Region %s is disabled in target. Not injecting.\n", + region_name(region_type)); + return -1; + } + + region_fd = open_for_read(region_fname, ®ion_size); + if (region_fd < 0) + return region_fd; + + if ((region_size > region.size) || + ((region_type != 1) && (region_size > region.size))) { + fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x) bytes. Not injecting.\n", + region_name(region_type), region.size, + region.size, region_size, region_size); + return -1; + } + + if ((region_type == 1) && (region_size < region.size)) { + fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x) bytes. Padding before injecting.\n", + region_name(region_type), region.size, + region.size, region_size, region_size); + offset = region.size - region_size; + memset(image + region.base, 0xff, offset); + } + + if (size < region.base + offset + region_size) { + fprintf(stderr, "Output file is too small. (%d < %d)\n", + size, region.base + offset + region_size); + return -1; + } + + if (read(region_fd, image + region.base + offset, region_size) + != region_size) { + perror("Could not read file"); + return -1; + } + + close(region_fd); + + debug("Adding %s as the %s section\n", region_fname, + region_name(region_type)); + + return 0; +} + +/** + * write_data() - Write some raw data into a region + * + * This puts a file into a particular place in the flash, ignoring the + * regions. Be careful not to overwrite something important. + * + * @image: Pointer to image + * @size: Size of image in bytes + * @addr: x86 ROM address to put file. The ROM ends at + * 0xffffffff so use an address relative to that. For an + * 8MB ROM the start address is 0xfff80000. + * @write_fname: Filename to add to the image + * @return 0 if OK, -ve on error + */ +static int write_data(char *image, int size, unsigned int addr, + const char *write_fname) +{ + int write_fd, write_size; + int offset; + + write_fd = open_for_read(write_fname, &write_size); + if (write_fd < 0) + return write_fd; + + offset = addr + size; + debug("Writing %s to offset %#x\n", write_fname, offset); + + if (offset < 0 || offset + write_size > size) { + fprintf(stderr, "Output file is too small. (%d < %d)\n", + size, offset + write_size); + return -1; + } + + if (read(write_fd, image + offset, write_size) != write_size) { + perror("Could not read file"); + return -1; + } + + close(write_fd); + + return 0; +} + +static void print_version(void) +{ + printf("ifdtool v%s -- ", IFDTOOL_VERSION); + printf("Copyright (C) 2014 Google Inc.\n\n"); + printf("SPDX-License-Identifier: GPL-2.0+\n"); +} + +static void print_usage(const char *name) +{ + printf("usage: %s [-vhdix?] <filename> [<outfile>]\n", name); + printf("\n" + " -d | --dump: dump intel firmware descriptor\n" + " -x | --extract: extract intel fd modules\n" + " -i | --inject <region>:<module> inject file <module> into region <region>\n" + " -w | --write <addr>:<file> write file to appear at memory address <addr>\n" + " -s | --spifreq <20|33|50> set the SPI frequency\n" + " -e | --em100 set SPI frequency to 20MHz and disable\n" + " Dual Output Fast Read Support\n" + " -l | --lock Lock firmware descriptor and ME region\n" + " -u | --unlock Unlock firmware descriptor and ME region\n" + " -r | --romsize Specify ROM size\n" + " -D | --write-descriptor <file> Write descriptor at base\n" + " -c | --create Create a new empty image\n" + " -v | --version: print the version\n" + " -h | --help: print this help\n\n" + "<region> is one of Descriptor, BIOS, ME, GbE, Platform\n" + "\n"); +} + +/** + * get_two_words() - Convert a string into two words separated by : + * + * The supplied string is split at ':', two substrings are allocated and + * returned. + * + * @str: String to split + * @firstp: Returns first string + * @secondp: Returns second string + * @return 0 if OK, -ve if @str does not have a : + */ +static int get_two_words(const char *str, char **firstp, char **secondp) +{ + const char *p; + + p = strchr(str, ':'); + if (!p) + return -1; + *firstp = strdup(str); + (*firstp)[p - str] = '\0'; + *secondp = strdup(p + 1); + + return 0; +} + +int main(int argc, char *argv[]) +{ + int opt, option_index = 0; + int mode_dump = 0, mode_extract = 0, mode_inject = 0; + int mode_spifreq = 0, mode_em100 = 0, mode_locked = 0; + int mode_unlocked = 0, mode_write = 0, mode_write_descriptor = 0; + int create = 0; + char *region_type_string = NULL, *src_fname = NULL; + char *addr_str = NULL; + int region_type = -1, inputfreq = 0; + enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ; + unsigned int addr = 0; + int rom_size = -1; + bool write_it; + char *filename; + char *outfile = NULL; + struct stat buf; + int size = 0; + int bios_fd; + char *image; + int ret; + static struct option long_options[] = { + {"create", 0, NULL, 'c'}, + {"dump", 0, NULL, 'd'}, + {"descriptor", 1, NULL, 'D'}, + {"em100", 0, NULL, 'e'}, + {"extract", 0, NULL, 'x'}, + {"inject", 1, NULL, 'i'}, + {"lock", 0, NULL, 'l'}, + {"romsize", 1, NULL, 'r'}, + {"spifreq", 1, NULL, 's'}, + {"unlock", 0, NULL, 'u'}, + {"write", 1, NULL, 'w'}, + {"version", 0, NULL, 'v'}, + {"help", 0, NULL, 'h'}, + {0, 0, 0, 0} + }; + + while ((opt = getopt_long(argc, argv, "cdD:ehi:lr:s:uvw:x?", + long_options, &option_index)) != EOF) { + switch (opt) { + case 'c': + create = 1; + break; + case 'd': + mode_dump = 1; + break; + case 'D': + mode_write_descriptor = 1; + src_fname = optarg; + break; + case 'e': + mode_em100 = 1; + break; + case 'i': + if (get_two_words(optarg, ®ion_type_string, + &src_fname)) { + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + if (!strcasecmp("Descriptor", region_type_string)) + region_type = 0; + else if (!strcasecmp("BIOS", region_type_string)) + region_type = 1; + else if (!strcasecmp("ME", region_type_string)) + region_type = 2; + else if (!strcasecmp("GbE", region_type_string)) + region_type = 3; + else if (!strcasecmp("Platform", region_type_string)) + region_type = 4; + if (region_type == -1) { + fprintf(stderr, "No such region type: '%s'\n\n", + region_type_string); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + mode_inject = 1; + break; + case 'l': + mode_locked = 1; + break; + case 'r': + rom_size = strtol(optarg, NULL, 0); + debug("ROM size %d\n", rom_size); + break; + case 's': + /* Parse the requested SPI frequency */ + inputfreq = strtol(optarg, NULL, 0); + switch (inputfreq) { + case 20: + spifreq = SPI_FREQUENCY_20MHZ; + break; + case 33: + spifreq = SPI_FREQUENCY_33MHZ; + break; + case 50: + spifreq = SPI_FREQUENCY_50MHZ; + break; + default: + fprintf(stderr, "Invalid SPI Frequency: %d\n", + inputfreq); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + mode_spifreq = 1; + break; + case 'u': + mode_unlocked = 1; + break; + case 'v': + print_version(); + exit(EXIT_SUCCESS); + break; + case 'w': + mode_write = 1; + if (get_two_words(optarg, &addr_str, &src_fname)) { + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + addr = strtol(optarg, NULL, 0); + break; + case 'x': + mode_extract = 1; + break; + case 'h': + case '?': + default: + print_usage(argv[0]); + exit(EXIT_SUCCESS); + break; + } + } + + if (mode_locked == 1 && mode_unlocked == 1) { + fprintf(stderr, "Locking/Unlocking FD and ME are mutually exclusive\n"); + exit(EXIT_FAILURE); + } + + if (mode_inject == 1 && mode_write == 1) { + fprintf(stderr, "Inject/Write are mutually exclusive\n"); + exit(EXIT_FAILURE); + } + + if ((mode_dump + mode_extract + mode_inject + + (mode_spifreq | mode_em100 | mode_unlocked | + mode_locked)) > 1) { + fprintf(stderr, "You may not specify more than one mode.\n\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + + if ((mode_dump + mode_extract + mode_inject + mode_spifreq + + mode_em100 + mode_locked + mode_unlocked + mode_write + + mode_write_descriptor) == 0 && !create) { + fprintf(stderr, "You need to specify a mode.\n\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + + if (create && rom_size == -1) { + fprintf(stderr, "You need to specify a rom size when creating.\n\n"); + exit(EXIT_FAILURE); + } + + if (optind + 1 != argc) { + fprintf(stderr, "You need to specify a file.\n\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + + filename = argv[optind]; + if (optind + 2 != argc) + outfile = argv[optind + 1]; + + if (create) + bios_fd = open(filename, O_WRONLY | O_CREAT, 0666); + else + bios_fd = open(filename, outfile ? O_RDONLY : O_RDWR); + + if (bios_fd == -1) { + perror("Could not open file"); + exit(EXIT_FAILURE); + } + + if (!create) { + if (fstat(bios_fd, &buf) == -1) { + perror("Could not stat file"); + exit(EXIT_FAILURE); + } + size = buf.st_size; + } + + debug("File %s is %d bytes\n", filename, size); + + if (rom_size == -1) + rom_size = size; + + image = malloc(rom_size); + if (!image) { + printf("Out of memory.\n"); + exit(EXIT_FAILURE); + } + + memset(image, '\xff', rom_size); + if (!create && read(bios_fd, image, size) != size) { + perror("Could not read file"); + exit(EXIT_FAILURE); + } + if (size != rom_size) { + debug("ROM size changed to %d bytes\n", rom_size); + size = rom_size; + } + + write_it = true; + ret = 0; + if (mode_dump) { + ret = dump_fd(image, size); + write_it = false; + } + + if (mode_extract) { + ret = write_regions(image, size); + write_it = false; + } + + if (mode_write_descriptor) + ret = write_data(image, size, -size, src_fname); + + if (mode_inject) + ret = inject_region(image, size, region_type, src_fname); + + if (mode_write) + ret = write_data(image, size, addr, src_fname); + + if (mode_spifreq) + set_spi_frequency(image, size, spifreq); + + if (mode_em100) + set_em100_mode(image, size); + + if (mode_locked) + lock_descriptor(image, size); + + if (mode_unlocked) + unlock_descriptor(image, size); + + if (write_it) { + if (outfile) { + ret = write_image(outfile, image, size); + } else { + if (lseek(bios_fd, 0, SEEK_SET)) { + perror("Error while seeking"); + ret = -1; + } + if (write(bios_fd, image, size) != size) { + perror("Error while writing"); + ret = -1; + } + } + } + + free(image); + close(bios_fd); + + return ret ? 1 : 0; +} diff --git a/tools/ifdtool.h b/tools/ifdtool.h new file mode 100644 index 0000000..fbec421 --- /dev/null +++ b/tools/ifdtool.h @@ -0,0 +1,88 @@ +/* + * ifdtool - Manage Intel Firmware Descriptor information + * + * Copyright (C) 2011 The ChromiumOS Authors. + * + * SPDX-License-Identifier: GPL-2.0 + * + * From Coreboot project + */ + +#include <stdint.h> + +#define __packed __attribute__((packed)) + +#define IFDTOOL_VERSION "1.1-U-Boot" + +enum spi_frequency { + SPI_FREQUENCY_20MHZ = 0, + SPI_FREQUENCY_33MHZ = 1, + SPI_FREQUENCY_50MHZ = 4, +}; + +enum component_density { + COMPONENT_DENSITY_512KB = 0, + COMPONENT_DENSITY_1MB = 1, + COMPONENT_DENSITY_2MB = 2, + COMPONENT_DENSITY_4MB = 3, + COMPONENT_DENSITY_8MB = 4, + COMPONENT_DENSITY_16MB = 5, +}; + +/* flash descriptor */ +struct __packed fdbar_t { + uint32_t flvalsig; + uint32_t flmap0; + uint32_t flmap1; + uint32_t flmap2; + uint8_t reserved[0xefc - 0x20]; + uint32_t flumap1; +}; + +#define MAX_REGIONS 5 + +/* regions */ +struct __packed frba_t { + uint32_t flreg[MAX_REGIONS]; +}; + +/* component section */ +struct __packed fcba_t { + uint32_t flcomp; + uint32_t flill; + uint32_t flpb; +}; + +#define MAX_STRAPS 18 + +/* pch strap */ +struct __packed fpsba_t { + uint32_t pchstrp[MAX_STRAPS]; +}; + +/* master */ +struct __packed fmba_t { + uint32_t flmstr1; + uint32_t flmstr2; + uint32_t flmstr3; +}; + +/* processor strap */ +struct __packed fmsba_t { + uint32_t data[8]; +}; + +/* ME VSCC */ +struct vscc_t { + uint32_t jid; + uint32_t vscc; +}; + +struct vtba_t { + /* Actual number of entries specified in vtl */ + struct vscc_t entry[8]; +}; + +struct region_t { + int base, limit, size; +}; diff --git a/tools/mxsimage.c b/tools/mxsimage.c index 81c7f2d..04beefe 100644 --- a/tools/mxsimage.c +++ b/tools/mxsimage.c @@ -125,7 +125,7 @@ struct sb_image_ctx { unsigned int in_section:1; unsigned int in_dcd:1; /* Image configuration */ - unsigned int verbose_boot:1; + unsigned int display_progress:1; unsigned int silent_dump:1; char *input_filename; char *output_filename; @@ -1308,8 +1308,8 @@ static int sb_prefill_image_header(struct sb_image_ctx *ictx) sizeof(struct sb_sections_header) / SB_BLOCK_SIZE; hdr->timestamp_us = sb_get_timestamp() * 1000000; - /* FIXME -- add proper config option */ - hdr->flags = ictx->verbose_boot ? SB_IMAGE_FLAG_VERBOSE : 0, + hdr->flags = ictx->display_progress ? + SB_IMAGE_FLAG_DISPLAY_PROGRESS : 0; /* FIXME -- We support only default key */ hdr->key_count = 1; @@ -1416,7 +1416,7 @@ static int sb_parse_line(struct sb_image_ctx *ictx, struct sb_cmd_list *cmd) { char *tok; char *line = cmd->cmd; - char *rptr; + char *rptr = NULL; int ret; /* Analyze the identifier on this line first. */ @@ -1428,6 +1428,12 @@ static int sb_parse_line(struct sb_image_ctx *ictx, struct sb_cmd_list *cmd) cmd->cmd = rptr; + /* set DISPLAY_PROGRESS flag */ + if (!strcmp(tok, "DISPLAYPROGRESS")) { + ictx->display_progress = 1; + return 0; + } + /* DCD */ if (!strcmp(tok, "DCD")) { ictx->in_section = 0; @@ -1681,10 +1687,11 @@ static int sb_verify_image_header(struct sb_image_ctx *ictx, ntohs(hdr->component_version.minor), ntohs(hdr->component_version.revision)); - if (hdr->flags & ~SB_IMAGE_FLAG_VERBOSE) + if (hdr->flags & ~SB_IMAGE_FLAGS_MASK) ret = -EINVAL; soprintf(ictx, "%s Image flags: %s\n", stat[!!ret], - hdr->flags & SB_IMAGE_FLAG_VERBOSE ? "Verbose_boot" : ""); + hdr->flags & SB_IMAGE_FLAG_DISPLAY_PROGRESS ? + "Display_progress" : ""); if (ret) return ret; @@ -2287,7 +2294,6 @@ static int mxsimage_generate(struct image_tool_params *params, ctx.cfg_filename = params->imagename; ctx.output_filename = params->imagefile; - ctx.verbose_boot = 1; ret = sb_build_tree_from_cfg(&ctx); if (ret) diff --git a/tools/mxsimage.h b/tools/mxsimage.h index 6cd59d2..88f72eb 100644 --- a/tools/mxsimage.h +++ b/tools/mxsimage.h @@ -81,8 +81,9 @@ struct sb_boot_image_header { #define SB_VERSION_MAJOR 1 #define SB_VERSION_MINOR 1 -/* Enable to HTLLC verbose boot report. */ -#define SB_IMAGE_FLAG_VERBOSE (1 << 0) +/* Enable to HTLLC boot report. */ +#define SB_IMAGE_FLAG_DISPLAY_PROGRESS (1 << 0) +#define SB_IMAGE_FLAGS_MASK SB_IMAGE_FLAG_DISPLAY_PROGRESS struct sb_key_dictionary_key { /* The CBC-MAC of image and sections header. */ diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index d630157..da04883 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -248,8 +248,7 @@ class PatchStream: # Detect the start of a new commit elif commit_match: self.CloseCommit() - # TODO: We should store the whole hash, and just display a subset - self.commit = commit.Commit(commit_match.group(1)[:8]) + self.commit = commit.Commit(commit_match.group(1)) # Detect tags in the commit message elif tag_match: diff --git a/tools/pblimage.c b/tools/pblimage.c index 6e6e801..2a799ab 100644 --- a/tools/pblimage.c +++ b/tools/pblimage.c @@ -1,5 +1,5 @@ /* - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,6 +8,10 @@ #include "pblimage.h" #include "pbl_crc32.h" +#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) +#define PBL_ACS_CONT_CMD 0x81000000 +#define PBL_ADDR_24BIT_MASK 0x00ffffff + /* * Initialize to an invalid value. */ @@ -22,6 +26,13 @@ static int pbl_size; static char *fname = "Unknown"; static int lineno = -1; static struct pbl_header pblimage_header; +static int uboot_size; +static int arch_flag; + +static uint32_t pbl_cmd_initaddr; +static uint32_t pbi_crc_cmd1; +static uint32_t pbi_crc_cmd2; +static uint32_t pbl_end_cmd[4]; static union { @@ -38,20 +49,6 @@ static union * start offset by subtracting the size of the u-boot image from the * top of the allowable 24-bit range. */ -static void init_next_pbl_cmd(FILE *fp_uboot) -{ - struct stat st; - int fd = fileno(fp_uboot); - - if (fstat(fd, &st) == -1) { - printf("Error: Could not determine u-boot image size. %s\n", - strerror(errno)); - exit(EXIT_FAILURE); - } - - next_pbl_cmd = 0x82000000 - st.st_size; -} - static void generate_pbl_cmd(void) { uint32_t val = next_pbl_cmd; @@ -66,11 +63,15 @@ static void generate_pbl_cmd(void) static void pbl_fget(size_t size, FILE *stream) { - unsigned char c; + unsigned char c = 0xff; int c_temp; - while (size && (c_temp = fgetc(stream)) != EOF) { - c = (unsigned char)c_temp; + while (size) { + c_temp = fgetc(stream); + if (c_temp != EOF) + c = (unsigned char)c_temp; + else if ((c_temp == EOF) && (arch_flag == IH_ARCH_ARM)) + c = 0xff; *pmem_buf++ = c; pbl_size++; size--; @@ -80,8 +81,8 @@ static void pbl_fget(size_t size, FILE *stream) /* load split u-boot with PBI command 81xxxxxx. */ static void load_uboot(FILE *fp_uboot) { - init_next_pbl_cmd(fp_uboot); - while (next_pbl_cmd < 0x82000000) { + next_pbl_cmd = pbl_cmd_initaddr - uboot_size; + while (next_pbl_cmd < pbl_cmd_initaddr) { generate_pbl_cmd(); pbl_fget(64, fp_uboot); } @@ -154,8 +155,6 @@ static uint32_t reverse_byte(uint32_t val) /* write end command and crc command to memory. */ static void add_end_cmd(void) { - uint32_t pbl_end_cmd[4] = {0x09138000, 0x00000000, - 0x091380c0, 0x00000000}; uint32_t crc32_pbl; int i; unsigned char *p = (unsigned char *)&pbl_end_cmd; @@ -172,8 +171,8 @@ static void add_end_cmd(void) /* Add PBI CRC command. */ *pmem_buf++ = 0x08; - *pmem_buf++ = 0x13; - *pmem_buf++ = 0x80; + *pmem_buf++ = pbi_crc_cmd1; + *pmem_buf++ = pbi_crc_cmd2; *pmem_buf++ = 0x40; pbl_size += 4; @@ -184,17 +183,6 @@ static void add_end_cmd(void) *pmem_buf++ = (crc32_pbl >> 8) & 0xff; *pmem_buf++ = (crc32_pbl) & 0xff; pbl_size += 4; - - if ((pbl_size % 16) != 0) { - for (i = 0; i < 8; i++) { - *pmem_buf++ = 0x0; - pbl_size++; - } - } - if ((pbl_size % 16 != 0)) { - printf("Error: Bad size of image file\n"); - exit(EXIT_FAILURE); - } } void pbl_load_uboot(int ifd, struct image_tool_params *params) @@ -268,12 +256,64 @@ static void pblimage_set_header(void *ptr, struct stat *sbuf, int ifd, /*nothing need to do, pbl_load_uboot takes care of whole file. */ } +int pblimage_check_params(struct image_tool_params *params) +{ + FILE *fp_uboot; + int fd; + struct stat st; + + if (!params) + return EXIT_FAILURE; + + fp_uboot = fopen(params->datafile, "r"); + if (fp_uboot == NULL) { + printf("Error: %s open failed\n", params->datafile); + exit(EXIT_FAILURE); + } + fd = fileno(fp_uboot); + + if (fstat(fd, &st) == -1) { + printf("Error: Could not determine u-boot image size. %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } + + /* For the variable size, we need to pad it to 64 byte boundary */ + uboot_size = roundup(st.st_size, 64); + + if (params->arch == IH_ARCH_ARM) { + arch_flag = IH_ARCH_ARM; + pbi_crc_cmd1 = 0x61; + pbi_crc_cmd2 = 0; + pbl_cmd_initaddr = params->addr & PBL_ADDR_24BIT_MASK; + pbl_cmd_initaddr |= PBL_ACS_CONT_CMD; + pbl_cmd_initaddr |= uboot_size; + pbl_end_cmd[0] = 0x09610000; + pbl_end_cmd[1] = 0x00000000; + pbl_end_cmd[2] = 0x096100c0; + pbl_end_cmd[3] = 0x00000000; + } else if (params->arch == IH_ARCH_PPC) { + arch_flag = IH_ARCH_PPC; + pbi_crc_cmd1 = 0x13; + pbi_crc_cmd2 = 0x80; + pbl_cmd_initaddr = 0x82000000; + pbl_end_cmd[0] = 0x09138000; + pbl_end_cmd[1] = 0x00000000; + pbl_end_cmd[2] = 0x091380c0; + pbl_end_cmd[3] = 0x00000000; + } + + next_pbl_cmd = pbl_cmd_initaddr; + return 0; +}; + /* pblimage parameters */ static struct image_type_params pblimage_params = { .name = "Freescale PBL Boot Image support", .header_size = sizeof(struct pbl_header), .hdr = (void *)&pblimage_header, .check_image_type = pblimage_check_image_types, + .check_params = pblimage_check_params, .verify_header = pblimage_verify_header, .print_header = pblimage_print_header, .set_header = pblimage_set_header, |