diff options
85 files changed, 3413 insertions, 834 deletions
@@ -2438,6 +2438,15 @@ CBFS (Coreboot Filesystem) support - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3 - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3 - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3 + - activate dual channel with CONFIG_SYS_I2C_IHS_DUAL + - CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1 + - CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1 + - CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1 + - CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1 + - CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1 + - CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1 + - CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1 + - CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1 additional defines: diff --git a/arch/arm/include/asm/arch-hi6220/gpio.h b/arch/arm/include/asm/arch-hi6220/gpio.h index 4fafaef..29ace17 100644 --- a/arch/arm/include/asm/arch-hi6220/gpio.h +++ b/arch/arm/include/asm/arch-hi6220/gpio.h @@ -21,7 +21,7 @@ struct gpio_bank { /* Information about a GPIO bank */ struct hikey_gpio_platdata { int bank_index; - unsigned int base; /* address of registers in physical memory */ + ulong base; /* address of registers in physical memory */ }; #endif /* _HI6220_GPIO_H_ */ diff --git a/arch/openrisc/config.mk b/arch/openrisc/config.mk index cd95f24..bfdb71f 100644 --- a/arch/openrisc/config.mk +++ b/arch/openrisc/config.mk @@ -6,7 +6,7 @@ # ifeq ($(CROSS_COMPILE),) -CROSS_COMPILE := or32-elf- +CROSS_COMPILE := or1k-elf- endif # r10 used for global object pointer, already set in OR32 GCC but just to be diff --git a/arch/openrisc/cpu/u-boot.lds b/arch/openrisc/cpu/u-boot.lds index d9bb7b7..854088b 100644 --- a/arch/openrisc/cpu/u-boot.lds +++ b/arch/openrisc/cpu/u-boot.lds @@ -1,5 +1,5 @@ #include <config.h> -OUTPUT_ARCH(or32) +OUTPUT_ARCH(or1k) __DYNAMIC = 0; MEMORY diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 3fb901f..3ea62ca 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -67,6 +67,9 @@ config TARGET_TQM834X config TARGET_HRCON bool "Support hrcon" +config TARGET_STRIDER + bool "Support strider" + endchoice source "board/esd/vme8349/Kconfig" diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c index 039ec20..ad74ff2 100644 --- a/board/BuR/kwb/board.c +++ b/board/BuR/kwb/board.c @@ -47,10 +47,6 @@ #define RSTCTRL_FORCE_PWR_NEN 0x0404 #define RSTCTRL_CAN_STB 0x4040 -#define VXWORKS_BOOTLINE 0x80001100 -#define DEFAULT_BOOTLINE "cpsw(0,0):pme/vxWorks" -#define VXWORKS_USER "u=vxWorksFTP pw=vxWorks tn=vxtarget" - DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_SPL_BUILD) @@ -281,20 +277,15 @@ int board_late_init(void) } else { puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); } - /* setup vxworks bootline */ - char *vxworksbootline = (char *)VXWORKS_BOOTLINE; - sprintf(vxworksbootline, - "%s h=%s e=%s:%s g=%s %s o=0x%08x;0x%08x;0x%08x;0x%08x", - DEFAULT_BOOTLINE, - getenv("serverip"), - getenv("ipaddr"), getenv("netmask"), - getenv("gatewayip"), - VXWORKS_USER, - (unsigned int) gd->fb_base-0x20, - (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20), - (u32)getenv_ulong("vx_romfsbase", 16, 0), - (u32)getenv_ulong("vx_romfssize", 16, 0)); - + /* setup othbootargs for bootvx-command (vxWorks bootline) */ + char othbootargs[128]; + snprintf(othbootargs, sizeof(othbootargs), + "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x", + (unsigned int) gd->fb_base-0x20, + (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20), + (u32)getenv_ulong("vx_romfsbase", 16, 0), + (u32)getenv_ulong("vx_romfssize", 16, 0)); + setenv("othbootargs", othbootargs); /* * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does * expect that vectors are there, original u-boot moves them to _start diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index 35dfbbc..54c7eb3 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -25,17 +25,19 @@ #define LATCH2_MC2_PRESENT_N 0x0080 enum { - UNITTYPE_VIDEO_USER = 0, - UNITTYPE_MAIN_USER = 1, - UNITTYPE_VIDEO_SERVER = 2, - UNITTYPE_MAIN_SERVER = 3, + UNITTYPE_MAIN = 1<<0, + UNITTYPE_SERVER = 1<<1, + UNITTYPE_DISPLAYPORT = 1<<2, }; enum { HWVER_101 = 0, HWVER_110 = 1, - HWVER_120 = 2, - HWVER_130 = 3, + HWVER_130 = 2, + HWVER_140 = 3, + HWVER_150 = 4, + HWVER_160 = 5, + HWVER_170 = 6, }; enum { @@ -121,43 +123,48 @@ static void print_fpga_info(unsigned dev) feature_carriers = (fpga_features >> 2) & 0x0003; feature_video_channels = fpga_features & 0x0003; - switch (unit_type) { - case UNITTYPE_VIDEO_USER: - printf("Videochannel Userside"); - break; + if (unit_type & UNITTYPE_MAIN) + printf("Mainchannel "); + else + printf("Videochannel "); - case UNITTYPE_MAIN_USER: - printf("Mainchannel Userside"); - break; + if (unit_type & UNITTYPE_SERVER) + printf("Serverside "); + else + printf("Userside "); + + if (unit_type & UNITTYPE_DISPLAYPORT) + printf("DisplayPort"); + else + printf("DVI-DL"); - case UNITTYPE_VIDEO_SERVER: - printf("Videochannel Serverside"); + switch (hardware_version) { + case HWVER_101: + printf(" HW-Ver 1.01\n"); break; - case UNITTYPE_MAIN_SERVER: - printf("Mainchannel Serverside"); + case HWVER_110: + printf(" HW-Ver 1.10-1.20\n"); break; - default: - printf("UnitType %d(not supported)", unit_type); + case HWVER_130: + printf(" HW-Ver 1.30\n"); break; - } - switch (hardware_version) { - case HWVER_101: - printf(" HW-Ver 1.01\n"); + case HWVER_140: + printf(" HW-Ver 1.40-1.43\n"); break; - case HWVER_110: - printf(" HW-Ver 1.10-1.12\n"); + case HWVER_150: + printf(" HW-Ver 1.50\n"); break; - case HWVER_120: - printf(" HW-Ver 1.20\n"); + case HWVER_160: + printf(" HW-Ver 1.60-1.61\n"); break; - case HWVER_130: - printf(" HW-Ver 1.30\n"); + case HWVER_170: + printf(" HW-Ver 1.70\n"); break; default: @@ -260,7 +267,7 @@ int last_stage_init(void) if (get_mc2_present()) print_fpga_info(1); - if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER) + if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER) return 0; if (!get_fpga_state(0) || (get_hwver() == HWVER_101)) diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c index 3a51d86..7484624 100644 --- a/board/gdsys/405ep/iocon.c +++ b/board/gdsys/405ep/iocon.c @@ -381,7 +381,7 @@ int last_stage_init(void) ch0_rgmii2_present = !pca9698_get_value(0x20, 30); } - /* wait for FPGA done */ + /* wait for FPGA done; then reset FPGA */ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { unsigned int ctr = 0; @@ -396,6 +396,12 @@ int last_stage_init(void) break; } } + + pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); + pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); + udelay(10); + pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, + MCFPGA_RESET_N); } if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) { diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 4957943..ce23045 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -9,7 +9,10 @@ obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o obj-$(CONFIG_IO) += miiphybb.o obj-$(CONFIG_IO64) += miiphybb.o -obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o -obj-$(CONFIG_DLVISION_10G) += osd.o +obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o +obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o obj-$(CONFIG_CONTROLCENTERD) += dp501.o -obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o +obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o +obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o +obj-$(CONFIG_STRIDER) += fanctrl.o +obj-$(CONFIG_STRIDER_CON) += osd.o diff --git a/board/gdsys/common/adv7611.c b/board/gdsys/common/adv7611.c new file mode 100644 index 0000000..b728274 --- /dev/null +++ b/board/gdsys/common/adv7611.c @@ -0,0 +1,177 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> + +#define ADV7611_I2C_ADDR 0x4c +#define ADV7611_RDINFO 0x2051 + +/* + * ADV7611 I2C Addresses in u-boot notation + */ +enum { + CP_I2C_ADDR = 0x22, + DPLL_I2C_ADDR = 0x26, + KSV_I2C_ADDR = 0x32, + HDMI_I2C_ADDR = 0x34, + EDID_I2C_ADDR = 0x36, + INFOFRAME_I2C_ADDR = 0x3e, + CEC_I2C_ADDR = 0x40, + IO_I2C_ADDR = ADV7611_I2C_ADDR, +}; + +/* + * Global Control Registers + */ +enum { + IO_RD_INFO_MSB = 0xea, + IO_RD_INFO_LSB = 0xeb, + IO_CEC_ADDR = 0xf4, + IO_INFOFRAME_ADDR = 0xf5, + IO_DPLL_ADDR = 0xf8, + IO_KSV_ADDR = 0xf9, + IO_EDID_ADDR = 0xfa, + IO_HDMI_ADDR = 0xfb, + IO_CP_ADDR = 0xfd, +}; + +int adv7611_i2c[] = CONFIG_SYS_ADV7611_I2C; + +int adv7611_probe(unsigned int screen) +{ + int old_bus = i2c_get_bus_num(); + unsigned int rd_info; + int res = 0; + + i2c_set_bus_num(adv7611_i2c[screen]); + + rd_info = (i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_MSB) << 8) + | i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_LSB); + + if (rd_info != ADV7611_RDINFO) { + res = -1; + goto out; + } + + /* + * set I2C addresses to default values + */ + i2c_reg_write(IO_I2C_ADDR, IO_CEC_ADDR, CEC_I2C_ADDR << 1); + i2c_reg_write(IO_I2C_ADDR, IO_INFOFRAME_ADDR, INFOFRAME_I2C_ADDR << 1); + i2c_reg_write(IO_I2C_ADDR, IO_DPLL_ADDR, DPLL_I2C_ADDR << 1); + i2c_reg_write(IO_I2C_ADDR, IO_KSV_ADDR, KSV_I2C_ADDR << 1); + i2c_reg_write(IO_I2C_ADDR, IO_EDID_ADDR, EDID_I2C_ADDR << 1); + i2c_reg_write(IO_I2C_ADDR, IO_HDMI_ADDR, HDMI_I2C_ADDR << 1); + i2c_reg_write(IO_I2C_ADDR, IO_CP_ADDR, CP_I2C_ADDR << 1); + + /* + * do magic initialization sequence from + * "ADV7611 Register Settings Recommendations Revision 1.5" + * with most registers undocumented + */ + i2c_reg_write(CP_I2C_ADDR, 0x6c, 0x00); + i2c_reg_write(HDMI_I2C_ADDR, 0x9b, 0x03); + i2c_reg_write(HDMI_I2C_ADDR, 0x6f, 0x08); + i2c_reg_write(HDMI_I2C_ADDR, 0x85, 0x1f); + i2c_reg_write(HDMI_I2C_ADDR, 0x87, 0x70); + i2c_reg_write(HDMI_I2C_ADDR, 0x57, 0xda); + i2c_reg_write(HDMI_I2C_ADDR, 0x58, 0x01); + i2c_reg_write(HDMI_I2C_ADDR, 0x03, 0x98); + i2c_reg_write(HDMI_I2C_ADDR, 0x4c, 0x44); + + /* + * IO_REG_02, default 0xf0 + * + * INP_COLOR_SPACE (IO, Address 0x02[7:4]) + * default: 0b1111 auto + * set to : 0b0001 force RGB (range 0 to 255) input + * + * RGB_OUT (IO, Address 0x02[1]) + * default: 0 YPbPr color space output + * set to : 1 RGB color space output + */ + i2c_reg_write(IO_I2C_ADDR, 0x02, 0x12); + + /* + * IO_REG_03, default 0x00 + * + * OP_FORMAT_SEL (IO, Address 0x03[7:0]) + * default: 0x00 8-bit SDR ITU-656 mode + * set to : 0x40 24-bit 4:4:4 SDR mode + */ + i2c_reg_write(IO_I2C_ADDR, 0x03, 0x40); + + /* + * IO_REG_05, default 0x2c + * + * AVCODE_INSERT_EN (IO, Address 0x05[2]) + * default: 1 insert AV codes into data stream + * set to : 0 do not insert AV codes into data stream + */ + i2c_reg_write(IO_I2C_ADDR, 0x05, 0x28); + + /* + * IO_REG_0C, default 0x62 + * + * POWER_DOWN (IO, Address 0x0C[5]) + * default: 1 chip is powered down + * set to : 0 chip is operational + */ + i2c_reg_write(IO_I2C_ADDR, 0x0c, 0x42); + + /* + * IO_REG_15, default 0xbe + * + * TRI_SYNCS (IO, Address 0x15[3) + * TRI_LLC (IO, Address 0x15[2]) + * TRI_PIX (IO, Address 0x15[1]) + * default: 1 video output pins are tristate + * set to : 0 video output pins are active + */ + i2c_reg_write(IO_I2C_ADDR, 0x15, 0xb0); + + /* + * HDMI_REGISTER_02H, default 0xff + * + * CLOCK_TERMA_DISABLE (HDMI, Address 0x83[0]) + * default: 1 disable termination + * set to : 0 enable termination + * Future options are: + * - use the chips automatic termination control + * - set this manually on cable detect + * but at the moment this seems a safe default. + */ + i2c_reg_write(HDMI_I2C_ADDR, 0x83, 0xfe); + + /* + * HDMI_CP_CNTRL_1, default 0x01 + * + * HDMI_FRUN_EN (CP, Address 0xBA[0]) + * default: 1 Enable the free run feature in HDMI mode + * set to : 0 Disable the free run feature in HDMI mode + */ + i2c_reg_write(CP_I2C_ADDR, 0xba, 0x00); + + /* + * INT1_CONFIGURATION, default 0x20 + * + * INTRQ_DUR_SEL[1:0] (IO, Address 0x40[7:6]) + * default: 00 Interrupt signal is active for 4 Xtal periods + * set to : 11 Active until cleared + * + * INTRQ_OP_SEL[1:0] (IO, Address 0x40[1:0]) + * default: 00 Open drain + * set to : 10 Drives high when active + */ + i2c_reg_write(IO_I2C_ADDR, 0x40, 0xc2); + +out: + i2c_set_bus_num(old_bus); + + return res; +} diff --git a/board/gdsys/common/adv7611.h b/board/gdsys/common/adv7611.h new file mode 100644 index 0000000..25a8367 --- /dev/null +++ b/board/gdsys/common/adv7611.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ADV7611_H_ +#define _ADV7611_H_ + +int adv7611_probe(unsigned int screen); + +#endif diff --git a/board/gdsys/common/ch7301.c b/board/gdsys/common/ch7301.c new file mode 100644 index 0000000..c054e55 --- /dev/null +++ b/board/gdsys/common/ch7301.c @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Chrontel CH7301C DVI Transmitter */ + +#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <i2c.h> + +#define CH7301_I2C_ADDR 0x75 + +enum { + CH7301_CM = 0x1c, /* Clock Mode Register */ + CH7301_IC = 0x1d, /* Input Clock Register */ + CH7301_GPIO = 0x1e, /* GPIO Control Register */ + CH7301_IDF = 0x1f, /* Input Data Format Register */ + CH7301_CD = 0x20, /* Connection Detect Register */ + CH7301_DC = 0x21, /* DAC Control Register */ + CH7301_HPD = 0x23, /* Hot Plug Detection Register */ + CH7301_TCTL = 0x31, /* DVI Control Input Register */ + CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */ + CH7301_TPD = 0x34, /* DVI PLL Divide Register */ + CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */ + CH7301_TPF = 0x36, /* DVI PLL Filter Register */ + CH7301_TCT = 0x37, /* DVI Clock Test Register */ + CH7301_TSTP = 0x48, /* Test Pattern Register */ + CH7301_PM = 0x49, /* Power Management register */ + CH7301_VID = 0x4a, /* Version ID Register */ + CH7301_DID = 0x4b, /* Device ID Register */ + CH7301_DSP = 0x56, /* DVI Sync polarity Register */ +}; + +int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; + +int ch7301_probe(unsigned screen, bool power) +{ + u8 value; + + i2c_set_bus_num(ch7301_i2c[screen]); + if (i2c_probe(CH7301_I2C_ADDR)) + return -1; + + value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); + if (value != 0x17) + return -1; + + if (power) { + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); + } else { + i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x00); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0x01); + } + + return 0; +} diff --git a/board/gdsys/common/ch7301.h b/board/gdsys/common/ch7301.h new file mode 100644 index 0000000..8383719 --- /dev/null +++ b/board/gdsys/common/ch7301.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CH7301_H_ +#define _CH7301_H_ + +int ch7301_probe(unsigned screen, bool power); + +#endif diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index 7eb15ed..d35aee0 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -40,11 +40,29 @@ static int dp501_detect_cable_adapter(u8 addr) static void dp501_link_training(u8 addr) { u8 val; + u8 link_bw; + u8 max_lane_cnt; + u8 lane_cnt; val = i2c_reg_read(addr, 0x51); - i2c_reg_write(addr, 0x5d, val); /* set link_bw */ + if (val >= 0x0a) + link_bw = 0x0a; + else + link_bw = 0x06; + if (link_bw != val) + printf("DP sink supports %d Mbps link rate, set to %d Mbps\n", + val * 270, link_bw * 270); + i2c_reg_write(addr, 0x5d, link_bw); /* set link_bw */ val = i2c_reg_read(addr, 0x52); - i2c_reg_write(addr, 0x5e, val); /* set lane_cnt */ + max_lane_cnt = val & 0x1f; + if (max_lane_cnt >= 4) + lane_cnt = 4; + else + lane_cnt = max_lane_cnt; + if (lane_cnt != max_lane_cnt) + printf("DP sink supports %d lanes, set to %d lanes\n", + max_lane_cnt, lane_cnt); + i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ val = i2c_reg_read(addr, 0x53); i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */ @@ -77,6 +95,8 @@ void dp501_powerup(u8 addr) i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */ #endif + i2c_reg_write(addr + 2, 0x1a, 0x04); /* SPDIF input method TTL */ + i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */ i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */ i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */ @@ -86,7 +106,8 @@ void dp501_powerup(u8 addr) dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */ i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */ i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */ - i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */ + i2c_reg_write(addr, 0x87, 0x7f); /* set retry counter as 7 + retry interval 400us */ if (dp501_detect_cable_adapter(addr)) { printf("DVI/HDMI cable adapter detected\n"); diff --git a/board/gdsys/common/fanctrl.c b/board/gdsys/common/fanctrl.c new file mode 100644 index 0000000..44569bb --- /dev/null +++ b/board/gdsys/common/fanctrl.c @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> + +enum { + FAN_CONFIG = 0x03, + FAN_TACHLIM_LSB = 0x48, + FAN_TACHLIM_MSB = 0x49, + FAN_PWM_FREQ = 0x4D, +}; + +void init_fan_controller(u8 addr) +{ + int val; + + /* set PWM Frequency to 2.5% resolution */ + i2c_reg_write(addr, FAN_PWM_FREQ, 20); + + /* set Tachometer Limit */ + i2c_reg_write(addr, FAN_TACHLIM_LSB, 0x10); + i2c_reg_write(addr, FAN_TACHLIM_MSB, 0x0a); + + /* enable Tach input */ + val = i2c_reg_read(addr, FAN_CONFIG) | 0x04; + i2c_reg_write(addr, FAN_CONFIG, val); +} diff --git a/board/gdsys/common/fanctrl.h b/board/gdsys/common/fanctrl.h new file mode 100644 index 0000000..12bc850 --- /dev/null +++ b/board/gdsys/common/fanctrl.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FANCTRL_H_ +#define _FANCTRL_H_ + +void init_fan_controller(u8 addr); + +#endif diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c new file mode 100644 index 0000000..96f02d6 --- /dev/null +++ b/board/gdsys/common/ioep-fpga.c @@ -0,0 +1,232 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#include <gdsys_fpga.h> + +enum { + UNITTYPE_MAIN_SERVER = 0, + UNITTYPE_MAIN_USER = 1, + UNITTYPE_VIDEO_SERVER = 2, + UNITTYPE_VIDEO_USER = 3, +}; + +enum { + UNITTYPEPCB_DVI = 0, + UNITTYPEPCB_DP_165 = 1, + UNITTYPEPCB_DP_300 = 2, + UNITTYPEPCB_HDMI = 3, +}; + +enum { + COMPRESSION_NONE = 0, + COMPRESSION_TYPE1_DELTA = 1, + COMPRESSION_TYPE1_TYPE2_DELTA = 3, +}; + +enum { + AUDIO_NONE = 0, + AUDIO_TX = 1, + AUDIO_RX = 2, + AUDIO_RXTX = 3, +}; + +enum { + SYSCLK_147456 = 0, +}; + +enum { + RAM_DDR2_32 = 0, + RAM_DDR3_32 = 1, + RAM_DDR3_48 = 2, +}; + +enum { + CARRIER_SPEED_1G = 0, + CARRIER_SPEED_2_5G = 1, +}; + +bool ioep_fpga_has_osd(unsigned int fpga) +{ + u16 fpga_features; + unsigned feature_osd; + + FPGA_GET_REG(0, fpga_features, &fpga_features); + feature_osd = fpga_features & (1<<11); + + return feature_osd; +} + +void ioep_fpga_print_info(unsigned int fpga) +{ + u16 versions; + u16 fpga_version; + u16 fpga_features; + unsigned unit_type; + unsigned unit_type_pcb_video; + unsigned feature_compression; + unsigned feature_osd; + unsigned feature_audio; + unsigned feature_sysclock; + unsigned feature_ramconfig; + unsigned feature_carrier_speed; + unsigned feature_carriers; + unsigned feature_video_channels; + + FPGA_GET_REG(fpga, versions, &versions); + FPGA_GET_REG(fpga, fpga_version, &fpga_version); + FPGA_GET_REG(fpga, fpga_features, &fpga_features); + + unit_type = (versions & 0xf000) >> 12; + unit_type_pcb_video = (versions & 0x01c0) >> 6; + feature_compression = (fpga_features & 0xe000) >> 13; + feature_osd = fpga_features & (1<<11); + feature_audio = (fpga_features & 0x0600) >> 9; + feature_sysclock = (fpga_features & 0x0180) >> 7; + feature_ramconfig = (fpga_features & 0x0060) >> 5; + feature_carrier_speed = fpga_features & (1<<4); + feature_carriers = (fpga_features & 0x000c) >> 2; + feature_video_channels = fpga_features & 0x0003; + + switch (unit_type) { + case UNITTYPE_MAIN_SERVER: + case UNITTYPE_MAIN_USER: + printf("Mainchannel"); + break; + + case UNITTYPE_VIDEO_SERVER: + case UNITTYPE_VIDEO_USER: + printf("Videochannel"); + break; + + default: + printf("UnitType %d(not supported)", unit_type); + break; + } + + switch (unit_type) { + case UNITTYPE_MAIN_SERVER: + case UNITTYPE_VIDEO_SERVER: + printf(" Server"); + if (versions & (1<<4)) + printf(" UC"); + break; + + case UNITTYPE_MAIN_USER: + case UNITTYPE_VIDEO_USER: + printf(" User"); + break; + + default: + break; + } + + if (versions & (1<<5)) + printf(" Fiber"); + else + printf(" CAT"); + + switch (unit_type_pcb_video) { + case UNITTYPEPCB_DVI: + printf(" DVI,"); + break; + + case UNITTYPEPCB_DP_165: + printf(" DP 165MPix/s,"); + break; + + case UNITTYPEPCB_DP_300: + printf(" DP 300MPix/s,"); + break; + + case UNITTYPEPCB_HDMI: + printf(" HDMI,"); + break; + } + + printf(" FPGA V %d.%02d\n features:", + fpga_version / 100, fpga_version % 100); + + + switch (feature_compression) { + case COMPRESSION_NONE: + printf(" no compression"); + break; + + case COMPRESSION_TYPE1_DELTA: + printf(" type1-deltacompression"); + break; + + case COMPRESSION_TYPE1_TYPE2_DELTA: + printf(" type1-deltacompression, type2-inlinecompression"); + break; + + default: + printf(" compression %d(not supported)", feature_compression); + break; + } + + printf(", %sosd", feature_osd ? "" : "no "); + + switch (feature_audio) { + case AUDIO_NONE: + printf(", no audio"); + break; + + case AUDIO_TX: + printf(", audio tx"); + break; + + case AUDIO_RX: + printf(", audio rx"); + break; + + case AUDIO_RXTX: + printf(", audio rx+tx"); + break; + + default: + printf(", audio %d(not supported)", feature_audio); + break; + } + + puts(",\n "); + + switch (feature_sysclock) { + case SYSCLK_147456: + printf("clock 147.456 MHz"); + break; + + default: + printf("clock %d(not supported)", feature_sysclock); + break; + } + + switch (feature_ramconfig) { + case RAM_DDR2_32: + printf(", RAM 32 bit DDR2"); + break; + + case RAM_DDR3_32: + printf(", RAM 32 bit DDR3"); + break; + + case RAM_DDR3_48: + printf(", RAM 48 bit DDR3"); + break; + + default: + printf(", RAM %d(not supported)", feature_ramconfig); + break; + } + + printf(", %d carrier(s) %s", feature_carriers, + feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); + + printf(", %d video channel(s)\n", feature_video_channels); +} diff --git a/board/gdsys/common/ioep-fpga.h b/board/gdsys/common/ioep-fpga.h new file mode 100644 index 0000000..44f7139 --- /dev/null +++ b/board/gdsys/common/ioep-fpga.h @@ -0,0 +1,14 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IOEP_FPGA_H_ +#define _IOEP_FPGA_H_ + +void ioep_fpga_print_info(unsigned int fpga); +bool ioep_fpga_has_osd(unsigned int fpga); + +#endif diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index 55ecdf1..7444bee 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -9,11 +9,10 @@ #include <i2c.h> #include <malloc.h> +#include "ch7301.h" #include "dp501.h" #include <gdsys_fpga.h> -#define CH7301_I2C_ADDR 0x75 - #define ICS8N3QV01_I2C_ADDR 0x6E #define ICS8N3QV01_FREF 114285000 #define ICS8N3QV01_FREF_LL 114285000LL @@ -28,43 +27,53 @@ #define DP501_I2C_ADDR 0x08 #define PIXCLK_640_480_60 25180000 +#define MAX_X_CHARS 53 +#define MAX_Y_CHARS 26 + +#ifdef CONFIG_SYS_OSD_DH +#define MAX_OSD_SCREEN 8 +#define OSD_DH_BASE 4 +#else +#define MAX_OSD_SCREEN 4 +#endif + +#ifdef CONFIG_SYS_OSD_DH +#define OSD_SET_REG(screen, fld, val) \ + do { \ + if (screen >= OSD_DH_BASE) \ + FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \ + else \ + FPGA_SET_REG(screen, osd0.fld, val); \ + } while (0) +#else +#define OSD_SET_REG(screen, fld, val) \ + FPGA_SET_REG(screen, osd0.fld, val) +#endif -enum { - CH7301_CM = 0x1c, /* Clock Mode Register */ - CH7301_IC = 0x1d, /* Input Clock Register */ - CH7301_GPIO = 0x1e, /* GPIO Control Register */ - CH7301_IDF = 0x1f, /* Input Data Format Register */ - CH7301_CD = 0x20, /* Connection Detect Register */ - CH7301_DC = 0x21, /* DAC Control Register */ - CH7301_HPD = 0x23, /* Hot Plug Detection Register */ - CH7301_TCTL = 0x31, /* DVI Control Input Register */ - CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */ - CH7301_TPD = 0x34, /* DVI PLL Divide Register */ - CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */ - CH7301_TPF = 0x36, /* DVI PLL Filter Register */ - CH7301_TCT = 0x37, /* DVI Clock Test Register */ - CH7301_TSTP = 0x48, /* Test Pattern Register */ - CH7301_PM = 0x49, /* Power Management register */ - CH7301_VID = 0x4a, /* Version ID Register */ - CH7301_DID = 0x4b, /* Device ID Register */ - CH7301_DSP = 0x56, /* DVI Sync polarity Register */ -}; +#ifdef CONFIG_SYS_OSD_DH +#define OSD_GET_REG(screen, fld, val) \ + do { \ + if (screen >= OSD_DH_BASE) \ + FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \ + else \ + FPGA_GET_REG(screen, osd0.fld, val); \ + } while (0) +#else +#define OSD_GET_REG(screen, fld, val) \ + FPGA_GET_REG(screen, osd0.fld, val) +#endif unsigned int base_width; unsigned int base_height; size_t bufsize; u16 *buf; -unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1; +unsigned int osd_screen_mask = 0; #ifdef CONFIG_SYS_ICS8N3QV01_I2C int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C; #endif -#ifdef CONFIG_SYS_CH7301_I2C -int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; -#endif - #ifdef CONFIG_SYS_SIL1178_I2C int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C; #endif @@ -73,6 +82,9 @@ int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C; int dp501_i2c[] = CONFIG_SYS_DP501_I2C; #endif +#ifdef CONFIG_SYS_DP501_BASE +int dp501_base[] = CONFIG_SYS_DP501_BASE; +#endif #ifdef CONFIG_SYS_MPC92469AC static void mpc92469ac_calc_parameters(unsigned int fout, @@ -242,7 +254,15 @@ static int osd_write_videomem(unsigned screen, unsigned offset, for (k = 0; k < charcount; ++k) { if (offset + k >= bufsize) return -1; - FPGA_SET_REG(screen, videomem[offset + k], data[k]); +#ifdef CONFIG_SYS_OSD_DH + if (screen >= OSD_DH_BASE) + FPGA_SET_REG(screen - OSD_DH_BASE, + videomem1[offset + k], data[k]); + else + FPGA_SET_REG(screen, videomem0[offset + k], data[k]); +#else + FPGA_SET_REG(screen, videomem0[offset + k], data[k]); +#endif } return charcount; @@ -252,7 +272,12 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned screen; - for (screen = 0; screen <= max_osd_screen; ++screen) { + if (argc < 5) { + cmd_usage(cmdtp); + return 1; + } + + for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) { unsigned x; unsigned y; unsigned charcount; @@ -262,10 +287,8 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char *text; int res; - if (argc < 5) { - cmd_usage(cmdtp); - return 1; - } + if (!(osd_screen_mask & (1 << screen))) + continue; x = simple_strtoul(argv[1], NULL, 16); y = simple_strtoul(argv[2], NULL, 16); @@ -280,6 +303,8 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) res = osd_write_videomem(screen, y * base_width + x, buf, len); if (res < 0) return res; + + OSD_SET_REG(screen, control, 0x0049); } return 0; @@ -292,9 +317,16 @@ int osd_probe(unsigned screen) int old_bus = i2c_get_bus_num(); bool pixclock_present = false; bool output_driver_present = false; +#ifdef CONFIG_SYS_DP501_I2C +#ifdef CONFIG_SYS_DP501_BASE + uint8_t dp501_addr = dp501_base[screen]; +#else + uint8_t dp501_addr = DP501_I2C_ADDR; +#endif +#endif - FPGA_GET_REG(0, osd.version, &version); - FPGA_GET_REG(0, osd.features, &features); + OSD_GET_REG(0, version, &version); + OSD_GET_REG(0, features, &features); base_width = ((features & 0x3f00) >> 8) + 1; base_height = (features & 0x001f) + 1; @@ -303,9 +335,15 @@ int osd_probe(unsigned screen) if (!buf) return -1; +#ifdef CONFIG_SYS_OSD_DH + printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n", + (screen >= OSD_DH_BASE) ? (screen - OSD_DH_BASE) : screen, + (screen > 3) ? 1 : 0, version/100, version%100, base_width, + base_height); +#else printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n", - screen, version/100, version%100, base_width, base_height); - + screen, version/100, version%100, base_width, base_height); +#endif /* setup pixclock */ #ifdef CONFIG_SYS_MPC92469AC @@ -327,19 +365,8 @@ int osd_probe(unsigned screen) /* setup output driver */ #ifdef CONFIG_SYS_CH7301_I2C - i2c_set_bus_num(ch7301_i2c[screen]); - if (!i2c_probe(CH7301_I2C_ADDR)) { - u8 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); - - if (value == 0x17) { - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); - output_driver_present = true; - } - } + if (!ch7301_probe(screen, true)) + output_driver_present = true; #endif #ifdef CONFIG_SYS_SIL1178_I2C @@ -367,8 +394,8 @@ int osd_probe(unsigned screen) #ifdef CONFIG_SYS_DP501_I2C i2c_set_bus_num(dp501_i2c[screen]); - if (!i2c_probe(DP501_I2C_ADDR)) { - dp501_powerup(DP501_I2C_ADDR); + if (!i2c_probe(dp501_addr)) { + dp501_powerup(dp501_addr); output_driver_present = true; } #endif @@ -376,14 +403,12 @@ int osd_probe(unsigned screen) if (!output_driver_present) printf(" no output driver found\n"); - FPGA_SET_REG(screen, osd.control, 0x0049); - - FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1)); - FPGA_SET_REG(screen, osd.x_pos, 0x007f); - FPGA_SET_REG(screen, osd.y_pos, 0x005f); + OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) | (16 - 1)); + OSD_SET_REG(screen, x_pos, 0x007f); + OSD_SET_REG(screen, y_pos, 0x005f); - if (screen > max_osd_screen) - max_osd_screen = screen; + if (pixclock_present && output_driver_present) + osd_screen_mask |= 1 << screen; i2c_set_bus_num(old_bus); @@ -394,7 +419,12 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned screen; - for (screen = 0; screen <= max_osd_screen; ++screen) { + if ((argc < 4) || (strlen(argv[3]) % 4)) { + cmd_usage(cmdtp); + return 1; + } + + for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) { unsigned x; unsigned y; unsigned k; @@ -404,10 +434,8 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) unsigned count = (argc > 4) ? simple_strtoul(argv[4], NULL, 16) : 1; - if ((argc < 4) || (strlen(argv[3]) % 4)) { - cmd_usage(cmdtp); - return 1; - } + if (!(osd_screen_mask & (1 << screen))) + continue; x = simple_strtoul(argv[1], NULL, 16); y = simple_strtoul(argv[2], NULL, 16); @@ -433,6 +461,37 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) osd_write_videomem(screen, offset, buffer, wp - buffer); } + + OSD_SET_REG(screen, control, 0x0049); + } + + return 0; +} + +int osd_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned screen; + unsigned x; + unsigned y; + + if (argc < 3) { + cmd_usage(cmdtp); + return 1; + } + + x = simple_strtoul(argv[1], NULL, 16); + y = simple_strtoul(argv[2], NULL, 16); + + if (!x || (x > 64) || (x > MAX_X_CHARS) || + !y || (y > 32) || (y > MAX_Y_CHARS)) { + cmd_usage(cmdtp); + return 1; + } + + for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) { + OSD_SET_REG(screen, xy_size, ((x - 1) << 8) | (y - 1)); + OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535); + OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535); } return 0; @@ -449,3 +508,10 @@ U_BOOT_CMD( "write ASCII buffer to osd memory", "pos_x pos_y color text\n" ); + +U_BOOT_CMD( + osdsize, 3, 0, osd_size, + "set OSD XY size in characters", + "size_x(max. " __stringify(MAX_X_CHARS) + ") size_y(max. " __stringify(MAX_Y_CHARS) ")\n" +); diff --git a/board/gdsys/common/osd.h b/board/gdsys/common/osd.h index 440b276..5b3f14b 100644 --- a/board/gdsys/common/osd.h +++ b/board/gdsys/common/osd.h @@ -8,6 +8,7 @@ #ifndef _OSD_H_ #define _OSD_H_ +int ch7301_probe(unsigned screen, bool power); int osd_probe(unsigned screen); #endif diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index 43e1663..9a1a3a2 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -10,3 +10,16 @@ config SYS_CONFIG_NAME default "hrcon" endif + +if TARGET_STRIDER + +config SYS_BOARD + default "mpc8308" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "strider" + +endif diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS index a7853a5..3895b01 100644 --- a/board/gdsys/mpc8308/MAINTAINERS +++ b/board/gdsys/mpc8308/MAINTAINERS @@ -4,3 +4,7 @@ S: Maintained F: board/gdsys/mpc8308/ F: include/configs/hrcon.h F: configs/hrcon_defconfig +F: configs/hrcon_dh_defconfig +F: include/configs/strider.h +F: configs/strider_cpu_defconfig +F: configs/strider_con_defconfig diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile index b5dfdbb..42702fb 100644 --- a/board/gdsys/mpc8308/Makefile +++ b/board/gdsys/mpc8308/Makefile @@ -7,3 +7,4 @@ obj-y := mpc8308.o sdram.o obj-$(CONFIG_HRCON) += hrcon.o +obj-$(CONFIG_STRIDER) += strider.o diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c index e4434b3..880b638 100644 --- a/board/gdsys/mpc8308/hrcon.c +++ b/board/gdsys/mpc8308/hrcon.c @@ -22,9 +22,11 @@ #include <gdsys_fpga.h> +#include "../common/ioep-fpga.h" #include "../common/osd.h" #include "../common/mclink.h" #include "../common/phy.h" +#include "../common/fanctrl.h" #include <pca953x.h> #include <pca9698.h> @@ -36,57 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; #define MAX_MUX_CHANNELS 2 enum { - UNITTYPE_MAIN_SERVER = 0, - UNITTYPE_MAIN_USER = 1, - UNITTYPE_VIDEO_SERVER = 2, - UNITTYPE_VIDEO_USER = 3, -}; - -enum { - UNITTYPEPCB_DVI = 0, - UNITTYPEPCB_DP_165 = 1, - UNITTYPEPCB_DP_300 = 2, - UNITTYPEPCB_HDMI = 3, -}; - -enum { - HWVER_100 = 0, - HWVER_110 = 1, -}; - -enum { - FPGA_HWVER_200 = 0, - FPGA_HWVER_210 = 1, -}; - -enum { - COMPRESSION_NONE = 0, - COMPRESSION_TYPE1_DELTA = 1, - COMPRESSION_TYPE1_TYPE2_DELTA = 3, -}; - -enum { - AUDIO_NONE = 0, - AUDIO_TX = 1, - AUDIO_RX = 2, - AUDIO_RXTX = 3, -}; - -enum { - SYSCLK_147456 = 0, -}; - -enum { - RAM_DDR2_32 = 0, - RAM_DDR3_32 = 1, -}; - -enum { - CARRIER_SPEED_1G = 0, - CARRIER_SPEED_2_5G = 1, -}; - -enum { MCFPGA_DONE = 1 << 0, MCFPGA_INIT_N = 1 << 1, MCFPGA_PROGRAM_N = 1 << 2, @@ -102,6 +53,11 @@ enum { unsigned int mclink_fpgacount; struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; +struct { + u8 bus; + u8 addr; +} hrcon_fans[] = CONFIG_HRCON_FANS; + int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) { int res; @@ -164,197 +120,12 @@ int checkboard(void) return 0; } -static void print_fpga_info(unsigned int fpga, bool rgmii2_present) -{ - u16 versions; - u16 fpga_version; - u16 fpga_features; - unsigned unit_type; - unsigned unit_type_pcb_video; - unsigned hardware_version; - unsigned feature_compression; - unsigned feature_osd; - unsigned feature_audio; - unsigned feature_sysclock; - unsigned feature_ramconfig; - unsigned feature_carrier_speed; - unsigned feature_carriers; - unsigned feature_video_channels; - - FPGA_GET_REG(fpga, versions, &versions); - FPGA_GET_REG(fpga, fpga_version, &fpga_version); - FPGA_GET_REG(fpga, fpga_features, &fpga_features); - - unit_type = (versions & 0xf000) >> 12; - unit_type_pcb_video = (versions & 0x01c0) >> 6; - feature_compression = (fpga_features & 0xe000) >> 13; - feature_osd = fpga_features & (1<<11); - feature_audio = (fpga_features & 0x0600) >> 9; - feature_sysclock = (fpga_features & 0x0180) >> 7; - feature_ramconfig = (fpga_features & 0x0060) >> 5; - feature_carrier_speed = fpga_features & (1<<4); - feature_carriers = (fpga_features & 0x000c) >> 2; - feature_video_channels = fpga_features & 0x0003; - - switch (unit_type) { - case UNITTYPE_MAIN_USER: - printf("Mainchannel"); - break; - - case UNITTYPE_VIDEO_USER: - printf("Videochannel"); - break; - - default: - printf("UnitType %d(not supported)", unit_type); - break; - } - - if (unit_type == UNITTYPE_MAIN_USER) { - hardware_version = - (!!pca9698_get_value(0x20, 24) << 0) - | (!!pca9698_get_value(0x20, 25) << 1) - | (!!pca9698_get_value(0x20, 26) << 2) - | (!!pca9698_get_value(0x20, 27) << 3) - | (!!pca9698_get_value(0x20, 28) << 4); - switch (hardware_version) { - case HWVER_100: - printf(" HW-Ver 1.00,"); - break; - - case HWVER_110: - printf(" HW-Ver 1.10,"); - break; - - default: - printf(" HW-Ver %d(not supported),", - hardware_version); - break; - } - if (rgmii2_present) - printf(" RGMII2,"); - } - - if (unit_type == UNITTYPE_VIDEO_USER) { - hardware_version = versions & 0x000f; - switch (hardware_version) { - case FPGA_HWVER_200: - printf(" HW-Ver 2.00,"); - break; - - case FPGA_HWVER_210: - printf(" HW-Ver 2.10,"); - break; - - default: - printf(" HW-Ver %d(not supported),", - hardware_version); - break; - } - } - - switch (unit_type_pcb_video) { - case UNITTYPEPCB_DVI: - printf(" DVI,"); - break; - - case UNITTYPEPCB_DP_165: - printf(" DP 165MPix/s,"); - break; - - case UNITTYPEPCB_DP_300: - printf(" DP 300MPix/s,"); - break; - - case UNITTYPEPCB_HDMI: - printf(" HDMI,"); - break; - } - - printf(" FPGA V %d.%02d\n features:", - fpga_version / 100, fpga_version % 100); - - - switch (feature_compression) { - case COMPRESSION_NONE: - printf(" no compression"); - break; - - case COMPRESSION_TYPE1_DELTA: - printf(" type1-deltacompression"); - break; - - case COMPRESSION_TYPE1_TYPE2_DELTA: - printf(" type1-deltacompression, type2-inlinecompression"); - break; - - default: - printf(" compression %d(not supported)", feature_compression); - break; - } - - printf(", %sosd", feature_osd ? "" : "no "); - - switch (feature_audio) { - case AUDIO_NONE: - printf(", no audio"); - break; - - case AUDIO_TX: - printf(", audio tx"); - break; - - case AUDIO_RX: - printf(", audio rx"); - break; - - case AUDIO_RXTX: - printf(", audio rx+tx"); - break; - - default: - printf(", audio %d(not supported)", feature_audio); - break; - } - - puts(",\n "); - - switch (feature_sysclock) { - case SYSCLK_147456: - printf("clock 147.456 MHz"); - break; - - default: - printf("clock %d(not supported)", feature_sysclock); - break; - } - - switch (feature_ramconfig) { - case RAM_DDR2_32: - printf(", RAM 32 bit DDR2"); - break; - - case RAM_DDR3_32: - printf(", RAM 32 bit DDR3"); - break; - - default: - printf(", RAM %d(not supported)", feature_ramconfig); - break; - } - - printf(", %d carrier(s) %s", feature_carriers, - feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); - - printf(", %d video channel(s)\n", feature_video_channels); -} - int last_stage_init(void) { int slaves; unsigned int k; unsigned int mux_ch; - unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 }; + unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; u16 fpga_features; bool hw_type_cat = pca9698_get_value(0x20, 20); bool ch0_rgmii2_present = false; @@ -363,10 +134,11 @@ int last_stage_init(void) /* Turn on Parade DP501 */ pca9698_direction_output(0x20, 10, 1); + pca9698_direction_output(0x20, 11, 1); ch0_rgmii2_present = !pca9698_get_value(0x20, 30); - /* wait for FPGA done */ + /* wait for FPGA done, then reset FPGA */ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { unsigned int ctr = 0; @@ -381,6 +153,12 @@ int last_stage_init(void) break; } } + + pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); + pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); + udelay(10); + pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, + MCFPGA_RESET_N); } if (hw_type_cat) { @@ -401,8 +179,11 @@ int last_stage_init(void) slaves = mclink_probe(); mclink_fpgacount = 0; - print_fpga_info(0, ch0_rgmii2_present); + ioep_fpga_print_info(0); osd_probe(0); +#ifdef CONFIG_SYS_OSD_DH + osd_probe(4); +#endif if (slaves <= 0) return 0; @@ -412,8 +193,11 @@ int last_stage_init(void) for (k = 1; k <= slaves; ++k) { FPGA_GET_REG(k, fpga_features, &fpga_features); - print_fpga_info(k, false); + ioep_fpga_print_info(k); osd_probe(k); +#ifdef CONFIG_SYS_OSD_DH + osd_probe(k + 4); +#endif if (hw_type_cat) { miiphy_register(bb_miiphy_buses[k].name, bb_miiphy_read, bb_miiphy_write); @@ -421,32 +205,53 @@ int last_stage_init(void) } } + for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) { + i2c_set_bus_num(hrcon_fans[k].bus); + init_fan_controller(hrcon_fans[k].addr); + } + return 0; } /* - * provide access to fpga gpios (for I2C bitbang) + * provide access to fpga gpios and controls (for I2C bitbang) * (these may look all too simple but make iocon.h much more readable) */ void fpga_gpio_set(unsigned int bus, int pin) { - FPGA_SET_REG(bus, gpio.set, pin); + FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin); } void fpga_gpio_clear(unsigned int bus, int pin) { - FPGA_SET_REG(bus, gpio.clear, pin); + FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin); } int fpga_gpio_get(unsigned int bus, int pin) { u16 val; - FPGA_GET_REG(bus, gpio.read, &val); + FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val); return val & pin; } +void fpga_control_set(unsigned int bus, int pin) +{ + u16 val; + + FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val); + FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin); +} + +void fpga_control_clear(unsigned int bus, int pin) +{ + u16 val; + + FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val); + FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin); +} + void mpc8308_init(void) { pca9698_direction_output(0x20, 4, 1); diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c new file mode 100644 index 0000000..ef5b6c0 --- /dev/null +++ b/board/gdsys/mpc8308/strider.c @@ -0,0 +1,479 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <hwconfig.h> +#include <i2c.h> +#include <spi.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <pci.h> +#include <mpc83xx.h> +#include <fsl_esdhc.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_mpc83xx_serdes.h> + +#include "mpc8308.h" + +#include <gdsys_fpga.h> + +#include "../common/adv7611.h" +#include "../common/ch7301.h" +#include "../common/ioep-fpga.h" +#include "../common/mclink.h" +#include "../common/osd.h" +#include "../common/phy.h" +#include "../common/fanctrl.h" + +#include <pca953x.h> +#include <pca9698.h> + +#include <miiphy.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MAX_MUX_CHANNELS 2 + +enum { + MCFPGA_DONE = 1 << 0, + MCFPGA_INIT_N = 1 << 1, + MCFPGA_PROGRAM_N = 1 << 2, + MCFPGA_UPDATE_ENABLE_N = 1 << 3, + MCFPGA_RESET_N = 1 << 4, +}; + +enum { + GPIO_MDC = 1 << 14, + GPIO_MDIO = 1 << 15, +}; + +unsigned int mclink_fpgacount; +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; + +struct { + u8 bus; + u8 addr; +} strider_fans[] = CONFIG_STRIDER_FANS; + +int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) +{ + int res; + + switch (fpga) { + case 0: + out_le16(reg, data); + break; + default: + res = mclink_send(fpga - 1, regoff, data); + if (res < 0) { + printf("mclink_send reg %02lx data %04x returned %d\n", + regoff, data, res); + return res; + } + break; + } + + return 0; +} + +int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) +{ + int res; + + switch (fpga) { + case 0: + *data = in_le16(reg); + break; + default: + if (fpga > mclink_fpgacount) + return -EINVAL; + res = mclink_receive(fpga - 1, regoff, data); + if (res < 0) { + printf("mclink_receive reg %02lx returned %d\n", + regoff, res); + return res; + } + } + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + bool hw_type_cat = pca9698_get_value(0x20, 18); + + puts("Board: "); + + printf("Strider %s", hw_type_cat ? "CAT" : "Fiber"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + + puts("\n"); + + return 0; +} + +int last_stage_init(void) +{ + int slaves; + unsigned int k; + unsigned int mux_ch; + unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; + bool hw_type_cat = pca9698_get_value(0x20, 18); + bool ch0_sgmii2_present = false; + + /* Turn on Analog Devices ADV7611 */ + pca9698_direction_output(0x20, 8, 0); + + /* Turn on Parade DP501 */ + pca9698_direction_output(0x20, 9, 1); + + ch0_sgmii2_present = !pca9698_get_value(0x20, 37); + + /* wait for FPGA done, then reset FPGA */ + for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { + unsigned int ctr = 0; + + if (i2c_probe(mclink_controllers[k])) + continue; + + while (!(pca953x_get_val(mclink_controllers[k]) + & MCFPGA_DONE)) { + udelay(100000); + if (ctr++ > 5) { + printf("no done for mclink_controller %d\n", k); + break; + } + } + + pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); + pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); + udelay(10); + pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, + MCFPGA_RESET_N); + } + + if (hw_type_cat) { + miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, + bb_miiphy_write); + for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { + if ((mux_ch == 1) && !ch0_sgmii2_present) + continue; + + setup_88e1514(bb_miiphy_buses[0].name, mux_ch); + } + } + + /* give slave-PLLs and Parade DP501 some time to be up and running */ + udelay(500000); + + mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; + slaves = mclink_probe(); + mclink_fpgacount = 0; + + ioep_fpga_print_info(0); + + if (!adv7611_probe(0)) + printf(" Advantiv ADV7611 HDMI Receiver\n"); + +#ifdef CONFIG_STRIDER_CON + if (ioep_fpga_has_osd(0)) + osd_probe(0); +#endif + +#ifdef CONFIG_STRIDER_CPU + ch7301_probe(0, false); +#endif + + if (slaves <= 0) + return 0; + + mclink_fpgacount = slaves; + + for (k = 1; k <= slaves; ++k) { + ioep_fpga_print_info(k); +#ifdef CONFIG_STRIDER_CON + if (ioep_fpga_has_osd(k)) + osd_probe(k); +#endif +#ifdef CONFIG_STRIDER_CPU + FPGA_SET_REG(k, extended_control, 0); /* enable video in*/ + if (!adv7611_probe(k)) + printf(" Advantiv ADV7611 HDMI Receiver\n"); + ch7301_probe(k, false); +#endif + if (hw_type_cat) { + miiphy_register(bb_miiphy_buses[k].name, + bb_miiphy_read, bb_miiphy_write); + setup_88e1514(bb_miiphy_buses[k].name, 0); + } + } + + for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) { + i2c_set_bus_num(strider_fans[k].bus); + init_fan_controller(strider_fans[k].addr); + } + + return 0; +} + +/* + * provide access to fpga gpios (for I2C bitbang) + * (these may look all too simple but make iocon.h much more readable) + */ +void fpga_gpio_set(unsigned int bus, int pin) +{ + FPGA_SET_REG(bus, gpio.set, pin); +} + +void fpga_gpio_clear(unsigned int bus, int pin) +{ + FPGA_SET_REG(bus, gpio.clear, pin); +} + +int fpga_gpio_get(unsigned int bus, int pin) +{ + u16 val; + + FPGA_GET_REG(bus, gpio.read, &val); + + return val & pin; +} + +void mpc8308_init(void) +{ + pca9698_direction_output(0x20, 26, 1); +} + +void mpc8308_set_fpga_reset(unsigned state) +{ + pca9698_set_value(0x20, 26, state ? 0 : 1); +} + +void mpc8308_setup_hw(void) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + /* + * set "startup-finished"-gpios + */ + setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); + setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); +} + +int mpc8308_get_fpga_done(unsigned fpga) +{ + return pca9698_get_value(0x20, 20); +} + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_init(bd_t *bd) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + sysconf83xx_t *sysconf = &immr->sysconf; + + /* Enable cache snooping in eSDHC system configuration register */ + out_be32(&sysconf->sdhccr, 0x02000000); + + return fsl_esdhc_mmc_init(bd); +} +#endif + +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +void pci_init_board(void) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + sysconf83xx_t *sysconf = &immr->sysconf; + law83xx_t *pcie_law = sysconf->pcielaw; + struct pci_region *pcie_reg[] = { pcie_regions_0 }; + + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(1, pcie_reg); +} + +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); + + return 0; +} +#endif + +/* + * FPGA MII bitbang implementation + */ + +struct fpga_mii { + unsigned fpga; + int mdio; +} fpga_mii[] = { + { 0, 1}, + { 1, 1}, + { 2, 1}, + { 3, 1}, +}; + +static int mii_dummy_init(struct bb_miiphy_bus *bus) +{ + return 0; +} + +static int mii_mdio_active(struct bb_miiphy_bus *bus) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (fpga_mii->mdio) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); + + return 0; +} + +static int mii_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct fpga_mii *fpga_mii = bus->priv; + + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + + return 0; +} + +static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (v) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); + + fpga_mii->mdio = v; + + return 0; +} + +static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + u16 gpio; + struct fpga_mii *fpga_mii = bus->priv; + + FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); + + *v = ((gpio & GPIO_MDIO) != 0); + + return 0; +} + +static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (v) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); + + return 0; +} + +static int mii_delay(struct bb_miiphy_bus *bus) +{ + udelay(1); + + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = "board0", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[0], + }, + { + .name = "board1", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[1], + }, + { + .name = "board2", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[2], + }, + { + .name = "board3", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[3], + }, +}; + +int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / + sizeof(bb_miiphy_buses[0]); diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c index 64d90dd..2f98e47 100644 --- a/board/gdsys/p1022/controlcenterd.c +++ b/board/gdsys/p1022/controlcenterd.c @@ -57,6 +57,8 @@ struct ihs_fpga { u32 versions; /* 0x0004 */ u32 fpga_version; /* 0x0008 */ u32 fpga_features; /* 0x000c */ + u32 reserved[4]; /* 0x0010 */ + u32 control; /* 0x0020 */ }; #ifndef CONFIG_TRAILBLAZER @@ -384,6 +386,9 @@ static void hydra_initialize(void) fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + /* disable sideband clocks */ + writel(1, &fpga->control); + versions = readl(&fpga->versions); fpga_version = readl(&fpga->fpga_version); fpga_features = readl(&fpga->fpga_features); diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c index 815c9a7..1f5a586 100644 --- a/board/silica/pengwyn/board.c +++ b/board/silica/pengwyn/board.c @@ -141,12 +141,6 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - .phy_if = PHY_INTERFACE_MODE_MII, - }, - { - .slave_reg_ofs = 0x308, - .sliver_reg_ofs = 0xdc0, .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_MII, }, diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 28c29a2..79ed02f 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -317,7 +317,6 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) /* Do board-specific muxes. */ if (board_is_bone(header)) { /* Beaglebone pinmux */ - configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); #if defined(CONFIG_NAND) @@ -356,7 +355,6 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(mmc0_pin_mux_sk_evm); } else if (board_is_bone_lt(header)) { /* Beaglebone LT pinmux */ - configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); #if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT) diff --git a/common/Makefile b/common/Makefile index d986cde..d8dc892 100644 --- a/common/Makefile +++ b/common/Makefile @@ -276,10 +276,15 @@ obj-y += memsize.o obj-y += stdio.o # This option is not just y/n - it can have a numeric value +ifdef CONFIG_FASTBOOT_FLASH +obj-y += image-sparse.o ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV -obj-y += aboot.o obj-y += fb_mmc.o endif +ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV +obj-y += fb_nand.o +endif +endif obj-$(CONFIG_CMD_BLOB) += cmd_blob.o diff --git a/common/aboot.c b/common/aboot.c deleted file mode 100644 index fba8e3e..0000000 --- a/common/aboot.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Copyright (c) 2009, Google Inc. - * All rights reserved. - * - * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved. - * Portions Copyright 2014 Broadcom Corporation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of The Linux Foundation nor - * the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * NOTE: - * Although it is very similar, this license text is not identical - * to the "BSD-3-Clause", therefore, DO NOT MODIFY THIS LICENSE TEXT! - */ - -#include <config.h> -#include <common.h> -#include <aboot.h> -#include <malloc.h> -#include <part.h> -#include <sparse_format.h> - -void write_sparse_image(block_dev_desc_t *dev_desc, - disk_partition_t *info, const char *part_name, - void *data, unsigned sz) -{ - lbaint_t blk; - lbaint_t blkcnt; - lbaint_t blks; - uint32_t bytes_written = 0; - unsigned int chunk; - unsigned int chunk_data_sz; - uint32_t *fill_buf = NULL; - uint32_t fill_val; - sparse_header_t *sparse_header; - chunk_header_t *chunk_header; - uint32_t total_blocks = 0; - int i; - - /* Read and skip over sparse image header */ - sparse_header = (sparse_header_t *) data; - - data += sparse_header->file_hdr_sz; - if (sparse_header->file_hdr_sz > sizeof(sparse_header_t)) - { - /* - * Skip the remaining bytes in a header that is longer than - * we expected. - */ - data += (sparse_header->file_hdr_sz - sizeof(sparse_header_t)); - } - - debug("=== Sparse Image Header ===\n"); - debug("magic: 0x%x\n", sparse_header->magic); - debug("major_version: 0x%x\n", sparse_header->major_version); - debug("minor_version: 0x%x\n", sparse_header->minor_version); - debug("file_hdr_sz: %d\n", sparse_header->file_hdr_sz); - debug("chunk_hdr_sz: %d\n", sparse_header->chunk_hdr_sz); - debug("blk_sz: %d\n", sparse_header->blk_sz); - debug("total_blks: %d\n", sparse_header->total_blks); - debug("total_chunks: %d\n", sparse_header->total_chunks); - - /* verify sparse_header->blk_sz is an exact multiple of info->blksz */ - if (sparse_header->blk_sz != - (sparse_header->blk_sz & ~(info->blksz - 1))) { - printf("%s: Sparse image block size issue [%u]\n", - __func__, sparse_header->blk_sz); - fastboot_fail("sparse image block size issue"); - return; - } - - puts("Flashing Sparse Image\n"); - - /* Start processing chunks */ - blk = info->start; - for (chunk=0; chunk<sparse_header->total_chunks; chunk++) - { - /* Read and skip over chunk header */ - chunk_header = (chunk_header_t *) data; - data += sizeof(chunk_header_t); - - if (chunk_header->chunk_type != CHUNK_TYPE_RAW) { - debug("=== Chunk Header ===\n"); - debug("chunk_type: 0x%x\n", chunk_header->chunk_type); - debug("chunk_data_sz: 0x%x\n", chunk_header->chunk_sz); - debug("total_size: 0x%x\n", chunk_header->total_sz); - } - - if (sparse_header->chunk_hdr_sz > sizeof(chunk_header_t)) - { - /* - * Skip the remaining bytes in a header that is longer - * than we expected. - */ - data += (sparse_header->chunk_hdr_sz - - sizeof(chunk_header_t)); - } - - chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz; - blkcnt = chunk_data_sz / info->blksz; - switch (chunk_header->chunk_type) - { - case CHUNK_TYPE_RAW: - if (chunk_header->total_sz != - (sparse_header->chunk_hdr_sz + chunk_data_sz)) - { - fastboot_fail( - "Bogus chunk size for chunk type Raw"); - return; - } - - if (blk + blkcnt > info->start + info->size) { - printf( - "%s: Request would exceed partition size!\n", - __func__); - fastboot_fail( - "Request would exceed partition size!"); - return; - } - - blks = dev_desc->block_write(dev_desc->dev, blk, blkcnt, - data); - if (blks != blkcnt) { - printf("%s: Write failed " LBAFU "\n", - __func__, blks); - fastboot_fail("flash write failure"); - return; - } - blk += blkcnt; - bytes_written += blkcnt * info->blksz; - total_blocks += chunk_header->chunk_sz; - data += chunk_data_sz; - break; - - case CHUNK_TYPE_FILL: - if (chunk_header->total_sz != - (sparse_header->chunk_hdr_sz + sizeof(uint32_t))) - { - fastboot_fail( - "Bogus chunk size for chunk type FILL"); - return; - } - - fill_buf = (uint32_t *) - memalign(ARCH_DMA_MINALIGN, - ROUNDUP(info->blksz, - ARCH_DMA_MINALIGN)); - if (!fill_buf) - { - fastboot_fail( - "Malloc failed for: CHUNK_TYPE_FILL"); - return; - } - - fill_val = *(uint32_t *)data; - data = (char *) data + sizeof(uint32_t); - - for (i = 0; i < (info->blksz / sizeof(fill_val)); i++) - fill_buf[i] = fill_val; - - if (blk + blkcnt > info->start + info->size) { - printf( - "%s: Request would exceed partition size!\n", - __func__); - fastboot_fail( - "Request would exceed partition size!"); - return; - } - - for (i = 0; i < blkcnt; i++) { - blks = dev_desc->block_write(dev_desc->dev, - blk, 1, fill_buf); - if (blks != 1) { - printf( - "%s: Write failed, block # " LBAFU "\n", - __func__, blkcnt); - fastboot_fail("flash write failure"); - free(fill_buf); - return; - } - blk++; - } - bytes_written += blkcnt * info->blksz; - total_blocks += chunk_data_sz / sparse_header->blk_sz; - - free(fill_buf); - break; - - case CHUNK_TYPE_DONT_CARE: - blk += blkcnt; - total_blocks += chunk_header->chunk_sz; - break; - - case CHUNK_TYPE_CRC32: - if (chunk_header->total_sz != - sparse_header->chunk_hdr_sz) - { - fastboot_fail( - "Bogus chunk size for chunk type Dont Care"); - return; - } - total_blocks += chunk_header->chunk_sz; - data += chunk_data_sz; - break; - - default: - printf("%s: Unknown chunk type: %x\n", __func__, - chunk_header->chunk_type); - fastboot_fail("Unknown chunk type"); - return; - } - } - - debug("Wrote %d blocks, expected to write %d blocks\n", - total_blocks, sparse_header->total_blks); - printf("........ wrote %u bytes to '%s'\n", bytes_written, part_name); - - if (total_blocks != sparse_header->total_blks) - fastboot_fail("sparse image write failure"); - - fastboot_okay(""); - return; -} diff --git a/common/board_f.c b/common/board_f.c index 725eb18..ed51305 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -808,10 +808,7 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_BOARD_POSTCLK_INIT) board_postclk_init, #endif -#ifdef CONFIG_SYS_FSL_CLK - get_clocks, -#endif -#ifdef CONFIG_M68K +#if defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) get_clocks, #endif env_init, /* initialize environment */ diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c index c56fe15..e3c0297 100644 --- a/common/cmd_gpt.c +++ b/common/cmd_gpt.c @@ -218,6 +218,23 @@ static int set_gpt_info(block_dev_desc_t *dev_desc, strcpy((char *)parts[i].uuid, p); free(val); } +#ifdef CONFIG_PARTITION_TYPE_GUID + /* guid */ + val = extract_val(tok, "type"); + if (val) { + /* 'type' is optional */ + if (extract_env(val, &p)) + p = val; + if (strlen(p) >= sizeof(parts[i].type_guid)) { + printf("Wrong type guid format for partition %d\n", + i); + errno = -4; + goto err; + } + strcpy((char *)parts[i].type_guid, p); + free(val); + } +#endif /* name */ val = extract_val(tok, "name"); if (!val) { /* name is mandatory */ diff --git a/common/fb_mmc.c b/common/fb_mmc.c index 0c48cf9..b480e76 100644 --- a/common/fb_mmc.c +++ b/common/fb_mmc.c @@ -6,32 +6,24 @@ #include <config.h> #include <common.h> +#include <errno.h> +#include <fastboot.h> #include <fb_mmc.h> +#include <image-sparse.h> #include <part.h> -#include <aboot.h> #include <sparse_format.h> #include <mmc.h> +#include <div64.h> #ifndef CONFIG_FASTBOOT_GPT_NAME #define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME #endif -/* The 64 defined bytes plus the '\0' */ -#define RESPONSE_LEN (64 + 1) - static char *response_str; -void fastboot_fail(const char *s) -{ - strncpy(response_str, "FAIL\0", 5); - strncat(response_str, s, RESPONSE_LEN - 4 - 1); -} - -void fastboot_okay(const char *s) -{ - strncpy(response_str, "OKAY\0", 5); - strncat(response_str, s, RESPONSE_LEN - 4 - 1); -} +struct fb_mmc_sparse { + block_dev_desc_t *dev_desc; +}; static int get_partition_info_efi_by_name_or_alias(block_dev_desc_t *dev_desc, const char *name, disk_partition_t *info) @@ -55,6 +47,24 @@ static int get_partition_info_efi_by_name_or_alias(block_dev_desc_t *dev_desc, return ret; } + +static int fb_mmc_sparse_write(struct sparse_storage *storage, + void *priv, + unsigned int offset, + unsigned int size, + char *data) +{ + struct fb_mmc_sparse *sparse = priv; + block_dev_desc_t *dev_desc = sparse->dev_desc; + int ret; + + ret = dev_desc->block_write(dev_desc->dev, offset, size, data); + if (!ret) + return -EIO; + + return ret; +} + static void write_raw_image(block_dev_desc_t *dev_desc, disk_partition_t *info, const char *part_name, void *buffer, unsigned int download_bytes) @@ -64,11 +74,11 @@ static void write_raw_image(block_dev_desc_t *dev_desc, disk_partition_t *info, /* determine number of blocks to write */ blkcnt = ((download_bytes + (info->blksz - 1)) & ~(info->blksz - 1)); - blkcnt = blkcnt / info->blksz; + blkcnt = lldiv(blkcnt, info->blksz); if (blkcnt > info->size) { error("too large for partition: '%s'\n", part_name); - fastboot_fail("too large for partition"); + fastboot_fail(response_str, "too large for partition"); return; } @@ -78,17 +88,18 @@ static void write_raw_image(block_dev_desc_t *dev_desc, disk_partition_t *info, buffer); if (blks != blkcnt) { error("failed writing to device %d\n", dev_desc->dev); - fastboot_fail("failed writing to device"); + fastboot_fail(response_str, "failed writing to device"); return; } printf("........ wrote " LBAFU " bytes to '%s'\n", blkcnt * info->blksz, part_name); - fastboot_okay(""); + fastboot_okay(response_str, ""); } -void fb_mmc_flash_write(const char *cmd, void *download_buffer, - unsigned int download_bytes, char *response) +void fb_mmc_flash_write(const char *cmd, unsigned int session_id, + void *download_buffer, unsigned int download_bytes, + char *response) { block_dev_desc_t *dev_desc; disk_partition_t info; @@ -99,7 +110,7 @@ void fb_mmc_flash_write(const char *cmd, void *download_buffer, dev_desc = get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV); if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) { error("invalid mmc device\n"); - fastboot_fail("invalid mmc device"); + fastboot_fail(response_str, "invalid mmc device"); return; } @@ -109,29 +120,47 @@ void fb_mmc_flash_write(const char *cmd, void *download_buffer, if (is_valid_gpt_buf(dev_desc, download_buffer)) { printf("%s: invalid GPT - refusing to write to flash\n", __func__); - fastboot_fail("invalid GPT partition"); + fastboot_fail(response_str, "invalid GPT partition"); return; } if (write_mbr_and_gpt_partitions(dev_desc, download_buffer)) { printf("%s: writing GPT partitions failed\n", __func__); - fastboot_fail("writing GPT partitions failed"); + fastboot_fail(response_str, + "writing GPT partitions failed"); return; } printf("........ success\n"); - fastboot_okay(""); + fastboot_okay(response_str, ""); return; } else if (get_partition_info_efi_by_name_or_alias(dev_desc, cmd, &info)) { error("cannot find partition: '%s'\n", cmd); - fastboot_fail("cannot find partition"); + fastboot_fail(response_str, "cannot find partition"); return; } - if (is_sparse_image(download_buffer)) - write_sparse_image(dev_desc, &info, cmd, download_buffer, - download_bytes); - else + if (is_sparse_image(download_buffer)) { + struct fb_mmc_sparse sparse_priv; + sparse_storage_t sparse; + + sparse_priv.dev_desc = dev_desc; + + sparse.block_sz = info.blksz; + sparse.start = info.start; + sparse.size = info.size; + sparse.name = cmd; + sparse.write = fb_mmc_sparse_write; + + printf("Flashing sparse image at offset " LBAFU "\n", + info.start); + + store_sparse_image(&sparse, &sparse_priv, session_id, + download_buffer); + } else { write_raw_image(dev_desc, &info, cmd, download_buffer, download_bytes); + } + + fastboot_okay(response_str, ""); } void fb_mmc_erase(const char *cmd, char *response) @@ -144,7 +173,7 @@ void fb_mmc_erase(const char *cmd, char *response) if (mmc == NULL) { error("invalid mmc device"); - fastboot_fail("invalid mmc device"); + fastboot_fail(response_str, "invalid mmc device"); return; } @@ -154,14 +183,14 @@ void fb_mmc_erase(const char *cmd, char *response) dev_desc = get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV); if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) { error("invalid mmc device"); - fastboot_fail("invalid mmc device"); + fastboot_fail(response_str, "invalid mmc device"); return; } ret = get_partition_info_efi_by_name_or_alias(dev_desc, cmd, &info); if (ret) { error("cannot find partition: '%s'", cmd); - fastboot_fail("cannot find partition"); + fastboot_fail(response_str, "cannot find partition"); return; } @@ -180,11 +209,11 @@ void fb_mmc_erase(const char *cmd, char *response) blks = dev_desc->block_erase(dev_desc->dev, blks_start, blks_size); if (blks != blks_size) { error("failed erasing from device %d", dev_desc->dev); - fastboot_fail("failed erasing from device"); + fastboot_fail(response_str, "failed erasing from device"); return; } printf("........ erased " LBAFU " bytes from '%s'\n", blks_size * info.blksz, cmd); - fastboot_okay(""); + fastboot_okay(response_str, ""); } diff --git a/common/fb_nand.c b/common/fb_nand.c new file mode 100644 index 0000000..9ca8602 --- /dev/null +++ b/common/fb_nand.c @@ -0,0 +1,213 @@ +/* + * Copyright 2014 Broadcom Corporation. + * Copyright 2015 Free Electrons. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> + +#include <fastboot.h> +#include <image-sparse.h> +#include <sparse_format.h> + +#include <linux/mtd/mtd.h> +#include <jffs2/jffs2.h> +#include <nand.h> + +static char *response_str; + +struct fb_nand_sparse { + nand_info_t *nand; + struct part_info *part; +}; + +__weak int board_fastboot_erase_partition_setup(char *name) +{ + return 0; +} + +__weak int board_fastboot_write_partition_setup(char *name) +{ + return 0; +} + +static int fb_nand_lookup(const char *partname, char *response, + nand_info_t **nand, + struct part_info **part) +{ + struct mtd_device *dev; + int ret; + u8 pnum; + + ret = mtdparts_init(); + if (ret) { + error("Cannot initialize MTD partitions\n"); + fastboot_fail(response_str, "cannot init mtdparts"); + return ret; + } + + ret = find_dev_and_part(partname, &dev, &pnum, part); + if (ret) { + error("cannot find partition: '%s'", partname); + fastboot_fail(response_str, "cannot find partition"); + return ret; + } + + if (dev->id->type != MTD_DEV_TYPE_NAND) { + error("partition '%s' is not stored on a NAND device", + partname); + fastboot_fail(response_str, "not a NAND device"); + return -EINVAL; + } + + *nand = &nand_info[dev->id->num]; + + return 0; +} + +static int _fb_nand_erase(nand_info_t *nand, struct part_info *part) +{ + nand_erase_options_t opts; + int ret; + + memset(&opts, 0, sizeof(opts)); + opts.offset = part->offset; + opts.length = part->size; + opts.quiet = 1; + + printf("Erasing blocks 0x%llx to 0x%llx\n", + part->offset, part->offset + part->size); + + ret = nand_erase_opts(nand, &opts); + if (ret) + return ret; + + printf("........ erased 0x%llx bytes from '%s'\n", + part->size, part->name); + + return 0; +} + +static int _fb_nand_write(nand_info_t *nand, struct part_info *part, + void *buffer, unsigned int offset, + unsigned int length, size_t *written) +{ + int flags = WITH_WR_VERIFY; + +#ifdef CONFIG_FASTBOOT_FLASH_NAND_TRIMFFS + flags |= WITH_DROP_FFS; +#endif + + return nand_write_skip_bad(nand, offset, &length, written, + part->size - (offset - part->offset), + buffer, flags); +} + +static int fb_nand_sparse_write(struct sparse_storage *storage, + void *priv, + unsigned int offset, + unsigned int size, + char *data) +{ + struct fb_nand_sparse *sparse = priv; + size_t written; + int ret; + + ret = _fb_nand_write(sparse->nand, sparse->part, data, + offset * storage->block_sz, + size * storage->block_sz, &written); + if (ret < 0) { + printf("Failed to write sparse chunk\n"); + return ret; + } + + return written / storage->block_sz; +} + +void fb_nand_flash_write(const char *partname, unsigned int session_id, + void *download_buffer, unsigned int download_bytes, + char *response) +{ + struct part_info *part; + nand_info_t *nand = NULL; + int ret; + + /* initialize the response buffer */ + response_str = response; + + ret = fb_nand_lookup(partname, response, &nand, &part); + if (ret) { + error("invalid NAND device"); + fastboot_fail(response_str, "invalid NAND device"); + return; + } + + ret = board_fastboot_write_partition_setup(part->name); + if (ret) + return; + + if (is_sparse_image(download_buffer)) { + struct fb_nand_sparse sparse_priv; + sparse_storage_t sparse; + + sparse_priv.nand = nand; + sparse_priv.part = part; + + sparse.block_sz = nand->writesize; + sparse.start = part->offset / sparse.block_sz; + sparse.size = part->size / sparse.block_sz; + sparse.name = part->name; + sparse.write = fb_nand_sparse_write; + + ret = store_sparse_image(&sparse, &sparse_priv, session_id, + download_buffer); + } else { + printf("Flashing raw image at offset 0x%llx\n", + part->offset); + + ret = _fb_nand_write(nand, part, download_buffer, part->offset, + download_bytes, NULL); + + printf("........ wrote %u bytes to '%s'\n", + download_bytes, part->name); + } + + if (ret) { + fastboot_fail(response_str, "error writing the image"); + return; + } + + fastboot_okay(response_str, ""); +} + +void fb_nand_erase(const char *partname, char *response) +{ + struct part_info *part; + nand_info_t *nand = NULL; + int ret; + + /* initialize the response buffer */ + response_str = response; + + ret = fb_nand_lookup(partname, response, &nand, &part); + if (ret) { + error("invalid NAND device"); + fastboot_fail(response_str, "invalid NAND device"); + return; + } + + ret = board_fastboot_erase_partition_setup(part->name); + if (ret) + return; + + ret = _fb_nand_erase(nand, part); + if (ret) { + error("failed erasing from device %s", nand->name); + fastboot_fail(response_str, "failed erasing from device"); + return; + } + + fastboot_okay(response_str, ""); +} diff --git a/common/image-sparse.c b/common/image-sparse.c new file mode 100644 index 0000000..dffe844 --- /dev/null +++ b/common/image-sparse.c @@ -0,0 +1,393 @@ +/* + * Copyright (c) 2009, Google Inc. + * All rights reserved. + * + * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved. + * Portions Copyright 2014 Broadcom Corporation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of The Linux Foundation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * NOTE: + * Although it is very similar, this license text is not identical + * to the "BSD-3-Clause", therefore, DO NOT MODIFY THIS LICENSE TEXT! + */ + +#include <config.h> +#include <common.h> +#include <div64.h> +#include <errno.h> +#include <image-sparse.h> +#include <malloc.h> +#include <part.h> +#include <sparse_format.h> + +#include <linux/math64.h> + +typedef struct sparse_buffer { + void *data; + u32 length; + u32 repeat; + u16 type; +} sparse_buffer_t; + +static uint32_t last_offset; + +static unsigned int sparse_get_chunk_data_size(sparse_header_t *sparse, + chunk_header_t *chunk) +{ + return chunk->total_sz - sparse->chunk_hdr_sz; +} + +static unsigned int sparse_block_size_to_storage(unsigned int size, + sparse_storage_t *storage, + sparse_header_t *sparse) +{ + return size * sparse->blk_sz / storage->block_sz; +} + +static bool sparse_chunk_has_buffer(chunk_header_t *chunk) +{ + switch (chunk->chunk_type) { + case CHUNK_TYPE_RAW: + case CHUNK_TYPE_FILL: + return true; + + default: + return false; + } +} + +static sparse_header_t *sparse_parse_header(void **data) +{ + /* Read and skip over sparse image header */ + sparse_header_t *sparse_header = (sparse_header_t *) *data; + + *data += sparse_header->file_hdr_sz; + + debug("=== Sparse Image Header ===\n"); + debug("magic: 0x%x\n", sparse_header->magic); + debug("major_version: 0x%x\n", sparse_header->major_version); + debug("minor_version: 0x%x\n", sparse_header->minor_version); + debug("file_hdr_sz: %d\n", sparse_header->file_hdr_sz); + debug("chunk_hdr_sz: %d\n", sparse_header->chunk_hdr_sz); + debug("blk_sz: %d\n", sparse_header->blk_sz); + debug("total_blks: %d\n", sparse_header->total_blks); + debug("total_chunks: %d\n", sparse_header->total_chunks); + + return sparse_header; +} + +static int sparse_parse_fill_chunk(sparse_header_t *sparse, + chunk_header_t *chunk) +{ + unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk); + + if (chunk_data_sz != sizeof(uint32_t)) + return -EINVAL; + + return 0; +} + +static int sparse_parse_raw_chunk(sparse_header_t *sparse, + chunk_header_t *chunk) +{ + unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk); + + /* Check if the data size is a multiple of the main block size */ + if (chunk_data_sz % sparse->blk_sz) + return -EINVAL; + + /* Check that the chunk size is consistent */ + if ((chunk_data_sz / sparse->blk_sz) != chunk->chunk_sz) + return -EINVAL; + + return 0; +} + +static chunk_header_t *sparse_parse_chunk(sparse_header_t *sparse, + void **image) +{ + chunk_header_t *chunk = (chunk_header_t *) *image; + int ret; + + debug("=== Chunk Header ===\n"); + debug("chunk_type: 0x%x\n", chunk->chunk_type); + debug("chunk_data_sz: 0x%x\n", chunk->chunk_sz); + debug("total_size: 0x%x\n", chunk->total_sz); + + switch (chunk->chunk_type) { + case CHUNK_TYPE_RAW: + ret = sparse_parse_raw_chunk(sparse, chunk); + if (ret) + return NULL; + break; + + case CHUNK_TYPE_FILL: + ret = sparse_parse_fill_chunk(sparse, chunk); + if (ret) + return NULL; + break; + + case CHUNK_TYPE_DONT_CARE: + case CHUNK_TYPE_CRC32: + debug("Ignoring chunk\n"); + break; + + default: + printf("%s: Unknown chunk type: %x\n", __func__, + chunk->chunk_type); + return NULL; + } + + *image += sparse->chunk_hdr_sz; + + return chunk; +} + +static int sparse_get_fill_buffer(sparse_header_t *sparse, + chunk_header_t *chunk, + sparse_buffer_t *buffer, + unsigned int blk_sz, + void *data) +{ + int i; + + buffer->type = CHUNK_TYPE_FILL; + + /* + * We create a buffer of one block, and ask it to be + * repeated as many times as needed. + */ + buffer->length = blk_sz; + buffer->repeat = (chunk->chunk_sz * sparse->blk_sz) / blk_sz; + + buffer->data = memalign(ARCH_DMA_MINALIGN, + ROUNDUP(blk_sz, + ARCH_DMA_MINALIGN)); + if (!buffer->data) + return -ENOMEM; + + for (i = 0; i < (buffer->length / sizeof(uint32_t)); i++) + ((uint32_t *)buffer->data)[i] = *(uint32_t *)(data); + + return 0; +} + +static int sparse_get_raw_buffer(sparse_header_t *sparse, + chunk_header_t *chunk, + sparse_buffer_t *buffer, + unsigned int blk_sz, + void *data) +{ + unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk); + + buffer->type = CHUNK_TYPE_RAW; + buffer->length = chunk_data_sz; + buffer->data = data; + buffer->repeat = 1; + + return 0; +} + +static sparse_buffer_t *sparse_get_data_buffer(sparse_header_t *sparse, + chunk_header_t *chunk, + unsigned int blk_sz, + void **image) +{ + unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk); + sparse_buffer_t *buffer; + void *data = *image; + int ret; + + *image += chunk_data_sz; + + if (!sparse_chunk_has_buffer(chunk)) + return NULL; + + buffer = calloc(sizeof(sparse_buffer_t), 1); + if (!buffer) + return NULL; + + switch (chunk->chunk_type) { + case CHUNK_TYPE_RAW: + ret = sparse_get_raw_buffer(sparse, chunk, buffer, blk_sz, + data); + if (ret) + return NULL; + break; + + case CHUNK_TYPE_FILL: + ret = sparse_get_fill_buffer(sparse, chunk, buffer, blk_sz, + data); + if (ret) + return NULL; + break; + + default: + return NULL; + } + + debug("=== Buffer ===\n"); + debug("length: 0x%x\n", buffer->length); + debug("repeat: 0x%x\n", buffer->repeat); + debug("type: 0x%x\n", buffer->type); + debug("data: 0x%p\n", buffer->data); + + return buffer; +} + +static void sparse_put_data_buffer(sparse_buffer_t *buffer) +{ + if (buffer->type == CHUNK_TYPE_FILL) + free(buffer->data); + + free(buffer); +} + +int store_sparse_image(sparse_storage_t *storage, void *storage_priv, + unsigned int session_id, void *data) +{ + unsigned int chunk, offset; + sparse_header_t *sparse_header; + chunk_header_t *chunk_header; + sparse_buffer_t *buffer; + uint32_t start; + uint32_t total_blocks = 0; + uint32_t skipped = 0; + int i; + + debug("=== Storage ===\n"); + debug("name: %s\n", storage->name); + debug("block_size: 0x%x\n", storage->block_sz); + debug("start: 0x%x\n", storage->start); + debug("size: 0x%x\n", storage->size); + debug("write: 0x%p\n", storage->write); + debug("priv: 0x%p\n", storage_priv); + + sparse_header = sparse_parse_header(&data); + if (!sparse_header) { + printf("sparse header issue\n"); + return -EINVAL; + } + + /* + * Verify that the sparse block size is a multiple of our + * storage backend block size + */ + div_u64_rem(sparse_header->blk_sz, storage->block_sz, &offset); + if (offset) { + printf("%s: Sparse image block size issue [%u]\n", + __func__, sparse_header->blk_sz); + return -EINVAL; + } + + /* + * If it's a new flashing session, start at the beginning of + * the partition. If not, then simply resume where we were. + */ + if (session_id > 0) + start = last_offset; + else + start = storage->start; + + printf("Flashing sparse image on partition %s at offset 0x%x (ID: %d)\n", + storage->name, start * storage->block_sz, session_id); + + /* Start processing chunks */ + for (chunk = 0; chunk < sparse_header->total_chunks; chunk++) { + uint32_t blkcnt; + + chunk_header = sparse_parse_chunk(sparse_header, &data); + if (!chunk_header) { + printf("Unknown chunk type"); + return -EINVAL; + } + + /* + * If we have a DONT_CARE type, just skip the blocks + * and go on parsing the rest of the chunks + */ + if (chunk_header->chunk_type == CHUNK_TYPE_DONT_CARE) { + skipped += sparse_block_size_to_storage(chunk_header->chunk_sz, + storage, + sparse_header); + continue; + } + + /* Retrieve the buffer we're going to write */ + buffer = sparse_get_data_buffer(sparse_header, chunk_header, + storage->block_sz, &data); + if (!buffer) + continue; + + blkcnt = (buffer->length / storage->block_sz) * buffer->repeat; + + if ((start + total_blocks + blkcnt) > + (storage->start + storage->size)) { + printf("%s: Request would exceed partition size!\n", + __func__); + return -EINVAL; + } + + for (i = 0; i < buffer->repeat; i++) { + unsigned long buffer_blk_cnt; + int ret; + + buffer_blk_cnt = buffer->length / storage->block_sz; + + ret = storage->write(storage, storage_priv, + start + total_blocks, + buffer_blk_cnt, + buffer->data); + if (ret < 0) { + printf("%s: Write %d failed %d\n", + __func__, i, ret); + return ret; + } + + total_blocks += ret; + } + + sparse_put_data_buffer(buffer); + } + + debug("Wrote %d blocks, skipped %d, expected to write %d blocks\n", + total_blocks, skipped, + sparse_block_size_to_storage(sparse_header->total_blks, + storage, sparse_header)); + printf("........ wrote %d blocks to '%s'\n", total_blocks, + storage->name); + + if ((total_blocks + skipped) != + sparse_block_size_to_storage(sparse_header->total_blks, + storage, sparse_header)) { + printf("sparse image write failure\n"); + return -EIO; + } + + last_offset = start + total_blocks; + + return 0; +} diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 34bf4ea..390803a 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -4,6 +4,7 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_EMR1=0 CONFIG_MMC0_CD_PIN="PG0" +CONFIG_USB0_VBUS_DET="PG1" CONFIG_USB1_VBUS_PIN="PG11" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set @@ -11,6 +12,8 @@ CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_PWM="PB2" +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_MUSB_GADGET=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index efe2317..bb9c42a 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -14,3 +14,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)" # CONFIG_CMD_FPGA is not set CONFIG_ETH_DESIGNWARE=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB0_ID_DET="PH19" +CONFIG_USB0_VBUS_DET="PH22" +CONFIG_USB0_VBUS_PIN="PH17" +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_MUSB_GADGET=y diff --git a/configs/bct-brettl2_defconfig b/configs/bct-brettl2_defconfig index 9e6f1ee..efcfe4d 100644 --- a/configs/bct-brettl2_defconfig +++ b/configs/bct-brettl2_defconfig @@ -2,4 +2,3 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BCT_BRETTL2=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf526-ezbrd_defconfig b/configs/bf526-ezbrd_defconfig index c8dab57..624484c 100644 --- a/configs/bf526-ezbrd_defconfig +++ b/configs/bf526-ezbrd_defconfig @@ -3,4 +3,3 @@ CONFIG_TARGET_BF526_EZBRD=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y -CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig index 74f352e..ad29088 100644 --- a/configs/bf527-ezkit-v2_defconfig +++ b/configs/bf527-ezkit-v2_defconfig @@ -3,5 +3,4 @@ CONFIG_TARGET_BF527_EZKIT=y CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1" # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y -CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y CONFIG_LIB_RAND=y diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig index 0cc81cc..8752267 100644 --- a/configs/bf527-ezkit_defconfig +++ b/configs/bf527-ezkit_defconfig @@ -3,5 +3,4 @@ CONFIG_TARGET_BF527_EZKIT=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y -CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y CONFIG_NET_TFTP_VARS=n diff --git a/configs/bf537-stamp_defconfig b/configs/bf537-stamp_defconfig index 294d0d9..a60c1b7 100644 --- a/configs/bf537-stamp_defconfig +++ b/configs/bf537-stamp_defconfig @@ -3,4 +3,3 @@ CONFIG_TARGET_BF537_STAMP=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y -CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf538f-ezkit_defconfig b/configs/bf538f-ezkit_defconfig index 668f9cb..0edaae5 100644 --- a/configs/bf538f-ezkit_defconfig +++ b/configs/bf538f-ezkit_defconfig @@ -1,6 +1,5 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF538F_EZKIT=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y # CONFIG_REGEX is not set CONFIG_LIB_RAND=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig new file mode 100644 index 0000000..a059dd9 --- /dev/null +++ b/configs/hrcon_dh_defconfig @@ -0,0 +1,5 @@ +CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH" + +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_HRCON=y diff --git a/configs/kwb_defconfig b/configs/kwb_defconfig index f82fcf3..0bbe0a7 100644 --- a/configs/kwb_defconfig +++ b/configs/kwb_defconfig @@ -3,6 +3,9 @@ CONFIG_TARGET_KWB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# " +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_GO is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig new file mode 100644 index 0000000..74ef69e --- /dev/null +++ b/configs/strider_con_defconfig @@ -0,0 +1,7 @@ +CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_STRIDER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " +# CONFIG_CMD_SETEXPR is not set diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig new file mode 100644 index 0000000..fc0a823 --- /dev/null +++ b/configs/strider_cpu_defconfig @@ -0,0 +1,7 @@ +CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU" +CONFIG_PPC=y +CONFIG_MPC83xx=y +CONFIG_TARGET_STRIDER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " +# CONFIG_CMD_SETEXPR is not set diff --git a/disk/part.c b/disk/part.c index e57a252..909712e 100644 --- a/disk/part.c +++ b/disk/part.c @@ -392,6 +392,9 @@ int get_partition_info(block_dev_desc_t *dev_desc, int part, /* The common case is no UUID support */ info->uuid[0] = 0; #endif +#ifdef CONFIG_PARTITION_TYPE_GUID + info->type_guid[0] = 0; +#endif switch (dev_desc->part_type) { #ifdef CONFIG_MAC_PARTITION @@ -532,6 +535,9 @@ int get_device_and_partition(const char *ifname, const char *dev_part_str, #ifdef CONFIG_PARTITION_UUIDS info->uuid[0] = 0; #endif +#ifdef CONFIG_PARTITION_TYPE_GUID + info->type_guid[0] = 0; +#endif return 0; } @@ -639,6 +645,9 @@ int get_device_and_partition(const char *ifname, const char *dev_part_str, #ifdef CONFIG_PARTITION_UUIDS info->uuid[0] = 0; #endif +#ifdef CONFIG_PARTITION_TYPE_GUID + info->type_guid[0] = 0; +#endif ret = 0; goto cleanup; diff --git a/disk/part_efi.c b/disk/part_efi.c index 15627f2..ea9c615 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -223,6 +223,10 @@ void print_part_efi(block_dev_desc_t * dev_desc) uuid_bin = (unsigned char *)gpt_pte[i].partition_type_guid.b; uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID); printf("\ttype:\t%s\n", uuid); +#ifdef CONFIG_PARTITION_TYPE_GUID + if (!uuid_guid_get_str(uuid_bin, uuid)) + printf("\ttype:\t%s\n", uuid); +#endif uuid_bin = (unsigned char *)gpt_pte[i].unique_partition_guid.b; uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID); printf("\tguid:\t%s\n", uuid); @@ -283,6 +287,10 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid, UUID_STR_FORMAT_GUID); #endif +#ifdef CONFIG_PARTITION_TYPE_GUID + uuid_bin_to_str(gpt_pte[part - 1].partition_type_guid.b, + info->type_guid, UUID_STR_FORMAT_GUID); +#endif debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s\n", __func__, info->start, info->size, info->name); @@ -419,6 +427,10 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e, char *str_uuid; unsigned char *bin_uuid; #endif +#ifdef CONFIG_PARTITION_TYPE_GUID + char *str_type_guid; + unsigned char *bin_type_guid; +#endif for (i = 0; i < parts; i++) { /* partition starting lba */ @@ -445,9 +457,26 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e, else gpt_e[i].ending_lba = cpu_to_le64(offset - 1); +#ifdef CONFIG_PARTITION_TYPE_GUID + str_type_guid = partitions[i].type_guid; + bin_type_guid = gpt_e[i].partition_type_guid.b; + if (strlen(str_type_guid)) { + if (uuid_str_to_bin(str_type_guid, bin_type_guid, + UUID_STR_FORMAT_GUID)) { + printf("Partition no. %d: invalid type guid: %s\n", + i, str_type_guid); + return -1; + } + } else { + /* default partition type GUID */ + memcpy(bin_type_guid, + &PARTITION_BASIC_DATA_GUID, 16); + } +#else /* partition type GUID */ memcpy(gpt_e[i].partition_type_guid.b, &PARTITION_BASIC_DATA_GUID, 16); +#endif #ifdef CONFIG_PARTITION_UUIDS str_uuid = partitions[i].uuid; diff --git a/doc/README.gpt b/doc/README.gpt index 59fdeeb..35902ce 100644 --- a/doc/README.gpt +++ b/doc/README.gpt @@ -31,7 +31,8 @@ More often UUID is displayed as 32 hexadecimal digits, in 5 groups, separated by hyphens, in the form 8-4-4-4-12 for a total of 36 characters (32 digits and 4 hyphens) -For instance, GUID of Linux data partition: EBD0A0A2-B9E5-4433-87C0-68B6B72699C7 +For instance, GUID of Basic data partition: EBD0A0A2-B9E5-4433-87C0-68B6B72699C7 +and GUID of Linux filesystem data: 0FC63DAF-8483-4772-8E79-3D69D8477DE4 Historically there are 5 methods to generate this number. The oldest one is combining machine's MAC address and timer (epoch) value. @@ -170,6 +171,43 @@ To restore GUID partition table one needs to: 2. From u-boot prompt type: gpt write mmc 0 $partitions +Partition type GUID: +==================== + +For created partition, the used partition type GUID is +PARTITION_BASIC_DATA_GUID (EBD0A0A2-B9E5-4433-87C0-68B6B72699C7). + +If you define 'CONFIG_PARTITION_TYPE_GUID', a optionnal parameter 'type' +can specify a other partition type guid: + + "partitions=uuid_disk=...;name=u-boot,size=60MiB,uuid=...; + name=kernel,size=60MiB,uuid=..., + type=0FC63DAF-8483-4772-8E79-3D69D8477DE4;" + +Some strings can be also used at the place of known GUID : + "system" = PARTITION_SYSTEM_GUID + (C12A7328-F81F-11D2-BA4B-00A0C93EC93B) + "mbr" = LEGACY_MBR_PARTITION_GUID + (024DEE41-33E7-11D3-9D69-0008C781F39F) + "msft" = PARTITION_MSFT_RESERVED_GUID + (E3C9E316-0B5C-4DB8-817D-F92DF00215AE) + "data" = PARTITION_BASIC_DATA_GUID + (EBD0A0A2-B9E5-4433-87C0-68B6B72699C7) + "linux" = PARTITION_LINUX_FILE_SYSTEM_DATA_GUID + (0FC63DAF-8483-4772-8E79-3D69D8477DE4) + "raid" = PARTITION_LINUX_RAID_GUID + (A19D880F-05FC-4D3B-A006-743F0F84911E) + "swap" = PARTITION_LINUX_SWAP_GUID + (0657FD6D-A4AB-43C4-84E5-0933C84B4F4F) + "lvm" = PARTITION_LINUX_LVM_GUID + (E6D6D379-F507-44C2-A23C-238F2A3DF928) + + "partitions=uuid_disk=...;name=u-boot,size=60MiB,uuid=...; + name=kernel,size=60MiB,uuid=...,type=linux;" + +They are also used to display the type of partition in "part list" command. + + Useful info: ============ diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 82c6843..1ad638e 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -485,36 +485,6 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) #endif } - -#ifdef CONFIG_AHCI_SETFEATURES_XFER -static void ahci_set_feature(u8 port) -{ - struct ahci_ioports *pp = &(probe_ent->port[port]); - void __iomem *port_mmio = pp->port_mmio; - u32 cmd_fis_len = 5; /* five dwords */ - u8 fis[20]; - - /* set feature */ - memset(fis, 0, sizeof(fis)); - fis[0] = 0x27; - fis[1] = 1 << 7; - fis[2] = ATA_CMD_SET_FEATURES; - fis[3] = SETFEATURES_XFER; - fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; - - memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis)); - ahci_fill_cmd_slot(pp, cmd_fis_len); - ahci_dcache_flush_sata_cmd(pp); - writel(1, port_mmio + PORT_CMD_ISSUE); - readl(port_mmio + PORT_CMD_ISSUE); - - if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, - WAIT_MS_DATAIO, 0x1)) { - printf("set feature error on port %d!\n", port); - } -} -#endif - static int wait_spinup(void __iomem *port_mmio) { ulong start; @@ -956,9 +926,6 @@ void scsi_low_level_init(int busdevfunc) printf("Can not start port %d\n", i); continue; } -#ifdef CONFIG_AHCI_SETFEATURES_XFER - ahci_set_feature((u8) i); -#endif } } } @@ -1002,9 +969,6 @@ int ahci_init(void __iomem *base) printf("Can not start port %d\n", i); continue; } -#ifdef CONFIG_AHCI_SETFEATURES_XFER - ahci_set_feature((u8) i); -#endif } } err_out: diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index 7371cd4..c8c8637 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -88,8 +88,10 @@ static int pca953x_reg_write(uint8_t chip, uint addr, uint mask, uint data) if (i2c_read(chip, addr << 1, 1, (u8*)&valw, 2)) return -1; + valw = le16_to_cpu(valw); valw &= ~mask; valw |= data; + valw = cpu_to_le16(valw); return i2c_write(chip, addr << 1, 1, (u8*)&valw, 2); } @@ -107,7 +109,7 @@ static int pca953x_reg_read(uint8_t chip, uint addr, uint *data) } else { if (i2c_read(chip, addr << 1, 1, (u8*)&valw, 2)) return -1; - *data = (int)valw; + *data = (uint)le16_to_cpu(valw); } return 0; } diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c index 19fbe59..b05c15f 100644 --- a/drivers/i2c/ihs_i2c.c +++ b/drivers/i2c/ihs_i2c.c @@ -11,6 +11,32 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SYS_I2C_IHS_DUAL +#define I2C_SET_REG(fld, val) \ + do { \ + if (I2C_ADAP_HWNR & 0x10) \ + FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \ + else \ + FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \ + } while (0) +#else +#define I2C_SET_REG(fld, val) \ + FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val) +#endif + +#ifdef CONFIG_SYS_I2C_IHS_DUAL +#define I2C_GET_REG(fld, val) \ + do { \ + if (I2C_ADAP_HWNR & 0x10) \ + FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \ + else \ + FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \ + } while (0) +#else +#define I2C_GET_REG(fld, val) \ + FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val) +#endif + enum { I2CINT_ERROR_EV = 1 << 13, I2CINT_TRANSMIT_EV = 1 << 14, @@ -29,14 +55,14 @@ static int wait_for_int(bool read) u16 val; unsigned int ctr = 0; - FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val); + I2C_GET_REG(interrupt_status, &val); while (!(val & (I2CINT_ERROR_EV | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) { udelay(10); if (ctr++ > 5000) { return 1; } - FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val); + I2C_GET_REG(interrupt_status, &val); } return (val & I2CINT_ERROR_EV) ? 1 : 0; @@ -47,30 +73,30 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, { u16 val; - FPGA_SET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, I2CINT_ERROR_EV + I2C_SET_REG(interrupt_status, I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV); - FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val); + I2C_GET_REG(interrupt_status, &val); if (!read && len) { val = buffer[0]; if (len > 1) val |= buffer[1] << 8; - FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox_ext, val); + I2C_SET_REG(write_mailbox_ext, val); } - FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox, - I2CMB_NATIVE - | (read ? 0 : I2CMB_WRITE) - | (chip << 1) - | ((len > 1) ? I2CMB_2BYTE : 0) - | (is_last ? 0 : I2CMB_HOLD_BUS)); + I2C_SET_REG(write_mailbox, + I2CMB_NATIVE + | (read ? 0 : I2CMB_WRITE) + | (chip << 1) + | ((len > 1) ? I2CMB_2BYTE : 0) + | (is_last ? 0 : I2CMB_HOLD_BUS)); if (wait_for_int(read)) return 1; if (read) { - FPGA_GET_REG(I2C_ADAP_HWNR, i2c.read_mailbox_ext, &val); + I2C_GET_REG(read_mailbox_ext, &val); buffer[0] = val & 0xff; if (len > 1) buffer[1] = val >> 8; @@ -109,7 +135,7 @@ static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, uint addr, if (len <= 0) return 1; - if (ihs_i2c_address(chip, addr, alen, !read)) + if (ihs_i2c_address(chip, addr, alen, len)) return 1; while (len) { @@ -163,7 +189,7 @@ static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, } static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap, - unsigned int speed) + unsigned int speed) { if (speed != adap->speed) return 1; @@ -179,6 +205,13 @@ U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe, ihs_i2c_set_bus_speed, CONFIG_SYS_I2C_IHS_SPEED_0, CONFIG_SYS_I2C_IHS_SLAVE_0, 0) +#ifdef CONFIG_SYS_I2C_IHS_DUAL +U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe, + ihs_i2c_read, ihs_i2c_write, + ihs_i2c_set_bus_speed, + CONFIG_SYS_I2C_IHS_SPEED_0_1, + CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16) +#endif #endif #ifdef CONFIG_SYS_I2C_IHS_CH1 U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe, @@ -186,6 +219,13 @@ U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe, ihs_i2c_set_bus_speed, CONFIG_SYS_I2C_IHS_SPEED_1, CONFIG_SYS_I2C_IHS_SLAVE_1, 1) +#ifdef CONFIG_SYS_I2C_IHS_DUAL +U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe, + ihs_i2c_read, ihs_i2c_write, + ihs_i2c_set_bus_speed, + CONFIG_SYS_I2C_IHS_SPEED_1_1, + CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17) +#endif #endif #ifdef CONFIG_SYS_I2C_IHS_CH2 U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe, @@ -193,6 +233,13 @@ U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe, ihs_i2c_set_bus_speed, CONFIG_SYS_I2C_IHS_SPEED_2, CONFIG_SYS_I2C_IHS_SLAVE_2, 2) +#ifdef CONFIG_SYS_I2C_IHS_DUAL +U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe, + ihs_i2c_read, ihs_i2c_write, + ihs_i2c_set_bus_speed, + CONFIG_SYS_I2C_IHS_SPEED_2_1, + CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18) +#endif #endif #ifdef CONFIG_SYS_I2C_IHS_CH3 U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe, @@ -200,4 +247,11 @@ U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe, ihs_i2c_set_bus_speed, CONFIG_SYS_I2C_IHS_SPEED_3, CONFIG_SYS_I2C_IHS_SLAVE_3, 3) +#ifdef CONFIG_SYS_I2C_IHS_DUAL +U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe, + ihs_i2c_read, ihs_i2c_write, + ihs_i2c_set_bus_speed, + CONFIG_SYS_I2C_IHS_SPEED_3_1, + CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19) +#endif #endif diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index db9b402..05bf4d4 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -448,28 +448,84 @@ static int soft_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, /* * Register soft i2c adapters */ -U_BOOT_I2C_ADAP_COMPLETE(soft0, soft_i2c_init, soft_i2c_probe, +U_BOOT_I2C_ADAP_COMPLETE(soft00, soft_i2c_init, soft_i2c_probe, soft_i2c_read, soft_i2c_write, NULL, CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE, 0) #if defined(I2C_SOFT_DECLARATIONS2) -U_BOOT_I2C_ADAP_COMPLETE(soft1, soft_i2c_init, soft_i2c_probe, +U_BOOT_I2C_ADAP_COMPLETE(soft01, soft_i2c_init, soft_i2c_probe, soft_i2c_read, soft_i2c_write, NULL, CONFIG_SYS_I2C_SOFT_SPEED_2, CONFIG_SYS_I2C_SOFT_SLAVE_2, 1) #endif #if defined(I2C_SOFT_DECLARATIONS3) -U_BOOT_I2C_ADAP_COMPLETE(soft2, soft_i2c_init, soft_i2c_probe, +U_BOOT_I2C_ADAP_COMPLETE(soft02, soft_i2c_init, soft_i2c_probe, soft_i2c_read, soft_i2c_write, NULL, CONFIG_SYS_I2C_SOFT_SPEED_3, CONFIG_SYS_I2C_SOFT_SLAVE_3, 2) #endif #if defined(I2C_SOFT_DECLARATIONS4) -U_BOOT_I2C_ADAP_COMPLETE(soft3, soft_i2c_init, soft_i2c_probe, +U_BOOT_I2C_ADAP_COMPLETE(soft03, soft_i2c_init, soft_i2c_probe, soft_i2c_read, soft_i2c_write, NULL, CONFIG_SYS_I2C_SOFT_SPEED_4, CONFIG_SYS_I2C_SOFT_SLAVE_4, 3) #endif +#if defined(I2C_SOFT_DECLARATIONS5) +U_BOOT_I2C_ADAP_COMPLETE(soft04, soft_i2c_init, soft_i2c_probe, + soft_i2c_read, soft_i2c_write, NULL, + CONFIG_SYS_I2C_SOFT_SPEED_5, + CONFIG_SYS_I2C_SOFT_SLAVE_5, + 4) +#endif +#if defined(I2C_SOFT_DECLARATIONS6) +U_BOOT_I2C_ADAP_COMPLETE(soft05, soft_i2c_init, soft_i2c_probe, + soft_i2c_read, soft_i2c_write, NULL, + CONFIG_SYS_I2C_SOFT_SPEED_6, + CONFIG_SYS_I2C_SOFT_SLAVE_6, + 5) +#endif +#if defined(I2C_SOFT_DECLARATIONS7) +U_BOOT_I2C_ADAP_COMPLETE(soft06, soft_i2c_init, soft_i2c_probe, + soft_i2c_read, soft_i2c_write, NULL, + CONFIG_SYS_I2C_SOFT_SPEED_7, + CONFIG_SYS_I2C_SOFT_SLAVE_7, + 6) +#endif +#if defined(I2C_SOFT_DECLARATIONS8) +U_BOOT_I2C_ADAP_COMPLETE(soft07, soft_i2c_init, soft_i2c_probe, + soft_i2c_read, soft_i2c_write, NULL, + CONFIG_SYS_I2C_SOFT_SPEED_8, + CONFIG_SYS_I2C_SOFT_SLAVE_8, + 7) +#endif +#if defined(I2C_SOFT_DECLARATIONS9) +U_BOOT_I2C_ADAP_COMPLETE(soft08, soft_i2c_init, soft_i2c_probe, + soft_i2c_read, soft_i2c_write, NULL, + CONFIG_SYS_I2C_SOFT_SPEED_9, + CONFIG_SYS_I2C_SOFT_SLAVE_9, + 8) +#endif +#if defined(I2C_SOFT_DECLARATIONS10) +U_BOOT_I2C_ADAP_COMPLETE(soft09, soft_i2c_init, soft_i2c_probe, + soft_i2c_read, soft_i2c_write, NULL, + CONFIG_SYS_I2C_SOFT_SPEED_10, + CONFIG_SYS_I2C_SOFT_SLAVE_10, + 9) +#endif +#if defined(I2C_SOFT_DECLARATIONS11) +U_BOOT_I2C_ADAP_COMPLETE(soft10, soft_i2c_init, soft_i2c_probe, + soft_i2c_read, soft_i2c_write, NULL, + CONFIG_SYS_I2C_SOFT_SPEED_11, + CONFIG_SYS_I2C_SOFT_SLAVE_11, + 10) +#endif +#if defined(I2C_SOFT_DECLARATIONS12) +U_BOOT_I2C_ADAP_COMPLETE(soft11, soft_i2c_init, soft_i2c_probe, + soft_i2c_read, soft_i2c_write, NULL, + CONFIG_SYS_I2C_SOFT_SPEED_12, + CONFIG_SYS_I2C_SOFT_SLAVE_12, + 11) +#endif diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 26d34ae..4375abc 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -40,7 +40,7 @@ static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, desc->flags = desc0; desc->cnt = desc1; desc->addr = desc2; - desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac); + desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac); } static void dwmci_prepare_data(struct dwmci_host *host, @@ -58,7 +58,7 @@ static void dwmci_prepare_data(struct dwmci_host *host, dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); data_start = (ulong)cur_idmac; - dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac); + dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac); do { flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; @@ -70,7 +70,7 @@ static void dwmci_prepare_data(struct dwmci_host *host, cnt = data->blocksize * 8; dwmci_set_idma_desc(cur_idmac, flags, cnt, - (u32)bounce_buffer + (i * PAGE_SIZE)); + (ulong)bounce_buffer + (i * PAGE_SIZE)); if (blk_cnt <= 8) break; diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c index 731458c..b0d063c 100644 --- a/drivers/mmc/hi6220_dw_mmc.c +++ b/drivers/mmc/hi6220_dw_mmc.c @@ -48,7 +48,7 @@ int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width) return -ENOMEM; } - host->ioaddr = (void *)regbase; + host->ioaddr = (void *)(ulong)regbase; host->buswidth = bus_width; host->bus_hz = MMC0_DEFAULT_FREQ; diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c index c517b9c..2138695 100644 --- a/drivers/mtd/mtd_uboot.c +++ b/drivers/mtd/mtd_uboot.c @@ -37,7 +37,7 @@ static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size, return 0; #else - puts("offset is not a number\n"); + puts("mtdparts support missing.\n"); return -1; #endif } diff --git a/drivers/net/phy/natsemi.c b/drivers/net/phy/natsemi.c index ea9fe83..d2e4c3c 100644 --- a/drivers/net/phy/natsemi.c +++ b/drivers/net/phy/natsemi.c @@ -53,7 +53,7 @@ static struct phy_driver DP83630_driver = { /* NatSemi DP83865 */ -static int dp83865_config(struct phy_device *phydev) +static int dp838xx_config(struct phy_device *phydev) { phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); genphy_config_aneg(phydev); @@ -105,15 +105,56 @@ static struct phy_driver DP83865_driver = { .uid = 0x20005c70, .mask = 0xfffffff0, .features = PHY_GBIT_FEATURES, - .config = &dp83865_config, + .config = &dp838xx_config, .startup = &dp83865_startup, .shutdown = &genphy_shutdown, }; +/* NatSemi DP83848 */ +static int dp83848_parse_status(struct phy_device *phydev) +{ + int mii_reg; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); + + if(mii_reg & (BMSR_100FULL | BMSR_100HALF)) { + phydev->speed = SPEED_100; + } else { + phydev->speed = SPEED_10; + } + + if (mii_reg & (BMSR_10FULL | BMSR_100FULL)) { + phydev->duplex = DUPLEX_FULL; + } else { + phydev->duplex = DUPLEX_HALF; + } + + return 0; +} + +static int dp83848_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + dp83848_parse_status(phydev); + + return 0; +} + +static struct phy_driver DP83848_driver = { + .name = "NatSemi DP83848", + .uid = 0x20005c90, + .mask = 0x2000ff90, + .features = PHY_BASIC_FEATURES, + .config = &dp838xx_config, + .startup = &dp83848_startup, + .shutdown = &genphy_shutdown, +}; + int phy_natsemi_init(void) { phy_register(&DP83630_driver); phy_register(&DP83865_driver); + phy_register(&DP83848_driver); return 0; } diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 9175d2c..5637a0d 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -327,13 +327,13 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) for (i = 0; i < RX_BUF; i++) { priv->rx_bd[i].status = 0xF0000000; priv->rx_bd[i].addr = - ((u32)(priv->rxbuffers) + + ((ulong)(priv->rxbuffers) + (i * PKTSIZE_ALIGN)); } /* WRAP bit to last BD */ priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; /* Write RxBDs to IP */ - writel((u32)priv->rx_bd, ®s->rxqbase); + writel((ulong)priv->rx_bd, ®s->rxqbase); /* Setup for DMA Configuration register */ writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); @@ -396,22 +396,22 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; /* setup BD */ - writel((u32)priv->tx_bd, ®s->txqbase); + writel((ulong)priv->tx_bd, ®s->txqbase); /* Setup Tx BD */ memset(priv->tx_bd, 0, sizeof(struct emac_bd)); - priv->tx_bd->addr = (u32)ptr; + priv->tx_bd->addr = (ulong)ptr; priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | ZYNQ_GEM_TXBUF_LAST_MASK | ZYNQ_GEM_TXBUF_WRAP_MASK; - addr = (u32) ptr; + addr = (ulong) ptr; addr &= ~(ARCH_DMA_MINALIGN - 1); size = roundup(len, ARCH_DMA_MINALIGN); flush_dcache_range(addr, addr + size); - addr = (u32)priv->rxbuffers; + addr = (ulong)priv->rxbuffers; addr &= ~(ARCH_DMA_MINALIGN - 1); size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); flush_dcache_range(addr, addr + size); @@ -451,7 +451,7 @@ static int zynq_gem_recv(struct eth_device *dev) u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; addr &= ~(ARCH_DMA_MINALIGN - 1); - net_process_received_packet((u8 *)addr, frame_len); + net_process_received_packet((u8 *)(ulong)addr, frame_len); if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) priv->rx_first_buf = priv->rxbd_current; @@ -530,7 +530,7 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, /* Initialize the bd spaces for tx and rx bd's */ priv->tx_bd = (struct emac_bd *)bd_space; - priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE); + priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); priv->phyaddr = phy_addr; priv->emio = emio; diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c index 07f1726..a64792f 100644 --- a/drivers/pci/pci_common.c +++ b/drivers/pci/pci_common.c @@ -231,7 +231,7 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose, * if PCI_REGION_MEM is set we do a two pass search with preference * on matches that don't have PCI_REGION_SYS_MEMORY set */ - if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) { + if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) { ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, PCI_REGION_SYS_MEMORY, &phys_addr); if (!ret) @@ -298,7 +298,7 @@ pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose, * if PCI_REGION_MEM is set we do a two pass search with preference * on matches that don't have PCI_REGION_SYS_MEMORY set */ - if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) { + if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) { ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, PCI_REGION_SYS_MEMORY, &bus_addr); if (!ret) diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c index 202e482..3099bf4 100644 --- a/drivers/usb/eth/smsc95xx.c +++ b/drivers/usb/eth/smsc95xx.c @@ -680,7 +680,8 @@ static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length) ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)); - debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg); + debug("** %s(), len %d, buf %#x\n", __func__, length, + (unsigned int)(ulong)msg); if (length > PKTSIZE) return -ENOSPC; @@ -701,8 +702,8 @@ static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length) &actual_len, USB_BULK_SEND_TIMEOUT); debug("Tx: len = %u, actual = %u, err = %d\n", - length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), - actual_len, err); + (unsigned int)(length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)), + (unsigned int)actual_len, err); return err; } @@ -784,7 +785,7 @@ static int smsc95xx_recv(struct eth_device *eth) /* Adjust for next iteration */ actual_len -= sizeof(packet_len) + packet_len; buf_ptr += sizeof(packet_len) + packet_len; - cur_buf_align = (int)buf_ptr - (int)recv_buf; + cur_buf_align = (ulong)buf_ptr - (ulong)recv_buf; if (cur_buf_align & 0x03) { int align = 4 - (cur_buf_align & 0x03); diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index ece48e6..20b6c18 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -13,6 +13,7 @@ #include <config.h> #include <common.h> #include <errno.h> +#include <fastboot.h> #include <malloc.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> @@ -23,6 +24,9 @@ #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV #include <fb_mmc.h> #endif +#ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV +#include <fb_nand.h> +#endif #define FASTBOOT_VERSION "0.4" @@ -34,9 +38,6 @@ #define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1 (0x0040) #define TX_ENDPOINT_MAXIMUM_PACKET_SIZE (0x0040) -/* The 64 defined bytes plus \0 */ -#define RESPONSE_LEN (64 + 1) - #define EP_BUFFER_SIZE 4096 struct f_fastboot { @@ -53,6 +54,7 @@ static inline struct f_fastboot *func_to_fastboot(struct usb_function *f) } static struct f_fastboot *fastboot_func; +static unsigned int fastboot_flash_session_id; static unsigned int download_size; static unsigned int download_bytes; static bool is_high_speed; @@ -125,6 +127,19 @@ static struct usb_gadget_strings *fastboot_strings[] = { static void rx_handler_command(struct usb_ep *ep, struct usb_request *req); static int strcmp_l1(const char *s1, const char *s2); + +void fastboot_fail(char *response, const char *reason) +{ + strncpy(response, "FAIL\0", 5); + strncat(response, reason, FASTBOOT_RESPONSE_LEN - 4 - 1); +} + +void fastboot_okay(char *response, const char *reason) +{ + strncpy(response, "OKAY\0", 5); + strncat(response, reason, FASTBOOT_RESPONSE_LEN - 4 - 1); +} + static void fastboot_complete(struct usb_ep *ep, struct usb_request *req) { int status = req->status; @@ -358,7 +373,7 @@ static int strcmp_l1(const char *s1, const char *s2) static void cb_getvar(struct usb_ep *ep, struct usb_request *req) { char *cmd = req->buf; - char response[RESPONSE_LEN]; + char response[FASTBOOT_RESPONSE_LEN]; const char *s; size_t chars_left; @@ -382,6 +397,15 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) sprintf(str_num, "0x%08x", CONFIG_FASTBOOT_BUF_SIZE); strncat(response, str_num, chars_left); + + /* + * This also indicates the start of a new flashing + * "session", in which we could have 1-N buffers to + * write to a partition. + * + * Reset our session counter. + */ + fastboot_flash_session_id = 0; } else if (!strcmp_l1("serialno", cmd)) { s = getenv("serial#"); if (s) @@ -415,7 +439,7 @@ static unsigned int rx_bytes_expected(unsigned int maxpacket) #define BYTES_PER_DOT 0x20000 static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) { - char response[RESPONSE_LEN]; + char response[FASTBOOT_RESPONSE_LEN]; unsigned int transfer_size = download_size - download_bytes; const unsigned char *buffer = req->buf; unsigned int buffer_size = req->actual; @@ -472,7 +496,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) static void cb_download(struct usb_ep *ep, struct usb_request *req) { char *cmd = req->buf; - char response[RESPONSE_LEN]; + char response[FASTBOOT_RESPONSE_LEN]; unsigned int max; strsep(&cmd, ":"); @@ -533,7 +557,7 @@ static void cb_continue(struct usb_ep *ep, struct usb_request *req) static void cb_flash(struct usb_ep *ep, struct usb_request *req) { char *cmd = req->buf; - char response[RESPONSE_LEN]; + char response[FASTBOOT_RESPONSE_LEN]; strsep(&cmd, ":"); if (!cmd) { @@ -544,9 +568,16 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req) strcpy(response, "FAILno flash device defined"); #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV - fb_mmc_flash_write(cmd, (void *)CONFIG_FASTBOOT_BUF_ADDR, + fb_mmc_flash_write(cmd, fastboot_flash_session_id, + (void *)CONFIG_FASTBOOT_BUF_ADDR, download_bytes, response); #endif +#ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV + fb_nand_flash_write(cmd, fastboot_flash_session_id, + (void *)CONFIG_FASTBOOT_BUF_ADDR, + download_bytes, response); +#endif + fastboot_flash_session_id++; fastboot_tx_write_str(response); } #endif @@ -577,7 +608,7 @@ static void cb_oem(struct usb_ep *ep, struct usb_request *req) static void cb_erase(struct usb_ep *ep, struct usb_request *req) { char *cmd = req->buf; - char response[RESPONSE_LEN]; + char response[FASTBOOT_RESPONSE_LEN]; strsep(&cmd, ":"); if (!cmd) { @@ -591,6 +622,9 @@ static void cb_erase(struct usb_ep *ep, struct usb_request *req) #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV fb_mmc_erase(cmd, response); #endif +#ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV + fb_nand_erase(cmd, response); +#endif fastboot_tx_write_str(response); } #endif diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index d93e3e7..b02abd3 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -177,11 +177,22 @@ "fdt ram 0x80f80000 0x80000;" \ "ramdisk ram 0x81000000 0x4000000\0" +#define CONFIG_DFU_SF +#define DFU_ALT_INFO_QSPI \ + "dfu_alt_info_qspi=" \ + "u-boot.bin raw 0x0 0x080000;" \ + "u-boot.backup raw 0x080000 0x080000;" \ + "u-boot-spl-os raw 0x100000 0x010000;" \ + "u-boot-env raw 0x110000 0x010000;" \ + "u-boot-env.backup raw 0x120000 0x010000;" \ + "kernel raw 0x130000 0x800000\0" + #define DFUARGS \ "dfu_bufsiz=0x10000\0" \ DFU_ALT_INFO_MMC \ DFU_ALT_INFO_EMMC \ - DFU_ALT_INFO_RAM + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_QSPI #else #define DFUARGS #endif diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index 0b804eb..b614f19 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -67,7 +67,7 @@ #undef CONFIG_CMD_DHCP #undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_I2C +#define CONFIG_CMD_I2C #undef CONFIG_CMD_IRQ /* @@ -105,17 +105,22 @@ #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F #define CONFIG_SYS_I2C_IHS +#define CONFIG_SYS_I2C_IHS_DUAL #define CONFIG_SYS_I2C_IHS_CH0 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F +#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F #define CONFIG_SYS_I2C_IHS_CH1 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F +#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F -#define CONFIG_SYS_SPD_BUS_NUM 2 +#define CONFIG_SYS_SPD_BUS_NUM 4 /* Temp sensor/hwmon/dtt */ -#define CONFIG_SYS_DTT_BUS_NUM 2 +#define CONFIG_SYS_DTT_BUS_NUM 4 #define CONFIG_DTT_LM63 1 /* National LM63 */ #define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */ #define CONFIG_DTT_PWM_LOOKUPTABLE \ @@ -123,8 +128,9 @@ { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } } #define CONFIG_DTT_TACH_LIMIT 0xa10 -#define CONFIG_SYS_ICS8N3QV01_I2C {0, 1} -#define CONFIG_SYS_SIL1178_I2C {0, 1} +#define CONFIG_SYS_ICS8N3QV01_I2C {1, 3} +#define CONFIG_SYS_SIL1178_I2C {0, 2} +#define CONFIG_SYS_DP501_I2C {0, 2} /* EBC peripherals */ @@ -327,5 +333,7 @@ */ #define CONFIG_SYS_MPC92469AC #define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT +#define CONFIG_SYS_DP501_DIFFERENTIAL +#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ #endif /* __CONFIG_H */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 3cb279a..84d0928 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -20,7 +20,11 @@ #define CONFIG_SYS_TEXT_BASE 0xFE000000 +#ifdef CONFIG_HRCON_DH +#define CONFIG_IDENT_STRING " hrcon dh 0.01" +#else #define CONFIG_IDENT_STRING " hrcon 0.01" +#endif #define CONFIG_BOARD_EARLY_INIT_F @@ -343,6 +347,22 @@ #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F +#ifdef CONFIG_HRCON_DH +#define CONFIG_SYS_I2C_IHS_DUAL +#define CONFIG_SYS_I2C_IHS_CH0_1 +#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH1_1 +#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH2_1 +#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH3_1 +#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F +#endif + /* * Software (bit-bang) I2C driver configuration */ @@ -358,34 +378,85 @@ #define I2C_SOFT_DECLARATIONS4 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F +#define I2C_SOFT_DECLARATIONS5 +#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F +#define I2C_SOFT_DECLARATIONS6 +#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F +#define I2C_SOFT_DECLARATIONS7 +#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F +#define I2C_SOFT_DECLARATIONS8 +#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F + +#ifdef CONFIG_HRCON_DH +#define I2C_SOFT_DECLARATIONS9 +#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F +#define I2C_SOFT_DECLARATIONS10 +#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F +#define I2C_SOFT_DECLARATIONS11 +#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F +#define I2C_SOFT_DECLARATIONS12 +#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F +#endif -#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} -#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} +#ifdef CONFIG_HRCON_DH +#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} +#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} +#define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \ + {12, 0x4c} } +#else +#define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12} #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} +#define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \ + {8, 0x4c} } +#endif #ifndef __ASSEMBLY__ void fpga_gpio_set(unsigned int bus, int pin); void fpga_gpio_clear(unsigned int bus, int pin); int fpga_gpio_get(unsigned int bus, int pin); +void fpga_control_set(unsigned int bus, int pin); +void fpga_control_clear(unsigned int bus, int pin); #endif +#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) +#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) +#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) + +#ifdef CONFIG_HRCON_DH +#define I2C_ACTIVE \ + do { \ + if (I2C_ADAP_HWNR > 7) \ + fpga_control_set(I2C_FPGA_IDX, 0x0004); \ + else \ + fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ + } while (0) +#else #define I2C_ACTIVE { } +#endif #define I2C_TRISTATE { } #define I2C_READ \ - (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0) + (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) #define I2C_SDA(bit) \ do { \ if (bit) \ - fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \ + fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ else \ - fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \ + fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ } while (0) #define I2C_SCL(bit) \ do { \ if (bit) \ - fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \ + fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ else \ - fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \ + fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ } while (0) #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ @@ -402,6 +473,10 @@ int fpga_gpio_get(unsigned int bus, int pin); #define CONFIG_SYS_DP501_DIFFERENTIAL #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ +#ifdef CONFIG_HRCON_DH +#define CONFIG_SYS_OSD_DH +#endif + /* * General PCI * Addresses are mapped 1-1. diff --git a/include/configs/kwb.h b/include/configs/kwb.h index 96f2e9d..45253b8 100644 --- a/include/configs/kwb.h +++ b/include/configs/kwb.h @@ -57,6 +57,8 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ +"bootaddr=0x80001100\0" \ +"bootdev=cpsw(0,0)\0" \ "vx_romfsbase=0x800E0000\0" \ "vx_romfssize=0x20000\0" \ "vx_memtop=0x8FBEF000\0" \ @@ -66,7 +68,7 @@ BUR_COMMON_ENV \ "logoaddr=0x82000000\0" \ "defaultARlen=0x8000\0" \ "loaddefaultAR=mmc read ${loadaddr} 800 ${defaultARlen}\0" \ -"defaultAR=run loadromfs; run loaddefaultAR; go ${loadaddr}\0" \ +"defaultAR=run loadromfs; run loaddefaultAR; bootvx ${loadaddr}\0" \ "logo0=fatload mmc 0:1 ${logoaddr} SYSTEM/ADDON/Bootlogo/Bootlogo.bmp.gz && " \ "bmp display ${logoaddr} 0 0\0" \ "logo1=fatload mmc 0:1 ${logoaddr} SYSTEM/BASE/Bootlogo/Bootlogo.bmp.gz && " \ @@ -74,11 +76,11 @@ BUR_COMMON_ENV \ "mmcboot=echo booting AR from eMMC-flash ...; "\ "run logo0 || run logo1; " \ "run loadromfs; " \ - "fatload mmc 0:1 ${loadaddr} arimg && go ${loadaddr}; " \ + "fatload mmc 0:1 ${loadaddr} arimg && bootvx ${loadaddr}; " \ "run defaultAR;\0" \ "netboot=echo booting AR from network ...; " \ "run loadromfs; " \ - "tftp ${loadaddr} arimg && go ${loadaddr}; " \ + "tftp ${loadaddr} arimg && bootvx ${loadaddr}; " \ "puts 'networkboot failed!';\0" \ "netscript=echo running script from network (tftp) ...; " \ "tftp 0x80000000 netscript.img && source; " \ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index ecd5615..7b60f29 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -272,13 +272,4 @@ #endif /* (CONFIG_CMD_NET) */ -/* - * BOOTP fields - */ - -#define CONFIG_BOOTP_SUBNETMASK 0x00000001 -#define CONFIG_BOOTP_GATEWAY 0x00000002 -#define CONFIG_BOOTP_HOSTNAME 0x00000004 -#define CONFIG_BOOTP_BOOTPATH 0x00000010 - #endif /* __CONFIG_H */ diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index ccb5dd3..d68cded 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -127,35 +127,58 @@ #define CONFIG_CMD_NAND #define CONFIG_NAND_OMAP_GPMC #define CONFIG_NAND_OMAP_ELM + +/* NAND Configuration. */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_SIZE 4096 +#define CONFIG_SYS_NAND_OOBSIZE 224 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*4096) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ + 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\ + 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,\ + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65,\ + 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,\ + 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,\ + 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,\ + 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\ + 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153,\ + 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,\ + 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193,\ + 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209} + #define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_ECCBYTES 26 +#define CONFIG_SYS_NAND_ECCSTEPS 8 +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW +/* END NAND Configuration. */ + #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +/* #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 + + + +#define CONFIG_CMD_MTDPARTS + +#define CONFIG_CMD_ASKENV /* monitor functions : ask for env variable */ +#define CONFIG_VERSION_VARIABLE /* monitor functions : u-boot version */ +#define CONFIG_CMD_DIAG /* monitor functions : Diagnostics */ #define MTDIDS_DEFAULT "nand0=omap2-nand.0" -#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ - "128k(SPL.backup1)," \ - "128k(SPL.backup2)," \ - "128k(SPL.backup3),1792k(u-boot)," \ - "128k(u-boot-spl-os)," \ - "128k(u-boot-env),5m(kernel),-(rootfs)" +/* Size must be a multiple of Nand erase size (524288 b) */ +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(SPL)," \ + "512k(SPL.backup1)," \ + "512k(SPL.backup2)," \ + "512k(SPL.backup3),1536k(u-boot)," \ + "512k(u-boot-spl-os)," \ + "512k(u-boot-env),5m(kernel),-(rootfs)" #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ @@ -198,11 +221,15 @@ #undef CONFIG_SPL_ETH_SUPPORT #endif +/* CPSW ethernet */ +#define CONFIG_NET_MULTI + /* Network */ #define CONFIG_CMD_MII #define CONFIG_PHYLIB #define CONFIG_PHY_RESET 1 #define CONFIG_PHY_NATSEMI +#define CONFIG_PHY_REALTEK /* CPSW support */ #define CONFIG_SPL_ETH_SUPPORT diff --git a/include/configs/strider.h b/include/configs/strider.h new file mode 100644 index 0000000..fb7b7f9 --- /dev/null +++ b/include/configs/strider.h @@ -0,0 +1,651 @@ +/* + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC830x 1 /* MPC830x family */ +#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ +#define CONFIG_STRIDER 1 /* STRIDER board specific */ + +#define CONFIG_SYS_TEXT_BASE 0xFE000000 + +#ifdef CONFIG_STRIDER_CPU +#define CONFIG_IDENT_STRING " strider cpu 0.01" +#else +#define CONFIG_IDENT_STRING " strider con 0.01" +#endif + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_LAST_STAGE_INIT + +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 + +#define CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 + +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_ALT_MEMTEST + +#define CONFIG_CMD_FPGAD +#define CONFIG_CMD_IOLOOP + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66.66MHz, then + * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz + * We choose the A type silicon as default, so the core is 400Mhz. + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_SVCOD_DIV_2 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_CORE_TO_CSB_3X1) +/* + * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits + * in 8308's HRCWH according to the manual, but original Freescale's + * code has them and I've expirienced some problems using the board + * with BDI3000 attached when I've tried to set these bits to zero + * (UART doesn't work after the 'reset run' command). + */ +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_MII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN) + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH (\ + SICRH_ESDHC_A_SD |\ + SICRH_ESDHC_B_SD |\ + SICRH_ESDHC_C_SD |\ + SICRH_GPIO_A_GPIO |\ + SICRH_GPIO_B_GPIO |\ + SICRH_IEEE1588_A_GPIO |\ + SICRH_USB |\ + SICRH_GTM_GPIO |\ + SICRH_IEEE1588_B_GPIO |\ + SICRH_ETSEC2_GPIO |\ + SICRH_GPIOSEL_1 |\ + SICRH_TMROBI_V3P3 |\ + SICRH_TSOBI1_V2P5 |\ + SICRH_TSOBI2_V2P5) /* 0x0037f103 */ +#define CONFIG_SYS_SICRL (\ + SICRL_SPI_PF0 |\ + SICRL_UART_PF0 |\ + SICRL_IRQ_PF0 |\ + SICRL_I2C2_PF0 |\ + SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * SERDES + */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 + +/* + * Arbiter Setup + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ +#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ + | DDRCDR_PZ_LOZ \ + | DDRCDR_NZ_LOZ \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x7b880001 */ +/* + * Manually set up DDR parameters + * consist of one chip NT5TU64M16HG from NANYA + */ + +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ + +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ + | CSCONFIG_BANK_BIT_3 \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) + /* 0x80010102 */ +#define CONFIG_SYS_DDR_TIMING_3 0 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00260802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (7 << TIMING_CFG1_CASLAT_SHIFT) \ + | (9 << TIMING_CFG1_REFREC_SHIFT) \ + | (2 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x26279222 */ +#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (4 << TIMING_CFG2_CPO_SHIFT) \ + | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x021848c5 */ +#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x08240100 */ +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_16) + /* 0x43100000 */ + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ +#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0242 << SDRAM_MODE_SD_SHIFT)) + /* ODT 150ohm CL=4, AL=0 on SDRAM */ +#define CONFIG_SYS_DDR_MODE2 0x00000000 + +/* + * Memory test + */ +#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x07f00000 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 +#define CONFIG_SYS_LBC_LBCR 0x00040000 + +/* + * FLASH on the Local Bus + */ +#if 1 +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 +#else +#define CONFIG_SYS_NO_FLASH +#endif + +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ + +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * FPGA + */ +#define CONFIG_SYS_FPGA0_BASE 0xE0600000 +#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ + +/* Window base at FPGA base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET) + +#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE +#define CONFIG_SYS_FPGA_DONE(k) 0x0010 + +#define CONFIG_SYS_FPGA_COUNT 1 + +#define CONFIG_SYS_MCLINK_MAX 3 + +#define CONFIG_SYS_FPGA_PTR \ + { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } + +#define CONFIG_SYS_FPGA_NO_RFL_HI + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 + +#define CONFIG_PCA953X /* NXP PCA9554 */ +#define CONFIG_PCA9698 /* NXP PCA9698 */ + +#define CONFIG_SYS_I2C_IHS +#define CONFIG_SYS_I2C_IHS_CH0 +#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F +#define CONFIG_SYS_I2C_IHS_CH1 +#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH2 +#define CONFIG_SYS_I2C_IHS_SPEED_2 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F +#define CONFIG_SYS_I2C_IHS_CH3 +#define CONFIG_SYS_I2C_IHS_SPEED_3 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F + +/* + * Software (bit-bang) I2C driver configuration + */ +#define CONFIG_SYS_I2C_SOFT +#define CONFIG_SOFT_I2C_READ_REPEATED_START +#define CONFIG_SYS_I2C_SOFT_SPEED 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F +#define I2C_SOFT_DECLARATIONS2 +#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F +#define I2C_SOFT_DECLARATIONS3 +#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F +#define I2C_SOFT_DECLARATIONS4 +#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F +#ifdef CONFIG_STRIDER_CON +#define I2C_SOFT_DECLARATIONS5 +#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F +#define I2C_SOFT_DECLARATIONS6 +#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F +#define I2C_SOFT_DECLARATIONS7 +#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F +#define I2C_SOFT_DECLARATIONS8 +#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F +#endif + +#ifdef CONFIG_STRIDER_CON +#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} +#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} +#define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} +#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} +#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ + {12, 0x4c} } +#else +#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} +#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} +#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} +#define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ + {4, 0x18} } +#endif + +#ifndef __ASSEMBLY__ +void fpga_gpio_set(unsigned int bus, int pin); +void fpga_gpio_clear(unsigned int bus, int pin); +int fpga_gpio_get(unsigned int bus, int pin); +#endif + +#ifdef CONFIG_STRIDER_CON +#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) +#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) +#define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ + (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) +#else +#define I2C_SDA_GPIO 0x0040 +#define I2C_SCL_GPIO 0x0020 +#define I2C_FPGA_IDX I2C_ADAP_HWNR +#endif +#define I2C_ACTIVE { } +#define I2C_TRISTATE { } +#define I2C_READ \ + (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) +#define I2C_SDA(bit) \ + do { \ + if (bit) \ + fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ + else \ + fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ + } while (0) +#define I2C_SCL(bit) \ + do { \ + if (bit) \ + fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ + else \ + fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ + } while (0) +#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ + +/* + * Software (bit-bang) MII driver configuration + */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +#define CONFIG_BITBANGMII_MULTI + +/* + * OSD Setup + */ +#define CONFIG_SYS_OSD_SCREENS 1 +#define CONFIG_SYS_DP501_DIFFERENTIAL +#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +/* enable PCIE clock */ +#define CONFIG_SYS_SCCR_PCIEXP1CM 1 + +#define CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCIE + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC1_FLAGS 0 + +/* Options are: eTSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC0" + +/* + * Environment + */ +#if 1 +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#else +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ + +#define CONFIG_HOSTNAME hrcon +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS1\0" \ + "u-boot=u-boot.bin\0" \ + "kernel_addr=1000000\0" \ + "fdt_addr=C00000\0" \ + "fdtfile=hrcon.dtb\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ + " +${filesize};cp.b ${fileaddr} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp ${kernel_addr} $bootfile;" \ + "tftp ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_MMCBOOTCOMMAND \ + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ + "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND + + +#endif /* __CONFIG_H */ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 32bb805..7810dd6 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -67,11 +67,6 @@ "rootfstype=${mmcrootfstype}\0" /* - * Default to a quick boot delay. - */ -#define CONFIG_BOOTDELAY 1 - -/* * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, * we say (for simplicity) that we have 1 bank, always, even when * we have more. We always start at 0x80000000, and we place the @@ -288,4 +283,6 @@ #define NETARGS "" #endif +#include <config_distro_defaults.h> + #endif /* __CONFIG_TI_ARMV7_COMMON_H__ */ diff --git a/include/fastboot.h b/include/fastboot.h new file mode 100644 index 0000000..db826d2 --- /dev/null +++ b/include/fastboot.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2008 - 2009 + * Windriver, <www.windriver.com> + * Tom Rix <Tom.Rix@windriver.com> + * + * Copyright 2011 Sebastian Andrzej Siewior <bigeasy@linutronix.de> + * + * Copyright 2014 Linaro, Ltd. + * Rob Herring <robh@kernel.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _FASTBOOT_H_ +#define _FASTBOOT_H_ + +/* The 64 defined bytes plus \0 */ +#define FASTBOOT_RESPONSE_LEN (64 + 1) + +void fastboot_fail(char *response, const char *reason); +void fastboot_okay(char *response, const char *reason); + +#endif /* _FASTBOOT_H_ */ diff --git a/include/fb_mmc.h b/include/fb_mmc.h index 402ba9b..978a139 100644 --- a/include/fb_mmc.h +++ b/include/fb_mmc.h @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -void fb_mmc_flash_write(const char *cmd, void *download_buffer, - unsigned int download_bytes, char *response); +void fb_mmc_flash_write(const char *cmd, unsigned int session_id, + void *download_buffer, unsigned int download_bytes, + char *response); void fb_mmc_erase(const char *cmd, char *response); diff --git a/include/fb_nand.h b/include/fb_nand.h new file mode 100644 index 0000000..80ddef5 --- /dev/null +++ b/include/fb_nand.h @@ -0,0 +1,11 @@ +/* + * Copyright 2014 Broadcom Corporation. + * Copyright 2015 Free Electrons. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +void fb_nand_flash_write(const char *cmd, unsigned int session_id, + void *download_buffer, unsigned int download_bytes, + char *response); +void fb_nand_erase(const char *cmd, char *response); diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index 8a5efe7..3b8762d 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -143,7 +143,7 @@ struct ihs_fpga { u16 reserved_2[2]; /* 0x001c */ struct ihs_io_ep ep; /* 0x0020 */ u16 reserved_3[9]; /* 0x002e */ - struct ihs_i2c i2c; /* 0x0040 */ + struct ihs_i2c i2c0; /* 0x0040 */ u16 reserved_4[10]; /* 0x004c */ u16 mc_int; /* 0x0060 */ u16 mc_int_en; /* 0x0062 */ @@ -157,9 +157,9 @@ struct ihs_fpga { u16 mc_rx_data; /* 0x0072 */ u16 reserved_5[69]; /* 0x0074 */ u16 reflection_high; /* 0x00fe */ - struct ihs_osd osd; /* 0x0100 */ + struct ihs_osd osd0; /* 0x0100 */ u16 reserved_6[889]; /* 0x010e */ - u16 videomem[31736]; /* 0x0800 */ + u16 videomem0[2048]; /* 0x0800 */ }; #endif @@ -171,13 +171,15 @@ struct ihs_fpga { u16 fpga_features; /* 0x0006 */ u16 reserved_0[1]; /* 0x0008 */ u16 top_interrupt; /* 0x000a */ - u16 reserved_1[4]; /* 0x000c */ + u16 reserved_1[2]; /* 0x000c */ + u16 control; /* 0x0010 */ + u16 extended_control; /* 0x0012 */ struct ihs_gpio gpio; /* 0x0014 */ u16 mpc3w_control; /* 0x001a */ u16 reserved_2[2]; /* 0x001c */ struct ihs_io_ep ep; /* 0x0020 */ u16 reserved_3[9]; /* 0x002e */ - struct ihs_i2c i2c; /* 0x0040 */ + struct ihs_i2c i2c0; /* 0x0040 */ u16 reserved_4[10]; /* 0x004c */ u16 mc_int; /* 0x0060 */ u16 mc_int_en; /* 0x0062 */ @@ -191,9 +193,82 @@ struct ihs_fpga { u16 mc_rx_data; /* 0x0072 */ u16 reserved_5[69]; /* 0x0074 */ u16 reflection_high; /* 0x00fe */ - struct ihs_osd osd; /* 0x0100 */ + struct ihs_osd osd0; /* 0x0100 */ +#ifdef CONFIG_SYS_OSD_DH + u16 reserved_6[57]; /* 0x010e */ + struct ihs_osd osd1; /* 0x0180 */ + u16 reserved_7[9]; /* 0x018e */ + struct ihs_i2c i2c1; /* 0x01a0 */ + u16 reserved_8[1834]; /* 0x01ac */ + u16 videomem0[2048]; /* 0x1000 */ + u16 videomem1[2048]; /* 0x2000 */ +#else + u16 reserved_6[889]; /* 0x010e */ + u16 videomem0[2048]; /* 0x0800 */ +#endif +}; +#endif + +#ifdef CONFIG_STRIDER_CPU +struct ihs_fpga { + u16 reflection_low; /* 0x0000 */ + u16 versions; /* 0x0002 */ + u16 fpga_version; /* 0x0004 */ + u16 fpga_features; /* 0x0006 */ + u16 reserved_0[1]; /* 0x0008 */ + u16 top_interrupt; /* 0x000a */ + u16 reserved_1[3]; /* 0x000c */ + u16 extended_control; /* 0x0012 */ + struct ihs_gpio gpio; /* 0x0014 */ + u16 mpc3w_control; /* 0x001a */ + u16 reserved_2[2]; /* 0x001c */ + struct ihs_io_ep ep; /* 0x0020 */ + u16 reserved_3[9]; /* 0x002e */ + u16 mc_int; /* 0x0040 */ + u16 mc_int_en; /* 0x0042 */ + u16 mc_status; /* 0x0044 */ + u16 mc_control; /* 0x0046 */ + u16 mc_tx_data; /* 0x0048 */ + u16 mc_tx_address; /* 0x004a */ + u16 mc_tx_cmd; /* 0x004c */ + u16 mc_res; /* 0x004e */ + u16 mc_rx_cmd_status; /* 0x0050 */ + u16 mc_rx_data; /* 0x0052 */ + u16 reserved_4[62]; /* 0x0054 */ + struct ihs_i2c i2c0; /* 0x00d0 */ +}; +#endif + +#ifdef CONFIG_STRIDER_CON +struct ihs_fpga { + u16 reflection_low; /* 0x0000 */ + u16 versions; /* 0x0002 */ + u16 fpga_version; /* 0x0004 */ + u16 fpga_features; /* 0x0006 */ + u16 reserved_0[1]; /* 0x0008 */ + u16 top_interrupt; /* 0x000a */ + u16 reserved_1[4]; /* 0x000c */ + struct ihs_gpio gpio; /* 0x0014 */ + u16 mpc3w_control; /* 0x001a */ + u16 reserved_2[2]; /* 0x001c */ + struct ihs_io_ep ep; /* 0x0020 */ + u16 reserved_3[9]; /* 0x002e */ + struct ihs_i2c i2c0; /* 0x0040 */ + u16 reserved_4[10]; /* 0x004c */ + u16 mc_int; /* 0x0060 */ + u16 mc_int_en; /* 0x0062 */ + u16 mc_status; /* 0x0064 */ + u16 mc_control; /* 0x0066 */ + u16 mc_tx_data; /* 0x0068 */ + u16 mc_tx_address; /* 0x006a */ + u16 mc_tx_cmd; /* 0x006c */ + u16 mc_res; /* 0x006e */ + u16 mc_rx_cmd_status; /* 0x0070 */ + u16 mc_rx_data; /* 0x0072 */ + u16 reserved_5[70]; /* 0x0074 */ + struct ihs_osd osd0; /* 0x0100 */ u16 reserved_6[889]; /* 0x010e */ - u16 videomem[31736]; /* 0x0800 */ + u16 videomem0[2048]; /* 0x0800 */ }; #endif @@ -208,11 +283,13 @@ struct ihs_fpga { u16 reserved_1[29]; /* 0x001e */ u16 mpc3w_control; /* 0x0058 */ u16 reserved_2[3]; /* 0x005a */ - struct ihs_i2c i2c; /* 0x0060 */ - u16 reserved_3[205]; /* 0x0066 */ - struct ihs_osd osd; /* 0x0200 */ - u16 reserved_4[761]; /* 0x020e */ - u16 videomem[31736]; /* 0x0800 */ + struct ihs_i2c i2c0; /* 0x0060 */ + u16 reserved_3[2]; /* 0x006c */ + struct ihs_i2c i2c1; /* 0x0070 */ + u16 reserved_4[194]; /* 0x007c */ + struct ihs_osd osd0; /* 0x0200 */ + u16 reserved_5[761]; /* 0x020e */ + u16 videomem0[2048]; /* 0x0800 */ }; #endif diff --git a/include/aboot.h b/include/image-sparse.h index 30e4d36..0382f5b 100644 --- a/include/aboot.h +++ b/include/image-sparse.h @@ -9,8 +9,16 @@ #define ROUNDUP(x, y) (((x) + ((y) - 1)) & ~((y) - 1)) -void fastboot_fail(const char *s); -void fastboot_okay(const char *s); +typedef struct sparse_storage { + unsigned int block_sz; + unsigned int start; + unsigned int size; + const char *name; + + int (*write)(struct sparse_storage *storage, void *priv, + unsigned int offset, unsigned int size, + char *data); +} sparse_storage_t; static inline int is_sparse_image(void *buf) { @@ -23,6 +31,5 @@ static inline int is_sparse_image(void *buf) return 0; } -void write_sparse_image(block_dev_desc_t *dev_desc, - disk_partition_t *info, const char *part_name, - void *data, unsigned sz); +int store_sparse_image(sparse_storage_t *storage, void *storage_priv, + unsigned int session_id, void *data); diff --git a/include/linux/mtd/concat.h b/include/linux/mtd/concat.h index 195a4a5..a374ca9 100644 --- a/include/linux/mtd/concat.h +++ b/include/linux/mtd/concat.h @@ -1,9 +1,10 @@ /* * MTD device concatenation layer definitions * - * (C) 2002 Robert Kaiser <rkaiser@sysgo.de> + * Copyright © 2002 Robert Kaiser <rkaiser@sysgo.de> + * + * SPDX-License-Identifier: GPL-2.0+ * - * This code is GPL */ #ifndef MTD_CONCAT_H diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h index ba29d53..a3cfe6b 100644 --- a/include/linux/mtd/doc2000.h +++ b/include/linux/mtd/doc2000.h @@ -1,12 +1,13 @@ /* * Linux driver for Disk-On-Chip devices * - * Copyright (C) 1999 Machine Vision Holdings, Inc. - * Copyright (C) 2001-2003 David Woodhouse <dwmw2@infradead.org> - * Copyright (C) 2002-2003 Greg Ungerer <gerg@snapgear.com> - * Copyright (C) 2002-2003 SnapGear Inc + * Copyright © 1999 Machine Vision Holdings, Inc. + * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org> + * Copyright © 2002-2003 Greg Ungerer <gerg@snapgear.com> + * Copyright © 2002-2003 SnapGear Inc + * + * SPDX-License-Identifier: GPL-2.0+ * - * Released under GPL */ #ifndef __MTD_DOC2000_H__ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index c2cd3df..9da77ec 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -1,7 +1,7 @@ /* * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org> et al. * - * Released under GPL + * SPDX-License-Identifier: GPL-2.0+ * */ diff --git a/include/linux/mtd/nand_ecc.h b/include/linux/mtd/nand_ecc.h index 090da50..02ba9f7 100644 --- a/include/linux/mtd/nand_ecc.h +++ b/include/linux/mtd/nand_ecc.h @@ -1,11 +1,11 @@ /* * drivers/mtd/nand_ecc.h * - * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) + * Copyright (C) 2000-2010 Steven J. Hill <sjhill@realitydiluted.com> + * David Woodhouse <dwmw2@infradead.org> + * Thomas Gleixner <tglx@linutronix.de> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 * * This file is the header for the ECC algorithm. */ diff --git a/include/part.h b/include/part.h index 8ea9b30..8b5ac12 100644 --- a/include/part.h +++ b/include/part.h @@ -93,6 +93,9 @@ typedef struct disk_partition { #ifdef CONFIG_PARTITION_UUIDS char uuid[37]; /* filesystem UUID as string, if exists */ #endif +#ifdef CONFIG_PARTITION_TYPE_GUID + char type_guid[37]; /* type GUID as string, if exists */ +#endif } disk_partition_t; /* Misc _get_dev functions */ diff --git a/include/part_efi.h b/include/part_efi.h index 3012b91..c8fc873 100644 --- a/include/part_efi.h +++ b/include/part_efi.h @@ -43,6 +43,9 @@ #define PARTITION_BASIC_DATA_GUID \ EFI_GUID( 0xEBD0A0A2, 0xB9E5, 0x4433, \ 0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7) +#define PARTITION_LINUX_FILE_SYSTEM_DATA_GUID \ + EFI_GUID(0x0FC63DAF, 0x8483, 0x4772, \ + 0x8E, 0x79, 0x3D, 0x69, 0xD8, 0x47, 0x7D, 0xE4) #define PARTITION_LINUX_RAID_GUID \ EFI_GUID( 0xa19d880f, 0x05fc, 0x4d3b, \ 0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e) diff --git a/include/uuid.h b/include/uuid.h index 93027c1..c3f423f 100644 --- a/include/uuid.h +++ b/include/uuid.h @@ -36,6 +36,10 @@ enum { int uuid_str_valid(const char *uuid); int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format); void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format); +#ifdef CONFIG_PARTITION_TYPE_GUID +int uuid_guid_get_bin(const char *guid_str, unsigned char *guid_bin); +int uuid_guid_get_str(unsigned char *guid_bin, char *guid_str); +#endif void gen_rand_uuid(unsigned char *uuid_bin); void gen_rand_uuid_str(char *uuid_str, int str_format); #endif @@ -80,10 +80,65 @@ int uuid_str_valid(const char *uuid) return 1; } +#ifdef CONFIG_PARTITION_TYPE_GUID +static const struct { + const char *string; + efi_guid_t guid; +} list_guid[] = { + {"system", PARTITION_SYSTEM_GUID}, + {"mbr", LEGACY_MBR_PARTITION_GUID}, + {"msft", PARTITION_MSFT_RESERVED_GUID}, + {"data", PARTITION_BASIC_DATA_GUID}, + {"linux", PARTITION_LINUX_FILE_SYSTEM_DATA_GUID}, + {"raid", PARTITION_LINUX_RAID_GUID}, + {"swap", PARTITION_LINUX_SWAP_GUID}, + {"lvm", PARTITION_LINUX_LVM_GUID} +}; + +/* + * uuid_guid_get_bin() - this function get GUID bin for string + * + * @param guid_str - pointer to partition type string + * @param guid_bin - pointer to allocated array for big endian output [16B] + */ +int uuid_guid_get_bin(const char *guid_str, unsigned char *guid_bin) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(list_guid); i++) { + if (!strcmp(list_guid[i].string, guid_str)) { + memcpy(guid_bin, &list_guid[i].guid, 16); + return 0; + } + } + return -ENODEV; +} + +/* + * uuid_guid_get_str() - this function get string for GUID. + * + * @param guid_bin - pointer to string with partition type guid [16B] + * @param guid_str - pointer to allocated partition type string [7B] + */ +int uuid_guid_get_str(unsigned char *guid_bin, char *guid_str) +{ + int i; + + *guid_str = 0; + for (i = 0; i < ARRAY_SIZE(list_guid); i++) { + if (!memcmp(list_guid[i].guid.b, guid_bin, 16)) { + strcpy(guid_str, list_guid[i].string); + return 0; + } + } + return -ENODEV; +} +#endif + /* * uuid_str_to_bin() - convert string UUID or GUID to big endian binary data. * - * @param uuid_str - pointer to UUID or GUID string [37B] + * @param uuid_str - pointer to UUID or GUID string [37B] or GUID shorcut * @param uuid_bin - pointer to allocated array for big endian output [16B] * @str_format - UUID string format: 0 - UUID; 1 - GUID */ @@ -93,8 +148,13 @@ int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format) uint32_t tmp32; uint64_t tmp64; - if (!uuid_str_valid(uuid_str)) + if (!uuid_str_valid(uuid_str)) { +#ifdef CONFIG_PARTITION_TYPE_GUID + if (!uuid_guid_get_bin(uuid_str, uuid_bin)) + return 0; +#endif return -EINVAL; + } if (str_format == UUID_STR_FORMAT_STD) { tmp32 = cpu_to_be32(simple_strtoul(uuid_str, NULL, 16)); diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index dd235b9..8f690eb 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -56,6 +56,7 @@ libs-y += common/init/ libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/ libs-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/ libs-y += drivers/ +libs-y += dts/ libs-y += fs/ libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/ libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/ diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.pl index 368a20e..4707dfd 100755 --- a/scripts/get_maintainer.pl +++ b/scripts/get_maintainer.pl @@ -62,7 +62,7 @@ my %commit_author_hash; my %commit_signer_hash; my @penguin_chief = (); -push(@penguin_chief, "Tom Rini:trini\@ti.com"); +push(@penguin_chief, "Tom Rini:trini\@konsulko.com"); my @penguin_chief_names = (); foreach my $chief (@penguin_chief) { |