diff options
60 files changed, 895 insertions, 285 deletions
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index e37e87b..a90ce30 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -45,7 +45,9 @@ int cleanup_before_linux (void) /* flush I/D-cache */ static void cache_flush (void) { +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long i = 0; asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); +#endif } diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index 9e412bb..4c9d3fd 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -181,7 +181,7 @@ static void kw_sysrst_check(void) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - char *rev; + char *rev = "??"; u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff; u8 revid = readl(KW_REG_PCIE_REVID) & 0xff; @@ -192,7 +192,13 @@ int print_cpuinfo(void) switch (revid) { case 0: - rev = "Z0"; + if (devid == 0x6281) + rev = "Z0"; + else if (devid == 0x6282) + rev = "A0"; + break; + case 1: + rev = "A1"; break; case 2: rev = "A0"; @@ -201,7 +207,6 @@ int print_cpuinfo(void) rev = "A1"; break; default: - rev = "??"; break; } diff --git a/arch/arm/cpu/armv7/at91/sama5d4_devices.c b/arch/arm/cpu/armv7/at91/sama5d4_devices.c index 2708097..7469825 100644 --- a/arch/arm/cpu/armv7/at91/sama5d4_devices.c +++ b/arch/arm/cpu/armv7/at91/sama5d4_devices.c @@ -6,6 +6,10 @@ */ #include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/sama5d4.h> char *get_cpu_name() @@ -28,3 +32,15 @@ char *get_cpu_name() else return "Unknown CPU type"; } + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +void at91_udp_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable UPLL clock */ + writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + /* Enable UDPHS clock */ + at91_periph_clk_enable(ATMEL_ID_UDPHS); +} +#endif diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 989780d..71a1753 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -15,6 +15,8 @@ #include <fsl_esdhc.h> #endif #include <tsec.h> +#include <asm/arch/immap_ls102xa.h> +#include <fsl_sec.h> DECLARE_GLOBAL_DATA_PTR; @@ -77,9 +79,24 @@ void ft_cpu_setup(void *blob, bd_t *bd) int off; int val; const char *sysclk_path; + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr; + svr = in_be32(&gur->svr); unsigned long busclk = get_bus_freq(0); + /* delete crypto node if not on an E-processor */ + if (!IS_E_PROCESSOR(svr)) + fdt_fixup_crypto_node(blob, 0); +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 + else { + ccsr_sec_t __iomem *sec; + + sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); + } +#endif + fdt_fixup_ethernet(blob); off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); @@ -107,6 +124,25 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); +#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT) +#define UBOOT_HEAD_LEN 0x1000 + /* + * Reserved memory in SD boot deep sleep case. + * Second stage uboot binary and malloc space should be reserved. + * If the memory they occupied has not been reserved, then this + * space would be used by kernel and overwritten in uboot when + * deep sleep resume, which cause deep sleep failed. + * Since second uboot binary has a head, that space need to be + * reserved either(assuming its size is less than 0x1000). + */ + off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN, + CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE + + UBOOT_HEAD_LEN); + if (off < 0) + printf("Failed to reserve memory for SD boot deep sleep: %s\n", + fdt_strerror(off)); +#endif + #if defined(CONFIG_FSL_ESDHC) fdt_fixup_esdhc(blob, bd); #endif @@ -133,4 +169,17 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan", "clock-frequency", busclk / 2, 1); + +#ifdef CONFIG_QSPI_BOOT + off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, + CONFIG_SYS_IFC_ADDR); + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +#else + off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT, + QSPI0_BASE_ADDR); + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); + off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT, + DSPI1_BASE_ADDR); + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +#endif } diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 651ca40..b69fd37 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -15,8 +15,6 @@ #include <asm/io.h> #include <asm/secure.h> -unsigned long gic_dist_addr; - static unsigned int read_id_pfr1(void) { unsigned int reg; @@ -68,6 +66,12 @@ static void kick_secondary_cpus_gic(unsigned long gicdaddr) void __weak smp_kick_all_cpus(void) { + unsigned long gic_dist_addr; + + gic_dist_addr = get_gicd_base_address(); + if (gic_dist_addr == -1) + return; + kick_secondary_cpus_gic(gic_dist_addr); } @@ -75,6 +79,7 @@ int armv7_init_nonsec(void) { unsigned int reg; unsigned itlinesnr, i; + unsigned long gic_dist_addr; /* check whether the CPU supports the security extensions */ reg = read_id_pfr1(); diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile index 3363a3c..901f2ce 100644 --- a/arch/arm/cpu/armv7/zynq/Makefile +++ b/arch/arm/cpu/armv7/zynq/Makefile @@ -13,4 +13,5 @@ obj-y += cpu.o obj-y += ddrc.o obj-y += slcr.o obj-y += clk.o +obj-y += lowlevel_init.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/arm/cpu/armv7/zynq/config.mk b/arch/arm/cpu/armv7/zynq/config.mk new file mode 100644 index 0000000..778a377 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/config.mk @@ -0,0 +1,7 @@ +# +# Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0 +# +# Allow NEON instructions (needed for lowlevel_init.S with GNU toolchain) +PLATFORM_RELFLAGS += -mfpu=neon diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 816d0c5..914b1fe 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -10,10 +10,6 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/hardware.h> -void lowlevel_init(void) -{ -} - #define ZYNQ_SILICON_VER_MASK 0xF0000000 #define ZYNQ_SILICON_VER_SHIFT 28 diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index d74f8db..5b20acc 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -42,6 +42,8 @@ void zynq_ddrc_init(void) */ /* cppcheck-suppress nullPointer */ memset((void *)0, 0, 1 * 1024 * 1024); + + gd->ram_size /= 2; } else { puts("ECC disabled "); } diff --git a/arch/arm/cpu/armv7/zynq/lowlevel_init.S b/arch/arm/cpu/armv7/zynq/lowlevel_init.S new file mode 100644 index 0000000..6d714b7 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/lowlevel_init.S @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2013 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + + /* Enable the the VFP */ + mrc p15, 0, r1, c1, c0, 2 + orr r1, r1, #(0x3 << 20) + orr r1, r1, #(0x3 << 20) + mcr p15, 0, r1, c1, c0, 2 + isb + fmrx r1, FPEXC + orr r1,r1, #(1<<30) + fmxr FPEXC, r1 + + /* Move back to caller */ + mov pc, lr + +ENDPROC(lowlevel_init) diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 934ccc3..2521589 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -132,7 +132,7 @@ void zynq_slcr_devcfg_disable(void) zynq_slcr_unlock(); /* Disable AXI interface by asserting FPGA resets */ - writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl); + writel(0xF, &slcr_base->fpga_rst_ctrl); /* Set Level Shifters DT618760 */ writel(0xA, &slcr_base->lvl_shftr_en); diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c index 0936bdd..b80c357 100644 --- a/arch/arm/cpu/armv7/zynq/spl.c +++ b/arch/arm/cpu/armv7/zynq/spl.c @@ -43,12 +43,21 @@ u32 spl_boot_device(void) mode = BOOT_DEVICE_SPI; break; #endif + case ZYNQ_BM_NAND: + mode = BOOT_DEVICE_NAND; + break; + case ZYNQ_BM_NOR: + mode = BOOT_DEVICE_NOR; + break; #ifdef CONFIG_SPL_MMC_SUPPORT case ZYNQ_BM_SD: puts("mmc boot\n"); mode = BOOT_DEVICE_MMC1; break; #endif + case ZYNQ_BM_JTAG: + mode = BOOT_DEVICE_RAM; + break; default: puts("Unsupported boot mode selected\n"); hang(); diff --git a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h b/arch/arm/include/asm/arch-at91/atmel_usba_udc.h index 6f540d2..38b5012 100644 --- a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h +++ b/arch/arm/include/asm/arch-at91/atmel_usba_udc.h @@ -31,7 +31,7 @@ static struct usba_ep_data usba_udc_ep[] = { EP("ep5", 5, 1024, 3, 1, 1), EP("ep6", 6, 1024, 3, 1, 1), }; -#elif defined(CONFIG_SAMA5D3) +#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) static struct usba_ep_data usba_udc_ep[] = { EP("ep0", 0, 64, 1, 0, 0), EP("ep1", 1, 1024, 3, 1, 0), diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 5e934da..7915518 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -97,8 +97,13 @@ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_FSL_ERRATUM_A008378 #else #error SoC not defined #endif +#define FSL_IFC_COMPAT "fsl,ifc" +#define FSL_QSPI_COMPAT "fsl,ls1-qspi" +#define FSL_DSPI_COMPAT "fsl,vf610-dspi" + #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h new file mode 100644 index 0000000..b704436 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/gpio.h @@ -0,0 +1,15 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Dummy header file to enable CONFIG_OF_CONTROL. + * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. + * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable + * OF_CONTROL must have arch/gpio.h. + */ + +#ifndef __ASM_ARCH_LS102XA_GPIO_H_ +#define __ASM_ARCH_LS102XA_GPIO_H_ + +#endif diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 697d4ca..f70d568 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -105,6 +105,8 @@ struct ccsr_gur { #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 +#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 +#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 #define SCFG_QSPI_CLKSEL 0xc0100000 @@ -456,6 +458,8 @@ struct ccsr_ddr { #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 #define CCI400_CTRLORD_EN_BARRIER 0 #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 +#define CCI400_SNOOP_REQ_EN 0x00000001 /* CCI-400 registers */ struct ccsr_cci400 { diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 2aede0c..e2e0b73 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -21,6 +21,9 @@ #define ZYNQ_I2C_BASEADDR1 0xE0005000 #define ZYNQ_SPI_BASEADDR0 0xE0006000 #define ZYNQ_SPI_BASEADDR1 0xE0007000 +#define ZYNQ_QSPI_BASEADDR 0xE000D000 +#define ZYNQ_SMC_BASEADDR 0xE000E000 +#define ZYNQ_NAND_BASEADDR 0xE1000000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 #define ZYNQ_EFUSE_BASEADDR 0xF800D000 #define ZYNQ_USB_BASEADDR0 0xE0002000 @@ -28,7 +31,9 @@ /* Bootmode setting values */ #define ZYNQ_BM_MASK 0x7 +#define ZYNQ_BM_QSPI 0x1 #define ZYNQ_BM_NOR 0x2 +#define ZYNQ_BM_NAND 0x4 #define ZYNQ_BM_SD 0x5 #define ZYNQ_BM_JTAG 0x0 diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 9cedeac..74cfde6 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -25,10 +25,12 @@ __weak void flush_cache(unsigned long start, unsigned long size) #endif /* CONFIG_CPU_ARM1136 */ #ifdef CONFIG_CPU_ARM926EJS +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) /* test and clean, page 2-23 of arm926ejs manual */ asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); +#endif #endif /* CONFIG_CPU_ARM926EJS */ return; } diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 1c63f93..9cc1676 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -73,176 +73,6 @@ void ft_fixup_num_cores(void *blob) { } #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */ -/* - * update crypto node properties to a specified revision of the SEC - * called with sec_rev == 0 if not on an E processor - */ -#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */ -void fdt_fixup_crypto_node(void *blob, int sec_rev) -{ - static const struct sec_rev_prop { - u32 sec_rev; - u32 num_channels; - u32 channel_fifo_len; - u32 exec_units_mask; - u32 descriptor_types_mask; - } sec_rev_prop_list [] = { - { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */ - { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */ - { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */ - { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */ - { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */ - { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */ - { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */ - }; - static char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) * - sizeof("fsl,secX.Y")]; - int crypto_node, sec_idx, err; - char *p; - u32 val; - - /* locate crypto node based on lowest common compatible */ - crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0"); - if (crypto_node == -FDT_ERR_NOTFOUND) - return; - - /* delete it if not on an E-processor */ - if (crypto_node > 0 && !sec_rev) { - fdt_del_node(blob, crypto_node); - return; - } - - /* else we got called for possible uprev */ - for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++) - if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev) - break; - - if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) { - puts("warning: unknown SEC revision number\n"); - return; - } - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels); - err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask); - err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask); - err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len); - err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = 0; - while (sec_idx >= 0) { - p = compat_strlist + val; - val += sprintf(p, "fsl,sec%d.%d", - (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8, - sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1; - sec_idx--; - } - err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); -} -#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */ -static u8 caam_get_era(void) -{ - static const struct { - u16 ip_id; - u8 maj_rev; - u8 era; - } caam_eras[] = { - {0x0A10, 1, 1}, - {0x0A10, 2, 2}, - {0x0A12, 1, 3}, - {0x0A14, 1, 3}, - {0x0A14, 2, 4}, - {0x0A16, 1, 4}, - {0x0A10, 3, 4}, - {0x0A11, 1, 4}, - {0x0A18, 1, 4}, - {0x0A11, 2, 5}, - {0x0A12, 2, 5}, - {0x0A13, 1, 5}, - {0x0A1C, 1, 5} - }; - - ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; - u32 secvid_ms = sec_in32(&sec->secvid_ms); - u32 ccbvid = sec_in32(&sec->ccbvid); - u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >> - SEC_SECVID_MS_IPID_SHIFT; - u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >> - SEC_SECVID_MS_MAJ_REV_SHIFT; - u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT; - - int i; - - if (era) /* This is '0' prior to CAAM ERA-6 */ - return era; - - for (i = 0; i < ARRAY_SIZE(caam_eras); i++) - if (caam_eras[i].ip_id == ip_id && - caam_eras[i].maj_rev == maj_rev) - return caam_eras[i].era; - - return 0; -} - -static void fdt_fixup_crypto_era(void *blob, u32 era) -{ - int err; - int crypto_node; - - crypto_node = fdt_path_offset(blob, "crypto"); - if (crypto_node < 0) { - printf("WARNING: Missing crypto node\n"); - return; - } - - err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era, - sizeof(era)); - if (err < 0) { - printf("ERROR: could not set fsl,sec-era property: %s\n", - fdt_strerror(err)); - } -} - -void fdt_fixup_crypto_node(void *blob, int sec_rev) -{ - u8 era; - - if (!sec_rev) { - fdt_del_node_and_alias(blob, "crypto"); - return; - } - - /* Add SEC ERA information in compatible */ - era = caam_get_era(); - if (era) { - fdt_fixup_crypto_era(blob, era); - } else { - printf("WARNING: Unable to get ERA for CAAM rev: %d\n", - sec_rev); - } -} -#endif - int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { return fdt_setprop_string(blob, offset, "phy-connection-type", diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 423a6fb..65496d0 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -75,6 +75,7 @@ * SEC (crypto unit) major compatible version determination */ #if defined(CONFIG_MPC83xx) +#define CONFIG_SYS_FSL_SEC_BE #define CONFIG_SYS_FSL_SEC_COMPAT 2 #endif diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 2758c5c..1c5b92c 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -10,6 +10,7 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/atmel_usba_udc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> #include <asm/arch/sama5d3_smc.h> @@ -294,6 +295,9 @@ int board_init(void) #ifdef CONFIG_CMD_USB sama5d4_xplained_usb_hw_init(); #endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); +#endif return 0; } @@ -313,5 +317,12 @@ int board_eth_init(bd_t *bis) rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); #endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + usba_udc_probe(&pdata); +#ifdef CONFIG_USB_ETH_RNDIS + usb_eth_initialize(bis); +#endif +#endif + return rc; } diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index d3039c0..d8ff648 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -10,6 +10,7 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/atmel_usba_udc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> #include <asm/arch/sama5d3_smc.h> @@ -293,6 +294,9 @@ int board_init(void) #ifdef CONFIG_CMD_USB sama5d4ek_usb_hw_init(); #endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); +#endif return 0; } @@ -312,5 +316,12 @@ int board_eth_init(bd_t *bis) rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); #endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + usba_udc_probe(&pdata); +#ifdef CONFIG_USB_ETH_RNDIS + usb_eth_initialize(bis); +#endif +#endif + return rc; } diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS index 638833d..661526b 100644 --- a/board/freescale/ls1021aqds/MAINTAINERS +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -6,6 +6,7 @@ F: include/configs/ls1021aqds.h F: configs/ls1021aqds_nor_defconfig F: configs/ls1021aqds_ddr4_nor_defconfig F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig +F: configs/ls1021aqds_nor_lpuart_defconfig F: configs/ls1021aqds_sdcard_defconfig F: configs/ls1021aqds_qspi_defconfig F: configs/ls1021aqds_nand_defconfig diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile index 3b6903c..ab02344 100644 --- a/board/freescale/ls1021aqds/Makefile +++ b/board/freescale/ls1021aqds/Makefile @@ -7,3 +7,4 @@ obj-y += ls1021aqds.o obj-y += ddr.o obj-y += eth.o +obj-$(CONFIG_FSL_DCU_FB) += dcu.o diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c new file mode 100644 index 0000000..90f5bc0 --- /dev/null +++ b/board/freescale/ls1021aqds/dcu.c @@ -0,0 +1,92 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <common.h> +#include <fsl_dcu_fb.h> +#include <i2c.h> +#include "div64.h" +#include "../common/diu_ch7301.h" +#include "ls1021aqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +unsigned int dcu_set_pixel_clock(unsigned int pixclock) +{ + unsigned long long div; + + div = (unsigned long long)(gd->bus_clk / 1000); + div *= (unsigned long long)pixclock; + do_div(div, 1000000000); + + return div; +} + +int platform_dcu_init(unsigned int xres, unsigned int yres, + const char *port, + struct fb_videomode *dcu_fb_videomode) +{ + const char *name; + unsigned int pixel_format; + int ret; + u8 ch; + + /* Mux I2C3+I2C4 as HSYNC+VSYNC */ + ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5, + 1, &ch, 1); + if (ret) { + printf("Error: failed to read I2C @%02x\n", + CONFIG_SYS_I2C_QIXIS_ADDR); + return ret; + } + ch &= 0x1F; + ch |= 0xA0; + ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5, + 1, &ch, 1); + if (ret) { + printf("Error: failed to write I2C @%02x\n", + CONFIG_SYS_I2C_QIXIS_ADDR); + return ret; + } + + if (strncmp(port, "hdmi", 4) == 0) { + unsigned long pixval; + + name = "HDMI"; + + pixval = 1000000000 / dcu_fb_videomode->pixclock; + pixval *= 1000; + + i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM); + select_i2c_ch_pca9547(I2C_MUX_CH_CH7301); + diu_set_dvi_encoder(pixval); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + } else { + return 0; + } + + printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); + + pixel_format = 32; + fsl_dcu_init(xres, yres, pixel_format); + + return 0; +} diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index a539ff9..6435bf9 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -7,6 +7,7 @@ #include <common.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> +#include <asm/io.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; @@ -149,6 +150,17 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, } #endif +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *qixis_base = (void *)QIXIS_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(qixis_base + 0x21, 0x2); + udelay(1); +} +#endif + phys_size_t initdram(int board_type) { phys_size_t dram_size; @@ -159,6 +171,11 @@ phys_size_t initdram(int board_type) #else dram_size = fsl_ddr_sdram_size(); #endif + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + return dram_size; } diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 152da2d..20eade4 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -20,6 +20,7 @@ #include <fsl_sec.h> #include <spl.h> +#include "../common/sleep.h" #include "../common/qixis.h" #include "ls1021aqds_qixis.h" #ifdef CONFIG_U_QE @@ -48,6 +49,12 @@ enum { MUX_TYPE_SD_PC_SG_SG, }; +enum { + GE0_CLK125, + GE2_CLK125, + GE1_CLK125, +}; + int checkboard(void) { #ifndef CONFIG_QSPI_BOOT @@ -177,7 +184,6 @@ int board_early_init_f(void) #ifdef CONFIG_TSEC_ENET out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); - out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); #endif #ifdef CONFIG_FSL_IFC @@ -188,6 +194,24 @@ int board_early_init_f(void) out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif +#ifdef CONFIG_FSL_DCU_FB + out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); +#endif + + /* + * Enable snoop requests and DVM message requests for + * Slave insterface S4 (A7 core cluster) + */ + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override Register + * All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + /* Workaround for the issue that DDR could not respond to * barrier transaction which is generated by executing DSB/ISB * instruction. Set CCI-400 control override register to @@ -195,6 +219,11 @@ int board_early_init_f(void) * allow barrier transaction to DDR again */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + return 0; } @@ -228,6 +257,11 @@ void board_init_f(ulong dummy) get_clocks(); +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + preloader_console_init(); #ifdef CONFIG_SPL_I2C_SUPPORT @@ -241,6 +275,32 @@ void board_init_f(ulong dummy) } #endif +void config_etseccm_source(int etsec_gtx_125_mux) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + + switch (etsec_gtx_125_mux) { + case GE0_CLK125: + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125); + debug("etseccm set to GE0_CLK125\n"); + break; + + case GE2_CLK125: + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); + debug("etseccm set to GE2_CLK125\n"); + break; + + case GE1_CLK125: + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125); + debug("etseccm set to GE1_CLK125\n"); + break; + + default: + printf("Error! trying to set etseccm to invalid value\n"); + break; + } +} + int config_board_mux(int ctrl_type) { u8 reg12, reg14; @@ -250,6 +310,7 @@ int config_board_mux(int ctrl_type) switch (ctrl_type) { case MUX_TYPE_CAN: + config_etseccm_source(GE2_CLK125); reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); break; case MUX_TYPE_IIC2: @@ -259,6 +320,7 @@ int config_board_mux(int ctrl_type) reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); break; case MUX_TYPE_SAI: + config_etseccm_source(GE2_CLK125); reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); break; case MUX_TYPE_SDHC: @@ -471,13 +533,6 @@ int board_init(void) /* Set CCI-400 control override register to * enable barrier transaction */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); - /* - * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register - * All transactions are treated as non-shareable - */ - out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); @@ -500,6 +555,21 @@ int board_init(void) return 0; } +#if defined(CONFIG_DEEP_SLEEP) +void board_sleep_prepare(void) +{ + struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + + /* Set CCI-400 control override register to + * enable barrier transaction */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_LS102XA_NS_ACCESS + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#endif +} +#endif + int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); diff --git a/board/freescale/ls1021aqds/ls1021aqds_qixis.h b/board/freescale/ls1021aqds/ls1021aqds_qixis.h index 09b3be2..8e482eb 100644 --- a/board/freescale/ls1021aqds/ls1021aqds_qixis.h +++ b/board/freescale/ls1021aqds/ls1021aqds_qixis.h @@ -32,4 +32,6 @@ #define QIXIS_SRDS1CLK_100 0x0 +#define QIXIS_DCU_BRDCFG5 0x55 + #endif diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS index 9176706..e9f6f0a 100644 --- a/board/freescale/ls1021atwr/MAINTAINERS +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -5,5 +5,6 @@ F: board/freescale/ls1021atwr/ F: include/configs/ls1021atwr.h F: configs/ls1021atwr_nor_defconfig F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig +F: configs/ls1021atwr_nor_lpuart_defconfig F: configs/ls1021atwr_sdcard_defconfig F: configs/ls1021atwr_qspi_defconfig diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 027b67e..bc8b006 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -263,6 +263,7 @@ int config_serdes_mux(void) int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; #ifdef CONFIG_TSEC_ENET out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); @@ -281,6 +282,20 @@ int board_early_init_f(void) out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif + /* + * Enable snoop requests and DVM message requests for + * Slave insterface S4 (A7 core cluster) + */ + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override Register + * All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + return 0; } @@ -405,16 +420,6 @@ struct smmu_stream_id dev_stream_id[] = { int board_init(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - - /* - * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register - * All transactions are treated as non-shareable - */ - out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); #ifndef CONFIG_QSPI_BOOT diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg index 3c63a03..f4260fa 100644 --- a/board/iomega/iconnect/kwbimage.cfg +++ b/board/iomega/iconnect/kwbimage.cfg @@ -20,7 +20,7 @@ NAND_PAGE_SIZE 0x0800 # Configure RGMII-0 interface pad voltage to 1.8V DATA 0xffd100e0 0x1b1b1b9b -#Dram initalization for SINGLE x16 CL=5 @ 400MHz +# Dram initalization for SINGLE x16 CL=5 @ 400MHz DATA 0xffd01400 0x43000c30 # DDR Configuration register # bit13-0: 0xc30, (3120 DDR2 clks refresh rate) # bit23-14: 0x0, @@ -87,7 +87,7 @@ DATA 0xffd0141c 0x00000c52 # DDR Mode # bit6-4: 0x4, CL=5 # bit7: 0x0, TestMode=0 normal # bit8: 0x0, DLL reset=0 normal -# bit11-9: 0x6, auto-precharge write recovery ???????????? +# bit11-9: 0x6, auto-precharge write recovery # bit12: 0x0, PD must be zero # bit31-13: 0x0, required diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg index 596071f..ec00c15 100644 --- a/board/raidsonic/ib62x0/kwbimage.cfg +++ b/board/raidsonic/ib62x0/kwbimage.cfg @@ -11,7 +11,7 @@ # # Boot Media configurations -BOOT_FROM nand # change from nand to uart if building UART image +BOOT_FROM nand NAND_ECC_MODE default NAND_PAGE_SIZE 0x0800 @@ -21,12 +21,12 @@ NAND_PAGE_SIZE 0x0800 # Configure RGMII-0 interface pad voltage to 1.8V DATA 0xffd100e0 0x1b1b1b9b -#Dram initalization for SINGLE x16 CL=5 @ 400MHz +# Dram initalization for SINGLE x16 CL=5 @ 400MHz DATA 0xffd01400 0x43000c30 # DDR Configuration register # bit13-0: 0xc30, (3120 DDR2 clks refresh rate) # bit23-14: 0x0, -# bit24: 0x1, enable exit self refresh mode on DDR access -# bit25: 0x1, required +# bit24: 0x1, enable exit self refresh mode on DDR access +# bit25: 0x1, required # bit29-26: 0x0, # bit31-30: 0x1, @@ -64,10 +64,10 @@ DATA 0xffd01410 0x0000000c # DDR Address Control # bit3-2: 11, Cs0size (1Gb) # bit5-4: 00, Cs1width (x8) # bit7-6: 11, Cs1size (1Gb) -# bit9-8: 00, Cs2width (nonexistent -# bit11-10: 00, Cs2size (nonexistent -# bit13-12: 00, Cs3width (nonexistent -# bit15-14: 00, Cs3size (nonexistent +# bit9-8: 00, Cs2width (nonexistent) +# bit11-10: 00, Cs2size (nonexistent) +# bit13-12: 00, Cs3width (nonexistent) +# bit15-14: 00, Cs3size (nonexistent) # bit16: 0, Cs0AddrSel # bit17: 0, Cs1AddrSel # bit18: 0, Cs2AddrSel @@ -88,7 +88,7 @@ DATA 0xffd0141c 0x00000c52 # DDR Mode # bit6-4: 0x4, CL=5 # bit7: 0x0, TestMode=0 normal # bit8: 0x0, DLL reset=0 normal -# bit11-9: 0x6, auto-precharge write recovery ???????????? +# bit11-9: 0x6, auto-precharge write recovery # bit12: 0x0, PD must be zero # bit31-13: 0x0, required @@ -148,8 +148,8 @@ DATA 0xffd0149c 0x0000e803 # CPU ODT Control DATA 0xffd01480 0x00000001 # DDR Initialization Control # bit0: 0x1, enable DDR init upon this register write -DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register -DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +DATA 0xffd20134 0x66666666 # L2 RAM Timing 0 Register +DATA 0xffd20138 0x66666666 # L2 RAM Timing 1 Register # End of Header extension DATA 0x0 0x0 diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index 0a11540..f3f6dae 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -43,13 +43,13 @@ static void corvus_nand_hw_init(void) writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | - AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), &smc->cs[3].cycle); writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | AT91_SMC_MODE_EXNW_DISABLE | @@ -62,9 +62,11 @@ static void corvus_nand_hw_init(void) &smc->cs[3].mode); at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOA); /* Enable NandFlash */ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); } #if defined(CONFIG_SPL_BUILD) diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index b8ff478..013dac2 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -68,6 +68,7 @@ static void taurus_nand_hw_init(void) #if defined(CONFIG_SPL_BUILD) #include <spl.h> #include <nand.h> +#include <spi_flash.h> void matrix_init(void) { @@ -81,23 +82,28 @@ void matrix_init(void) void at91_spl_board_init(void) { taurus_nand_hw_init(); + at91_spi0_hw_init(TAURUS_SPI_MASK); /* Configure recovery button PINs */ at91_set_gpio_input(AT91_PIN_PA31, 1); /* check if button is pressed */ if (at91_get_gpio_value(AT91_PIN_PA31) == 0) { - u32 boot_device; + struct spi_flash *flash; debug("Recovery button pressed\n"); - boot_device = spl_boot_device(); - switch (boot_device) { -#ifdef CONFIG_SPL_NAND_SUPPORT - case BOOT_DEVICE_NAND: - nand_init(); - spl_nand_erase_one(0, 0); - break; -#endif + nand_init(); + spl_nand_erase_one(0, 0); + flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, + 0, + CONFIG_SF_DEFAULT_SPEED, + SPI_MODE_3); + if (!flash) { + puts("no flash\n"); + } else { + puts("erase spi flash sector 0\n"); + spi_flash_erase(flash, 0, + CONFIG_SYS_NAND_U_BOOT_SIZE); } } } diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 3a2198f..738c31c 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -91,6 +91,14 @@ int board_late_init(void) return 0; } +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + puts("Board:\tXilinx Zynq\n"); + return 0; +} +#endif + int board_eth_init(bd_t *bis) { u32 ret = 0; @@ -115,11 +123,13 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_ZYNQ_GEM) # if defined(CONFIG_ZYNQ_GEM0) ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, - CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); + CONFIG_ZYNQ_GEM_PHY_ADDR0, + CONFIG_ZYNQ_GEM_EMIO0); # endif # if defined(CONFIG_ZYNQ_GEM1) ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, - CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); + CONFIG_ZYNQ_GEM_PHY_ADDR1, + CONFIG_ZYNQ_GEM_EMIO1); # endif #endif return ret; diff --git a/configs/axm_defconfig b/configs/axm_defconfig index c0e8da2..076ad0f 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -1,3 +1,4 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM" -CONFIG_ARM=y -CONFIG_TARGET_TAURUS=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_TAURUS=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig new file mode 100644 index 0000000..29335ee --- /dev/null +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="LPUART" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig new file mode 100644 index 0000000..bdab6d9 --- /dev/null +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="LPUART" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021ATWR=y diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index cb13d2e..067d0a9 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -6,5 +6,6 @@ # Version 2 as published by the Free Software Foundation. # +obj-y += sec.o obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o obj-$(CONFIG_CMD_BLOB) += fsl_blob.o diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c new file mode 100644 index 0000000..443ee96 --- /dev/null +++ b/drivers/crypto/fsl/sec.c @@ -0,0 +1,184 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> +#if CONFIG_SYS_FSL_SEC_COMPAT == 2 || CONFIG_SYS_FSL_SEC_COMPAT >= 4 +#include <fsl_sec.h> +#endif + +/* + * update crypto node properties to a specified revision of the SEC + * called with sec_rev == 0 if not on an E processor + */ +#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */ +void fdt_fixup_crypto_node(void *blob, int sec_rev) +{ + static const struct sec_rev_prop { + u32 sec_rev; + u32 num_channels; + u32 channel_fifo_len; + u32 exec_units_mask; + u32 descriptor_types_mask; + } sec_rev_prop_list[] = { + { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */ + { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */ + { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */ + { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */ + { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */ + { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */ + { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */ + }; + static char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) * + sizeof("fsl,secX.Y")]; + int crypto_node, sec_idx, err; + char *p; + u32 val; + + /* locate crypto node based on lowest common compatible */ + crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0"); + if (crypto_node == -FDT_ERR_NOTFOUND) + return; + + /* delete it if not on an E-processor */ + if (crypto_node > 0 && !sec_rev) { + fdt_del_node(blob, crypto_node); + return; + } + + /* else we got called for possible uprev */ + for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++) + if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev) + break; + + if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) { + puts("warning: unknown SEC revision number\n"); + return; + } + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels); + err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask); + err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", + &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask); + err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len); + err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = 0; + while (sec_idx >= 0) { + p = compat_strlist + val; + val += sprintf(p, "fsl,sec%d.%d", + (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8, + sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1; + sec_idx--; + } + err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, + val); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); +} +#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */ +static u8 caam_get_era(void) +{ + static const struct { + u16 ip_id; + u8 maj_rev; + u8 era; + } caam_eras[] = { + {0x0A10, 1, 1}, + {0x0A10, 2, 2}, + {0x0A12, 1, 3}, + {0x0A14, 1, 3}, + {0x0A14, 2, 4}, + {0x0A16, 1, 4}, + {0x0A10, 3, 4}, + {0x0A11, 1, 4}, + {0x0A18, 1, 4}, + {0x0A11, 2, 5}, + {0x0A12, 2, 5}, + {0x0A13, 1, 5}, + {0x0A1C, 1, 5} + }; + + ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + u32 secvid_ms = sec_in32(&sec->secvid_ms); + u32 ccbvid = sec_in32(&sec->ccbvid); + u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >> + SEC_SECVID_MS_IPID_SHIFT; + u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >> + SEC_SECVID_MS_MAJ_REV_SHIFT; + u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT; + + int i; + + if (era) /* This is '0' prior to CAAM ERA-6 */ + return era; + + for (i = 0; i < ARRAY_SIZE(caam_eras); i++) + if (caam_eras[i].ip_id == ip_id && + caam_eras[i].maj_rev == maj_rev) + return caam_eras[i].era; + + return 0; +} + +static void fdt_fixup_crypto_era(void *blob, u32 era) +{ + int err; + int crypto_node; + + crypto_node = fdt_path_offset(blob, "crypto"); + if (crypto_node < 0) { + printf("WARNING: Missing crypto node\n"); + return; + } + + err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era, + sizeof(era)); + if (err < 0) { + printf("ERROR: could not set fsl,sec-era property: %s\n", + fdt_strerror(err)); + } +} + +void fdt_fixup_crypto_node(void *blob, int sec_rev) +{ + u8 era; + + if (!sec_rev) { + fdt_del_node_and_alias(blob, "crypto"); + return; + } + + /* Add SEC ERA information in compatible */ + era = caam_get_era(); + if (era) { + fdt_fixup_crypto_era(blob, era); + } else { + printf("WARNING: Unable to get ERA for CAAM rev: %d\n", + sec_rev); + } +} +#endif diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index a3c01e7..4eef047 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -171,6 +171,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->debug[i], regs->debug[i]); } } +#ifdef CONFIG_SYS_FSL_ERRATUM_A008378 + /* Erratum applies when accumulated ECC is used, or DBI is enabled */ +#define IS_ACC_ECC_EN(v) ((v) & 0x4) +#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) + if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || + IS_DBI(regs->ddr_sdram_cfg_3)) + ddr_setbits32(ddr->debug[28], 0x9 << 20); +#endif /* * For RDIMMs, JEDEC spec requires clocks to be stable before reset is diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 6ef6cac..6b31a82 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -35,6 +35,10 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_MVGBE_PORTS +# define CONFIG_MVGBE_PORTS {0, 0} +#endif + #define MV_PHY_ADR_REQUEST 0xee #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 1ff27d5..3e2b8dc 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -27,14 +27,14 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ struct uart_zynq { - u32 control; /* Control Register [8:0] */ - u32 mode; /* Mode Register [10:0] */ + u32 control; /* 0x0 - Control Register [8:0] */ + u32 mode; /* 0x4 - Mode Register [10:0] */ u32 reserved1[4]; - u32 baud_rate_gen; /* Baud Rate Generator [15:0] */ + u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */ u32 reserved2[4]; - u32 channel_sts; /* Channel Status [11:0] */ - u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */ - u32 baud_rate_divider; /* Baud Rate Divider [7:0] */ + u32 channel_sts; /* 0x2c - Channel Status [11:0] */ + u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */ + u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ }; static struct uart_zynq *uart_zynq_ports[2] = { @@ -42,29 +42,13 @@ static struct uart_zynq *uart_zynq_ports[2] = { [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1, }; -#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) -# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE -#endif -#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) -# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE -#endif - -struct uart_zynq_params { - u32 baudrate; -}; - -static struct uart_zynq_params uart_zynq_ports_param[2] = { - [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0, - [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1, -}; - /* Set up the baud rate in gd struct */ static void uart_zynq_serial_setbrg(const int port) { /* Calculation results. */ unsigned int calc_bauderror, bdiv, bgen; unsigned long calc_baud = 0; - unsigned long baud = uart_zynq_ports_param[port].baudrate; + unsigned long baud = gd->baudrate; unsigned long clock = get_uart_clk(port); struct uart_zynq *regs = uart_zynq_ports[port]; diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 5b50c1d..ace511f 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -18,6 +18,7 @@ #define MACH_TYPE_CORVUS 2066 +#define CONFIG_MACH_TYPE MACH_TYPE_CORVUS #define CONFIG_SYS_GENERIC_BOARD /* * Warning: changing CONFIG_SYS_TEXT_BASE requires @@ -106,6 +107,7 @@ /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 #endif /* Ethernet */ @@ -171,7 +173,6 @@ #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_BASE @@ -184,7 +185,6 @@ #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_SIZE (256*1024*1024) #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index 46a42b3..ec7f721 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -12,6 +12,8 @@ #ifndef _CONFIG_DOCKSTAR_H #define _CONFIG_DOCKSTAR_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 5ed9497..836515d 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -15,6 +15,8 @@ #ifndef _CONFIG_GOFLEXHOME_H #define _CONFIG_GOFLEXHOME_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index a56a4cb..8e53af8 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -1,5 +1,6 @@ /* - * (C) Copyright 2009 + * (C) Copyright 2009-2014 + * Gerald Kerma <dreagle@doukki.net> * Marvell Semiconductor <www.marvell.com> * Written-by: Siddarth Gore <gores@marvell.com> * @@ -9,6 +10,8 @@ #ifndef _CONFIG_GURUPLUG_H #define _CONFIG_GURUPLUG_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ @@ -23,17 +26,36 @@ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* + * Compression configuration + */ +#define CONFIG_BZIP2 +#define CONFIG_LZMA +#define CONFIG_LZO + +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ + +/* * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include <config_cmd_default.h> +#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV -#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MII #define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_USB -#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT /* * mv-common.h should be defined after CMD configs since it used them @@ -55,24 +77,38 @@ * it has to be rounded to sector size */ #define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x60000 -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ +#define CONFIG_ENV_OFFSET 0xE0000 /* env starts here */ /* * Default environment variables */ -#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \ - "${x_bootcmd_ethernet}; setenv ethact egiga1; " \ - "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "bootm 0x6400000;" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "x_bootcmd_ethernet=ping 192.168.2.1\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootcmd_kernel=nand read.e 0x6400000 0x100000 0x400000\0" \ - "x_bootargs=console=ttyS0,115200\0" \ - "x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount ubi:rootfs; " \ + "ubifsload 0x800000 ${kernel}; " \ + "ubifsload 0x700000 ${fdt}; " \ + "ubifsumount; " \ + "fdt addr 0x700000; fdt resize; fdt chosen; " \ + "bootz 0x800000 - 0x700000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "896K(uboot),128K(uboot_env)," \ + "-@1M(root)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS \ + "kernel=/boot/zImage\0" \ + "fdt=/boot/guruplug-server-plus.dtb\0" \ + "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" + +#define MTDIDS_DEFAULT "nand0=orion_nand" + +#define MTDPARTS_DEFAULT \ + "mtdparts="CONFIG_MTDPARTS /* * Ethernet Driver configuration @@ -89,6 +125,20 @@ #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET #endif /*CONFIG_MVSATA_IDE*/ +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS + #define CONFIG_SYS_ALT_MEMTEST #endif /* _CONFIG_GURUPLUG_H */ diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index f4c748a..f1ddf21 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -9,6 +9,8 @@ #ifndef _CONFIG_IB62x0_H #define _CONFIG_IB62x0_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index 9f4a4b8..2baf50c 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -9,6 +9,8 @@ #ifndef _CONFIG_ICONNECT_H #define _CONFIG_ICONNECT_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 8dc04f2..2874ccc 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -19,6 +19,11 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) +#define CONFIG_SILENT_CONSOLE +#endif + /* * Size of malloc() pool */ @@ -72,7 +77,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPL_PAD_TO 0x1c000 #define CONFIG_SYS_TEXT_BASE 0x82000000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 @@ -365,11 +371,16 @@ unsigned long get_board_ddr_clk(void); /* * Serial Port */ +#ifdef CONFIG_LPUART +#define CONFIG_FSL_LPUART +#define CONFIG_LPUART_32B_REG +#else #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif #define CONFIG_BAUDRATE 115200 @@ -385,6 +396,7 @@ unsigned long get_board_ddr_clk(void); */ #define I2C_MUX_PCA_ADDR_PRI 0x77 #define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_CH7301 0xC /* * MMC @@ -427,6 +439,25 @@ unsigned long get_board_ddr_clk(void); #endif /* + * Video + */ +#define CONFIG_FSL_DCU_FB + +#ifdef CONFIG_FSL_DCU_FB +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO + +#define CONFIG_FSL_DIU_CH7301 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 +#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 +#define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#endif + +/* * eTSEC */ #define CONFIG_TSEC_ENET @@ -508,11 +539,19 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 +#ifdef CONFIG_LPUART +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ + "fdt_high=0xcfffffff\0" \ + "initrd_high=0xcfffffff\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" +#else #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "fdt_high=0xcfffffff\0" \ "initrd_high=0xcfffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" +#endif /* * Miscellaneous configurable options diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 66954d0..0a0bb5f 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -186,11 +186,16 @@ /* * Serial Port */ +#ifdef CONFIG_LPUART +#define CONFIG_FSL_LPUART +#define CONFIG_LPUART_32B_REG +#else #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif #define CONFIG_BAUDRATE 115200 @@ -325,10 +330,17 @@ #define CONFIG_BOOTDELAY 3 +#ifdef CONFIG_LPUART +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ + "initrd_high=0xcfffffff\0" \ + "fdt_high=0xcfffffff\0" +#else #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xcfffffff\0" \ "fdt_high=0xcfffffff\0" +#endif /* * Miscellaneous configurable options diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h index 7594bdb..89560ad 100644 --- a/include/configs/pogo_e02.h +++ b/include/configs/pogo_e02.h @@ -13,6 +13,8 @@ #ifndef _CONFIG_POGO_E02_H #define _CONFIG_POGO_E02_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Machine type definition and ID */ diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index d5588b1..9458047 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -246,6 +246,7 @@ #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER #endif diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 104edef..996973d 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -121,6 +121,14 @@ #define CONFIG_USB_STORAGE #endif +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK" + #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index cbdb3a2..09ab4d7 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -121,6 +121,14 @@ #define CONFIG_USB_STORAGE #endif +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK" + #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 71be823..21c8bda 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -10,6 +10,8 @@ #ifndef _CONFIG_SHEEVAPLUG_H #define _CONFIG_SHEEVAPLUG_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 942af2e..9fa644f 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -34,7 +34,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SKIP_RELOCATE_UBOOT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_FIT diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 20194ae..65468ad 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -26,6 +26,11 @@ #define CONFIG_SYS_GENERIC_BOARD +#if defined(CONFIG_SPL_BUILD) +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#endif /* * Warning: changing CONFIG_SYS_TEXT_BASE requires * adapting the initial boot program. @@ -137,6 +142,19 @@ #define TAURUS_SPI_MASK (1 << 4) #define TAURUS_SPI_CS_PIN AT91_PIN_PA3 +#if defined(CONFIG_SPL_BUILD) +/* SPL related */ +#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + /* load address */ #define CONFIG_SYS_LOAD_ADDR 0x22000000 @@ -171,8 +189,11 @@ /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x0 -#define CONFIG_SPL_MAX_SIZE (11 * 1024) +#define CONFIG_SPL_MAX_SIZE (14 * 1024) #define CONFIG_SPL_STACK (16 * 1024) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE #define CONFIG_SPL_BSS_MAX_SIZE (3 * 1024) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 87b4fff..2d28e89 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -47,6 +47,17 @@ # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_PHYLIB # define CONFIG_PHY_MARVELL +# define CONFIG_BOOTP_SERVERIP +# define CONFIG_BOOTP_BOOTPATH +# define CONFIG_BOOTP_GATEWAY +# define CONFIG_BOOTP_HOSTNAME +# define CONFIG_BOOTP_MAY_FAIL +# if !defined(CONFIG_ZYNQ_GEM_EMIO0) +# define CONFIG_ZYNQ_GEM_EMIO0 0 +# endif +# if !defined(CONFIG_ZYNQ_GEM_EMIO1) +# define CONFIG_ZYNQ_GEM_EMIO1 0 +# endif #endif /* SPI */ @@ -90,6 +101,55 @@ # define CONFIG_USB_ULPI # define CONFIG_EHCI_IS_TDI # define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +# define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ +# define CONFIG_USB_GADGET +# define CONFIG_USB_GADGET_DUALSPEED +# define CONFIG_USBDOWNLOAD_GADGET +# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000 +# define DFU_DEFAULT_POLL_TIMEOUT 300 +# define CONFIG_DFU_FUNCTION +# define CONFIG_DFU_RAM +# define CONFIG_USB_GADGET_VBUS_DRAW 2 +# define CONFIG_G_DNL_VENDOR_NUM 0x03FD +# define CONFIG_G_DNL_PRODUCT_NUM 0x0300 +# define CONFIG_G_DNL_MANUFACTURER "Xilinx" +# define CONFIG_USB_GADGET +# define CONFIG_USB_CABLE_CHECK +# define CONFIG_CMD_DFU +# define CONFIG_CMD_THOR_DOWNLOAD +# define CONFIG_THOR_FUNCTION +# define DFU_ALT_INFO_RAM \ + "dfu_ram_info=" \ + "set dfu_alt_info " \ + "${kernel_image} ram 0x3000000 0x500000\\\\;" \ + "${devicetree_image} ram 0x2A00000 0x20000\\\\;" \ + "${ramdisk_image} ram 0x2000000 0x600000\0" \ + "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ + "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" + +# if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) +# define CONFIG_DFU_MMC +# define DFU_ALT_INFO_MMC \ + "dfu_mmc_info=" \ + "set dfu_alt_info " \ + "${kernel_image} fat 0 1\\\\;" \ + "${devicetree_image} fat 0 1\\\\;" \ + "${ramdisk_image} fat 0 1\0" \ + "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \ + "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0" + +# define DFU_ALT_INFO \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_MMC +# else +# define DFU_ALT_INFO \ + DFU_ALT_INFO_RAM +# endif +#endif + +#if !defined(DFU_ALT_INFO) +# define DFU_ALT_INFO #endif #if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQ_USB) @@ -100,6 +160,7 @@ # define CONFIG_DOS_PARTITION # define CONFIG_CMD_EXT4 # define CONFIG_CMD_EXT4_WRITE +# define CONFIG_CMD_FS_GENERIC #endif #define CONFIG_SYS_I2C_ZYNQ @@ -121,12 +182,6 @@ # define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */ #endif -#define CONFIG_BOOTP_SERVERIP -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_MAY_FAIL - /* Total Size of Environment Sector */ #define CONFIG_ENV_SIZE (128 << 10) @@ -159,16 +214,17 @@ "cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \ "bootm ${load_addr}\0" \ "sdboot=echo Copying FIT from SD to RAM... && " \ - "fatload mmc 0 ${load_addr} ${fit_image} && " \ + "load mmc 0 ${load_addr} ${fit_image} && " \ "bootm ${load_addr}\0" \ "jtagboot=echo TFTPing FIT to RAM... && " \ "tftpboot ${load_addr} ${fit_image} && " \ "bootm ${load_addr}\0" \ "usbboot=if usb start; then " \ "echo Copying FIT from USB to RAM... && " \ - "fatload usb 0 ${load_addr} ${fit_image} && " \ + "load usb 0 ${load_addr} ${fit_image} && " \ "bootm ${load_addr}\0" \ - "fi\0" + "fi\0" \ + DFU_ALT_INFO #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */ @@ -181,6 +237,7 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE #define CONFIG_BOARD_LATE_INIT +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_LONGHELP #define CONFIG_CLOCKS #define CONFIG_CMD_CLK @@ -198,7 +255,7 @@ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) -#define CONFIG_SYS_MALLOC_LEN 0x400000 +#define CONFIG_SYS_MALLOC_LEN 0xC00000 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 675557a..3286c95 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -23,9 +23,15 @@ #ifdef CONFIG_SYS_FSL_DDR_LE #define ddr_in32(a) in_le32(a) #define ddr_out32(a, v) out_le32(a, v) +#define ddr_setbits32(a, v) setbits_le32(a, v) +#define ddr_clrbits32(a, v) clrbits_le32(a, v) +#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set) #else #define ddr_in32(a) in_be32(a) #define ddr_out32(a, v) out_be32(a, v) +#define ddr_setbits32(a, v) setbits_be32(a, v) +#define ddr_clrbits32(a, v) clrbits_be32(a, v) +#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) #endif #define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR |