diff options
508 files changed, 17764 insertions, 2838 deletions
@@ -114,6 +114,16 @@ config SPL help If you want to build SPL as well as the normal image, say Y. +config SPL_SYS_MALLOC_SIMPLE + bool + depends on SPL + prompt "Only use malloc_simple functions in the spl" + help + Say Y here to only use the *_simple malloc functions from + malloc_simple.c, rather then using the versions from dlmalloc.c + this will make the SPL binary smaller at the cost of more heap + usage as the *_simple malloc functions do not re-use free-ed mem. + config SPL_STACK_R depends on SPL bool "Enable SDRAM location for SPL stack" @@ -132,6 +142,16 @@ config SPL_STACK_R_ADDR Specify the address in SDRAM for the SPL stack. This will be set up before board_init_r() is called. +config SPL_STACK_R_MALLOC_SIMPLE_LEN + depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE + hex "Size of malloc_simple heap after switching to DRAM SPL stack" + default 0x100000 + help + Specify the amount of the stack to use as memory pool for + malloc_simple after switching the stack to DRAM. This may be set + to give board_init_r() a larger heap then the initial heap in + SRAM which is limited to SYS_MALLOC_F_LEN bytes. + config TPL bool depends on SPL && SUPPORT_TPL @@ -1,7 +1,7 @@ VERSION = 2015 PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = -rc5 +EXTRAVERSION = NAME = # *DOCUMENTATION* @@ -901,7 +901,7 @@ MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \ -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \ - -T kwbimage -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) + -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage @@ -909,8 +909,18 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE $(call if_changed,mkimage) -u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE +# If the kwboot xmodem protocol is used, to boot U-Boot on the MVEBU +# SoC's, the SPL U-Boot returns to the BootROM after it completes +# the SDRAM setup. The BootROM expects no U-Boot header in the main +# U-Boot image. So we need to combine SPL and u-boot.bin instead of +# u-boot.img in this case. +ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT +u-boot-spl.kwb: u-boot-dtb.bin spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) +else +u-boot-spl.kwb: u-boot-dtb.img spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) +endif MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img) @@ -1278,6 +1288,7 @@ define filechk_timestamp.h LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE "%b %d %C%y"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \ + LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \ else \ return 42; \ fi; \ @@ -1285,6 +1296,7 @@ define filechk_timestamp.h LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \ LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \ LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \ + LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \ fi) endef @@ -796,18 +796,10 @@ The following options need to be configured: - vxWorks boot parameters: bootvx constructs a valid bootline using the following - environments variables: bootfile, ipaddr, serverip, hostname. + environments variables: bootdev, bootfile, ipaddr, netmask, + serverip, gatewayip, hostname, othbootargs. It loads the vxWorks image pointed bootfile. - CONFIG_SYS_VXWORKS_BOOT_DEVICE - The vxworks device name - CONFIG_SYS_VXWORKS_MAC_PTR - Ethernet 6 byte MA -address - CONFIG_SYS_VXWORKS_SERVERNAME - Name of the server - CONFIG_SYS_VXWORKS_BOOT_ADDR - Address of boot parameters - - CONFIG_SYS_VXWORKS_ADD_PARAMS - - Add it at the end of the bootline. E.g "u=username pw=secret" - Note: If a "bootargs" environment is defined, it will overwride the defaults discussed just above. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7981355..2632099 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -105,20 +105,14 @@ config KIRKWOOD bool "Marvell Kirkwood" select CPU_ARM926EJS -config TARGET_DB_88F6820_GP - bool "Support DB-88F6820-GP" - select CPU_V7 - select SUPPORT_SPL - -config TARGET_DB_MV784MP_GP - bool "Support db-mv784mp-gp" - select CPU_V7 - select SUPPORT_SPL - -config TARGET_MAXBCM - bool "Support maxbcm" +config ARCH_MVEBU + bool "Marvell MVEBU family (Armada XP/38x)" select CPU_V7 select SUPPORT_SPL + select OF_CONTROL + select OF_SEPARATE + select DM + select DM_SERIAL config TARGET_DEVKIT3250 bool "Support devkit3250" @@ -522,6 +516,8 @@ config ARCH_SUNXI select DM_USB select OF_CONTROL select OF_SEPARATE + select SPL_STACK_R if !MACH_SUN9I + select SPL_SYS_MALLOC_SIMPLE if !MACH_SUN9I select USB select USB_STORAGE select USB_KEYBOARD @@ -684,6 +680,8 @@ source "arch/arm/mach-keystone/Kconfig" source "arch/arm/mach-kirkwood/Kconfig" +source "arch/arm/mach-mvebu/Kconfig" + source "arch/arm/cpu/armv7/mx7/Kconfig" source "arch/arm/cpu/armv7/mx6/Kconfig" diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c index df5f817..602d993 100644 --- a/arch/arm/cpu/armv7/omap-common/utils.c +++ b/arch/arm/cpu/armv7/omap-common/utils.c @@ -41,35 +41,73 @@ void cancel_out(u32 *num, u32 *den, u32 den_limit) } } -void __weak usb_fake_mac_from_die_id(u32 *id) +__weak void omap_die_id(unsigned int *die_id) { - uint8_t device_mac[6]; + die_id[0] = die_id[1] = die_id[2] = die_id[3] = 0; +} + +void omap_die_id_serial(void) +{ + unsigned int die_id[4] = { 0 }; + char serial_string[17] = { 0 }; + + omap_die_id((unsigned int *)&die_id); + + if (!getenv("serial#")) { + snprintf(serial_string, sizeof(serial_string), + "%08x%08x", die_id[0], die_id[3]); + + setenv("serial#", serial_string); + } +} + +void omap_die_id_get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial_string; + unsigned long long serial; + + serial_string = getenv("serial#"); + + if (serial_string) { + serial = simple_strtoull(serial_string, NULL, 16); + + serialnr->high = (unsigned int) (serial >> 32); + serialnr->low = (unsigned int) (serial & 0xffffffff); + } else { + serialnr->high = 0; + serialnr->low = 0; + } +} + +void omap_die_id_usbethaddr(void) +{ + unsigned int die_id[4] = { 0 }; + unsigned char mac[6] = { 0 }; + + omap_die_id((unsigned int *)&die_id); if (!getenv("usbethaddr")) { /* - * create a fake MAC address from the processor ID code. - * first byte is 0x02 to signify locally administered. + * Create a fake MAC address from the processor ID code. + * First byte is 0x02 to signify locally administered. */ - device_mac[0] = 0x02; - device_mac[1] = id[3] & 0xff; - device_mac[2] = id[2] & 0xff; - device_mac[3] = id[1] & 0xff; - device_mac[4] = id[0] & 0xff; - device_mac[5] = (id[0] >> 8) & 0xff; - - eth_setenv_enetaddr("usbethaddr", device_mac); + mac[0] = 0x02; + mac[1] = die_id[3] & 0xff; + mac[2] = die_id[2] & 0xff; + mac[3] = die_id[1] & 0xff; + mac[4] = die_id[0] & 0xff; + mac[5] = (die_id[0] >> 8) & 0xff; + + eth_setenv_enetaddr("usbethaddr", mac); } } -void __weak usb_set_serial_num_from_die_id(u32 *id) +void omap_die_id_display(void) { - char serialno[72]; - uint32_t serialno_lo, serialno_hi; + unsigned int die_id[4] = { 0 }; - if (!getenv("serial#")) { - serialno_hi = id[0]; - serialno_lo = id[1]; - sprintf(serialno, "%08x%08x", serialno_hi, serialno_lo); - setenv("serial#", serialno); - } + omap_die_id(die_id); + + printf("OMAP die ID: %08x%08x%08x%08x", die_id[0], die_id[1], die_id[2], + die_id[3]); } diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 8252b32..0c44ea5 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -214,7 +214,7 @@ void board_init_f(ulong dummy) */ int __weak misc_init_r(void) { - dieid_num_r(); + omap_die_id_display(); return 0; } diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c index ab60a03..6818fab 100644 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ b/arch/arm/cpu/armv7/omap3/sys_info.c @@ -42,39 +42,14 @@ static char *rev_s_37xx[CPU_37XX_MAX_REV] = { "1.2"}; #endif /* CONFIG_DISPLAY_CPUINFO */ -/***************************************************************** - * get_dieid(u32 *id) - read die ID - *****************************************************************/ -void get_dieid(u32 *id) +void omap_die_id(unsigned int *die_id) { struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; - id[3] = readl(&id_base->die_id_0); - id[2] = readl(&id_base->die_id_1); - id[1] = readl(&id_base->die_id_2); - id[0] = readl(&id_base->die_id_3); -} - -/***************************************************************** - * dieid_num_r(void) - read and set die ID - *****************************************************************/ -void dieid_num_r(void) -{ - char *uid_s, die_id[34]; - u32 id[4]; - - memset(die_id, 0, sizeof(die_id)); - - uid_s = getenv("dieid#"); - - if (uid_s == NULL) { - get_dieid(id); - sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]); - setenv("dieid#", die_id); - uid_s = die_id; - } - - printf("Die ID #%s\n", uid_s); + die_id[0] = readl(&id_base->die_id_0); + die_id[1] = readl(&id_base->die_id_1); + die_id[2] = readl(&id_base->die_id_2); + die_id[3] = readl(&id_base->die_id_3); } /****************************************** diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index a68947f..7c6638c 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -156,6 +156,14 @@ void init_omap_revision(void) } } +void omap_die_id(unsigned int *die_id) +{ + die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0); + die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1); + die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2); + die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3); +} + #ifndef CONFIG_SYS_L2CACHE_OFF void v7_outer_cache_enable(void) { diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c index 8698ec7..a09581e 100644 --- a/arch/arm/cpu/armv7/omap4/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c @@ -280,7 +280,10 @@ struct prcm_regs const omap4_prcm = { struct omap_sys_ctrl_regs const omap4_ctrl = { .control_status = 0x4A0022C4, - .control_id_code = 0x4A002204, + .control_std_fuse_die_id_0 = 0x4A002200, + .control_std_fuse_die_id_1 = 0x4A002208, + .control_std_fuse_die_id_2 = 0x4A00220C, + .control_std_fuse_die_id_3 = 0x4A002210, .control_std_fuse_opp_bgap = 0x4a002260, .control_status = 0x4a0022c4, .control_ldosram_iva_voltage_ctrl = 0x4A002320, diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 325a7e8..8f184df 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -379,6 +379,14 @@ void init_omap_revision(void) init_cpu_configuration(); } +void omap_die_id(unsigned int *die_id) +{ + die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0); + die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1); + die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2); + die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3); +} + void reset_cpu(ulong ignored) { u32 omap_rev = omap_revision(); diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index ea659bd..cd289dd 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -298,6 +298,10 @@ struct prcm_regs const omap5_es1_prcm = { struct omap_sys_ctrl_regs const omap5_ctrl = { .control_status = 0x4A002134, .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4, + .control_std_fuse_die_id_0 = 0x4A002200, + .control_std_fuse_die_id_1 = 0x4A002208, + .control_std_fuse_die_id_2 = 0x4A00220C, + .control_std_fuse_die_id_3 = 0x4A002210, .control_phy_power_usb = 0x4A002370, .control_phy_power_sata = 0x4A002374, .control_padconf_core_base = 0x4A002800, diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index d11365b..4785ac6 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -136,7 +136,7 @@ DECLARE_GLOBAL_DATA_PTR; */ u32 spl_boot_device(void) { - struct mmc *mmc0, *mmc1; + __maybe_unused struct mmc *mmc0, *mmc1; /* * When booting from the SD card or NAND memory, the "eGON.BT0" * signature is expected to be found in memory at the address 0x0004 @@ -157,15 +157,18 @@ u32 spl_boot_device(void) return BOOT_DEVICE_BOARD; /* The BROM will try to boot from mmc0 first, so try that first. */ +#ifdef CONFIG_MMC mmc_initialize(gd->bd); mmc0 = find_mmc_device(0); if (sunxi_mmc_has_egon_boot_signature(mmc0)) return BOOT_DEVICE_MMC1; +#endif /* Fallback to booting NAND if enabled. */ if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT)) return BOOT_DEVICE_NAND; +#ifdef CONFIG_MMC if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) { mmc1 = find_mmc_device(1); if (sunxi_mmc_has_egon_boot_signature(mmc1)) { @@ -179,6 +182,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_MMC2; } } +#endif panic("Could not determine boot source\n"); return -1; /* Never reached */ @@ -192,6 +196,7 @@ u32 spl_boot_mode(void) void board_init_f(ulong dummy) { + spl_init(); preloader_console_init(); #ifdef CONFIG_SPL_I2C_SUPPORT diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index a276fad..05fef32 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -10,7 +10,7 @@ #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/clock.h> -#include <axp221.h> +#include <axp_pmic.h> #include <errno.h> #ifdef CONFIG_MACH_SUN6I @@ -82,7 +82,7 @@ int print_cpuinfo(void) int sunxi_get_sid(unsigned int *sid) { #ifdef CONFIG_AXP221_POWER - return axp221_get_sid(sid); + return axp_get_sid(sid); #elif defined SUNXI_SID_BASE int i; diff --git a/arch/arm/cpu/armv7/sunxi/usb_phy.c b/arch/arm/cpu/armv7/sunxi/usb_phy.c index b7ca5d4..19bb5a1 100644 --- a/arch/arm/cpu/armv7/sunxi/usb_phy.c +++ b/arch/arm/cpu/armv7/sunxi/usb_phy.c @@ -17,15 +17,6 @@ #include <asm/gpio.h> #include <asm/io.h> #include <errno.h> -#ifdef CONFIG_AXP152_POWER -#include <axp152.h> -#endif -#ifdef CONFIG_AXP209_POWER -#include <axp209.h> -#endif -#ifdef CONFIG_AXP221_POWER -#include <axp221.h> -#endif #define SUNXI_USB_PMU_IRQ_ENABLE 0x800 #ifdef CONFIG_MACH_SUN8I_A33 diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index d846236..ab8c089 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -112,7 +112,7 @@ ENDPROC(__asm_flush_dcache_all) ENTRY(__asm_invalidate_dcache_all) mov x16, lr - mov x0, #0xffff + mov x0, #0x1 bl __asm_dcache_all mov lr, x16 ret diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 6bde1cf..b1ea822 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -59,15 +59,15 @@ static void mmu_setup(void) el = current_el(); if (el == 1) { set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL1_IPS_BITS, + TCR_EL1_RSVD | TCR_FLAGS | TCR_EL1_IPS_BITS, MEMORY_ATTRIBUTES); } else if (el == 2) { set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL2_IPS_BITS, + TCR_EL2_RSVD | TCR_FLAGS | TCR_EL2_IPS_BITS, MEMORY_ATTRIBUTES); } else { set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL3_IPS_BITS, + TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS, MEMORY_ATTRIBUTES); } /* enable the mmu */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 65b4230..ddc6a05 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -41,6 +41,11 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra210-p2371-0000.dtb \ tegra210-p2371-2180.dtb \ tegra210-p2571.dtb + +dtb-$(CONFIG_ARCH_MVEBU) += \ + armada-388-gp.dtb \ + armada-xp-gp.dtb + dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-ld4-ref.dtb \ uniphier-ph1-ld6b-ref.dtb \ @@ -61,6 +66,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb +dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ @@ -69,7 +75,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_de0_nano_soc.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb -dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb +dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb +dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ @@ -107,15 +114,14 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a10s-r7-tv-dongle.dtb \ sun5i-a10s-wobo-i5.dtb \ sun5i-a13-ampe-a76.dtb \ - sun5i-a13-forfun-q88db.dtb \ sun5i-a13-hsg-h702.dtb \ sun5i-a13-inet-86vs.dtb \ sun5i-a13-inet-98v-rev2.dtb \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb \ sun5i-a13-q8-tablet.dtb \ - sun5i-a13-tzx-q8-713b7.dtb \ - sun5i-a13-utoo-p66.dtb + sun5i-a13-utoo-p66.dtb \ + sun5i-r8-chip.dtb dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31-app4-evb1.dtb \ sun6i-a31-colombus.dtb \ @@ -125,7 +131,8 @@ dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31-mele-a1000g-quad.dtb \ sun6i-a31-mixtile-loftq.dtb \ sun6i-a31s-cs908.dtb \ - sun6i-a31s-primo81.dtb + sun6i-a31s-primo81.dtb \ + sun6i-a31s-sinovoip-bpi-m2.dtb dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-ainol-aw1.dtb \ sun7i-a20-bananapi.dtb \ @@ -152,13 +159,9 @@ dtb-$(CONFIG_MACH_SUN7I) += \ dtb-$(CONFIG_MACH_SUN8I_A23) += \ sun8i-a23-evb.dtb \ sun8i-a23-gt90h-v4.dtb \ - sun8i-a23-ippo-q8h-v5.dtb \ - sun8i-a23-ippo-q8h-v1.2.dtb \ sun8i-a23-q8-tablet.dtb dtb-$(CONFIG_MACH_SUN8I_A33) += \ - sun8i-a33-et-q8-v1.6.dtb \ sun8i-a33-ga10h-v1.1.dtb \ - sun8i-a33-ippo-q8h-v1.2.dtb \ sun8i-a33-q8-tablet.dtb \ sun8i-a33-sinlinx-sina33.dtb dtb-$(CONFIG_MACH_SUN9I) += \ @@ -168,6 +171,11 @@ dtb-$(CONFIG_MACH_SUN9I) += \ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ vf610-colibri.dtb +dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ + k2l-evm.dtb \ + k2e-evm.dtb \ + k2g-evm.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi new file mode 100644 index 0000000..ade28c7 --- /dev/null +++ b/arch/arm/dts/am4372.dtsi @@ -0,0 +1,999 @@ +/* + * Device Tree Source for AM4372 SoC + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "skeleton.dtsi" + +/ { + compatible = "ti,am4372", "ti,am43"; + interrupt-parent = <&wakeupgen>; + + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + serial0 = &uart0; + ethernet0 = &cpsw_emac0; + ethernet1 = &cpsw_emac1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + }; + }; + + gic: interrupt-controller@48241000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48241000 0x1000>, + <0x48240100 0x0100>; + interrupt-parent = <&gic>; + }; + + wakeupgen: interrupt-controller@48281000 { + compatible = "ti,omap4-wugen-mpu"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48281000 0x1000>; + interrupt-parent = <&gic>; + }; + + l2-cache-controller@48242000 { + compatible = "arm,pl310-cache"; + reg = <0x48242000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + ocp { + compatible = "ti,am4372-l3-noc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + reg = <0x44000000 0x400000 + 0x44800000 0x400000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + + l4_wkup: l4_wkup@44c00000 { + compatible = "ti,am4-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x44c00000 0x287000>; + + prcm: prcm@1f0000 { + compatible = "ti,am4-prcm"; + reg = <0x1f0000 0x11000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scm: scm@210000 { + compatible = "ti,am4-scm", "simple-bus"; + reg = <0x210000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x210000 0x4000>; + + am43xx_pinmux: pinmux@800 { + compatible = "ti,am437-padconf", + "pinctrl-single"; + reg = <0x800 0x31c>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; + }; + }; + + emif: emif@4c000000 { + compatible = "ti,emif-am4372"; + reg = <0x4c000000 0x1000000>; + ti,hwmods = "emif"; + }; + + edma: edma@49000000 { + compatible = "ti,edma3"; + ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; + reg = <0x49000000 0x10000>, + <0x44e10f90 0x10>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + }; + + uart0: serial@44e09000 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x44e09000 0x2000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "uart1"; + }; + + uart1: serial@48022000 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x48022000 0x2000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "uart2"; + status = "disabled"; + }; + + uart2: serial@48024000 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x48024000 0x2000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "uart3"; + status = "disabled"; + }; + + uart3: serial@481a6000 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x481a6000 0x2000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "uart4"; + status = "disabled"; + }; + + uart4: serial@481a8000 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x481a8000 0x2000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "uart5"; + status = "disabled"; + }; + + uart5: serial@481aa000 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x481aa000 0x2000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "uart6"; + status = "disabled"; + }; + + mailbox: mailbox@480C8000 { + compatible = "ti,omap4-mailbox"; + reg = <0x480C8000 0x200>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "mailbox"; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <8>; + mbox_wkupm3: wkup_m3 { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <0 0 3>; + }; + }; + + timer1: timer@44e31000 { + compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; + reg = <0x44e31000 0x400>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-alwon; + ti,hwmods = "timer1"; + }; + + timer2: timer@48040000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x48040000 0x400>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "timer2"; + }; + + timer3: timer@48042000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x48042000 0x400>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "timer3"; + status = "disabled"; + }; + + timer4: timer@48044000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x48044000 0x400>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; + ti,hwmods = "timer4"; + status = "disabled"; + }; + + timer5: timer@48046000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x48046000 0x400>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; + ti,hwmods = "timer5"; + status = "disabled"; + }; + + timer6: timer@48048000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x48048000 0x400>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; + ti,hwmods = "timer6"; + status = "disabled"; + }; + + timer7: timer@4804a000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x4804a000 0x400>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; + ti,hwmods = "timer7"; + status = "disabled"; + }; + + timer8: timer@481c1000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x481c1000 0x400>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "timer8"; + status = "disabled"; + }; + + timer9: timer@4833d000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x4833d000 0x400>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "timer9"; + status = "disabled"; + }; + + timer10: timer@4833f000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x4833f000 0x400>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "timer10"; + status = "disabled"; + }; + + timer11: timer@48341000 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x48341000 0x400>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "timer11"; + status = "disabled"; + }; + + counter32k: counter@44e86000 { + compatible = "ti,am4372-counter32k","ti,omap-counter32k"; + reg = <0x44e86000 0x40>; + ti,hwmods = "counter_32k"; + }; + + rtc: rtc@44e3e000 { + compatible = "ti,am4372-rtc","ti,da830-rtc"; + reg = <0x44e3e000 0x1000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "rtc"; + status = "disabled"; + }; + + wdt: wdt@44e35000 { + compatible = "ti,am4372-wdt","ti,omap3-wdt"; + reg = <0x44e35000 0x1000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "wd_timer2"; + }; + + gpio0: gpio@44e07000 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x44e07000 0x1000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ti,hwmods = "gpio1"; + status = "disabled"; + }; + + gpio1: gpio@4804c000 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x4804c000 0x1000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ti,hwmods = "gpio2"; + status = "disabled"; + }; + + gpio2: gpio@481ac000 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x481ac000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ti,hwmods = "gpio3"; + status = "disabled"; + }; + + gpio3: gpio@481ae000 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x481ae000 0x1000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ti,hwmods = "gpio4"; + status = "disabled"; + }; + + gpio4: gpio@48320000 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x48320000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ti,hwmods = "gpio5"; + status = "disabled"; + }; + + gpio5: gpio@48322000 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x48322000 0x1000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + ti,hwmods = "gpio6"; + status = "disabled"; + }; + + hwspinlock: spinlock@480ca000 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x480ca000 0x1000>; + ti,hwmods = "spinlock"; + #hwlock-cells = <1>; + }; + + i2c0: i2c@44e0b000 { + compatible = "ti,am4372-i2c","ti,omap4-i2c"; + reg = <0x44e0b000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "i2c1"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@4802a000 { + compatible = "ti,am4372-i2c","ti,omap4-i2c"; + reg = <0x4802a000 0x1000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "i2c2"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4819c000 { + compatible = "ti,am4372-i2c","ti,omap4-i2c"; + reg = <0x4819c000 0x1000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "i2c3"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@48030000 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x48030000 0x400>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "spi0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mmc1: mmc@48060000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x48060000 0x1000>; + ti,hwmods = "mmc1"; + ti,dual-volt; + ti,needs-special-reset; + dmas = <&edma 24 + &edma 25>; + dma-names = "tx", "rx"; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + mmc2: mmc@481d8000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x481d8000 0x1000>; + ti,hwmods = "mmc2"; + ti,needs-special-reset; + dmas = <&edma 2 + &edma 3>; + dma-names = "tx", "rx"; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + mmc3: mmc@47810000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x47810000 0x1000>; + ti,hwmods = "mmc3"; + ti,needs-special-reset; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + spi1: spi@481a0000 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x481a0000 0x400>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "spi1"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@481a2000 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x481a2000 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "spi2"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@481a4000 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x481a4000 0x400>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "spi3"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@48345000 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x48345000 0x400>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "spi4"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mac: ethernet@4a100000 { + compatible = "ti,am4372-cpsw","ti,cpsw"; + reg = <0x4a100000 0x800 + 0x4a101200 0x100>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + ti,hwmods = "cpgmac0"; + clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; + clock-names = "fck", "cpts"; + status = "disabled"; + cpdma_channels = <8>; + ale_entries = <1024>; + bd_ram_size = <0x2000>; + no_bd_ram = <0>; + rx_descs = <64>; + mac_control = <0x20>; + slaves = <2>; + active_slave = <0>; + cpts_clock_mult = <0x80000000>; + cpts_clock_shift = <29>; + ranges; + + davinci_mdio: mdio@4a101000 { + compatible = "ti,am4372-mdio","ti,davinci_mdio"; + reg = <0x4a101000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "davinci_mdio"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpsw_emac0: slave@4a100200 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + cpsw_emac1: slave@4a100300 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + phy_sel: cpsw-phy-sel@44e10650 { + compatible = "ti,am43xx-cpsw-phy-sel"; + reg= <0x44e10650 0x4>; + reg-names = "gmii-sel"; + }; + }; + + epwmss0: epwmss@48300000 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x48300000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "epwmss0"; + status = "disabled"; + + ecap0: ecap@48300100 { + compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48300100 0x80>; + ti,hwmods = "ecap0"; + status = "disabled"; + }; + + ehrpwm0: ehrpwm@48300200 { + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48300200 0x80>; + ti,hwmods = "ehrpwm0"; + status = "disabled"; + }; + }; + + epwmss1: epwmss@48302000 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x48302000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "epwmss1"; + status = "disabled"; + + ecap1: ecap@48302100 { + compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48302100 0x80>; + ti,hwmods = "ecap1"; + status = "disabled"; + }; + + ehrpwm1: ehrpwm@48302200 { + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48302200 0x80>; + ti,hwmods = "ehrpwm1"; + status = "disabled"; + }; + }; + + epwmss2: epwmss@48304000 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x48304000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "epwmss2"; + status = "disabled"; + + ecap2: ecap@48304100 { + compatible = "ti,am4372-ecap","ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48304100 0x80>; + ti,hwmods = "ecap2"; + status = "disabled"; + }; + + ehrpwm2: ehrpwm@48304200 { + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48304200 0x80>; + ti,hwmods = "ehrpwm2"; + status = "disabled"; + }; + }; + + epwmss3: epwmss@48306000 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x48306000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "epwmss3"; + status = "disabled"; + + ehrpwm3: ehrpwm@48306200 { + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48306200 0x80>; + ti,hwmods = "ehrpwm3"; + status = "disabled"; + }; + }; + + epwmss4: epwmss@48308000 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x48308000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "epwmss4"; + status = "disabled"; + + ehrpwm4: ehrpwm@48308200 { + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48308200 0x80>; + ti,hwmods = "ehrpwm4"; + status = "disabled"; + }; + }; + + epwmss5: epwmss@4830a000 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x4830a000 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "epwmss5"; + status = "disabled"; + + ehrpwm5: ehrpwm@4830a200 { + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x4830a200 0x80>; + ti,hwmods = "ehrpwm5"; + status = "disabled"; + }; + }; + + tscadc: tscadc@44e0d000 { + compatible = "ti,am3359-tscadc"; + reg = <0x44e0d000 0x1000>; + ti,hwmods = "adc_tsc"; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&adc_tsc_fck>; + clock-names = "fck"; + status = "disabled"; + + tsc { + compatible = "ti,am3359-tsc"; + }; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + + }; + + sham: sham@53100000 { + compatible = "ti,omap5-sham"; + ti,hwmods = "sham"; + reg = <0x53100000 0x300>; + dmas = <&edma 36>; + dma-names = "rx"; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + }; + + aes: aes@53501000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes"; + reg = <0x53501000 0xa0>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&edma 6 + &edma 5>; + dma-names = "tx", "rx"; + }; + + des: des@53701000 { + compatible = "ti,omap4-des"; + ti,hwmods = "des"; + reg = <0x53701000 0xa0>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&edma 34 + &edma 33>; + dma-names = "tx", "rx"; + }; + + mcasp0: mcasp@48038000 { + compatible = "ti,am33xx-mcasp-audio"; + ti,hwmods = "mcasp0"; + reg = <0x48038000 0x2000>, + <0x46000000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <80>, <81>; + interrupt-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 8>, + <&edma 9>; + dma-names = "tx", "rx"; + }; + + mcasp1: mcasp@4803C000 { + compatible = "ti,am33xx-mcasp-audio"; + ti,hwmods = "mcasp1"; + reg = <0x4803C000 0x2000>, + <0x46400000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <82>, <83>; + interrupt-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 10>, + <&edma 11>; + dma-names = "tx", "rx"; + }; + + elm: elm@48080000 { + compatible = "ti,am3352-elm"; + reg = <0x48080000 0x2000>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "elm"; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + status = "disabled"; + }; + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + clocks = <&l3s_gclk>; + clock-names = "fck"; + reg = <0x50000000 0x2000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; + }; + + am43xx_control_usb2phy1: control-phy@44e10620 { + compatible = "ti,control-phy-usb2-am437"; + reg = <0x44e10620 0x4>; + reg-names = "power"; + }; + + am43xx_control_usb2phy2: control-phy@0x44e10628 { + compatible = "ti,control-phy-usb2-am437"; + reg = <0x44e10628 0x4>; + reg-names = "power"; + }; + + ocp2scp0: ocp2scp@483a8000 { + compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "ocp2scp0"; + + usb2_phy1: phy@483a8000 { + compatible = "ti,am437x-usb2"; + reg = <0x483a8000 0x8000>; + ctrl-module = <&am43xx_control_usb2phy1>; + clocks = <&usb_phy0_always_on_clk32k>, + <&usb_otg_ss0_refclk960m>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + ocp2scp1: ocp2scp@483e8000 { + compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "ocp2scp1"; + + usb2_phy2: phy@483e8000 { + compatible = "ti,am437x-usb2"; + reg = <0x483e8000 0x8000>; + ctrl-module = <&am43xx_control_usb2phy2>; + clocks = <&usb_phy1_always_on_clk32k>, + <&usb_otg_ss1_refclk960m>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + dwc3_1: omap_dwc3@48380000 { + compatible = "ti,am437x-dwc3"; + ti,hwmods = "usb_otg_ss0"; + reg = <0x48380000 0x10000>; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <1>; + ranges; + + usb1: usb@48390000 { + compatible = "synopsys,dwc3"; + reg = <0x48390000 0x10000>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_phy1>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + status = "disabled"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + }; + }; + + dwc3_2: omap_dwc3@483c0000 { + compatible = "ti,am437x-dwc3"; + ti,hwmods = "usb_otg_ss1"; + reg = <0x483c0000 0x10000>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <1>; + ranges; + + usb2: usb@483d0000 { + compatible = "synopsys,dwc3"; + reg = <0x483d0000 0x10000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_phy2>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + status = "disabled"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + }; + }; + + qspi: qspi@47900000 { + compatible = "ti,am4372-qspi"; + reg = <0x47900000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "qspi"; + interrupts = <0 138 0x4>; + num-cs = <4>; + status = "disabled"; + }; + + hdq: hdq@48347000 { + compatible = "ti,am4372-hdq"; + reg = <0x48347000 0x1000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&func_12m_clk>; + clock-names = "fck"; + ti,hwmods = "hdq1w"; + status = "disabled"; + }; + + dss: dss@4832a000 { + compatible = "ti,omap3-dss"; + reg = <0x4832a000 0x200>; + status = "disabled"; + ti,hwmods = "dss_core"; + clocks = <&disp_clk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dispc: dispc@4832a400 { + compatible = "ti,omap3-dispc"; + reg = <0x4832a400 0x400>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "dss_dispc"; + clocks = <&disp_clk>; + clock-names = "fck"; + }; + + rfbi: rfbi@4832a800 { + compatible = "ti,omap3-rfbi"; + reg = <0x4832a800 0x100>; + ti,hwmods = "dss_rfbi"; + clocks = <&disp_clk>; + clock-names = "fck"; + status = "disabled"; + }; + }; + + ocmcram: ocmcram@40300000 { + compatible = "mmio-sram"; + reg = <0x40300000 0x40000>; /* 256k */ + }; + + dcan0: can@481cc000 { + compatible = "ti,am4372-d_can", "ti,am3352-d_can"; + ti,hwmods = "d_can0"; + clocks = <&dcan0_fck>; + clock-names = "fck"; + reg = <0x481cc000 0x2000>; + syscon-raminit = <&scm_conf 0x644 0>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + dcan1: can@481d0000 { + compatible = "ti,am4372-d_can", "ti,am3352-d_can"; + ti,hwmods = "d_can1"; + clocks = <&dcan1_fck>; + clock-names = "fck"; + reg = <0x481d0000 0x2000>; + syscon-raminit = <&scm_conf 0x644 1>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + vpfe0: vpfe@48326000 { + compatible = "ti,am437x-vpfe"; + reg = <0x48326000 0x2000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "vpfe0"; + status = "disabled"; + }; + + vpfe1: vpfe@48328000 { + compatible = "ti,am437x-vpfe"; + reg = <0x48328000 0x2000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "vpfe1"; + status = "disabled"; + }; + }; +}; + +/include/ "am43xx-clocks.dtsi" diff --git a/arch/arm/dts/am437x-gp-evm.dts b/arch/arm/dts/am437x-gp-evm.dts new file mode 100644 index 0000000..b5f0b4e --- /dev/null +++ b/arch/arm/dts/am437x-gp-evm.dts @@ -0,0 +1,797 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* AM437x GP EVM */ + +/dts-v1/; + +#include "am4372.dtsi" +#include <dt-bindings/pinctrl/am43xx.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "TI AM437x GP EVM"; + compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43"; + + aliases { + display0 = &lcd0; + serial3 = &uart3; + }; + + chosen { + stdout-path = &uart0; + }; + + vmmcsd_fixed: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + + vtt_fixed: fixedregulator-vtt { + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; + }; + + vmmcwl_fixed: fixedregulator-mmcwl { + compatible = "regulator-fixed"; + regulator-name = "vmmcwl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + matrix_keypad: matrix_keypad@0 { + compatible = "gpio-matrix-keypad"; + debounce-delay-ms = <5>; + col-scan-delay-us = <2>; + + row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */ + &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ + &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */ + + col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */ + &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */ + + linux,keymap = <0x00000201 /* P1 */ + 0x00010202 /* P2 */ + 0x01000067 /* UP */ + 0x0101006a /* RIGHT */ + 0x02000069 /* LEFT */ + 0x0201006c>; /* DOWN */ + }; + + lcd0: display { + compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + /* + * SelLCDorHDMI, LOW to select HDMI. This is not really the + * panel's enable GPIO, but we don't have HDMI driver support nor + * support to switch between two displays, so using this gpio as + * panel's enable should be safe. + */ + enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <210>; + hback-porch = <16>; + hsync-len = <30>; + vback-porch = <10>; + vfront-porch = <22>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + /* fixed 12MHz oscillator */ + refclk: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + +}; + +&am43xx_pinmux { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&wlan_pins_default>; + pinctrl-1 = <&wlan_pins_sleep>; + + i2c0_pins: i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: i2c1_pins { + pinctrl-single,pins = < + 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + ecap0_pins: backlight_pins { + pinctrl-single,pins = < + 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ + >; + }; + + pixcir_ts_pins: pixcir_ts_pins { + pinctrl-single,pins = < + 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + nand_flash_x8: nand_flash_x8 { + pinctrl-single,pins = < + 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */ + 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ + 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; + + dss_pins: dss_pins { + pinctrl-single,pins = < + 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ + 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) + 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ + 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ + 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0) + 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ + 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ + 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ + 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ + 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ + + >; + }; + + lcd_pins: lcd_pins { + pinctrl-single,pins = < + /* GPIO 5_8 to select LCD / HDMI */ + 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + dcan0_default: dcan0_default_pins { + pinctrl-single,pins = < + 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ + 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ + >; + }; + + dcan1_default: dcan1_default_pins { + pinctrl-single,pins = < + 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ + 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ + >; + }; + + vpfe0_pins_default: vpfe0_pins_default { + pinctrl-single,pins = < + 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ + 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ + 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ + 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ + 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ + 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ + 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ + 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ + 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ + 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ + 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ + 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ + 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ + >; + }; + + vpfe0_pins_sleep: vpfe0_pins_sleep { + pinctrl-single,pins = < + 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ + 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ + 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/ + 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/ + 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/ + 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/ + 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/ + 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/ + 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/ + 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/ + 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/ + 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/ + 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/ + >; + }; + + vpfe1_pins_default: vpfe1_pins_default { + pinctrl-single,pins = < + 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ + 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ + 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/ + 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/ + 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/ + 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/ + 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/ + 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/ + 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/ + 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/ + 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/ + 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/ + 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/ + >; + }; + + vpfe1_pins_sleep: vpfe1_pins_sleep { + pinctrl-single,pins = < + 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ + 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ + 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/ + 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/ + 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/ + 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/ + 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/ + 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/ + 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/ + 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/ + 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/ + 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/ + 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/ + >; + }; + + mmc3_pins_default: pinmux_mmc3_pins_default { + pinctrl-single,pins = < + 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ + 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ + 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ + 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ + 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ + >; + }; + + mmc3_pins_sleep: pinmux_mmc3_pins_sleep { + pinctrl-single,pins = < + 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ + 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */ + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */ + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */ + 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ + >; + }; + + wlan_pins_default: pinmux_wlan_pins_default { + pinctrl-single,pins = < + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ + 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ + >; + }; + + wlan_pins_sleep: pinmux_wlan_pins_sleep { + pinctrl-single,pins = < + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ + 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ + 0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ + >; + }; + + uart3_pins: uart3_pins { + pinctrl-single,pins = < + 0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ + 0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ + 0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */ + 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ + >; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + + tps65218: tps65218@24 { + reg = <0x24>; + compatible = "ti,tps65218"; + interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + compatible = "ti,tps65218-dcdc1"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + compatible = "ti,tps65218-dcdc2"; + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + compatible = "ti,tps65218-dcdc3"; + regulator-name = "vdcdc3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,tps65218-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + + ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + + clocks = <&refclk 0>; + clock-names = "xvclk"; + + port { + ov2659_0: endpoint { + remote-endpoint = <&vpfe1_ep>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + pixcir_ts@5c { + compatible = "pixcir,pixcir_tangoc"; + pinctrl-names = "default"; + pinctrl-0 = <&pixcir_ts_pins>; + reg = <0x5c>; + interrupt-parent = <&gpio3>; + interrupts = <22 0>; + + attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + }; + + ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + + clocks = <&refclk 0>; + clock-names = "xvclk"; + + port { + ov2659_1: endpoint { + remote-endpoint = <&vpfe0_ep>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&tscadc { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; + ti,no-reset-on-init; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; +}; + +&mmc3 { + /* disable MMC3 as SDIO is not supported in U-Boot */ + status = "disabled"; + /* these are on the crossbar and are outlined in the + xbar-event-map element */ + dmas = <&edma 30 + &edma 31>; + dma-names = "tx", "rx"; + vmmc-supply = <&vmmcwl_fixed>; + bus-width = <4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc3_pins_default>; + pinctrl-1 = <&mmc3_pins_sleep>; + cap-power-off-card; + keep-power-in-suspend; + ti,non-removable; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@0 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&edma { + ti,edma-xbar-event-map = /bits/ 16 <1 30 + 2 31>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&usb2_phy1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; +}; + +&mac { + slaves = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rgmii"; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_flash_x8>; + ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ + nand@0,0 { + reg = <0 0 4>; /* device IO registers */ + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <25>; + gpmc,adv-wr-off-ns = <25>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <3>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,wait-pin = <0>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x00040000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00040000 0x00040000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00080000 0x00040000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x000c0000 0x00040000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00100000 0x00080000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x00180000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x00280000 0x00040000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x002c0000 0x00040000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00300000 0x00700000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x1f600000>; + }; + }; +}; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_pins>; + + port { + dpi_out: endpoint@0 { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&dcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan0_default>; + status = "okay"; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_default>; + status = "okay"; +}; + +&vpfe0 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&vpfe0_pins_default>; + pinctrl-1 = <&vpfe0_pins_sleep>; + + port { + vpfe0_ep: endpoint { + remote-endpoint = <&ov2659_1>; + ti,am437x-vpfe-interface = <0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; +}; + +&vpfe1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&vpfe1_pins_default>; + pinctrl-1 = <&vpfe1_pins_sleep>; + + port { + vpfe1_ep: endpoint { + remote-endpoint = <&ov2659_0>; + ti,am437x-vpfe-interface = <0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; +}; diff --git a/arch/arm/dts/am437x-sk-evm.dts b/arch/arm/dts/am437x-sk-evm.dts new file mode 100644 index 0000000..3f9d808 --- /dev/null +++ b/arch/arm/dts/am437x-sk-evm.dts @@ -0,0 +1,704 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* AM437x SK EVM */ + +/dts-v1/; + +#include "am4372.dtsi" +#include <dt-bindings/pinctrl/am43xx.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "TI AM437x SK EVM"; + compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43"; + + aliases { + display0 = &lcd0; + }; + + chosen { + stdout-path = &uart0; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + sound { + compatible = "ti,da830-evm-audio"; + ti,model = "AM437x-SK-EVM"; + ti,audio-codec = <&tlv320aic3106>; + ti,mcasp-controller = <&mcasp1>; + ti,codec-clock-rate = <24000000>; + ti,audio-routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT"; + }; + + matrix_keypad: matrix_keypad@0 { + compatible = "gpio-matrix-keypad"; + + pinctrl-names = "default"; + pinctrl-0 = <&matrix_keypad_pins>; + + debounce-delay-ms = <5>; + col-scan-delay-us = <5>; + + row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ + &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ + + col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */ + &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */ + + linux,keymap = < + MATRIX_KEY(0, 0, KEY_DOWN) + MATRIX_KEY(0, 1, KEY_RIGHT) + MATRIX_KEY(1, 0, KEY_LEFT) + MATRIX_KEY(1, 1, KEY_UP) + >; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; + + led@0 { + label = "am437x-sk:red:heartbeat"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@1 { + label = "am437x-sk:green:mmc1"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@2 { + label = "am437x-sk:blue:cpu0"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led@3 { + label = "am437x-sk:blue:usr3"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ + default-state = "off"; + }; + }; + + lcd0: display { + compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <2>; + hback-porch = <2>; + hsync-len = <41>; + vfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; +}; + +&am43xx_pinmux { + matrix_keypad_pins: matrix_keypad_pins { + pinctrl-single,pins = < + 0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ + 0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ + 0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ + 0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ + >; + }; + + leds_pins: leds_pins { + pinctrl-single,pins = < + 0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ + 0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ + 0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ + 0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ + >; + }; + + i2c0_pins: i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: i2c1_pins { + pinctrl-single,pins = < + 0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + 0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + 0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + 0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + 0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + ecap0_pins: backlight_pins { + pinctrl-single,pins = < + 0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ + >; + }; + + edt_ft5306_ts_pins: edt_ft5306_ts_pins { + pinctrl-single,pins = < + 0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + 0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ + >; + }; + + vpfe0_pins_default: vpfe0_pins_default { + pinctrl-single,pins = < + 0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ + 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ + 0x1b8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/ + 0x1bc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/ + 0x1c0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ + 0x1c4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ + 0x1c8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ + 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ + 0x20c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ + 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ + 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ + 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ + 0x21c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ + 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ + 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ + >; + }; + + vpfe0_pins_sleep: vpfe0_pins_sleep { + pinctrl-single,pins = < + 0x1b0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + 0x1b4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + 0x1b8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + 0x1bc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + 0x1c0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + 0x1c4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + 0x1c8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + 0x20c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + 0x21c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ + 0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + 0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + 0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + 0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ + 0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ + 0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ + 0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + 0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + 0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + 0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ + 0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ + + /* Slave 2 */ + 0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + 0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + 0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + 0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + 0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + 0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + 0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + 0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ + 0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + 0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + 0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + 0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value */ + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + dss_pins: dss_pins { + pinctrl-single,pins = < + 0x020 (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ + 0x024 (PIN_OUTPUT | MUX_MODE1) + 0x028 (PIN_OUTPUT | MUX_MODE1) + 0x02c (PIN_OUTPUT | MUX_MODE1) + 0x030 (PIN_OUTPUT | MUX_MODE1) + 0x034 (PIN_OUTPUT | MUX_MODE1) + 0x038 (PIN_OUTPUT | MUX_MODE1) + 0x03c (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ + 0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ + 0x0a4 (PIN_OUTPUT | MUX_MODE0) + 0x0a8 (PIN_OUTPUT | MUX_MODE0) + 0x0ac (PIN_OUTPUT | MUX_MODE0) + 0x0b0 (PIN_OUTPUT | MUX_MODE0) + 0x0b4 (PIN_OUTPUT | MUX_MODE0) + 0x0b8 (PIN_OUTPUT | MUX_MODE0) + 0x0bc (PIN_OUTPUT | MUX_MODE0) + 0x0c0 (PIN_OUTPUT | MUX_MODE0) + 0x0c4 (PIN_OUTPUT | MUX_MODE0) + 0x0c8 (PIN_OUTPUT | MUX_MODE0) + 0x0cc (PIN_OUTPUT | MUX_MODE0) + 0x0d0 (PIN_OUTPUT | MUX_MODE0) + 0x0d4 (PIN_OUTPUT | MUX_MODE0) + 0x0d8 (PIN_OUTPUT | MUX_MODE0) + 0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ + 0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ + 0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ + 0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ + 0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ + + >; + }; + + qspi_pins: qspi_pins { + pinctrl-single,pins = < + 0x7c (PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */ + 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ + 0x90 (PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ + 0x94 (PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ + 0x98 (PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */ + 0x9c (PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ + >; + }; + + mcasp1_pins: mcasp1_pins { + pinctrl-single,pins = < + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + >; + }; + + lcd_pins: lcd_pins { + pinctrl-single,pins = < + 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ + >; + }; + + usb1_pins: usb1_pins { + pinctrl-single,pins = < + 0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ + >; + }; + + usb2_pins: usb2_pins { + pinctrl-single,pins = < + 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ + >; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + + tps@24 { + compatible = "ti,tps65218"; + reg = <0x24>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + compatible = "ti,tps65218-dcdc1"; + /* VDD_CORE limits min of OPP50 and max of OPP100 */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + compatible = "ti,tps65218-dcdc2"; + /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + compatible = "ti,tps65218-dcdc3"; + regulator-name = "vdds_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc4: regulator-dcdc4 { + compatible = "ti,tps65218-dcdc4"; + regulator-name = "v3_3d"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,tps65218-ldo1"; + regulator-name = "v1_8d"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + power-button { + compatible = "ti,tps65218-pwrbutton"; + status = "okay"; + interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + }; + }; + + at24@50 { + compatible = "at24,24c256"; + pagesize = <64>; + reg = <0x50>; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + + edt-ft5306@38 { + status = "okay"; + compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; + pinctrl-names = "default"; + pinctrl-0 = <&edt_ft5306_ts_pins>; + + reg = <0x38>; + interrupt-parent = <&gpio0>; + interrupts = <31 0>; + + reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + + touchscreen-size-x = <480>; + touchscreen-size-y = <272>; + }; + + tlv320aic3106: tlv320aic3106@1b { + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + AVDD-supply = <&dcdc4>; + IOVDD-supply = <&dcdc4>; + DRVDD-supply = <&dcdc4>; + DVDD-supply = <&ldo1>; + }; + + lis331dlh@18 { + compatible = "st,lis331dlh"; + reg = <0x18>; + status = "okay"; + + Vdd-supply = <&dcdc4>; + Vdd_IO-supply = <&dcdc4>; + interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + + vmmc-supply = <&dcdc4>; + bus-width = <4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; +}; + +&usb2_phy1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_pins>; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + + spi-max-frequency = <48000000>; + m25p80@0 { + compatible = "mx66l51235l"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpol; + spi-cpha; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first 512KiB + * for a valid file to boot(XIP). + */ + partition@0 { + label = "QSPI.U_BOOT"; + reg = <0x00000000 0x000080000>; + }; + partition@1 { + label = "QSPI.U_BOOT.backup"; + reg = <0x00080000 0x00080000>; + }; + partition@2 { + label = "QSPI.U-BOOT-SPL_OS"; + reg = <0x00100000 0x00010000>; + }; + partition@3 { + label = "QSPI.U_BOOT_ENV"; + reg = <0x00110000 0x00010000>; + }; + partition@4 { + label = "QSPI.U-BOOT-ENV.backup"; + reg = <0x00120000 0x00010000>; + }; + partition@5 { + label = "QSPI.KERNEL"; + reg = <0x00130000 0x0800000>; + }; + partition@6 { + label = "QSPI.FILESYSTEM"; + reg = <0x00930000 0x36D0000>; + }; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac = <1>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <4>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <5>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&elm { + status = "okay"; +}; + +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcasp1_pins>; + + status = "okay"; + + op-mode = <0>; + tdm-slots = <2>; + serial-dir = < + 0 0 1 2 + >; + + tx-num-evt = <1>; + rx-num-evt = <1>; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_pins>; + + port { + dpi_out: endpoint@0 { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&cpu { + cpu0-supply = <&dcdc2>; +}; + +&vpfe0 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&vpfe0_pins_default>; + pinctrl-1 = <&vpfe0_pins_sleep>; + + /* Camera port */ + port { + vpfe0_ep: endpoint { + /* remote-endpoint = <&sensor>; add once we have it */ + ti,am437x-vpfe-interface = <0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; +}; diff --git a/arch/arm/dts/am43xx-clocks.dtsi b/arch/arm/dts/am43xx-clocks.dtsi new file mode 100644 index 0000000..d0c0dfa --- /dev/null +++ b/arch/arm/dts/am43xx-clocks.dtsi @@ -0,0 +1,757 @@ +/* + * Device Tree Source for AM43xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&scm_clocks { + sys_clkin_ck: sys_clkin_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; + ti,bit-shift = <31>; + reg = <0x0040>; + }; + + crystal_freq_sel_ck: crystal_freq_sel_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; + ti,bit-shift = <29>; + reg = <0x0040>; + }; + + sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; + ti,bit-shift = <22>; + reg = <0x0040>; + }; + + adc_tsc_fck: adc_tsc_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dcan0_fck: dcan0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dcan1_fck: dcan1_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mcasp0_fck: mcasp0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mcasp1_fck: mcasp1_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + smartreflex0_fck: smartreflex0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + smartreflex1_fck: smartreflex1_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + sha0_fck: sha0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + aes0_fck: aes0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + ehrpwm0_tbclk: ehrpwm0_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <0>; + reg = <0x0664>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <1>; + reg = <0x0664>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm3_tbclk: ehrpwm3_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <4>; + reg = <0x0664>; + }; + + ehrpwm4_tbclk: ehrpwm4_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <5>; + reg = <0x0664>; + }; + + ehrpwm5_tbclk: ehrpwm5_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <6>; + reg = <0x0664>; + }; +}; +&prcm_clocks { + clk_32768_ck: clk_32768_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_rc32k_ck: clk_rc32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + virt_24000000_ck: virt_24000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + virt_25000000_ck: virt_25000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + virt_26000000_ck: virt_26000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + tclkin_ck: tclkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + dpll_core_ck: dpll_core_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-core-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2d20>, <0x2d24>, <0x2d2c>; + }; + + dpll_core_x2_ck: dpll_core_x2_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-x2-clock"; + clocks = <&dpll_core_ck>; + }; + + dpll_core_m4_ck: dpll_core_m4_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2d38>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_m5_ck: dpll_core_m5_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2d3c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_m6_ck: dpll_core_m6_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2d40>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_mpu_ck: dpll_mpu_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2d60>, <0x2d64>, <0x2d6c>; + }; + + dpll_mpu_m2_ck: dpll_mpu_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_mpu_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2d70>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_ddr_ck: dpll_ddr_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2da0>, <0x2da4>, <0x2dac>; + }; + + dpll_ddr_m2_ck: dpll_ddr_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_ddr_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2db0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_disp_ck: dpll_disp_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2e20>, <0x2e24>, <0x2e2c>; + }; + + dpll_disp_m2_ck: dpll_disp_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_disp_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2e30>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + ti,set-rate-parent; + }; + + dpll_per_ck: dpll_per_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-j-type-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2de0>, <0x2de4>, <0x2dec>; + }; + + dpll_per_m2_ck: dpll_per_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x2df0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + clk_24mhz: clk_24mhz { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + clkdiv32k_ck: clkdiv32k_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_24mhz>; + clock-mult = <1>; + clock-div = <732>; + }; + + clkdiv32k_ick: clkdiv32k_ick { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ck>; + ti,bit-shift = <8>; + reg = <0x2a38>; + }; + + sysclk_div: sysclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + pruss_ocp_gclk: pruss_ocp_gclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; + reg = <0x4248>; + }; + + clk_32k_tpm_ck: clk_32k_tpm_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + timer1_fck: timer1_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; + reg = <0x4200>; + }; + + timer2_fck: timer2_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4204>; + }; + + timer3_fck: timer3_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4208>; + }; + + timer4_fck: timer4_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x420c>; + }; + + timer5_fck: timer5_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4210>; + }; + + timer6_fck: timer6_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4214>; + }; + + timer7_fck: timer7_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4218>; + }; + + wdt1_fck: wdt1_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; + reg = <0x422c>; + }; + + l3_gclk: l3_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sysclk_div>; + clock-mult = <1>; + clock-div = <2>; + }; + + l4hs_gclk: l4hs_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l3s_gclk: l3s_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_div2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l4ls_gclk: l4ls_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_div2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + cpsw_125mhz_gclk: cpsw_125mhz_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m5_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; + reg = <0x4238>; + }; + + clk_32k_mosc_ck: clk_32k_mosc_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; + reg = <0x4240>; + }; + + gpio0_dbclk: gpio0_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&gpio0_dbclk_mux_ck>; + ti,bit-shift = <8>; + reg = <0x2b68>; + }; + + gpio1_dbclk: gpio1_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ick>; + ti,bit-shift = <8>; + reg = <0x8c78>; + }; + + gpio2_dbclk: gpio2_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ick>; + ti,bit-shift = <8>; + reg = <0x8c80>; + }; + + gpio3_dbclk: gpio3_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ick>; + ti,bit-shift = <8>; + reg = <0x8c88>; + }; + + gpio4_dbclk: gpio4_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ick>; + ti,bit-shift = <8>; + reg = <0x8c90>; + }; + + gpio5_dbclk: gpio5_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ick>; + ti,bit-shift = <8>; + reg = <0x8c98>; + }; + + mmc_clk: mmc_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sysclk_div>, <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + reg = <0x423c>; + }; + + gfx_fck_div_ck: gfx_fck_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&gfx_fclk_clksel_ck>; + reg = <0x423c>; + ti,max-div = <2>; + }; + + disp_clk: disp_clk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; + reg = <0x4244>; + ti,set-rate-parent; + }; + + dpll_extdev_ck: dpll_extdev_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2e60>, <0x2e64>, <0x2e6c>; + }; + + dpll_extdev_m2_ck: dpll_extdev_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_extdev_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x2e70>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + mux_synctimer32k_ck: mux_synctimer32k_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; + reg = <0x4230>; + }; + + synctimer_32kclk: synctimer_32kclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&mux_synctimer32k_ck>; + ti,bit-shift = <8>; + reg = <0x2a30>; + }; + + timer8_fck: timer8_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; + reg = <0x421c>; + }; + + timer9_fck: timer9_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; + reg = <0x4220>; + }; + + timer10_fck: timer10_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; + reg = <0x4224>; + }; + + timer11_fck: timer11_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; + reg = <0x4228>; + }; + + cpsw_50m_clkdiv: cpsw_50m_clkdiv { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m5_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + cpsw_5m_clkdiv: cpsw_5m_clkdiv { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpsw_50m_clkdiv>; + clock-mult = <1>; + clock-div = <10>; + }; + + dpll_ddr_x2_ck: dpll_ddr_x2_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-x2-clock"; + clocks = <&dpll_ddr_ck>; + }; + + dpll_ddr_m4_ck: dpll_ddr_m4_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_ddr_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2db8>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_clkdcoldo: dpll_per_clkdcoldo { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&dpll_per_ck>; + ti,clock-mult = <1>; + ti,clock-div = <1>; + ti,autoidle-shift = <8>; + reg = <0x2e14>; + ti,invert-autoidle-bit; + }; + + dll_aging_clk_div: dll_aging_clk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkin_ck>; + reg = <0x4250>; + ti,dividers = <8>, <16>, <32>; + }; + + div_core_25m_ck: div_core_25m_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sysclk_div>; + clock-mult = <1>; + clock-div = <8>; + }; + + func_12m_clk: func_12m_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + vtp_clk_div: vtp_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + usbphy_32khz_clkmux: usbphy_32khz_clkmux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; + reg = <0x4260>; + }; + + usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&usbphy_32khz_clkmux>; + ti,bit-shift = <8>; + reg = <0x2a40>; + }; + + usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&usbphy_32khz_clkmux>; + ti,bit-shift = <8>; + reg = <0x2a48>; + }; + + usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_clkdcoldo>; + ti,bit-shift = <8>; + reg = <0x8a60>; + }; + + usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_clkdcoldo>; + ti,bit-shift = <8>; + reg = <0x8a68>; + }; +}; diff --git a/arch/arm/dts/am57xx-beagle-x15.dts b/arch/arm/dts/am57xx-beagle-x15.dts new file mode 100644 index 0000000..e424562 --- /dev/null +++ b/arch/arm/dts/am57xx-beagle-x15.dts @@ -0,0 +1,699 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra74x.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "TI AM5728 BeagleBoard-X15"; + compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; + + chosen { + stdout-path = &uart3; + }; + + aliases { + rtc0 = &mcp_rtc; + rtc1 = &tps659038_rtc; + rtc2 = &rtc; + display0 = &hdmi0; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + vdd_3v3: fixedregulator-vdd_3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <®en1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vtt_fixed: fixedregulator-vtt { + /* TPS51200 */ + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + vin-supply = <&smps3_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>; + + led@0 { + label = "beagle-x15:usr0"; + gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@1 { + label = "beagle-x15:usr1"; + gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led@2 { + label = "beagle-x15:usr2"; + gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@3 { + label = "beagle-x15:usr3"; + gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "ide-disk"; + default-state = "off"; + }; + }; + + gpio_fan: gpio_fan { + /* Based on 5v 500mA AFB02505HHB */ + compatible = "gpio-fan"; + gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0>, + <13000 1>; + #cooling-cells = <2>; + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&extcon_usb1_pins>; + }; + + extcon_usb2: extcon_usb2 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&gpio7 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&extcon_usb2_pins>; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + pinctrl-names = "default"; + pinctrl-0 = <&tpd12s015_pins>; + + gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ + <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&dra7_pmx_core { + leds_pins_default: leds_pins_default { + pinctrl-single,pins = < + 0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */ + 0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */ + 0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */ + 0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */ + >; + }; + + i2c1_pins_default: i2c1_pins_default { + pinctrl-single,pins = < + 0x400 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ + 0x404 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ + >; + }; + + hdmi_pins: pinmux_hdmi_pins { + pinctrl-single,pins = < + 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ + 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ + >; + }; + + i2c3_pins_default: i2c3_pins_default { + pinctrl-single,pins = < + 0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ + 0x2a8 (PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ + >; + }; + + uart3_pins_default: uart3_pins_default { + pinctrl-single,pins = < + 0x3f8 (PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */ + 0x3fc (PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */ + >; + }; + + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + cpsw_pins_default: cpsw_pins_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */ + 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */ + 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */ + 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */ + 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */ + 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */ + 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */ + 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */ + 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */ + 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */ + 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */ + 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */ + + /* Slave 2 */ + 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */ + 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */ + 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */ + 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */ + 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */ + 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */ + 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */ + 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */ + 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */ + 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */ + 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */ + 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */ + >; + + }; + + cpsw_pins_sleep: cpsw_pins_sleep { + pinctrl-single,pins = < + /* Slave 1 */ + 0x250 (PIN_INPUT | MUX_MODE15) + 0x254 (PIN_INPUT | MUX_MODE15) + 0x258 (PIN_INPUT | MUX_MODE15) + 0x25c (PIN_INPUT | MUX_MODE15) + 0x260 (PIN_INPUT | MUX_MODE15) + 0x264 (PIN_INPUT | MUX_MODE15) + 0x268 (PIN_INPUT | MUX_MODE15) + 0x26c (PIN_INPUT | MUX_MODE15) + 0x270 (PIN_INPUT | MUX_MODE15) + 0x274 (PIN_INPUT | MUX_MODE15) + 0x278 (PIN_INPUT | MUX_MODE15) + 0x27c (PIN_INPUT | MUX_MODE15) + + /* Slave 2 */ + 0x198 (PIN_INPUT | MUX_MODE15) + 0x19c (PIN_INPUT | MUX_MODE15) + 0x1a0 (PIN_INPUT | MUX_MODE15) + 0x1a4 (PIN_INPUT | MUX_MODE15) + 0x1a8 (PIN_INPUT | MUX_MODE15) + 0x1ac (PIN_INPUT | MUX_MODE15) + 0x1b0 (PIN_INPUT | MUX_MODE15) + 0x1b4 (PIN_INPUT | MUX_MODE15) + 0x1b8 (PIN_INPUT | MUX_MODE15) + 0x1bc (PIN_INPUT | MUX_MODE15) + 0x1c0 (PIN_INPUT | MUX_MODE15) + 0x1c4 (PIN_INPUT | MUX_MODE15) + >; + }; + + davinci_mdio_pins_default: davinci_mdio_pins_default { + pinctrl-single,pins = < + /* MDIO */ + 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_mclk */ + 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_d */ + >; + }; + + davinci_mdio_pins_sleep: davinci_mdio_pins_sleep { + pinctrl-single,pins = < + 0x23c (PIN_INPUT | MUX_MODE15) + 0x240 (PIN_INPUT | MUX_MODE15) + >; + }; + + tps659038_pins_default: tps659038_pins_default { + pinctrl-single,pins = < + 0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ + >; + }; + + tmp102_pins_default: tmp102_pins_default { + pinctrl-single,pins = < + 0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */ + >; + }; + + mcp79410_pins_default: mcp79410_pins_default { + pinctrl-single,pins = < + 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ + >; + }; + + usb1_pins: pinmux_usb1_pins { + pinctrl-single,pins = < + 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ + >; + }; + + extcon_usb1_pins: extcon_usb1_pins { + pinctrl-single,pins = < + 0x3ec (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */ + >; + }; + + extcon_usb2_pins: extcon_usb2_pins { + pinctrl-single,pins = < + 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_ctsn.gpio7_24 */ + >; + }; + + tpd12s015_pins: pinmux_tpd12s015_pins { + pinctrl-single,pins = < + 0x3b0 (PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */ + 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ + 0x370 (PIN_OUTPUT | MUX_MODE14) /* gpio6_28 LS_OE */ + >; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_default>; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&tps659038_pins_default>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + regulators { + smps12_reg: smps12 { + /* VDD_MPU */ + regulator-name = "smps12"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps3_reg: smps3 { + /* VDD_DDR */ + regulator-name = "smps3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_CORE */ + regulator-name = "smps6"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1030000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SMPS7 unused */ + + smps8_reg: smps8 { + /* VDD_1V8 */ + regulator-name = "smps8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SMPS9 unused */ + + ldo1_reg: ldo1 { + /* VDD_SD */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + ldo2_reg: ldo2 { + /* VDD_SHV5 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + regen1: regen1 { + /* VDD_3V3_ON */ + regulator-name = "regen1"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659038_rtc: tps659038_rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&tps659038>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + + tps659038_gpio: tps659038_gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + tmp102: tmp102@48 { + compatible = "ti,tmp102"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&tmp102_pins_default>; + interrupt-parent = <&gpio7>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_default>; + clock-frequency = <400000>; + + mcp_rtc: rtc@6f { + compatible = "microchip,mcp7941x"; + reg = <0x6f>; + interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; /* IRQ_SYS_1N */ + + pinctrl-names = "default"; + pinctrl-0 = <&mcp79410_pins_default>; + + vcc-supply = <&vdd_3v3>; + wakeup-source; + }; +}; + +&gpio7 { + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&cpu0 { + cpu0-supply = <&smps12_reg>; + voltage-tolerance = <1>; +}; + +&uart3 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3f8>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_default>; +}; + +&mac { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_pins_default>; + pinctrl-1 = <&cpsw_pins_sleep>; + dual_emac; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <2>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_pins_default>; + pinctrl-1 = <&davinci_mdio_pins_sleep>; +}; + +&mmc1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + + vmmc-supply = <&ldo1_reg>; + vmmc_aux-supply = <&vdd_3v3>; + pbias-supply = <&pbias_mmc_reg>; + bus-width = <4>; + cd-gpios = <&gpio6 27 0>; /* gpio 219 */ +}; + +&mmc2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; + + vmmc-supply = <&vdd_3v3>; + bus-width = <8>; + ti,non-removable; + cap-mmc-dual-data-rate; +}; + +&sata { + status = "okay"; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; +}; + +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&usb2 { + dr_mode = "peripheral"; +}; + +&cpu_trips { + cpu_alert1: cpu_alert1 { + temperature = <50000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; +}; + +&cpu_cooling_maps { + map1 { + trip = <&cpu_alert1>; + cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&thermal_zones { + board_thermal: board_thermal { + polling-delay-passive = <1250>; /* milliseconds */ + polling-delay = <1500>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tmp102 0>; + + board_trips: trips { + board_alert0: board_alert { + temperature = <40000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + + board_crit: board_crit { + temperature = <105000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + board_cooling_maps: cooling-maps { + map0 { + trip = <&board_alert0>; + cooling-device = + <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&dss { + status = "ok"; + + vdda_video-supply = <&ldoln_reg>; +}; + +&hdmi { + status = "ok"; + vdda-supply = <&ldo3_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; diff --git a/arch/arm/dts/armada-370-xp.dtsi b/arch/arm/dts/armada-370-xp.dtsi new file mode 100644 index 0000000..a718866 --- /dev/null +++ b/arch/arm/dts/armada-370-xp.dtsi @@ -0,0 +1,333 @@ +/* + * Device Tree Include file for Marvell Armada 370 and Armada XP SoC + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem <alior@marvell.com> + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * Ben Dooks <ben.dooks@codethink.co.uk> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * This file contains the definitions that are common to the Armada + * 370 and Armada XP SoC. + */ + +/include/ "skeleton64.dtsi" + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + model = "Marvell Armada 370 and XP SoC"; + compatible = "marvell,armada-370-xp"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "marvell,sheeva-v7"; + device_type = "cpu"; + reg = <0>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + + soc { + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + interrupt-parent = <&mpic>; + pcie-mem-aperture = <0xf8000000 0x7e00000>; + pcie-io-aperture = <0xffe00000 0x100000>; + + devbus-bootcs { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; + ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs0 { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; + ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs1 { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; + ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs2 { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; + ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs3 { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; + ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + rtc@10300 { + compatible = "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <50>; + }; + + spi0: spi@10600 { + reg = <0x10600 0x28>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <30>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + reg = <0x10680 0x28>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <92>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <31>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <32>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <41>; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <42>; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + pinctrl: pin-ctrl@18000 { + reg = <0x18000 0x38>; + }; + + coredivclk: corediv-clock@18740 { + compatible = "marvell,armada-370-corediv-clock"; + reg = <0x18740 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>, + <0x20250 0x8>; + }; + + mpic: interrupt-controller@20a00 { + compatible = "marvell,mpic"; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + msi-controller; + }; + + coherency-fabric@20200 { + compatible = "marvell,coherency-fabric"; + reg = <0x20200 0xb0>, <0x21010 0x1c>; + }; + + timer@20300 { + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts = <37>, <38>, <39>, <40>, <5>, <6>; + }; + + watchdog@20300 { + reg = <0x20300 0x34>, <0x20704 0x4>; + }; + + pmsu@22000 { + compatible = "marvell,armada-370-pmsu"; + reg = <0x22000 0x1000>; + }; + + usb@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x500>; + interrupts = <45>; + status = "disabled"; + }; + + usb@51000 { + compatible = "marvell,orion-ehci"; + reg = <0x51000 0x500>; + interrupts = <46>; + status = "disabled"; + }; + + eth0: ethernet@70000 { + reg = <0x70000 0x4000>; + interrupts = <8>; + clocks = <&gateclk 4>; + status = "disabled"; + }; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x72004 0x4>; + clocks = <&gateclk 4>; + }; + + eth1: ethernet@74000 { + reg = <0x74000 0x4000>; + interrupts = <10>; + clocks = <&gateclk 3>; + status = "disabled"; + }; + + sata@a0000 { + compatible = "marvell,armada-370-sata"; + reg = <0xa0000 0x5000>; + interrupts = <55>; + clocks = <&gateclk 15>, <&gateclk 30>; + clock-names = "0", "1"; + status = "disabled"; + }; + + nand@d0000 { + compatible = "marvell,armada370-nand"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <113>; + clocks = <&coredivclk 0>; + status = "disabled"; + }; + + mvsdio@d4000 { + compatible = "marvell,orion-sdio"; + reg = <0xd4000 0x200>; + interrupts = <54>; + clocks = <&gateclk 17>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + }; + }; + + clocks { + /* 2 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + }; + }; diff --git a/arch/arm/dts/armada-380.dtsi b/arch/arm/dts/armada-380.dtsi new file mode 100644 index 0000000..5102d19 --- /dev/null +++ b/arch/arm/dts/armada-380.dtsi @@ -0,0 +1,152 @@ +/* + * Device Tree Include file for Marvell Armada 380 SoC. + * + * Copyright (C) 2014 Marvell + * + * Lior Amsalem <alior@marvell.com> + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "armada-38x.dtsi" + +/ { + model = "Marvell Armada 380 family SoC"; + compatible = "marvell,armada380"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-380-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + }; + + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6810-pinctrl"; + }; + }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; + + /* x1 port */ + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + /* x1 port */ + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + /* x1 port */ + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/armada-385.dtsi b/arch/arm/dts/armada-385.dtsi new file mode 100644 index 0000000..8e67d2c --- /dev/null +++ b/arch/arm/dts/armada-385.dtsi @@ -0,0 +1,184 @@ +/* + * Device Tree Include file for Marvell Armada 385 SoC. + * + * Copyright (C) 2014 Marvell + * + * Lior Amsalem <alior@marvell.com> + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "armada-38x.dtsi" + +/ { + model = "Marvell Armada 385 family SoC"; + compatible = "marvell,armada385", "marvell,armada380"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-380-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6820-pinctrl"; + }; + }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; + + /* + * This port can be either x4 or x1. When + * configured in x4 by the bootloader, then + * pcie@4,0 is not available. + */ + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + /* x1 port */ + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + /* x1 port */ + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + /* + * x1 port only available when pcie@1,0 is + * configured as a x1 port + */ + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/armada-388-gp.dts b/arch/arm/dts/armada-388-gp.dts new file mode 100644 index 0000000..fd4f6fd --- /dev/null +++ b/arch/arm/dts/armada-388-gp.dts @@ -0,0 +1,413 @@ +/* + * Device Tree file for Marvell Armada 385 development board + * (RD-88F6820-GP) + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-388.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Marvell Armada 385 GP"; + compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; + + internal-regs { + spi@10600 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; + }; + + i2c@11000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; + /* + * The EEPROM located at adresse 54 is needed + * for the boot - DO NOT ERASE IT - + */ + + expander0: pca9555@20 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pca0_pins>; + interrupt-parent = <&gpio0>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x20>; + }; + + expander1: pca9555@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + interrupt-parent = <&gpio0>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x21>; + }; + + }; + + serial@12000 { + /* + * Exported on the micro USB connector CON16 + * through an FTDI + */ + + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; + + /* GE1 CON15 */ + ethernet@30000 { + pinctrl-names = "default"; + pinctrl-0 = <&ge1_rgmii_pins>; + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + /* CON4 */ + usb@58000 { + vcc-supply = <®_usb2_0_vbus>; + status = "okay"; + }; + + /* GE0 CON1 */ + ethernet@70000 { + pinctrl-names = "default"; + /* + * The Reference Clock 0 is used to provide a + * clock to the PHY + */ + pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + + mdio@72004 { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + + phy1: ethernet-phy@0 { + reg = <0>; + }; + }; + + sata@a8000 { + pinctrl-names = "default"; + pinctrl-0 = <&sata0_pins>, <&sata1_pins>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + target-supply = <®_5v_sata0>; + }; + + sata1: sata-port@1 { + reg = <1>; + target-supply = <®_5v_sata1>; + }; + }; + + sata@e0000 { + pinctrl-names = "default"; + pinctrl-0 = <&sata2_pins>, <&sata3_pins>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + sata2: sata-port@0 { + reg = <0>; + target-supply = <®_5v_sata2>; + }; + + sata3: sata-port@1 { + reg = <1>; + target-supply = <®_5v_sata3>; + }; + }; + + sdhci@d8000 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; + cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>; + no-1-8-v; + wp-inverted; + bus-width = <8>; + status = "okay"; + }; + + /* CON5 */ + usb3@f0000 { + vcc-supply = <®_usb2_1_vbus>; + status = "okay"; + }; + + /* CON7 */ + usb3@f8000 { + vcc-supply = <®_usb3_vbus>; + status = "okay"; + }; + }; + + pcie-controller { + status = "okay"; + /* + * One PCIe units is accessible through + * standard PCIe slot on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* + * The two other PCIe units are accessible + * through mini PCIe slot on the board. + */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + pcie@3,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + }; + + gpio-fan { + compatible = "gpio-fan"; + gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 3000 1>; + }; + }; + + reg_usb3_vbus: usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; + }; + + reg_usb2_0_vbus: v5-vbus0 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-vbus0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; + }; + + reg_usb2_1_vbus: v5-vbus1 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-vbus1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; + }; + + reg_usb2_1_vbus: v5-vbus1 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-vbus1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; + }; + + reg_sata0: pwr-sata0 { + compatible = "regulator-fixed"; + regulator-name = "pwr_en_sata0"; + enable-active-high; + regulator-always-on; + + }; + + reg_5v_sata0: v5-sata0 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-sata0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_sata0>; + }; + + reg_12v_sata0: v12-sata0 { + compatible = "regulator-fixed"; + regulator-name = "v12.0-sata0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + vin-supply = <®_sata0>; + }; + + reg_sata1: pwr-sata1 { + regulator-name = "pwr_en_sata1"; + compatible = "regulator-fixed"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + regulator-always-on; + gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; + }; + + reg_5v_sata1: v5-sata1 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-sata1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_sata1>; + }; + + reg_12v_sata1: v12-sata1 { + compatible = "regulator-fixed"; + regulator-name = "v12.0-sata1"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + vin-supply = <®_sata1>; + }; + + reg_sata2: pwr-sata2 { + compatible = "regulator-fixed"; + regulator-name = "pwr_en_sata2"; + enable-active-high; + regulator-always-on; + gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; + }; + + reg_5v_sata2: v5-sata2 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-sata2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_sata2>; + }; + + reg_12v_sata2: v12-sata2 { + compatible = "regulator-fixed"; + regulator-name = "v12.0-sata2"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + vin-supply = <®_sata2>; + }; + + reg_sata3: pwr-sata3 { + compatible = "regulator-fixed"; + regulator-name = "pwr_en_sata3"; + enable-active-high; + regulator-always-on; + gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; + }; + + reg_5v_sata3: v5-sata3 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-sata3"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_sata3>; + }; + + reg_12v_sata3: v12-sata3 { + compatible = "regulator-fixed"; + regulator-name = "v12.0-sata3"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + vin-supply = <®_sata3>; + }; +}; + +&pinctrl { + pca0_pins: pca0_pins { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/dts/sun8i-a33-et-q8-v1.6.dts b/arch/arm/dts/armada-388.dtsi index 19db844..564fa59 100644 --- a/arch/arm/dts/sun8i-a33-et-q8-v1.6.dts +++ b/arch/arm/dts/armada-388.dtsi @@ -1,21 +1,18 @@ /* - * Copyright 2015 Vishnu Patekar - * Vishnu Patekar <vishnupatekar0510@gmail.com> + * Device Tree Include file for Marvell Armada 388 SoC. + * + * Copyright (C) 2015 Marvell + * + * Gregory CLEMENT <gregory.clement@free-electrons.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. * * Or, alternatively, * @@ -39,50 +36,35 @@ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. + * + * + * The main difference with the Armada 385 is that the 388 can handle two more + * SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl + * property and the name of the SoC, and add the second SATA host which control + * the 2 other ports. */ -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include "armada-385.dtsi" / { - model = "ET Q8 Quad Core Tablet (v1.6)"; - compatible = "et,q8-v1.6", "allwinner,sun8i-a33"; - - aliases { - serial0 = &uart0; - }; + model = "Marvell Armada 388 family SoC"; + compatible = "marvell,armada388", "marvell,armada385", + "marvell,armada380"; - chosen { - stdout-path = "serial0:115200n8"; - }; -}; + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6828-pinctrl"; + }; -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; + sata@e0000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xe0000 0x2000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 30>; + status = "disabled"; + }; - button@200 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <200000>; + }; }; - - button@400 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <400000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; }; diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi new file mode 100644 index 0000000..04ecfe6 --- /dev/null +++ b/arch/arm/dts/armada-38x.dtsi @@ -0,0 +1,600 @@ +/* + * Device Tree Include file for Marvell Armada 38x family of SoCs. + * + * Copyright (C) 2014 Marvell + * + * Lior Amsalem <alior@marvell.com> + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + +/ { + model = "Marvell Armada 38x family SoC"; + compatible = "marvell,armada380"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + serial0 = &uart0; + serial1 = &uart1; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + + soc { + compatible = "marvell,armada380-mbus", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + interrupt-parent = <&gic>; + pcie-mem-aperture = <0xe0000000 0x8000000>; + pcie-io-aperture = <0xe8000000 0x100000>; + + bootrom { + compatible = "marvell,bootrom"; + reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; + }; + + devbus-bootcs { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; + ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs0 { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; + ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs1 { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; + ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs2 { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; + ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs3 { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; + ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + L2: cache-controller@8000 { + compatible = "arm,pl310-cache"; + reg = <0x8000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + scu@c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xc000 0x58>; + }; + + timer@c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xc600 0x20>; + interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; + clocks = <&coreclk 2>; + }; + + gic: interrupt-controller@d000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + interrupt-controller; + reg = <0xd000 0x1000>, + <0xc100 0x100>; + }; + + spi0: spi@10600 { + compatible = "marvell,armada-380-spi", + "marvell,orion-spi"; + reg = <0x10600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,armada-380-spi", + "marvell,orion-spi"; + reg = <0x10680 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + pinctrl: pinctrl@18000 { + reg = <0x18000 0x20>; + + ge0_rgmii_pins: ge-rgmii-pins-0 { + marvell,pins = "mpp6", "mpp7", "mpp8", + "mpp9", "mpp10", "mpp11", + "mpp12", "mpp13", "mpp14", + "mpp15", "mpp16", "mpp17"; + marvell,function = "ge0"; + }; + + ge1_rgmii_pins: ge-rgmii-pins-1 { + marvell,pins = "mpp21", "mpp27", "mpp28", + "mpp29", "mpp30", "mpp31", + "mpp32", "mpp37", "mpp38", + "mpp39", "mpp40", "mpp41"; + marvell,function = "ge1"; + }; + + i2c0_pins: i2c-pins-0 { + marvell,pins = "mpp2", "mpp3"; + marvell,function = "i2c0"; + }; + + mdio_pins: mdio-pins { + marvell,pins = "mpp4", "mpp5"; + marvell,function = "ge"; + }; + + ref_clk0_pins: ref-clk-pins-0 { + marvell,pins = "mpp45"; + marvell,function = "ref"; + }; + + ref_clk1_pins: ref-clk-pins-1 { + marvell,pins = "mpp46"; + marvell,function = "ref"; + }; + + spi0_pins: spi-pins-0 { + marvell,pins = "mpp22", "mpp23", "mpp24", + "mpp25"; + marvell,function = "spi0"; + }; + + spi1_pins: spi-pins-1 { + marvell,pins = "mpp56", "mpp57", "mpp58", + "mpp59"; + marvell,function = "spi1"; + }; + + uart0_pins: uart-pins-0 { + marvell,pins = "mpp0", "mpp1"; + marvell,function = "ua0"; + }; + + uart1_pins: uart-pins-1 { + marvell,pins = "mpp19", "mpp20"; + marvell,function = "ua1"; + }; + + sdhci_pins: sdhci-pins { + marvell,pins = "mpp48", "mpp49", "mpp50", + "mpp52", "mpp53", "mpp54", + "mpp55", "mpp57", "mpp58", + "mpp59"; + marvell,function = "sd0"; + }; + + sata0_pins: sata-pins-0 { + marvell,pins = "mpp20"; + marvell,function = "sata0"; + }; + + sata1_pins: sata-pins-1 { + marvell,pins = "mpp19"; + marvell,function = "sata1"; + }; + + sata2_pins: sata-pins-2 { + marvell,pins = "mpp47"; + marvell,function = "sata2"; + }; + + sata3_pins: sata-pins-3 { + marvell,pins = "mpp44"; + marvell,function = "sata3"; + }; + }; + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <28>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + }; + + system-controller@18200 { + compatible = "marvell,armada-380-system-controller", + "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x100>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-380-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + coreclk: mvebu-sar@18600 { + compatible = "marvell,armada-380-core-clock"; + reg = <0x18600 0x04>; + #clock-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>; + }; + + mpic: interrupt-controller@20a00 { + compatible = "marvell,mpic"; + reg = <0x20a00 0x2d0>, <0x21070 0x58>; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + msi-controller; + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer@20300 { + compatible = "marvell,armada-380-timer", + "marvell,armada-xp-timer"; + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <&mpic 5>, + <&mpic 6>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + + watchdog@20300 { + compatible = "marvell,armada-380-wdt"; + reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + + cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x10>; + }; + + mpcore-soc-ctrl@20d20 { + compatible = "marvell,armada-380-mpcore-soc-ctrl"; + reg = <0x20d20 0x6c>; + }; + + coherency-fabric@21010 { + compatible = "marvell,armada-380-coherency-fabric"; + reg = <0x21010 0x1c>; + }; + + pmsu@22000 { + compatible = "marvell,armada-380-pmsu"; + reg = <0x22000 0x1000>; + }; + + eth1: ethernet@30000 { + compatible = "marvell,armada-370-neta"; + reg = <0x30000 0x4000>; + interrupts-extended = <&mpic 10>; + clocks = <&gateclk 3>; + status = "disabled"; + }; + + eth2: ethernet@34000 { + compatible = "marvell,armada-370-neta"; + reg = <0x34000 0x4000>; + interrupts-extended = <&mpic 12>; + clocks = <&gateclk 2>; + status = "disabled"; + }; + + usb@58000 { + compatible = "marvell,orion-ehci"; + reg = <0x58000 0x500>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 18>; + status = "disabled"; + }; + + xor@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60a00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor00 { + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gateclk 28>; + status = "okay"; + + xor10 { + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + eth0: ethernet@70000 { + compatible = "marvell,armada-370-neta"; + reg = <0x70000 0x4000>; + interrupts-extended = <&mpic 8>; + clocks = <&gateclk 4>; + status = "disabled"; + }; + + mdio: mdio@72004 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x72004 0x4>; + clocks = <&gateclk 4>; + }; + + rtc@a3800 { + compatible = "marvell,armada-380-rtc"; + reg = <0xa3800 0x20>, <0x184a0 0x0c>; + reg-names = "rtc", "rtc-soc"; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + }; + + sata@a8000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xa8000 0x2000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 15>; + status = "disabled"; + }; + + sata@e0000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xe0000 0x2000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 30>; + status = "disabled"; + }; + + coredivclk: clock@e4250 { + compatible = "marvell,armada-380-corediv-clock"; + reg = <0xe4250 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + + thermal@e8078 { + compatible = "marvell,armada380-thermal"; + reg = <0xe4078 0x4>, <0xe4074 0x4>; + status = "okay"; + }; + + flash@d0000 { + compatible = "marvell,armada370-nand"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&coredivclk 0>; + status = "disabled"; + }; + + sdhci@d8000 { + compatible = "marvell,armada-380-sdhci"; + reg-names = "sdhci", "mbus", "conf-sdio3"; + reg = <0xd8000 0x1000>, + <0xdc000 0x100>, + <0x18454 0x4>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 17>; + mrvl,clk-delay-cycles = <0x1F>; + status = "disabled"; + }; + + usb3@f0000 { + compatible = "marvell,armada-380-xhci"; + reg = <0xf0000 0x4000>,<0xf4000 0x4000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + + usb3@f8000 { + compatible = "marvell,armada-380-xhci"; + reg = <0xf8000 0x4000>,<0xfc000 0x4000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 10>; + status = "disabled"; + }; + }; + }; + + clocks { + /* 2 GHz fixed main PLL */ + mainpll: mainpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; +}; diff --git a/arch/arm/dts/armada-xp-gp.dts b/arch/arm/dts/armada-xp-gp.dts new file mode 100644 index 0000000..bf724ca --- /dev/null +++ b/arch/arm/dts/armada-xp-gp.dts @@ -0,0 +1,245 @@ +/* + * Device Tree file for Marvell Armada XP development board + * (DB-MV784MP-GP) + * + * Copyright (C) 2013-2014 Marvell + * + * Lior Amsalem <alior@marvell.com> + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "armada-xp-mv78460.dtsi" + +/ { + model = "Marvell Armada XP Development Board DB-MV784MP-GP"; + compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + /* + * 8 GB of plug-in RAM modules by default.The amount + * of memory available can be changed by the + * bootloader according the size of the module + * actually plugged. However, memory between + * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is + * the address range used for I/O (internal registers, + * MBus windows). + */ + reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, + <0x00000001 0x00000000 0x00000001 0x00000000>; + }; + + cpus { + pm_pic { + ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, + <&gpio0 17 GPIO_ACTIVE_LOW>, + <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; + + devbus-bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 16 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <2>; + }; + }; + + pcie-controller { + status = "okay"; + + /* + * The 3 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; + }; + + internal-regs { + serial@12000 { + status = "okay"; + }; + serial@12100 { + status = "okay"; + }; + serial@12200 { + status = "okay"; + }; + serial@12300 { + status = "okay"; + }; + pinctrl { + pinctrl-0 = <&pic_pins>; + pinctrl-names = "default"; + pic_pins: pic-pins-0 { + marvell,pins = "mpp16", "mpp17", + "mpp18"; + marvell,function = "gpio"; + }; + }; + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + mdio { + phy0: ethernet-phy@0 { + reg = <16>; + }; + + phy1: ethernet-phy@1 { + reg = <17>; + }; + + phy2: ethernet-phy@2 { + reg = <18>; + }; + + phy3: ethernet-phy@3 { + reg = <19>; + }; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "qsgmii"; + }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "qsgmii"; + }; + ethernet@30000 { + status = "okay"; + phy = <&phy2>; + phy-mode = "qsgmii"; + }; + ethernet@34000 { + status = "okay"; + phy = <&phy3>; + phy-mode = "qsgmii"; + }; + + /* Front-side USB slot */ + usb@50000 { + status = "okay"; + }; + + /* Back-side USB slot */ + usb@51000 { + status = "okay"; + }; + + spi0: spi@10600 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + }; + }; + }; +}; diff --git a/arch/arm/dts/armada-xp-mv78230.dtsi b/arch/arm/dts/armada-xp-mv78230.dtsi new file mode 100644 index 0000000..6e6d0f0 --- /dev/null +++ b/arch/arm/dts/armada-xp-mv78230.dtsi @@ -0,0 +1,231 @@ +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Contains definitions specific to the Armada XP MV78230 SoC that are not + * common to all Armada XP SoCs. + */ + +#include "armada-xp.dtsi" + +/ { + model = "Marvell Armada XP MV78230 SoC"; + compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-xp-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; + clock-latency = <1000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + clock-latency = <1000000>; + }; + }; + + soc { + /* + * MV78230 has 2 PCIe units Gen2.0: One unit can be + * configured as x4 or quad x1 lanes. One unit is + * x1 only. + */ + pcie-controller { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ + 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + pcie@5,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + }; + + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <17>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>; + }; + }; + }; +}; + +&pinctrl { + compatible = "marvell,mv78230-pinctrl"; +}; diff --git a/arch/arm/dts/armada-xp-mv78260.dtsi b/arch/arm/dts/armada-xp-mv78260.dtsi new file mode 100644 index 0000000..c5fdc99 --- /dev/null +++ b/arch/arm/dts/armada-xp-mv78260.dtsi @@ -0,0 +1,333 @@ +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Contains definitions specific to the Armada XP MV78260 SoC that are not + * common to all Armada XP SoCs. + */ + +#include "armada-xp.dtsi" + +/ { + model = "Marvell Armada XP MV78260 SoC"; + compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-xp-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; + clock-latency = <1000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + clock-latency = <1000000>; + }; + }; + + soc { + /* + * MV78260 has 3 PCIe units Gen2.0: Two units can be + * configured as x4 or quad x1 lanes. One unit is + * x4 only. + */ + pcie-controller { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ + 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ + 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ + + 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ + 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ + 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ + 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ + 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ + 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ + 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ + + 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ + 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + pcie@5,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + + pcie@6,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 + 0x81000000 0 0 0x81000000 0x6 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 63>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 10>; + status = "disabled"; + }; + + pcie@7,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; + reg = <0x3800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 + 0x81000000 0 0 0x81000000 0x7 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 64>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 11>; + status = "disabled"; + }; + + pcie@8,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; + reg = <0x4000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 + 0x81000000 0 0 0x81000000 0x8 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 65>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 12>; + status = "disabled"; + }; + + pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + }; + }; + + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; + }; + + gpio2: gpio@18180 { + compatible = "marvell,orion-gpio"; + reg = <0x18180 0x40>; + ngpios = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <91>; + }; + + eth3: ethernet@34000 { + compatible = "marvell,armada-xp-neta"; + reg = <0x34000 0x4000>; + interrupts = <14>; + clocks = <&gateclk 1>; + status = "disabled"; + }; + }; + }; +}; + +&pinctrl { + compatible = "marvell,mv78260-pinctrl"; +}; diff --git a/arch/arm/dts/armada-xp-mv78460.dtsi b/arch/arm/dts/armada-xp-mv78460.dtsi new file mode 100644 index 0000000..0e24f1a --- /dev/null +++ b/arch/arm/dts/armada-xp-mv78460.dtsi @@ -0,0 +1,371 @@ +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Contains definitions specific to the Armada XP MV78460 SoC that are not + * common to all Armada XP SoCs. + */ + +#include "armada-xp.dtsi" + +/ { + model = "Marvell Armada XP MV78460 SoC"; + compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-xp-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; + clock-latency = <1000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + clock-latency = <1000000>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <2>; + clocks = <&cpuclk 2>; + clock-latency = <1000000>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <3>; + clocks = <&cpuclk 3>; + clock-latency = <1000000>; + }; + }; + + soc { + /* + * MV78460 has 4 PCIe units Gen2.0: Two units can be + * configured as x4 or quad x1 lanes. Two units are + * x4/x1. + */ + pcie-controller { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ + 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ + 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ + 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ + + 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ + 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ + 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ + 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ + 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ + 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ + 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ + + 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ + 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ + + 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ + 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + pcie@5,0 { + device_type = "pci"; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + + pcie@6,0 { + device_type = "pci"; + assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 + 0x81000000 0 0 0x81000000 0x6 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 63>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 10>; + status = "disabled"; + }; + + pcie@7,0 { + device_type = "pci"; + assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; + reg = <0x3800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 + 0x81000000 0 0 0x81000000 0x7 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 64>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 11>; + status = "disabled"; + }; + + pcie@8,0 { + device_type = "pci"; + assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; + reg = <0x4000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 + 0x81000000 0 0 0x81000000 0x8 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 65>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 12>; + status = "disabled"; + }; + + pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + }; + + pcie@10,0 { + device_type = "pci"; + assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; + reg = <0x5000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 + 0x81000000 0 0 0x81000000 0xa 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 103>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 27>; + status = "disabled"; + }; + }; + + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; + }; + + gpio2: gpio@18180 { + compatible = "marvell,orion-gpio"; + reg = <0x18180 0x40>; + ngpios = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <91>; + }; + + eth3: ethernet@34000 { + compatible = "marvell,armada-xp-neta"; + reg = <0x34000 0x4000>; + interrupts = <14>; + clocks = <&gateclk 1>; + status = "disabled"; + }; + }; + }; +}; + +&pinctrl { + compatible = "marvell,mv78460-pinctrl"; +}; diff --git a/arch/arm/dts/armada-xp.dtsi b/arch/arm/dts/armada-xp.dtsi new file mode 100644 index 0000000..3de9b76 --- /dev/null +++ b/arch/arm/dts/armada-xp.dtsi @@ -0,0 +1,320 @@ +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem <alior@marvell.com> + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * Ben Dooks <ben.dooks@codethink.co.uk> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Contains definitions specific to the Armada XP SoC that are not + * common to all Armada SoCs. + */ + +#include "armada-370-xp.dtsi" + +/ { + model = "Marvell Armada XP family SoC"; + compatible = "marvell,armadaxp", "marvell,armada-370-xp"; + + aliases { + serial2 = &uart2; + serial3 = &uart3; + }; + + soc { + compatible = "marvell,armadaxp-mbus", "simple-bus"; + + bootrom { + compatible = "marvell,bootrom"; + reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; + }; + + internal-regs { + sdramc@1400 { + compatible = "marvell,armada-xp-sdram-controller"; + reg = <0x1400 0x500>; + }; + + L2: l2-cache { + compatible = "marvell,aurora-system-cache"; + reg = <0x08000 0x1000>; + cache-id-part = <0x100>; + cache-level = <2>; + cache-unified; + wt-override; + }; + + spi0: spi@10600 { + compatible = "marvell,armada-xp-spi", + "marvell,orion-spi"; + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + }; + + spi1: spi@10680 { + compatible = "marvell,armada-xp-spi", + "marvell,orion-spi"; + }; + + + i2c0: i2c@11000 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11100 0x100>; + }; + + uart2: serial@12200 { + compatible = "snps,dw-apb-uart"; + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + reg = <0x12200 0x100>; + reg-shift = <2>; + interrupts = <43>; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + uart3: serial@12300 { + compatible = "snps,dw-apb-uart"; + pinctrl-0 = <&uart3_pins>; + pinctrl-names = "default"; + reg = <0x12300 0x100>; + reg-shift = <2>; + interrupts = <44>; + reg-io-width = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x500>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-xp-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + coreclk: mvebu-sar@18230 { + compatible = "marvell,armada-xp-core-clock"; + reg = <0x18230 0x08>; + #clock-cells = <1>; + }; + + thermal@182b0 { + compatible = "marvell,armadaxp-thermal"; + reg = <0x182b0 0x4 + 0x184d0 0x4>; + status = "okay"; + }; + + cpuclk: clock-complex@18700 { + #clock-cells = <1>; + compatible = "marvell,armada-xp-cpu-clock"; + reg = <0x18700 0x24>, <0x1c054 0x10>; + clocks = <&coreclk 1>; + }; + + interrupt-controller@20a00 { + reg = <0x20a00 0x2d0>, <0x21070 0x58>; + }; + + timer@20300 { + compatible = "marvell,armada-xp-timer"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + + watchdog@20300 { + compatible = "marvell,armada-xp-wdt"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + + cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x20>; + }; + + eth2: ethernet@30000 { + compatible = "marvell,armada-xp-neta"; + reg = <0x30000 0x4000>; + interrupts = <12>; + clocks = <&gateclk 2>; + status = "disabled"; + }; + + usb@50000 { + clocks = <&gateclk 18>; + }; + + usb@51000 { + clocks = <&gateclk 19>; + }; + + usb@52000 { + compatible = "marvell,orion-ehci"; + reg = <0x52000 0x500>; + interrupts = <47>; + clocks = <&gateclk 20>; + status = "disabled"; + }; + + xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor10 { + interrupts = <51>; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = <52>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + ethernet@70000 { + compatible = "marvell,armada-xp-neta"; + }; + + ethernet@74000 { + compatible = "marvell,armada-xp-neta"; + }; + + xor@f0900 { + compatible = "marvell,orion-xor"; + reg = <0xF0900 0x100 + 0xF0B00 0x100>; + clocks = <&gateclk 28>; + status = "okay"; + + xor00 { + interrupts = <94>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <95>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + }; + }; + + clocks { + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; +}; + +&pinctrl { + ge0_gmii_pins: ge0-gmii-pins { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", "mpp11", + "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19", + "mpp20", "mpp21", "mpp22", "mpp23"; + marvell,function = "ge0"; + }; + + ge0_rgmii_pins: ge0-rgmii-pins { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", "mpp11"; + marvell,function = "ge0"; + }; + + ge1_rgmii_pins: ge1-rgmii-pins { + marvell,pins = + "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19", + "mpp20", "mpp21", "mpp22", "mpp23"; + marvell,function = "ge1"; + }; + + sdio_pins: sdio-pins { + marvell,pins = "mpp30", "mpp31", "mpp32", + "mpp33", "mpp34", "mpp35"; + marvell,function = "sd0"; + }; + + spi0_pins: spi0-pins { + marvell,pins = "mpp36", "mpp37", + "mpp38", "mpp39"; + marvell,function = "spi0"; + }; + + uart2_pins: uart2-pins { + marvell,pins = "mpp42", "mpp43"; + marvell,function = "uart2"; + }; + + uart3_pins: uart3-pins { + marvell,pins = "mpp44", "mpp45"; + marvell,function = "uart3"; + }; +}; diff --git a/arch/arm/dts/axp209.dtsi b/arch/arm/dts/axp209.dtsi index 24c935c..051ab3b 100644 --- a/arch/arm/dts/axp209.dtsi +++ b/arch/arm/dts/axp209.dtsi @@ -89,4 +89,9 @@ regulator-name = "ldo5"; }; }; + + usb_power_supply: usb_power_supply { + compatible = "x-powers,axp202-usb-power-supply"; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts new file mode 100644 index 0000000..096f68b --- /dev/null +++ b/arch/arm/dts/dra7-evm.dts @@ -0,0 +1,693 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra74x.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "TI DRA742"; + compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x60000000>; /* 1536 MB */ + }; + + mmc2_3v3: fixedregulator-mmc2 { + compatible = "regulator-fixed"; + regulator-name = "mmc2_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; + }; + + extcon_usb2: extcon_usb2 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; + }; + + vtt_fixed: fixedregulator-vtt { + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; + }; +}; + +&dra7_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&vtt_pin>; + + vtt_pin: pinmux_vtt_pin { + pinctrl-single,pins = < + 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */ + 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + >; + }; + + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */ + 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */ + >; + }; + + mcspi1_pins: pinmux_mcspi1_pins { + pinctrl-single,pins = < + 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */ + 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */ + 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */ + 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */ + 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */ + 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */ + >; + }; + + mcspi2_pins: pinmux_mcspi2_pins { + pinctrl-single,pins = < + 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */ + 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ + 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ + 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ + 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ + 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ + 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */ + 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */ + 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ + 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ + 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ + >; + }; + + qspi1_pins: pinmux_qspi1_pins { + pinctrl-single,pins = < + 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */ + 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */ + 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ + 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ + 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ + 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ + 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ + 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ + 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ + 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ + >; + }; + + usb1_pins: pinmux_usb1_pins { + pinctrl-single,pins = < + 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ + >; + }; + + usb2_pins: pinmux_usb2_pins { + pinctrl-single,pins = < + 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ + >; + }; + + nand_flash_x16: nand_flash_x16 { + /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch + * So NAND flash requires following switch settings: + * SW5.9 (GPMC_WPN) = LOW + * SW5.1 (NAND_BOOTn) = HIGH */ + pinctrl-single,pins = < + 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ + 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ + 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ + 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ + 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ + 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ + 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ + 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ + 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ + 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ + 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ + 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ + 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ + 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ + 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ + 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ + 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ + 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ + 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ + 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ + 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ + 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ + 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ + 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ + 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ + 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ + 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ + 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ + 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ + 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ + 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ + 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ + 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ + + /* Slave 2 */ + 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ + 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ + 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ + 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ + 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ + 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ + 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ + 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ + 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ + 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ + 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ + 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ + >; + + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 */ + 0x250 (MUX_MODE15) + 0x254 (MUX_MODE15) + 0x258 (MUX_MODE15) + 0x25c (MUX_MODE15) + 0x260 (MUX_MODE15) + 0x264 (MUX_MODE15) + 0x268 (MUX_MODE15) + 0x26c (MUX_MODE15) + 0x270 (MUX_MODE15) + 0x274 (MUX_MODE15) + 0x278 (MUX_MODE15) + 0x27c (MUX_MODE15) + + /* Slave 2 */ + 0x198 (MUX_MODE15) + 0x19c (MUX_MODE15) + 0x1a0 (MUX_MODE15) + 0x1a4 (MUX_MODE15) + 0x1a8 (MUX_MODE15) + 0x1ac (MUX_MODE15) + 0x1b0 (MUX_MODE15) + 0x1b4 (MUX_MODE15) + 0x1b8 (MUX_MODE15) + 0x1bc (MUX_MODE15) + 0x1c0 (MUX_MODE15) + 0x1c4 (MUX_MODE15) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ + 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + 0x23c (MUX_MODE15) + 0x240 (MUX_MODE15) + >; + }; + + dcan1_pins_default: dcan1_pins_default { + pinctrl-single,pins = < + 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ + 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ + >; + }; + + dcan1_pins_sleep: dcan1_pins_sleep { + pinctrl-single,pins = < + 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ + 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ + >; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + regulators { + smps123_reg: smps123 { + /* VDD_MPU */ + regulator-name = "smps123"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_DSPEVE */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_GPU - over VDD_SMPS6 */ + regulator-name = "smps6"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps7_reg: smps7 { + /* CORE_VDD */ + regulator-name = "smps7"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1060000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8_reg: smps8 { + /* VDD_IVAHD */ + regulator-name = "smps8"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps9_reg: smps9 { + /* VDDS1V8 */ + regulator-name = "smps9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: ldo1 { + /* LDO1_OUT --> SDIO */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + ldo2_reg: ldo2 { + /* VDD_RTCIO */ + /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; + }; + }; + + pcf_gpio_21: gpio@21 { + compatible = "ti,pcf8575"; + reg = <0x21>; + lines-initial-states = <0x1408>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio6>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; +}; + +&mcspi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; +}; + +&mcspi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcspi2_pins>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3e0>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&ldo1_reg>; + bus-width = <4>; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&mmc2_3v3>; + bus-width = <8>; +}; + +&cpu0 { + cpu0-supply = <&smps123_reg>; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi1_pins>; + + spi-max-frequency = <48000000>; + m25p80@0 { + compatible = "s25fl256s1"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-cpol; + spi-cpha; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first four physical blocks + * for a valid file to boot and the flash here is + * 64KiB block size. + */ + partition@0 { + label = "QSPI.SPL"; + reg = <0x00000000 0x000010000>; + }; + partition@1 { + label = "QSPI.SPL.backup1"; + reg = <0x00010000 0x00010000>; + }; + partition@2 { + label = "QSPI.SPL.backup2"; + reg = <0x00020000 0x00010000>; + }; + partition@3 { + label = "QSPI.SPL.backup3"; + reg = <0x00030000 0x00010000>; + }; + partition@4 { + label = "QSPI.u-boot"; + reg = <0x00040000 0x00100000>; + }; + partition@5 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00140000 0x00080000>; + }; + partition@6 { + label = "QSPI.u-boot-env"; + reg = <0x001c0000 0x00010000>; + }; + partition@7 { + label = "QSPI.u-boot-env.backup1"; + reg = <0x001d0000 0x0010000>; + }; + partition@8 { + label = "QSPI.kernel"; + reg = <0x001e0000 0x0800000>; + }; + partition@9 { + label = "QSPI.file-system"; + reg = <0x009e0000 0x01620000>; + }; + }; +}; + +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&usb1 { + dr_mode = "peripheral"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; +}; + +&usb2 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_pins>; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_flash_x16>; + ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ + nand@0,0 { + reg = <0 0 4>; /* device IO registers */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <80>; + gpmc,cs-wr-off-ns = <80>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <60>; + gpmc,adv-wr-off-ns = <60>; + gpmc,we-on-ns = <10>; + gpmc,we-off-ns = <50>; + gpmc,oe-on-ns = <4>; + gpmc,oe-off-ns = <40>; + gpmc,access-ns = <40>; + gpmc,wr-access-ns = <80>; + gpmc,rd-cycle-ns = <80>; + gpmc,wr-cycle-ns = <80>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x000020000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00020000 0x00020000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00040000 0x00020000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x00060000 0x00020000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00080000 0x00040000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x000c0000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x001c0000 0x00020000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x001e0000 0x00020000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00200000 0x00800000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x0f600000>; + }; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&gpio7 { + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&mac { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <2>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <3>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; +}; + +&dcan1 { + status = "ok"; + pinctrl-names = "default", "sleep", "active"; + pinctrl-0 = <&dcan1_pins_sleep>; + pinctrl-1 = <&dcan1_pins_sleep>; + pinctrl-2 = <&dcan1_pins_default>; +}; diff --git a/arch/arm/dts/dra74x.dtsi b/arch/arm/dts/dra74x.dtsi new file mode 100644 index 0000000..fa995d0 --- /dev/null +++ b/arch/arm/dts/dra74x.dtsi @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * Based on "omap4.dtsi" + */ + +#include "dra7.dtsi" + +/ { + compatible = "ti,dra742", "ti,dra74", "ti,dra7"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + + operating-points = < + /* kHz uV */ + 1000000 1060000 + 1176000 1160000 + >; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + + /* cooling options */ + cooling-min-level = <0>; + cooling-max-level = <2>; + #cooling-cells = <2>; /* min followed by max */ + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&wakeupgen>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + }; + + ocp { + omap_dwc3_4: omap_dwc3_4@48940000 { + compatible = "ti,dwc3"; + ti,hwmods = "usb_otg_ss4"; + reg = <0x48940000 0x10000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + status = "disabled"; + usb4: usb@48950000 { + compatible = "snps,dwc3"; + reg = <0x48950000 0x17000>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + }; +}; + +&dss { + reg = <0x58000000 0x80>, + <0x58004054 0x4>, + <0x58004300 0x20>, + <0x58005054 0x4>, + <0x58005300 0x20>; + reg-names = "dss", "pll1_clkctrl", "pll1", + "pll2_clkctrl", "pll2"; + + clocks = <&dss_dss_clk>, + <&dss_video1_clk>, + <&dss_video2_clk>; + clock-names = "fck", "video1_clk", "video2_clk"; +}; diff --git a/arch/arm/dts/k2e-clocks.dtsi b/arch/arm/dts/k2e-clocks.dtsi new file mode 100644 index 0000000..d56d68f --- /dev/null +++ b/arch/arm/dts/k2e-clocks.dtsi @@ -0,0 +1,77 @@ +/* + * Copyright 2014 Texas Instruments, Inc. + * + * Keystone 2 Edison SoC specific device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +clocks { + mainpllclk: mainpllclk@2310110 { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; + reg-names = "control", "multiplier", "post-divider"; + }; + + papllclk: papllclk@2620358 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkpass>; + clock-output-names = "papllclk"; + reg = <0x02620358 4>; + reg-names = "control"; + }; + + ddr3apllclk: ddr3apllclk@2620360 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkddr3a>; + clock-output-names = "ddr-3a-pll-clk"; + reg = <0x02620360 4>; + reg-names = "control"; + }; + + clkusb1: clkusb1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk16>; + clock-output-names = "usb1"; + reg = <0x02350004 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkhyperlink0: clkhyperlink0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "hyperlink-0"; + reg = <0x02350030 0xb00>, <0x02350014 0x400>; + reg-names = "control", "domain"; + domain-id = <5>; + }; + + clkpcie1: clkpcie1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "pcie1"; + reg = <0x0235006c 0xb00>, <0x02350048 0x400>; + reg-names = "control", "domain"; + domain-id = <18>; + }; + + clkxge: clkxge { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "xge"; + reg = <0x023500c8 0xb00>, <0x02350074 0x400>; + reg-names = "control", "domain"; + domain-id = <29>; + }; +}; diff --git a/arch/arm/dts/k2e-evm.dts b/arch/arm/dts/k2e-evm.dts new file mode 100644 index 0000000..50c83c2 --- /dev/null +++ b/arch/arm/dts/k2e-evm.dts @@ -0,0 +1,154 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 Edison EVM device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "keystone.dtsi" +#include "k2e.dtsi" + +/ { + compatible = "ti,k2e-evm","ti,keystone"; + model = "Texas Instruments Keystone 2 Edison EVM"; + + soc { + + clocks { + refclksys: refclksys { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-sys"; + }; + + refclkpass: refclkpass { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-pass"; + }; + + refclkddr3a: refclkddr3a { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-ddr3a"; + }; + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&i2c0 { + dtt@50 { + compatible = "at,24c1024"; + reg = <0x50>; + }; +}; + +&aemif { + cs0 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <0>; + /* all timings in nanoseconds */ + ti,cs-min-turnaround-ns = <12>; + ti,cs-read-hold-ns = <6>; + ti,cs-read-strobe-ns = <23>; + ti,cs-read-setup-ns = <9>; + ti,cs-write-hold-ns = <8>; + ti,cs-write-strobe-ns = <23>; + ti,cs-write-setup-ns = <8>; + + nand@0,0 { + compatible = "ti,keystone-nand","ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x4000000 + 1 0 0x0000100>; + + ti,davinci-chipselect = <0>; + ti,davinci-mask-ale = <0x2000>; + ti,davinci-mask-cle = <0x4000>; + ti,davinci-mask-chipsel = <0>; + nand-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "params"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "ubifs"; + reg = <0x180000 0x1FE80000>; + }; + }; + }; +}; + +&spi0 { + nor_flash: n25q128a11@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "Micron,n25q128a11"; + spi-max-frequency = <54000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x80000 0xf80000>; + }; + }; +}; + +&mdio { + status = "ok"; + ethphy0: ethernet-phy@0 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm/dts/k2e-netcp.dtsi b/arch/arm/dts/k2e-netcp.dtsi new file mode 100644 index 0000000..b13b3c9 --- /dev/null +++ b/arch/arm/dts/k2e-netcp.dtsi @@ -0,0 +1,206 @@ +/* + * Device Tree Source for Keystone 2 Edison Netcp driver + * + * Copyright 2015 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +qmss: qmss@2a40000 { + compatible = "ti,keystone-navigator-qmss"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&chipclk13>; + ranges; + queue-range = <0 0x2000>; + linkram0 = <0x100000 0x4000>; + linkram1 = <0 0x10000>; + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x2000>; + reg = <0x2a40000 0x20000>, + <0x2a06000 0x400>, + <0x2a02000 0x1000>, + <0x2a03000 0x1000>, + <0x23a80000 0x20000>, + <0x2a80000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + }; + queue-pools { + qpend { + qpend-0 { + qrange = <658 8>; + interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 + 0 43 0xf04 0 44 0xf04 0 45 0xf04 + 0 46 0xf04 0 47 0xf04>; + }; + qpend-1 { + qrange = <528 16>; + interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 + 0 51 0xf04 0 52 0xf04 0 53 0xf04 + 0 54 0xf04 0 55 0xf04 0 56 0xf04 + 0 57 0xf04 0 58 0xf04 0 59 0xf04 + 0 60 0xf04 0 61 0xf04 0 62 0xf04 + 0 63 0xf04>; + qalloc-by-id; + }; + qpend-2 { + qrange = <544 16>; + interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 + 0 59 0xf04 0 68 0xf04 0 69 0xf04 + 0 70 0xf04 0 71 0xf04 0 72 0xf04 + 0 73 0xf04 0 74 0xf04 0 75 0xf04 + 0 76 0xf04 0 77 0xf04 0 78 0xf04 + 0 79 0xf04>; + }; + }; + general-purpose { + gp-0 { + qrange = <4000 64>; + }; + netcp-tx { + qrange = <896 128>; + qalloc-by-id; + }; + }; + }; + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <8192 128>; /* num_desc desc_size */ + link-index = <0x4000>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + clocks = <&papllclk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,navigator-cloud-address = <0x23a80000 0x23a90000 + 0x23a80000 0x23a90000>; + + dma_gbe: dma_gbe@0 { + reg = <0x24186000 0x100>, + <0x24187000 0x2a0>, + <0x24188000 0xb60>, + <0x24186100 0x80>, + <0x24189000 0x1000>; + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; +}; + +netcp: netcp@24000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + + /* NetCP address range */ + ranges = <0 0x24000000 0x1000000>; + + clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 0>, + <&dma_gbe 8>, + <&dma_gbe 0>; + ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe@200000 { /* ETHSS */ + label = "netcp-gbe"; + compatible = "ti,netcp-gbe-9"; + reg = <0x200000 0x900>, <0x220000 0x20000>; + /* enable-ale; */ + tx-queue = <896>; + tx-channel = "nettx"; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <1>; + phy-handle = <ðphy0>; + }; + gbe1: interface-1 { + slave-port = <1>; + link-interface = <1>; + phy-handle = <ðphy1>; + }; + }; + + secondary-slave-ports { + port-2 { + slave-port = <2>; + link-interface = <2>; + }; + port-3 { + slave-port = <3>; + link-interface = <2>; + }; + port-4 { + slave-port = <4>; + link-interface = <2>; + }; + port-5 { + slave-port = <5>; + link-interface = <2>; + }; + port-6 { + slave-port = <6>; + link-interface = <2>; + }; + port-7 { + slave-port = <7>; + link-interface = <2>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <528>; + tx-completion-queue = <530>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + + }; + interface-1 { + rx-channel = "netrx1"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <529>; + tx-completion-queue = <531>; + efuse-mac = <0>; + local-mac-address = [02 18 31 7e 3e 00]; + netcp-gbe = <&gbe1>; + }; + }; +}; diff --git a/arch/arm/dts/k2e.dtsi b/arch/arm/dts/k2e.dtsi new file mode 100644 index 0000000..675fb8e --- /dev/null +++ b/arch/arm/dts/k2e.dtsi @@ -0,0 +1,147 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 Edison soc device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; + }; + + soc { + /include/ "k2e-clocks.dtsi" + + usb: usb@2680000 { + interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; + dwc3@2690000 { + interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; + }; + }; + + usb1_phy: usb_phy@2620750 { + compatible = "ti,keystone-usbphy"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2620750 24>; + status = "disabled"; + }; + + usb1: usb@25000000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x25000000 0x10000>; + clocks = <&clkusb1>; + clock-names = "usb"; + interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + + dwc3@25010000 { + compatible = "synopsys,dwc3"; + reg = <0x25010000 0x70000>; + interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>; + usb-phy = <&usb1_phy>, <&usb1_phy>; + }; + }; + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + pcie1: pcie@21020000 { + compatible = "ti,keystone-pcie","snps,dw-pcie"; + clocks = <&clkpcie1>; + clock-names = "pcie"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; + ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000 + 0x82000000 0 0x60000000 0x60000000 0 0x10000000>; + + status = "disabled"; + device_type = "pci"; + num-lanes = <2>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ + <0 0 0 2 &pcie_intc1 1>, /* INT B */ + <0 0 0 3 &pcie_intc1 2>, /* INT C */ + <0 0 0 4 &pcie_intc1 3>; /* INT D */ + + pcie_msi_intc1: msi-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>; + }; + + pcie_intc1: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>; + }; + }; + + mdio: mdio@24200f00 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x24200f00 0x100>; + status = "disabled"; + clocks = <&clkcpgmac>; + clock-names = "fck"; + bus_freq = <2500000>; + }; + /include/ "k2e-netcp.dtsi" + }; +}; diff --git a/arch/arm/dts/k2g-evm.dts b/arch/arm/dts/k2g-evm.dts new file mode 100644 index 0000000..de50e8f --- /dev/null +++ b/arch/arm/dts/k2g-evm.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2014 Texas Instruments, Inc. + * + * Keystone 2 Galileo EVM device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "k2g.dtsi" + +/ { + compatible = "ti,k2g-evm","ti,keystone"; + model = "Texas Instruments Keystone 2 Galileo EVM"; + + chosen { + stdout-path = &uart0; + }; +}; diff --git a/arch/arm/dts/k2g.dtsi b/arch/arm/dts/k2g.dtsi new file mode 100644 index 0000000..6b79b16 --- /dev/null +++ b/arch/arm/dts/k2g.dtsi @@ -0,0 +1,72 @@ +/* + * Copyright 2014 Texas Instruments, Inc. + * + * Keystone 2 Galileo soc device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "skeleton.dtsi" + +/ { + model = "Texas Instruments Keystone 2 SoC"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + }; + + gic: interrupt-controller { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x02561000 0x0 0x1000>, + <0x0 0x02562000 0x0 0x2000>, + <0x0 0x02564000 0x0 0x1000>, + <0x0 0x02566000 0x0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ti,keystone","simple-bus"; + interrupt-parent = <&gic>; + ranges; + + uart0: serial@02530c00 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02530c00 0x100>; + clock-names = "uart"; + interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>; + }; + + }; +}; diff --git a/arch/arm/dts/k2hk-clocks.dtsi b/arch/arm/dts/k2hk-clocks.dtsi new file mode 100644 index 0000000..af9b719 --- /dev/null +++ b/arch/arm/dts/k2hk-clocks.dtsi @@ -0,0 +1,425 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 Kepler/Hawking SoC clock nodes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +clocks { + armpllclk: armpllclk@2620370 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkarm>; + clock-output-names = "arm-pll-clk"; + reg = <0x02620370 4>; + reg-names = "control"; + }; + + mainpllclk: mainpllclk@2310110 { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; + reg-names = "control", "multiplier", "post-divider"; + }; + + papllclk: papllclk@2620358 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkpass>; + clock-output-names = "papllclk"; + reg = <0x02620358 4>; + reg-names = "control"; + }; + + ddr3apllclk: ddr3apllclk@2620360 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkddr3a>; + clock-output-names = "ddr-3a-pll-clk"; + reg = <0x02620360 4>; + reg-names = "control"; + }; + + ddr3bpllclk: ddr3bpllclk@2620368 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkddr3b>; + clock-output-names = "ddr-3b-pll-clk"; + reg = <0x02620368 4>; + reg-names = "control"; + }; + + clktsip: clktsip { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk16>; + clock-output-names = "tsip"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clksrio: clksrio { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1rstiso13>; + clock-output-names = "srio"; + reg = <0x0235002c 0xb00>, <0x02350010 0x400>; + reg-names = "control", "domain"; + domain-id = <4>; + }; + + clkhyperlink0: clkhyperlink0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "hyperlink-0"; + reg = <0x02350030 0xb00>, <0x02350014 0x400>; + reg-names = "control", "domain"; + domain-id = <5>; + }; + + clkgem1: clkgem1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem1"; + reg = <0x02350040 0xb00>, <0x02350024 0x400>; + reg-names = "control", "domain"; + domain-id = <9>; + }; + + clkgem2: clkgem2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem2"; + reg = <0x02350044 0xb00>, <0x02350028 0x400>; + reg-names = "control", "domain"; + domain-id = <10>; + }; + + clkgem3: clkgem3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem3"; + reg = <0x02350048 0xb00>, <0x0235002c 0x400>; + reg-names = "control", "domain"; + domain-id = <11>; + }; + + clkgem4: clkgem4 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem4"; + reg = <0x0235004c 0xb00>, <0x02350030 0x400>; + reg-names = "control", "domain"; + domain-id = <12>; + }; + + clkgem5: clkgem5 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem5"; + reg = <0x02350050 0xb00>, <0x02350034 0x400>; + reg-names = "control", "domain"; + domain-id = <13>; + }; + + clkgem6: clkgem6 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem6"; + reg = <0x02350054 0xb00>, <0x02350038 0x400>; + reg-names = "control", "domain"; + domain-id = <14>; + }; + + clkgem7: clkgem7 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem7"; + reg = <0x02350058 0xb00>, <0x0235003c 0x400>; + reg-names = "control", "domain"; + domain-id = <15>; + }; + + clkddr31: clkddr31 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "ddr3-1"; + reg = <0x02350060 0xb00>, <0x02350040 0x400>; + reg-names = "control", "domain"; + domain-id = <16>; + }; + + clktac: clktac { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tac"; + reg = <0x02350064 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkrac01: clkrac01 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "rac-01"; + reg = <0x02350068 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkrac23: clkrac23 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "rac-23"; + reg = <0x0235006c 0xb00>, <0x02350048 0x400>; + reg-names = "control", "domain"; + domain-id = <18>; + }; + + clkfftc0: clkfftc0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-0"; + reg = <0x02350070 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <19>; + }; + + clkfftc1: clkfftc1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-1"; + reg = <0x02350074 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <19>; + }; + + clkfftc2: clkfftc2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-2"; + reg = <0x02350078 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkfftc3: clkfftc3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-3"; + reg = <0x0235007c 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkfftc4: clkfftc4 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-4"; + reg = <0x02350080 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkfftc5: clkfftc5 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-5"; + reg = <0x02350084 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkaif: clkaif { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "aif"; + reg = <0x02350088 0xb00>, <0x02350054 0x400>; + reg-names = "control", "domain"; + domain-id = <21>; + }; + + clktcp3d0: clktcp3d0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-0"; + reg = <0x0235008c 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <22>; + }; + + clktcp3d1: clktcp3d1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-1"; + reg = <0x02350090 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <22>; + }; + + clktcp3d2: clktcp3d2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-2"; + reg = <0x02350094 0xb00>, <0x0235005c 0x400>; + reg-names = "control", "domain"; + domain-id = <23>; + }; + + clktcp3d3: clktcp3d3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-3"; + reg = <0x02350098 0xb00>, <0x0235005c 0x400>; + reg-names = "control", "domain"; + domain-id = <23>; + }; + + clkvcp0: clkvcp0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-0"; + reg = <0x0235009c 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp1: clkvcp1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-1"; + reg = <0x023500a0 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp2: clkvcp2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-2"; + reg = <0x023500a4 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp3: clkvcp3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-3"; + reg = <0x023500a8 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp4: clkvcp4 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-4"; + reg = <0x023500ac 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkvcp5: clkvcp5 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-5"; + reg = <0x023500b0 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkvcp6: clkvcp6 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-6"; + reg = <0x023500b4 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkvcp7: clkvcp7 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-7"; + reg = <0x023500b8 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkbcp: clkbcp { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "bcp"; + reg = <0x023500bc 0xb00>, <0x02350068 0x400>; + reg-names = "control", "domain"; + domain-id = <26>; + }; + + clkdxb: clkdxb { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "dxb"; + reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; + reg-names = "control", "domain"; + domain-id = <27>; + }; + + clkhyperlink1: clkhyperlink1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "hyperlink-1"; + reg = <0x023500c4 0xb00>, <0x02350070 0x400>; + reg-names = "control", "domain"; + domain-id = <28>; + }; + + clkxge: clkxge { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "xge"; + reg = <0x023500c8 0xb00>, <0x02350074 0x400>; + reg-names = "control", "domain"; + domain-id = <29>; + }; +}; diff --git a/arch/arm/dts/k2hk-evm.dts b/arch/arm/dts/k2hk-evm.dts new file mode 100644 index 0000000..660ebf5 --- /dev/null +++ b/arch/arm/dts/k2hk-evm.dts @@ -0,0 +1,182 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 Kepler/Hawking EVM device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "keystone.dtsi" +#include "k2hk.dtsi" + +/ { + compatible = "ti,k2hk-evm","ti,keystone"; + model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; + + soc { + clocks { + refclksys: refclksys { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <122880000>; + clock-output-names = "refclk-sys"; + }; + + refclkpass: refclkpass { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <122880000>; + clock-output-names = "refclk-pass"; + }; + + refclkarm: refclkarm { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "refclk-arm"; + }; + + refclkddr3a: refclkddr3a { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-ddr3a"; + }; + + refclkddr3b: refclkddr3b { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-ddr3b"; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + debug1_1 { + label = "keystone:green:debug1"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ + }; + + debug1_2 { + label = "keystone:red:debug1"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ + }; + + debug2 { + label = "keystone:blue:debug2"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ + }; + + debug3 { + label = "keystone:blue:debug3"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&aemif { + cs0 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <0>; + /* all timings in nanoseconds */ + ti,cs-min-turnaround-ns = <12>; + ti,cs-read-hold-ns = <6>; + ti,cs-read-strobe-ns = <23>; + ti,cs-read-setup-ns = <9>; + ti,cs-write-hold-ns = <8>; + ti,cs-write-strobe-ns = <23>; + ti,cs-write-setup-ns = <8>; + + nand@0,0 { + compatible = "ti,keystone-nand","ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x4000000 + 1 0 0x0000100>; + + ti,davinci-chipselect = <0>; + ti,davinci-mask-ale = <0x2000>; + ti,davinci-mask-cle = <0x4000>; + ti,davinci-mask-chipsel = <0>; + nand-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "params"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "ubifs"; + reg = <0x180000 0x1fe80000>; + }; + }; + }; +}; + +&i2c0 { + dtt@50 { + compatible = "at,24c1024"; + reg = <0x50>; + }; +}; + +&spi0 { + nor_flash: n25q128a11@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "Micron,n25q128a11"; + spi-max-frequency = <54000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x80000 0xf80000>; + }; + }; +}; + +&mdio { + status = "ok"; + ethphy0: ethernet-phy@0 { + compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm/dts/k2hk-netcp.dtsi b/arch/arm/dts/k2hk-netcp.dtsi new file mode 100644 index 0000000..77a32c3 --- /dev/null +++ b/arch/arm/dts/k2hk-netcp.dtsi @@ -0,0 +1,208 @@ +/* + * Device Tree Source for Keystone 2 Hawking Netcp driver + * + * Copyright 2015 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +qmss: qmss@2a40000 { + compatible = "ti,keystone-navigator-qmss"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&chipclk13>; + ranges; + queue-range = <0 0x4000>; + linkram0 = <0x100000 0x8000>; + linkram1 = <0x0 0x10000>; + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x2000>; + reg = <0x2a40000 0x20000>, + <0x2a06000 0x400>, + <0x2a02000 0x1000>, + <0x2a03000 0x1000>, + <0x23a80000 0x20000>, + <0x2a80000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + + qmgr1 { + managed-queues = <0x2000 0x2000>; + reg = <0x2a60000 0x20000>, + <0x2a06400 0x400>, + <0x2a04000 0x1000>, + <0x2a05000 0x1000>, + <0x23aa0000 0x20000>, + <0x2aa0000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + }; + queue-pools { + qpend { + qpend-0 { + qrange = <658 8>; + interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 + 0 43 0xf04 0 44 0xf04 0 45 0xf04 + 0 46 0xf04 0 47 0xf04>; + }; + qpend-1 { + qrange = <8704 16>; + interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 + 0 51 0xf04 0 52 0xf04 0 53 0xf04 + 0 54 0xf04 0 55 0xf04 0 56 0xf04 + 0 57 0xf04 0 58 0xf04 0 59 0xf04 + 0 60 0xf04 0 61 0xf04 0 62 0xf04 + 0 63 0xf04>; + qalloc-by-id; + }; + qpend-2 { + qrange = <8720 16>; + interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 + 0 59 0xf04 0 68 0xf04 0 69 0xf04 + 0 70 0xf04 0 71 0xf04 0 72 0xf04 + 0 73 0xf04 0 74 0xf04 0 75 0xf04 + 0 76 0xf04 0 77 0xf04 0 78 0xf04 + 0 79 0xf04>; + }; + }; + general-purpose { + gp-0 { + qrange = <4000 64>; + }; + netcp-tx { + qrange = <640 9>; + qalloc-by-id; + }; + netcpx-tx { + qrange = <8752 8>; + qalloc-by-id; + }; + }; + }; + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <8192 128>; /* num_desc desc_size */ + link-index = <0x4000>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + clocks = <&papllclk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,navigator-cloud-address = <0x23a80000 0x23a90000 + 0x23aa0000 0x23ab0000>; + + dma_gbe: dma_gbe@0 { + reg = <0x2004000 0x100>, + <0x2004400 0x120>, + <0x2004800 0x300>, + <0x2004c00 0x120>, + <0x2005000 0x400>; + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; +}; + +netcp: netcp@2000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + + /* NetCP address range */ + ranges = <0 0x2000000 0x100000>; + + clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 22>, + <&dma_gbe 23>, + <&dma_gbe 8>; + ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; + + netcp-devices { + ranges; + #address-cells = <1>; + #size-cells = <1>; + gbe@90000 { /* ETHSS */ + #address-cells = <1>; + #size-cells = <1>; + label = "netcp-gbe"; + compatible = "ti,netcp-gbe"; + reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>; + /* enable-ale; */ + tx-queue = <648>; + tx-channel = "nettx"; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <1>; + phy-handle = <ðphy0>; + }; + gbe1: interface-1 { + slave-port = <1>; + link-interface = <1>; + phy-handle = <ðphy1>; + }; + }; + + secondary-slave-ports { + port-2 { + slave-port = <2>; + link-interface = <2>; + }; + port-3 { + slave-port = <3>; + link-interface = <2>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <8704>; + tx-completion-queue = <8706>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + + }; + interface-1 { + rx-channel = "netrx1"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <8705>; + tx-completion-queue = <8707>; + efuse-mac = <0>; + local-mac-address = [02 18 31 7e 3e 6f]; + netcp-gbe = <&gbe1>; + }; + }; +}; diff --git a/arch/arm/dts/k2hk.dtsi b/arch/arm/dts/k2hk.dtsi new file mode 100644 index 0000000..d0810a5 --- /dev/null +++ b/arch/arm/dts/k2hk.dtsi @@ -0,0 +1,114 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 Kepler/Hawking soc specific device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; + }; + + soc { + /include/ "k2hk-clocks.dtsi" + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + dspgpio1: keystone_dsp_gpio@2620244 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x244>; + }; + + dspgpio2: keystone_dsp_gpio@2620248 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x248>; + }; + + dspgpio3: keystone_dsp_gpio@262024c { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x24c>; + }; + + dspgpio4: keystone_dsp_gpio@2620250 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x250>; + }; + + dspgpio5: keystone_dsp_gpio@2620254 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x254>; + }; + + dspgpio6: keystone_dsp_gpio@2620258 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x258>; + }; + + dspgpio7: keystone_dsp_gpio@262025c { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x25c>; + }; + + mdio: mdio@02090300 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x02090300 0x100>; + status = "disabled"; + clocks = <&clkcpgmac>; + clock-names = "fck"; + bus_freq = <2500000>; + }; + /include/ "k2hk-netcp.dtsi" + }; +}; diff --git a/arch/arm/dts/k2l-clocks.dtsi b/arch/arm/dts/k2l-clocks.dtsi new file mode 100644 index 0000000..ef8464b --- /dev/null +++ b/arch/arm/dts/k2l-clocks.dtsi @@ -0,0 +1,266 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 lamarr SoC clock nodes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +clocks { + armpllclk: armpllclk@2620370 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclksys>; + clock-output-names = "arm-pll-clk"; + reg = <0x02620370 4>; + reg-names = "control"; + }; + + mainpllclk: mainpllclk@2310110 { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; + reg-names = "control", "multiplier", "post-divider"; + }; + + papllclk: papllclk@2620358 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclksys>; + clock-output-names = "papllclk"; + reg = <0x02620358 4>; + reg-names = "control"; + }; + + ddr3apllclk: ddr3apllclk@2620360 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclksys>; + clock-output-names = "ddr-3a-pll-clk"; + reg = <0x02620360 4>; + reg-names = "control"; + }; + + clkdfeiqnsys: clkdfeiqnsys { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "dfe"; + reg-names = "control", "domain"; + reg = <0x02350004 0xb00>, <0x02350000 0x400>; + domain-id = <0>; + }; + + clkpcie1: clkpcie1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "pcie"; + reg = <0x0235002c 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <4>; + }; + + clkgem1: clkgem1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem1"; + reg = <0x02350040 0xb00>, <0x02350024 0x400>; + reg-names = "control", "domain"; + domain-id = <9>; + }; + + clkgem2: clkgem2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem2"; + reg = <0x02350044 0xb00>, <0x02350028 0x400>; + reg-names = "control", "domain"; + domain-id = <10>; + }; + + clkgem3: clkgem3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem3"; + reg = <0x02350048 0xb00>, <0x0235002c 0x400>; + reg-names = "control", "domain"; + domain-id = <11>; + }; + + clktac: clktac { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tac"; + reg = <0x02350064 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkrac: clkrac { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "rac"; + reg = <0x02350068 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkdfepd0: clkdfepd0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "dfe-pd0"; + reg = <0x0235006c 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <18>; + }; + + clkfftc0: clkfftc0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-0"; + reg = <0x02350070 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <19>; + }; + + clkosr: clkosr { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "osr"; + reg = <0x02350088 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <21>; + }; + + clktcp3d0: clktcp3d0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-0"; + reg = <0x0235008c 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <22>; + }; + + clktcp3d1: clktcp3d1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-1"; + reg = <0x02350094 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <23>; + }; + + clkvcp0: clkvcp0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-0"; + reg = <0x0235009c 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp1: clkvcp1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-1"; + reg = <0x023500a0 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp2: clkvcp2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-2"; + reg = <0x023500a4 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp3: clkvcp3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-3"; + reg = <0x023500a8 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkbcp: clkbcp { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "bcp"; + reg = <0x023500bc 0xb00>, <0x02350068 0x400>; + reg-names = "control", "domain"; + domain-id = <26>; + }; + + clkdfepd1: clkdfepd1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "dfe-pd1"; + reg = <0x023500c0 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <27>; + }; + + clkfftc1: clkfftc1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-1"; + reg = <0x023500c4 0xb00>, <0x023504c0 0x400>; + reg-names = "control", "domain"; + domain-id = <28>; + }; + + clkiqnail: clkiqnail { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "iqn-ail"; + reg = <0x023500c8 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <29>; + }; + + clkuart2: clkuart2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "uart2"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkuart3: clkuart3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "uart3"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; +}; diff --git a/arch/arm/dts/k2l-evm.dts b/arch/arm/dts/k2l-evm.dts new file mode 100644 index 0000000..9a69a6b --- /dev/null +++ b/arch/arm/dts/k2l-evm.dts @@ -0,0 +1,131 @@ +/* + * Copyright 2014 Texas Instruments, Inc. + * + * Keystone 2 Lamarr EVM device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "keystone.dtsi" +#include "k2l.dtsi" + +/ { + compatible = "ti,k2l-evm","ti,keystone"; + model = "Texas Instruments Keystone 2 Lamarr EVM"; + + soc { + clocks { + refclksys: refclksys { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <122880000>; + clock-output-names = "refclk-sys"; + }; + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&i2c0 { + dtt@50 { + compatible = "at,24c1024"; + reg = <0x50>; + }; +}; + +&aemif { + cs0 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <0>; + /* all timings in nanoseconds */ + ti,cs-min-turnaround-ns = <12>; + ti,cs-read-hold-ns = <6>; + ti,cs-read-strobe-ns = <23>; + ti,cs-read-setup-ns = <9>; + ti,cs-write-hold-ns = <8>; + ti,cs-write-strobe-ns = <23>; + ti,cs-write-setup-ns = <8>; + + nand@0,0 { + compatible = "ti,keystone-nand","ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x4000000 + 1 0 0x0000100>; + + ti,davinci-chipselect = <0>; + ti,davinci-mask-ale = <0x2000>; + ti,davinci-mask-cle = <0x4000>; + ti,davinci-mask-chipsel = <0>; + nand-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "params"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "ubifs"; + reg = <0x180000 0x7FE80000>; + }; + }; + }; +}; + +&spi0 { + nor_flash: n25q128a11@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "Micron,n25q128a11"; + spi-max-frequency = <54000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x80000 0xf80000>; + }; + }; +}; + +&mdio { + status = "ok"; + ethphy0: ethernet-phy@0 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm/dts/k2l-netcp.dtsi b/arch/arm/dts/k2l-netcp.dtsi new file mode 100644 index 0000000..6b95284 --- /dev/null +++ b/arch/arm/dts/k2l-netcp.dtsi @@ -0,0 +1,189 @@ +/* + * Device Tree Source for Keystone 2 Lamarr Netcp driver + * + * Copyright 2015 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +qmss: qmss@2a40000 { + compatible = "ti,keystone-navigator-qmss"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&chipclk13>; + ranges; + queue-range = <0 0x2000>; + linkram0 = <0x100000 0x4000>; + linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x2000>; + reg = <0x2a40000 0x20000>, + <0x2a06000 0x400>, + <0x2a02000 0x1000>, + <0x2a03000 0x1000>, + <0x23a80000 0x20000>, + <0x2a80000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + }; + queue-pools { + qpend { + qpend-0 { + qrange = <658 8>; + interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 + 0 43 0xf04 0 44 0xf04 0 45 0xf04 + 0 46 0xf04 0 47 0xf04>; + }; + qpend-1 { + qrange = <528 16>; + interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 + 0 51 0xf04 0 52 0xf04 0 53 0xf04 + 0 54 0xf04 0 55 0xf04 0 56 0xf04 + 0 57 0xf04 0 58 0xf04 0 59 0xf04 + 0 60 0xf04 0 61 0xf04 0 62 0xf04 + 0 63 0xf04>; + qalloc-by-id; + }; + qpend-2 { + qrange = <544 16>; + interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 + 0 59 0xf04 0 68 0xf04 0 69 0xf04 + 0 70 0xf04 0 71 0xf04 0 72 0xf04 + 0 73 0xf04 0 74 0xf04 0 75 0xf04 + 0 76 0xf04 0 77 0xf04 0 78 0xf04 + 0 79 0xf04>; + }; + }; + general-purpose { + gp-0 { + qrange = <4000 64>; + }; + netcp-tx { + qrange = <896 128>; + qalloc-by-id; + }; + }; + }; + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <8192 128>; /* num_desc desc_size */ + link-index = <0x4000>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + clocks = <&papllclk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,navigator-cloud-address = <0x23a80000 0x23a90000>; + + dma_gbe: dma_gbe@0 { + reg = <0x26186000 0x100>, + <0x26187000 0x2a0>, + <0x26188000 0xb60>, + <0x26186100 0x80>, + <0x26189000 0x1000>; + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; +}; + +netcp: netcp@26000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + + /* NetCP address range */ + ranges = <0 0x26000000 0x1000000>; + + clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 0>, + <&dma_gbe 8>, + <&dma_gbe 0>; + ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe@200000 { /* ETHSS */ + label = "netcp-gbe"; + compatible = "ti,netcp-gbe-5"; + reg = <0x200000 0x900>, <0x220000 0x20000>; + /* enable-ale; */ + tx-queue = <896>; + tx-channel = "nettx"; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <1>; + phy-handle = <ðphy0>; + }; + gbe1: interface-1 { + slave-port = <1>; + link-interface = <1>; + phy-handle = <ðphy1>; + }; + }; + + secondary-slave-ports { + port-2 { + slave-port = <2>; + link-interface = <2>; + }; + port-3 { + slave-port = <3>; + link-interface = <2>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <528>; + tx-completion-queue = <530>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + + }; + interface-1 { + rx-channel = "netrx1"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <529>; + tx-completion-queue = <531>; + efuse-mac = <0>; + local-mac-address = [02 18 31 7e 3e 7f]; + netcp-gbe = <&gbe1>; + }; + }; +}; diff --git a/arch/arm/dts/k2l.dtsi b/arch/arm/dts/k2l.dtsi new file mode 100644 index 0000000..49fd414 --- /dev/null +++ b/arch/arm/dts/k2l.dtsi @@ -0,0 +1,108 @@ +/* + * Copyright 2014 Texas Instruments, Inc. + * + * Keystone 2 Lamarr SoC specific device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + }; + + soc { + /include/ "k2l-clocks.dtsi" + + uart2: serial@02348400 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02348400 0x100>; + clocks = <&clkuart2>; + interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>; + }; + + uart3: serial@02348800 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02348800 0x100>; + clocks = <&clkuart3>; + interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>; + }; + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + dspgpio1: keystone_dsp_gpio@2620244 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x244>; + }; + + dspgpio2: keystone_dsp_gpio@2620248 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x248>; + }; + + dspgpio3: keystone_dsp_gpio@262024c { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x24c>; + }; + + mdio: mdio@26200f00 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x26200f00 0x100>; + status = "disabled"; + clocks = <&clkcpgmac>; + clock-names = "fck"; + bus_freq = <2500000>; + }; + /include/ "k2l-netcp.dtsi" + }; +}; + +&spi0 { + ti,davinci-spi-num-cs = <5>; +}; + +&spi1 { + ti,davinci-spi-num-cs = <3>; +}; + +&spi2 { + ti,davinci-spi-num-cs = <5>; + /* Pin muxed. Enabled and configured by Bootloader */ + status = "disabled"; +}; diff --git a/arch/arm/dts/keystone-clocks.dtsi b/arch/arm/dts/keystone-clocks.dtsi new file mode 100644 index 0000000..0c334b2 --- /dev/null +++ b/arch/arm/dts/keystone-clocks.dtsi @@ -0,0 +1,414 @@ +/* + * Device Tree Source for Keystone 2 clock tree + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mainmuxclk: mainmuxclk@2310108 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-mux-clock"; + clocks = <&mainpllclk>, <&refclksys>; + reg = <0x02310108 4>; + bit-shift = <23>; + bit-mask = <1>; + clock-output-names = "mainmuxclk"; + }; + + chipclk1: chipclk1 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&mainmuxclk>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "chipclk1"; + }; + + chipclk1rstiso: chipclk1rstiso { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&mainmuxclk>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "chipclk1rstiso"; + }; + + gemtraceclk: gemtraceclk@2310120 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-divider-clock"; + clocks = <&mainmuxclk>; + reg = <0x02310120 4>; + bit-shift = <0>; + bit-mask = <8>; + clock-output-names = "gemtraceclk"; + }; + + chipstmxptclk: chipstmxptclk { + #clock-cells = <0>; + compatible = "ti,keystone,pll-divider-clock"; + clocks = <&mainmuxclk>; + reg = <0x02310164 4>; + bit-shift = <0>; + bit-mask = <8>; + clock-output-names = "chipstmxptclk"; + }; + + chipclk12: chipclk12 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "chipclk12"; + }; + + chipclk13: chipclk13 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "chipclk13"; + }; + + paclk13: paclk13 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&papllclk>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "paclk13"; + }; + + chipclk14: chipclk14 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "chipclk14"; + }; + + chipclk16: chipclk16 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "chipclk16"; + }; + + chipclk112: chipclk112 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "chipclk112"; + }; + + chipclk124: chipclk124 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "chipclk114"; + }; + + chipclk1rstiso13: chipclk1rstiso13 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1rstiso>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "chipclk1rstiso13"; + }; + + chipclk1rstiso14: chipclk1rstiso14 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1rstiso>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "chipclk1rstiso14"; + }; + + chipclk1rstiso16: chipclk1rstiso16 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1rstiso>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "chipclk1rstiso16"; + }; + + chipclk1rstiso112: chipclk1rstiso112 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&chipclk1rstiso>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "chipclk1rstiso112"; + }; + + clkmodrst0: clkmodrst0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk16>; + clock-output-names = "modrst0"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + + clkusb: clkusb { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk16>; + clock-output-names = "usb"; + reg = <0x02350008 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkaemifspi: clkaemifspi { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk16>; + clock-output-names = "aemif-spi"; + reg = <0x0235000c 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + + clkdebugsstrc: clkdebugsstrc { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "debugss-trc"; + reg = <0x02350014 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <1>; + }; + + clktetbtrc: clktetbtrc { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tetb-trc"; + reg = <0x02350018 0xb00>, <0x02350004 0x400>; + reg-names = "control", "domain"; + domain-id = <1>; + }; + + clkpa: clkpa { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&paclk13>; + clock-output-names = "pa"; + reg = <0x0235001c 0xb00>, <0x02350008 0x400>; + reg-names = "control", "domain"; + domain-id = <2>; + }; + + clkcpgmac: clkcpgmac { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkpa>; + clock-output-names = "cpgmac"; + reg = <0x02350020 0xb00>, <0x02350008 0x400>; + reg-names = "control", "domain"; + domain-id = <2>; + }; + + clksa: clksa { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkpa>; + clock-output-names = "sa"; + reg = <0x02350024 0xb00>, <0x02350008 0x400>; + reg-names = "control", "domain"; + domain-id = <2>; + }; + + clkpcie: clkpcie { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "pcie"; + reg = <0x02350028 0xb00>, <0x0235000c 0x400>; + reg-names = "control", "domain"; + domain-id = <3>; + }; + + clksr: clksr { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1rstiso112>; + clock-output-names = "sr"; + reg = <0x02350034 0xb00>, <0x02350018 0x400>; + reg-names = "control", "domain"; + domain-id = <6>; + }; + + clkgem0: clkgem0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem0"; + reg = <0x0235003c 0xb00>, <0x02350020 0x400>; + reg-names = "control", "domain"; + domain-id = <8>; + }; + + clkddr30: clkddr30 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "ddr3-0"; + reg = <0x0235005c 0xb00>, <0x02350040 0x400>; + reg-names = "control", "domain"; + domain-id = <16>; + }; + + clkwdtimer0: clkwdtimer0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "timer0"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkwdtimer1: clkwdtimer1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "timer1"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkwdtimer2: clkwdtimer2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "timer2"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkwdtimer3: clkwdtimer3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "timer3"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clktimer15: clktimer15 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "timer15"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkuart0: clkuart0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "uart0"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkuart1: clkuart1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "uart1"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkaemif: clkaemif { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkaemifspi>; + clock-output-names = "aemif"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkusim: clkusim { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "usim"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clki2c: clki2c { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "i2c"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkspi: clkspi { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkaemifspi>; + clock-output-names = "spi"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkgpio: clkgpio { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "gpio"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkkeymgr: clkkeymgr { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "keymgr"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; +}; diff --git a/arch/arm/dts/keystone.dtsi b/arch/arm/dts/keystone.dtsi new file mode 100644 index 0000000..f39b969 --- /dev/null +++ b/arch/arm/dts/keystone.dtsi @@ -0,0 +1,327 @@ +/* + * Copyright 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/gpio/gpio.h> + +#include "skeleton.dtsi" + +/ { + model = "Texas Instruments Keystone 2 SoC"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = &uart0; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + gic: interrupt-controller { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x02561000 0x1000>, + <0x02562000 0x2000>, + <0x02564000 0x1000>, + <0x02566000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = + <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ti,keystone","simple-bus"; + interrupt-parent = <&gic>; + ranges; + + pllctrl: pll-controller@02310000 { + compatible = "ti,keystone-pllctrl", "syscon"; + reg = <0x02310000 0x200>; + }; + + devctrl: device-state-control@02620000 { + compatible = "ti,keystone-devctrl", "syscon"; + reg = <0x02620000 0x1000>; + }; + + rstctrl: reset-controller { + compatible = "ti,keystone-reset"; + ti,syscon-pll = <&pllctrl 0xe4>; + ti,syscon-dev = <&devctrl 0x328>; + ti,wdt-list = <0>; + }; + + /include/ "keystone-clocks.dtsi" + + uart0: serial@02530c00 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02530c00 0x100>; + clocks = <&clkuart0>; + interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; + }; + + uart1: serial@02531000 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02531000 0x100>; + clocks = <&clkuart1>; + interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; + }; + + i2c0: i2c@2530000 { + compatible = "ti,davinci-i2c"; + reg = <0x02530000 0x400>; + clock-frequency = <100000>; + clocks = <&clki2c>; + interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@2530400 { + compatible = "ti,davinci-i2c"; + reg = <0x02530400 0x400>; + clock-frequency = <100000>; + clocks = <&clki2c>; + interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@2530800 { + compatible = "ti,davinci-i2c"; + reg = <0x02530800 0x400>; + clock-frequency = <100000>; + clocks = <&clki2c>; + interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi@21000400 { + compatible = "ti,dm6441-spi"; + reg = <0x21000400 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkspi>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@21000600 { + compatible = "ti,dm6441-spi"; + reg = <0x21000600 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkspi>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi2: spi@21000800 { + compatible = "ti,dm6441-spi"; + reg = <0x21000800 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkspi>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_phy: usb_phy@2620738 { + compatible = "ti,keystone-usbphy"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2620738 24>; + status = "disabled"; + }; + + usb: usb@2680000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2680000 0x10000>; + clocks = <&clkusb>; + clock-names = "usb"; + interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + + dwc3@2690000 { + compatible = "synopsys,dwc3"; + reg = <0x2690000 0x70000>; + interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; + usb-phy = <&usb_phy>, <&usb_phy>; + }; + }; + + wdt: wdt@022f0080 { + compatible = "ti,keystone-wdt","ti,davinci-wdt"; + reg = <0x022f0080 0x80>; + clocks = <&clkwdtimer0>; + }; + + clock_event: timer@22f0000 { + compatible = "ti,keystone-timer"; + reg = <0x022f0000 0x80>; + interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>; + clocks = <&clktimer15>; + }; + + gpio0: gpio@260bf00 { + compatible = "ti,keystone-gpio"; + reg = <0x0260bf00 0x100>; + gpio-controller; + #gpio-cells = <2>; + /* HW Interrupts mapped to GPIO pins */ + interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkgpio>; + clock-names = "gpio"; + ti,ngpio = <32>; + ti,davinci-gpio-unbanked = <32>; + }; + + aemif: aemif@21000A00 { + compatible = "ti,keystone-aemif", "ti,davinci-aemif"; + #address-cells = <2>; + #size-cells = <1>; + clocks = <&clkaemif>; + clock-names = "aemif"; + clock-ranges; + + reg = <0x21000A00 0x00000100>; + ranges = <0 0 0x30000000 0x10000000 + 1 0 0x21000A00 0x00000100>; + }; + + kirq0: keystone_irq@26202a0 { + compatible = "ti,keystone-irq"; + interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <1>; + ti,syscon-dev = <&devctrl 0x2a0>; + }; + + pcie0: pcie@21800000 { + compatible = "ti,keystone-pcie", "snps,dw-pcie"; + clocks = <&clkpcie>; + clock-names = "pcie"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; + ranges = <0x81000000 0 0 0x23250000 0 0x4000 + 0x82000000 0 0x50000000 0x50000000 0 0x10000000>; + + status = "disabled"; + device_type = "pci"; + num-lanes = <2>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */ + <0 0 0 2 &pcie_intc0 1>, /* INT B */ + <0 0 0 3 &pcie_intc0 2>, /* INT C */ + <0 0 0 4 &pcie_intc0 3>; /* INT D */ + + pcie_msi_intc0: msi-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>; + }; + + pcie_intc0: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; + }; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 9650eb0..5465609 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -69,6 +69,9 @@ }; &mmc0 { + status = "okay"; + u-boot,dm-pre-reloc; + cd-gpios = <&portb 18 0>; vmmc-supply = <®ulator_3_3v>; vqmmc-supply = <®ulator_3_3v>; diff --git a/arch/arm/dts/sun5i-a10s.dtsi b/arch/arm/dts/sun5i-a10s.dtsi index 4173e1e..bddd0de 100644 --- a/arch/arm/dts/sun5i-a10s.dtsi +++ b/arch/arm/dts/sun5i-a10s.dtsi @@ -77,6 +77,15 @@ clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; status = "disabled"; }; + + framebuffer@2 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-tve0"; + clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, + <&ahb_gates 44>; + status = "disabled"; + }; }; clocks { @@ -85,6 +94,17 @@ compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <5>, <6>, + <7>, <8>, <9>, + <10>, <13>, + <14>, <17>, <18>, + <20>, <21>, <22>, + <26>, <28>, <32>, + <34>, <36>, <40>, + <43>, <44>, + <46>, <51>, + <52>; clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", @@ -103,6 +123,9 @@ compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; + clock-indices = <0>, <3>, + <5>, <6>, + <10>; clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio", "apb0_ir", "apb0_keypad"; @@ -113,9 +136,14 @@ compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; + clock-indices = <0>, <1>, + <2>, <16>, + <17>, <18>, + <19>; clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_uart0", "apb1_uart1", - "apb1_uart2", "apb1_uart3"; + "apb1_i2c2", "apb1_uart0", + "apb1_uart1", "apb1_uart2", + "apb1_uart3"; }; }; @@ -137,6 +165,14 @@ #size-cells = <0>; }; + pwm: pwm@01c20e00 { + compatible = "allwinner,sun5i-a10s-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; @@ -176,13 +212,6 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - uart3_pins_a: uart3@0 { - allwinner,pins = "PG9", "PG10"; - allwinner,function = "uart3"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - emac_pins_a: emac0@0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", diff --git a/arch/arm/dts/sun5i-a13-forfun-q88db.dts b/arch/arm/dts/sun5i-a13-forfun-q88db.dts deleted file mode 100644 index 24de86c..0000000 --- a/arch/arm/dts/sun5i-a13-forfun-q88db.dts +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * Minimal dts file for the Forfun Q88db for u-boot only - * - * SPDX-License-Identifier: GPL-2.0+ or X11 - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" - -/ { - model = "Forfun Q88db"; - compatible = "forfun,q88db", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-a13-tzx-q8-713b7.dts b/arch/arm/dts/sun5i-a13-tzx-q8-713b7.dts deleted file mode 100644 index 47f630e..0000000 --- a/arch/arm/dts/sun5i-a13-tzx-q8-713b7.dts +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * Minimal dts file for the TZX Q8 713b7 for u-boot only - * - * SPDX-License-Identifier: GPL-2.0+ or X11 - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" - -/ { - model = "TZX Q8 713b7"; - compatible = "tzx,q8-713b7", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-a13.dtsi b/arch/arm/dts/sun5i-a13.dtsi index 976d4fa..d910d3a 100644 --- a/arch/arm/dts/sun5i-a13.dtsi +++ b/arch/arm/dts/sun5i-a13.dtsi @@ -104,6 +104,16 @@ compatible = "allwinner,sun5i-a13-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <5>, <6>, + <7>, <8>, <9>, + <10>, <13>, + <14>, <20>, + <21>, <22>, + <28>, <32>, <36>, + <40>, <44>, + <46>, <51>, + <52>; clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", @@ -121,6 +131,8 @@ compatible = "allwinner,sun5i-a13-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; + clock-indices = <0>, <5>, + <6>; clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; }; @@ -130,8 +142,22 @@ compatible = "allwinner,sun5i-a13-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; + clock-indices = <0>, <1>, + <2>, <17>, + <19>; clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_uart1", "apb1_uart3"; + "apb1_i2c2", "apb1_uart1", + "apb1_uart3"; + }; + }; + + soc@01c00000 { + pwm: pwm@01c20e00 { + compatible = "allwinner,sun5i-a13-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; }; }; }; diff --git a/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/dts/sun5i-r8-chip.dts index 8d9da68..abf3ccb 100644 --- a/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts +++ b/arch/arm/dts/sun5i-r8-chip.dts @@ -1,7 +1,8 @@ /* - * Copyright 2014 Chen-Yu Tsai + * Copyright 2015 Free Electrons + * Copyright 2015 NextThing Co * - * Chen-Yu Tsai <wens@csie.org> + * Maxime Ripard <maxime.ripard@free-electrons.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,19 +44,21 @@ */ /dts-v1/; -#include "sun8i-a23.dtsi" +#include "sun5i-r8.dtsi" #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/interrupt-controller/irq.h> / { - model = "Ippo Q8H Dual Core Tablet (v5)"; - compatible = "ippo,q8h-v5", "allwinner,sun8i-a23"; + model = "NextThing C.H.I.P."; + compatible = "nextthing,chip", "allwinner,sun5i-r8"; aliases { - serial0 = &r_uart; + i2c0 = &i2c0; + i2c2 = &i2c2; + serial0 = &uart1; + serial1 = &uart3; }; chosen { @@ -63,74 +66,149 @@ }; }; -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; +&ehci0 { status = "okay"; }; -&i2c1 { +&i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + + /* + * The interrupt is routed through the "External Fast + * Interrupt Request" pin (ball G13 of the module) + * directly to the main interrupt controller, without + * any other controller interfering. + */ + interrupts = <0>; + }; }; +#include "axp209.dtsi" + &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; - /* pull-ups and devices require PMIC regulator */ - status = "failed"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; status = "okay"; - button@200 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <200000>; - }; + xio: gpio@38 { + compatible = "nxp,pcf8574a"; + reg = <0x38>; + + gpio-controller; + #gpio-cells = <2>; - button@400 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <400000>; + interrupt-parent = <&pio>; + interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; }; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>; - vmmc-supply = <®_vcc3v0>; + pinctrl-0 = <&mmc0_pins_a>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { status = "okay"; }; &pio { - mmc0_cd_pin_q8h: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; + chip_vbus_pin: chip_vbus_pin@0 { + allwinner,pins = "PB10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + chip_id_det_pin: chip_id_det_pin@0 { + allwinner,pins = "PG2"; allwinner,function = "gpio_in"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; }; -&r_uart { +®_dcdc2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "cpuvdd"; + regulator-always-on; +}; + +®_dcdc3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "corevdd"; + regulator-always-on; +}; + +®_ldo1 { + regulator-name = "rtcvdd"; +}; + +®_ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; + regulator-always-on; +}; + +®_ldo5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_usb0_vbus { + pinctrl-0 = <&chip_vbus_pin>; + vin-supply = <®_vcc5v0>; + gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; +}; + +&uart3 { pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; + pinctrl-0 = <&uart3_pins_a>, + <&uart3_pins_cts_rts_a>; status = "okay"; }; &usb_otg { - dr_mode = "host"; + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { status = "okay"; }; &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&chip_id_det_pin>; status = "okay"; + + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_vcc5v0>; }; diff --git a/arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/dts/sun5i-r8.dtsi index 382d64c..0ef8656 100644 --- a/arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts +++ b/arch/arm/dts/sun5i-r8.dtsi @@ -1,5 +1,8 @@ /* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * Copyright 2015 Free Electrons + * Copyright 2015 NextThing Co + * + * Maxime Ripard <maxime.ripard@free-electrons.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -40,15 +43,17 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/* - * The Ippo Q8H v1.2 is almost identical to the v5, still it needs a separate - * dtb file since some gpio-s surrounding the wlan/bluetooth are different, - * and it uses different camera sensors. - */ - -#include "sun8i-a23-ippo-q8h-v5.dts" +#include "sun5i-a13.dtsi" / { - model = "Ippo Q8H Dual Core Tablet (v1.2)"; - compatible = "ippo,q8h-v1.2", "allwinner,sun8i-a23"; + chosen { + framebuffer@1 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-tve0"; + clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, + <&ahb_gates 44>; + status = "disabled"; + }; + }; }; diff --git a/arch/arm/dts/sun5i.dtsi b/arch/arm/dts/sun5i.dtsi index 759117d..9ffee9b 100644 --- a/arch/arm/dts/sun5i.dtsi +++ b/arch/arm/dts/sun5i.dtsi @@ -178,6 +178,7 @@ compatible = "allwinner,sun4i-a10-axi-gates-clk"; reg = <0x01c2005c 0x4>; clocks = <&axi>; + clock-indices = <0>; clock-output-names = "axi_dram"; }; @@ -528,6 +529,27 @@ allwinner,drive = <SUN4I_PINCTRL_30_MA>; allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; + + uart3_pins_a: uart3@0 { + allwinner,pins = "PG9", "PG10"; + allwinner,function = "uart3"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart3_pins_cts_rts_a: uart3-cts-rts@0 { + allwinner,pins = "PG11", "PG12"; + allwinner,function = "uart3"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + pwm0_pins: pwm0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; timer@01c20c00 { diff --git a/arch/arm/dts/sun6i-a31.dtsi b/arch/arm/dts/sun6i-a31.dtsi index 39953e7..44f889f 100644 --- a/arch/arm/dts/sun6i-a31.dtsi +++ b/arch/arm/dts/sun6i-a31.dtsi @@ -659,6 +659,24 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + mmc2_pins_a: mmc2@0 { + allwinner,pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11"; + allwinner,function = "mmc2"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + mmc2_8bit_emmc_pins: mmc2@1 { + allwinner,pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", + "PC13", "PC14", "PC15", + "PC24"; + allwinner,function = "mmc2"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + gmac_pins_mii_a: gmac_mii@0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3", "PA8", "PA9", "PA11", diff --git a/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts b/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts index a438975..db7fa13 100644 --- a/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts +++ b/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts @@ -6,12 +6,12 @@ * licensing only applies to this file, and not this project as a * whole. * - * a) This file is free software; you can redistribute it and/or + * a) This library is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * - * This file is distributed in the hope that it will be useful, + * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. @@ -41,90 +41,151 @@ */ /dts-v1/; -#include "sun8i-a33.dtsi" +#include "sun6i-a31s.dtsi" #include "sunxi-common-regulators.dtsi" - #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { - model = "Ippo Q8H Quad Core Tablet (v1.2)"; - compatible = "ippo,a33-q8h-v1.2", "allwinner,sun8i-a33"; + model = "Sinovoip BPI-M2"; + compatible = "sinovoip,bpi-m2", "allwinner,sun6i-a31s"; aliases { - serial0 = &r_uart; + serial0 = &uart0; }; chosen { stdout-path = "serial0:115200n8"; }; -}; -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_bpi_m2>; + + blue { + label = "bpi-m2:blue:usr"; + gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + }; + + green { + label = "bpi-m2:green:usr"; + gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ + }; + + red { + label = "bpi-m2:red:usr"; + gpios = <&pio 6 5 GPIO_ACTIVE_HIGH>; /* PG5 */ + }; + }; + + mmc2_pwrseq: mmc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pwrseq_pin_bpi_m2>; + reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 WIFI_EN */ + }; }; -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; +&ehci0 { status = "okay"; }; -&lradc { - vref-supply = <®_vcc3v0>; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_bpi_m2>; + phy = <&phy1>; + phy-mode = "rgmii"; + snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */ + snps,reset-active-low; + snps,reset-delays-us = <0 10000 30000>; status = "okay"; - button@200 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <200000>; + phy1: ethernet-phy@1 { + reg = <1>; }; +}; - button@400 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <400000>; - }; +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m2>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */ cd-inverted; status = "okay"; }; +&mmc0_pins_a { + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_a>; + vmmc-supply = <®_vcc3v0>; + mmc-pwrseq = <&mmc2_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2_pins_a { + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + +&ohci0 { + status = "okay"; +}; + &pio { - mmc0_cd_pin_q8h: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; + gmac_phy_reset_pin_bpi_m2: gmac_phy_reset_pin@0 { + allwinner,pins = "PA21"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + led_pins_bpi_m2: led_pins@0 { + allwinner,pins = "PG5", "PG10", "PG11"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_cd_pin_bpi_m2: mmc0_cd_pin@0 { + allwinner,pins = "PA4"; allwinner,function = "gpio_in"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; }; -&r_uart { - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; - status = "okay"; +&r_pio { + mmc2_pwrseq_pin_bpi_m2: mmc2_pwrseq_pin@0 { + allwinner,pins = "PL8"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; -/* - * FIXME for now we only support host mode and rely on u-boot to have - * turned on Vbus which is controlled by the axp223 pmic on the board. - * - * Once we have axp223 support we should switch to fully supporting otg. - */ -&usb_otg { - dr_mode = "host"; +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index 9b3a91f..907cb40 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -18,6 +18,8 @@ #define IOMUXC_GPR1_REF_SSP_EN (1 << 16) #define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) +#define IOMUXC_GPR1_PCIE_SW_RST (1 << 29) + /* * IOMUXC_GPR5 bit fields */ diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 94f29fd..24563c0 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -69,8 +69,6 @@ void sdelay(unsigned long); void make_cs1_contiguous(void); void omap_nand_switch_ecc(uint32_t, uint32_t); void power_init_r(void); -void dieid_num_r(void); -void get_dieid(u32 *id); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); void omap3_set_aux_cr_secure(u32 acr); u32 warm_reset(void); diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 12b1a09..4712722 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -33,10 +33,6 @@ /* CONTROL_ID_CODE */ #define CONTROL_ID_CODE 0x4A002204 -#define STD_FUSE_DIE_ID_0 0x4A002200 -#define STD_FUSE_DIE_ID_1 0x4A002208 -#define STD_FUSE_DIE_ID_2 0x4A00220c -#define STD_FUSE_DIE_ID_3 0x4A002210 #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 0c928d4..587ee39 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -103,13 +103,17 @@ #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ #define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ -/* PTWs cacheable, inner/outer WBWA and non-shareable */ +/* PTWs cacheable, inner/outer WBWA and inner shareable */ #define TCR_FLAGS (TCR_TG0_64K | \ - TCR_SHARED_NON | \ + TCR_SHARED_INNER | \ TCR_ORGN_WBWA | \ TCR_IRGN_WBWA | \ TCR_T0SZ(VA_BITS)) +#define TCR_EL1_RSVD (1 << 31) +#define TCR_EL2_RSVD (1 << 31 | 1 << 23) +#define TCR_EL3_RSVD (1 << 31 | 1 << 23) + #ifndef __ASSEMBLY__ void set_pgtable_section(u64 *page_table, u64 index, diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 81f1616..d7b81c1 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -603,8 +603,11 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, u32 txdone, u32 txdone_mask, u32 opp); s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); -void usb_fake_mac_from_die_id(u32 *id); -void usb_set_serial_num_from_die_id(u32 *id); +void omap_die_id_serial(void); +void omap_die_id_get_board_serial(struct tag_serialnr *serialnr); +void omap_die_id_usbethaddr(void); +void omap_die_id_display(void); + void recalibrate_iodelay(void); void omap_smc1(u32 service, u32 val); @@ -612,6 +615,8 @@ void omap_smc1(u32 service, u32 val); void enable_edma3_clocks(void); void disable_edma3_clocks(void); +void omap_die_id(unsigned int *die_id); + /* ABB */ #define OMAP_ABB_NOMINAL_OPP 0 #define OMAP_ABB_FAST_OPP 1 diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 617e22f..b69d073 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -26,6 +26,9 @@ #define OMAP_MMC_H_ struct hsmmc { +#ifdef CONFIG_DM_MMC + unsigned char res0[0x100]; +#endif unsigned char res1[0x10]; unsigned int sysconfig; /* 0x10 */ unsigned int sysstatus; /* 0x14 */ diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index de7650e..d588f94 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -17,6 +17,8 @@ #define L2X0_CTRL_EN 1 #define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) +#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) +#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) struct pl310_regs { u32 pl310_cache_id; diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 868ea54..cfc7834 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -194,7 +194,7 @@ void save_boot_params_ret(void); static inline unsigned int get_cr(void) { unsigned int val; - asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); + asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); return val; } diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index 011c03c..a0d0d9b 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -11,6 +11,7 @@ #define _KEYSTONE_NET_H_ #include <asm/io.h> +#include <phy.h> /* EMAC */ #ifdef CONFIG_KSNET_NETCP_V1_0 @@ -49,7 +50,11 @@ #define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE /* MDIO module input frequency */ +#ifdef CONFIG_SOC_K2G +#define EMAC_MDIO_BUS_FREQ (clk_get_rate(sys_clk0_3_clk)) +#else #define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk)) +#endif /* MDIO clock output frequency */ #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ @@ -188,6 +193,11 @@ struct mac_sl_cfg { #define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034) #define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038) +/* RGMII */ +#define RGMII_REG_STATUS_LINK BIT(0) + +#define RGMII_STATUS_REG (GBETH_BASE + 0x18) + /* PSS */ #ifdef CONFIG_KSNET_NETCP_V1_0 @@ -239,6 +249,7 @@ struct eth_priv_t { int phy_addr; int slave_port; int sgmii_link_type; + phy_interface_t phy_if; struct phy_device *phy_dev; }; diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index afd4f10..4c3a94a 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -25,7 +25,8 @@ * the GD ('global data') structure, both located in some readily * available RAM (SRAM, locked cache...). In this context, VARIABLE * global data, initialized or not (BSS), are UNAVAILABLE; only - * CONSTANT initialized data are available. + * CONSTANT initialized data are available. GD should be zeroed + * before board_init_f() is called. * * 2. Call board_init_f(). This function prepares the hardware for * execution from system RAM (DRAM, DDR...) As system RAM may not @@ -34,24 +35,29 @@ * data include the relocation destination, the future stack, and * the future GD location. * - * (the following applies only to non-SPL builds) - * * 3. Set up intermediate environment where the stack and GD are the * ones allocated by board_init_f() in system RAM, but BSS and * initialized non-const data are still not available. * - * 4. Call relocate_code(). This function relocates U-Boot from its - * current location into the relocation destination computed by - * board_init_f(). + * 4a.For U-Boot proper (not SPL), call relocate_code(). This function + * relocates U-Boot from its current location into the relocation + * destination computed by board_init_f(). + * + * 4b.For SPL, board_init_f() just returns (to crt0). There is no + * code relocation in SPL. * * 5. Set up final environment for calling board_init_r(). This * environment has BSS (initialized to 0), initialized non-const * data (initialized to their intended value), and stack in system - * RAM. GD has retained values set by board_init_f(). Some CPUs - * have some work left to do at this point regarding memory, so - * call c_runtime_cpu_setup. + * RAM (for SPL moving the stack and GD into RAM is optional - see + * CONFIG_SPL_STACK_R). GD has retained values set by board_init_f(). + * + * 6. For U-Boot proper (not SPL), some CPUs have some work left to do + * at this point regarding memory, so call c_runtime_cpu_setup. + * + * 7. Branch to board_init_r(). * - * 6. Branch to board_init_r(). + * For more information see 'Board Initialisation Flow in README. */ /* diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 98a906e..8b34e04 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -27,7 +27,8 @@ * the GD ('global data') structure, both located in some readily * available RAM (SRAM, locked cache...). In this context, VARIABLE * global data, initialized or not (BSS), are UNAVAILABLE; only - * CONSTANT initialized data are available. + * CONSTANT initialized data are available. GD should be zeroed + * before board_init_f() is called. * * 2. Call board_init_f(). This function prepares the hardware for * execution from system RAM (DRAM, DDR...) As system RAM may not @@ -36,24 +37,31 @@ * data include the relocation destination, the future stack, and * the future GD location. * - * (the following applies only to non-SPL builds) - * * 3. Set up intermediate environment where the stack and GD are the * ones allocated by board_init_f() in system RAM, but BSS and * initialized non-const data are still not available. * - * 4. Call relocate_code(). This function relocates U-Boot from its - * current location into the relocation destination computed by - * board_init_f(). + * 4a.For U-Boot proper (not SPL), call relocate_code(). This function + * relocates U-Boot from its current location into the relocation + * destination computed by board_init_f(). + * + * 4b.For SPL, board_init_f() just returns (to crt0). There is no + * code relocation in SPL. * * 5. Set up final environment for calling board_init_r(). This * environment has BSS (initialized to 0), initialized non-const * data (initialized to their intended value), and stack in system - * RAM. GD has retained values set by board_init_f(). Some CPUs - * have some work left to do at this point regarding memory, so - * call c_runtime_cpu_setup. + * RAM (for SPL moving the stack and GD into RAM is optional - see + * CONFIG_SPL_STACK_R). GD has retained values set by board_init_f(). + * + * TODO: For SPL, implement stack relocation on AArch64. * - * 6. Branch to board_init_r(). + * 6. For U-Boot proper (not SPL), some CPUs have some work left to do + * at this point regarding memory, so call c_runtime_cpu_setup. + * + * 7. Branch to board_init_r(). + * + * For more information see 'Board Initialisation Flow in README. */ ENTRY(_main) @@ -106,6 +114,8 @@ relocation_return: */ bl c_runtime_cpu_setup /* still call old routine */ +/* TODO: For SPL, call spl_relocate_stack_gd() to alloc stack relocation */ + /* * Clear BSS section */ diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S index a3e18f7..62d0022 100644 --- a/arch/arm/lib/gic_64.S +++ b/arch/arm/lib/gic_64.S @@ -46,11 +46,19 @@ ENTRY(gic_init_secure) ldr w9, [x0, GICD_TYPER] and w10, w9, #0x1f /* ITLinesNumber */ cbz w10, 1f /* No SPIs */ - add x11, x0, (GICD_IGROUPRn + 4) + add x11, x0, GICD_IGROUPRn mov w9, #~0 /* Config SPIs as Grp1 */ + str w9, [x11], #0x4 0: str w9, [x11], #0x4 sub w10, w10, #0x1 cbnz w10, 0b + + ldr x1, =GICC_BASE /* GICC_CTLR */ + mov w0, #3 /* EnableGrp0 | EnableGrp1 */ + str w0, [x1] + + mov w0, #1 << 7 /* allow NS access to GICC_PMR */ + str w0, [x1, #4] /* GICC_PMR */ #endif 1: ret diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index ff959c8..9260ee2 100644 --- a/arch/arm/mach-bcm283x/include/mach/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -150,6 +150,7 @@ struct bcm2835_mbox_tag_hdr { #define BCM2835_BOARD_REV_A_PLUS 0x12 #define BCM2835_BOARD_REV_B_PLUS_13 0x13 #define BCM2835_BOARD_REV_CM_14 0x14 +#define BCM2835_BOARD_REV_A_PLUS_15 0x15 #endif struct bcm2835_mbox_tag_get_board_rev { diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index 67f1a33..e1962c7 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -13,6 +13,9 @@ config TARGET_K2E_EVM config TARGET_K2L_EVM bool "TI Keystone 2 Lamar EVM" +config TARGET_K2G_EVM + bool "TI Keystone 2 Galileo EVM" + endchoice config SYS_SOC diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index fc3eadb..5c6051e 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -31,8 +31,14 @@ const struct keystone_pll_regs keystone_pll_regs[] = { [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, + [UART_PLL] = {KS2_UARTPLLCTL0, KS2_UARTPLLCTL1}, }; +inline void pll_pa_clk_sel(void) +{ + setbits_le32(keystone_pll_regs[PASS_PLL].reg1, CFG_PLLCTL1_PAPLL_MASK); +} + static void wait_for_completion(const struct pll_init_data *data) { int i; @@ -180,9 +186,8 @@ void configure_secondary_pll(const struct pll_init_data *data) sdelay(21000); /* Select the Output of PASS PLL as input to PASS */ - if (data->pll == PASS_PLL) - setbits_le32(keystone_pll_regs[data->pll].reg1, - CFG_PLLCTL1_PAPLL_MASK); + if (data->pll == PASS_PLL && cpu_is_k2hk()) + pll_pa_clk_sel(); /* Select the Output of ARM PLL as input to ARM */ if (data->pll == TETRIS_PLL) @@ -309,6 +314,10 @@ static unsigned long pll_freq_get(int pll) ret = external_clk[ddr3b_clk]; reg = KS2_DDR3BPLLCTL0; break; + case UART_PLL: + ret = external_clk[uart_clk]; + reg = KS2_UARTPLLCTL0; + break; default: return 0; } @@ -351,6 +360,10 @@ unsigned long clk_get_rate(unsigned int clk) if (cpu_is_k2hk()) freq = pll_freq_get(DDR3B_PLL); break; + case uart_pll_clk: + if (cpu_is_k2g()) + freq = pll_freq_get(UART_PLL); + break; case sys_clk0_1_clk: case sys_clk0_clk: freq = pll_freq_get(CORE_PLL) / pll0div_read(1); diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c index 73ceb83..a539d5d 100644 --- a/arch/arm/mach-keystone/cmd_mon.c +++ b/arch/arm/mach-keystone/cmd_mon.c @@ -37,7 +37,7 @@ static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc, if (argc < 2) return CMD_RET_USAGE; - freq = clk_get_rate(sys_clk0_6_clk); + freq = CONFIG_SYS_HZ_CLOCK; addr = simple_strtoul(argv[1], NULL, 16); diff --git a/arch/arm/mach-keystone/config.mk b/arch/arm/mach-keystone/config.mk index ceacffa..9ae1e9a 100644 --- a/arch/arm/mach-keystone/config.mk +++ b/arch/arm/mach-keystone/config.mk @@ -16,13 +16,13 @@ spl/u-boot-spl.gph: spl/u-boot-spl.bin FORCE OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ --gap-fill=0 -u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE +u-boot-spi.gph: spl/u-boot-spl.gph u-boot-dtb.img FORCE $(call if_changed,pad_cat) ifndef CONFIG_SPL_BUILD MKIMAGEFLAGS_MLO = -A $(ARCH) -T gpimage -C none \ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot -MLO: u-boot.bin FORCE +MLO: u-boot-dtb.bin FORCE $(call if_changed,mkimage) @dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@ endif diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index dfb27b5..34606f4 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -52,7 +52,8 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET); __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET); - __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); + if (!cpu_is_k2g()) + __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET); __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET); @@ -64,6 +65,15 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) ; + /* Disable ECC for K2G */ + if (cpu_is_k2g()) { + clrbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1); + clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1); + clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1); + clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1); + clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1); + } + __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET); while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) ; diff --git a/arch/arm/mach-keystone/include/mach/clock-k2g.h b/arch/arm/mach-keystone/include/mach/clock-k2g.h new file mode 100644 index 0000000..214c1d3 --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/clock-k2g.h @@ -0,0 +1,20 @@ +/* + * K2G: Clock data + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_K2G_H +#define __ASM_ARCH_CLOCK_K2G_H + +#define PLLSET_CMD_LIST "<pa|arm|ddr3>" + +#define DEV_SUPPORTED_SPEEDS 0xfff +#define ARM_SUPPORTED_SPEEDS 0xfff + +#define KS2_CLK1_6 sys_clk0_6_clk + +#endif diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index ddc5f8e..cdcff3b 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -24,8 +24,13 @@ #include <asm/arch/clock-k2l.h> #endif +#ifdef CONFIG_SOC_K2G +#include <asm/arch/clock-k2g.h> +#endif + #define CORE_PLL MAIN_PLL #define DDR3_PLL DDR3A_PLL +#define NSS_PLL PASS_PLL #define CLK_LIST(CLK)\ CLK(0, core_pll_clk)\ @@ -48,7 +53,8 @@ CLK(17, sys_clk1_6_clk)\ CLK(18, sys_clk1_12_clk)\ CLK(19, sys_clk2_clk)\ - CLK(20, sys_clk3_clk) + CLK(20, sys_clk3_clk)\ + CLK(21, uart_pll_clk) #include <asm/types.h> @@ -75,6 +81,7 @@ enum { PASS_PLL, DDR3A_PLL, DDR3B_PLL, + UART_PLL, MAX_PLL_COUNT, }; @@ -85,6 +92,7 @@ enum ext_clk_e { tetris_clk, ddr3a_clk, ddr3b_clk, + uart_clk, ext_clk_count /* number of external clocks */ }; @@ -118,6 +126,7 @@ unsigned long clk_round_rate(unsigned int clk, unsigned long hz); int clk_set_rate(unsigned int clk, unsigned long hz); int get_max_dev_speed(void); int get_max_arm_speed(void); +void pll_pa_clk_sel(void); #endif #endif diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h new file mode 100644 index 0000000..fa4162f --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h @@ -0,0 +1,74 @@ +/* + * K2G: SoC definitions + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_HARDWARE_K2G_H +#define __ASM_ARCH_HARDWARE_K2G_H + +#define KS2_NUM_DSPS 0 + +/* Power and Sleep Controller (PSC) Domains */ +#define KS2_LPSC_ALWAYSON 0 +#define KS2_LPSC_PMMC 1 +#define KS2_LPSC_DEBUG 2 +#define KS2_LPSC_NSS 3 +#define KS2_LPSC_SA 4 +#define KS2_LPSC_TERANET 5 +#define KS2_LPSC_SYS_COMP 6 +#define KS2_LPSC_QSPI 7 +#define KS2_LPSC_MMC 8 +#define KS2_LPSC_GPMC 9 +#define KS2_LPSC_MLB 11 +#define KS2_LPSC_EHRPWM 12 +#define KS2_LPSC_EQEP 13 +#define KS2_LPSC_ECAP 14 +#define KS2_LPSC_MCASP 15 +#define KS2_LPSC_SR 16 +#define KS2_LPSC_MSMC 17 +#define KS2_LPSC_GEM 18 +#define KS2_LPSC_ARM 19 +#define KS2_LPSC_ASRC 20 +#define KS2_LPSC_ICSS 21 +#define KS2_LPSC_DSS 23 +#define KS2_LPSC_PCIE 24 +#define KS2_LPSC_USB_0 25 +#define KS2_LPSC_USB KS2_LPSC_USB_0 +#define KS2_LPSC_USB_1 26 +#define KS2_LPSC_DDR3 27 +#define KS2_LPSC_SPARE0_LPSC0 28 +#define KS2_LPSC_SPARE0_LPSC1 29 +#define KS2_LPSC_SPARE1_LPSC0 30 +#define KS2_LPSC_SPARE1_LPSC1 31 + +#define KS2_LPSC_CPGMAC KS2_LPSC_NSS +#define KS2_LPSC_CRYPTO KS2_LPSC_SA + +/* SGMII SerDes */ +#define KS2_LANES_PER_SGMII_SERDES 4 + +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_CTRL_BASE 0x04010000 +#define KS2_NETCP_PDMA_TX_BASE 0x04011000 +#define KS2_NETCP_PDMA_TX_CH_NUM 21 +#define KS2_NETCP_PDMA_RX_BASE 0x04012000 +#define KS2_NETCP_PDMA_RX_CH_NUM 32 +#define KS2_NETCP_PDMA_SCHED_BASE 0x04010100 +#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x04013000 +#define KS2_NETCP_PDMA_RX_FLOW_NUM 32 +#define KS2_NETCP_PDMA_TX_SND_QUEUE 5 + +/* NETCP */ +#define KS2_NETCP_BASE 0x04000000 + +#define K2G_GPIO0_BASE 0X02603000 +#define K2G_GPIO1_BASE 0X0260a000 +#define K2G_GPIO1_BANK2_BASE K2G_GPIO1_BASE + 0x38 +#define K2G_GPIO_DIR_OFFSET 0x0 +#define K2G_GPIO_SETDATA_OFFSET 0x8 + +#endif /* __ASM_ARCH_HARDWARE_K2G_H */ diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index f98a24e..edebcd7 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -52,6 +52,10 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4 #define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4 +#define KS2_DDRPHY_DATX8_4_OFFSET 0x2C0 +#define KS2_DDRPHY_DATX8_5_OFFSET 0x300 +#define KS2_DDRPHY_DATX8_6_OFFSET 0x340 +#define KS2_DDRPHY_DATX8_7_OFFSET 0x380 #define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0 #define IODDRM_MASK 0x00000180 @@ -121,8 +125,13 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x)) /* NETCP pktdma */ +#ifdef CONFIG_SOC_K2G +#define KS2_NETCP_PDMA_RX_FREE_QUEUE 113 +#define KS2_NETCP_PDMA_RX_RCV_QUEUE 114 +#else #define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001 #define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002 +#endif /* Chip Interrupt Controller */ #define KS2_CIC2_BASE 0x02608000 @@ -143,6 +152,8 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) #define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) #define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c) +#define KS2_ETHERNET_CFG (KS2_DEVICE_STATE_CTRL_BASE + 0xe20) +#define KS2_ETHERNET_RGMII 2 /* PSC */ #define KS2_PSC_BASE 0x02350000 @@ -167,6 +178,8 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) #define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) #define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) +#define KS2_UARTPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x390) +#define KS2_UARTPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x394) #define KS2_PLL_CNTRL_BASE 0x02310000 #define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE @@ -179,10 +192,17 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_RSTYPE_PLL_SOFT BIT(13) /* SPI */ +#ifdef CONFIG_SOC_K2G +#define KS2_SPI0_BASE 0x21805400 +#define KS2_SPI1_BASE 0x21805800 +#define KS2_SPI2_BASE 0x21805c00 +#define KS2_SPI3_BASE 0x21806000 +#else #define KS2_SPI0_BASE 0x21000400 #define KS2_SPI1_BASE 0x21000600 #define KS2_SPI2_BASE 0x21000800 #define KS2_SPI_BASE KS2_SPI0_BASE +#endif /* AEMIF */ #define KS2_AEMIF_CNTRL_BASE 0x21000a00 @@ -194,10 +214,16 @@ typedef volatile unsigned int *dv_reg_p; /* MSMC control */ #define KS2_MSMC_CTRL_BASE 0x0bc00000 #define KS2_MSMC_DATA_BASE 0x0c000000 +#ifndef CONFIG_SOC_K2G #define KS2_MSMC_SEGMENT_TETRIS 8 #define KS2_MSMC_SEGMENT_NETCP 9 #define KS2_MSMC_SEGMENT_QM_PDSP 10 #define KS2_MSMC_SEGMENT_PCIE0 11 +#else +#define KS2_MSMC_SEGMENT_TETRIS 1 +#define KS2_MSMC_SEGMENT_NETCP 4 +#define KS2_MSMC_SEGMENT_PCIE0 5 +#endif /* MSMC segment size shift bits */ #define KS2_MSMC_SEG_SIZE_SHIFT 12 @@ -211,6 +237,22 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) /* Queue manager */ +#ifdef CONFIG_SOC_K2G +#define KS2_QM_BASE_ADDRESS 0x040C0000 +#define KS2_QM_CONF_BASE 0x04040000 +#define KS2_QM_DESC_SETUP_BASE 0x04080000 +#define KS2_QM_STATUS_RAM_BASE 0x0 /* K2G doesn't have it */ +#define KS2_QM_INTD_CONF_BASE 0x0 +#define KS2_QM_PDSP1_CMD_BASE 0x0 +#define KS2_QM_PDSP1_CTRL_BASE 0x0 +#define KS2_QM_PDSP1_IRAM_BASE 0x0 +#define KS2_QM_MANAGER_QUEUES_BASE 0x040c0000 +#define KS2_QM_MANAGER_Q_PROXY_BASE 0x04040200 +#define KS2_QM_QUEUE_STATUS_BASE 0x04100000 +#define KS2_QM_LINK_RAM_BASE 0x04020000 +#define KS2_QM_REGION_NUM 8 +#define KS2_QM_QPOOL_NUM 112 +#else #define KS2_QM_BASE_ADDRESS 0x23a80000 #define KS2_QM_CONF_BASE 0x02a02000 #define KS2_QM_DESC_SETUP_BASE 0x02a03000 @@ -225,6 +267,7 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_QM_LINK_RAM_BASE 0x00100000 #define KS2_QM_REGION_NUM 64 #define KS2_QM_QPOOL_NUM 4000 +#endif /* USB */ #define KS2_USB_SS_BASE 0x02680000 @@ -247,6 +290,7 @@ typedef volatile unsigned int *dv_reg_p; #define CPU_66AK2Hx 0xb981 #define CPU_66AK2Ex 0xb9a6 #define CPU_66AK2Lx 0xb9a7 +#define CPU_66AK2Gx 0xbb06 /* DEVSPEED register */ #define DEVSPEED_DEVSPEED_SHIFT 16 @@ -267,6 +311,10 @@ typedef volatile unsigned int *dv_reg_p; #include <asm/arch/hardware-k2l.h> #endif +#ifdef CONFIG_SOC_K2G +#include <asm/arch/hardware-k2g.h> +#endif + #ifndef __ASSEMBLY__ static inline u16 get_part_number(void) @@ -291,6 +339,11 @@ static inline u8 cpu_is_k2l(void) return get_part_number() == CPU_66AK2Lx; } +static inline u8 cpu_is_k2g(void) +{ + return get_part_number() == CPU_66AK2Gx; +} + static inline u8 cpu_revision(void) { u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG); diff --git a/arch/arm/mach-keystone/include/mach/mmc_host_def.h b/arch/arm/mach-keystone/include/mach/mmc_host_def.h new file mode 100644 index 0000000..a5050ac --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/mmc_host_def.h @@ -0,0 +1,22 @@ +/* + * K2G: MMC + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef K2G_MMC_HOST_DEF_H +#define K2G_MMC_HOST_DEF_H + +#include <asm/omap_mmc.h> + +/* + * OMAP HSMMC register definitions + */ + +#define OMAP_HSMMC1_BASE 0x23000100 +#define OMAP_HSMMC2_BASE 0x23100100 + +#endif /* K2G_MMC_HOST_DEF_H */ diff --git a/arch/arm/mach-keystone/include/mach/mux-k2g.h b/arch/arm/mach-keystone/include/mach/mux-k2g.h new file mode 100644 index 0000000..6167d2c --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/mux-k2g.h @@ -0,0 +1,58 @@ +/* + * K2G: Pinmux configuration + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MUX_K2G_H +#define __ASM_ARCH_MUX_K2G_H + +#include <common.h> +#include <asm/io.h> + +#define K2G_PADCFG_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x1000) + +/* + * 20:19 - buffer class RW fixed + * 18 - rxactive (Input enabled for the pad ) 0 - Di; 1 - En; + * 17 - pulltypesel (0 - PULLDOWN; 1 - PULLUP); + * 16 - pulluden (0 - PULLUP/DOWN EN; 1 - DI); + * 3:0 - muxmode (available modes 0:5) + */ + +#define PIN_IEN (1 << 18) /* pin input enabled */ +#define PIN_PDIS (1 << 16) /* pull up/down disabled */ +#define PIN_PTU (1 << 17) /* pull up */ +#define PIN_PTD (0 << 17) /* pull down */ + +#define MODE(m) ((m) & 0x7) +#define MAX_PIN_N 260 + +#define MUX_CFG(value, index) \ + __raw_writel(\ + (value) | \ + (__raw_readl(K2G_PADCFG_REG + (index << 2)) & \ + (0x3 << 19)),\ + (K2G_PADCFG_REG + (index << 2))\ + ); + +struct pin_cfg { + int reg_inx; + u32 val; +}; + +static inline void configure_pin_mux(struct pin_cfg *pin_mux) +{ + if (!pin_mux) + return; + + while ((pin_mux->reg_inx >= 0) && (pin_mux->reg_inx < MAX_PIN_N)) { + MUX_CFG(pin_mux->val, pin_mux->reg_inx); + pin_mux++; + } +} + +#endif /* __ASM_ARCH_MUX_K2G_H */ diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index a9a7d41..aadd10b 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -103,7 +103,9 @@ int arch_cpu_init(void) msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS); msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP); +#ifdef KS2_MSMC_SEGMENT_QM_PDSP msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP); +#endif msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0); /* Initialize the PCIe-0 to work as Root Complex */ @@ -122,8 +124,10 @@ int arch_cpu_init(void) * UART register PWREMU_MGMT is initialized. Linux UART * driver doesn't handle this. */ +#ifndef CONFIG_DM_SERIAL NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2), CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); +#endif return 0; } @@ -167,6 +171,9 @@ int print_cpuinfo(void) case CPU_66AK2Ex: puts("66AK2Ex SR"); break; + case CPU_66AK2Gx: + puts("66AK2Gx SR"); + break; default: puts("Unknown\n"); } diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig new file mode 100644 index 0000000..79ff0e8 --- /dev/null +++ b/arch/arm/mach-mvebu/Kconfig @@ -0,0 +1,31 @@ +if ARCH_MVEBU + +choice + prompt "Marvell MVEBU (Armada XP/38x) board select" + optional + +config TARGET_DB_88F6820_GP + bool "Support DB-88F6820-GP" + +config TARGET_DB_MV784MP_GP + bool "Support db-mv784mp-gp" + +config TARGET_MAXBCM + bool "Support maxbcm" + +endchoice + +config SYS_SOC + default "mvebu" + +config MVEBU_BOOTROM_UARTBOOT + bool "Use kwboot to boot via BootROM xmodem protocol" + help + This option provides support for booting via the Marvell + xmodem protocol, used by the kwboot tool. + + Please don't forget to configure the boot device in + the board specific kwbimage.cfg file this way: + BOOT_FROM uart + +endif diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index efd4d04..895ad92 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -27,6 +27,14 @@ static struct mbus_win windows[] = { CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM }, }; +void lowlevel_init(void) +{ + /* + * Dummy implementation, we only need LOWLEVEL_INIT + * on Armada to configure CP15 in start.S / cpu_init_cp15() + */ +} + void reset_cpu(unsigned long ignored) { struct mvebu_system_registers *reg = @@ -214,7 +222,10 @@ static void setup_usb_phys(void) int arch_cpu_init(void) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMADA_38X) +#if !defined(CONFIG_SPL_BUILD) + struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + /* * Only with disabled MMU its possible to switch the base * register address on Armada 38x. Without this the SDRAM @@ -234,18 +245,14 @@ int arch_cpu_init(void) * configured the internal register base to the value used * in the macros / defines in the U-Boot header (soc.h). */ - if (mvebu_soc_family() == MVEBU_SOC_A38X) { - struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; - /* - * To fully release / unlock this area from cache, we need - * to flush all caches and disable the L2 cache. - */ - icache_disable(); - dcache_disable(); - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - } + /* + * To fully release / unlock this area from cache, we need + * to flush all caches and disable the L2 cache. + */ + icache_disable(); + dcache_disable(); + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); #endif /* diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 6fa4173..5e8bf0c 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -119,6 +119,8 @@ int mvebu_mbus_probe(struct mbus_win windows[], int count); int mvebu_soc_family(void); u32 mvebu_get_nand_clock(void); +void return_to_bootrom(void); + int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); /* diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 02c21bc..22abde0 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -31,7 +31,7 @@ /* SOC specific definations */ #define INTREG_BASE 0xd0000000 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYS_MVEBU_DDR_A38X) +#if defined(CONFIG_SPL_BUILD) /* * On A38x switching the regs base address without running from * SDRAM doesn't seem to work. So let the SPL still use the diff --git a/arch/arm/mach-mvebu/lowlevel_spl.S b/arch/arm/mach-mvebu/lowlevel_spl.S index 69da7fe..2e2181e 100644 --- a/arch/arm/mach-mvebu/lowlevel_spl.S +++ b/arch/arm/mach-mvebu/lowlevel_spl.S @@ -5,10 +5,26 @@ #include <config.h> #include <linux/linkage.h> +#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT ENTRY(save_boot_params) + stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */ + ldr r12, =CONFIG_SPL_BOOTROM_SAVE + str sp, [r12] b save_boot_params_ret ENDPROC(save_boot_params) +ENTRY(return_to_bootrom) + ldr r12, =CONFIG_SPL_BOOTROM_SAVE + ldr sp, [r12] + mov r0, #0x0 /* @ return value: 0x0 NO_ERR */ + ldmfd sp!, {r0 - r12, pc} /* @ restore regs and return */ +ENDPROC(return_to_bootrom) +#else +ENTRY(save_boot_params) + b save_boot_params_ret +ENDPROC(save_boot_params) +#endif + /* * cache_inv - invalidate Cache line * r0 - dest diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index af61ded..0ab729a 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -31,11 +31,18 @@ u32 spl_boot_mode(void) void board_init_f(ulong dummy) { - /* Set global data pointer */ - gd = &gdata; +#ifndef CONFIG_MVEBU_BOOTROM_UARTBOOT + /* + * Only call arch_cpu_init() when not returning to the + * Marvell BootROM, which is done when booting via + * the xmodem protocol (kwboot tool). Otherwise the + * internal register will get remapped and the BootROM + * can't continue to run correctly. + */ /* Linux expects the internal registers to be at 0xf1000000 */ arch_cpu_init(); +#endif /* * Pin muxing needs to be done before UART output, since @@ -54,5 +61,18 @@ void board_init_f(ulong dummy) /* Setup DDR */ ddr3_init(); - board_init_r(NULL, 0); +#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT + /* + * Return to the BootROM to continue the Marvell xmodem + * UART boot protocol. As initiated by the kwboot tool. + * + * This can only be done by the BootROM and not by the + * U-Boot SPL infrastructure, since the beginning of the + * image is already read and interpreted by the BootROM. + * SPL has no chance to receive this information. So we + * need to return to the BootROM to enable this xmodem + * UART download. + */ + return_to_bootrom(); +#endif } diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 0940cc5..bbd31ef 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -52,6 +52,18 @@ void enable_caches(void) #endif } +void v7_outer_cache_enable(void) +{ + /* disable the L2 cache */ + writel(0, &pl310->pl310_ctrl); + + /* enable BRESP, instruction and data prefetch, full line of zeroes */ + setbits_le32(&pl310->pl310_aux_ctrl, + L310_AUX_CTRL_DATA_PREFETCH_MASK | + L310_AUX_CTRL_INST_PREFETCH_MASK | + L310_SHARED_ATT_OVERRIDE_ENABLE); +} + /* * DesignWare Ethernet initialization */ diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 83b49b5..6b44a37 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -15,7 +15,8 @@ LDFLAGS_FINAL += --bss-plt PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections \ -fdata-sections -mcall-linux -PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 -m32 +PF_CPPFLAGS_POWERPC := $(call cc-option,-fno-ira-hoist-pressure,) +PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 -m32 $(PF_CPPFLAGS_POWERPC) PLATFORM_LDFLAGS += -m32 -melf32ppclinux # diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c deleted file mode 100644 index 4c9c3ac..0000000 --- a/arch/powerpc/lib/board.c +++ /dev/null @@ -1,986 +0,0 @@ -/* - * (C) Copyright 2000-2011 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <watchdog.h> -#include <command.h> -#include <malloc.h> -#include <stdio_dev.h> -#ifdef CONFIG_8xx -#include <mpc8xx.h> -#endif -#ifdef CONFIG_5xx -#include <mpc5xx.h> -#endif -#ifdef CONFIG_MPC5xxx -#include <mpc5xxx.h> -#endif -#if defined(CONFIG_CMD_IDE) -#include <ide.h> -#endif -#if defined(CONFIG_CMD_SCSI) -#include <scsi.h> -#endif -#if defined(CONFIG_CMD_KGDB) -#include <kgdb.h> -#endif -#ifdef CONFIG_STATUS_LED -#include <status_led.h> -#endif -#include <net.h> -#ifdef CONFIG_GENERIC_MMC -#include <mmc.h> -#endif -#include <serial.h> -#ifdef CONFIG_SYS_ALLOC_DPRAM -#if !defined(CONFIG_CPM2) -#include <commproc.h> -#endif -#endif -#include <version.h> -#if defined(CONFIG_BAB7xx) -#include <w83c553f.h> -#endif -#include <dtt.h> -#if defined(CONFIG_POST) -#include <post.h> -#endif -#if defined(CONFIG_LOGBUFFER) -#include <logbuff.h> -#endif -#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) -#include <asm/cache.h> -#endif -#ifdef CONFIG_PS2KBD -#include <keyboard.h> -#endif - -#ifdef CONFIG_ADDR_MAP -#include <asm/mmu.h> -#endif - -#ifdef CONFIG_MP -#include <asm/mp.h> -#endif - -#ifdef CONFIG_BITBANGMII -#include <miiphy.h> -#endif - -#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE -extern int update_flash_size(int flash_size); -#endif - -#if defined(CONFIG_CMD_DOC) -void doc_init(void); -#endif -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) -#include <i2c.h> -#endif -#include <spi.h> -#include <nand.h> - -static char *failed = "*** failed ***\n"; - -#if defined(CONFIG_OXC) || defined(CONFIG_RMU) -extern flash_info_t flash_info[]; -#endif - -#if defined(CONFIG_START_IDE) -extern int board_start_ide(void); -#endif -#include <environment.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_SYS_MEM_TOP_HIDE) -#define CONFIG_SYS_MEM_TOP_HIDE 0 -#endif - -extern ulong __init_end; -extern ulong __bss_end; -ulong monitor_flash_len; - -#if defined(CONFIG_CMD_BEDBUG) -#include <bedbug/type.h> -#endif - -/* - * Utilities - */ - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ -typedef int (init_fnc_t)(void); - -/* - * Init Utilities - * - * Some of this code should be moved into the core functions, - * but let's get it working (again) first... - */ - -static int init_baudrate(void) -{ - gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); - return 0; -} - -/***********************************************************************/ - -static void __board_add_ram_info(int use_default) -{ - /* please define platform specific board_add_ram_info() */ -} - -void board_add_ram_info(int) - __attribute__ ((weak, alias("__board_add_ram_info"))); - -static int __board_flash_wp_on(void) -{ - /* - * Most flashes can't be detected when write protection is enabled, - * so provide a way to let U-Boot gracefully ignore write protected - * devices. - */ - return 0; -} - -int board_flash_wp_on(void) - __attribute__ ((weak, alias("__board_flash_wp_on"))); - -static void __cpu_secondary_init_r(void) -{ -} - -void cpu_secondary_init_r(void) - __attribute__ ((weak, alias("__cpu_secondary_init_r"))); - -static int init_func_ram(void) -{ -#ifdef CONFIG_BOARD_TYPES - int board_type = gd->board_type; -#else - int board_type = 0; /* use dummy arg */ -#endif - puts("DRAM: "); - - gd->ram_size = initdram(board_type); - - if (gd->ram_size > 0) { - print_size(gd->ram_size, ""); - board_add_ram_info(0); - putc('\n'); - return 0; - } - puts(failed); - return 1; -} - -/***********************************************************************/ - -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) -static int init_func_i2c(void) -{ - puts("I2C: "); -#ifdef CONFIG_SYS_I2C - i2c_init_all(); -#else - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - puts("ready\n"); - return 0; -} -#endif - -#if defined(CONFIG_HARD_SPI) -static int init_func_spi(void) -{ - puts("SPI: "); - spi_init(); - puts("ready\n"); - return 0; -} -#endif - -/***********************************************************************/ - -#if defined(CONFIG_WATCHDOG) -int init_func_watchdog_init(void) -{ -#if defined(CONFIG_MPC85xx) - init_85xx_watchdog(); -#endif - puts(" Watchdog enabled\n"); - WATCHDOG_RESET(); - return 0; -} - -int init_func_watchdog_reset(void) -{ - WATCHDOG_RESET(); - return 0; -} -#endif /* CONFIG_WATCHDOG */ - -/* - * Initialization sequence - */ - -static init_fnc_t *init_sequence[] = { -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) - probecpu, -#endif -#if defined(CONFIG_BOARD_EARLY_INIT_F) - board_early_init_f, -#endif -#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) - get_clocks, /* get CPU and bus clocks (etc.) */ -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ - && !defined(CONFIG_TQM885D) - adjust_sdram_tbs_8xx, -#endif - init_timebase, -#endif -#ifdef CONFIG_SYS_ALLOC_DPRAM -#if !defined(CONFIG_CPM2) - dpram_init, -#endif -#endif -#if defined(CONFIG_BOARD_POSTCLK_INIT) - board_postclk_init, -#endif - env_init, -#if defined(CONFIG_8xx_CPUCLK_DEFAULT) - /* get CPU and bus clocks according to the environment variable */ - get_clocks_866, - /* adjust sdram refresh rate according to the new clock */ - sdram_adjust_866, - init_timebase, -#endif - init_baudrate, - serial_init, - console_init_f, - display_options, -#if defined(CONFIG_MPC8260) - prt_8260_rsr, - prt_8260_clks, -#endif /* CONFIG_MPC8260 */ -#if defined(CONFIG_MPC83xx) - prt_83xx_rsr, -#endif - checkcpu, -#if defined(CONFIG_MPC5xxx) - prt_mpc5xxx_clks, -#endif /* CONFIG_MPC5xxx */ - checkboard, - INIT_FUNC_WATCHDOG_INIT -#if defined(CONFIG_MISC_INIT_F) - misc_init_f, -#endif - INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) - init_func_i2c, -#endif -#if defined(CONFIG_HARD_SPI) - init_func_spi, -#endif -#ifdef CONFIG_POST - post_init_f, -#endif - INIT_FUNC_WATCHDOG_RESET - init_func_ram, -#if defined(CONFIG_SYS_DRAM_TEST) - testdram, -#endif /* CONFIG_SYS_DRAM_TEST */ - INIT_FUNC_WATCHDOG_RESET - NULL, /* Terminate this list */ -}; - -static int __fixup_cpu(void) -{ - return 0; -} - -int fixup_cpu(void) __attribute__((weak, alias("__fixup_cpu"))); - -/* - * This is the first part of the initialization sequence that is - * implemented in C, but still running from ROM. - * - * The main purpose is to provide a (serial) console interface as - * soon as possible (so we can see any error messages), and to - * initialize the RAM so that we can relocate the monitor code to - * RAM. - * - * Be aware of the restrictions: global data is read-only, BSS is not - * initialized, and stack space is limited to a few kB. - */ - -void board_init_f(ulong bootflag) -{ - bd_t *bd; - ulong len, addr, addr_sp; - ulong *s; - gd_t *id; - init_fnc_t **init_fnc_ptr; - -#ifdef CONFIG_PRAM - ulong reg; -#endif - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("":::"memory"); - -#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \ - !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \ - !defined(CONFIG_MPC86xx) - /* Clear initial global data */ - memset((void *) gd, 0, sizeof(gd_t)); -#endif - - gd->flags = bootflag; - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) - if ((*init_fnc_ptr) () != 0) - hang(); - -#ifdef CONFIG_POST - post_bootmode_init(); - post_run(NULL, POST_ROM | post_bootmode_get(NULL)); -#endif - - WATCHDOG_RESET(); - - /* - * Now that we have DRAM mapped and working, we can - * relocate the code and continue running from DRAM. - * - * Reserve memory at end of RAM for (top down in that order): - * - area that won't get touched by U-Boot and Linux (optional) - * - kernel log buffer - * - protected RAM - * - LCD framebuffer - * - monitor code - * - board info struct - */ - len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; - - /* - * Subtract specified amount of memory to hide so that it won't - * get "touched" at all by U-Boot. By fixing up gd->ram_size - * the Linux kernel should now get passed the now "corrected" - * memory size and won't touch it either. This should work - * for arch/ppc and arch/powerpc. Only Linux board ports in - * arch/powerpc with bootwrapper support, that recalculate the - * memory size from the SDRAM controller setup will have to - * get fixed. - */ - gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; - - addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize(); - -#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) - /* - * We need to make sure the location we intend to put secondary core - * boot code is reserved and not used by any part of u-boot - */ - if (addr > determine_mp_bootpg(NULL)) { - addr = determine_mp_bootpg(NULL); - debug("Reserving MP boot page to %08lx\n", addr); - } -#endif - -#ifdef CONFIG_LOGBUFFER -#ifndef CONFIG_ALT_LB_ADDR - /* reserve kernel log buffer */ - addr -= (LOGBUFF_RESERVE); - debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, - addr); -#endif -#endif - -#ifdef CONFIG_PRAM - /* - * reserve protected RAM - */ - reg = getenv_ulong("pram", 10, CONFIG_PRAM); - addr -= (reg << 10); /* size is in kB */ - debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr); -#endif /* CONFIG_PRAM */ - - /* round down to next 4 kB limit */ - addr &= ~(4096 - 1); - debug("Top of RAM usable for U-Boot at: %08lx\n", addr); - -#ifdef CONFIG_LCD -#ifdef CONFIG_FB_ADDR - gd->fb_base = CONFIG_FB_ADDR; -#else - /* reserve memory for LCD display (always full pages) */ - addr = lcd_setmem(addr); - gd->fb_base = addr; -#endif /* CONFIG_FB_ADDR */ -#endif /* CONFIG_LCD */ - -#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx) - /* reserve memory for video display (always full pages) */ - addr = video_setmem(addr); - gd->fb_base = addr; -#endif /* CONFIG_VIDEO */ - - /* - * reserve memory for U-Boot code, data & bss - * round down to next 4 kB limit - */ - addr -= len; - addr &= ~(4096 - 1); -#ifdef CONFIG_E500 - /* round down to next 64 kB limit so that IVPR stays aligned */ - addr &= ~(65536 - 1); -#endif - - debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); - - /* - * reserve memory for malloc() arena - */ - addr_sp = addr - TOTAL_MALLOC_LEN; - debug("Reserving %dk for malloc() at: %08lx\n", - TOTAL_MALLOC_LEN >> 10, addr_sp); - - /* - * (permanently) allocate a Board Info struct - * and a permanent copy of the "global" data - */ - addr_sp -= sizeof(bd_t); - bd = (bd_t *) addr_sp; - memset(bd, 0, sizeof(bd_t)); - gd->bd = bd; - debug("Reserving %zu Bytes for Board Info at: %08lx\n", - sizeof(bd_t), addr_sp); - addr_sp -= sizeof(gd_t); - id = (gd_t *) addr_sp; - debug("Reserving %zu Bytes for Global Data at: %08lx\n", - sizeof(gd_t), addr_sp); - - /* - * Finally, we set up a new (bigger) stack. - * - * Leave some safety gap for SP, force alignment on 16 byte boundary - * Clear initial stack frame - */ - addr_sp -= 16; - addr_sp &= ~0xF; - s = (ulong *) addr_sp; - *s = 0; /* Terminate back chain */ - *++s = 0; /* NULL return address */ - debug("Stack Pointer at: %08lx\n", addr_sp); - - /* - * Save local variables to board info struct - */ - - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ - bd->bi_memsize = gd->ram_size; /* size in bytes */ - -#ifdef CONFIG_SYS_SRAM_BASE - bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ - bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ -#endif - -#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ - defined(CONFIG_E500) || defined(CONFIG_MPC86xx) - bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ -#endif -#if defined(CONFIG_MPC5xxx) - bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ -#endif -#if defined(CONFIG_MPC83xx) - bd->bi_immrbar = CONFIG_SYS_IMMR; -#endif - - WATCHDOG_RESET(); - bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ - bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ -#if defined(CONFIG_CPM2) - bd->bi_cpmfreq = gd->arch.cpm_clk; - bd->bi_brgfreq = gd->arch.brg_clk; - bd->bi_sccfreq = gd->arch.scc_clk; - bd->bi_vco = gd->arch.vco_out; -#endif /* CONFIG_CPM2 */ -#if defined(CONFIG_MPC512X) - bd->bi_ipsfreq = gd->arch.ips_clk; -#endif /* CONFIG_MPC512X */ -#if defined(CONFIG_MPC5xxx) - bd->bi_ipbfreq = gd->arch.ipb_clk; - bd->bi_pcifreq = gd->pci_clk; -#endif /* CONFIG_MPC5xxx */ - -#ifdef CONFIG_SYS_EXTBDINFO - strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); - strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, - sizeof(bd->bi_r_version)); - - bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ - bd->bi_plb_busfreq = gd->bus_clk; -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - bd->bi_pci_busfreq = get_PCI_freq(); - bd->bi_opbfreq = get_OPB_freq(); -#elif defined(CONFIG_XILINX_405) - bd->bi_pci_busfreq = get_PCI_freq(); -#endif -#endif - - debug("New Stack Pointer is: %08lx\n", addr_sp); - - WATCHDOG_RESET(); - - gd->relocaddr = addr; /* Store relocation addr, useful for debug */ - - memcpy(id, (void *) gd, sizeof(gd_t)); - - relocate_code(addr_sp, id, addr); - - /* NOTREACHED - relocate_code() does not return */ -} - -/* - * This is the next part if the initialization sequence: we are now - * running from RAM and have a "normal" C environment, i. e. global - * data can be written, BSS has been cleared, the stack size in not - * that critical any more, etc. - */ -void board_init_r(gd_t *id, ulong dest_addr) -{ - bd_t *bd; - ulong malloc_start; - -#ifndef CONFIG_SYS_NO_FLASH - ulong flash_size; -#endif - - gd = id; /* initialize RAM version of global data */ - bd = gd->bd; - - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - - /* The Malloc area is immediately below the monitor copy in DRAM */ - malloc_start = dest_addr - TOTAL_MALLOC_LEN; - -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) - /* - * The gd->arch.cpu pointer is set to an address in flash before - * relocation. We need to update it to point to the same CPU entry - * in RAM. - */ - gd->arch.cpu += dest_addr - CONFIG_SYS_MONITOR_BASE; - - /* - * If we didn't know the cpu mask & # cores, we can save them of - * now rather than 'computing' them constantly - */ - fixup_cpu(); -#endif - -#ifdef CONFIG_SYS_EXTRA_ENV_RELOC - /* - * Some systems need to relocate the env_addr pointer early because the - * location it points to will get invalidated before env_relocate is - * called. One example is on systems that might use a L2 or L3 cache - * in SRAM mode and initialize that cache from SRAM mode back to being - * a cache in cpu_init_r. - */ - gd->env_addr += dest_addr - CONFIG_SYS_MONITOR_BASE; -#endif - - serial_initialize(); - - debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr); - - WATCHDOG_RESET(); - - /* - * Setup trap handlers - */ - trap_init(dest_addr); - -#ifdef CONFIG_ADDR_MAP - init_addr_map(); -#endif - -#if defined(CONFIG_BOARD_EARLY_INIT_R) - board_early_init_r(); -#endif - - monitor_flash_len = (ulong)&__init_end - dest_addr; - - WATCHDOG_RESET(); - -#ifdef CONFIG_LOGBUFFER - logbuff_init_ptrs(); -#endif -#ifdef CONFIG_POST - post_output_backlog(); -#endif - - WATCHDOG_RESET(); - -#if defined(CONFIG_SYS_DELAYED_ICACHE) - icache_enable(); /* it's time to enable the instruction cache */ -#endif - -#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) - unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */ -#endif - -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT) - /* - * Do early PCI configuration _before_ the flash gets initialised, - * because PCU ressources are crucial for flash access on some boards. - */ - pci_init(); -#endif -#if defined(CONFIG_WINBOND_83C553) - /* - * Initialise the ISA bridge - */ - initialise_w83c553f(); -#endif - - asm("sync ; isync"); - - mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN); - -#if !defined(CONFIG_SYS_NO_FLASH) - puts("Flash: "); - - if (board_flash_wp_on()) { - printf("Uninitialized - Write Protect On\n"); - /* Since WP is on, we can't find real size. Set to 0 */ - flash_size = 0; - } else if ((flash_size = flash_init()) > 0) { -#ifdef CONFIG_SYS_FLASH_CHECKSUM - print_size(flash_size, ""); - /* - * Compute and print flash CRC if flashchecksum is set to 'y' - * - * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX - */ - if (getenv_yesno("flashchecksum") == 1) { - printf(" CRC: %08X", - crc32(0, - (const unsigned char *) - CONFIG_SYS_FLASH_BASE, flash_size) - ); - } - putc('\n'); -#else /* !CONFIG_SYS_FLASH_CHECKSUM */ - print_size(flash_size, "\n"); -#endif /* CONFIG_SYS_FLASH_CHECKSUM */ - } else { - puts(failed); - hang(); - } - - /* update start of FLASH memory */ - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; - /* size of FLASH memory (final value) */ - bd->bi_flashsize = flash_size; - -#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) - /* Make a update of the Memctrl. */ - update_flash_size(flash_size); -#endif - - -#if defined(CONFIG_OXC) || defined(CONFIG_RMU) - /* flash mapped at end of memory map */ - bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size; -#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE - bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */ -#endif -#endif /* !CONFIG_SYS_NO_FLASH */ - - WATCHDOG_RESET(); - - /* initialize higher level parts of CPU like time base and timers */ - cpu_init_r(); - - WATCHDOG_RESET(); - -#ifdef CONFIG_SPI -#if !defined(CONFIG_ENV_IS_IN_EEPROM) - spi_init_f(); -#endif - spi_init_r(); -#endif - -#if defined(CONFIG_CMD_NAND) - WATCHDOG_RESET(); - puts("NAND: "); - nand_init(); /* go init the NAND */ -#endif - -#ifdef CONFIG_GENERIC_MMC -/* - * MMC initialization is called before relocating env. - * Thus It is required that operations like pin multiplexer - * be put in board_init. - */ - WATCHDOG_RESET(); - puts("MMC: "); - mmc_initialize(bd); -#endif - - /* relocate environment function pointers etc. */ - env_relocate(); - - /* - * after non-volatile devices & environment is setup and cpu code have - * another round to deal with any initialization that might require - * full access to the environment or loading of some image (firmware) - * from a non-volatile device - */ - cpu_secondary_init_r(); - - /* - * Fill in missing fields of bd_info. - * We do this here, where we have "normal" access to the - * environment; we used to do this still running from ROM, - * where had to use getenv_f(), which can be pretty slow when - * the environment is in EEPROM. - */ - -#if defined(CONFIG_SYS_EXTBDINFO) -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) -#if defined(CONFIG_I2CFAST) - /* - * set bi_iic_fast for linux taking environment variable - * "i2cfast" into account - */ - { - if (getenv_yesno("i2cfast") == 1) { - bd->bi_iic_fast[0] = 1; - bd->bi_iic_fast[1] = 1; - } - } -#endif /* CONFIG_I2CFAST */ -#endif /* CONFIG_405GP, CONFIG_405EP */ -#endif /* CONFIG_SYS_EXTBDINFO */ - -#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET) - mac_read_from_eeprom(); -#endif - -#ifdef CONFIG_CMD_NET - /* kept around for legacy kernels only ... ignore the next section */ - eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr); -#ifdef CONFIG_HAS_ETH1 - eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr); -#endif -#ifdef CONFIG_HAS_ETH2 - eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr); -#endif -#ifdef CONFIG_HAS_ETH3 - eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr); -#endif -#ifdef CONFIG_HAS_ETH4 - eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr); -#endif -#ifdef CONFIG_HAS_ETH5 - eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr); -#endif -#endif /* CONFIG_CMD_NET */ - - WATCHDOG_RESET(); - -#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT) - /* - * Do pci configuration - */ - pci_init(); -#endif - -/** leave this here (after malloc(), environment and PCI are working) **/ - /* Initialize stdio devices */ - stdio_init(); - - /* Initialize the jump table for applications */ - jumptable_init(); - -#if defined(CONFIG_API) - /* Initialize API */ - api_init(); -#endif - - /* Initialize the console (after the relocation and devices init) */ - console_init_r(); - -#if defined(CONFIG_MISC_INIT_R) - /* miscellaneous platform dependent initialisations */ - misc_init_r(); -#endif - -#if defined(CONFIG_CMD_KGDB) - WATCHDOG_RESET(); - puts("KGDB: "); - kgdb_init(); -#endif - - debug("U-Boot relocated to %08lx\n", dest_addr); - - /* - * Enable Interrupts - */ - interrupt_init(); - -#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) - status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); -#endif - - udelay(20); - - /* Initialize from environment */ - load_addr = getenv_ulong("loadaddr", 16, load_addr); - - WATCHDOG_RESET(); - -#if defined(CONFIG_CMD_SCSI) - WATCHDOG_RESET(); - puts("SCSI: "); - scsi_init(); -#endif - -#if defined(CONFIG_CMD_DOC) - WATCHDOG_RESET(); - puts("DOC: "); - doc_init(); -#endif - -#ifdef CONFIG_BITBANGMII - bb_miiphy_init(); -#endif -#if defined(CONFIG_CMD_NET) - WATCHDOG_RESET(); - puts("Net: "); - eth_initialize(); -#endif - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) - WATCHDOG_RESET(); - debug("Reset Ethernet PHY\n"); - reset_phy(); -#endif - -#ifdef CONFIG_POST - post_run(NULL, POST_RAM | post_bootmode_get(0)); -#endif - -#if defined(CONFIG_CMD_PCMCIA) \ - && !defined(CONFIG_CMD_IDE) - WATCHDOG_RESET(); - puts("PCMCIA:"); - pcmcia_init(); -#endif - -#if defined(CONFIG_CMD_IDE) - WATCHDOG_RESET(); -#ifdef CONFIG_IDE_8xx_PCCARD - puts("PCMCIA:"); -#else - puts("IDE: "); -#endif -#if defined(CONFIG_START_IDE) - if (board_start_ide()) - ide_init(); -#else - ide_init(); -#endif -#endif - -#ifdef CONFIG_LAST_STAGE_INIT - WATCHDOG_RESET(); - /* - * Some parts can be only initialized if all others (like - * Interrupts) are up and running (i.e. the PC-style ISA - * keyboard). - */ - last_stage_init(); -#endif - -#if defined(CONFIG_CMD_BEDBUG) - WATCHDOG_RESET(); - bedbug_init(); -#endif - -#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) - /* - * Export available size of memory for Linux, - * taking into account the protected RAM at top of memory - */ - { - ulong pram = 0; - char memsz[32]; - -#ifdef CONFIG_PRAM - pram = getenv_ulong("pram", 10, CONFIG_PRAM); -#endif -#ifdef CONFIG_LOGBUFFER -#ifndef CONFIG_ALT_LB_ADDR - /* Also take the logbuffer into account (pram is in kB) */ - pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; -#endif -#endif - sprintf(memsz, "%ldk", (ulong) (bd->bi_memsize / 1024) - pram); - setenv("mem", memsz); - } -#endif - -#ifdef CONFIG_PS2KBD - puts("PS/2: "); - kbd_init(); -#endif - - /* Initialization complete - start the monitor */ - - /* main_loop() can return to retry autoboot, if so just run it again. */ - for (;;) { - WATCHDOG_RESET(); - main_loop(); - } - - /* NOTREACHED - no way out of command loop except booting */ -} - -#if 0 /* We could use plain global data, but the resulting code is bigger */ -/* - * Pointer to initial global data area - * - * Here we initialize it. - */ -#undef XTRN_DECLARE_GLOBAL_DATA_PTR -#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ -DECLARE_GLOBAL_DATA_PTR = - (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); -#endif /* 0 */ - -/************************************************************************/ diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index f5217fb..730de8a 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -13,6 +13,8 @@ eth5 = ð_5; i2c0 = "/i2c@0"; pci0 = &pci; + remoteproc1 = &rproc_1; + remoteproc2 = &rproc_2; rtc0 = &rtc_0; rtc1 = &rtc_1; spi0 = "/spi@0"; @@ -233,6 +235,17 @@ compatible = "sandbox,reset"; }; + rproc_1: rproc@1 { + compatible = "sandbox,test-processor"; + remoteproc-name = "remoteproc-test-dev1"; + }; + + rproc_2: rproc@2 { + compatible = "sandbox,test-processor"; + internal-memory-mapped; + remoteproc-name = "remoteproc-test-dev2"; + }; + spi@0 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5e42d7d..f92082d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -239,6 +239,14 @@ config FSP_SYS_MALLOC_F_LEN help Additional size of malloc() pool before relocation. +config ENABLE_MRC_CACHE + bool "Enable MRC cache" + depends on !EFI && !SYS_COREBOOT + help + Enable this feature to cause MRC data to be cached in NV storage + to be used for speeding up boot time on future reboots and/or + power cycles. + config SMP bool "Enable Symmetric Multiprocessing" default n @@ -358,6 +366,17 @@ config GENERATE_ACPI_TABLE by the operating system. It defines platform-independent interfaces for configuration and power management monitoring. +config GENERATE_SMBIOS_TABLE + bool "Generate an SMBIOS (System Management BIOS) table" + default y + help + The System Management BIOS (SMBIOS) specification addresses how + motherboard and system vendors present management information about + their products in a standard format by extending the BIOS interface + on Intel architecture systems. + + Check http://www.dmtf.org/standards/smbios for details. + endmenu config MAX_PIRQ_LINKS diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index 4baaae6..a009c14 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -8,6 +8,7 @@ #include <mmc.h> #include <pci_ids.h> #include <asm/irq.h> +#include <asm/mrccache.h> #include <asm/post.h> static struct pci_device_id mmc_supported[] = { @@ -43,6 +44,30 @@ int arch_misc_init(void) if (!ll_boot_init()) return 0; +#ifdef CONFIG_ENABLE_MRC_CACHE + /* + * We intend not to check any return value here, as even MRC cache + * is not saved successfully, it is not a severe error that will + * prevent system from continuing to boot. + */ + mrccache_save(); +#endif + return pirq_init(); } + +int reserve_arch(void) +{ +#ifdef CONFIG_ENABLE_MRC_CACHE + return mrccache_reserve(); +#else + return 0; +#endif +} #endif + +void reset_cpu(ulong addr) +{ + /* cold reset */ + x86_full_reset(); +} diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 1b76ca1..812c5e4 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -142,7 +142,12 @@ void arch_setup_gd(gd_t *new_gd) gdt_addr = new_gd->arch.gdt; - /* CS: code, read/execute, 4 GB, base 0 */ + /* + * CS: code, read/execute, 4 GB, base 0 + * + * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS + */ + gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff); gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); /* DS: data, read/write, 4 GB, base 0 */ diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 3576b83..0c7efae 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -14,7 +14,6 @@ obj-y += lpc.o obj-y += me_status.o obj-y += model_206ax.o obj-y += microcode_intel.o -obj-y += mrccache.o obj-y += northbridge.o obj-y += pch.o obj-y += pci.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index ca8cccf..3e7a907 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -55,38 +55,6 @@ void bd82x6x_pci_init(pci_dev_t dev) x86_pci_write_config16(dev, SECSTS, reg16); } -#define PCI_BRIDGE_UPDATE_COMMAND -void bd82x6x_pci_dev_enable_resources(pci_dev_t dev) -{ - uint16_t command; - - command = x86_pci_read_config16(dev, PCI_COMMAND); - command |= PCI_COMMAND_IO; -#ifdef PCI_BRIDGE_UPDATE_COMMAND - /* - * If we write to PCI_COMMAND, on some systems this will cause the - * ROM and APICs to become invisible. - */ - debug("%x cmd <- %02x\n", dev, command); - x86_pci_write_config16(dev, PCI_COMMAND, command); -#else - printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); -#endif -} - -void bd82x6x_pci_bus_enable_resources(pci_dev_t dev) -{ - uint16_t ctrl; - - ctrl = x86_pci_read_config16(dev, PCI_BRIDGE_CONTROL); - ctrl |= PCI_COMMAND_IO; - ctrl |= PCI_BRIDGE_CTL_VGA; - debug("%x bridge ctrl <- %04x\n", dev, ctrl); - x86_pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); - - bd82x6x_pci_dev_enable_resources(dev); -} - static int bd82x6x_probe(struct udevice *dev) { const void *blob = gd->fdt_blob; diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S index 407e451..1defabf 100644 --- a/arch/x86/cpu/ivybridge/car.S +++ b/arch/x86/cpu/ivybridge/car.S @@ -188,7 +188,7 @@ car_uninit: wrmsr /* Disable the no-eviction run state */ - movl NOEVICTMOD_MSR, %ecx + movl $NOEVICTMOD_MSR, %ecx rdmsr andl $~2, %eax wrmsr diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index cce5923..0e6512c 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -340,3 +340,10 @@ int print_cpuinfo(void) return 0; } + +void board_debug_uart_init(void) +{ + /* This enables the debug UART */ + pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, + PCI_SIZE_16); +} diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 7f3b13d..4372a5c 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -21,10 +21,10 @@ #include <asm/processor.h> #include <asm/gpio.h> #include <asm/global_data.h> +#include <asm/mrccache.h> #include <asm/mtrr.h> #include <asm/pci.h> #include <asm/arch/me.h> -#include <asm/arch/mrccache.h> #include <asm/arch/pei_data.h> #include <asm/arch/pch.h> #include <asm/post.h> @@ -89,51 +89,15 @@ void dram_init_banksize(void) } } -static int get_mrc_entry(struct udevice **devp, struct fmap_entry *entry) -{ - const void *blob = gd->fdt_blob; - int node, spi_node, mrc_node; - int upto; - int ret; - - /* Find the flash chip within the SPI controller node */ - upto = 0; - spi_node = fdtdec_next_alias(blob, "spi", COMPAT_INTEL_ICH_SPI, &upto); - if (spi_node < 0) - return -ENOENT; - node = fdt_first_subnode(blob, spi_node); - if (node < 0) - return -ECHILD; - - /* Find the place where we put the MRC cache */ - mrc_node = fdt_subnode_offset(blob, node, "rw-mrc-cache"); - if (mrc_node < 0) - return -EPERM; - - if (fdtdec_read_fmap_entry(blob, mrc_node, "rm-mrc-cache", entry)) - return -EINVAL; - - if (devp) { - debug("getting sf\n"); - ret = uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, - devp); - debug("ret = %d\n", ret); - if (ret) - return ret; - } - - return 0; -} - static int read_seed_from_cmos(struct pei_data *pei_data) { u16 c1, c2, checksum, seed_checksum; struct udevice *dev; - int rcode = 0; + int ret = 0; - rcode = uclass_get_device(UCLASS_RTC, 0, &dev); - if (rcode) { - debug("Cannot find RTC: err=%d\n", rcode); + ret = uclass_get_device(UCLASS_RTC, 0, &dev); + if (ret) { + debug("Cannot find RTC: err=%d\n", ret); return -ENODEV; } @@ -143,11 +107,18 @@ static int read_seed_from_cmos(struct pei_data *pei_data) * the flash too much. So we store these in CMOS and the large MRC * data in SPI flash. */ - rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed); + ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed); + if (!ret) { + ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3, + &pei_data->scrambler_seed_s3); + } + if (ret) { + debug("Failed to read from RTC %s\n", dev->name); + return ret; + } + debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n", pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); - - rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3, &pei_data->scrambler_seed_s3); debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); @@ -174,27 +145,21 @@ static int read_seed_from_cmos(struct pei_data *pei_data) static int prepare_mrc_cache(struct pei_data *pei_data) { struct mrc_data_container *mrc_cache; - struct fmap_entry entry; + struct mrc_region entry; int ret; ret = read_seed_from_cmos(pei_data); if (ret) return ret; - ret = get_mrc_entry(NULL, &entry); + ret = mrccache_get_region(NULL, &entry); if (ret) return ret; mrc_cache = mrccache_find_current(&entry); if (!mrc_cache) return -ENOENT; - /* - * TODO(sjg@chromium.org): Skip this for now as it causes boot - * problems - */ - if (0) { - pei_data->mrc_input = mrc_cache->data; - pei_data->mrc_input_len = mrc_cache->data_size; - } + pei_data->mrc_input = mrc_cache->data; + pei_data->mrc_input_len = mrc_cache->data_size; debug("%s: at %p, size %x checksum %04x\n", __func__, pei_data->mrc_input, pei_data->mrc_input_len, mrc_cache->checksum); @@ -202,41 +167,15 @@ static int prepare_mrc_cache(struct pei_data *pei_data) return 0; } -static int build_mrc_data(struct mrc_data_container **datap) -{ - struct mrc_data_container *data; - int orig_len; - int output_len; - - orig_len = gd->arch.mrc_output_len; - output_len = ALIGN(orig_len, 16); - data = malloc(output_len + sizeof(*data)); - if (!data) - return -ENOMEM; - data->signature = MRC_DATA_SIGNATURE; - data->data_size = output_len; - data->reserved = 0; - memcpy(data->data, gd->arch.mrc_output, orig_len); - - /* Zero the unused space in aligned buffer. */ - if (output_len > orig_len) - memset(data->data + orig_len, 0, output_len - orig_len); - - data->checksum = compute_ip_checksum(data->data, output_len); - *datap = data; - - return 0; -} - static int write_seeds_to_cmos(struct pei_data *pei_data) { u16 c1, c2, checksum; struct udevice *dev; - int rcode = 0; + int ret = 0; - rcode = uclass_get_device(UCLASS_RTC, 0, &dev); - if (rcode) { - debug("Cannot find RTC: err=%d\n", rcode); + ret = uclass_get_device(UCLASS_RTC, 0, &dev); + if (ret) { + debug("Cannot find RTC: err=%d\n", ret); return -ENODEV; } @@ -262,42 +201,12 @@ static int write_seeds_to_cmos(struct pei_data *pei_data) return 0; } -static int sdram_save_mrc_data(void) -{ - struct mrc_data_container *data; - struct fmap_entry entry; - struct udevice *sf; - int ret; - - if (!gd->arch.mrc_output_len) - return 0; - debug("Saving %d bytes of MRC output data to SPI flash\n", - gd->arch.mrc_output_len); - - ret = get_mrc_entry(&sf, &entry); - if (ret) - goto err_entry; - ret = build_mrc_data(&data); - if (ret) - goto err_data; - ret = mrccache_update(sf, &entry, data); - if (!ret) - debug("Saved MRC data with checksum %04x\n", data->checksum); - - free(data); -err_data: -err_entry: - if (ret) - debug("%s: Failed: %d\n", __func__, ret); - return ret; -} - /* Use this hook to save our SDRAM parameters */ int misc_init_r(void) { int ret; - ret = sdram_save_mrc_data(); + ret = mrccache_save(); if (ret) printf("Unable to save MRC data: %d\n", ret); @@ -421,9 +330,11 @@ int sdram_initialise(struct pei_data *pei_data) if (data) { int rv; int (*func)(struct pei_data *); + ulong start; debug("Calling MRC at %p\n", data); post_code(POST_PRE_MRC); + start = get_timer(0); func = (int (*)(struct pei_data *))data; rv = func(pei_data); post_code(POST_MRC); @@ -441,6 +352,7 @@ int sdram_initialise(struct pei_data *pei_data) printf("Nonzero MRC return value.\n"); return -EFAULT; } + debug("MRC execution time %lu ms\n", get_timer(start)); } else { printf("UEFI PEI System Agent not found.\n"); return -ENOSYS; @@ -455,7 +367,7 @@ int sdram_initialise(struct pei_data *pei_data) debug("System Agent Version %d.%d.%d Build %d\n", version >> 24 , (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff); - debug("MCR output data length %#x at %p\n", pei_data->mrc_output_len, + debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len, pei_data->mrc_output); /* @@ -476,7 +388,7 @@ int sdram_initialise(struct pei_data *pei_data) if (pei_data->boot_mode != PEI_BOOT_RESUME) { /* * This will be copied to SDRAM in reserve_arch(), then written - * to SPI flash in sdram_save_mrc_data() + * to SPI flash in mrccache_save() */ gd->arch.mrc_output = (char *)pei_data->mrc_output; gd->arch.mrc_output_len = pei_data->mrc_output_len; @@ -490,19 +402,7 @@ int sdram_initialise(struct pei_data *pei_data) int reserve_arch(void) { - u16 checksum; - - checksum = compute_ip_checksum(gd->arch.mrc_output, - gd->arch.mrc_output_len); - debug("Saving %d bytes for MRC output data, checksum %04x\n", - gd->arch.mrc_output_len, checksum); - gd->start_addr_sp -= gd->arch.mrc_output_len; - memcpy((void *)gd->start_addr_sp, gd->arch.mrc_output, - gd->arch.mrc_output_len); - gd->arch.mrc_output = (char *)gd->start_addr_sp; - gd->start_addr_sp &= ~0xf; - - return 0; + return mrccache_reserve(); } static int copy_spd(struct pei_data *peid) @@ -827,7 +727,7 @@ int dram_init(void) int ret; debug("Boot mode %d\n", gd->arch.pei_boot_mode); - debug("mcr_input %p\n", pei_data.mrc_input); + debug("mrc_input %p\n", pei_data.mrc_input); pei_data.boot_mode = gd->arch.pei_boot_mode; ret = copy_spd(&pei_data); if (!ret) diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 1b89376..40c830a 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -7,6 +7,8 @@ #include <common.h> #include <errno.h> #include <fdtdec.h> +#include <malloc.h> +#include <asm/mrccache.h> #include <asm/mtrr.h> #include <asm/post.h> #include <asm/arch/mrc.h> @@ -15,6 +17,29 @@ DECLARE_GLOBAL_DATA_PTR; +static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params) +{ + struct mrc_data_container *cache; + struct mrc_region entry; + int ret; + + ret = mrccache_get_region(NULL, &entry); + if (ret) + return ret; + + cache = mrccache_find_current(&entry); + if (!cache) + return -ENOENT; + + debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, + cache->data, cache->data_size, cache->checksum); + + /* copy mrc cache to the mrc_params */ + memcpy(&mrc_params->timings, cache->data, cache->data_size); + + return 0; +} + static int mrc_configure_params(struct mrc_params *mrc_params) { const void *blob = gd->fdt_blob; @@ -27,14 +52,15 @@ static int mrc_configure_params(struct mrc_params *mrc_params) return -EINVAL; } - /* - * TODO: - * - * We need support fast boot (MRC cache) in the future. - * - * Set boot mode to cold boot for now - */ +#ifdef CONFIG_ENABLE_MRC_CACHE + mrc_params->boot_mode = prepare_mrc_cache(mrc_params); + if (mrc_params->boot_mode) + mrc_params->boot_mode = BM_COLD; + else + mrc_params->boot_mode = BM_FAST; +#else mrc_params->boot_mode = BM_COLD; +#endif /* * TODO: @@ -98,6 +124,9 @@ static int mrc_configure_params(struct mrc_params *mrc_params) int dram_init(void) { struct mrc_params mrc_params; +#ifdef CONFIG_ENABLE_MRC_CACHE + char *cache; +#endif int ret; memset(&mrc_params, 0, sizeof(struct mrc_params)); @@ -121,6 +150,15 @@ int dram_init(void) (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID); enable_caches(); +#ifdef CONFIG_ENABLE_MRC_CACHE + cache = malloc(sizeof(struct mrc_timings)); + if (cache) { + memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings)); + gd->arch.mrc_output = cache; + gd->arch.mrc_output_len = sizeof(struct mrc_timings); + } +#endif + return 0; } diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 77d644a..f737e19 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -8,6 +8,7 @@ #include <mmc.h> #include <asm/io.h> #include <asm/irq.h> +#include <asm/mrccache.h> #include <asm/mtrr.h> #include <asm/pci.h> #include <asm/post.h> @@ -368,6 +369,15 @@ void cpu_irq_init(void) int arch_misc_init(void) { +#ifdef CONFIG_ENABLE_MRC_CACHE + /* + * We intend not to check any return value here, as even MRC cache + * is not saved successfully, it is not a severe error that will + * prevent system from continuing to boot. + */ + mrccache_save(); +#endif + return pirq_init(); } @@ -390,3 +400,12 @@ void board_final_cleanup(void) return; } + +int reserve_arch(void) +{ +#ifdef CONFIG_ENABLE_MRC_CACHE + return mrccache_reserve(); +#else + return 0; +#endif +} diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig index fbf85f2..6136d75 100644 --- a/arch/x86/cpu/queensbay/Kconfig +++ b/arch/x86/cpu/queensbay/Kconfig @@ -42,4 +42,12 @@ config CPU_ADDR_BITS int default 32 +config DISABLE_IGD + bool "Disable Integrated Graphics Device (IGD)" + help + Disable the Integrated Graphics Device (IGD) so that it does not + show in the PCI configuration space as a VGA disaplay controller. + This gives a chance for U-Boot to run PCI/PCIe based graphics + card's VGA BIOS and use that card for the graphics console. + endif diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 9682cff..0c02a44 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -23,6 +23,16 @@ static void unprotect_spi_flash(void) x86_pci_write_config32(TNC_LPC, 0xd8, bc); } +static void __maybe_unused disable_igd(void) +{ + u32 gc; + + gc = x86_pci_read_config32(TNC_IGD, IGD_GC); + gc &= ~GMS_MASK; + gc |= VGA_DISABLE; + x86_pci_write_config32(TNC_IGD, IGD_GC, gc); +} + int arch_cpu_init(void) { int ret; @@ -39,6 +49,15 @@ int arch_cpu_init(void) return 0; } +int arch_early_init_r(void) +{ +#ifdef CONFIG_DISABLE_IGD + disable_igd(); +#endif + + return 0; +} + void cpu_irq_init(void) { struct tnc_rcba *rcba; diff --git a/arch/x86/cpu/sipi_vector.S b/arch/x86/cpu/sipi_vector.S index bcef12c..0c4a157 100644 --- a/arch/x86/cpu/sipi_vector.S +++ b/arch/x86/cpu/sipi_vector.S @@ -190,8 +190,8 @@ load_msr: /* c_handler(cpu_num) */ movl %esi, %eax /* cpu_num */ - mov c_handler, %eax - call *%eax + mov c_handler, %esi + call *%esi .align 4 .globl sipi_params diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index d072825..5b4ee79 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -126,14 +126,9 @@ car_init_ret: call board_init_f_mem mov %eax, %esp - /* - * Debug UART is available here although it may not be plumbed out - * to pins depending on the board. To use it: - * - * call debug_uart_init - * mov $'a', %eax - * call printch - */ +#ifdef CONFIG_DEBUG_UART + call debug_uart_init +#endif /* Get address of global_data */ mov %fs:0, %edx diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 71595c7..83a2b8c 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -6,7 +6,8 @@ dtb-y += bayleybay.dtb \ galileo.dtb \ minnowmax.dtb \ qemu-x86_i440fx.dtb \ - qemu-x86_q35.dtb + qemu-x86_q35.dtb \ + broadwell_som-6896.dtb targets += $(dtb-y) diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index d646987..52d0999 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -68,9 +68,15 @@ #size-cells = <0>; compatible = "intel,ich-spi"; spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; compatible = "winbond,w25q64dw", "spi-flash"; memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x006e0000 0x00010000>; + }; }; }; diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts new file mode 100644 index 0000000..a6b5d0f --- /dev/null +++ b/arch/x86/dts/broadwell_som-6896.dts @@ -0,0 +1,43 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "rtc.dtsi" + +/ { + model = "Advantech SOM-6896"; + compatible = "advantech,som-6896", "intel,broadwell"; + + aliases { + spi0 = "/spi"; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 + 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + reg = <0>; + compatible = "winbond,w25q128", "spi-flash"; + memory-map = <0xff000000 0x01000000>; + }; + }; +}; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 4291141..f27263a 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -208,8 +208,6 @@ rw-mrc-cache { label = "rw-mrc-cache"; reg = <0x003e0000 0x00010000>; - type = "wiped"; - wipe-value = [ff]; }; }; }; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index c60ab71..61e8f2f 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -64,10 +64,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache"; - /* Alignment: 4k (for updating) */ reg = <0x003e0000 0x00010000>; - type = "wiped"; - wipe-value = [ff]; }; }; }; diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index a4e1676..b49b1f5 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -132,6 +132,10 @@ reg = <0>; compatible = "winbond,w25q64", "spi-flash"; memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x00010000 0x00010000>; + }; }; }; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index e917f0f..b03f987 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -273,9 +273,15 @@ #size-cells = <0>; compatible = "intel,ich-spi"; spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; compatible = "stmicro,n25q064a", "spi-flash"; memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x006f0000 0x00010000>; + }; }; }; diff --git a/arch/x86/include/asm/arch-ivybridge/mrccache.h b/arch/x86/include/asm/arch-ivybridge/mrccache.h deleted file mode 100644 index 1d50ebb..0000000 --- a/arch/x86/include/asm/arch-ivybridge/mrccache.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2014 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_MRCCACHE_H -#define _ASM_ARCH_MRCCACHE_H - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | ('C' << 16) | \ - ('D'<<24)) - -__packed struct mrc_data_container { - u32 signature; /* "MRCD" */ - u32 data_size; /* Size of the 'data' field */ - u32 checksum; /* IP style checksum */ - u32 reserved; /* For header alignment */ - u8 data[0]; /* Variable size, platform/run time dependent */ -}; - -struct fmap_entry; -struct udevice; - -/** - * mrccache_find_current() - find the latest MRC cache record - * - * This searches the MRC cache region looking for the latest record to use - * for setting up SDRAM - * - * @entry: Information about the position and size of the MRC cache - * @return pointer to latest record, or NULL if none - */ -struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); - -/** - * mrccache_update() - update the MRC cache with a new record - * - * This writes a new record to the end of the MRC cache. If the new record is - * the same as the latest record then the write is skipped - * - * @sf: SPI flash to write to - * @entry: Position and size of MRC cache in SPI flash - * @cur: Record to write - * @return 0 if updated, -EEXIST if the record is the same as the latest - * record, other error if SPI write failed - */ -int mrccache_update(struct udevice *sf, struct fmap_entry *entry, - struct mrc_data_container *cur); - -#endif diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h index ad9a6c4..2365394 100644 --- a/arch/x86/include/asm/arch-queensbay/tnc.h +++ b/arch/x86/include/asm/arch-queensbay/tnc.h @@ -7,6 +7,11 @@ #ifndef _X86_ARCH_TNC_H_ #define _X86_ARCH_TNC_H_ +/* IGD Control Register */ +#define IGD_GC 0x50 +#define VGA_DISABLE 0x00020000 +#define GMS_MASK 0x00700000 + /* Memory BAR Enable */ #define MEM_BAR_EN 0x00000001 diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h index 21bc633..351f021 100644 --- a/arch/x86/include/asm/e820.h +++ b/arch/x86/include/asm/e820.h @@ -23,4 +23,7 @@ struct e820entry { #endif /* __ASSEMBLY__ */ +/* Implementation defined function to install an e820 map */ +unsigned install_e820_map(unsigned max_entries, struct e820entry *); + #endif /* _ASM_X86_E820_H */ diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h new file mode 100644 index 0000000..e35b5ed --- /dev/null +++ b/arch/x86/include/asm/mrccache.h @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2014 Google, Inc + * Copyright (C) 2015 Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_MRCCACHE_H +#define _ASM_MRCCACHE_H + +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | \ + ('C' << 16) | ('D'<<24)) + +#define MRC_DATA_HEADER_SIZE 32 + +struct __packed mrc_data_container { + u32 signature; /* "MRCD" */ + u32 data_size; /* Size of the 'data' field */ + u32 checksum; /* IP style checksum */ + u32 reserved; /* For header alignment */ + u8 data[0]; /* Variable size, platform/run time dependent */ +}; + +struct mrc_region { + u32 base; + u32 offset; + u32 length; +}; + +struct udevice; + +/** + * mrccache_find_current() - find the latest MRC cache record + * + * This searches the MRC cache region looking for the latest record to use + * for setting up SDRAM + * + * @entry: Position and size of MRC cache in SPI flash + * @return pointer to latest record, or NULL if none + */ +struct mrc_data_container *mrccache_find_current(struct mrc_region *entry); + +/** + * mrccache_update() - update the MRC cache with a new record + * + * This writes a new record to the end of the MRC cache region. If the new + * record is the same as the latest record then the write is skipped + * + * @sf: SPI flash to write to + * @entry: Position and size of MRC cache in SPI flash + * @cur: Record to write + * @return 0 if updated, -EEXIST if the record is the same as the latest + * record, -EINVAL if the record is not valid, other error if SPI write failed + */ +int mrccache_update(struct udevice *sf, struct mrc_region *entry, + struct mrc_data_container *cur); + +/** + * mrccache_reserve() - reserve MRC data on the stack + * + * This copies MRC data pointed by gd->arch.mrc_output to a new place on the + * stack with length gd->arch.mrc_output_len, and updates gd->arch.mrc_output + * to point to the new place once the migration is done. + * + * This routine should be called by reserve_arch() before U-Boot is relocated + * when MRC cache is enabled. + * + * @return 0 always + */ +int mrccache_reserve(void); + +/** + * mrccache_get_region() - get MRC region on the SPI flash + * + * This gets MRC region whose offset and size are described in the device tree + * as a subnode to the SPI flash. If a non-NULL device pointer is supplied, + * this also probes the SPI flash device and returns its device pointer for + * the caller to use later. + * + * Be careful when calling this routine with a non-NULL device pointer: + * - driver model initialization must be complete + * - calling in the pre-relocation phase may bring some side effects during + * the SPI flash device probe (eg: for SPI controllers on a PCI bus, it + * triggers PCI bus enumeration during which insufficient memory issue + * might be exposed and it causes subsequent SPI flash probe fails). + * + * @devp: Returns pointer to the SPI flash device + * @entry: Position and size of MRC cache in SPI flash + * @return 0 if success, -ENOENT if SPI flash node does not exist in the + * device tree, -EPERM if MRC region subnode does not exist in the device + * tree, -EINVAL if MRC region properties format is incorrect, other error + * if SPI flash probe failed. + */ +int mrccache_get_region(struct udevice **devp, struct mrc_region *entry); + +/** + * mrccache_save() - save MRC data to the SPI flash + * + * This saves MRC data stored previously by gd->arch.mrc_output to a proper + * place within the MRC region on the SPI flash. + * + * @return 0 if saved to SPI flash successfully, other error if failed + */ +int mrccache_save(void); + +#endif /* _ASM_MRCCACHE_H */ diff --git a/arch/x86/include/asm/smbios.h b/arch/x86/include/asm/smbios.h new file mode 100644 index 0000000..623a703 --- /dev/null +++ b/arch/x86/include/asm/smbios.h @@ -0,0 +1,236 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * Adapted from coreboot src/include/smbios.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SMBIOS_H_ +#define _SMBIOS_H_ + +/* SMBIOS spec version implemented */ +#define SMBIOS_MAJOR_VER 3 +#define SMBIOS_MINOR_VER 0 + +/* SMBIOS structure types */ +enum { + SMBIOS_BIOS_INFORMATION = 0, + SMBIOS_SYSTEM_INFORMATION = 1, + SMBIOS_BOARD_INFORMATION = 2, + SMBIOS_SYSTEM_ENCLOSURE = 3, + SMBIOS_PROCESSOR_INFORMATION = 4, + SMBIOS_CACHE_INFORMATION = 7, + SMBIOS_SYSTEM_SLOTS = 9, + SMBIOS_PHYS_MEMORY_ARRAY = 16, + SMBIOS_MEMORY_DEVICE = 17, + SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS = 19, + SMBIOS_SYSTEM_BOOT_INFORMATION = 32, + SMBIOS_END_OF_TABLE = 127 +}; + +#define SMBIOS_INTERMEDIATE_OFFSET 16 +#define SMBIOS_STRUCT_EOS_BYTES 2 + +struct __packed smbios_entry { + u8 anchor[4]; + u8 checksum; + u8 length; + u8 major_ver; + u8 minor_ver; + u16 max_struct_size; + u8 entry_point_rev; + u8 formatted_area[5]; + u8 intermediate_anchor[5]; + u8 intermediate_checksum; + u16 struct_table_length; + u32 struct_table_address; + u16 struct_count; + u8 bcd_rev; +}; + +/* BIOS characteristics */ +#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) +#define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11) +#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16) + +#define BIOS_CHARACTERISTICS_EXT1_ACPI (1 << 0) +#define BIOS_CHARACTERISTICS_EXT2_TARGET (1 << 2) + +struct __packed smbios_type0 { + u8 type; + u8 length; + u16 handle; + u8 vendor; + u8 bios_ver; + u16 bios_start_segment; + u8 bios_release_date; + u8 bios_rom_size; + u64 bios_characteristics; + u8 bios_characteristics_ext1; + u8 bios_characteristics_ext2; + u8 bios_major_release; + u8 bios_minor_release; + u8 ec_major_release; + u8 ec_minor_release; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +struct __packed smbios_type1 { + u8 type; + u8 length; + u16 handle; + u8 manufacturer; + u8 product_name; + u8 version; + u8 serial_number; + u8 uuid[16]; + u8 wakeup_type; + u8 sku_number; + u8 family; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +#define SMBIOS_BOARD_FEATURE_HOSTING (1 << 0) +#define SMBIOS_BOARD_MOTHERBOARD 10 + +struct __packed smbios_type2 { + u8 type; + u8 length; + u16 handle; + u8 manufacturer; + u8 product_name; + u8 version; + u8 serial_number; + u8 asset_tag_number; + u8 feature_flags; + u8 chassis_location; + u16 chassis_handle; + u8 board_type; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +#define SMBIOS_ENCLOSURE_DESKTOP 3 +#define SMBIOS_STATE_SAFE 3 +#define SMBIOS_SECURITY_NONE 3 + +struct __packed smbios_type3 { + u8 type; + u8 length; + u16 handle; + u8 manufacturer; + u8 chassis_type; + u8 version; + u8 serial_number; + u8 asset_tag_number; + u8 bootup_state; + u8 power_supply_state; + u8 thermal_state; + u8 security_status; + u32 oem_defined; + u8 height; + u8 number_of_power_cords; + u8 element_count; + u8 element_record_length; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +#define SMBIOS_PROCESSOR_TYPE_CENTRAL 3 +#define SMBIOS_PROCESSOR_STATUS_ENABLED 1 +#define SMBIOS_PROCESSOR_UPGRADE_NONE 6 + +struct __packed smbios_type4 { + u8 type; + u8 length; + u16 handle; + u8 socket_designation; + u8 processor_type; + u8 processor_family; + u8 processor_manufacturer; + u32 processor_id[2]; + u8 processor_version; + u8 voltage; + u16 external_clock; + u16 max_speed; + u16 current_speed; + u8 status; + u8 processor_upgrade; + u16 l1_cache_handle; + u16 l2_cache_handle; + u16 l3_cache_handle; + u8 serial_number; + u8 asset_tag; + u8 part_number; + u8 core_count; + u8 core_enabled; + u8 thread_count; + u16 processor_characteristics; + u16 processor_family2; + u16 core_count2; + u16 core_enabled2; + u16 thread_count2; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +struct __packed smbios_type32 { + u8 type; + u8 length; + u16 handle; + u8 reserved[6]; + u8 boot_status; + u8 eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +struct __packed smbios_type127 { + u8 type; + u8 length; + u16 handle; + u8 eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +struct __packed smbios_header { + u8 type; + u8 length; + u16 handle; +}; + +/** + * fill_smbios_header() - Fill the header of an SMBIOS table + * + * This fills the header of an SMBIOS table structure. + * + * @table: start address of the structure + * @type: the type of structure + * @length: the length of the formatted area of the structure + * @handle: the structure's handle, a unique 16-bit number + */ +static inline void fill_smbios_header(void *table, int type, + int length, int handle) +{ + struct smbios_header *header = table; + + header->type = type; + header->length = length - SMBIOS_STRUCT_EOS_BYTES; + header->handle = handle; +} + +/** + * Function prototype to write a specific type of SMBIOS structure + * + * @addr: start address to write the structure + * @handle: the structure's handle, a unique 16-bit number + * @return: size of the structure + */ +typedef int (*smbios_write_type)(u32 *addr, int handle); + +/** + * write_smbios_table() - Write SMBIOS table + * + * This writes SMBIOS table at a given address. + * + * @addr: start address to write SMBIOS table + * @return: end address of SMBIOS table + */ +u32 write_smbios_table(u32 addr); + +#endif /* _SMBIOS_H_ */ diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h index bf351ed..94fa2a7 100644 --- a/arch/x86/include/asm/zimage.h +++ b/arch/x86/include/asm/zimage.h @@ -31,9 +31,6 @@ #define BZIMAGE_LOAD_ADDR 0x100000 #define ZIMAGE_LOAD_ADDR 0x10000 -/* Implementation defined function to install an e820 map. */ -unsigned install_e820_map(unsigned max_entries, struct e820entry *); - struct boot_params *load_zimage(char *image, unsigned long kernel_size, ulong *load_addressp); int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 6ecd6db..2f82a21 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -10,13 +10,14 @@ obj-y += bios_asm.o obj-y += bios_interrupts.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cmd_boot.o -obj-$(CONFIG_HAVE_FSP) += cmd_hob.o obj-$(CONFIG_EFI) += efi/ +obj-y += e820.o obj-y += gcc.o obj-y += init_helpers.o obj-y += interrupts.o obj-y += lpc-uclass.o obj-y += mpspec.o +obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o obj-y += cmd_mtrr.o obj-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o @@ -29,6 +30,7 @@ obj-y += relocate.o obj-y += physmem.o obj-$(CONFIG_X86_RAMTEST) += ramtest.o obj-y += sfi.o +obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o obj-y += string.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o obj-y += tables.o diff --git a/arch/x86/lib/cmd_hob.c b/arch/x86/lib/cmd_hob.c deleted file mode 100644 index 915746a..0000000 --- a/arch/x86/lib/cmd_hob.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <linux/compiler.h> -#include <asm/fsp/fsp_support.h> - -DECLARE_GLOBAL_DATA_PTR; - -static char *hob_type[] = { - "reserved", - "Hand-off", - "Memory Allocation", - "Resource Descriptor", - "GUID Extension", - "Firmware Volume", - "CPU", - "Memory Pool", - "reserved", - "Firmware Volume 2", - "Load PEIM Unused", - "UEFI Capsule", -}; - -int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - const struct hob_header *hdr; - uint type; - char *desc; - int i = 0; - - hdr = gd->arch.hob_list; - - printf("HOB list address: 0x%08x\n\n", (unsigned int)hdr); - - printf("No. | Address | Type | Length in Bytes\n"); - printf("----|----------|---------------------|----------------\n"); - while (!end_of_hob(hdr)) { - printf("%-3d | %08x | ", i, (unsigned int)hdr); - type = hdr->type; - if (type == HOB_TYPE_UNUSED) - desc = "*Unused*"; - else if (type == HOB_TYPE_EOH) - desc = "*END OF HOB*"; - else if (type >= 0 && type <= ARRAY_SIZE(hob_type)) - desc = hob_type[type]; - else - desc = "*Invalid Type*"; - printf("%-19s | %-15d\n", desc, hdr->len); - hdr = get_next_hob(hdr); - i++; - } - - return 0; -} - -U_BOOT_CMD( - hob, 1, 1, do_hob, - "print Firmware Support Package (FSP) Hand-Off Block information", - "" -); diff --git a/arch/x86/lib/e820.c b/arch/x86/lib/e820.c new file mode 100644 index 0000000..5babfde --- /dev/null +++ b/arch/x86/lib/e820.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/e820.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Install a default e820 table with 4 entries as follows: + * + * 0x000000-0x0a0000 Useable RAM + * 0x0a0000-0x100000 Reserved for ISA + * 0x100000-gd->ram_size Useable RAM + * CONFIG_PCIE_ECAM_BASE PCIe ECAM + */ +__weak unsigned install_e820_map(unsigned max_entries, + struct e820entry *entries) +{ + entries[0].addr = 0; + entries[0].size = ISA_START_ADDRESS; + entries[0].type = E820_RAM; + entries[1].addr = ISA_START_ADDRESS; + entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS; + entries[1].type = E820_RESERVED; + entries[2].addr = ISA_END_ADDRESS; + entries[2].size = gd->ram_size - ISA_END_ADDRESS; + entries[2].type = E820_RAM; + entries[3].addr = CONFIG_PCIE_ECAM_BASE; + entries[3].size = CONFIG_PCIE_ECAM_SIZE; + entries[3].type = E820_RESERVED; + + return 4; +} diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile index 5b12c12..3ea4880 100644 --- a/arch/x86/lib/fsp/Makefile +++ b/arch/x86/lib/fsp/Makefile @@ -4,6 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-y += cmd_fsp.o obj-y += fsp_car.o obj-y += fsp_common.o obj-y += fsp_dram.o diff --git a/arch/x86/lib/fsp/cmd_fsp.c b/arch/x86/lib/fsp/cmd_fsp.c new file mode 100644 index 0000000..4959edf --- /dev/null +++ b/arch/x86/lib/fsp/cmd_fsp.c @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2014-2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <asm/fsp/fsp_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +static char *hob_type[] = { + "reserved", + "Hand-off", + "Mem Alloc", + "Res Desc", + "GUID Ext", + "FV", + "CPU", + "Mem Pool", + "reserved", + "FV2", + "Load PEIM", + "Capsule", +}; + +static int do_hdr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct fsp_header *hdr = find_fsp_header(); + u32 img_addr = hdr->img_base; + char *sign = (char *)&hdr->sign; + int i; + + printf("FSP : binary 0x%08x, header 0x%08x\n", + CONFIG_FSP_ADDR, (int)hdr); + printf("Header : sign "); + for (i = 0; i < sizeof(hdr->sign); i++) + printf("%c", *sign++); + printf(", size %d, rev %d\n", hdr->hdr_len, hdr->hdr_rev); + printf("Image : rev %d.%d, id ", + (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff); + for (i = 0; i < ARRAY_SIZE(hdr->img_id); i++) + printf("%c", hdr->img_id[i]); + printf(", addr 0x%08x, size %d\n", img_addr, hdr->img_size); + printf("VPD : addr 0x%08x, size %d\n", + hdr->cfg_region_off + img_addr, hdr->cfg_region_size); + printf("\nNumber of APIs Supported : %d\n", hdr->api_num); + printf("\tTempRamInit : 0x%08x\n", hdr->fsp_tempram_init + img_addr); + printf("\tFspInit : 0x%08x\n", hdr->fsp_init + img_addr); + printf("\tFspNotify : 0x%08x\n", hdr->fsp_notify + img_addr); + + return 0; +} + +static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const struct hob_header *hdr; + uint type; + char *desc; + int i = 0; + + hdr = gd->arch.hob_list; + + printf("HOB list address: 0x%08x\n\n", (unsigned int)hdr); + + printf("# | Address | Type | Len | "); + printf("%42s\n", "GUID"); + printf("---|----------|-----------|------|-"); + printf("------------------------------------------\n"); + while (!end_of_hob(hdr)) { + printf("%-2d | %08x | ", i, (unsigned int)hdr); + type = hdr->type; + if (type == HOB_TYPE_UNUSED) + desc = "*Unused*"; + else if (type == HOB_TYPE_EOH) + desc = "*EOH*"; + else if (type >= 0 && type <= ARRAY_SIZE(hob_type)) + desc = hob_type[type]; + else + desc = "*Invalid*"; + printf("%-9s | %-4d | ", desc, hdr->len); + + if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC || + type == HOB_TYPE_GUID_EXT) { + struct efi_guid *guid = (struct efi_guid *)(hdr + 1); + int j; + + printf("%08x-%04x-%04x", guid->data1, + guid->data2, guid->data3); + for (j = 0; j < ARRAY_SIZE(guid->data4); j++) + printf("-%02x", guid->data4[j]); + } else { + printf("%42s", "Not Available"); + } + printf("\n"); + hdr = get_next_hob(hdr); + i++; + } + + return 0; +} + +static cmd_tbl_t fsp_commands[] = { + U_BOOT_CMD_MKENT(hdr, 0, 1, do_hdr, "", ""), + U_BOOT_CMD_MKENT(hob, 0, 1, do_hob, "", ""), +}; + +static int do_fsp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cmd_tbl_t *fsp_cmd; + int ret; + + if (argc < 2) + return CMD_RET_USAGE; + fsp_cmd = find_cmd_tbl(argv[1], fsp_commands, ARRAY_SIZE(fsp_commands)); + argc -= 2; + argv += 2; + if (!fsp_cmd || argc > fsp_cmd->maxargs) + return CMD_RET_USAGE; + + ret = fsp_cmd->cmd(fsp_cmd, flag, argc, argv); + + return cmd_process_error(fsp_cmd, ret); +} + +U_BOOT_CMD( + fsp, 2, 1, do_fsp, + "Show Intel Firmware Support Package (FSP) related information", + "hdr - Print FSP header information\n" + "fsp hob - Print FSP Hand-Off Block (HOB) information" +); diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 658f32d..c78df94 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -7,6 +7,7 @@ #include <common.h> #include <errno.h> #include <asm/io.h> +#include <asm/mrccache.h> #include <asm/post.h> #include <asm/processor.h> #include <asm/fsp/fsp_support.h> @@ -54,15 +55,42 @@ void board_final_cleanup(void) return; } +static __maybe_unused void *fsp_prepare_mrc_cache(void) +{ + struct mrc_data_container *cache; + struct mrc_region entry; + int ret; + + ret = mrccache_get_region(NULL, &entry); + if (ret) + return NULL; + + cache = mrccache_find_current(&entry); + if (!cache) + return NULL; + + debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, + cache->data, cache->data_size, cache->checksum); + + return cache->data; +} + int x86_fsp_init(void) { + void *nvs; + if (!gd->arch.hob_list) { +#ifdef CONFIG_ENABLE_MRC_CACHE + nvs = fsp_prepare_mrc_cache(); +#else + nvs = NULL; +#endif /* * The first time we enter here, call fsp_init(). * Note the execution does not return to this function, * instead it jumps to fsp_continue(). */ - fsp_init(CONFIG_FSP_TEMP_RAM_ADDR, BOOT_FULL_CONFIG, NULL); + fsp_init(CONFIG_FSP_TEMP_RAM_ADDR, BOOT_FULL_CONFIG, nvs); } else { /* * The second time we enter here, adjust the size of malloc() diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index e51ca96..fcfe693 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -7,6 +7,7 @@ #include <common.h> #include <asm/fsp/fsp_support.h> #include <asm/e820.h> +#include <asm/mrccache.h> #include <asm/post.h> DECLARE_GLOBAL_DATA_PTR; @@ -32,6 +33,11 @@ int dram_init(void) gd->ram_size = ram_size; post_code(POST_DRAM); +#ifdef CONFIG_ENABLE_MRC_CACHE + gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list, + &gd->arch.mrc_output_len); +#endif + return 0; } diff --git a/arch/x86/cpu/ivybridge/mrccache.c b/arch/x86/lib/mrccache.c index 9205494..53a1259 100644 --- a/arch/x86/cpu/ivybridge/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -1,32 +1,37 @@ /* - * From Coreboot src/southbridge/intel/bd82x6x/mrccache.c + * From coreboot src/southbridge/intel/bd82x6x/mrccache.c * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Bin Meng <bmeng.cn@gmail.com> * * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> +#include <dm.h> #include <errno.h> #include <fdtdec.h> #include <net.h> #include <spi.h> #include <spi_flash.h> -#include <asm/arch/mrccache.h> -#include <asm/arch/sandybridge.h> +#include <asm/mrccache.h> + +DECLARE_GLOBAL_DATA_PTR; static struct mrc_data_container *next_mrc_block( - struct mrc_data_container *mrc_cache) + struct mrc_data_container *cache) { /* MRC data blocks are aligned within the region */ - u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->data_size; + u32 mrc_size = sizeof(*cache) + cache->data_size; + u8 *region_ptr = (u8 *)cache; + if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { mrc_size &= ~(MRC_DATA_ALIGN - 1UL); mrc_size += MRC_DATA_ALIGN; } - u8 *region_ptr = (u8 *)mrc_cache; region_ptr += mrc_size; + return (struct mrc_data_container *)region_ptr; } @@ -35,17 +40,13 @@ static int is_mrc_cache(struct mrc_data_container *cache) return cache && (cache->signature == MRC_DATA_SIGNATURE); } -/* - * Find the largest index block in the MRC cache. Return NULL if none is - * found. - */ -struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry) +struct mrc_data_container *mrccache_find_current(struct mrc_region *entry) { struct mrc_data_container *cache, *next; ulong base_addr, end_addr; uint id; - base_addr = (1ULL << 32) - CONFIG_ROM_SIZE + entry->offset; + base_addr = entry->base + entry->offset; end_addr = base_addr + entry->length; cache = NULL; @@ -84,12 +85,12 @@ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry) * * @return next cache entry if found, NULL if we got to the end */ -static struct mrc_data_container *find_next_mrc_cache(struct fmap_entry *entry, +static struct mrc_data_container *find_next_mrc_cache(struct mrc_region *entry, struct mrc_data_container *cache) { ulong base_addr, end_addr; - base_addr = (1ULL << 32) - CONFIG_ROM_SIZE + entry->offset; + base_addr = entry->base + entry->offset; end_addr = base_addr + entry->length; cache = next_mrc_block(cache); @@ -105,7 +106,7 @@ static struct mrc_data_container *find_next_mrc_cache(struct fmap_entry *entry, return cache; } -int mrccache_update(struct udevice *sf, struct fmap_entry *entry, +int mrccache_update(struct udevice *sf, struct mrc_region *entry, struct mrc_data_container *cur) { struct mrc_data_container *cache; @@ -113,8 +114,11 @@ int mrccache_update(struct udevice *sf, struct fmap_entry *entry, ulong base_addr; int ret; + if (!is_mrc_cache(cur)) + return -EINVAL; + /* Find the last used block */ - base_addr = (1ULL << 32) - CONFIG_ROM_SIZE + entry->offset; + base_addr = entry->base + entry->offset; debug("Updating MRC cache data\n"); cache = mrccache_find_current(entry); if (cache && (cache->data_size == cur->data_size) && @@ -155,3 +159,95 @@ int mrccache_update(struct udevice *sf, struct fmap_entry *entry, return 0; } + +int mrccache_reserve(void) +{ + struct mrc_data_container *cache; + u16 checksum; + + if (!gd->arch.mrc_output_len) + return 0; + + /* adjust stack pointer to store pure cache data plus the header */ + gd->start_addr_sp -= (gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE); + cache = (struct mrc_data_container *)gd->start_addr_sp; + + cache->signature = MRC_DATA_SIGNATURE; + cache->data_size = gd->arch.mrc_output_len; + checksum = compute_ip_checksum(gd->arch.mrc_output, cache->data_size); + debug("Saving %d bytes for MRC output data, checksum %04x\n", + cache->data_size, checksum); + cache->checksum = checksum; + cache->reserved = 0; + memcpy(cache->data, gd->arch.mrc_output, cache->data_size); + + /* gd->arch.mrc_output now points to the container */ + gd->arch.mrc_output = (char *)cache; + + gd->start_addr_sp &= ~0xf; + + return 0; +} + +int mrccache_get_region(struct udevice **devp, struct mrc_region *entry) +{ + const void *blob = gd->fdt_blob; + int node, mrc_node; + u32 reg[2]; + int ret; + + /* Find the flash chip within the SPI controller node */ + node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); + if (node < 0) + return -ENOENT; + + if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2)) + return -FDT_ERR_NOTFOUND; + entry->base = reg[0]; + + /* Find the place where we put the MRC cache */ + mrc_node = fdt_subnode_offset(blob, node, "rw-mrc-cache"); + if (mrc_node < 0) + return -EPERM; + + if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2)) + return -FDT_ERR_NOTFOUND; + entry->offset = reg[0]; + entry->length = reg[1]; + + if (devp) { + ret = uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, + devp); + debug("ret = %d\n", ret); + if (ret) + return ret; + } + + return 0; +} + +int mrccache_save(void) +{ + struct mrc_data_container *data; + struct mrc_region entry; + struct udevice *sf; + int ret; + + if (!gd->arch.mrc_output_len) + return 0; + debug("Saving %d bytes of MRC output data to SPI flash\n", + gd->arch.mrc_output_len); + + ret = mrccache_get_region(&sf, &entry); + if (ret) + goto err_entry; + data = (struct mrc_data_container *)gd->arch.mrc_output; + ret = mrccache_update(sf, &entry, data); + if (!ret) + debug("Saved MRC data with checksum %04x\n", data->checksum); + +err_entry: + if (ret) + debug("%s: Failed: %d\n", __func__, ret); + return ret; +} diff --git a/arch/x86/lib/smbios.c b/arch/x86/lib/smbios.c new file mode 100644 index 0000000..441fca9 --- /dev/null +++ b/arch/x86/lib/smbios.c @@ -0,0 +1,269 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * Adapted from coreboot src/arch/x86/smbios.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <version.h> +#include <asm/cpu.h> +#include <asm/smbios.h> +#include <asm/tables.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * smbios_add_string() - add a string to the string area + * + * This adds a string to the string area which is appended directly after + * the formatted portion of an SMBIOS structure. + * + * @start: string area start address + * @str: string to add + * @return: string number in the string area + */ +static int smbios_add_string(char *start, const char *str) +{ + int i = 1; + char *p = start; + + for (;;) { + if (!*p) { + strcpy(p, str); + p += strlen(str); + *p++ = '\0'; + *p++ = '\0'; + + return i; + } + + if (!strcmp(p, str)) + return i; + + p += strlen(p) + 1; + i++; + } +} + +/** + * smbios_string_table_len() - compute the string area size + * + * This computes the size of the string area including the string terminator. + * + * @start: string area start address + * @return: string area size + */ +static int smbios_string_table_len(char *start) +{ + char *p = start; + int i, len = 0; + + while (*p) { + i = strlen(p) + 1; + p += i; + len += i; + } + + return len + 1; +} + +static int smbios_write_type0(u32 *current, int handle) +{ + struct smbios_type0 *t = (struct smbios_type0 *)*current; + int len = sizeof(struct smbios_type0); + + memset(t, 0, sizeof(struct smbios_type0)); + fill_smbios_header(t, SMBIOS_BIOS_INFORMATION, len, handle); + t->vendor = smbios_add_string(t->eos, "U-Boot"); + t->bios_ver = smbios_add_string(t->eos, PLAIN_VERSION); + t->bios_release_date = smbios_add_string(t->eos, U_BOOT_DMI_DATE); + t->bios_rom_size = (CONFIG_ROM_SIZE / 65536) - 1; + t->bios_characteristics = BIOS_CHARACTERISTICS_PCI_SUPPORTED | + BIOS_CHARACTERISTICS_SELECTABLE_BOOT | + BIOS_CHARACTERISTICS_UPGRADEABLE; +#ifdef CONFIG_GENERATE_ACPI_TABLE + t->bios_characteristics_ext1 = BIOS_CHARACTERISTICS_EXT1_ACPI; +#endif + t->bios_characteristics_ext2 = BIOS_CHARACTERISTICS_EXT2_TARGET; + t->bios_major_release = 0xff; + t->bios_minor_release = 0xff; + t->ec_major_release = 0xff; + t->ec_minor_release = 0xff; + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + + return len; +} + +static int smbios_write_type1(u32 *current, int handle) +{ + struct smbios_type1 *t = (struct smbios_type1 *)*current; + int len = sizeof(struct smbios_type1); + + memset(t, 0, sizeof(struct smbios_type1)); + fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle); + t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR); + t->product_name = smbios_add_string(t->eos, CONFIG_SYS_BOARD); + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + + return len; +} + +static int smbios_write_type2(u32 *current, int handle) +{ + struct smbios_type2 *t = (struct smbios_type2 *)*current; + int len = sizeof(struct smbios_type2); + + memset(t, 0, sizeof(struct smbios_type2)); + fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle); + t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR); + t->product_name = smbios_add_string(t->eos, CONFIG_SYS_BOARD); + t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING; + t->board_type = SMBIOS_BOARD_MOTHERBOARD; + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + + return len; +} + +static int smbios_write_type3(u32 *current, int handle) +{ + struct smbios_type3 *t = (struct smbios_type3 *)*current; + int len = sizeof(struct smbios_type3); + + memset(t, 0, sizeof(struct smbios_type3)); + fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle); + t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR); + t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP; + t->bootup_state = SMBIOS_STATE_SAFE; + t->power_supply_state = SMBIOS_STATE_SAFE; + t->thermal_state = SMBIOS_STATE_SAFE; + t->security_status = SMBIOS_SECURITY_NONE; + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + + return len; +} + +static int smbios_write_type4(u32 *current, int handle) +{ + struct smbios_type4 *t = (struct smbios_type4 *)*current; + int len = sizeof(struct smbios_type4); + const char *vendor; + char *name; + char processor_name[CPU_MAX_NAME_LEN]; + struct cpuid_result res; + + memset(t, 0, sizeof(struct smbios_type4)); + fill_smbios_header(t, SMBIOS_PROCESSOR_INFORMATION, len, handle); + t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL; + t->processor_family = gd->arch.x86; + vendor = cpu_vendor_name(gd->arch.x86_vendor); + t->processor_manufacturer = smbios_add_string(t->eos, vendor); + res = cpuid(1); + t->processor_id[0] = res.eax; + t->processor_id[1] = res.edx; + name = cpu_get_name(processor_name); + t->processor_version = smbios_add_string(t->eos, name); + t->status = SMBIOS_PROCESSOR_STATUS_ENABLED; + t->processor_upgrade = SMBIOS_PROCESSOR_UPGRADE_NONE; + t->l1_cache_handle = 0xffff; + t->l2_cache_handle = 0xffff; + t->l3_cache_handle = 0xffff; + t->processor_family2 = t->processor_family; + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + + return len; +} + +static int smbios_write_type32(u32 *current, int handle) +{ + struct smbios_type32 *t = (struct smbios_type32 *)*current; + int len = sizeof(struct smbios_type32); + + memset(t, 0, sizeof(struct smbios_type32)); + fill_smbios_header(t, SMBIOS_SYSTEM_BOOT_INFORMATION, len, handle); + + *current += len; + + return len; +} + +static int smbios_write_type127(u32 *current, int handle) +{ + struct smbios_type127 *t = (struct smbios_type127 *)*current; + int len = sizeof(struct smbios_type127); + + memset(t, 0, sizeof(struct smbios_type127)); + fill_smbios_header(t, SMBIOS_END_OF_TABLE, len, handle); + + *current += len; + + return len; +} + +static smbios_write_type smbios_write_funcs[] = { + smbios_write_type0, + smbios_write_type1, + smbios_write_type2, + smbios_write_type3, + smbios_write_type4, + smbios_write_type32, + smbios_write_type127 +}; + +u32 write_smbios_table(u32 addr) +{ + struct smbios_entry *se; + u32 tables; + int len = 0; + int max_struct_size = 0; + int handle = 0; + char *istart; + int isize; + int i; + + /* 16 byte align the table address */ + addr = ALIGN(addr, 16); + + se = (struct smbios_entry *)addr; + memset(se, 0, sizeof(struct smbios_entry)); + + addr += sizeof(struct smbios_entry); + addr = ALIGN(addr, 16); + tables = addr; + + /* populate minimum required tables */ + for (i = 0; i < ARRAY_SIZE(smbios_write_funcs); i++) { + int tmp = smbios_write_funcs[i](&addr, handle++); + max_struct_size = max(max_struct_size, tmp); + len += tmp; + } + + memcpy(se->anchor, "_SM_", 4); + se->length = sizeof(struct smbios_entry); + se->major_ver = SMBIOS_MAJOR_VER; + se->minor_ver = SMBIOS_MINOR_VER; + se->max_struct_size = max_struct_size; + memcpy(se->intermediate_anchor, "_DMI_", 5); + se->struct_table_length = len; + se->struct_table_address = tables; + se->struct_count = handle; + + /* calculate checksums */ + istart = (char *)se + SMBIOS_INTERMEDIATE_OFFSET; + isize = sizeof(struct smbios_entry) - SMBIOS_INTERMEDIATE_OFFSET; + se->intermediate_checksum = table_compute_checksum(istart, isize); + se->checksum = table_compute_checksum(se, sizeof(struct smbios_entry)); + + return addr; +} diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index f15b2e2..14b15cf 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -7,6 +7,7 @@ #include <common.h> #include <asm/sfi.h> #include <asm/mpspec.h> +#include <asm/smbios.h> #include <asm/tables.h> #include <asm/acpi_table.h> @@ -56,4 +57,8 @@ void write_tables(void) rom_table_end = write_acpi_tables(rom_table_end); rom_table_end = ALIGN(rom_table_end, 1024); #endif +#ifdef CONFIG_GENERATE_SMBIOS_TABLE + rom_table_end = write_smbios_table(rom_table_end); + rom_table_end = ALIGN(rom_table_end, 1024); +#endif } diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index a1ec57e..1b33c77 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -42,32 +42,6 @@ DECLARE_GLOBAL_DATA_PTR; #define COMMAND_LINE_SIZE 2048 -/* - * Install a default e820 table with 3 entries as follows: - * - * 0x000000-0x0a0000 Useable RAM - * 0x0a0000-0x100000 Reserved for ISA - * 0x100000-gd->ram_size Useable RAM - */ -__weak unsigned install_e820_map(unsigned max_entries, - struct e820entry *entries) -{ - entries[0].addr = 0; - entries[0].size = ISA_START_ADDRESS; - entries[0].type = E820_RAM; - entries[1].addr = ISA_START_ADDRESS; - entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS; - entries[1].type = E820_RESERVED; - entries[2].addr = ISA_END_ADDRESS; - entries[2].size = gd->ram_size - ISA_END_ADDRESS; - entries[2].type = E820_RAM; - entries[3].addr = CONFIG_PCIE_ECAM_BASE; - entries[3].size = CONFIG_PCIE_ECAM_SIZE; - entries[3].type = E820_RESERVED; - - return 4; -} - static void build_command_line(char *command_line, int auto_boot) { char *env_command_line; diff --git a/board/LaCie/net2big_v2/MAINTAINERS b/board/LaCie/net2big_v2/MAINTAINERS index 205c75e..8fec703 100644 --- a/board/LaCie/net2big_v2/MAINTAINERS +++ b/board/LaCie/net2big_v2/MAINTAINERS @@ -1,11 +1,7 @@ NET2BIG_V2 BOARD -#M: - +M: Simon Guinot <simon.guinot@sequanux.org> S: Maintained F: board/LaCie/net2big_v2/ F: include/configs/lacie_kw.h F: configs/d2net_v2_defconfig - -NET2BIG_V2 BOARD -M: Simon Guinot <simon.guinot@sequanux.org> -S: Maintained F: configs/net2big_v2_defconfig diff --git a/board/Marvell/db-88f6820-gp/Kconfig b/board/Marvell/db-88f6820-gp/Kconfig index b2e9115..f12b968 100644 --- a/board/Marvell/db-88f6820-gp/Kconfig +++ b/board/Marvell/db-88f6820-gp/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "Marvell" -config SYS_SOC - default "mvebu" - config SYS_CONFIG_NAME default "db-88f6820-gp" diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig index d0b426e..428a5e1 100644 --- a/board/Marvell/db-mv784mp-gp/Kconfig +++ b/board/Marvell/db-mv784mp-gp/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "Marvell" -config SYS_SOC - default "mvebu" - config SYS_CONFIG_NAME default "db-mv784mp-gp" diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile index e009141..a35db40 100644 --- a/board/armltd/vexpress64/Makefile +++ b/board/armltd/vexpress64/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := vexpress64.o +obj-y := vexpress64.o pcie.o diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c new file mode 100644 index 0000000..7b999e8 --- /dev/null +++ b/board/armltd/vexpress64/pcie.c @@ -0,0 +1,197 @@ +/* + * Copyright (C) ARM Ltd 2015 + * + * Author: Liviu Dudau <Liviu.Dudau@arm.com> + * + * SPDX-Licence-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <pci_ids.h> +#include "pcie.h" + +/* XpressRICH3 support */ +#define XR3_CONFIG_BASE 0x7ff30000 +#define XR3_RESET_BASE 0x7ff20000 + +#define XR3_PCI_ECAM_START 0x40000000 +#define XR3_PCI_ECAM_SIZE 28 /* as power of 2 = 0x10000000 */ +#define XR3_PCI_IOSPACE_START 0x5f800000 +#define XR3_PCI_IOSPACE_SIZE 23 /* as power of 2 = 0x800000 */ +#define XR3_PCI_MEMSPACE_START 0x50000000 +#define XR3_PCI_MEMSPACE_SIZE 27 /* as power of 2 = 0x8000000 */ +#define XR3_PCI_MEMSPACE64_START 0x4000000000 +#define XR3_PCI_MEMSPACE64_SIZE 33 /* as power of 2 = 0x200000000 */ + +#define JUNO_V2M_MSI_START 0x2c1c0000 +#define JUNO_V2M_MSI_SIZE 12 /* as power of 2 = 4096 */ + +#define XR3PCI_BASIC_STATUS 0x18 +#define XR3PCI_BS_GEN_MASK (0xf << 8) +#define XR3PCI_BS_LINK_MASK 0xff + +#define XR3PCI_VIRTCHAN_CREDITS 0x90 +#define XR3PCI_BRIDGE_PCI_IDS 0x9c +#define XR3PCI_PEX_SPC2 0xd8 + +#define XR3PCI_ATR_PCIE_WIN0 0x600 +#define XR3PCI_ATR_PCIE_WIN1 0x700 +#define XR3PCI_ATR_AXI4_SLV0 0x800 + +#define XR3PCI_ATR_TABLE_SIZE 0x20 +#define XR3PCI_ATR_SRC_ADDR_LOW 0x0 +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4 +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8 +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc +#define XR3PCI_ATR_TRSL_PARAM 0x10 + +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */ +#define XR3PCI_ATR_TRSLID_AXIDEVICE (0x420004) +#define XR3PCI_ATR_TRSLID_AXIMEMORY (0x4e0004) /* Write-through, read/write allocate */ +#define XR3PCI_ATR_TRSLID_PCIE_CONF (0x000001) +#define XR3PCI_ATR_TRSLID_PCIE_IO (0x020000) +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY (0x000000) + +#define XR3PCI_ECAM_OFFSET(b, d, o) (((b) << 20) | \ + (PCI_SLOT(d) << 15) | \ + (PCI_FUNC(d) << 12) | o) + +#define JUNO_RESET_CTRL 0x1004 +#define JUNO_RESET_CTRL_PHY BIT(0) +#define JUNO_RESET_CTRL_RC BIT(1) + +#define JUNO_RESET_STATUS 0x1008 +#define JUNO_RESET_STATUS_PLL BIT(0) +#define JUNO_RESET_STATUS_PHY BIT(1) +#define JUNO_RESET_STATUS_RC BIT(2) +#define JUNO_RESET_STATUS_MASK (JUNO_RESET_STATUS_PLL | \ + JUNO_RESET_STATUS_PHY | \ + JUNO_RESET_STATUS_RC) + +void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, + unsigned long trsl_addr, int window_size, + int trsl_param) +{ + /* X3PCI_ATR_SRC_ADDR_LOW: + - bit 0: enable entry, + - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1) + - bits 7-11: reserved + - bits 12-31: start of source address + */ + writel((u32)(src_addr & 0xfffff000) | (window_size - 1) << 1 | 1, + base + XR3PCI_ATR_SRC_ADDR_LOW); + writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH); + writel((u32)(trsl_addr & 0xfffff000), base + XR3PCI_ATR_TRSL_ADDR_LOW); + writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH); + writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM); + + printf("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n", + src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr, + ((u64)1) << window_size, trsl_param); +} + +void xr3pci_setup_atr(void) +{ + /* setup PCIe to CPU address translation tables */ + unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0; + + /* forward all writes from PCIe to GIC V2M (used for MSI) */ + xr3pci_set_atr_entry(base, JUNO_V2M_MSI_START, JUNO_V2M_MSI_START, + JUNO_V2M_MSI_SIZE, XR3PCI_ATR_TRSLID_AXIDEVICE); + + base += XR3PCI_ATR_TABLE_SIZE; + + /* PCIe devices can write anywhere in memory */ + xr3pci_set_atr_entry(base, PHYS_SDRAM_1, PHYS_SDRAM_1, + 31 /* grant access to all RAM under 4GB */, + XR3PCI_ATR_TRSLID_AXIMEMORY); + base += XR3PCI_ATR_TABLE_SIZE; + xr3pci_set_atr_entry(base, PHYS_SDRAM_2, PHYS_SDRAM_2, + XR3_PCI_MEMSPACE64_SIZE, + XR3PCI_ATR_TRSLID_AXIMEMORY); + + + /* setup CPU to PCIe address translation table */ + base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0; + + /* setup ECAM space to bus configuration interface */ + xr3pci_set_atr_entry(base, XR3_PCI_ECAM_START, 0, XR3_PCI_ECAM_SIZE, + XR3PCI_ATR_TRSLID_PCIE_CONF); + + base += XR3PCI_ATR_TABLE_SIZE; + + /* setup IO space translation */ + xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, XR3_PCI_IOSPACE_START, + XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO); + + base += XR3PCI_ATR_TABLE_SIZE; + + /* setup 32bit MEM space translation */ + xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE_START, XR3_PCI_MEMSPACE_START, + XR3_PCI_MEMSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY); + + base += XR3PCI_ATR_TABLE_SIZE; + + /* setup 64bit MEM space translation */ + xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE64_START, XR3_PCI_MEMSPACE64_START, + XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY); +} + +void xr3pci_init(void) +{ + u32 val; + int timeout = 200; + + /* Initialise the XpressRICH3 PCIe host bridge */ + + /* add credits */ + writel(0x00f0b818, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS); + writel(0x1, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS + 4); + /* allow ECRC */ + writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2); + /* setup the correct class code for the host bridge */ + writel(PCI_CLASS_BRIDGE_PCI << 16, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS); + + /* reset phy and root complex */ + writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC, + XR3_RESET_BASE + JUNO_RESET_CTRL); + + do { + mdelay(1); + val = readl(XR3_RESET_BASE + JUNO_RESET_STATUS); + } while (--timeout && + (val & JUNO_RESET_STATUS_MASK) != JUNO_RESET_STATUS_MASK); + + if (!timeout) { + printf("PCI XR3 Root complex reset timed out\n"); + return; + } + + /* Wait for the link to train */ + mdelay(20); + timeout = 20; + + do { + mdelay(1); + val = readl(XR3_CONFIG_BASE + XR3PCI_BASIC_STATUS); + } while (--timeout && !(val & XR3PCI_BS_LINK_MASK)); + + if (!(val & XR3PCI_BS_LINK_MASK)) { + printf("Failed to negotiate a link!\n"); + return; + } + + printf("PCIe XR3 Host Bridge enabled: x%d link (Gen %d)\n", + val & XR3PCI_BS_LINK_MASK, (val & XR3PCI_BS_GEN_MASK) >> 8); + + xr3pci_setup_atr(); +} + +void vexpress64_pcie_init(void) +{ +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO + xr3pci_init(); +#endif +} diff --git a/board/armltd/vexpress64/pcie.h b/board/armltd/vexpress64/pcie.h new file mode 100644 index 0000000..14642f4 --- /dev/null +++ b/board/armltd/vexpress64/pcie.h @@ -0,0 +1,6 @@ +#ifndef __VEXPRESS64_PCIE_H__ +#define __VEXPRESS64_PCIE_H__ + +void vexpress64_pcie_init(void); + +#endif /* __VEXPRESS64_PCIE_H__ */ diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 7cb4e00..f4e8084 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -13,6 +13,7 @@ #include <linux/compiler.h> #include <dm/platdata.h> #include <dm/platform_data/serial_pl01x.h> +#include "pcie.h" DECLARE_GLOBAL_DATA_PTR; @@ -29,6 +30,7 @@ U_BOOT_DEVICE(vexpress_serials) = { int board_init(void) { + vexpress64_pcie_init(); return 0; } @@ -38,6 +40,14 @@ int dram_init(void) return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +} + /* * Board specific reset that is system reset. */ diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 8f17b97..ccefc40 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -110,7 +110,7 @@ u32 get_board_rev(void) int misc_init_r(void) { cl_print_pcb_info(); - dieid_num_r(); + omap_die_id_display(); return 0; } diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c index b33522e..d1c74db 100644 --- a/board/compulab/cm_t3517/cm_t3517.c +++ b/board/compulab/cm_t3517/cm_t3517.c @@ -101,7 +101,7 @@ int board_init(void) int misc_init_r(void) { cl_print_pcb_info(); - dieid_num_r(); + omap_die_id_display(); return 0; } diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index 0fddf45..0009452 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -124,7 +124,7 @@ int misc_init_r(void) status_led_set(1, STATUS_LED_ON); status_led_set(2, STATUS_LED_ON); - dieid_num_r(); + omap_die_id_display(); return 0; } diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 6eb191c..044c6d5 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -171,7 +171,7 @@ int misc_init_r(void) setup_net_chip(); - dieid_num_r(); + omap_die_id_display(); set_fdt(); diff --git a/board/lge/sniper/sniper.c b/board/lge/sniper/sniper.c index a43f640..4eff01a 100644 --- a/board/lge/sniper/sniper.c +++ b/board/lge/sniper/sniper.c @@ -92,9 +92,7 @@ int board_init(void) int misc_init_r(void) { unsigned char keypad_matrix[64] = { 0 }; - char serial_string[17] = { 0 }; char reboot_mode[2] = { 0 }; - u32 dieid[4] = { 0 }; unsigned char keys[3]; unsigned char data = 0; @@ -140,14 +138,7 @@ int misc_init_r(void) /* Serial number */ - get_dieid((u32 *)&dieid); - - if (!getenv("serial#")) { - snprintf(serial_string, sizeof(serial_string), - "%08x%08x", dieid[0], dieid[3]); - - setenv("serial#", serial_string); - } + omap_die_id_serial(); /* MUSB */ @@ -158,20 +149,7 @@ int misc_init_r(void) void get_board_serial(struct tag_serialnr *serialnr) { - char *serial_string; - unsigned long long serial; - - serial_string = getenv("serial#"); - - if (serial_string) { - serial = simple_strtoull(serial_string, NULL, 16); - - serialnr->high = (unsigned int) (serial >> 32); - serialnr->low = (unsigned int) (serial & 0xffffffff); - } else { - serialnr->high = 0; - serialnr->low = 0; - } + omap_die_id_get_board_serial(serialnr); } void reset_misc(void) diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 24ff9c3..1f1e5ae 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -109,7 +109,7 @@ int misc_init_r(void) i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif - dieid_num_r(); + omap_die_id_display(); am3517_evm_musb_init(); diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index d39203a..0a3b55b 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -80,7 +80,7 @@ int misc_init_r(void) { twl4030_power_init(); twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); - dieid_num_r(); + omap_die_id_display(); /* * Board Reset diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig index e86aa16..2edccfe 100644 --- a/board/maxbcm/Kconfig +++ b/board/maxbcm/Kconfig @@ -3,9 +3,6 @@ if TARGET_MAXBCM config SYS_BOARD default "maxbcm" -config SYS_SOC - default "mvebu" - config SYS_CONFIG_NAME default "maxbcm" diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index 3d019b0..6a4427a 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -421,7 +421,7 @@ int misc_init_r(void) /* reuse atags from previous bootloader */ reuse_atags(); - dieid_num_r(); + omap_die_id_display(); print_cpuinfo(); /* diff --git a/board/overo/overo.c b/board/overo/overo.c index 34bf265..20cbec2 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -285,7 +285,7 @@ int misc_init_r(void) if (expansion_config.content == 1) setenv(expansion_config.env_var, expansion_config.env_setting); - dieid_num_r(); + omap_die_id_display(); if (get_cpu_family() == CPU_OMAP34XX) setenv("boardname", "overo"); diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index 59b5a7e..b371a40 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -102,7 +102,7 @@ int misc_init_r(void) TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV | TWL4030_BB_CFG_BBISEL_500UA); - dieid_num_r(); + omap_die_id_display(); return 0; } diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 6d7be11..942badb 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -176,6 +176,11 @@ static const struct { "bcm2835-rpi-cm.dtb", false, }, + [BCM2835_BOARD_REV_A_PLUS_15] = { + "Model A+", + "bcm2835-rpi-a-plus.dtb", + false, + }, #endif }; diff --git a/board/sbc8641d/README b/board/sbc8641d/README index a051466..d07f1cc 100644 --- a/board/sbc8641d/README +++ b/board/sbc8641d/README @@ -3,7 +3,7 @@ Wind River SBC8641D reference board Created 06/14/2007 Joe Hamman Copyright 2007, Embedded Specialties, Inc. -Copyright 2007 Wind River Systemes, Inc. +Copyright 2007 Wind River Systems, Inc. ----------------------------- 1. Building U-Boot @@ -26,3 +26,24 @@ and settings may change with board revisions. -------------------- PCI: The PCI command may hang if no boards are present in either slot. + +4. Reflashing U-Boot +-------------------- +The board has two independent flash devices which can be used for dual +booting, or for u-boot backup and recovery. A two pin jumper on the +three pin JP10 determines which device is attached to /CS0 line. + +Assuming one device has a functional u-boot, and the other device has +a recently installed non-functional image, to perform a recovery from +that non-functional image goes essentially as follows: + +a) power down the board and jumper JP10 to select the functional image. +b) power on the board and let it get to u-boot prompt. +c) while on, using static precautions, move JP10 back to the failed image. +d) use "md fff00000" to confirm you are looking at the failed image +e) turn off write protect with "prot off all" +f) get new image, i.e. "tftp 200000 /somepath/u-boot.bin" +g) erase failed image: "erase FFF00000 FFF5FFFF" +h) copy in new image: "cp.b 200000 FFF00000 60000" +i) ensure new image is written: "md fff00000" +k) power cycle the board and confirm new image works. diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 55906b5..f6f2a60 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -227,6 +227,10 @@ config OLD_SUNXI_KERNEL_COMPAT Set this to enable various workarounds for old kernels, this results in sub-optimal settings for newer kernels, only enable if needed. +config MMC + depends on !UART0_PORT_F + default y if ARCH_SUNXI + config MMC0_CD_PIN string "Card detect pin for mmc0" default "" @@ -562,4 +566,8 @@ config GMAC_TX_DELAY ---help--- Set the GMAC Transmit Clock Delay Chain value. +config SPL_STACK_R_ADDR + default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I + default 0x2fe00000 if MACH_SUN9I + endif diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 67a9d29..96c4f3a 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -24,16 +24,18 @@ F: configs/A13-OLinuXino_defconfig F: configs/A13-OLinuXinoM_defconfig F: configs/Auxtek-T003_defconfig F: configs/Auxtek-T004_defconfig +F: configs/CHIP_defconfig F: configs/inet98v_rev2_defconfig F: configs/mk802_a10s_defconfig F: configs/q8_a13_tablet_defconfig F: configs/r7-tv-dongle_defconfig F: configs/UTOO_P66_defconfig +F: configs/Wobo_i5_defconfig F: include/configs/sun6i.h F: configs/CSQ_CS908_defconfig F: configs/Mele_A1000G_quad_defconfig F: configs/Mele_M9_defconfig -F: configs/Wobo_i5_defconfig +F: configs/Sinovoip_BPI_M2_defconfig F: include/configs/sun7i.h F: configs/A20-OLinuXino_MICRO_defconfig F: configs/Bananapi_defconfig @@ -48,8 +50,6 @@ F: configs/Wits_Pro_A20_DKT_defconfig F: include/configs/sun8i.h F: configs/ga10h_v1_1_defconfig F: configs/gt90h_v4_defconfig -F: configs/Ippo_q8h_v1_2_defconfig -F: configs/Ippo_q8h_v1_2_a33_1024x600_defconfig F: configs/q8_a23_tablet_800x480_defconfig F: configs/q8_a33_tablet_800x480_defconfig F: configs/q8_a33_tablet_1024x600_defconfig @@ -94,16 +94,6 @@ F: include/configs/sun7i.h F: configs/Cubieboard2_defconfig F: configs/Cubietruck_defconfig -ET Q8 V1.6 Tablet BOARD -M: VishnuPatekar <vishnupatekar0510@gmail.com> -S: Maintained -F: configs/Et_q8_v1_6_defconfig - -FORFUN-Q88DB TABLET -M: Jens Lucius <info@jenslucius.com> -S: Maintained -F: configs/forfun_q88db_defconfig - GEMEI-G9 TABLET M: Priit Laes <plaes@plaes.org> S: Maintained @@ -129,11 +119,6 @@ M: Michal Suchanek <hramrach@gmail.com> S: Maintained F: configs/iNet_86VS_defconfig -IPPO-Q8H-V5 BOARD -M: Chen-Yu Tsai <wens@csie.org> -S: Maintained -F: configs/Ippo_q8h_v5_defconfig - LINKSPRITE-PCDUINO BOARD M: Zoltan Herpai <wigyori@uid0.hu> S: Maintained @@ -185,11 +170,6 @@ S: Maintained F: configs/Sinlinx_SinA33_defconfig W: http://linux-sunxi.org/Sinlinx_SinA33 -TZX-Q8-713B7 BOARD -M: Paul Kocialkowski <contact@paulk.fr> -S: Maintained -F: configs/TZX-Q8-713B7_defconfig - WEXLER-TAB7200 BOARD M: Aleksei Mamlin <mamlinav@gmail.com> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 096d127..6ac398c 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -13,15 +13,7 @@ #include <common.h> #include <mmc.h> -#ifdef CONFIG_AXP152_POWER -#include <axp152.h> -#endif -#ifdef CONFIG_AXP209_POWER -#include <axp209.h> -#endif -#ifdef CONFIG_AXP221_POWER -#include <axp221.h> -#endif +#include <axp_pmic.h> #include <asm/arch/clock.h> #include <asm/arch/cpu.h> #include <asm/arch/display.h> @@ -438,40 +430,42 @@ void sunxi_board_init(void) int power_failed = 0; unsigned long ramsize; -#ifdef CONFIG_AXP152_POWER - power_failed = axp152_init(); - power_failed |= axp152_set_dcdc2(1400); - power_failed |= axp152_set_dcdc3(1500); - power_failed |= axp152_set_dcdc4(1250); - power_failed |= axp152_set_ldo2(3000); +#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER + power_failed = axp_init(); + +#ifdef CONFIG_AXP221_POWER + power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); #endif -#ifdef CONFIG_AXP209_POWER - power_failed |= axp209_init(); - power_failed |= axp209_set_dcdc2(1400); - power_failed |= axp209_set_dcdc3(1250); - power_failed |= axp209_set_ldo2(3000); - power_failed |= axp209_set_ldo3(2800); - power_failed |= axp209_set_ldo4(2800); + power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); + power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); +#ifndef CONFIG_AXP209_POWER + power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); #endif #ifdef CONFIG_AXP221_POWER - power_failed = axp221_init(); - power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT); - power_failed |= axp221_set_dcdc2(CONFIG_AXP221_DCDC2_VOLT); - power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */ -#ifdef CONFIG_MACH_SUN6I - power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */ -#else - power_failed |= axp221_set_dcdc4(0); /* A23:unused */ + power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); #endif - power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */ - power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT); - power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT); - power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT); - power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT); - power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT); - power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT); + +#ifdef CONFIG_AXP221_POWER + power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); +#endif + power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); +#ifndef CONFIG_AXP152_POWER + power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); +#endif +#ifdef CONFIG_AXP209_POWER + power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); #endif +#ifdef CONFIG_AXP221_POWER + power_failed |= axp_set_dldo1(CONFIG_AXP_DLDO1_VOLT); + power_failed |= axp_set_dldo2(CONFIG_AXP_DLDO2_VOLT); + power_failed |= axp_set_dldo3(CONFIG_AXP_DLDO3_VOLT); + power_failed |= axp_set_dldo4(CONFIG_AXP_DLDO4_VOLT); + power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); + power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); + power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); +#endif +#endif printf("DRAM:"); ramsize = sunxi_dram_init(); printf(" %lu MiB\n", ramsize >> 20); diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c index 744ff44..d51b5d9 100644 --- a/board/technexion/tao3530/tao3530.c +++ b/board/technexion/tao3530/tao3530.c @@ -160,7 +160,7 @@ int misc_init_r(void) puts("Unknown board revision\n"); } - dieid_num_r(); + omap_die_id_display(); return 0; } diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index a4aed3b..48d207f 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -92,7 +92,7 @@ int misc_init_r(void) struct tam3517_module_info info; int ret; - dieid_num_r(); + omap_die_id_display(); eth_addr = getenv("ethaddr"); if (eth_addr) diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index b4a0a72..c2de1fe 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -257,7 +257,7 @@ int misc_init_r(void) int ret; TAM3517_READ_EEPROM(&info, ret); - dieid_num_r(); + omap_die_id_display(); if (ret) return 0; diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 1dc2ed0..f0cb1e2 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -38,7 +38,10 @@ DECLARE_GLOBAL_DATA_PTR; /* GPIO that controls power to DDR on EVM-SK */ #define GPIO_DDR_VTT_EN 7 +#if defined(CONFIG_SPL_BUILD) || \ + (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH)) static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; +#endif /* * Read header information from EEPROM into global structure. @@ -513,6 +516,8 @@ int board_late_init(void) } #endif +#ifndef CONFIG_DM_ETH + #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) static void cpsw_control(int enabled) @@ -670,3 +675,5 @@ int board_eth_init(bd_t *bis) return n; } #endif + +#endif /* CONFIG_DM_ETH */ diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 680f656..28c29a2 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -65,7 +65,7 @@ static struct module_pin_mux mmc0_pin_mux[] = { {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ - {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_6 */ {-1}, }; diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index a649697..8d1c390 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -47,7 +47,7 @@ int misc_init_r(void) i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif - dieid_num_r(); + omap_die_id_display(); return 0; } diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 3b0a9e7..56e3cfe 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -494,7 +494,7 @@ int misc_init_r(void) writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); - dieid_num_r(); + omap_die_id_display(); #ifdef CONFIG_VIDEO_OMAP3 beagle_dvi_pup(); @@ -506,12 +506,8 @@ int misc_init_r(void) musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); #endif - if (generate_fake_mac) { - u32 id[4]; - - get_dieid(id); - usb_fake_mac_from_die_id(id); - } + if (generate_fake_mac) + omap_die_id_usbethaddr(); return 0; } diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 890b603..eebec88 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -57,16 +57,12 @@ int board_init(void) int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - u32 id[4]; - if (omap_revision() == DRA722_ES1_0) setenv("board_name", "dra72x"); else setenv("board_name", "dra7xx"); - id[0] = readl((*ctrl)->control_std_fuse_die_id_0); - id[1] = readl((*ctrl)->control_std_fuse_die_id_1); - usb_set_serial_num_from_die_id(id); + omap_die_id_serial(); #endif return 0; } diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 3f93d9c..ff3971d 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -159,7 +159,7 @@ int misc_init_r(void) #if defined(CONFIG_CMD_NET) reset_net_chip(); #endif - dieid_num_r(); + omap_die_id_display(); return 0; } diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig index 384b175..c0568ec 100644 --- a/board/ti/ks2_evm/Kconfig +++ b/board/ti/ks2_evm/Kconfig @@ -36,3 +36,16 @@ config SYS_CONFIG_NAME default "k2l_evm" endif + +if TARGET_K2G_EVM + +config SYS_BOARD + default "ks2_evm" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "k2g_evm" + +endif diff --git a/board/ti/ks2_evm/MAINTAINERS b/board/ti/ks2_evm/MAINTAINERS index 87c36c9..999ef0a 100644 --- a/board/ti/ks2_evm/MAINTAINERS +++ b/board/ti/ks2_evm/MAINTAINERS @@ -8,3 +8,5 @@ F: include/configs/k2e_evm.h F: configs/k2e_evm_defconfig F: include/configs/k2l_evm.h F: configs/k2l_evm_defconfig +F: include/configs/k2g_evm.h +F: configs/k2g_evm_defconfig diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index 071dbee..d60496e 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -13,3 +13,5 @@ obj-$(CONFIG_K2E_EVM) += board_k2e.o obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o obj-$(CONFIG_K2L_EVM) += board_k2l.o obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o +obj-$(CONFIG_K2G_EVM) += board_k2g.o +obj-$(CONFIG_K2G_EVM) += ddr3_k2g.o diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README index b8d55e7..0fe5c3b 100644 --- a/board/ti/ks2_evm/README +++ b/board/ti/ks2_evm/README @@ -59,8 +59,8 @@ Supported boot modes: - UART boot Supported image formats: - - u-boot.bin: for loading and running u-boot.bin through Texas instruments - code composure studio (CCS) and for UART boot. + - u-boot-dtb.bin: for loading and running u-boot-dtb.bin through + Texas Instruments code composure studio (CCS) and for UART boot. - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot - MLO: gpimage for programming AEMIF NAND flash for NAND boot @@ -69,18 +69,18 @@ Build instructions: Examples for k2hk, for k2e and k2l just replace k2hk prefix accordingly. Don't forget to add ARCH=arm and CROSS_COMPILE. -To build u-boot.bin, u-boot-spi.gph, MLO: +To build u-boot-dtb.bin, u-boot-spi.gph, MLO: >make k2hk_evm_defconfig >make Load and Run U-Boot on keystone EVMs using CCS ========================================= -Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin +Need Code Composer Studio (CCS) installed on a PC to load and run u-boot-dtb.bin on EVM. See instructions at below link for installing CCS on a Windows PC. http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started# Installing_Code_Composer_Studio -Use u-boot.bin from the build folder for loading and running u-boot binary +Use u-boot-dtb.bin from the build folder for loading and running u-boot binary on EVM. Follow instructions at K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup @@ -100,7 +100,7 @@ loading the u-boot binary on the target EVM. Instead do the following:- is connected: Unknown)" at the debug window (This is created once Target configuration is launched) and select "Connect Target". 2. Once target connect is successful, choose Tools->Load Memory option from the - top level menu. At the Load Memory window, choose the file u-boot.bin + top level menu. At the Load Memory window, choose the file u-boot-dtb.bin through "Browse" button and click "next >" button. In the next window, enter Start address as 0xc001000, choose Type-size "32 bits" and click "Finish" button. @@ -167,7 +167,7 @@ Load and Run U-Boot on keystone EVMs using UART download Open BMC and regular UART terminals. -1. On the regular UART port start xmodem transfer of the u-boot.bin +1. On the regular UART port start xmodem transfer of the u-boot-dtb.bin 2. Using BMC terminal set the ARM-UART bootmode and reboot the EVM BMC> bootmode #4 MBC> reboot diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 859a260..73d94a6 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -14,6 +14,7 @@ #include <fdt_support.h> #include <asm/arch/ddr3.h> #include <asm/arch/psc_defs.h> +#include <asm/arch/clock.h> #include <asm/ti-common/ti-aemif.h> #include <asm/ti-common/keystone_net.h> @@ -42,7 +43,8 @@ int dram_init(void) gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); - ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); + if (ddr3_size) + ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); return 0; } @@ -73,14 +75,22 @@ int board_eth_init(bd_t *bis) int port_num; char link_type_name[32]; + if (cpu_is_k2g()) + writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG); + /* By default, select PA PLL clock as PA clock source */ +#ifndef CONFIG_SOC_K2G if (psc_enable_module(KS2_LPSC_PA)) return -1; +#endif if (psc_enable_module(KS2_LPSC_CPGMAC)) return -1; if (psc_enable_module(KS2_LPSC_CRYPTO)) return -1; + if (cpu_is_k2e() || cpu_is_k2l()) + pll_pa_clk_sel(); + port_num = get_num_eth_ports(); for (j = 0; j < port_num; j++) { diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index dc00cf6..f58f623 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -82,6 +82,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 0, .slave_port = 1, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC1", @@ -89,6 +90,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 1, .slave_port = 2, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC2", @@ -96,6 +98,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 2, .slave_port = 3, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC3", @@ -103,6 +106,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 3, .slave_port = 4, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC4", @@ -110,6 +114,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 4, .slave_port = 5, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC5", @@ -117,6 +122,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 5, .slave_port = 6, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC6", @@ -124,6 +130,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 6, .slave_port = 7, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2E_EMAC7", @@ -131,6 +138,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 7, .slave_port = 8, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, }; diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c new file mode 100644 index 0000000..cdeb056 --- /dev/null +++ b/board/ti/ks2_evm/board_k2g.c @@ -0,0 +1,117 @@ +/* + * K2G EVM : Board initialization + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/ti-common/keystone_net.h> +#include <asm/arch/psc_defs.h> +#include <asm/arch/mmc_host_def.h> +#include "mux-k2g.h" + +#define SYS_CLK 24000000 + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = SYS_CLK, + [pa_clk] = SYS_CLK, + [tetris_clk] = SYS_CLK, + [ddr3a_clk] = SYS_CLK, + [uart_clk] = SYS_CLK, +}; + +static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4}; +static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4}; +static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; +static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2}; +static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10}; + +struct pll_init_data *get_pll_init_data(int pll) +{ + struct pll_init_data *data = NULL; + + switch (pll) { + case MAIN_PLL: + data = &main_pll_config; + break; + case TETRIS_PLL: + data = &tetris_pll_config; + break; + case NSS_PLL: + data = &nss_pll_config; + break; + case UART_PLL: + data = &uart_pll_config; + break; + case DDR3_PLL: + data = &ddr3_pll_config; + break; + default: + data = NULL; + } + + return data; +} + +s16 divn_val[16] = { + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 +}; + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + if (psc_enable_module(KS2_LPSC_MMC)) { + printf("%s module enabled failed\n", __func__); + return -1; + } + + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); + return 0; +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + init_plls(); + + k2g_mux_config(); + + /* deassert FLASH_HOLD */ + clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET, + BIT(9)); + setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET, + BIT(9)); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +void spl_init_keystone_plls(void) +{ + init_plls(); +} +#endif + +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +struct eth_priv_t eth_priv_cfg[] = { + { + .int_name = "K2G_EMAC", + .rx_flow = 0, + .phy_addr = 0, + .slave_port = 1, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, +}; + +int get_num_eth_ports(void) +{ + return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); +} +#endif diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index 6e681d7..0bd6b86 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -76,6 +76,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 0, .slave_port = 1, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2HK_EMAC1", @@ -83,6 +84,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 1, .slave_port = 2, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2HK_EMAC2", @@ -90,6 +92,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 2, .slave_port = 3, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2HK_EMAC3", @@ -97,6 +100,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 3, .slave_port = 4, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, }; diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index f35a64f..d750ad3 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -75,6 +75,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 0, .slave_port = 1, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2L_EMAC1", @@ -82,6 +83,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 1, .slave_port = 2, .sgmii_link_type = SGMII_LINK_MAC_PHY, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2L_EMAC2", @@ -89,6 +91,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 2, .slave_port = 3, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, { .int_name = "K2L_EMAC3", @@ -96,6 +99,7 @@ struct eth_priv_t eth_priv_cfg[] = { .phy_addr = 3, .slave_port = 4, .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + .phy_if = PHY_INTERFACE_MODE_SGMII, }, }; diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c new file mode 100644 index 0000000..344961d --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2g.c @@ -0,0 +1,64 @@ +/* + * K2G: DDR3 initialization + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include "ddr3_cfg.h" +#include <asm/arch/ddr3.h> + +struct ddr3_phy_config ddr3phy_800_2g = { + .pllcr = 0x000DC000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, + .ptr3 = 0x06C30D40ul, + .ptr4 = 0x06413880ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x550F6644ul, + .dtpr1 = 0x328341E0ul, + .dtpr2 = 0x50022A00ul, + .mr0 = 0x00001430ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F03D09ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x00000F81ul, +}; + +struct ddr3_emif_config ddr3_800_2g = { + .sdcfg = 0x62005662ul, + .sdtim1 = 0x0A385033ul, + .sdtim2 = 0x00001CA5ul, + .sdtim3 = 0x21ADFF32ul, + .sdtim4 = 0x533F067Ful, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00000C34ul, +}; + +u32 ddr3_init(void) +{ + /* Reset DDR3 PHY after PLL enabled */ + ddr3_reset_ddrphy(); + + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g); + + return 0; +} + +inline int ddr3_get_size(void) +{ + return 2; +} diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h new file mode 100644 index 0000000..773f9b7 --- /dev/null +++ b/board/ti/ks2_evm/mux-k2g.h @@ -0,0 +1,313 @@ +/* + * K2G EVM: Pinmux configuration + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mux-k2g.h> +#include <asm/arch/hardware.h> + +struct pin_cfg k2g_evm_pin_cfg[] = { + /* GPMC */ + { 0, MODE(0) }, /* GPMCAD0 */ + { 1, MODE(0) }, /* GPMCAD1 */ + { 2, MODE(0) }, /* GPMCAD2 */ + { 3, MODE(0) }, /* GPMCAD3 */ + { 4, MODE(0) }, /* GPMCAD4 */ + { 5, MODE(0) }, /* GPMCAD5 */ + { 6, MODE(0) }, /* GPMCAD6 */ + { 7, MODE(0) }, /* GPMCAD7 */ + { 8, MODE(0) }, /* GPMCAD8 */ + { 9, MODE(0) }, /* GPMCAD9 */ + { 10, MODE(0) }, /* GPMCAD10 */ + { 11, MODE(0) }, /* GPMCAD11 */ + { 12, MODE(0) }, /* GPMCAD12 */ + { 13, MODE(0) }, /* GPMCAD13 */ + { 14, MODE(0) }, /* GPMCAD14 */ + { 15, MODE(0) }, /* GPMCAD15 */ + { 17, MODE(0) }, /* GPMCADVNALE */ + { 18, MODE(0) }, /* GPMCOENREN */ + { 19, MODE(0) }, /* GPMCWEN */ + { 20, MODE(0) }, /* GPMCBE0NCLE */ + { 22, MODE(0) }, /* GPMCWAIT0 */ + { 24, MODE(0) }, /* GPMCWPN */ + { 26, MODE(0) }, /* GPMCCSN0 */ + + /* GPIOs */ + { 16, MODE(3) | PIN_IEN }, /* GPIO0_16 - PRSNT1# */ + { 21, MODE(3) | PIN_IEN }, /* GPIO0_21 - DC_BRD_DET */ + { 82, MODE(3) | PIN_IEN }, /* GPIO0_82 - TPS_INT1 */ + { 83, MODE(3) }, /* GPIO0_83 - TPS_SLEEP */ + { 84, MODE(3) }, /* GPIO0_84 - SEL_HDMIn_GPIO */ + { 87, MODE(3) }, /* GPIO0_87 - SD_LP2996A */ + { 106, MODE(3) | PIN_IEN}, /* GPIO0_100 - SOC_INT */ + { 201, MODE(3) | PIN_IEN}, /* GPIO1_26 - GPIO_EXP_INT */ + { 202, MODE(3) }, /* GPIO1_27 - SEL_LCDn_GPIO */ + { 203, MODE(3) | PIN_IEN}, /* GPIO1_28 - SOC_MLB_GPIO2 */ + { 204, MODE(3) | PIN_IEN}, /* GPIO1_29 - SOC_PCIE_WAKEn */ + { 205, MODE(3) | PIN_IEN}, /* GPIO1_30 - BMC_INT1 */ + { 206, MODE(3) | PIN_IEN}, /* GPIO1_31 - HDMI_INTn*/ + { 207, MODE(3) | PIN_IEN}, /* GPIO1_32 - CS2000_AUX_OUT */ + { 208, MODE(3) | PIN_IEN}, /* GPIO1_33 - TEMP_INT */ + { 209, MODE(3) | PIN_IEN}, /* GPIO1_34 - WLAN_IRQ */ + { 216, MODE(3) }, /* GPIO1_41 - FLASH_HOLD */ + { 217, MODE(3) | PIN_IEN}, /* GPIO1_42 - TOUCH_INTn */ + + /* MLB */ + { 23, MODE(2) }, /* SOC_MLBCLK */ + { 25, MODE(2) }, /* SOC_MLBSIG */ + { 27, MODE(2) }, /* SOC_MLBDAT */ + + /* DSS */ + { 30, MODE(0) }, /* SOC_DSSDATA23 */ + { 31, MODE(0) }, /* SOC_DSSDATA22 */ + { 32, MODE(0) }, /* SOC_DSSDATA21 */ + { 33, MODE(0) }, /* SOC_DSSDATA20 */ + { 34, MODE(0) }, /* SOC_DSSDATA19 */ + { 35, MODE(0) }, /* SOC_DSSDATA18 */ + { 36, MODE(0) }, /* SOC_DSSDATA17 */ + { 37, MODE(0) }, /* SOC_DSSDATA16 */ + { 38, MODE(0) }, /* SOC_DSSDATA15 */ + { 39, MODE(0) }, /* SOC_DSSDATA14 */ + { 40, MODE(0) }, /* SOC_DSSDATA13 */ + { 41, MODE(0) }, /* SOC_DSSDATA12 */ + { 42, MODE(0) }, /* SOC_DSSDATA11 */ + { 43, MODE(0) }, /* SOC_DSSDATA10 */ + { 44, MODE(0) }, /* SOC_DSSDATA9 */ + { 45, MODE(0) }, /* SOC_DSSDATA8 */ + { 46, MODE(0) }, /* SOC_DSSDATA7 */ + { 47, MODE(0) }, /* SOC_DSSDATA6 */ + { 48, MODE(0) }, /* SOC_DSSDATA5 */ + { 49, MODE(0) }, /* SOC_DSSDATA4 */ + { 50, MODE(0) }, /* SOC_DSSDATA3 */ + { 51, MODE(0) }, /* SOC_DSSDATA2 */ + { 52, MODE(0) }, /* SOC_DSSDATA1 */ + { 53, MODE(0) }, /* SOC_DSSDATA0 */ + { 54, MODE(0) }, /* SOC_DSSVSYNC */ + { 55, MODE(0) }, /* SOC_DSSHSYNC */ + { 56, MODE(0) }, /* SOC_DSSPCLK */ + { 57, MODE(0) }, /* SOC_DSS_DE */ + { 58, MODE(0) }, /* SOC_DSS_FID */ + { 221, MODE(4) }, /* PWM0 - SOC_BACKLIGHT_PWM */ + + /* MMC1 */ + { 59, MODE(0) }, /* SOC_MMC1_DAT7 */ + { 60, MODE(0) }, /* SOC_MMC1_DAT6 */ + { 61, MODE(0) }, /* SOC_MMC1_DAT5 */ + { 62, MODE(0) }, /* SOC_MMC1_DAT4 */ + { 63, MODE(0) }, /* SOC_MMC1_DAT3 */ + { 64, MODE(0) }, /* SOC_MMC1_DAT2 */ + { 65, MODE(0) }, /* SOC_MMC1_DAT1 */ + { 66, MODE(0) }, /* SOC_MMC1_DAT0 */ + { 67, MODE(0) }, /* SOC_MMC1_CLK */ + { 68, MODE(0) }, /* SOC_MMC1_CMD */ + { 69, MODE(0) }, /* MMC1SDCD TP125 */ + { 70, MODE(0) }, /* SOC_MMC1_SDWP */ + { 71, MODE(0) }, /* MMC1POW TP124 */ + + /* RGMII */ + { 72, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCLK */ + { 77, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD3 */ + { 78, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD2 */ + { 79, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD1 */ + { 80, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD0 */ + { 81, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCTL */ + { 85, MODE(1) }, /* SOC_RGMII_TXCLK */ + { 91, MODE(1) }, /* SOC_RGMII_TXD3 */ + { 92, MODE(1) }, /* SOC_RGMII_TXD2 */ + { 93, MODE(1) }, /* SOC_RGMII_TXD1 */ + { 94, MODE(1) }, /* SOC_RGMII_TXD0 */ + { 95, MODE(1) }, /* SOC_RGMII_TXCTL */ + { 98, MODE(0) }, /* SOC_MDIO_DATA */ + { 99, MODE(0) }, /* SOC_MDIO_CLK */ + + /* PWM */ + { 73, MODE(4) }, /* SOC_EHRPWM3A */ + { 74, MODE(4) }, /* SOC_EHRPWM3B */ + { 75, MODE(4) }, /* SOC_EHRPWM3_SYNCI */ + { 76, MODE(4) }, /* SOC_EHRPWM3_SYNCO */ + { 96, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT3 */ + { 198, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT4 */ + { 199, MODE(4) }, /* SOC_EHRPWM4A */ + { 200, MODE(4) }, /* SOC_EHRPWM4B */ + { 218, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT5 */ + { 219, MODE(4) }, /* SOC_EHRPWM5A */ + { 220, MODE(4) }, /* SOC_EHRPWM5B */ + { 222, MODE(4) }, /* SOC_ECAP1_IN_PWM1_OUT */ + + /* SPI3 */ + { 86, MODE(1) }, /* SOC_SPI3_SCS0 */ + { 88, MODE(1) }, /* SOC_SPI3_CLK */ + { 89, MODE(1) }, /* SOC_SPI3_MISO */ + { 90, MODE(1) }, /* SOC_SPI3_MOSI */ + + /* CLK */ + { 97, MODE(0) }, /* SMD - TP132 */ + + /* SPI0 */ + { 100, MODE(0) }, /* SOC_SPI0_SCS0 */ + { 101, MODE(0) }, /* SOC_SPI0_SCS1 */ + { 102, MODE(0) }, /* SOC_SPI0_CLK */ + { 103, MODE(0) }, /* SOC_SPI0_MISO */ + { 104, MODE(0) }, /* SOC_SPI0_MOSI */ + + /* SPI1 NORFLASH */ + { 105, MODE(0) }, /* SOC_SPI1_SCS0 */ + { 107, MODE(0) }, /* SOC_SPI1_CLK */ + { 108, MODE(0) }, /* SOC_SPI1_MISO */ + { 109, MODE(0) }, /* SOC_SPI1_MOSI */ + + /* SPI2 */ + { 110, MODE(0) }, /* SOC_SPI2_SCS0 */ + { 111, MODE(1) }, /* SOC_HOUT */ + { 112, MODE(0) }, /* SOC_SPI2_CLK */ + { 113, MODE(0) }, /* SOC_SPI2_MISO */ + { 114, MODE(0) }, /* SOC_SPI2_MOSI */ + + /* UART0 */ + { 115, MODE(0) }, /* SOC_UART0_RXD */ + { 116, MODE(0) }, /* SOC_UART0_TXD */ + { 117, MODE(0) }, /* SOC_UART0_CTSn */ + { 118, MODE(0) }, /* SOC_UART0_RTSn */ + + /* UART1 */ + { 119, MODE(0) }, /* SOC_UART1_RXD */ + { 120, MODE(0) }, /* SOC_UART1_TXD */ + { 121, MODE(0) }, /* SOC_UART1_CTSn */ + { 122, MODE(0) }, /* SOC_UART1_RTSn */ + + /* UART2 */ + { 123, MODE(0) }, /* SOC_UART2_RXD */ + { 124, MODE(0) }, /* SOC_UART2_TXD */ + { 125, MODE(0) }, /* UART0_TXVR_EN */ + { 126, MODE(4) }, /* SOC_CPTS_TS_COMP */ + + /* DCAN */ + { 127, MODE(0) }, /* SOC_DCAN0_TX */ + { 128, MODE(0) }, /* SOC_DCAN0_RX */ + { 137, MODE(1) }, /* SOC_DCAN1_TX */ + { 138, MODE(1) }, /* SOC_DCAN1_RX */ + + /* QSPI */ + { 129, MODE(0) }, /* SOC_QSPI_CLK */ + { 130, MODE(0) }, /* SOC_QSPI_RTCLK */ + { 131, MODE(0) }, /* SOC_QSPI_D0 */ + { 132, MODE(0) }, /* SOC_QSPI_D1 */ + { 133, MODE(0) }, /* SOC_QSPI_D2 */ + { 134, MODE(0) }, /* SOC_QSPI_D3 */ + { 135, MODE(0) }, /* SOC_QSPI_CSN0 */ + { 136, MODE(1) }, /* DNI <-> WLAN_SLOW_CLK */ + + /* MCASP2 */ + { 139, MODE(3) }, /* SOC_MCASP2AXR0 - (GPIO0_108)SOC_LED0 */ + { 140, MODE(4) }, /* SOC_MCASP2AXR1 */ + { 141, MODE(4) }, /* SOC_MCASP2AXR2 */ + { 142, MODE(4) }, /* SOC_MCASP2AXR3 */ + { 143, MODE(4) }, /* SOC_MCASP2AXR4 */ + { 144, MODE(4) }, /* SOC_MCASP2AXR5 */ + { 145, MODE(4) }, /* SOC_McASP2ACLKR */ + { 146, MODE(4) }, /* SOC_McASP2FSR */ + { 147, MODE(4) }, /* SOC_McASP2AHCLKR */ + { 148, MODE(3) }, /* GPIO0_117 - WLAN_TRANS_EN */ + { 149, MODE(4) }, /* SOC_McASP2FSX */ + { 150, MODE(4) }, /* SOC_McASP2AHCLKX */ + { 151, MODE(4) }, /* SOC_McASP2ACLKX */ + + /* MCASP1 */ + { 152, MODE(4) }, /* SOC_MCASP1ACLKR */ + { 153, MODE(4) }, /* SOC_MCASP1FSR */ + { 154, MODE(4) }, /* SOC_MCASP1AHCLKR */ + { 155, MODE(4) }, /* SOC_MCASP1ACLKX */ + { 156, MODE(4) }, /* SOC_MCASP1FSX */ + { 157, MODE(4) }, /* SOC_MCASP1AHCLKX */ + { 158, MODE(4) }, /* SOC_MCASP1AMUTE */ + { 159, MODE(4) }, /* SOC_MCASP1AXR0 */ + { 160, MODE(4) }, /* SOC_MCASP1AXR1 */ + { 161, MODE(4) }, /* SOC_MCASP1AXR2 */ + { 162, MODE(4) }, /* SOC_MCASP1AXR3 */ + { 163, MODE(4) }, /* SOC_MCASP1AXR4 */ + { 164, MODE(4) }, /* SOC_MCASP1AXR5 */ + { 165, MODE(4) }, /* SOC_MCASP1AXR6 */ + { 166, MODE(4) }, /* SOC_MCASP1AXR7 */ + { 167, MODE(4) }, /* SOC_MCASP1AXR8 */ + { 168, MODE(4) }, /* SOC_MCASP1AXR9 */ + + /* MCASP0 */ + { 169, MODE(4) }, /* SOC_MCASP0AMUTE */ + { 170, MODE(4) }, /* SOC_MCASP0ACLKR */ + { 171, MODE(4) }, /* SOC_MCASP0FSR */ + { 172, MODE(4) }, /* SOC_MCASP0AHCLKR */ + { 173, MODE(4) }, /* SOC_MCASP0ACLKX */ + { 174, MODE(4) }, /* SOC_MCASP0FSX */ + { 175, MODE(4) }, /* SOC_MCASP0AHCLKX */ + { 176, MODE(4) }, /* SOC_MCASP0AXR0 */ + { 177, MODE(4) }, /* SOC_MCASP0AXR1 */ + { 178, MODE(4) }, /* SOC_MCASP0AXR2 */ + { 179, MODE(4) }, /* SOC_MCASP0AXR3 */ + { 180, MODE(4) }, /* SOC_MCASP0AXR4 */ + { 181, MODE(4) }, /* SOC_MCASP0AXR5 */ + { 182, MODE(4) }, /* SOC_MCASP0AXR6 */ + { 183, MODE(4) }, /* SOC_MCASP0AXR7 */ + { 184, MODE(4) }, /* SOC_MCASP0AXR8 */ + { 185, MODE(4) }, /* SOC_MCASP0AXR9 */ + { 186, MODE(3) }, /* SOC_MCASP0AXR10 - (GPIO1_11)SOC_LED1 */ + { 188, MODE(4) }, /* SOC_MCASP0AXR12 */ + { 189, MODE(4) }, /* SOC_MCASP0AXR13 */ + { 190, MODE(4) }, /* SOC_MCASP0AXR14 */ + { 191, MODE(4) }, /* SOC_MCASP0AXR15 */ + + /* MMC0 */ + { 192, MODE(2) }, /* SOC_MMC0_DAT3 */ + { 193, MODE(2) }, /* SOC_MMC0_DAT2 */ + { 194, MODE(2) }, /* SOC_MMC0_DAT1 */ + { 195, MODE(2) }, /* SOC_MMC0_DAT0 */ + { 196, MODE(2) }, /* SOC_MMC0_CLK */ + { 197, MODE(2) }, /* SOC_MMC0_CMD */ + { 187, MODE(2) }, /* SOC_MMC0_SDCD */ + + /* McBSP */ + { 28, MODE(2) | PIN_IEN }, /* SOC_TIMI1 */ + { 29, MODE(2) }, /* SOC_TIMO1 */ + { 210, MODE(2) }, /* SOC_MCBSPDR */ + { 211, MODE(2) }, /* SOC_MCBSPDX */ + { 212, MODE(2) }, /* SOC_MCBSPFSX */ + { 213, MODE(2) }, /* SOC_MCBSPCLKX */ + { 214, MODE(2) }, /* SOC_MCBSPFSR */ + { 215, MODE(2) }, /* SOC_MCBSPCLKR */ + + /* I2C */ + { 223, MODE(0) }, /* SOC_I2C0_SCL */ + { 224, MODE(0) }, /* SOC_I2C0_SDA */ + { 225, MODE(0) }, /* SOC_I2C1_SCL */ + { 226, MODE(0) }, /* SOC_I2C1_SDA */ + { 227, MODE(0) }, /* SOC_I2C2_SCL */ + { 228, MODE(0) }, /* SOC_I2C2_SDA */ + { 229, MODE(0) }, /* NMIz */ + { 230, MODE(0) }, /* LRESETz */ + { 231, MODE(0) }, /* LRESETNMIENz */ + + { 235, MODE(0) }, + { 236, MODE(0) }, + { 237, MODE(0) }, + { 238, MODE(0) }, + { 239, MODE(0) }, + { 240, MODE(0) }, + { 241, MODE(0) }, + { 242, MODE(0) }, + { 243, MODE(0) }, + { 244, MODE(0) }, + + { 258, MODE(0) }, /* USB0DRVVBUS */ + { 259, MODE(0) }, /* USB1DRVVBUS */ + { MAX_PIN_N, } +}; + +void k2g_mux_config(void) +{ + configure_pin_mux(k2g_evm_pin_cfg); +} diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index 659877c..853f196 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -189,20 +189,11 @@ static void enable_host_clocks(void) */ int misc_init_r(void) { - int reg; - u32 id[4]; - #ifdef CONFIG_PALMAS_POWER palmas_init_settings(); #endif - reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET; - - id[0] = readl(reg); - id[1] = readl(reg + 0x8); - id[2] = readl(reg + 0xC); - id[3] = readl(reg + 0x10); - usb_fake_mac_from_die_id(id); + omap_die_id_usbethaddr(); return 0; } diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index 783ba35..eb9ce63 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -101,7 +101,7 @@ int get_board_revision(void) board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO); #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es")); + setenv("board_name", "panda-es"); #endif board_id = ((board_id4 << 4) | (board_id3 << 3) | (board_id2 << 2) | (board_id1 << 1) | (board_id0)); @@ -115,7 +115,7 @@ int get_board_revision(void) #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3)) - setenv("board_name", strcat(CONFIG_SYS_BOARD, "-a4")); + setenv("board_name", "panda-a4"); #endif } @@ -209,7 +209,6 @@ int misc_init_r(void) { int phy_type; u32 auxclk, altclksrc; - u32 id[4]; /* EHCI is not supported on ES1.0 */ if (omap_revision() == OMAP4430_ES1_0) @@ -263,11 +262,7 @@ int misc_init_r(void) writel(altclksrc, &scrm->altclksrc); - id[0] = readl(STD_FUSE_DIE_ID_0); - id[1] = readl(STD_FUSE_DIE_ID_1); - id[2] = readl(STD_FUSE_DIE_ID_2); - id[3] = readl(STD_FUSE_DIE_ID_3); - usb_fake_mac_from_die_id(id); + omap_die_id_usbethaddr(); return 0; } diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 4d07313..a61cc14 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -114,7 +114,7 @@ int misc_init_r(void) } #endif - dieid_num_r(); + omap_die_id_display(); return 0; } diff --git a/common/Kconfig b/common/Kconfig index 2c42b8e..0388a6c 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -148,6 +148,12 @@ config CMD_BOOTM help Boot an application image from the memory. +config CMD_ELF + bool "bootelf, bootvx" + default y + help + Boot an ELF/vxWorks image from the memory. + config CMD_GO bool "go" default y @@ -344,6 +350,11 @@ config CMD_FPGA help FPGA support. +config CMD_REMOTEPROC + bool "remoteproc" + depends on REMOTEPROC + help + Support for Remote Processor control endmenu diff --git a/common/Makefile b/common/Makefile index 491c565..8c7775a 100644 --- a/common/Makefile +++ b/common/Makefile @@ -154,6 +154,7 @@ obj-$(CONFIG_CMD_PXE) += cmd_pxe.o obj-$(CONFIG_CMD_READ) += cmd_read.o obj-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o obj-$(CONFIG_CMD_REISER) += cmd_reiser.o +obj-$(CONFIG_CMD_REMOTEPROC) += cmd_remoteproc.o obj-$(CONFIG_SANDBOX) += cmd_host.o obj-$(CONFIG_CMD_SATA) += cmd_sata.o obj-$(CONFIG_CMD_SF) += cmd_sf.o diff --git a/common/cmd_elf.c b/common/cmd_elf.c index 22475dc..86e694a 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -14,23 +14,98 @@ */ #include <common.h> -#include <bootm.h> #include <command.h> -#include <linux/ctype.h> -#include <net.h> #include <elf.h> +#include <net.h> #include <vxworks.h> - -#if defined(CONFIG_WALNUT) || defined(CONFIG_SYS_VXWORKS_MAC_PTR) -DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_X86 +#include <asm/e820.h> +#include <linux/linkage.h> #endif -static unsigned long load_elf_image_phdr(unsigned long addr); -static unsigned long load_elf_image_shdr(unsigned long addr); +/* + * A very simple elf loader, assumes the image is valid, returns the + * entry point address. + */ +static unsigned long load_elf_image_phdr(unsigned long addr) +{ + Elf32_Ehdr *ehdr; /* Elf header structure pointer */ + Elf32_Phdr *phdr; /* Program header structure pointer */ + int i; + + ehdr = (Elf32_Ehdr *)addr; + phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff); + + /* Load each program header */ + for (i = 0; i < ehdr->e_phnum; ++i) { + void *dst = (void *)(uintptr_t)phdr->p_paddr; + void *src = (void *)addr + phdr->p_offset; + debug("Loading phdr %i to 0x%p (%i bytes)\n", + i, dst, phdr->p_filesz); + if (phdr->p_filesz) + memcpy(dst, src, phdr->p_filesz); + if (phdr->p_filesz != phdr->p_memsz) + memset(dst + phdr->p_filesz, 0x00, + phdr->p_memsz - phdr->p_filesz); + flush_cache((unsigned long)dst, phdr->p_filesz); + ++phdr; + } + + return ehdr->e_entry; +} + +static unsigned long load_elf_image_shdr(unsigned long addr) +{ + Elf32_Ehdr *ehdr; /* Elf header structure pointer */ + Elf32_Shdr *shdr; /* Section header structure pointer */ + unsigned char *strtab = 0; /* String table pointer */ + unsigned char *image; /* Binary image pointer */ + int i; /* Loop counter */ + + ehdr = (Elf32_Ehdr *)addr; + + /* Find the section header string table for output info */ + shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff + + (ehdr->e_shstrndx * sizeof(Elf32_Shdr))); + + if (shdr->sh_type == SHT_STRTAB) + strtab = (unsigned char *)(addr + shdr->sh_offset); + + /* Load each appropriate section */ + for (i = 0; i < ehdr->e_shnum; ++i) { + shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff + + (i * sizeof(Elf32_Shdr))); + + if (!(shdr->sh_flags & SHF_ALLOC) || + shdr->sh_addr == 0 || shdr->sh_size == 0) { + continue; + } + + if (strtab) { + debug("%sing %s @ 0x%08lx (%ld bytes)\n", + (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load", + &strtab[shdr->sh_name], + (unsigned long)shdr->sh_addr, + (long)shdr->sh_size); + } + + if (shdr->sh_type == SHT_NOBITS) { + memset((void *)(uintptr_t)shdr->sh_addr, 0, + shdr->sh_size); + } else { + image = (unsigned char *)addr + shdr->sh_offset; + memcpy((void *)(uintptr_t)shdr->sh_addr, + (const void *)image, shdr->sh_size); + } + flush_cache(shdr->sh_addr, shdr->sh_size); + } + + return ehdr->e_entry; +} /* Allow ports to override the default behavior */ static unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]), - int argc, char * const argv[]) + int argc, char * const argv[]) { unsigned long ret; @@ -54,18 +129,16 @@ static unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]), return ret; } -/* ====================================================================== +/* * Determine if a valid ELF image exists at the given memory location. - * First looks at the ELF header magic field, the makes sure that it is - * executable and makes sure that it is for a PowerPC. - * ====================================================================== */ + * First look at the ELF header magic field, then make sure that it is + * executable. + */ int valid_elf_image(unsigned long addr) { - Elf32_Ehdr *ehdr; /* Elf header structure pointer */ - - /* -------------------------------------------------- */ + Elf32_Ehdr *ehdr; /* Elf header structure pointer */ - ehdr = (Elf32_Ehdr *) addr; + ehdr = (Elf32_Ehdr *)addr; if (!IS_ELF(*ehdr)) { printf("## No elf image at address 0x%08lx\n", addr); @@ -77,27 +150,17 @@ int valid_elf_image(unsigned long addr) return 0; } -#if 0 - if (ehdr->e_machine != EM_PPC) { - printf("## Not a PowerPC elf image at address 0x%08lx\n", addr); - return 0; - } -#endif - return 1; } -/* ====================================================================== - * Interpreter command to boot an arbitrary ELF image from memory. - * ====================================================================== */ +/* Interpreter command to boot an arbitrary ELF image from memory */ int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - unsigned long addr; /* Address of the ELF image */ - unsigned long rc; /* Return value from user code */ + unsigned long addr; /* Address of the ELF image */ + unsigned long rc; /* Return value from user code */ char *sload, *saddr; const char *ep = getenv("autostart"); - /* -------------------------------------------------- */ int rcode = 0; sload = saddr = NULL; @@ -138,28 +201,32 @@ int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) rcode = 1; printf("## Application terminated, rc = 0x%lx\n", rc); + return rcode; } -/* ====================================================================== +/* * Interpreter command to boot VxWorks from a memory image. The image can * be either an ELF image or a raw binary. Will attempt to setup the * bootline and other parameters correctly. - * ====================================================================== */ + */ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - unsigned long addr; /* Address of image */ - unsigned long bootaddr; /* Address to put the bootline */ - char *bootline; /* Text of the bootline */ - char *tmp; /* Temporary char pointer */ - char build_buf[128]; /* Buffer for building the bootline */ - - /* --------------------------------------------------- - * + unsigned long addr; /* Address of image */ + unsigned long bootaddr; /* Address to put the bootline */ + char *bootline; /* Text of the bootline */ + char *tmp; /* Temporary char pointer */ + char build_buf[128]; /* Buffer for building the bootline */ + int ptr = 0; +#ifdef CONFIG_X86 + struct e820info *info; + struct e820entry *data; +#endif + + /* * Check the loadaddr variable. * If we don't know where the image is then we're done. */ - if (argc < 2) addr = load_addr; else @@ -167,7 +234,8 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_CMD_NET) /* - * Check to see if we need to tftp the image ourselves before starting + * Check to see if we need to tftp the image ourselves + * before starting */ if ((argc == 2) && (strcmp(argv[1], "tftp") == 0)) { if (net_loop(TFTPGET) <= 0) @@ -177,18 +245,18 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif - /* This should equate - * to NV_RAM_ADRS + NV_BOOT_OFFSET + NV_ENET_OFFSET + /* + * This should equate to + * NV_RAM_ADRS + NV_BOOT_OFFSET + NV_ENET_OFFSET * from the VxWorks BSP header files. * This will vary from board to board */ - #if defined(CONFIG_WALNUT) - tmp = (char *) CONFIG_SYS_NVRAM_BASE_ADDR + 0x500; + tmp = (char *)CONFIG_SYS_NVRAM_BASE_ADDR + 0x500; eth_getenv_enetaddr("ethaddr", (uchar *)build_buf); memcpy(tmp, &build_buf[3], 3); #elif defined(CONFIG_SYS_VXWORKS_MAC_PTR) - tmp = (char *) CONFIG_SYS_VXWORKS_MAC_PTR; + tmp = (char *)CONFIG_SYS_VXWORKS_MAC_PTR; eth_getenv_enetaddr("ethaddr", (uchar *)build_buf); memcpy(tmp, build_buf, 6); #else @@ -197,169 +265,135 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* * Use bootaddr to find the location in memory that VxWorks - * will look for the bootline string. The default value for - * PowerPC is LOCAL_MEM_LOCAL_ADRS + BOOT_LINE_OFFSET which - * defaults to 0x4200 + * will look for the bootline string. The default value is + * (LOCAL_MEM_LOCAL_ADRS + BOOT_LINE_OFFSET) as defined by + * VxWorks BSP. For example, on PowerPC it defaults to 0x4200. */ tmp = getenv("bootaddr"); - if (!tmp) - bootaddr = CONFIG_SYS_VXWORKS_BOOT_ADDR; - else - bootaddr = simple_strtoul(tmp, NULL, 16); - - /* - * Check to see if the bootline is defined in the 'bootargs' - * parameter. If it is not defined, we may be able to - * construct the info - */ - bootline = getenv("bootargs"); - if (bootline) { - memcpy((void *)bootaddr, bootline, - max(strlen(bootline), (size_t)255)); - flush_cache(bootaddr, max(strlen(bootline), (size_t)255)); + if (!tmp) { + printf("## VxWorks bootline address not specified\n"); } else { - sprintf(build_buf, CONFIG_SYS_VXWORKS_BOOT_DEVICE); - tmp = getenv("bootfile"); - if (tmp) - sprintf(&build_buf[strlen(build_buf)], - "%s:%s ", CONFIG_SYS_VXWORKS_SERVERNAME, tmp); - else - sprintf(&build_buf[strlen(build_buf)], - "%s:file ", CONFIG_SYS_VXWORKS_SERVERNAME); + bootaddr = simple_strtoul(tmp, NULL, 16); - tmp = getenv("ipaddr"); - if (tmp) - sprintf(&build_buf[strlen(build_buf)], "e=%s ", tmp); + /* + * Check to see if the bootline is defined in the 'bootargs' + * parameter. If it is not defined, we may be able to + * construct the info. + */ + bootline = getenv("bootargs"); + if (bootline) { + memcpy((void *)bootaddr, bootline, + max(strlen(bootline), (size_t)255)); + flush_cache(bootaddr, max(strlen(bootline), + (size_t)255)); + } else { + tmp = getenv("bootdev"); + if (tmp) + ptr = sprintf(build_buf, tmp); + else + printf("## VxWorks boot device not specified\n"); + + tmp = getenv("bootfile"); + if (tmp) + ptr += sprintf(build_buf + ptr, + "host:%s ", tmp); + else + ptr += sprintf(build_buf + ptr, + "host:vxWorks "); + + /* + * The following parameters are only needed if 'bootdev' + * is an ethernet device, otherwise they are optional. + */ + tmp = getenv("ipaddr"); + if (tmp) { + ptr += sprintf(build_buf + ptr, "e=%s", tmp); + tmp = getenv("netmask"); + if (tmp) { + u32 mask = getenv_ip("netmask").s_addr; + ptr += sprintf(build_buf + ptr, + ":%08x ", ntohl(mask)); + } else { + ptr += sprintf(build_buf + ptr, " "); + } + } + + tmp = getenv("serverip"); + if (tmp) + ptr += sprintf(build_buf + ptr, "h=%s ", tmp); + + tmp = getenv("gatewayip"); + if (tmp) + ptr += sprintf(build_buf + ptr, "g=%s ", tmp); + + tmp = getenv("hostname"); + if (tmp) + ptr += sprintf(build_buf + ptr, "tn=%s ", tmp); + + tmp = getenv("othbootargs"); + if (tmp) + ptr += sprintf(build_buf + ptr, tmp); + + memcpy((void *)bootaddr, build_buf, + max(strlen(build_buf), (size_t)255)); + flush_cache(bootaddr, max(strlen(build_buf), + (size_t)255)); + } - tmp = getenv("serverip"); - if (tmp) - sprintf(&build_buf[strlen(build_buf)], "h=%s ", tmp); + printf("## Using bootline (@ 0x%lx): %s\n", bootaddr, + (char *)bootaddr); + } - tmp = getenv("hostname"); - if (tmp) - sprintf(&build_buf[strlen(build_buf)], "tn=%s ", tmp); +#ifdef CONFIG_X86 + /* + * Since E820 information is critical to the kernel, if we don't + * specify these in the environments, use a default one. + */ + tmp = getenv("e820data"); + if (tmp) + data = (struct e820entry *)simple_strtoul(tmp, NULL, 16); + else + data = (struct e820entry *)VXWORKS_E820_DATA_ADDR; + tmp = getenv("e820info"); + if (tmp) + info = (struct e820info *)simple_strtoul(tmp, NULL, 16); + else + info = (struct e820info *)VXWORKS_E820_INFO_ADDR; -#ifdef CONFIG_SYS_VXWORKS_ADD_PARAMS - sprintf(&build_buf[strlen(build_buf)], - CONFIG_SYS_VXWORKS_ADD_PARAMS); + memset(info, 0, sizeof(struct e820info)); + info->sign = E820_SIGNATURE; + info->entries = install_e820_map(E820MAX, data); + info->addr = (info->entries - 1) * sizeof(struct e820entry) + + VXWORKS_E820_DATA_ADDR; #endif - memcpy((void *)bootaddr, build_buf, - max(strlen(build_buf), (size_t)255)); - flush_cache(bootaddr, max(strlen(build_buf), (size_t)255)); - } - /* * If the data at the load address is an elf image, then * treat it like an elf image. Otherwise, assume that it is a - * binary image + * binary image. */ - - if (valid_elf_image(addr)) { + if (valid_elf_image(addr)) addr = load_elf_image_shdr(addr); - } else { + else puts("## Not an ELF image, assuming binary\n"); - /* leave addr as load_addr */ - } - printf("## Using bootline (@ 0x%lx): %s\n", bootaddr, - (char *) bootaddr); printf("## Starting vxWorks at 0x%08lx ...\n", addr); dcache_disable(); - ((void (*)(int)) addr) (0); +#ifdef CONFIG_X86 + /* VxWorks on x86 uses stack to pass parameters */ + ((asmlinkage void (*)(int))addr)(0); +#else + ((void (*)(int))addr)(0); +#endif puts("## vxWorks terminated\n"); - return 1; -} - -/* ====================================================================== - * A very simple elf loader, assumes the image is valid, returns the - * entry point address. - * ====================================================================== */ -static unsigned long load_elf_image_phdr(unsigned long addr) -{ - Elf32_Ehdr *ehdr; /* Elf header structure pointer */ - Elf32_Phdr *phdr; /* Program header structure pointer */ - int i; - - ehdr = (Elf32_Ehdr *) addr; - phdr = (Elf32_Phdr *) (addr + ehdr->e_phoff); - - /* Load each program header */ - for (i = 0; i < ehdr->e_phnum; ++i) { - void *dst = (void *)(uintptr_t) phdr->p_paddr; - void *src = (void *) addr + phdr->p_offset; - debug("Loading phdr %i to 0x%p (%i bytes)\n", - i, dst, phdr->p_filesz); - if (phdr->p_filesz) - memcpy(dst, src, phdr->p_filesz); - if (phdr->p_filesz != phdr->p_memsz) - memset(dst + phdr->p_filesz, 0x00, - phdr->p_memsz - phdr->p_filesz); - flush_cache((unsigned long)dst, phdr->p_filesz); - ++phdr; - } - - return ehdr->e_entry; -} - -static unsigned long load_elf_image_shdr(unsigned long addr) -{ - Elf32_Ehdr *ehdr; /* Elf header structure pointer */ - Elf32_Shdr *shdr; /* Section header structure pointer */ - unsigned char *strtab = 0; /* String table pointer */ - unsigned char *image; /* Binary image pointer */ - int i; /* Loop counter */ - - /* -------------------------------------------------- */ - ehdr = (Elf32_Ehdr *) addr; - - /* Find the section header string table for output info */ - shdr = (Elf32_Shdr *) (addr + ehdr->e_shoff + - (ehdr->e_shstrndx * sizeof(Elf32_Shdr))); - - if (shdr->sh_type == SHT_STRTAB) - strtab = (unsigned char *) (addr + shdr->sh_offset); - - /* Load each appropriate section */ - for (i = 0; i < ehdr->e_shnum; ++i) { - shdr = (Elf32_Shdr *) (addr + ehdr->e_shoff + - (i * sizeof(Elf32_Shdr))); - - if (!(shdr->sh_flags & SHF_ALLOC) - || shdr->sh_addr == 0 || shdr->sh_size == 0) { - continue; - } - - if (strtab) { - debug("%sing %s @ 0x%08lx (%ld bytes)\n", - (shdr->sh_type == SHT_NOBITS) ? - "Clear" : "Load", - &strtab[shdr->sh_name], - (unsigned long) shdr->sh_addr, - (long) shdr->sh_size); - } - - if (shdr->sh_type == SHT_NOBITS) { - memset((void *)(uintptr_t) shdr->sh_addr, 0, - shdr->sh_size); - } else { - image = (unsigned char *) addr + shdr->sh_offset; - memcpy((void *)(uintptr_t) shdr->sh_addr, - (const void *) image, - shdr->sh_size); - } - flush_cache(shdr->sh_addr, shdr->sh_size); - } - - return ehdr->e_entry; + return 1; } -/* ====================================================================== */ U_BOOT_CMD( - bootelf, 3, 0, do_bootelf, + bootelf, 3, 0, do_bootelf, "Boot from an ELF image in memory", "[-p|-s] [address]\n" "\t- load ELF image at [address] via program headers (-p)\n" @@ -367,7 +401,7 @@ U_BOOT_CMD( ); U_BOOT_CMD( - bootvx, 2, 0, do_bootvx, + bootvx, 2, 0, do_bootvx, "Boot vxWorks from an ELF image", " [address] - load address of vxWorks ELF image." ); diff --git a/common/cmd_remoteproc.c b/common/cmd_remoteproc.c new file mode 100644 index 0000000..794a406 --- /dev/null +++ b/common/cmd_remoteproc.c @@ -0,0 +1,281 @@ +/* + * (C) Copyright 2015 + * Texas Instruments Incorporated - http://www.ti.com/ + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <command.h> +#include <dm.h> +#include <errno.h> +#include <malloc.h> +#include <remoteproc.h> + +/** + * print_remoteproc_list() - print all the remote processor devices + * + * Return: 0 if no error, else returns appropriate error value. + */ +static int print_remoteproc_list(void) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + char *type; + + ret = uclass_get(UCLASS_REMOTEPROC, &uc); + if (ret) { + printf("Cannot find Remote processor class\n"); + return ret; + } + + uclass_foreach_dev(dev, uc) { + struct dm_rproc_uclass_pdata *uc_pdata; + const struct dm_rproc_ops *ops = rproc_get_ops(dev); + + uc_pdata = dev_get_uclass_platdata(dev); + + switch (uc_pdata->mem_type) { + case RPROC_INTERNAL_MEMORY_MAPPED: + type = "internal memory mapped"; + break; + default: + type = "unknown"; + break; + } + printf("%d - Name:'%s' type:'%s' supports: %s%s%s%s%s%s\n", + dev->seq, + uc_pdata->name, + type, + ops->load ? "load " : "", + ops->start ? "start " : "", + ops->stop ? "stop " : "", + ops->reset ? "reset " : "", + ops->is_running ? "is_running " : "", + ops->ping ? "ping " : ""); + } + return 0; +} + +/** + * do_rproc_init() - do basic initialization + * @cmdtp: unused + * @flag: unused + * @argc: unused + * @argv: unused + * + * Return: 0 if no error, else returns appropriate error value. + */ +static int do_rproc_init(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (rproc_is_initialized()) { + printf("\tRemote Processors are already initialized\n"); + } else { + if (!rproc_init()) + return 0; + printf("Few Remote Processors failed to be initalized\n"); + } + + return CMD_RET_FAILURE; +} + +/** + * do_remoteproc_list() - print list of remote proc devices. + * @cmdtp: unused + * @flag: unused + * @argc: unused + * @argv: unused + * + * Return: 0 if no error, else returns appropriate error value. + */ +static int do_remoteproc_list(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (!rproc_is_initialized()) { + printf("\t Remote Processors is not initialized\n"); + return CMD_RET_USAGE; + } + + if (print_remoteproc_list()) + return CMD_RET_FAILURE; + + return 0; +} + +/** + * do_remoteproc_load() - Load a remote processor with binary image + * @cmdtp: unused + * @flag: unused + * @argc: argument count for the load function + * @argv: arguments for the load function + * + * Return: 0 if no error, else returns appropriate error value. + */ +static int do_remoteproc_load(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong addr, size; + int id, ret; + + if (argc != 4) + return CMD_RET_USAGE; + + id = (int)simple_strtoul(argv[1], NULL, 3); + addr = simple_strtoul(argv[2], NULL, 16); + + size = simple_strtoul(argv[3], NULL, 16); + + if (!size) { + printf("\t Expect some size??\n"); + return CMD_RET_USAGE; + } + + if (!rproc_is_initialized()) { + printf("\tRemote Processors are not initialized\n"); + return CMD_RET_USAGE; + } + + ret = rproc_load(id, addr, size); + printf("Load Remote Processor %d with data@addr=0x%08lx %lu bytes:%s\n", + id, addr, size, ret ? " Failed!" : " Success!"); + + return ret ? CMD_RET_FAILURE : 0; +} + +/** + * do_remoteproc_wrapper() - wrapper for various rproc commands + * @cmdtp: unused + * @flag: unused + * @argc: argument count for the rproc command + * @argv: arguments for the rproc command + * + * Most of the commands just take id as a parameter andinvoke various + * helper routines in remote processor core. by using a set of + * common checks, we can reduce the amount of code used for this. + * + * Return: 0 if no error, else returns appropriate error value. + */ +static int do_remoteproc_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + int id, ret = CMD_RET_USAGE; + + if (argc != 2) + return CMD_RET_USAGE; + + id = (int)simple_strtoul(argv[1], NULL, 3); + + if (!rproc_is_initialized()) { + printf("\tRemote Processors are not initialized\n"); + return CMD_RET_USAGE; + } + + if (!strcmp(argv[0], "start")) { + ret = rproc_start(id); + } else if (!strcmp(argv[0], "stop")) { + ret = rproc_stop(id); + } else if (!strcmp(argv[0], "reset")) { + ret = rproc_reset(id); + } else if (!strcmp(argv[0], "is_running")) { + ret = rproc_is_running(id); + if (!ret) { + printf("Remote processor is Running\n"); + } else if (ret == 1) { + printf("Remote processor is NOT Running\n"); + ret = 0; + } + /* Else error.. */ + } else if (!strcmp(argv[0], "ping")) { + ret = rproc_ping(id); + if (!ret) { + printf("Remote processor responds 'Pong'\n"); + } else if (ret == 1) { + printf("No response from Remote processor\n"); + ret = 0; + } + /* Else error.. */ + } + + if (ret < 0) + printf("Operation Failed with error (%d)\n", ret); + + return ret ? CMD_RET_FAILURE : 0; +} + +static cmd_tbl_t cmd_remoteproc_sub[] = { + U_BOOT_CMD_MKENT(init, 0, 1, do_rproc_init, + "Enumerate and initialize all processors", ""), + U_BOOT_CMD_MKENT(list, 0, 1, do_remoteproc_list, + "list remote processors", ""), + U_BOOT_CMD_MKENT(load, 5, 1, do_remoteproc_load, + "Load remote processor with provided image", + "<id> [addr] [size]\n" + "- id: ID of the remote processor(see 'list' cmd)\n" + "- addr: Address in memory of the image to loadup\n" + "- size: Size of the image to loadup\n"), + U_BOOT_CMD_MKENT(start, 1, 1, do_remoteproc_wrapper, + "Start remote processor", + "id - ID of the remote processor (see 'list' cmd)\n"), + U_BOOT_CMD_MKENT(stop, 1, 1, do_remoteproc_wrapper, + "Stop remote processor", + "id - ID of the remote processor (see 'list' cmd)\n"), + U_BOOT_CMD_MKENT(reset, 1, 1, do_remoteproc_wrapper, + "Reset remote processor", + "id - ID of the remote processor (see 'list' cmd)\n"), + U_BOOT_CMD_MKENT(is_running, 1, 1, do_remoteproc_wrapper, + "Check to see if remote processor is running\n", + "id - ID of the remote processor (see 'list' cmd)\n"), + U_BOOT_CMD_MKENT(ping, 1, 1, do_remoteproc_wrapper, + "Ping to communicate with remote processor\n", + "id - ID of the remote processor (see 'list' cmd)\n"), +}; + +/** + * do_remoteproc() - (replace: short desc) + * @cmdtp: unused + * @flag: unused + * @argc: argument count + * @argv: argument list + * + * parses up the command table to invoke the correct command. + * + * Return: 0 if no error, else returns appropriate error value. + */ +static int do_remoteproc(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + cmd_tbl_t *c = NULL; + + /* Strip off leading 'rproc' command argument */ + argc--; + argv++; + + if (argc) + c = find_cmd_tbl(argv[0], cmd_remoteproc_sub, + ARRAY_SIZE(cmd_remoteproc_sub)); + if (c) + return c->cmd(cmdtp, flag, argc, argv); + + return CMD_RET_USAGE; +} + +U_BOOT_CMD(rproc, 5, 1, do_remoteproc, + "Control operation of remote processors in an SoC", + " [init|list|load|start|stop|reset|is_running|ping]\n" + "\t\t Where:\n" + "\t\t[addr] is a memory address\n" + "\t\t<id> is a numerical identifier for the remote processor\n" + "\t\t provided by 'list' command.\n" + "\t\tNote: Remote processors must be initalized prior to usage\n" + "\t\tNote: Services are dependent on the driver capability\n" + "\t\t 'list' command shows the capability of each device\n" + "\n\tSubcommands:\n" + "\tinit - Enumerate and initalize the remote processors\n" + "\tlist - list available remote processors\n" + "\tload <id> [addr] [size]- Load the remote processor with binary\n" + "\t image stored at address [addr] in memory\n" + "\tstart <id> - Start the remote processor(must be loaded)\n" + "\tstop <id> - Stop the remote processor\n" + "\treset <id> - Reset the remote processor\n" + "\tis_running <id> - Reports if the remote processor is running\n" + "\tping <id> - Ping the remote processor for communication\n"); diff --git a/common/image-fit.c b/common/image-fit.c index 28f7aa8..c531ee7 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1030,8 +1030,10 @@ int fit_image_verify(const void *fit, int image_noffset) strlen(FIT_SIG_NODENAME))) { ret = fit_image_check_sig(fit, noffset, data, size, -1, &err_msg); - if (ret) + if (ret) { puts("- "); + goto error; + } else puts("+ "); } diff --git a/common/malloc_simple.c b/common/malloc_simple.c index c745863..479a1e4 100644 --- a/common/malloc_simple.c +++ b/common/malloc_simple.c @@ -19,10 +19,13 @@ void *malloc_simple(size_t bytes) void *ptr; new_ptr = gd->malloc_ptr + bytes; + debug("%s: size=%zx, ptr=%lx, limit=%lx\n", __func__, bytes, new_ptr, + gd->malloc_limit); if (new_ptr > gd->malloc_limit) return NULL; ptr = map_sysmem(gd->malloc_base + gd->malloc_ptr, bytes); gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr)); + return ptr; } @@ -37,10 +40,11 @@ void *memalign_simple(size_t align, size_t bytes) return NULL; ptr = map_sysmem(addr, bytes); gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr)); + return ptr; } -#ifdef CONFIG_SYS_MALLOC_SIMPLE +#if CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) void *calloc(size_t nmemb, size_t elem_size) { size_t size = nmemb * elem_size; diff --git a/common/spl/spl.c b/common/spl/spl.c index a5892d7..4b319d6 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -347,8 +347,17 @@ ulong spl_relocate_stack_gd(void) memcpy(new_gd, (void *)gd, sizeof(gd_t)); gd = new_gd; - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); +#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE + if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) { + if (!(gd->flags & GD_FLG_SPL_INIT)) + panic("spl_init must be called before heap reloc"); + + ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN; + gd->malloc_base = ptr; + gd->malloc_limit = CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN; + gd->malloc_ptr = 0; + } +#endif return ptr; #else diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index f4ff7c5..b22fdb3 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -8,7 +8,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index 7783c7d..d9add78 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -9,8 +9,9 @@ CONFIG_USB1_VBUS_PIN="PB10" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_USB_EHCI_HCD=y +CONFIG_AXP152_POWER=y diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index ccf35c7..f438e50 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -18,3 +18,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_USB_EHCI_HCD=y +CONFIG_SUNXI_NO_PMIC=y diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 1f68d98..34bf4ea 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -14,7 +14,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index c9d0f47..678132c 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -8,7 +8,7 @@ CONFIG_USB0_VBUS_DET="PH5" CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index 4a257b3..ffcdf29 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -6,7 +6,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index a7f1395..9507b87 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -9,7 +9,7 @@ CONFIG_VIDEO_VGA=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index e8c3d18..0b7ab62 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -8,7 +8,7 @@ CONFIG_USB0_VBUS_DET="PH5" CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index 7c41aa8..fc1be7d 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index 57ff52d..8262be5 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -15,7 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig index b9692dc..5dd9a16 100644 --- a/configs/Auxtek-T003_defconfig +++ b/configs/Auxtek-T003_defconfig @@ -8,8 +8,8 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_USB_EHCI_HCD=y +CONFIG_AXP152_POWER=y diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index c019176..c1a58d8 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -6,8 +6,8 @@ CONFIG_USB1_VBUS_PIN="PG13" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_USB_EHCI_HCD=y +CONFIG_AXP152_POWER=y diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 898631d..d9b1bd6 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -7,7 +7,7 @@ CONFIG_GMAC_TX_DELAY=3 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index e9909d9..9226df5 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -9,7 +9,7 @@ CONFIG_GMAC_TX_DELAY=3 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig new file mode 100644 index 0000000..c4e8079 --- /dev/null +++ b/configs/CHIP_defconfig @@ -0,0 +1,14 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y +# CONFIG_MMC is not set +CONFIG_USB0_VBUS_PIN="PB10" +CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2" +# CONFIG_CMD_IMLS is not set +CONFIG_AXP_DCDC2_VOLT=1300 +CONFIG_AXP_ALDO3_VOLT=3300 +CONFIG_AXP_ALDO4_VOLT=3300 +CONFIG_USB_MUSB_GADGET=y diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index 7c8eca8..3ffd34e 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -12,7 +12,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_ETH_DESIGNWARE=y -CONFIG_AXP221_DLDO1_VOLT=3300 -CONFIG_AXP221_ALDO1_VOLT=3300 +CONFIG_AXP_DLDO1_VOLT=3300 +CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index 1725f65..3257aae 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index 35f644a..2ce8cb1 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -22,6 +22,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_ETH_DESIGNWARE=y -CONFIG_AXP221_ALDO1_VOLT=3300 -CONFIG_AXP221_ELDO3_VOLT=1800 +CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index 9bcaed1..4b9d722 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -6,7 +6,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index bbda5bf..c884115 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -6,7 +6,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index e1b76ce..efe2317 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -8,7 +8,7 @@ CONFIG_GMAC_TX_DELAY=1 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Et_q8_v1_6_defconfig b/configs/Et_q8_v1_6_defconfig deleted file mode 100644 index 65b8e1a..0000000 --- a/configs/Et_q8_v1_6_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN8I_A33=y -CONFIG_DRAM_CLK=480 -CONFIG_DRAM_ZQ=15291 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" -CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:168,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" -CONFIG_VIDEO_LCD_DCLK_PHASE=0 -CONFIG_VIDEO_LCD_POWER="PH7" -CONFIG_VIDEO_LCD_BL_EN="PH6" -CONFIG_VIDEO_LCD_BL_PWM="PH0" -CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-et-q8-v1.6" -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -CONFIG_AXP221_DLDO1_VOLT=3300 -CONFIG_AXP221_ALDO1_VOLT=3000 -CONFIG_USB_MUSB_HOST=y diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig index 35c746c..02bcdbf 100644 --- a/configs/Hummingbird_A31_defconfig +++ b/configs/Hummingbird_A31_defconfig @@ -14,5 +14,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_ETH_DESIGNWARE=y -CONFIG_AXP221_ALDO1_VOLT=3300 +CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index 9ef06a7..fef3685 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig b/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig deleted file mode 100644 index 40ccf8f..0000000 --- a/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN8I_A33=y -CONFIG_DRAM_CLK=480 -CONFIG_DRAM_ZQ=15291 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" -CONFIG_USB0_ID_DET="PH8" -CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" -CONFIG_VIDEO_LCD_DCLK_PHASE=0 -CONFIG_VIDEO_LCD_POWER="PH7" -CONFIG_VIDEO_LCD_BL_EN="PH6" -CONFIG_VIDEO_LCD_BL_PWM="PH0" -CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ippo-q8h-v1.2" -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -CONFIG_AXP221_DLDO1_VOLT=3300 -CONFIG_AXP221_ALDO1_VOLT=3000 -CONFIG_USB_MUSB_HOST=y diff --git a/configs/Ippo_q8h_v1_2_defconfig b/configs/Ippo_q8h_v1_2_defconfig deleted file mode 100644 index 5b49c44..0000000 --- a/configs/Ippo_q8h_v1_2_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN8I_A23=y -CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=63306 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" -CONFIG_USB0_ID_DET="PH8" -CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" -CONFIG_VIDEO_LCD_DCLK_PHASE=0 -CONFIG_VIDEO_LCD_POWER="PH7" -CONFIG_VIDEO_LCD_BL_EN="PH6" -CONFIG_VIDEO_LCD_BL_PWM="PH0" -CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v1.2" -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -CONFIG_AXP221_DLDO1_VOLT=3300 -CONFIG_AXP221_ALDO1_VOLT=3000 -CONFIG_USB_MUSB_HOST=y diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig deleted file mode 100644 index 5316860..0000000 --- a/configs/Ippo_q8h_v5_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN8I_A23=y -CONFIG_DRAM_CLK=480 -CONFIG_DRAM_ZQ=63351 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" -CONFIG_USB0_ID_DET="PH8" -CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:168,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" -CONFIG_VIDEO_LCD_DCLK_PHASE=0 -CONFIG_VIDEO_LCD_POWER="PH7" -CONFIG_VIDEO_LCD_BL_EN="PH6" -CONFIG_VIDEO_LCD_BL_PWM="PH0" -CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5" -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -CONFIG_AXP221_DLDO1_VOLT=3300 -CONFIG_AXP221_ALDO1_VOLT=3000 -CONFIG_USB_MUSB_HOST=y diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig index 0b64b60..378abce 100644 --- a/configs/Linksprite_pcDuino3_Nano_defconfig +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -8,7 +8,7 @@ CONFIG_GMAC_TX_DELAY=3 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2)" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2)" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index cced032..c3f0421 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -6,7 +6,7 @@ CONFIG_DRAM_ZQ=122 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2)" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2)" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index 13b7ed3..9d8d325 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -6,7 +6,7 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig index 5e37485..49bb26a 100644 --- a/configs/MK808C_defconfig +++ b/configs/MK808C_defconfig @@ -5,7 +5,6 @@ CONFIG_DRAM_CLK=384 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig index a60ce34..5559444 100644 --- a/configs/MSI_Primo73_defconfig +++ b/configs/MSI_Primo73_defconfig @@ -10,7 +10,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig index 9d667b7..3d71bf5 100644 --- a/configs/MSI_Primo81_defconfig +++ b/configs/MSI_Primo81_defconfig @@ -16,7 +16,7 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set -CONFIG_AXP221_DLDO1_VOLT=3300 +CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_MUSB_HOST=y CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27 CONFIG_VIDEO_LCD_SSD2828_RESET="PA26" diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig index 5e31ef6..e81e6b6 100644 --- a/configs/Mele_A1000G_quad_defconfig +++ b/configs/Mele_A1000G_quad_defconfig @@ -12,9 +12,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_ETH_DESIGNWARE=y -CONFIG_AXP221_DCDC1_VOLT=3300 -CONFIG_AXP221_DLDO1_VOLT=3300 -CONFIG_AXP221_DLDO4_VOLT=3300 -CONFIG_AXP221_ALDO1_VOLT=3300 +CONFIG_AXP_DCDC1_VOLT=3300 +CONFIG_AXP_DLDO1_VOLT=3300 +CONFIG_AXP_DLDO4_VOLT=3300 +CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index b983c8c..f076e30 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -6,7 +6,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig index 774a92f..38cd845 100644 --- a/configs/Mele_I7_defconfig +++ b/configs/Mele_I7_defconfig @@ -12,8 +12,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_ETH_DESIGNWARE=y -CONFIG_AXP221_DCDC1_VOLT=3300 -CONFIG_AXP221_DLDO1_VOLT=3300 -CONFIG_AXP221_DLDO4_VOLT=3300 -CONFIG_AXP221_ALDO1_VOLT=3300 +CONFIG_AXP_DCDC1_VOLT=3300 +CONFIG_AXP_DLDO1_VOLT=3300 +CONFIG_AXP_DLDO4_VOLT=3300 +CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig index 5c9796a..d72dcc0 100644 --- a/configs/Mele_M3_defconfig +++ b/configs/Mele_M3_defconfig @@ -9,7 +9,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index b52e3c2..93a28a6 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -12,8 +12,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_ETH_DESIGNWARE=y -CONFIG_AXP221_DCDC1_VOLT=3300 -CONFIG_AXP221_DLDO1_VOLT=3300 -CONFIG_AXP221_DLDO4_VOLT=3300 -CONFIG_AXP221_ALDO1_VOLT=3300 +CONFIG_AXP_DCDC1_VOLT=3300 +CONFIG_AXP_DLDO1_VOLT=3300 +CONFIG_AXP_DLDO4_VOLT=3300 +CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index 314f97b..53f9bfe 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -6,7 +6,6 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index d67bb90..00c671b 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -10,7 +10,7 @@ CONFIG_GMAC_TX_DELAY=3 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index 71d236b..a865255 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -12,7 +12,7 @@ CONFIG_GMAC_TX_DELAY=3 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index 720f3dc..013c35e 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -9,4 +9,3 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set -CONFIG_AXP221_ALDO1_VOLT=3000 diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig new file mode 100644 index 0000000..17c30a8 --- /dev/null +++ b/configs/Sinovoip_BPI_M2_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN6I=y +CONFIG_DRAM_CLK=432 +CONFIG_USB1_VBUS_PIN="" +CONFIG_USB2_VBUS_PIN="" +CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_ETH_DESIGNWARE=y +CONFIG_AXP_DLDO1_VOLT=3000 +CONFIG_AXP_ALDO1_VOLT=3300 +CONFIG_AXP_ALDO2_VOLT=1800 +CONFIG_USB_EHCI_HCD=y diff --git a/configs/TZX-Q8-713B7_defconfig b/configs/TZX-Q8-713B7_defconfig deleted file mode 100644 index f5e3574..0000000 --- a/configs/TZX-Q8-713B7_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN5I=y -CONFIG_DRAM_CLK=408 -CONFIG_MMC0_CD_PIN="PG0" -CONFIG_USB0_VBUS_PIN="PG12" -CONFIG_USB0_VBUS_DET="PG1" -CONFIG_AXP_GPIO=y -# CONFIG_VIDEO_HDMI is not set -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" -CONFIG_VIDEO_LCD_POWER="AXP0-0" -CONFIG_VIDEO_LCD_BL_EN="AXP0-1" -CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-tzx-q8-713b7" -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -CONFIG_USB_MUSB_HOST=y diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index 5417814..d36a5dc 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -20,7 +20,6 @@ CONFIG_VIDEO_LCD_TL059WV5C0=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig index a54ad4f..5f3d624 100644 --- a/configs/Wexler_TAB7200_defconfig +++ b/configs/Wexler_TAB7200_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig index 66b51bc..bfc8cba 100644 --- a/configs/Wits_Pro_A20_DKT_defconfig +++ b/configs/Wits_Pro_A20_DKT_defconfig @@ -11,7 +11,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig index 206fd48..fc43cc5 100644 --- a/configs/Wobo_i5_defconfig +++ b/configs/Wobo_i5_defconfig @@ -7,7 +7,6 @@ CONFIG_USB1_VBUS_PIN="PG12" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index e26816c..65c1d8e 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -19,7 +19,6 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index b52ddfd..011239b 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -13,3 +13,5 @@ CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_SPI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_DM_MMC=y diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig index 65c7b90..03c558c 100644 --- a/configs/am335x_gp_evm_defconfig +++ b/configs/am335x_gp_evm_defconfig @@ -11,3 +11,5 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_OF_CONTROL=y CONFIG_SPI_FLASH=y CONFIG_RSA=y +CONFIG_DM_ETH=y +CONFIG_DM_MMC=y diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig new file mode 100644 index 0000000..53fb0bf --- /dev/null +++ b/configs/am437x_gp_evm_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM43XX_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_DISABLE_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_DM_MMC=y diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig new file mode 100644 index 0000000..02485f8 --- /dev/null +++ b/configs/am437x_sk_evm_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM43XX_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm" +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_DISABLE_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_DM_MMC=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig new file mode 100644 index 0000000..f6566bf --- /dev/null +++ b/configs/am57xx_evm_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_OMAP54XX=y +CONFIG_TARGET_BEAGLE_X15=y +CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15" +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_DM_MMC=y diff --git a/configs/atngw100_defconfig b/configs/atngw100_defconfig index 043f6bf..5b01c18 100644 --- a/configs/atngw100_defconfig +++ b/configs/atngw100_defconfig @@ -5,6 +5,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " +# CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SOURCE is not set diff --git a/configs/atngw100mkii_defconfig b/configs/atngw100mkii_defconfig index c8d9107..48ea9ba 100644 --- a/configs/atngw100mkii_defconfig +++ b/configs/atngw100mkii_defconfig @@ -5,6 +5,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " +# CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/atstk1002_defconfig b/configs/atstk1002_defconfig index d525868..1b108e5 100644 --- a/configs/atstk1002_defconfig +++ b/configs/atstk1002_defconfig @@ -5,6 +5,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " +# CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SOURCE is not set diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index 104d53d..1cfb380 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -9,7 +9,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 56316ee..fc40da8 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="bayleybay" CONFIG_TARGET_BAYLEYBAY=y CONFIG_HAVE_INTEL_ME=y +CONFIG_ENABLE_MRC_CACHE=y CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y CONFIG_VGA_BIOS_ADDR=0xfffa0000 diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 21e85f3..78a9470 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -4,6 +4,7 @@ CONFIG_VENDOR_GOOGLE=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" CONFIG_TARGET_CHROMEBOOK_LINK=y CONFIG_HAVE_MRC=y +CONFIG_ENABLE_MRC_CACHE=y CONFIG_HAVE_VGA_BIOS=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set @@ -21,6 +22,10 @@ CONFIG_CROS_EC_LPC=y CONFIG_SPI_FLASH=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DM_TPM=y CONFIG_TPM_TIS_LPC=y CONFIG_VIDEO_VESA=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index 70a22a9..663aab0 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_GOOGLE=y CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther" CONFIG_TARGET_CHROMEBOX_PANTHER=y CONFIG_HAVE_MRC=y +CONFIG_ENABLE_MRC_CACHE=y CONFIG_HAVE_VGA_BIOS=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig new file mode 100644 index 0000000..d5f783f --- /dev/null +++ b/configs/d2net_v2_defconfig @@ -0,0 +1,8 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NET2BIG_V2=y +CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_SPI_FLASH=y diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index e22f5f7..6f612d9 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -1,7 +1,14 @@ CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y CONFIG_TARGET_DB_88F6820_GP=y +CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp" CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index c9859a8..258e4d6 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -1,8 +1,15 @@ CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y CONFIG_TARGET_DB_MV784MP_GP=y +CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp" CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_NAND_PXA3XX=y CONFIG_SPI_FLASH=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig index 5ffe104..c69d404 100644 --- a/configs/dbau1000_defconfig +++ b/configs/dbau1000_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_DBAU1X00=y CONFIG_SYS_EXTRA_OPTIONS="DBAU1000" CONFIG_SYS_PROMPT="DbAu1xx0 # " # CONFIG_CMD_BDI is not set +# CONFIG_CMD_ELF is not set # CONFIG_CMD_RUN is not set # CONFIG_CMD_SAVEENV is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig index 84e369a..2e38812 100644 --- a/configs/dbau1100_defconfig +++ b/configs/dbau1100_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_DBAU1X00=y CONFIG_DBAU1100=y CONFIG_SYS_PROMPT="DbAu1xx0 # " # CONFIG_CMD_BDI is not set +# CONFIG_CMD_ELF is not set # CONFIG_CMD_RUN is not set # CONFIG_CMD_SAVEENV is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig index 8a9583b..f61e7b6 100644 --- a/configs/dbau1500_defconfig +++ b/configs/dbau1500_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_DBAU1X00=y CONFIG_DBAU1500=y CONFIG_SYS_PROMPT="DbAu1xx0 # " # CONFIG_CMD_BDI is not set +# CONFIG_CMD_ELF is not set # CONFIG_CMD_RUN is not set # CONFIG_CMD_SAVEENV is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/dbau1550_defconfig b/configs/dbau1550_defconfig index 333a922..7f1bdf4 100644 --- a/configs/dbau1550_defconfig +++ b/configs/dbau1550_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_DBAU1X00=y CONFIG_DBAU1550=y CONFIG_SYS_PROMPT="DbAu1xx0 # " # CONFIG_CMD_BDI is not set +# CONFIG_CMD_ELF is not set # CONFIG_CMD_RUN is not set # CONFIG_CMD_SAVEENV is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/dbau1550_el_defconfig b/configs/dbau1550_el_defconfig index 5970e43..6cd0161 100644 --- a/configs/dbau1550_el_defconfig +++ b/configs/dbau1550_el_defconfig @@ -4,6 +4,7 @@ CONFIG_DBAU1550=y CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_SYS_PROMPT="DbAu1xx0 # " # CONFIG_CMD_BDI is not set +# CONFIG_CMD_ELF is not set # CONFIG_CMD_RUN is not set # CONFIG_CMD_SAVEENV is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig index 4ed14f8..04037ba 100644 --- a/configs/dlvision-10g_defconfig +++ b/configs/dlvision-10g_defconfig @@ -3,4 +3,5 @@ CONFIG_4xx=y CONFIG_TARGET_DLVISION_10G=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " +# CONFIG_CMD_ELF is not set # CONFIG_CMD_NFS is not set diff --git a/configs/dlvision_defconfig b/configs/dlvision_defconfig index 7982c17..97bdd51 100644 --- a/configs/dlvision_defconfig +++ b/configs/dlvision_defconfig @@ -1,4 +1,5 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_DLVISION=y +# CONFIG_CMD_ELF is not set # CONFIG_CMD_NFS is not set diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig index b5bd798..cce3255 100644 --- a/configs/dra72_evm_defconfig +++ b/configs/dra72_evm_defconfig @@ -1,11 +1,13 @@ CONFIG_ARM=y CONFIG_OMAP54XX=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_DRA7XX_EVM=y +CONFIG_DM_SERIAL=y CONFIG_DM_GPIO=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="dra72-evm" CONFIG_SPL=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_ADDR=0x82000000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig new file mode 100644 index 0000000..a57cd7f --- /dev/null +++ b/configs/dra74_evm_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_OMAP54XX=y +CONFIG_TARGET_DRA7XX_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_DISABLE_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_DM_GPIO=y diff --git a/configs/forfun_q88db_defconfig b/configs/forfun_q88db_defconfig deleted file mode 100644 index 30e0937..0000000 --- a/configs/forfun_q88db_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN5I=y -CONFIG_DRAM_CLK=384 -CONFIG_USB0_VBUS_PIN="PG12" -CONFIG_USB0_VBUS_DET="PG1" -CONFIG_AXP_GPIO=y -# CONFIG_VIDEO_HDMI is not set -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" -CONFIG_VIDEO_LCD_POWER="AXP0-0" -CONFIG_VIDEO_LCD_BL_EN="AXP0-1" -CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-forfun-q88db" -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -CONFIG_USB_MUSB_HOST=y diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig index 417a89c..34e74af 100644 --- a/configs/ga10h_v1_1_defconfig +++ b/configs/ga10h_v1_1_defconfig @@ -21,7 +21,6 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set -CONFIG_AXP221_DLDO1_VOLT=3300 -CONFIG_AXP221_ALDO1_VOLT=3000 +CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index d1808a5..1e1ce95 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -2,6 +2,7 @@ CONFIG_X86=y CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="galileo" CONFIG_TARGET_GALILEO=y +CONFIG_ENABLE_MRC_CACHE=y CONFIG_GENERATE_PIRQ_TABLE=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/gr_cpci_ax2000_defconfig b/configs/gr_cpci_ax2000_defconfig index f003d77..ddac3ab 100644 --- a/configs/gr_cpci_ax2000_defconfig +++ b/configs/gr_cpci_ax2000_defconfig @@ -1,4 +1,5 @@ CONFIG_SPARC=y CONFIG_TARGET_GR_CPCI_AX2000=y CONFIG_SYS_TEXT_BASE=0x00000000 +# CONFIG_CMD_ELF is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/gr_ep2s60_defconfig b/configs/gr_ep2s60_defconfig index bbf1808..0064554 100644 --- a/configs/gr_ep2s60_defconfig +++ b/configs/gr_ep2s60_defconfig @@ -1,4 +1,5 @@ CONFIG_SPARC=y CONFIG_TARGET_GR_EP2S60=y CONFIG_SYS_TEXT_BASE=0x00000000 +# CONFIG_CMD_ELF is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/gr_xc3s_1500_defconfig b/configs/gr_xc3s_1500_defconfig index 5c1442d..a05b709 100644 --- a/configs/gr_xc3s_1500_defconfig +++ b/configs/gr_xc3s_1500_defconfig @@ -1,4 +1,5 @@ CONFIG_SPARC=y CONFIG_TARGET_GR_XC3S_1500=y CONFIG_SYS_TEXT_BASE=0x00000000 +# CONFIG_CMD_ELF is not sets # CONFIG_CMD_SETEXPR is not set diff --git a/configs/grasshopper_defconfig b/configs/grasshopper_defconfig index 92a73e2..6c5c9e3 100644 --- a/configs/grasshopper_defconfig +++ b/configs/grasshopper_defconfig @@ -5,5 +5,6 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " +# CONFIG_CMD_ELF is not set # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/grsim_defconfig b/configs/grsim_defconfig index b83abb6..f0fa23f 100644 --- a/configs/grsim_defconfig +++ b/configs/grsim_defconfig @@ -2,6 +2,7 @@ CONFIG_SPARC=y CONFIG_TARGET_GRSIM=y CONFIG_SYS_TEXT_BASE=0x00000000 # CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_EDITENV is not set diff --git a/configs/grsim_leon2_defconfig b/configs/grsim_leon2_defconfig index 756a786..9c9c968 100644 --- a/configs/grsim_leon2_defconfig +++ b/configs/grsim_leon2_defconfig @@ -2,6 +2,7 @@ CONFIG_SPARC=y CONFIG_TARGET_GRSIM_LEON2=y CONFIG_SYS_TEXT_BASE=0x00000000 # CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_EDITENV is not set diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig index e9aecc3..a14de0d 100644 --- a/configs/gt90h_v4_defconfig +++ b/configs/gt90h_v4_defconfig @@ -20,7 +20,5 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set -CONFIG_AXP221_DCDC2_VOLT=1100 -CONFIG_AXP221_DLDO1_VOLT=3300 -CONFIG_AXP221_ALDO1_VOLT=3000 +CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig index d4d9524..54fa819 100644 --- a/configs/i12-tvbox_defconfig +++ b/configs/i12-tvbox_defconfig @@ -6,7 +6,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21)" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,MACPWR=SUNXI_GPH(21)" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index 211cb86..7ec54a7 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index 35f08e5..5e68769 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index bb8d080..3dea793 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index b2ba497..a8b32cb 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig index 71f9d4f..0b03e16 100644 --- a/configs/inet97fv2_defconfig +++ b/configs/inet97fv2_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig index 4760047..27b5019 100644 --- a/configs/inet98v_rev2_defconfig +++ b/configs/inet98v_rev2_defconfig @@ -15,7 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig index b51c367..153450f 100644 --- a/configs/inet9f_rev03_defconfig +++ b/configs/inet9f_rev03_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig new file mode 100644 index 0000000..f314059 --- /dev/null +++ b/configs/inetspace_v2_defconfig @@ -0,0 +1,8 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NETSPACE_V2=y +CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_SPI_FLASH=y diff --git a/configs/io_defconfig b/configs/io_defconfig index 722d95a..7b71805 100644 --- a/configs/io_defconfig +++ b/configs/io_defconfig @@ -3,4 +3,5 @@ CONFIG_4xx=y CONFIG_TARGET_IO=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " +# CONFIG_CMD_ELF is not set # CONFIG_CMD_NFS is not set diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig index 89e5cf5..63f0c37 100644 --- a/configs/iocon_defconfig +++ b/configs/iocon_defconfig @@ -3,4 +3,5 @@ CONFIG_4xx=y CONFIG_TARGET_IOCON=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " +# CONFIG_CMD_ELF is not set # CONFIG_CMD_NFS is not set diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index cedf63d..9cb8b1d 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -7,7 +7,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(19)" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(19)" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 4637087..c0d8210 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -1,9 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_KEYSTONE=y CONFIG_TARGET_K2E_EVM=y +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="k2e-evm" CONFIG_SPL=y CONFIG_SYS_PROMPT="K2E EVM # " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_DM=y CONFIG_SPI_FLASH=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig new file mode 100644 index 0000000..59020af --- /dev/null +++ b/configs/k2g_evm_defconfig @@ -0,0 +1,14 @@ +CONFIG_ARM=y +CONFIG_ARCH_KEYSTONE=y +CONFIG_TARGET_K2G_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="k2g-evm" +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_DISABLE_OF_CONTROL=y +CONFIG_SPI_FLASH=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_KEYSTONE_SERIAL=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index d0a0cbf..d5a4ef2 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -1,9 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_KEYSTONE=y CONFIG_TARGET_K2HK_EVM=y +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="k2hk-evm" CONFIG_SPL=y CONFIG_SYS_PROMPT="K2HK EVM # " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_DM=y CONFIG_SPI_FLASH=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 8d6bdbd..47fcad3 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -1,9 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_KEYSTONE=y CONFIG_TARGET_K2L_EVM=y +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="k2l-evm" CONFIG_SPL=y CONFIG_SYS_PROMPT="K2L EVM # " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_DM=y CONFIG_SPI_FLASH=y diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index b0b0d6c..d49def1 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -1,5 +1,7 @@ CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y CONFIG_TARGET_MAXBCM=y +CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp" CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 0d5bd4e..8f99f0e 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="minnowmax" CONFIG_TARGET_MINNOWMAX=y CONFIG_HAVE_INTEL_ME=y +CONFIG_ENABLE_MRC_CACHE=y CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig index 26fc4ce..ce81309 100644 --- a/configs/mixtile_loftq_defconfig +++ b/configs/mixtile_loftq_defconfig @@ -13,5 +13,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_ETH_DESIGNWARE=y -CONFIG_AXP221_ALDO1_VOLT=3300 +CONFIG_AXP_ALDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig index db437f0..aff8dfc 100644 --- a/configs/mk802_a10s_defconfig +++ b/configs/mk802_a10s_defconfig @@ -7,8 +7,8 @@ CONFIG_USB1_VBUS_PIN="PB10" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_USB_EHCI_HCD=y +CONFIG_AXP152_POWER=y diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index 68b2c5e..bed8f23 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -10,3 +10,4 @@ CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_USB_EHCI_HCD=y +CONFIG_SUNXI_NO_PMIC=y diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig index d3cb664..de1b73f 100644 --- a/configs/mk802ii_defconfig +++ b/configs/mk802ii_defconfig @@ -4,7 +4,6 @@ CONFIG_MACH_SUN4I=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/neo_defconfig b/configs/neo_defconfig index 77eefe9..1ef57ad 100644 --- a/configs/neo_defconfig +++ b/configs/neo_defconfig @@ -1,4 +1,5 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_NEO=y +# CONFIG_CMD_ELF is not set # CONFIG_CMD_NFS is not set diff --git a/configs/pb1000_defconfig b/configs/pb1000_defconfig index f24cd07..131014d 100644 --- a/configs/pb1000_defconfig +++ b/configs/pb1000_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_PB1X00=y CONFIG_SYS_EXTRA_OPTIONS="PB1000" CONFIG_SYS_PROMPT="Pb1x00 # " # CONFIG_CMD_BDI is not set +# CONFIG_CMD_ELF is not set # CONFIG_CMD_RUN is not set # CONFIG_CMD_SAVEENV is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig index c5249d6..9aa5280 100644 --- a/configs/pov_protab2_ips9_defconfig +++ b/configs/pov_protab2_ips9_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig index 2c61f51..b467b62 100644 --- a/configs/q8_a13_tablet_defconfig +++ b/configs/q8_a13_tablet_defconfig @@ -15,7 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig index 3a3afa5..7391464 100644 --- a/configs/q8_a23_tablet_800x480_defconfig +++ b/configs/q8_a23_tablet_800x480_defconfig @@ -20,6 +20,5 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set -CONFIG_AXP221_DLDO1_VOLT=3300 -CONFIG_AXP221_ALDO1_VOLT=3000 +CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig index fbbf128..16f8600 100644 --- a/configs/q8_a33_tablet_1024x600_defconfig +++ b/configs/q8_a33_tablet_1024x600_defconfig @@ -20,6 +20,5 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set -CONFIG_AXP221_DLDO1_VOLT=3300 -CONFIG_AXP221_ALDO1_VOLT=3000 +CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig index 8e8aa92..6378918 100644 --- a/configs/q8_a33_tablet_800x480_defconfig +++ b/configs/q8_a33_tablet_800x480_defconfig @@ -20,6 +20,5 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set -CONFIG_AXP221_DLDO1_VOLT=3300 -CONFIG_AXP221_ALDO1_VOLT=3000 +CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index 62c58fc..fcc681f 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -6,8 +6,8 @@ CONFIG_USB1_VBUS_PIN="PG13" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_USB_EHCI_HCD=y +CONFIG_AXP152_POWER=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index b2675c7..67ae99b 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -3,6 +3,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sandbox" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +# CONFIG_CMD_ELF is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set @@ -62,3 +63,5 @@ CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y CONFIG_UT_ENV=y +CONFIG_REMOTEPROC_SANDBOX=y +CONFIG_CMD_REMOTEPROC=y diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index d0f987c..6d39dec 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -11,7 +11,6 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/vct_platinum_onenand_small_defconfig b/configs/vct_platinum_onenand_small_defconfig index 33ce32a..47985cd 100644 --- a/configs/vct_platinum_onenand_small_defconfig +++ b/configs/vct_platinum_onenand_small_defconfig @@ -6,6 +6,7 @@ CONFIG_VCT_SMALL_IMAGE=y CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_CRC32 is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/vct_platinum_small_defconfig b/configs/vct_platinum_small_defconfig index ceb61e1..f85d3f7 100644 --- a/configs/vct_platinum_small_defconfig +++ b/configs/vct_platinum_small_defconfig @@ -5,6 +5,7 @@ CONFIG_VCT_SMALL_IMAGE=y CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set # CONFIG_CMD_CRC32 is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/vct_platinumavc_onenand_small_defconfig b/configs/vct_platinumavc_onenand_small_defconfig index 1958fcd..77dd414 100644 --- a/configs/vct_platinumavc_onenand_small_defconfig +++ b/configs/vct_platinumavc_onenand_small_defconfig @@ -6,6 +6,7 @@ CONFIG_VCT_SMALL_IMAGE=y CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_CRC32 is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/vct_platinumavc_small_defconfig b/configs/vct_platinumavc_small_defconfig index 0ac2def..8fe82fc 100644 --- a/configs/vct_platinumavc_small_defconfig +++ b/configs/vct_platinumavc_small_defconfig @@ -5,6 +5,7 @@ CONFIG_VCT_SMALL_IMAGE=y CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set # CONFIG_CMD_CRC32 is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/vct_premium_onenand_small_defconfig b/configs/vct_premium_onenand_small_defconfig index 471a005..ac6f422 100644 --- a/configs/vct_premium_onenand_small_defconfig +++ b/configs/vct_premium_onenand_small_defconfig @@ -6,6 +6,7 @@ CONFIG_VCT_SMALL_IMAGE=y CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_CRC32 is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/vct_premium_small_defconfig b/configs/vct_premium_small_defconfig index 68c0d9a..3297434 100644 --- a/configs/vct_premium_small_defconfig +++ b/configs/vct_premium_small_defconfig @@ -5,6 +5,7 @@ CONFIG_VCT_SMALL_IMAGE=y CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set # CONFIG_CMD_CRC32 is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/doc/README.scrapyard b/doc/README.scrapyard index c7b4fa3..2760f60 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,15 +12,86 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -stxgp3 powerpc mpc85xx - - Dan Malek <dan@embeddedalley.com> -stxssa powerpc mpc85xx - - Dan Malek <dan@embeddedalley.com> -cmi_mpc5xx powerpc mpc5xx - - -zeus powerpc ppc4xx - - Stefan Roese <sr@denx.de> -sbc405 powerpc ppc4xx - - -pcs440ep powerpc ppc4xx - - Stefan Roese <sr@denx.de> -p3p440 powerpc ppc4xx - - Stefan Roese <sr@denx.de> -csb272/csb472 powerpc ppc4xx - - Tolunay Orkun <torkun@nextio.com> -alpr powerpc ppc4xx - - Stefan Roese <sr@denx.de> +lcd4_lwmon5 powerpc ppc4xx b6b5e394 2015-10-02 Stefan Roese <sr@denx.de> +da830evm arm arm926ejs d7e8b2b9 2015-09-12 Nick Thompson <nick.thompson@gefanuc.com> +wireless_space arm arm926ejs b352182a 2015-09-12 Albert ARIBAUD <albert.u.boot@aribaud.net> +stxgp3 powerpc mpc85xx 2ec69b88 2015-09-02 Dan Malek <dan@embeddedalley.com> +stxssa powerpc mpc85xx 2ec69b88 2015-09-02 Dan Malek <dan@embeddedalley.com> +cmi_mpc5xx powerpc mpc5xx 972f5320 2015-09-02 +zeus powerpc ppc4xx eb5d1dc7 2015-09-02 Stefan Roese <sr@denx.de> +sbc405 powerpc ppc4xx 0e030593 2015-09-02 +pcs440ep powerpc ppc4xx 242836a8 2015-09-02 Stefan Roese <sr@denx.de> +p3p440 powerpc ppc4xx c6999e5f 2015-09-02 Stefan Roese <sr@denx.de> +csb272/csb472 powerpc ppc4xx 54a3f260 2015-09-02 Tolunay Orkun <torkun@nextio.com> +alpr powerpc ppc4xx 0d2fc811 2015-09-02 Stefan Roese <sr@denx.de> +balloon3 arm pxa 679d4456 2015-08-30 Marek Vasut <marex@denx.de> +cpu9260_128M arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com> +cpu9260 arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com> +cpu9260_nand_128M arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com> +cpu9260_nand arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com> +cpu9G20_128M arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com> +cpu9G20 arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com> +cpuat91 arm arm920t af7f884b 2015-08-30 Eric Benard <eric@eukrea.com> +cpuat91_ram arm arm920t af7f884b 2015-08-30 Eric Benard <eric@eukrea.com> +davinci_dm355evm arm arm926ejs 6761946f 2015-08-30 +davinci_dm355leopard arm arm926ejs 6761946f 2015-08-30 +davinci_dm365evm arm arm926ejs 6761946f 2015-08-30 +davinci_dm6467evm arm arm926ejs 6761946f 2015-08-30 +davinci_dm6467Tevm arm arm926ejs 6761946f 2015-08-30 +davinci_dvevm arm arm926ejs 6761946f 2015-08-30 +davinci_schmoogie arm arm926ejs 6761946f 2015-08-30 +davinci_sffsdr arm arm926ejs 6761946f 2015-08-30 +davinci_sonata arm arm926ejs 6761946f 2015-08-30 +dig297 arm armv7 5ff33d04 2015-08-30 Luca Ceresoli <luca.ceresoli@comelit.it> +ea20 arm arm926ejs 6761946f 2015-08-30 +eb_cpux9k2 arm arm920t 5522f12b 2015-08-30 Jens Scharsig <esw@bus-elektronik.de> +eb_cpux9k2_ram arm arm920t 5522f12b 2015-08-30 Jens Scharsig <esw@bus-elektronik.de> +enbw_cmc arm arm926ejs a6f7f787 2015-08-30 Heiko Schocher <hs@denx.de> +ima3-mx53 arm armv7 3eb8f58d 2015-08-30 +imx27lite arm arm926ejs bc0840bc 2015-08-30 Wolfgang Denk <wd@denx.de> +imx31_litekit arm arm1136 36d14178 2015-08-30 +jornada arm sa1100 df0b116d 2015-08-30 Kristoffer Ericson <kristoffer.ericson@gmail.com> +lp8x4x arm pxa 9f840b8d 2015-08-30 Sergey Yanovich <ynvich@gmail.com> +magnesium arm arm926ejs bc0840bc 2015-08-30 Heiko Schocher <hs@denx.de> +mv88f6281gtw_ge arm arm926ejs 7cd768cf 2015-08-30 Prafulla Wadaskar <prafulla@marvell.com> +mx51_efikamx arm armv7 b6073fd2 2015-08-30 +mx51_efikasb arm armv7 b6073fd2 2015-08-30 +nhk8815 arm arm926ejs 0abdd9d0 2015-08-30 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com> +nhk8815_onenand arm arm926ejs 0abdd9d0 2015-08-30 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com> +omap3_mvblx arm armv7 8dc372f9 2015-08-30 Michael Jones <michael.jones@matrix-vision.de> +omap3_sdp3430 arm armv7 93b25c08 2015-08-30 Nishanth Menon <nm@ti.com> +openrd_base arm arm926ejs 7a2c1b13 2015-08-30 Prafulla Wadaskar <prafulla@marvell.com> +openrd_client arm arm926ejs 7a2c1b13 2015-08-30 Prafulla Wadaskar <prafulla@marvell.com> +openrd_ultimate arm arm926ejs 7a2c1b13 2015-08-30 Prafulla Wadaskar <prafulla@marvell.com> +otc570 arm arm926ejs 819216dd 2015-08-30 Daniel Gorsulowski <daniel.gorsulowski@esd.eu> +otc570_dataflash arm arm926ejs 819216dd 2015-08-30 Daniel Gorsulowski <daniel.gorsulowski@esd.eu> +palmld arm pxa 35782e9c 2015-08-30 Marek Vasut <marex@denx.de> +palmtc arm pxa 8896325d 2015-08-30 Marek Vasut <marex@denx.de> +palmtreo680 arm pxa ad4f54ea 2015-08-30 Mike Dunn <mikedunn@newsguy.com> +polaris arm pxa f6eac00a 2015-08-30 Stefano Babic <sbabic@denx.de> +portuxg20 arm arm926ejs 79d19734 2015-08-30 Markus Hubig <mhubig@imko.de> +pxa255_idp arm pxa 49d8899b 2015-08-30 Marek Vasut <marex@denx.de> +qong arm arm1136 daf77086 2015-08-30 Wolfgang Denk <wd@denx.de> +rd6281a arm arm926ejs 47b87d2e 2015-08-30 Prafulla Wadaskar <prafulla@marvell.com> +scb9328 arm arm920t 7650beb7 2015-08-30 Torsten Koschorrek <koschorrek@synertronixx.de> +snowball arm armv7 7495e41b 2015-08-30 Mathieu Poirier <mathieu.poirier@linaro.org> +stamp9g20 arm arm926ejs 79d19734 2015-08-30 Markus Hubig <mhubig@imko.de> +tk71 arm arm926ejs f73db66d 2015-08-30 +trizepsiv arm pxa f6eac00a 2015-08-30 Stefano Babic <sbabic@denx.de> +tt01 arm arm1136 0c81f37d 2015-08-30 Helmut Raiger <helmut.raiger@hale.at> +tx25 arm arm926ejs b9599dd8 2015-08-30 John Rigby <jcrigby@gmail.com> +u8500_href arm armv7 7495e41b 2015-08-30 +versatileab arm arm926ejs b928e658 2015-08-30 +versatilepb arm arm926ejs b928e658 2015-08-30 +versatileqemu arm arm926ejs b928e658 2015-08-30 +vision2 arm armv7 bee2b99d 2015-08-30 Stefano Babic <sbabic@denx.de> +vl_ma2sc arm arm926ejs 6e830dfc 2015-08-30 Jens Scharsig <esw@bus-elektronik.de> +vl_ma2sc_ram arm arm926ejs 6e830dfc 2015-08-30 Jens Scharsig <esw@bus-elektronik.de> +vpac270_nor_128 arm pxa 452ef830 2015-08-30 Marek Vasut <marex@denx.de> +vpac270_nor_256 arm pxa 452ef830 2015-08-30 Marek Vasut <marex@denx.de> +vpac270_ond_256 arm pxa 452ef830 2015-08-30 Marek Vasut <marex@denx.de> +xaeniax arm pxa 1c87dd76 2015-08-30 +zipitz2 arm pxa 49d8899b 2015-08-30 Cliff Brake <cliff.brake@gmail.com> cam_enc_4xx arm arm926ejs 8d775763 2015-08-20 Heiko Schocher <hs@denx.de> atstk1003 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com> atstk1004 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com> diff --git a/doc/README.uniphier b/doc/README.uniphier index 6ba0320..57b947b 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -129,10 +129,10 @@ as follows: BKSZ Description RAM slot Peripherals -------------------------------------------------------------------- - 0b00 15MB RAM / 1MB Peri 00000000-0effffff 0f000000-0fffffff - 0b01 31MB RAM / 1MB Peri 00000000-1effffff 1f000000-1fffffff - 0b10 64MB RAM / 1MB Peri 00000000-3effffff 3f000000-3fffffff - 0b11 127MB RAM / 1MB Peri 00000000-7effffff 7f000000-7fffffff + 0b00 15MB RAM / 1MB Peri 00000000-00efffff 00f00000-00ffffff + 0b01 31MB RAM / 1MB Peri 00000000-01efffff 01f00000-01ffffff + 0b10 64MB RAM / 1MB Peri 00000000-03efffff 03f00000-03ffffff + 0b11 127MB RAM / 1MB Peri 00000000-07efffff 07f00000-07ffffff Set BSKZ[1:0] to 0b01 for U-Boot. This mode is the most handy because EA[24] is always supported by the save pin diff --git a/doc/README.vxworks b/doc/README.vxworks index 4cb302e..3433e4f 100644 --- a/doc/README.vxworks +++ b/doc/README.vxworks @@ -1,19 +1,85 @@ -From VxWorks 6.9+ (not include 6.9), VxWorks starts adopting device tree as its hardware -decription mechansim (for PowerPC and ARM), thus requiring boot interface changes. +# +# Copyright (C) 2013, Miao Yan <miao.yan@windriver.com> +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +VxWorks Support +=============== + +This document describes the information about U-Boot loading VxWorks kernel. + +Status +------ +U-Boot supports loading VxWorks kernels via 'bootvx' and 'bootm' commands. +For booting old kernels (6.9.x) on PowerPC and ARM, and all kernel versions +on other architectures, 'bootvx' shall be used. For booting VxWorks 7 kernels +on PowerPC and ARM, 'bootm' shall be used. + +64-bit x86 kernel cannot be loaded as of today. + +VxWork 7 on PowerPC and ARM +--------------------------- +From VxWorks 7, VxWorks starts adopting device tree as its hardware decription +mechansim (for PowerPC and ARM), thus requiring boot interface changes. This section will describe the new interface. -For PowerPC, the calling convention of the new VxWorks entry point conforms to the ePAPR standard, -which is shown below (see ePAPR for more details): +For PowerPC, the calling convention of the new VxWorks entry point conforms to +the ePAPR standard, which is shown below (see ePAPR for more details): - void (*kernel_entry)(fdt_addr, - 0, 0, EPAPR_MAGIC, boot_IMA, 0, 0) + void (*kernel_entry)(fdt_addr, 0, 0, EPAPR_MAGIC, boot_IMA, 0, 0) For ARM, the calling convention is show below: void (*kernel_entry)(void *fdt_addr) -When booting new VxWorks kernel (uImage format), the parameters passed to bootm is like below: +When booting new VxWorks kernel (uImage format), the parameters passed to bootm +is like below: bootm <kernel image address> - <device tree address> -The do_bootvx command still works as it was for older VxWorks kernels. +VxWorks bootline +---------------- +When using 'bootvx', the kernel bootline must be prepared by U-Boot at a +board-specific address before loading VxWorks. U-Boot supplies its address +via "bootaddr" environment variable. To check where the bootline should be +for a specific board, go to the VxWorks BSP for that board, and look for a +parameter called BOOT_LINE_ADRS. Assign its value to "bootaddr". A typical +value for "bootaddr" is 0x101200. + +If a "bootargs" variable is defined, its content will be copied to the memory +location pointed by "bootaddr" as the kernel bootline. If "bootargs" is not +there, command 'bootvx' can construct a valid bootline using the following +environments variables: bootdev, bootfile, ipaddr, netmask, serverip, +gatewayip, hostname, othbootargs. + +When using 'bootm', just define "bootargs" in the environment and U-Boot will +handle bootline fix up for the kernel dtb automatically. + +Serial console +-------------- +It's very common that VxWorks BSPs configure a different baud rate for the +serial console from what is being used by U-Boot. For example, VxWorks tends +to use 9600 as the default baud rate on all x86 BSPs while U-Boot uses 115200. +Please configure both U-Boot and VxWorks to use the same baud rate, or it may +look like VxWorks hangs somewhere as nothing outputs on the serial console. + +x86-specific information +------------------------ +Before loading an x86 kernel, two additional environment variables need to be +provided. They are "e820data" and "e820info", which represent the address of +E820 table and E820 information (defined by VxWorks) in system memory. + +Check VxWorks kernel configuration to look for BIOS_E820_DATA_START and +BIOS_E820_INFO_START, and assign their values to "e820data" and "e820info" +accordingly. If neither of these two are supplied, U-Boot assumes a default +location at 0x4000 for "e820data" and 0x4a00 for "e820info". Typical values +for "e820data" and "e820info" are 0x104000 and 0x104a00. But there is one +exception on Intel Galileo, where "e820data" and "e820info" should be left +unset, which assume the default location for VxWorks. + +Note since currently U-Boot does not support ACPI yet, VxWorks kernel must +be configured to use MP table and virtual wire interrupt mode. This requires +INCLUDE_MPTABLE_BOOT_OP and INCLUDE_VIRTUAL_WIRE_MODE to be included in a +VxWorks kernel configuration. diff --git a/doc/README.x86 b/doc/README.x86 index 6cf293b..1271e5e 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -25,6 +25,8 @@ targets and all Intel boards support running U-Boot 'bare metal'. As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit Linux kernel as part of a FIT image. It also supports a compressed zImage. +U-Boot supports loading an x86 VxWorks kernel. Please check README.vxworks +for more details. Build Instructions for U-Boot as coreboot payload ------------------------------------------------- @@ -188,6 +190,7 @@ Offset Description Controlling config 000000 descriptor.bin Hard-coded to 0 in ifdtool 001000 me.bin Set by the descriptor 500000 <spare> +6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE 700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE 790000 vga.bin CONFIG_VGA_BIOS_ADDR 7c0000 fsp.bin CONFIG_FSP_ADDR @@ -330,9 +333,8 @@ In keeping with the U-Boot philosophy of providing functions to check and adjust internal settings, there are several x86-specific commands that may be useful: -hob - Display information about Firmware Support Package (FSP) Hand-off - Block. This is only available on platforms which use FSP, mostly - Atom. +fsp - Display information about Intel Firmware Support Package (FSP). + This is only available on platforms which use FSP, mostly Atom. iod - Display I/O memory iow - Write I/O memory mtrr - List and set the Memory Type Range Registers (MTRR). These are used to @@ -762,7 +764,6 @@ TODO List - Audio - Chrome OS verified boot - SMI and ACPI support, to provide platform info and facilities to Linux -- Desktop Management Interface (DMI) [15] support References ---------- @@ -780,4 +781,3 @@ References [12] http://events.linuxfoundation.org/sites/events/files/slides/chromeos_and_diy_vboot_0.pdf [13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf [14] doc/device-tree-bindings/misc/intel,irq-router.txt -[15] http://en.wikipedia.org/wiki/Desktop_Management_Interface diff --git a/doc/device-tree-bindings/remoteproc/remoteproc.txt b/doc/device-tree-bindings/remoteproc/remoteproc.txt new file mode 100644 index 0000000..031764f --- /dev/null +++ b/doc/device-tree-bindings/remoteproc/remoteproc.txt @@ -0,0 +1,14 @@ +Remote Processor uclass + +Binding: + +Remoteproc devices shall have compatible corresponding to thier +drivers. However the following generic properties will be supported + +Optional Properties: +- remoteproc-name: a string, used if provided to describe the processor. + This must be unique in an operational system. +- remoteproc-internal-memory-mapped: a bool, indicates that the remote + processor has internal memory that it uses to execute code and store + data. Such a device is not expected to have a MMU. If no type property + is provided, the device is assumed to map to such a model. diff --git a/doc/driver-model/remoteproc-framework.txt b/doc/driver-model/remoteproc-framework.txt new file mode 100644 index 0000000..094e98b --- /dev/null +++ b/doc/driver-model/remoteproc-framework.txt @@ -0,0 +1,168 @@ +# +# (C) Copyright 2015 +# Texas Instruments Incorporated - http://www.ti.com/ +# SPDX-License-Identifier: GPL-2.0+ +# + +Remote Processor Framework +========================== +TOC: +1. Introduction +2. How does it work - The driver +3. Describing the device using platform data +4. Describing the device using device tree + +1. Introduction +=============== + +This is an introduction to driver-model for Remote Processors found +on various System on Chip(SoCs). The term remote processor is used to +indicate that this is not the processor on which U-Boot is operating +on, instead is yet another processing entity that may be controlled by +the processor on which we are functional. + +The simplified model depends on a single UCLASS - UCLASS_REMOTEPROC + +UCLASS_REMOTEPROC: +- drivers/remoteproc/rproc-uclass.c +- include/remoteproc.h + +Commands: +- common/cmd_remoteproc.c + +Configuration: +CONFIG_REMOTEPROC is selected by drivers as needed +CONFIG_CMD_REMOTEPROC for the commands if required. + +2. How does it work - The driver +================================= + +Overall, the driver statemachine transitions are typically as follows: + (entry) + +-------+ + +---+ init | + | | | <---------------------+ + | +-------+ | + | | + | | + | +--------+ | +Load| | reset | | + | | | <----------+ | + | +--------+ | | + | |Load | | + | | | | + | +----v----+ reset | | + +-> | | (opt) | | + | Loaded +-----------+ | + | | | + +----+----+ | + | Start | + +---v-----+ (opt) | + +->| Running | Stop | +Ping +- | +--------------------+ +(opt) +---------+ + +(is_running does not change state) +opt: Optional state transition implemented by driver. + +NOTE: It depends on the remote processor as to the exact behavior +of the statemachine, remoteproc core does not intent to implement +statemachine logic. Certain processors may allow start/stop without +reloading the image in the middle, certain other processors may only +allow us to start the processor(image from a EEPROM/OTP) etc. + +It is hence the responsibility of the driver to handle the requisite +state transitions of the device as necessary. + +Basic design assumptions: + +Remote processor can operate on a certain firmware that maybe loaded +and released from reset. + +The driver follows a standard UCLASS DM. + +in the bare minimum form: + +static const struct dm_rproc_ops sandbox_testproc_ops = { + .load = sandbox_testproc_load, + .start = sandbox_testproc_start, +}; + +static const struct udevice_id sandbox_ids[] = { + {.compatible = "sandbox,test-processor"}, + {} +}; + +U_BOOT_DRIVER(sandbox_testproc) = { + .name = "sandbox_test_proc", + .of_match = sandbox_ids, + .id = UCLASS_REMOTEPROC, + .ops = &sandbox_testproc_ops, + .probe = sandbox_testproc_probe, +}; + +This allows for the device to be probed as part of the "init" command +or invocation of 'rproc_init()' function as the system dependencies define. + +The driver is expected to maintain it's own statemachine which is +appropriate for the device it maintains. It must, at the very least +provide a load and start function. We assume here that the device +needs to be loaded and started, else, there is no real purpose of +using the remoteproc framework. + +3. Describing the device using platform data +============================================ + +*IMPORTANT* NOTE: THIS SUPPORT IS NOT MEANT FOR USE WITH NEWER PLATFORM +SUPPORT. THIS IS ONLY FOR LEGACY DEVICES. THIS MODE OF INITIALIZATION +*WILL* BE EVENTUALLY REMOVED ONCE ALL NECESSARY PLATFORMS HAVE MOVED +TO DM/FDT. + +Considering that many platforms are yet to move to device-tree model, +a simplified definition of a device is as follows: + +struct dm_rproc_uclass_pdata proc_3_test = { + .name = "proc_3_legacy", + .mem_type = RPROC_INTERNAL_MEMORY_MAPPED, + .driver_plat_data = &mydriver_data; +}; + +U_BOOT_DEVICE(proc_3_demo) = { + .name = "sandbox_test_proc", + .platdata = &proc_3_test, +}; + +There can be additional data that may be desired depending on the +remoteproc driver specific needs (for example: SoC integration +details such as clock handle or something similar). See appropriate +documentation for specific remoteproc driver for further details. +These are passed via driver_plat_data. + +3. Describing the device using device tree +========================================== +/ { + ... + aliases { + ... + remoteproc0 = &rproc_1; + remoteproc1 = &rproc_2; + + }; + ... + + rproc_1: rproc@1 { + compatible = "sandbox,test-processor"; + remoteproc-name = "remoteproc-test-dev1"; + }; + + rproc_2: rproc@2 { + compatible = "sandbox,test-processor"; + internal-memory-mapped; + remoteproc-name = "remoteproc-test-dev2"; + }; + ... +}; + +aliases usage is optional, but it is usually recommended to ensure the +users have a consistent usage model for a platform. +the compatible string used here is specific to the remoteproc driver involved. diff --git a/drivers/Kconfig b/drivers/Kconfig index 63c92c5..c02f323 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -46,6 +46,8 @@ source "drivers/power/Kconfig" source "drivers/ram/Kconfig" +source "drivers/remoteproc/Kconfig" + source "drivers/rtc/Kconfig" source "drivers/serial/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 9d0a595..1a30ad1 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -59,6 +59,7 @@ obj-y += pwm/ obj-y += input/ # SOC specific infrastructure drivers. obj-y += soc/ +obj-$(CONFIG_REMOTEPROC) += remoteproc/ obj-y += thermal/ endif diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 41f4e69..15681df 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -120,4 +120,34 @@ config SPL_SIMPLE_BUS Supports the 'simple-bus' driver, which is used on some systems in SPL. +config OF_TRANSLATE + bool "Translate addresses using fdt_translate_address" + depends on DM && OF_CONTROL + default y + help + If this option is enabled, the reg property will be translated + using the fdt_translate_address() function. This is necessary + on some platforms (e.g. MVEBU) using complex "ranges" + properties in many nodes. As this translation is not handled + correctly in the default simple_bus_translate() function. + + If this option is not enabled, simple_bus_translate() will be + used for the address translation. This function is faster and + smaller in size than fdt_translate_address(). + +config SPL_OF_TRANSLATE + bool "Translate addresses using fdt_translate_address" + depends on SPL_DM && SPL_OF_CONTROL + default n + help + If this option is enabled, the reg property will be translated + using the fdt_translate_address() function. This is necessary + on some platforms (e.g. MVEBU) using complex "ranges" + properties in many nodes. As this translation is not handled + correctly in the default simple_bus_translate() function. + + If this option is not enabled, simple_bus_translate() will be + used for the address translation. This function is faster and + smaller in size than fdt_translate_address(). + endmenu diff --git a/drivers/core/device.c b/drivers/core/device.c index 833a803..a3dc2ca 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -11,6 +11,7 @@ #include <common.h> #include <fdtdec.h> +#include <fdt_support.h> #include <malloc.h> #include <dm/device.h> #include <dm/device-internal.h> @@ -585,6 +586,25 @@ fdt_addr_t dev_get_addr(struct udevice *dev) #if CONFIG_IS_ENABLED(OF_CONTROL) fdt_addr_t addr; + if (CONFIG_IS_ENABLED(OF_TRANSLATE)) { + const fdt32_t *reg; + + reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", NULL); + if (!reg) + return FDT_ADDR_T_NONE; + + /* + * Use the full-fledged translate function for complex + * bus setups. + */ + return fdt_translate_address((void *)gd->fdt_blob, + dev->of_offset, reg); + } + + /* + * Use the "simple" translate function for less complex + * bus setups. + */ addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, dev->parent->of_offset, dev->of_offset, "reg", diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c index c3d3c3b..7646c6b 100644 --- a/drivers/dfu/dfu_sf.c +++ b/drivers/dfu/dfu_sf.c @@ -23,16 +23,25 @@ static int dfu_read_medium_sf(struct dfu_entity *dfu, u64 offset, void *buf, return spi_flash_read(dfu->data.sf.dev, offset, *len, buf); } +static u64 find_sector(struct dfu_entity *dfu, u64 start, u64 offset) +{ + return (lldiv((start + offset), dfu->data.sf.dev->sector_size)) * + dfu->data.sf.dev->sector_size; +} + static int dfu_write_medium_sf(struct dfu_entity *dfu, u64 offset, void *buf, long *len) { int ret; - ret = spi_flash_erase(dfu->data.sf.dev, offset, *len); + ret = spi_flash_erase(dfu->data.sf.dev, + find_sector(dfu, dfu->data.sf.start, offset), + dfu->data.sf.dev->sector_size); if (ret) return ret; - ret = spi_flash_write(dfu->data.sf.dev, offset, *len, buf); + ret = spi_flash_write(dfu->data.sf.dev, dfu->data.sf.start + offset, + *len, buf); if (ret) return ret; diff --git a/drivers/dma/keystone_nav.c b/drivers/dma/keystone_nav.c index dfca75a..5a65b62 100644 --- a/drivers/dma/keystone_nav.c +++ b/drivers/dma/keystone_nav.c @@ -54,7 +54,7 @@ int _qm_init(struct qm_config *cfg) qm_cfg = cfg; qm_cfg->mngr_cfg->link_ram_base0 = qm_cfg->i_lram; - qm_cfg->mngr_cfg->link_ram_size0 = HDESC_NUM * 8; + qm_cfg->mngr_cfg->link_ram_size0 = HDESC_NUM * 8 - 1; qm_cfg->mngr_cfg->link_ram_base1 = 0; qm_cfg->mngr_cfg->link_ram_size1 = 0; qm_cfg->mngr_cfg->link_ram_base2 = 0; diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c index 2e97cc3..bd2ac89 100644 --- a/drivers/gpio/axp_gpio.c +++ b/drivers/gpio/axp_gpio.c @@ -10,22 +10,13 @@ #include <asm/arch/gpio.h> #include <asm/arch/pmic_bus.h> #include <asm/gpio.h> +#include <axp_pmic.h> #include <dm.h> #include <dm/device-internal.h> #include <dm/lists.h> #include <dm/root.h> #include <errno.h> -#ifdef CONFIG_AXP152_POWER -#include <axp152.h> -#elif defined CONFIG_AXP209_POWER -#include <axp209.h> -#elif defined CONFIG_AXP221_POWER -#include <axp221.h> -#else -#error Unknown AXP model -#endif - static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val); static u8 axp_get_gpio_ctrl_reg(unsigned pin) diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c index cd960dc..93d18e4 100644 --- a/drivers/gpio/omap_gpio.c +++ b/drivers/gpio/omap_gpio.c @@ -25,6 +25,7 @@ #include <asm/io.h> #include <asm/errno.h> #include <malloc.h> +#include <dt-bindings/gpio/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -276,12 +277,22 @@ static int omap_gpio_get_function(struct udevice *dev, unsigned offset) return GPIOF_INPUT; } +static int omap_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct fdtdec_phandle_args *args) +{ + desc->offset = args->args[0]; + desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; + + return 0; +} + static const struct dm_gpio_ops gpio_omap_ops = { .direction_input = omap_gpio_direction_input, .direction_output = omap_gpio_direction_output, .get_value = omap_gpio_get_value, .set_value = omap_gpio_set_value, .get_function = omap_gpio_get_function, + .xlate = omap_gpio_xlate, }; static int omap_gpio_probe(struct udevice *dev) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 6277f92..ceae7bc 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -1,5 +1,11 @@ menu "MMC Host controller Support" +config MMC + bool "Enable MMC support" + depends on ARCH_SUNXI + help + TODO: Move all architectures to use this option + config DM_MMC bool "Enable MMC controllers using Driver Model" depends on DM diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index 75fa014..82c695f 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -1,6 +1,41 @@ +/* + * Marvell SD Host Controller Interface + * + * SPDX-License-Identifier: GPL-2.0+ + */ + #include <common.h> #include <malloc.h> #include <sdhci.h> +#include <linux/mbus.h> + +#define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4)) +#define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4)) + +static void sdhci_mvebu_mbus_config(void __iomem *base) +{ + const struct mbus_dram_target_info *dram; + int i; + + dram = mvebu_mbus_dram_info(); + + for (i = 0; i < 4; i++) { + writel(0, base + SDHCI_WINDOW_CTRL(i)); + writel(0, base + SDHCI_WINDOW_BASE(i)); + } + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + + /* Write size, attributes and target id to control register */ + writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + base + SDHCI_WINDOW_CTRL(i)); + + /* Write base address to base register */ + writel(cs->base, base + SDHCI_WINDOW_BASE(i)); + } +} #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS static struct sdhci_ops mv_ops; @@ -47,6 +82,12 @@ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) mv_ops.write_b = mv_sdhci_writeb; host->ops = &mv_ops; #endif + + if (CONFIG_IS_ENABLED(ARCH_MVEBU)) { + /* Configure SDHCI MBUS mbus bridge windows */ + sdhci_mvebu_mbus_config((void __iomem *)regbase); + } + if (quirks & SDHCI_QUIRK_REG32_RW) host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; else diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index d7b388f..5038a9f 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -31,10 +31,15 @@ #include <twl4030.h> #include <twl6030.h> #include <palmas.h> -#include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/mmc_host_def.h> +#if !defined(CONFIG_SOC_KEYSTONE) +#include <asm/gpio.h> #include <asm/arch/sys_proto.h> +#endif +#include <dm.h> + +DECLARE_GLOBAL_DATA_PTR; /* simplify defines to OMAP_HSMMC_USE_GPIO */ #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ @@ -52,9 +57,15 @@ struct omap_hsmmc_data { struct hsmmc *base_addr; struct mmc_config cfg; #ifdef OMAP_HSMMC_USE_GPIO +#ifdef CONFIG_DM_MMC + struct gpio_desc cd_gpio; /* Change Detect GPIO */ + struct gpio_desc wp_gpio; /* Write Protect GPIO */ + bool cd_inverted; +#else int cd_gpio; int wp_gpio; #endif +#endif }; /* If we fail after 1 second wait, something is really bad */ @@ -64,7 +75,7 @@ static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, unsigned int siz); -#ifdef OMAP_HSMMC_USE_GPIO +#if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC) static int omap_mmc_setup_gpio_in(int gpio, const char *label) { int ret; @@ -600,6 +611,34 @@ static void omap_hsmmc_set_ios(struct mmc *mmc) } #ifdef OMAP_HSMMC_USE_GPIO +#ifdef CONFIG_DM_MMC +static int omap_hsmmc_getcd(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv = mmc->priv; + int value; + + value = dm_gpio_get_value(&priv->cd_gpio); + /* if no CD return as 1 */ + if (value < 0) + return 1; + + if (priv->cd_inverted) + return !value; + return value; +} + +static int omap_hsmmc_getwp(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv = mmc->priv; + int value; + + value = dm_gpio_get_value(&priv->wp_gpio); + /* if no WP return as 0 */ + if (value < 0) + return 0; + return value; +} +#else static int omap_hsmmc_getcd(struct mmc *mmc) { struct omap_hsmmc_data *priv_data = mmc->priv; @@ -628,6 +667,7 @@ static int omap_hsmmc_getwp(struct mmc *mmc) return gpio_get_value(wp_gpio); } #endif +#endif static const struct mmc_ops omap_hsmmc_ops = { .send_cmd = omap_hsmmc_send_cmd, @@ -639,6 +679,7 @@ static const struct mmc_ops omap_hsmmc_ops = { #endif }; +#ifndef CONFIG_DM_MMC int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, int wp_gpio) { @@ -662,7 +703,8 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \ - defined(CONFIG_AM43XX)) && defined(CONFIG_HSMMC2_8BIT) + defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \ + defined(CONFIG_HSMMC2_8BIT) /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ host_caps_val |= MMC_MODE_8BIT; #endif @@ -724,3 +766,79 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, return 0; } +#else +static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) +{ + struct omap_hsmmc_data *priv = dev_get_priv(dev); + const void *fdt = gd->fdt_blob; + int node = dev->of_offset; + struct mmc_config *cfg; + int val; + + priv->base_addr = (struct hsmmc *)dev_get_addr(dev); + cfg = &priv->cfg; + + cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; + val = fdtdec_get_int(fdt, node, "bus-width", -1); + if (val < 0) { + printf("error: bus-width property missing\n"); + return -ENOENT; + } + + switch (val) { + case 0x8: + cfg->host_caps |= MMC_MODE_8BIT; + case 0x4: + cfg->host_caps |= MMC_MODE_4BIT; + break; + default: + printf("error: invalid bus-width property\n"); + return -ENOENT; + } + + cfg->f_min = 400000; + cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000); + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); + + return 0; +} + +static int omap_hsmmc_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct omap_hsmmc_data *priv = dev_get_priv(dev); + struct mmc_config *cfg; + struct mmc *mmc; + + cfg = &priv->cfg; + cfg->name = "OMAP SD/MMC"; + cfg->ops = &omap_hsmmc_ops; + + mmc = mmc_create(cfg, priv); + if (mmc == NULL) + return -1; + + upriv->mmc = mmc; + + return 0; +} + +static const struct udevice_id omap_hsmmc_ids[] = { + { .compatible = "ti,omap3-hsmmc" }, + { .compatible = "ti,omap4-hsmmc" }, + { .compatible = "ti,am33xx-hsmmc" }, + { } +}; + +U_BOOT_DRIVER(omap_hsmmc) = { + .name = "omap_hsmmc", + .id = UCLASS_MMC, + .of_match = omap_hsmmc_ids, + .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata, + .probe = omap_hsmmc_probe, + .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data), +}; +#endif diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 4db51d6..15ecfee 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -84,9 +84,9 @@ static int s5p_sdhci_core_init(struct sdhci_host *host) int s5p_sdhci_init(u32 regbase, int index, int bus_width) { - struct sdhci_host *host = malloc(sizeof(struct sdhci_host)); + struct sdhci_host *host = calloc(1, sizeof(struct sdhci_host)); if (!host) { - printf("sdhci__host malloc fail!\n"); + printf("sdhci__host allocation fail!\n"); return 1; } host->ioaddr = (void *)regbase; @@ -101,29 +101,31 @@ struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS]; static int do_sdhci_init(struct sdhci_host *host) { - int dev_id, flag; - int err = 0; + int dev_id, flag, ret; flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; dev_id = host->index + PERIPH_ID_SDMMC0; if (dm_gpio_is_valid(&host->pwr_gpio)) { dm_gpio_set_value(&host->pwr_gpio, 1); - err = exynos_pinmux_config(dev_id, flag); - if (err) { + ret = exynos_pinmux_config(dev_id, flag); + if (ret) { debug("MMC not configured\n"); - return err; + return ret; } } if (dm_gpio_is_valid(&host->cd_gpio)) { - if (dm_gpio_get_value(&host->cd_gpio)) + ret = dm_gpio_get_value(&host->cd_gpio); + if (ret) { + debug("no SD card detected (%d)\n", ret); return -ENODEV; + } - err = exynos_pinmux_config(dev_id, flag); - if (err) { + ret = exynos_pinmux_config(dev_id, flag); + if (ret) { printf("external SD not configured\n"); - return err; + return ret; } } @@ -170,7 +172,8 @@ static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) static int process_nodes(const void *blob, int node_list[], int count) { struct sdhci_host *host; - int i, node; + int i, node, ret; + int failed = 0; debug("%s: count = %d\n", __func__, count); @@ -182,13 +185,22 @@ static int process_nodes(const void *blob, int node_list[], int count) host = &sdhci_host[i]; - if (sdhci_get_config(blob, node, host)) { - printf("%s: failed to decode dev %d\n", __func__, i); - return -1; + ret = sdhci_get_config(blob, node, host); + if (ret) { + printf("%s: failed to decode dev %d (%d)\n", __func__, i, ret); + failed++; + continue; + } + + ret = do_sdhci_init(host); + if (ret) { + printf("%s: failed to initialize dev %d (%d)\n", __func__, i, ret); + failed++; } - do_sdhci_init(host); } - return 0; + + /* we only consider it an error when all nodes fail */ + return (failed == count ? -1 : 0); } int exynos_mmc_init(const void *blob) @@ -200,8 +212,6 @@ int exynos_mmc_init(const void *blob) COMPAT_SAMSUNG_EXYNOS_MMC, node_list, SDHCI_MAX_HOSTS); - process_nodes(blob, node_list, count); - - return 0; + return process_nodes(blob, node_list, count); } #endif diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index fb4d621..3dff9df 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -25,6 +25,9 @@ #include <asm/io.h> #include <phy.h> #include <asm/arch/cpu.h> +#include <dm.h> + +DECLARE_GLOBAL_DATA_PTR; #define BITMASK(bits) (BIT(bits) - 1) #define PHY_REG_MASK 0x1f @@ -37,6 +40,23 @@ #define FULLDUPLEXEN BIT(0) #define MIIEN BIT(15) +/* reg offset */ +#define CPSW_HOST_PORT_OFFSET 0x108 +#define CPSW_SLAVE0_OFFSET 0x208 +#define CPSW_SLAVE1_OFFSET 0x308 +#define CPSW_SLAVE_SIZE 0x100 +#define CPSW_CPDMA_OFFSET 0x800 +#define CPSW_HW_STATS 0x900 +#define CPSW_STATERAM_OFFSET 0xa00 +#define CPSW_CPTS_OFFSET 0xc00 +#define CPSW_ALE_OFFSET 0xd00 +#define CPSW_SLIVER0_OFFSET 0xd80 +#define CPSW_SLIVER1_OFFSET 0xdc0 +#define CPSW_BD_OFFSET 0x2000 +#define CPSW_MDIO_DIV 0xff + +#define AM335X_GMII_SEL_OFFSET 0x630 + /* DMA Registers */ #define CPDMA_TXCONTROL 0x004 #define CPDMA_RXCONTROL 0x014 @@ -218,7 +238,11 @@ struct cpdma_chan { (priv)->data.slaves; slave++) struct cpsw_priv { +#ifdef CONFIG_DM_ETH + struct udevice *dev; +#else struct eth_device *dev; +#endif struct cpsw_platform_data data; int host_port; @@ -522,7 +546,7 @@ static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr, return 0; } -static void cpsw_mdio_init(char *name, u32 mdio_base, u32 div) +static void cpsw_mdio_init(const char *name, u32 mdio_base, u32 div) { struct mii_dev *bus = mdio_alloc(); @@ -563,8 +587,15 @@ static inline void setbit_and_wait_for_clear32(void *addr) static void cpsw_set_slave_mac(struct cpsw_slave *slave, struct cpsw_priv *priv) { +#ifdef CONFIG_DM_ETH + struct eth_pdata *pdata = dev_get_platdata(priv->dev); + + writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi); + writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo); +#else __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi); __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo); +#endif } static void cpsw_slave_update_link(struct cpsw_slave *slave, @@ -745,9 +776,8 @@ static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan, return 0; } -static int cpsw_init(struct eth_device *dev, bd_t *bis) +static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr) { - struct cpsw_priv *priv = dev->priv; struct cpsw_slave *slave; int i, ret; @@ -772,8 +802,7 @@ static int cpsw_init(struct eth_device *dev, bd_t *bis) cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD); - cpsw_ale_add_ucast(priv, priv->dev->enetaddr, priv->host_port, - ALE_SECURE); + cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE); cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port); for_active_slave(slave, priv) @@ -857,10 +886,8 @@ static int cpsw_init(struct eth_device *dev, bd_t *bis) return 0; } -static void cpsw_halt(struct eth_device *dev) +static void _cpsw_halt(struct cpsw_priv *priv) { - struct cpsw_priv *priv = dev->priv; - writel(0, priv->dma_regs + CPDMA_TXCONTROL); writel(0, priv->dma_regs + CPDMA_RXCONTROL); @@ -870,12 +897,10 @@ static void cpsw_halt(struct eth_device *dev) /* clear dma state */ setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); - priv->data.control(0); } -static int cpsw_send(struct eth_device *dev, void *packet, int length) +static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length) { - struct cpsw_priv *priv = dev->priv; void *buffer; int len; int timeout = CPDMA_TIMEOUT; @@ -896,20 +921,21 @@ static int cpsw_send(struct eth_device *dev, void *packet, int length) return cpdma_submit(priv, &priv->tx_chan, packet, length); } -static int cpsw_recv(struct eth_device *dev) +static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt) { - struct cpsw_priv *priv = dev->priv; void *buffer; int len; + int ret = -EAGAIN; - while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) { - invalidate_dcache_range((unsigned long)buffer, - (unsigned long)buffer + PKTSIZE_ALIGN); - net_process_received_packet(buffer, len); - cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE); - } + ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len); + if (ret < 0) + return ret; - return 0; + invalidate_dcache_range((unsigned long)buffer, + (unsigned long)buffer + PKTSIZE_ALIGN); + *pkt = buffer; + + return len; } static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num, @@ -923,15 +949,14 @@ static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num, slave->sliver = regs + data->sliver_reg_ofs; } -static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave) +static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave) { - struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv; struct phy_device *phydev; u32 supported = PHY_GBIT_FEATURES; phydev = phy_connect(priv->bus, slave->data->phy_addr, - dev, + priv->dev, slave->data->phy_if); if (!phydev) @@ -946,30 +971,14 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave) return 1; } -int cpsw_register(struct cpsw_platform_data *data) +int _cpsw_register(struct cpsw_priv *priv) { - struct cpsw_priv *priv; struct cpsw_slave *slave; + struct cpsw_platform_data *data = &priv->data; void *regs = (void *)data->cpsw_base; - struct eth_device *dev; - - dev = calloc(sizeof(*dev), 1); - if (!dev) - return -ENOMEM; - - priv = calloc(sizeof(*priv), 1); - if (!priv) { - free(dev); - return -ENOMEM; - } - - priv->data = *data; - priv->dev = dev; priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves); if (!priv->slaves) { - free(dev); - free(priv); return -ENOMEM; } @@ -987,6 +996,71 @@ int cpsw_register(struct cpsw_platform_data *data) idx = idx + 1; } + cpsw_mdio_init(priv->dev->name, data->mdio_base, data->mdio_div); + priv->bus = miiphy_get_dev_by_name(priv->dev->name); + for_active_slave(slave, priv) + cpsw_phy_init(priv, slave); + + return 0; +} + +#ifndef CONFIG_DM_ETH +static int cpsw_init(struct eth_device *dev, bd_t *bis) +{ + struct cpsw_priv *priv = dev->priv; + + return _cpsw_init(priv, dev->enetaddr); +} + +static void cpsw_halt(struct eth_device *dev) +{ + struct cpsw_priv *priv = dev->priv; + + return _cpsw_halt(priv); +} + +static int cpsw_send(struct eth_device *dev, void *packet, int length) +{ + struct cpsw_priv *priv = dev->priv; + + return _cpsw_send(priv, packet, length); +} + +static int cpsw_recv(struct eth_device *dev) +{ + struct cpsw_priv *priv = dev->priv; + uchar *pkt = NULL; + int len; + + len = _cpsw_recv(priv, &pkt); + + if (len > 0) { + net_process_received_packet(pkt, len); + cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE); + } + + return len; +} + +int cpsw_register(struct cpsw_platform_data *data) +{ + struct cpsw_priv *priv; + struct eth_device *dev; + int ret; + + dev = calloc(sizeof(*dev), 1); + if (!dev) + return -ENOMEM; + + priv = calloc(sizeof(*priv), 1); + if (!priv) { + free(dev); + return -ENOMEM; + } + + priv->dev = dev; + priv->data = *data; + strcpy(dev->name, "cpsw"); dev->iobase = 0; dev->init = cpsw_init; @@ -997,10 +1071,224 @@ int cpsw_register(struct cpsw_platform_data *data) eth_register(dev); - cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div); - priv->bus = miiphy_get_dev_by_name(dev->name); - for_active_slave(slave, priv) - cpsw_phy_init(dev, slave); + ret = _cpsw_register(priv); + if (ret < 0) { + eth_unregister(dev); + free(dev); + free(priv); + return ret; + } return 1; } +#else +static int cpsw_eth_start(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct cpsw_priv *priv = dev_get_priv(dev); + + return _cpsw_init(priv, pdata->enetaddr); +} + +static int cpsw_eth_send(struct udevice *dev, void *packet, int length) +{ + struct cpsw_priv *priv = dev_get_priv(dev); + + return _cpsw_send(priv, packet, length); +} + +static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct cpsw_priv *priv = dev_get_priv(dev); + + return _cpsw_recv(priv, packetp); +} + +static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct cpsw_priv *priv = dev_get_priv(dev); + + return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE); +} + +static void cpsw_eth_stop(struct udevice *dev) +{ + struct cpsw_priv *priv = dev_get_priv(dev); + + return _cpsw_halt(priv); +} + + +static int cpsw_eth_probe(struct udevice *dev) +{ + struct cpsw_priv *priv = dev_get_priv(dev); + + priv->dev = dev; + + return _cpsw_register(priv); +} + +static const struct eth_ops cpsw_eth_ops = { + .start = cpsw_eth_start, + .send = cpsw_eth_send, + .recv = cpsw_eth_recv, + .free_pkt = cpsw_eth_free_pkt, + .stop = cpsw_eth_stop, +}; + +static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct cpsw_priv *priv = dev_get_priv(dev); + const char *phy_mode; + const void *fdt = gd->fdt_blob; + int node = dev->of_offset; + int subnode; + int slave_index = 0; + uint32_t mac_hi, mac_lo; + fdt32_t gmii = 0; + int active_slave; + + pdata->iobase = dev_get_addr(dev); + priv->data.version = CPSW_CTRL_VERSION_2; + priv->data.bd_ram_ofs = CPSW_BD_OFFSET; + priv->data.ale_reg_ofs = CPSW_ALE_OFFSET; + priv->data.cpdma_reg_ofs = CPSW_CPDMA_OFFSET; + priv->data.mdio_div = CPSW_MDIO_DIV; + priv->data.host_port_reg_ofs = CPSW_HOST_PORT_OFFSET, + + pdata->phy_interface = -1; + + priv->data.cpsw_base = pdata->iobase; + priv->data.channels = fdtdec_get_int(fdt, node, "cpdma_channels", -1); + if (priv->data.channels <= 0) { + printf("error: cpdma_channels not found in dt\n"); + return -ENOENT; + } + + priv->data.slaves = fdtdec_get_int(fdt, node, "slaves", -1); + if (priv->data.slaves <= 0) { + printf("error: slaves not found in dt\n"); + return -ENOENT; + } + priv->data.slave_data = malloc(sizeof(struct cpsw_slave_data) * + priv->data.slaves); + + priv->data.ale_entries = fdtdec_get_int(fdt, node, "ale_entries", -1); + if (priv->data.ale_entries <= 0) { + printf("error: ale_entries not found in dt\n"); + return -ENOENT; + } + + priv->data.bd_ram_ofs = fdtdec_get_int(fdt, node, "bd_ram_size", -1); + if (priv->data.bd_ram_ofs <= 0) { + printf("error: bd_ram_size not found in dt\n"); + return -ENOENT; + } + + priv->data.mac_control = fdtdec_get_int(fdt, node, "mac_control", -1); + if (priv->data.mac_control <= 0) { + printf("error: ale_entries not found in dt\n"); + return -ENOENT; + } + + active_slave = fdtdec_get_int(fdt, node, "active_slave", 0); + priv->data.active_slave = active_slave; + + fdt_for_each_subnode(fdt, subnode, node) { + int len; + const char *name; + + name = fdt_get_name(fdt, subnode, &len); + if (!strncmp(name, "mdio", 4)) { + priv->data.mdio_base = fdtdec_get_addr(fdt, subnode, + "reg"); + } + + if (!strncmp(name, "slave", 5)) { + u32 phy_id[2]; + + if (slave_index >= priv->data.slaves) { + printf("error: num slaves and slave nodes did not match\n"); + return -EINVAL; + } + phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL); + if (phy_mode) + priv->data.slave_data[slave_index].phy_if = + phy_get_interface_by_name(phy_mode); + fdtdec_get_int_array(fdt, subnode, "phy_id", phy_id, 2); + priv->data.slave_data[slave_index].phy_addr = phy_id[1]; + slave_index++; + } + + if (!strncmp(name, "cpsw-phy-sel", 12)) { + priv->data.gmii_sel = fdtdec_get_addr(fdt, subnode, + "reg"); + } + } + + priv->data.slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET; + priv->data.slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET; + + if (priv->data.slaves == 2) { + priv->data.slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET; + priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET; + } + + subnode = fdtdec_lookup_phandle(fdt, node, "syscon"); + priv->data.mac_id = fdt_translate_address((void *)fdt, subnode, &gmii); + priv->data.mac_id += AM335X_GMII_SEL_OFFSET; + priv->data.mac_id += active_slave * 8; + + /* try reading mac address from efuse */ + mac_lo = readl(priv->data.mac_id); + mac_hi = readl(priv->data.mac_id + 4); + pdata->enetaddr[0] = mac_hi & 0xFF; + pdata->enetaddr[1] = (mac_hi & 0xFF00) >> 8; + pdata->enetaddr[2] = (mac_hi & 0xFF0000) >> 16; + pdata->enetaddr[3] = (mac_hi & 0xFF000000) >> 24; + pdata->enetaddr[4] = mac_lo & 0xFF; + pdata->enetaddr[5] = (mac_lo & 0xFF00) >> 8; + + pdata->phy_interface = priv->data.slave_data[active_slave].phy_if; + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + switch (pdata->phy_interface) { + case PHY_INTERFACE_MODE_MII: + writel(MII_MODE_ENABLE, priv->data.gmii_sel); + break; + case PHY_INTERFACE_MODE_RMII: + writel(RMII_MODE_ENABLE, priv->data.gmii_sel); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + writel(RGMII_MODE_ENABLE, priv->data.gmii_sel); + break; + } + return 0; +} + + +static const struct udevice_id cpsw_eth_ids[] = { + { .compatible = "ti,cpsw" }, + { .compatible = "ti,am335x-cpsw" }, + { } +}; + +U_BOOT_DRIVER(eth_cpsw) = { + .name = "eth_cpsw", + .id = UCLASS_ETH, + .of_match = cpsw_eth_ids, + .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata, + .probe = cpsw_eth_probe, + .ops = &cpsw_eth_ops, + .priv_auto_alloc_size = sizeof(struct cpsw_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#endif /* CONFIG_DM_ETH */ diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 67b5702..5ed29ae 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -42,7 +42,9 @@ struct rx_buff_desc net_rx_buffs = { .rx_flow = 22, }; +#ifndef CONFIG_SOC_K2G static void keystone2_net_serdes_setup(void); +#endif int keystone2_eth_read_mac_addr(struct eth_device *dev) { @@ -161,16 +163,37 @@ static void __attribute__((unused)) DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL); } -int keystone_sgmii_link_status(int port) +#ifdef CONFIG_SOC_K2G +int keystone_rgmii_config(struct phy_device *phy_dev) { - u32 status = 0; + unsigned int i, status; - status = __raw_readl(SGMII_STATUS_REG(port)); + i = 0; + do { + if (i > SGMII_ANEG_TIMEOUT) { + puts(" TIMEOUT !\n"); + phy_dev->link = 0; + return 0; + } - return (status & SGMII_REG_STATUS_LOCK) && - (status & SGMII_REG_STATUS_LINK); -} + if (ctrlc()) { + puts("user interrupt!\n"); + phy_dev->link = 0; + return -EINTR; + } + if ((i++ % 500) == 0) + printf("."); + + udelay(1000); /* 1 ms */ + status = readl(RGMII_STATUS_REG); + } while (!(status & RGMII_REG_STATUS_LINK)); + + puts(" done\n"); + + return 0; +} +#else int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface) { unsigned int i, status, mask; @@ -264,6 +287,7 @@ int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface) return 0; } +#endif int mac_sl_reset(u32 port) { @@ -315,7 +339,7 @@ int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN); writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL); -#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) +#ifndef CONFIG_SOC_K2HK /* Map RX packet flow priority to 0 */ writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP); #endif @@ -401,8 +425,12 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) if (sys_has_mdio) keystone2_mdio_reset(mdio_bus); +#ifdef CONFIG_SOC_K2G + keystone_rgmii_config(phy_dev); +#else keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1, eth_priv->sgmii_link_type); +#endif udelay(10000); @@ -564,16 +592,18 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv) return res; } +#ifndef CONFIG_SOC_K2G keystone2_net_serdes_setup(); +#endif /* Create phy device and bind it with driver */ #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr, - dev, PHY_INTERFACE_MODE_SGMII); + dev, eth_priv->phy_if); phy_config(phy_dev); #else phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr, - PHY_INTERFACE_MODE_SGMII); + eth_priv->phy_if); phy_dev->dev = dev; #endif eth_priv->phy_dev = phy_dev; @@ -589,6 +619,7 @@ struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { .loopback = 0, }; +#ifndef CONFIG_SOC_K2G static void keystone2_net_serdes_setup(void) { ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, @@ -604,3 +635,4 @@ static void keystone2_net_serdes_setup(void) /* wait till setup */ udelay(5000); } +#endif diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 0756bbe..1d93194 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -85,30 +85,7 @@ static int pci_get_bus_max(void) int pci_last_busno(void) { - struct pci_controller *hose; - struct udevice *bus; - struct uclass *uc; - int ret; - - debug("pci_last_busno\n"); - ret = uclass_get(UCLASS_PCI, &uc); - if (ret || list_empty(&uc->dev_head)) - return -1; - - /* Probe the last bus */ - bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node); - debug("bus = %p, %s\n", bus, bus->name); - assert(bus); - ret = device_probe(bus); - if (ret) - return ret; - - /* If that bus has bridges, we may have new buses now. Get the last */ - bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node); - hose = dev_get_uclass_priv(bus); - debug("bus = %s, hose = %p\n", bus->name, hose); - - return hose->last_busno; + return pci_get_bus_max(); } int pci_get_ff(enum pci_size_t size) @@ -387,9 +364,23 @@ int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep) return 0; } +static void set_vga_bridge_bits(struct udevice *dev) +{ + struct udevice *parent = dev->parent; + u16 bc; + + while (parent->seq != 0) { + dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc); + bc |= PCI_BRIDGE_CTL_VGA; + dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc); + parent = parent->parent; + } +} + int pci_auto_config_devices(struct udevice *bus) { struct pci_controller *hose = bus->uclass_priv; + struct pci_child_platdata *pplat; unsigned int sub_bus; struct udevice *dev; int ret; @@ -401,10 +392,18 @@ int pci_auto_config_devices(struct udevice *bus) !ret && dev; ret = device_find_next_child(&dev)) { unsigned int max_bus; + int ret; debug("%s: device %s\n", __func__, dev->name); - max_bus = pciauto_config_device(hose, pci_get_bdf(dev)); + ret = pciauto_config_device(hose, pci_get_bdf(dev)); + if (ret < 0) + return ret; + max_bus = ret; sub_bus = max(sub_bus, max_bus); + + pplat = dev_get_parent_platdata(dev); + if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8)) + set_vga_bridge_bits(dev); } debug("%s: done\n", __func__); @@ -434,7 +433,7 @@ int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf) ret = device_probe(bus); if (ret) { - debug("%s: Cannot probe bus bus %s: %d\n", __func__, bus->name, + debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name, ret); return ret; } @@ -474,10 +473,17 @@ static bool pci_match_one_id(const struct pci_device_id *id, * pci_find_and_bind_driver() - Find and bind the right PCI driver * * This only looks at certain fields in the descriptor. + * + * @parent: Parent bus + * @find_id: Specification of the driver to find + * @bdf: Bus/device/function addreess - see PCI_BDF() + * @devp: Returns a pointer to the device created + * @return 0 if OK, -EPERM if the device is not needed before relocation and + * therefore was not created, other -ve value on error */ static int pci_find_and_bind_driver(struct udevice *parent, - struct pci_device_id *find_id, pci_dev_t bdf, - struct udevice **devp) + struct pci_device_id *find_id, + pci_dev_t bdf, struct udevice **devp) { struct pci_driver_entry *start, *entry; const char *drv; @@ -513,7 +519,7 @@ static int pci_find_and_bind_driver(struct udevice *parent, */ if (!(gd->flags & GD_FLG_RELOC) && !(drv->flags & DM_FLAG_PRE_RELOC)) - return 0; + return -EPERM; /* * We could pass the descriptor to the driver as @@ -541,7 +547,7 @@ static int pci_find_and_bind_driver(struct udevice *parent, * limited (ie: using Cache As RAM). */ if (!(gd->flags & GD_FLG_RELOC) && !bridge) - return 0; + return -EPERM; /* Bind a generic driver so that the device can be used */ sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf), @@ -553,7 +559,7 @@ static int pci_find_and_bind_driver(struct udevice *parent, ret = device_bind_driver(parent, drv, str, devp); if (ret) { - debug("%s: Failed to bind generic driver: %d", __func__, ret); + debug("%s: Failed to bind generic driver: %d\n", __func__, ret); return ret; } debug("%s: No match found: bound generic driver instead\n", __func__); @@ -629,17 +635,17 @@ int pci_bind_bus_devices(struct udevice *bus) ret = pci_find_and_bind_driver(bus, &find_id, bdf, &dev); } - if (ret) + if (ret == -EPERM) + continue; + else if (ret) return ret; /* Update the platform data */ - if (dev) { - pplat = dev_get_parent_platdata(dev); - pplat->devfn = PCI_MASK_BUS(bdf); - pplat->vendor = vendor; - pplat->device = device; - pplat->class = class; - } + pplat = dev_get_parent_platdata(dev); + pplat->devfn = PCI_MASK_BUS(bdf); + pplat->vendor = vendor; + pplat->device = device; + pplat->class = class; } return 0; @@ -777,6 +783,8 @@ static int pci_uclass_post_probe(struct udevice *bus) #ifdef CONFIG_PCI_PNP ret = pci_auto_config_devices(bus); + if (ret < 0) + return ret; #endif #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP) @@ -793,11 +801,14 @@ static int pci_uclass_post_probe(struct udevice *bus) * Note we only call this 1) after U-Boot is relocated, and 2) * root bus has finished probing. */ - if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) + if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) { ret = fsp_init_phase_pci(); + if (ret) + return ret; + } #endif - return ret < 0 ? ret : 0; + return 0; } static int pci_uclass_child_post_bind(struct udevice *dev) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 79f27c7..0412bf3 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -89,6 +89,7 @@ void pciauto_setup_device(struct pci_controller *hose, struct pci_region *bar_res; int found_mem64 = 0; #endif + u16 class; pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; @@ -206,6 +207,11 @@ void pciauto_setup_device(struct pci_controller *hose, } #endif + /* PCI_COMMAND_IO must be set for VGA device */ + pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); + if (class == PCI_CLASS_DISPLAY_VGA) + cmdstat |= PCI_COMMAND_IO; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat); pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, CONFIG_SYS_PCI_CACHE_LINE_SIZE); diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 1568f20..f1e189e 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -19,6 +19,7 @@ #include <asm/io.h> #include <linux/sizes.h> #include <errno.h> +#include <asm/arch/sys_proto.h> #define PCI_ACCESS_READ 0 #define PCI_ACCESS_WRITE 1 @@ -430,6 +431,10 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d, static int imx6_pcie_assert_core_reset(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + if (is_mx6dqp()) + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST); + #if defined(CONFIG_MX6SX) struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR; @@ -536,6 +541,9 @@ static int imx6_pcie_deassert_core_reset(void) enable_pcie_clock(); + if (is_mx6dqp()) + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST); + /* * Wait for the clock to settle a bit, when the clock are sourced * from the CPU, we need about 30 ms to settle. diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index df5e373..809f8f1 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -4,87 +4,201 @@ source "drivers/power/pmic/Kconfig" source "drivers/power/regulator/Kconfig" +choice + prompt "Select Sunxi PMIC Variant" + depends on ARCH_SUNXI + default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I + default AXP221_POWER if MACH_SUN6I || MACH_SUN8I + +config SUNXI_NO_PMIC + boolean "board without a pmic" + ---help--- + Select this for boards which do not use a PMIC. + +config AXP152_POWER + boolean "axp152 pmic support" + depends on MACH_SUN5I + ---help--- + Select this to enable support for the axp152 pmic found on most + A10s boards. + +config AXP209_POWER + boolean "axp209 pmic support" + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I + ---help--- + Select this to enable support for the axp209 pmic found on most + A10, A13 and A20 boards. + config AXP221_POWER boolean "axp221 / axp223 pmic support" depends on MACH_SUN6I || MACH_SUN8I - default y ---help--- - Say y here to enable support for the axp221 / axp223 pmic found on most - sun6i (A31) / sun8i (A23) boards. + Select this to enable support for the axp221/axp223 pmic found on most + A23 and A31 boards. + +endchoice + +config AXP_DCDC1_VOLT + int "axp pmic dcdc1 voltage" + depends on AXP221_POWER + default 3000 if MACH_SUN6I || MACH_SUN8I + ---help--- + Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to + disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for + generic 3.3V IO voltage for external devices like the lcd-panal and + sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to + safe battery. On A31 devices dcdc1 is also used for VCC-IO. -config AXP221_DCDC1_VOLT - int "axp221 dcdc1 voltage" +config AXP_DCDC2_VOLT + int "axp pmic dcdc2 voltage" + depends on AXP152_POWER || AXP209_POWER || AXP221_POWER + default 1400 if AXP152_POWER || AXP209_POWER + default 1200 if MACH_SUN6I + default 1100 if MACH_SUN8I + ---help--- + Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to + disable dcdc2. + On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V. + On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V. + On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V. + +config AXP_DCDC3_VOLT + int "axp pmic dcdc3 voltage" + depends on AXP152_POWER || AXP209_POWER || AXP221_POWER + default 1500 if AXP152_POWER + default 1250 if AXP209_POWER + default 1200 if MACH_SUN6I || MACH_SUN8I + ---help--- + Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to + disable dcdc3. + On A10(s) / A13 / A20 boards with an axp209 dcdc3 is VDD-INT-DLL and + should be 1.25V. + On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V. + On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V. + +config AXP_DCDC4_VOLT + int "axp pmic dcdc4 voltage" + depends on AXP152_POWER || AXP221_POWER + default 1250 if AXP152_POWER + default 1200 if MACH_SUN6I + default 0 if MACH_SUN8I + ---help--- + Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to + disable dcdc4. + On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V. + On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V. + On A23 / A33 boards dcdc4 is unused and should be disabled. + +config AXP_DCDC5_VOLT + int "axp pmic dcdc5 voltage" depends on AXP221_POWER - default 3000 + default 1500 if MACH_SUN6I || MACH_SUN8I ---help--- - Set the voltage (mV) to program the axp221 dcdc1 at, set to 0 to - disable dcdc1. This is typically used as generic 3.3V IO voltage for - things like GPIO-s, sdcard interfaces, etc. On most boards this is - undervolted to 3.0V to safe battery. + Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to + disable dcdc5. + On A23 / A31 / A33 boards dcdc5 is VCC-DRAM and should be 1.5V. -config AXP221_DCDC2_VOLT - int "axp221 dcdc2 voltage" +config AXP_ALDO1_VOLT + int "axp pmic (a)ldo1 voltage" depends on AXP221_POWER - default 1200 + default 0 if MACH_SUN6I + default 3000 if MACH_SUN8I ---help--- - Set the voltage (mV) to program the axp221 dcdc2 at, set to 0 to - disable dcdc2. On A31 boards this is typically used for VDD-GPU, - on A23/A33 for VDD-SYS, this should normally be set to 1.2V. + Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to + disable aldo1. + On A31 boards aldo1 is often used to power the wifi module. + On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V. -config AXP221_DLDO1_VOLT - int "axp221 dldo1 voltage" +config AXP_ALDO2_VOLT + int "axp pmic (a)ldo2 voltage" + depends on AXP152_POWER || AXP209_POWER || AXP221_POWER + default 3000 if AXP152_POWER || AXP209_POWER + default 0 if MACH_SUN6I + default 2500 if MACH_SUN8I + ---help--- + Set the voltage (mV) to program the axp pmic aldo2 at, set to 0 to + disable aldo2. + On A10(s) / A13 / A20 boards aldo2 is AVCC and should be 3.0V. + On A31 boards aldo2 is typically unused and should be disabled. + On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V. + On A23 / A33 boards aldo2 is used for VDD-DLL and should be 2.5V. + +config AXP_ALDO3_VOLT + int "axp pmic (a)ldo3 voltage" + depends on AXP209_POWER || AXP221_POWER + default 0 if AXP209_POWER + default 3000 if MACH_SUN6I || MACH_SUN8I + ---help--- + Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to + disable aldo3. + On A10(s) / A13 / A20 boards aldo3 should be 2.8V. + On A23 / A31 / A33 boards aldo3 is VCC-PLL and AVCC and should be 3.0V. + +config AXP_ALDO4_VOLT + int "axp pmic (a)ldo4 voltage" + depends on AXP209_POWER + default 0 if AXP209_POWER + ---help--- + Set the voltage (mV) to program the axp pmic aldo4 at, set to 0 to + disable aldo4. + On A10(s) / A13 / A20 boards aldo4 should be 2.8V. + +config AXP_DLDO1_VOLT + int "axp pmic dldo1 voltage" depends on AXP221_POWER default 0 ---help--- - Set the voltage (mV) to program the axp221 dldo1 at, set to 0 to - disable dldo1. On sun6i (A31) boards with ethernet this is often used + Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to + disable dldo1. On sun6i (A31) boards with ethernet dldo1 is often used to power the ethernet phy. On sun8i (A23) boards this is often used to power the wifi. -config AXP221_DLDO4_VOLT - int "axp221 dldo4 voltage" +config AXP_DLDO2_VOLT + int "axp pmic dldo2 voltage" depends on AXP221_POWER default 0 ---help--- - Set the voltage (mV) to program the axp221 dldo4 at, set to 0 to - disable dldo4. + Set the voltage (mV) to program the axp pmic dldo2 at, set to 0 to + disable dldo2. -config AXP221_ALDO1_VOLT - int "axp221 aldo1 voltage" +config AXP_DLDO3_VOLT + int "axp pmic dldo3 voltage" depends on AXP221_POWER default 0 ---help--- - Set the voltage (mV) to program the axp221 aldo1 at, set to 0 to - disable aldo1. On sun6i (A31) boards which have a wifi module this is - often used to power the wifi module. + Set the voltage (mV) to program the axp pmic dldo3 at, set to 0 to + disable dldo3. -config AXP221_ALDO2_VOLT - int "axp221 aldo2 voltage" +config AXP_DLDO4_VOLT + int "axp pmic dldo4 voltage" depends on AXP221_POWER - default 0 if MACH_SUN6I - default 2500 if MACH_SUN8I + default 0 ---help--- - Set the voltage (mV) to program the axp221 aldo2 at, set to 0 to - disable aldo2. On sun6i (A31) boards this is typically unused and - should be disabled, if it is used for LPDDR2 it should be set to 1.8V. - On sun8i (A23) this is typically connected to VDD-DLL and must be set - to 2.5V. + Set the voltage (mV) to program the axp pmic dldo4 at, set to 0 to + disable dldo4. -config AXP221_ALDO3_VOLT - int "axp221 aldo3 voltage" +config AXP_ELDO1_VOLT + int "axp pmic eldo1 voltage" depends on AXP221_POWER - default 3000 + default 0 + ---help--- + Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to + disable eldo1. + +config AXP_ELDO2_VOLT + int "axp pmic eldo2 voltage" + depends on AXP221_POWER + default 0 ---help--- - Set the voltage (mV) to program the axp221 aldo3 at, set to 0 to - disable aldo3. This is typically connected to VCC-PLL and AVCC and - must be set to 3V. + Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to + disable eldo2. -config AXP221_ELDO3_VOLT - int "axp221 eldo3 voltage" +config AXP_ELDO3_VOLT + int "axp pmic eldo3 voltage" depends on AXP221_POWER default 0 ---help--- - Set the voltage (mV) to program the axp221 eldo3 at, set to 0 to + Set the voltage (mV) to program the axp pmic eldo3 at, set to 0 to disable eldo3. On some A31(s) tablets it might be used to supply 1.2V for the SSD2828 chip (converter of parallel LCD interface into MIPI DSI). diff --git a/drivers/power/axp152.c b/drivers/power/axp152.c index 740a3b4..2972586 100644 --- a/drivers/power/axp152.c +++ b/drivers/power/axp152.c @@ -5,18 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include <i2c.h> -#include <axp152.h> - -static int axp152_write(enum axp152_reg reg, u8 val) -{ - return i2c_write(0x30, reg, 1, &val, 1); -} - -static int axp152_read(enum axp152_reg reg, u8 *val) -{ - return i2c_read(0x30, reg, 1, val, 1); -} +#include <asm/arch/pmic_bus.h> +#include <axp_pmic.h> static u8 axp152_mvolt_to_target(int mvolt, int min, int max, int div) { @@ -28,7 +18,7 @@ static u8 axp152_mvolt_to_target(int mvolt, int min, int max, int div) return (mvolt - min) / div; } -int axp152_set_dcdc2(int mvolt) +int axp_set_dcdc2(unsigned int mvolt) { int rc; u8 current, target; @@ -36,46 +26,50 @@ int axp152_set_dcdc2(int mvolt) target = axp152_mvolt_to_target(mvolt, 700, 2275, 25); /* Do we really need to be this gentle? It has built-in voltage slope */ - while ((rc = axp152_read(AXP152_DCDC2_VOLTAGE, ¤t)) == 0 && + while ((rc = pmic_bus_read(AXP152_DCDC2_VOLTAGE, ¤t)) == 0 && current != target) { if (current < target) current++; else current--; - rc = axp152_write(AXP152_DCDC2_VOLTAGE, current); + rc = pmic_bus_write(AXP152_DCDC2_VOLTAGE, current); if (rc) break; } return rc; } -int axp152_set_dcdc3(int mvolt) +int axp_set_dcdc3(unsigned int mvolt) { u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 50); - return axp152_write(AXP152_DCDC3_VOLTAGE, target); + return pmic_bus_write(AXP152_DCDC3_VOLTAGE, target); } -int axp152_set_dcdc4(int mvolt) +int axp_set_dcdc4(unsigned int mvolt) { u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 25); - return axp152_write(AXP152_DCDC4_VOLTAGE, target); + return pmic_bus_write(AXP152_DCDC4_VOLTAGE, target); } -int axp152_set_ldo2(int mvolt) +int axp_set_aldo2(unsigned int mvolt) { u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 100); - return axp152_write(AXP152_LDO2_VOLTAGE, target); + return pmic_bus_write(AXP152_LDO2_VOLTAGE, target); } -int axp152_init(void) +int axp_init(void) { u8 ver; int rc; - rc = axp152_read(AXP152_CHIP_VERSION, &ver); + rc = pmic_bus_init(); + if (rc) + return rc; + + rc = pmic_bus_read(AXP152_CHIP_VERSION, &ver); if (rc) return rc; diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c index 5161bc1..71aa000 100644 --- a/drivers/power/axp209.c +++ b/drivers/power/axp209.c @@ -6,19 +6,8 @@ */ #include <common.h> -#include <i2c.h> -#include <asm/arch/gpio.h> -#include <axp209.h> - -static int axp209_write(enum axp209_reg reg, u8 val) -{ - return i2c_write(0x34, reg, 1, &val, 1); -} - -static int axp209_read(enum axp209_reg reg, u8 *val) -{ - return i2c_read(0x34, reg, 1, val, 1); -} +#include <asm/arch/pmic_bus.h> +#include <axp_pmic.h> static u8 axp209_mvolt_to_cfg(int mvolt, int min, int max, int div) { @@ -30,22 +19,30 @@ static u8 axp209_mvolt_to_cfg(int mvolt, int min, int max, int div) return (mvolt - min) / div; } -int axp209_set_dcdc2(int mvolt) +int axp_set_dcdc2(unsigned int mvolt) { int rc; u8 cfg, current; + if (mvolt == 0) + return pmic_bus_clrbits(AXP209_OUTPUT_CTRL, + AXP209_OUTPUT_CTRL_DCDC2); + + rc = pmic_bus_setbits(AXP209_OUTPUT_CTRL, AXP209_OUTPUT_CTRL_DCDC2); + if (rc) + return rc; + cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25); /* Do we really need to be this gentle? It has built-in voltage slope */ - while ((rc = axp209_read(AXP209_DCDC2_VOLTAGE, ¤t)) == 0 && + while ((rc = pmic_bus_read(AXP209_DCDC2_VOLTAGE, ¤t)) == 0 && current != cfg) { if (current < cfg) current++; else current--; - rc = axp209_write(AXP209_DCDC2_VOLTAGE, current); + rc = pmic_bus_write(AXP209_DCDC2_VOLTAGE, current); if (rc) break; } @@ -53,68 +50,106 @@ int axp209_set_dcdc2(int mvolt) return rc; } -int axp209_set_dcdc3(int mvolt) +int axp_set_dcdc3(unsigned int mvolt) { u8 cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25); + int rc; - return axp209_write(AXP209_DCDC3_VOLTAGE, cfg); + if (mvolt == 0) + return pmic_bus_clrbits(AXP209_OUTPUT_CTRL, + AXP209_OUTPUT_CTRL_DCDC3); + + rc = pmic_bus_write(AXP209_DCDC3_VOLTAGE, cfg); + if (rc) + return rc; + + return pmic_bus_setbits(AXP209_OUTPUT_CTRL, AXP209_OUTPUT_CTRL_DCDC3); } -int axp209_set_ldo2(int mvolt) +int axp_set_aldo2(unsigned int mvolt) { int rc; u8 cfg, reg; + if (mvolt == 0) + return pmic_bus_clrbits(AXP209_OUTPUT_CTRL, + AXP209_OUTPUT_CTRL_LDO2); + cfg = axp209_mvolt_to_cfg(mvolt, 1800, 3300, 100); - rc = axp209_read(AXP209_LDO24_VOLTAGE, ®); + rc = pmic_bus_read(AXP209_LDO24_VOLTAGE, ®); if (rc) return rc; /* LDO2 configuration is in upper 4 bits */ reg = (reg & 0x0f) | (cfg << 4); - return axp209_write(AXP209_LDO24_VOLTAGE, reg); + rc = pmic_bus_write(AXP209_LDO24_VOLTAGE, reg); + if (rc) + return rc; + + return pmic_bus_setbits(AXP209_OUTPUT_CTRL, AXP209_OUTPUT_CTRL_LDO2); } -int axp209_set_ldo3(int mvolt) +int axp_set_aldo3(unsigned int mvolt) { u8 cfg; + int rc; + + if (mvolt == 0) + return pmic_bus_clrbits(AXP209_OUTPUT_CTRL, + AXP209_OUTPUT_CTRL_LDO3); if (mvolt == -1) cfg = 0x80; /* determined by LDO3IN pin */ else cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25); - return axp209_write(AXP209_LDO3_VOLTAGE, cfg); + rc = pmic_bus_write(AXP209_LDO3_VOLTAGE, cfg); + if (rc) + return rc; + + return pmic_bus_setbits(AXP209_OUTPUT_CTRL, AXP209_OUTPUT_CTRL_LDO3); } -int axp209_set_ldo4(int mvolt) +int axp_set_aldo4(unsigned int mvolt) { int rc; - static const int vindex[] = { + static const unsigned int vindex[] = { 1250, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2500, 2700, 2800, 3000, 3100, 3200, 3300 }; u8 cfg, reg; + if (mvolt == 0) + return pmic_bus_clrbits(AXP209_OUTPUT_CTRL, + AXP209_OUTPUT_CTRL_LDO4); + /* Translate mvolt to register cfg value, requested <= selected */ for (cfg = 15; vindex[cfg] > mvolt && cfg > 0; cfg--); - rc = axp209_read(AXP209_LDO24_VOLTAGE, ®); + rc = pmic_bus_read(AXP209_LDO24_VOLTAGE, ®); if (rc) return rc; /* LDO4 configuration is in lower 4 bits */ reg = (reg & 0xf0) | (cfg << 0); - return axp209_write(AXP209_LDO24_VOLTAGE, reg); + rc = pmic_bus_write(AXP209_LDO24_VOLTAGE, reg); + if (rc) + return rc; + + return pmic_bus_setbits(AXP209_OUTPUT_CTRL, AXP209_OUTPUT_CTRL_LDO4); } -int axp209_init(void) +int axp_init(void) { u8 ver; int i, rc; - rc = axp209_read(AXP209_CHIP_VERSION, &ver); + rc = pmic_bus_init(); + if (rc) + return rc; + + rc = pmic_bus_read(AXP209_CHIP_VERSION, &ver); if (rc) return rc; @@ -126,32 +161,10 @@ int axp209_init(void) /* Mask all interrupts */ for (i = AXP209_IRQ_ENABLE1; i <= AXP209_IRQ_ENABLE5; i++) { - rc = axp209_write(i, 0); + rc = pmic_bus_write(i, 0); if (rc) return rc; } return 0; } - -int axp209_poweron_by_dc(void) -{ - u8 v; - - if (axp209_read(AXP209_POWER_STATUS, &v)) - return 0; - - return (v & AXP209_POWER_STATUS_ON_BY_DC); -} - -int axp209_power_button(void) -{ - u8 v; - - if (axp209_read(AXP209_IRQ_STATUS5, &v)) - return 0; - - axp209_write(AXP209_IRQ_STATUS5, AXP209_IRQ5_PEK_DOWN); - - return v & AXP209_IRQ5_PEK_DOWN; -} diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c index 7bbaec8..65802e4 100644 --- a/drivers/power/axp221.c +++ b/drivers/power/axp221.c @@ -12,9 +12,8 @@ #include <common.h> #include <errno.h> -#include <asm/arch/gpio.h> #include <asm/arch/pmic_bus.h> -#include <axp221.h> +#include <axp_pmic.h> static u8 axp221_mvolt_to_cfg(int mvolt, int min, int max, int div) { @@ -26,7 +25,7 @@ static u8 axp221_mvolt_to_cfg(int mvolt, int min, int max, int div) return (mvolt - min) / div; } -int axp221_set_dcdc1(unsigned int mvolt) +int axp_set_dcdc1(unsigned int mvolt) { int ret; u8 cfg = axp221_mvolt_to_cfg(mvolt, 1600, 3400, 100); @@ -48,7 +47,7 @@ int axp221_set_dcdc1(unsigned int mvolt) AXP221_OUTPUT_CTRL1_DCDC1_EN); } -int axp221_set_dcdc2(unsigned int mvolt) +int axp_set_dcdc2(unsigned int mvolt) { int ret; u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20); @@ -65,7 +64,7 @@ int axp221_set_dcdc2(unsigned int mvolt) AXP221_OUTPUT_CTRL1_DCDC2_EN); } -int axp221_set_dcdc3(unsigned int mvolt) +int axp_set_dcdc3(unsigned int mvolt) { int ret; u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1860, 20); @@ -82,7 +81,7 @@ int axp221_set_dcdc3(unsigned int mvolt) AXP221_OUTPUT_CTRL1_DCDC3_EN); } -int axp221_set_dcdc4(unsigned int mvolt) +int axp_set_dcdc4(unsigned int mvolt) { int ret; u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20); @@ -99,7 +98,7 @@ int axp221_set_dcdc4(unsigned int mvolt) AXP221_OUTPUT_CTRL1_DCDC4_EN); } -int axp221_set_dcdc5(unsigned int mvolt) +int axp_set_dcdc5(unsigned int mvolt) { int ret; u8 cfg = axp221_mvolt_to_cfg(mvolt, 1000, 2550, 50); @@ -116,7 +115,7 @@ int axp221_set_dcdc5(unsigned int mvolt) AXP221_OUTPUT_CTRL1_DCDC5_EN); } -int axp221_set_dldo1(unsigned int mvolt) +int axp_set_dldo1(unsigned int mvolt) { int ret; u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); @@ -133,7 +132,7 @@ int axp221_set_dldo1(unsigned int mvolt) AXP221_OUTPUT_CTRL2_DLDO1_EN); } -int axp221_set_dldo2(unsigned int mvolt) +int axp_set_dldo2(unsigned int mvolt) { int ret; u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); @@ -150,7 +149,7 @@ int axp221_set_dldo2(unsigned int mvolt) AXP221_OUTPUT_CTRL2_DLDO2_EN); } -int axp221_set_dldo3(unsigned int mvolt) +int axp_set_dldo3(unsigned int mvolt) { int ret; u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); @@ -167,7 +166,7 @@ int axp221_set_dldo3(unsigned int mvolt) AXP221_OUTPUT_CTRL2_DLDO3_EN); } -int axp221_set_dldo4(unsigned int mvolt) +int axp_set_dldo4(unsigned int mvolt) { int ret; u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); @@ -184,7 +183,7 @@ int axp221_set_dldo4(unsigned int mvolt) AXP221_OUTPUT_CTRL2_DLDO4_EN); } -int axp221_set_aldo1(unsigned int mvolt) +int axp_set_aldo1(unsigned int mvolt) { int ret; u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); @@ -201,7 +200,7 @@ int axp221_set_aldo1(unsigned int mvolt) AXP221_OUTPUT_CTRL1_ALDO1_EN); } -int axp221_set_aldo2(unsigned int mvolt) +int axp_set_aldo2(unsigned int mvolt) { int ret; u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); @@ -218,7 +217,7 @@ int axp221_set_aldo2(unsigned int mvolt) AXP221_OUTPUT_CTRL1_ALDO2_EN); } -int axp221_set_aldo3(unsigned int mvolt) +int axp_set_aldo3(unsigned int mvolt) { int ret; u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); @@ -235,7 +234,7 @@ int axp221_set_aldo3(unsigned int mvolt) AXP221_OUTPUT_CTRL3_ALDO3_EN); } -int axp221_set_eldo(int eldo_num, unsigned int mvolt) +int axp_set_eldo(int eldo_num, unsigned int mvolt) { int ret; u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100); @@ -268,16 +267,11 @@ int axp221_set_eldo(int eldo_num, unsigned int mvolt) return pmic_bus_setbits(AXP221_OUTPUT_CTRL2, bits); } -int axp221_init(void) +int axp_init(void) { - /* This cannot be 0 because it is used in SPL before BSS is ready */ - static int needs_init = 1; u8 axp_chip_id; int ret; - if (!needs_init) - return 0; - ret = pmic_bus_init(); if (ret) return ret; @@ -289,16 +283,15 @@ int axp221_init(void) if (!(axp_chip_id == 0x6 || axp_chip_id == 0x7 || axp_chip_id == 0x17)) return -ENODEV; - needs_init = 0; return 0; } -int axp221_get_sid(unsigned int *sid) +int axp_get_sid(unsigned int *sid) { u8 *dest = (u8 *)sid; int i, ret; - ret = axp221_init(); + ret = pmic_bus_init(); if (ret) return ret; diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig new file mode 100644 index 0000000..437224b --- /dev/null +++ b/drivers/remoteproc/Kconfig @@ -0,0 +1,24 @@ +# +# (C) Copyright 2015 +# Texas Instruments Incorporated - http://www.ti.com/ +# SPDX-License-Identifier: GPL-2.0+ +# + +menu "Remote Processor drivers" + +# REMOTEPROC gets selected by drivers as needed +# All users should depend on DM +config REMOTEPROC + bool + depends on DM + +# Please keep the configuration alphabetically sorted. +config REMOTEPROC_SANDBOX + bool "Support for Test processor for Sandbox" + select REMOTEPROC + depends on DM + depends on SANDBOX + help + Say 'y' here to add support for test processor which does dummy + operations for sandbox platform. +endmenu diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile new file mode 100644 index 0000000..720aa6e --- /dev/null +++ b/drivers/remoteproc/Makefile @@ -0,0 +1,10 @@ +# +# (C) Copyright 2015 +# Texas Instruments Incorporated - http://www.ti.com/ +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_REMOTEPROC) += rproc-uclass.o + +# Remote proc drivers - Please keep this list alphabetically sorted. +obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c new file mode 100644 index 0000000..a421e12 --- /dev/null +++ b/drivers/remoteproc/rproc-uclass.c @@ -0,0 +1,417 @@ +/* + * (C) Copyright 2015 + * Texas Instruments Incorporated - http://www.ti.com/ + * SPDX-License-Identifier: GPL-2.0+ + */ +#define pr_fmt(fmt) "%s: " fmt, __func__ +#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <malloc.h> +#include <remoteproc.h> +#include <asm/io.h> +#include <dm/device-internal.h> +#include <dm.h> +#include <dm/uclass.h> +#include <dm/uclass-internal.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * for_each_remoteproc_device() - iterate through the list of rproc devices + * @fn: check function to call per match, if this function returns fail, + * iteration is aborted with the resultant error value + * @skip_dev: Device to skip calling the callback about. + * @data: Data to pass to the callback function + * + * Return: 0 if none of the callback returned a non 0 result, else returns the + * result from the callback function + */ +static int for_each_remoteproc_device(int (*fn) (struct udevice *dev, + struct dm_rproc_uclass_pdata *uc_pdata, + const void *data), + struct udevice *skip_dev, + const void *data) +{ + struct udevice *dev; + struct dm_rproc_uclass_pdata *uc_pdata; + int ret; + + for (ret = uclass_find_first_device(UCLASS_REMOTEPROC, &dev); dev; + ret = uclass_find_next_device(&dev)) { + if (ret || dev == skip_dev) + continue; + uc_pdata = dev_get_uclass_platdata(dev); + ret = fn(dev, uc_pdata, data); + if (ret) + return ret; + } + + return 0; +} + +/** + * _rproc_name_is_unique() - iteration helper to check if rproc name is unique + * @dev: device that we are checking name for + * @uc_pdata: uclass platform data + * @data: compare data (this is the name we want to ensure is unique) + * + * Return: 0 is there is no match(is unique); if there is a match(we dont + * have a unique name), return -EINVAL. + */ +static int _rproc_name_is_unique(struct udevice *dev, + struct dm_rproc_uclass_pdata *uc_pdata, + const void *data) +{ + const char *check_name = data; + + /* devices not yet populated with data - so skip them */ + if (!uc_pdata->name && check_name) + return 0; + + /* Return 0 to search further if we dont match */ + if (strlen(uc_pdata->name) != strlen(check_name)) + return 0; + + if (!strcmp(uc_pdata->name, check_name)) + return -EINVAL; + + return 0; +} + +/** + * rproc_name_is_unique() - Check if the rproc name is unique + * @check_dev: Device we are attempting to ensure is unique + * @check_name: Name we are trying to ensure is unique. + * + * Return: true if we have a unique name, false if name is not unique. + */ +static bool rproc_name_is_unique(struct udevice *check_dev, + const char *check_name) +{ + int ret; + + ret = for_each_remoteproc_device(_rproc_name_is_unique, + check_dev, check_name); + return ret ? false : true; +} + +/** + * rproc_pre_probe() - Pre probe accessor for the uclass + * @dev: device for which we are preprobing + * + * Parses and fills up the uclass pdata for use as needed by core and + * remote proc drivers. + * + * Return: 0 if all wernt ok, else appropriate error value. + */ +static int rproc_pre_probe(struct udevice *dev) +{ + struct dm_rproc_uclass_pdata *uc_pdata; + const struct dm_rproc_ops *ops; + + uc_pdata = dev_get_uclass_platdata(dev); + + /* See if we need to populate via fdt */ + + if (!dev->platdata) { +#if CONFIG_IS_ENABLED(OF_CONTROL) + int node = dev->of_offset; + const void *blob = gd->fdt_blob; + bool tmp; + if (!blob) { + debug("'%s' no dt?\n", dev->name); + return -EINVAL; + } + debug("'%s': using fdt\n", dev->name); + uc_pdata->name = fdt_getprop(blob, node, + "remoteproc-name", NULL); + + /* Default is internal memory mapped */ + uc_pdata->mem_type = RPROC_INTERNAL_MEMORY_MAPPED; + tmp = fdtdec_get_bool(blob, node, + "remoteproc-internal-memory-mapped"); + if (tmp) + uc_pdata->mem_type = RPROC_INTERNAL_MEMORY_MAPPED; +#else + /* Nothing much we can do about this, can we? */ + return -EINVAL; +#endif + + } else { + struct dm_rproc_uclass_pdata *pdata = dev->platdata; + + debug("'%s': using legacy data\n", dev->name); + if (pdata->name) + uc_pdata->name = pdata->name; + uc_pdata->mem_type = pdata->mem_type; + uc_pdata->driver_plat_data = pdata->driver_plat_data; + } + + /* Else try using device Name */ + if (!uc_pdata->name) + uc_pdata->name = dev->name; + if (!uc_pdata->name) { + debug("Unnamed device!"); + return -EINVAL; + } + + if (!rproc_name_is_unique(dev, uc_pdata->name)) { + debug("%s duplicate name '%s'\n", dev->name, uc_pdata->name); + return -EINVAL; + } + + ops = rproc_get_ops(dev); + if (!ops) { + debug("%s driver has no ops?\n", dev->name); + return -EINVAL; + } + + if (!ops->load || !ops->start) { + debug("%s driver has missing mandatory ops?\n", dev->name); + return -EINVAL; + } + + return 0; +} + +/** + * rproc_post_probe() - post probe accessor for the uclass + * @dev: deivce we finished probing + * + * initiate init function after the probe is completed. This allows + * the remote processor drivers to split up the initializations between + * probe and init as needed. + * + * Return: if the remote proc driver has a init routine, invokes it and + * hands over the return value. overall, 0 if all went well, else appropriate + * error value. + */ +static int rproc_post_probe(struct udevice *dev) +{ + const struct dm_rproc_ops *ops; + + ops = rproc_get_ops(dev); + if (!ops) { + debug("%s driver has no ops?\n", dev->name); + return -EINVAL; + } + + if (ops->init) + return ops->init(dev); + + return 0; +} + +UCLASS_DRIVER(rproc) = { + .id = UCLASS_REMOTEPROC, + .name = "remoteproc", + .flags = DM_UC_FLAG_SEQ_ALIAS, + .pre_probe = rproc_pre_probe, + .post_probe = rproc_post_probe, + .per_device_platdata_auto_alloc_size = + sizeof(struct dm_rproc_uclass_pdata), +}; + +/* Remoteproc subsystem access functions */ +/** + * _rproc_probe_dev() - iteration helper to probe a rproc device + * @dev: device to probe + * @uc_pdata: uclass data allocated for the device + * @data: unused + * + * Return: 0 if all ok, else appropriate error value. + */ +static int _rproc_probe_dev(struct udevice *dev, + struct dm_rproc_uclass_pdata *uc_pdata, + const void *data) +{ + int ret; + + ret = device_probe(dev); + + if (ret) + debug("%s: Failed to initialize - %d\n", dev->name, ret); + return ret; +} + +/** + * _rproc_dev_is_probed() - check if the device has been probed + * @dev: device to check + * @uc_pdata: unused + * @data: unused + * + * Return: -EAGAIN if not probed else return 0 + */ +static int _rproc_dev_is_probed(struct udevice *dev, + struct dm_rproc_uclass_pdata *uc_pdata, + const void *data) +{ + if (dev->flags & DM_FLAG_ACTIVATED) + return 0; + + return -EAGAIN; +} + +bool rproc_is_initialized(void) +{ + int ret = for_each_remoteproc_device(_rproc_dev_is_probed, NULL, NULL); + return ret ? false : true; +} + +int rproc_init(void) +{ + int ret; + + if (rproc_is_initialized()) { + debug("Already initialized\n"); + return -EINVAL; + } + + ret = for_each_remoteproc_device(_rproc_probe_dev, NULL, NULL); + return ret; +} + +int rproc_load(int id, ulong addr, ulong size) +{ + struct udevice *dev = NULL; + struct dm_rproc_uclass_pdata *uc_pdata; + const struct dm_rproc_ops *ops; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_REMOTEPROC, id, &dev); + if (ret) { + debug("Unknown remote processor id '%d' requested(%d)\n", + id, ret); + return ret; + } + + uc_pdata = dev_get_uclass_platdata(dev); + + ops = rproc_get_ops(dev); + if (!ops) { + debug("%s driver has no ops?\n", dev->name); + return -EINVAL; + } + + debug("Loading to '%s' from address 0x%08lX size of %lu bytes\n", + uc_pdata->name, addr, size); + if (ops->load) + return ops->load(dev, addr, size); + + debug("%s: data corruption?? mandatory function is missing!\n", + dev->name); + + return -EINVAL; +}; + +/* + * Completely internal helper enums.. + * Keeping this isolated helps this code evolve independent of other + * parts.. + */ +enum rproc_ops { + RPROC_START, + RPROC_STOP, + RPROC_RESET, + RPROC_PING, + RPROC_RUNNING, +}; + +/** + * _rproc_ops_wrapper() - wrapper for invoking remote proc driver callback + * @id: id of the remote processor + * @op: one of rproc_ops that indicate what operation to invoke + * + * Most of the checks and verification for remoteproc operations are more + * or less same for almost all operations. This allows us to put a wrapper + * and use the common checks to allow the driver to function appropriately. + * + * Return: 0 if all ok, else appropriate error value. + */ +static int _rproc_ops_wrapper(int id, enum rproc_ops op) +{ + struct udevice *dev = NULL; + struct dm_rproc_uclass_pdata *uc_pdata; + const struct dm_rproc_ops *ops; + int (*fn)(struct udevice *dev); + bool mandatory = false; + char *op_str; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_REMOTEPROC, id, &dev); + if (ret) { + debug("Unknown remote processor id '%d' requested(%d)\n", + id, ret); + return ret; + } + + uc_pdata = dev_get_uclass_platdata(dev); + + ops = rproc_get_ops(dev); + if (!ops) { + debug("%s driver has no ops?\n", dev->name); + return -EINVAL; + } + switch (op) { + case RPROC_START: + fn = ops->start; + mandatory = true; + op_str = "Starting"; + break; + case RPROC_STOP: + fn = ops->stop; + op_str = "Stopping"; + break; + case RPROC_RESET: + fn = ops->reset; + op_str = "Resetting"; + break; + case RPROC_RUNNING: + fn = ops->is_running; + op_str = "Checking if running:"; + break; + case RPROC_PING: + fn = ops->ping; + op_str = "Pinging"; + break; + default: + debug("what is '%d' operation??\n", op); + return -EINVAL; + } + + debug("%s %s...\n", op_str, uc_pdata->name); + if (fn) + return fn(dev); + + if (mandatory) + debug("%s: data corruption?? mandatory function is missing!\n", + dev->name); + + return -ENOSYS; +} + +int rproc_start(int id) +{ + return _rproc_ops_wrapper(id, RPROC_START); +}; + +int rproc_stop(int id) +{ + return _rproc_ops_wrapper(id, RPROC_STOP); +}; + +int rproc_reset(int id) +{ + return _rproc_ops_wrapper(id, RPROC_RESET); +}; + +int rproc_ping(int id) +{ + return _rproc_ops_wrapper(id, RPROC_PING); +}; + +int rproc_is_running(int id) +{ + return _rproc_ops_wrapper(id, RPROC_RUNNING); +}; diff --git a/drivers/remoteproc/sandbox_testproc.c b/drivers/remoteproc/sandbox_testproc.c new file mode 100644 index 0000000..004c779 --- /dev/null +++ b/drivers/remoteproc/sandbox_testproc.c @@ -0,0 +1,336 @@ +/* + * (C) Copyright 2015 + * Texas Instruments Incorporated - http://www.ti.com/ + * SPDX-License-Identifier: GPL-2.0+ + */ +#define pr_fmt(fmt) "%s: " fmt, __func__ +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <remoteproc.h> + +/** + * enum sandbox_state - different device states + * @sb_booted: Entry condition, just booted + * @sb_init: Initialized (basic environment is ready) + * @sb_reset: Held in reset (accessible, but not running) + * @sb_loaded: Loaded with image (but not running) + * @sb_running: Processor is running + */ +enum sandbox_state { + sb_booted, + sb_init, + sb_reset, + sb_loaded, + sb_running +}; + +/** + * struct sandbox_test_devdata - private data per device + * @current_state: device current state + */ +struct sandbox_test_devdata { + enum sandbox_state current_state; +}; + +/** + * sandbox_dev_move_to_state() - statemachine for our dummy device + * @dev: device to switch state + * @next_state: next proposed state + * + * This tries to follow the following statemachine: + * Entry + * | + * v + * +-------+ + * +---+ init | + * | | | <---------------------+ + * | +-------+ | + * | | + * | | + * | +--------+ | + * Load| | reset | | + * | | | <----------+ | + * | +--------+ | | + * | |Load | | + * | | | | + * | +----v----+ reset | | + * +-> | | (opt) | | + * | Loaded +-----------+ | + * | | | + * +----+----+ | + * | Start | + * +---v-----+ (opt) | + * +->| Running | Stop | + * Ping +- | +--------------------+ + * (opt) +---------+ + * + * (is_running does not change state) + * + * Return: 0 when valid state transition is seen, else returns -EINVAL + */ +static int sandbox_dev_move_to_state(struct udevice *dev, + enum sandbox_state next_state) +{ + struct sandbox_test_devdata *ddata = dev_get_priv(dev); + + /* No state transition is OK */ + if (ddata->current_state == next_state) + return 0; + + debug("current_state=%d, next_state=%d\n", ddata->current_state, + next_state); + switch (ddata->current_state) { + case sb_booted: + if (next_state == sb_init) + goto ok_state; + break; + + case sb_init: + if (next_state == sb_reset || next_state == sb_loaded) + goto ok_state; + break; + + case sb_reset: + if (next_state == sb_loaded || next_state == sb_init) + goto ok_state; + break; + + case sb_loaded: + if (next_state == sb_reset || next_state == sb_init || + next_state == sb_running) + goto ok_state; + break; + + case sb_running: + if (next_state == sb_reset || next_state == sb_init) + goto ok_state; + break; + }; + return -EINVAL; + +ok_state: + ddata->current_state = next_state; + return 0; +} + +/** + * sandbox_testproc_probe() - basic probe function + * @dev: test proc device that is being probed. + * + * Return: 0 if all went ok, else return appropriate error + */ +static int sandbox_testproc_probe(struct udevice *dev) +{ + struct dm_rproc_uclass_pdata *uc_pdata; + struct sandbox_test_devdata *ddata; + int ret; + + uc_pdata = dev_get_uclass_platdata(dev); + ddata = dev_get_priv(dev); + if (!ddata) { + debug("%s: platform private data missing\n", uc_pdata->name); + return -EINVAL; + } + ret = sandbox_dev_move_to_state(dev, sb_booted); + debug("%s: called(%d)\n", uc_pdata->name, ret); + + return ret; +} + +/** + * sandbox_testproc_init() - Simple initialization function + * @dev: device to operate upon + * + * Return: 0 if all went ok, else return appropriate error + */ +static int sandbox_testproc_init(struct udevice *dev) +{ + struct dm_rproc_uclass_pdata *uc_pdata; + int ret; + + uc_pdata = dev_get_uclass_platdata(dev); + + ret = sandbox_dev_move_to_state(dev, sb_init); + + debug("%s: called(%d)\n", uc_pdata->name, ret); + if (ret) + debug("%s init failed\n", uc_pdata->name); + + return ret; +} + +/** + * sandbox_testproc_reset() - Reset the remote processor + * @dev: device to operate upon + * + * Return: 0 if all went ok, else return appropriate error + */ +static int sandbox_testproc_reset(struct udevice *dev) +{ + struct dm_rproc_uclass_pdata *uc_pdata; + int ret; + + uc_pdata = dev_get_uclass_platdata(dev); + + ret = sandbox_dev_move_to_state(dev, sb_reset); + + debug("%s: called(%d)\n", uc_pdata->name, ret); + + if (ret) + debug("%s reset failed\n", uc_pdata->name); + return ret; +} + +/** + * sandbox_testproc_load() - (replace: short desc) + * @dev: device to operate upon + * @addr: Address of the binary image to load + * @size: Size (in bytes) of the binary image to load + * + * Return: 0 if all went ok, else return appropriate error + */ +static int sandbox_testproc_load(struct udevice *dev, ulong addr, ulong size) +{ + struct dm_rproc_uclass_pdata *uc_pdata; + int ret; + + uc_pdata = dev_get_uclass_platdata(dev); + + ret = sandbox_dev_move_to_state(dev, sb_loaded); + + debug("%s: called(%d) Loading to %08lX %lu size\n", + uc_pdata->name, ret, addr, size); + + if (ret) + debug("%s load failed\n", uc_pdata->name); + return ret; +} + +/** + * sandbox_testproc_start() - Start the remote processor + * @dev: device to operate upon + * + * Return: 0 if all went ok, else return appropriate error + */ +static int sandbox_testproc_start(struct udevice *dev) +{ + struct dm_rproc_uclass_pdata *uc_pdata; + int ret; + + uc_pdata = dev_get_uclass_platdata(dev); + + ret = sandbox_dev_move_to_state(dev, sb_running); + + debug("%s: called(%d)\n", uc_pdata->name, ret); + + if (ret) + debug("%s start failed\n", uc_pdata->name); + return ret; +} + +/** + * sandbox_testproc_stop() - Stop the remote processor + * @dev: device to operate upon + * + * Return: 0 if all went ok, else return appropriate error + */ +static int sandbox_testproc_stop(struct udevice *dev) +{ + struct dm_rproc_uclass_pdata *uc_pdata; + int ret; + + uc_pdata = dev_get_uclass_platdata(dev); + + ret = sandbox_dev_move_to_state(dev, sb_init); + + debug("%s: called(%d)\n", uc_pdata->name, ret); + + if (ret) + debug("%s stop failed\n", uc_pdata->name); + return ret; +} + +/** + * sandbox_testproc_is_running() - Check if remote processor is running + * @dev: device to operate upon + * + * Return: 0 if running, 1 if not running + */ +static int sandbox_testproc_is_running(struct udevice *dev) +{ + struct dm_rproc_uclass_pdata *uc_pdata; + struct sandbox_test_devdata *ddata; + int ret = 1; + + uc_pdata = dev_get_uclass_platdata(dev); + ddata = dev_get_priv(dev); + + if (ddata->current_state == sb_running) + ret = 0; + debug("%s: called(%d)\n", uc_pdata->name, ret); + + return ret; +} + +/** + * sandbox_testproc_ping() - Try pinging remote processor + * @dev: device to operate upon + * + * Return: 0 if running, -EINVAL if not running + */ +static int sandbox_testproc_ping(struct udevice *dev) +{ + struct dm_rproc_uclass_pdata *uc_pdata; + struct sandbox_test_devdata *ddata; + int ret; + + uc_pdata = dev_get_uclass_platdata(dev); + ddata = dev_get_priv(dev); + + if (ddata->current_state == sb_running) + ret = 0; + else + ret = -EINVAL; + + debug("%s: called(%d)\n", uc_pdata->name, ret); + if (ret) + debug("%s: No response.(Not started?)\n", uc_pdata->name); + + return ret; +} + +static const struct dm_rproc_ops sandbox_testproc_ops = { + .init = sandbox_testproc_init, + .reset = sandbox_testproc_reset, + .load = sandbox_testproc_load, + .start = sandbox_testproc_start, + .stop = sandbox_testproc_stop, + .is_running = sandbox_testproc_is_running, + .ping = sandbox_testproc_ping, +}; + +static const struct udevice_id sandbox_ids[] = { + {.compatible = "sandbox,test-processor"}, + {} +}; + +U_BOOT_DRIVER(sandbox_testproc) = { + .name = "sandbox_test_proc", + .of_match = sandbox_ids, + .id = UCLASS_REMOTEPROC, + .ops = &sandbox_testproc_ops, + .probe = sandbox_testproc_probe, + .priv_auto_alloc_size = sizeof(struct sandbox_test_devdata), +}; + +/* TODO(nm@ti.com): Remove this along with non-DT support */ +static struct dm_rproc_uclass_pdata proc_3_test = { + .name = "proc_3_legacy", + .mem_type = RPROC_INTERNAL_MEMORY_MAPPED, +}; + +U_BOOT_DEVICE(proc_3_demo) = { + .name = "sandbox_test_proc", + .platdata = &proc_3_test, +}; diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index 363ade3..da804d5 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -192,7 +192,7 @@ static void mc146818_init(void) /* Clear any pending interrupts */ mc146818_read8(RTC_CONFIG_C); } -#endif +#endif /* CONFIG_CMD_DATE */ #ifdef CONFIG_DM_RTC @@ -225,7 +225,7 @@ static int rtc_mc146818_write8(struct udevice *dev, unsigned int reg, int val) return 0; } -static int rtc_mc146818_bind(struct udevice *dev) +static int rtc_mc146818_probe(struct udevice *dev) { mc146818_init(); @@ -249,7 +249,7 @@ U_BOOT_DRIVER(rtc_mc146818) = { .name = "rtc_mc146818", .id = UCLASS_RTC, .of_match = rtc_mc146818_ids, - .bind = rtc_mc146818_bind, + .probe = rtc_mc146818_probe, .ops = &rtc_mc146818_ops, }; diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c index fe74c69..300e9b3 100644 --- a/drivers/rtc/rtc-uclass.c +++ b/drivers/rtc/rtc-uclass.c @@ -68,7 +68,7 @@ int rtc_read32(struct udevice *dev, unsigned int reg, u32 *valuep) for (i = 0; i < sizeof(value); i++) { ret = rtc_read8(dev, reg + i); - if (ret) + if (ret < 0) return ret; value |= ret << (i << 3); } diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ddb725d..ac5920a 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -109,6 +109,27 @@ config DEBUG_UART_SHIFT value. Use this value to specify the shift to use, where 0=byte registers, 2=32-bit word registers, etc. +config DEBUG_UART_BOARD_INIT + bool "Enable board-specific debug UART init" + depends on DEBUG_UART + help + Some boards need to set things up before the debug UART can be used. + On these boards a call to debug_uart_init() is insufficient. When + this option is enabled, the function board_debug_uart_init() will + be called when debug_uart_init() is called. You can put any code + here that is needed to set up the UART ready for use, such as set + pin multiplexing or enable clocks. + +config DEBUG_UART_ANNOUNCE + bool "Show a message when the debug UART starts up" + depends on DEBUG_UART + help + Enable this option to show a message when the debug UART is ready + for use. You will see a message like "<debug_uart> " as soon as + U-Boot has the UART ready for use (i.e. your code calls + debug_uart_init()). This can be useful just as a check that + everything is working. + config ROCKCHIP_SERIAL bool "Rockchip on-chip UART support" depends on ARCH_ROCKCHIP && DM_SERIAL diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 6275a11..6433844 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -257,7 +257,7 @@ int NS16550_tstc(NS16550_t com_port) (1 << CONFIG_DEBUG_UART_SHIFT), \ CONFIG_DEBUG_UART_SHIFT) -void debug_uart_init(void) +static inline void _debug_uart_init(void) { struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; int baud_divisor; diff --git a/drivers/serial/serial_efi.c b/drivers/serial/serial_efi.c index cf57d89..ea25c25 100644 --- a/drivers/serial/serial_efi.c +++ b/drivers/serial/serial_efi.c @@ -107,7 +107,7 @@ static int serial_efi_pending(struct udevice *dev, bool input) * There is nothing to init here since the EFI console is already running by * the time we enter U-Boot. */ -void debug_uart_init(void) +static inline void _debug_uart_init(void) { } diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c index e8d544f..891cd7b 100644 --- a/drivers/serial/serial_omap.c +++ b/drivers/serial/serial_omap.c @@ -12,10 +12,16 @@ DECLARE_GLOBAL_DATA_PTR; +#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */ + #if CONFIG_IS_ENABLED(OF_CONTROL) static const struct udevice_id omap_serial_ids[] = { + { .compatible = "ti,omap2-uart" }, { .compatible = "ti,omap3-uart" }, { .compatible = "ti,omap4-uart" }, + { .compatible = "ti,am3352-uart" }, + { .compatible = "ti,am4372-uart" }, + { .compatible = "ti,dra742-uart" }, { } }; @@ -28,7 +34,7 @@ static int omap_serial_ofdata_to_platdata(struct udevice *dev) if (ret) return ret; plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, - "clock-frequency", -1); + "clock-frequency", DEFAULT_CLK_SPEED); plat->reg_shift = 2; return 0; diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 3f0b588..feba467 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -207,7 +207,7 @@ U_BOOT_DRIVER(serial_s5p) = { #include <debug_uart.h> -void debug_uart_init(void) +static inline void _debug_uart_init(void) { struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE; diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 2e388e7..be4c0a3 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -133,7 +133,8 @@ static int get_ich_version(uint16_t device_id) (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) || device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC || - device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC) + device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC || + device_id == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LPC) return 9; return 0; diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index ca01a01..ece48e6 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -554,7 +554,7 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req) static void cb_oem(struct usb_ep *ep, struct usb_request *req) { char *cmd = req->buf; -#ifdef CONFIG_FASTBOOT_FLASH +#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV if (strncmp("format", cmd + 4, 6) == 0) { char cmdbuf[32]; sprintf(cmdbuf, "gpt write mmc %x $partitions", diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index b30b43d..2a2bffe 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -52,6 +52,13 @@ config USB_EHCI if USB_EHCI_HCD +config USB_EHCI_MARVELL + bool "Support for MVEBU (AXP / A38x) on-chip EHCI USB controller" + depends on ARCH_MVEBU + default y + ---help--- + Enables support for the on-chip EHCI controller on MVEBU SoCs. + config USB_EHCI_MX6 bool "Support for i.MX6 on-chip EHCI USB controller" depends on ARCH_MX6 diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 50fa01c..5b0f46a 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -12,6 +12,7 @@ #include "ehci.h" #include <linux/mbus.h> #include <asm/arch/cpu.h> +#include <dm.h> #if defined(CONFIG_KIRKWOOD) #include <asm/arch/soc.h> @@ -28,24 +29,19 @@ DECLARE_GLOBAL_DATA_PTR; /* * USB 2.0 Bridge Address Decoding registers setup */ -#ifdef CONFIG_ARMADA_XP +#ifdef CONFIG_DM_USB -/* - * Armada XP and Armada 38x have different base addresses for - * the USB 2.0 EHCI host controller. So we need to provide - * a mechnism to support both here. - */ -#define MVUSB0_BASE \ - (mvebu_soc_family() == MVEBU_SOC_A38X ? \ - MVEBU_USB20_BASE : MVEBU_AXP_USB_BASE) -#define MVUSB_BASE(port) MVUSB0_BASE + ((port) << 12) +struct ehci_mvebu_priv { + struct ehci_ctrl ehci; + fdt_addr_t hcd_base; +}; /* * Once all the older Marvell SoC's (Orion, Kirkwood) are converted * to the common mvebu archticture including the mbus setup, this * will be the only function needed to configure the access windows */ -static void usb_brg_adrdec_setup(int index) +static void usb_brg_adrdec_setup(u32 base) { const struct mbus_dram_target_info *dram; int i; @@ -53,8 +49,8 @@ static void usb_brg_adrdec_setup(int index) dram = mvebu_mbus_dram_info(); for (i = 0; i < 4; i++) { - writel(0, MVUSB_BASE(index) + USB_WINDOW_CTRL(i)); - writel(0, MVUSB_BASE(index) + USB_WINDOW_BASE(i)); + writel(0, base + USB_WINDOW_CTRL(i)); + writel(0, base + USB_WINDOW_BASE(i)); } for (i = 0; i < dram->num_cs; i++) { @@ -63,12 +59,69 @@ static void usb_brg_adrdec_setup(int index) /* Write size, attributes and target id to control register */ writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | (dram->mbus_dram_target_id << 4) | 1, - MVUSB_BASE(index) + USB_WINDOW_CTRL(i)); + base + USB_WINDOW_CTRL(i)); /* Write base address to base register */ - writel(cs->base, MVUSB_BASE(index) + USB_WINDOW_BASE(i)); + writel(cs->base, base + USB_WINDOW_BASE(i)); } } + +static int ehci_mvebu_probe(struct udevice *dev) +{ + struct ehci_mvebu_priv *priv = dev_get_priv(dev); + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; + + /* + * Get the base address for EHCI controller from the device node + */ + priv->hcd_base = dev_get_addr(dev); + if (priv->hcd_base == FDT_ADDR_T_NONE) { + debug("Can't get the EHCI register base address\n"); + return -ENXIO; + } + + usb_brg_adrdec_setup(priv->hcd_base); + + hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100); + hcor = (struct ehci_hcor *) + ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n", + (u32)hccr, (u32)hcor, + (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); +} + +static int ehci_mvebu_remove(struct udevice *dev) +{ + int ret; + + ret = ehci_deregister(dev); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id ehci_usb_ids[] = { + { .compatible = "marvell,orion-ehci", }, + { } +}; + +U_BOOT_DRIVER(ehci_mvebu) = { + .name = "ehci_mvebu", + .id = UCLASS_USB, + .of_match = ehci_usb_ids, + .probe = ehci_mvebu_probe, + .remove = ehci_mvebu_remove, + .ops = &ehci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct ehci_mvebu_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + #else #define MVUSB_BASE(port) MVUSB0_BASE @@ -112,7 +165,6 @@ static void usb_brg_adrdec_setup(int index) writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i)); } } -#endif /* * Create the appropriate control structures to manage @@ -142,3 +194,5 @@ int ehci_hcd_stop(int index) { return 0; } + +#endif /* CONFIG_DM_USB */ diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index fc1aea3..9fee66a 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -15,7 +15,7 @@ #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/io.h> -#include <axp221.h> +#include <axp_pmic.h> #include <errno.h> #include <fdtdec.h> #include <fdt_support.h> @@ -1217,10 +1217,10 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode, if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) { /* * The anx9804 needs 1.8V from eldo3, we do this here - * and not via CONFIG_AXP221_ELDO3 from board_init() + * and not via CONFIG_AXP_ELDO3_VOLT from board_init() * to avoid turning this on when using hdmi output. */ - axp221_set_eldo(3, 1800); + axp_set_eldo(3, 1800); anx9804_init(CONFIG_VIDEO_LCD_I2C_BUS, 4, ANX9804_DATA_RATE_1620M, sunxi_display.depth); diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c index 4e6d070..a19651f 100644 --- a/drivers/video/vesa_fb.c +++ b/drivers/video/vesa_fb.c @@ -34,7 +34,7 @@ void *video_hw_init(void) } if (vbe_get_video_info(gdev)) { dev = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0); - if (dev == -1) { + if (dev < 0) { printf("no card detected\n"); return NULL; } diff --git a/include/_exports.h b/include/_exports.h index 74a882a..11beeb2 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -23,7 +23,7 @@ EXPORT_FUNC(dummy, void, free_hdlr, void) #endif EXPORT_FUNC(malloc, void *, malloc, size_t) -#ifndef CONFIG_SYS_MALLOC_SIMPLE +#if !CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) EXPORT_FUNC(free, void, free, void *) #endif EXPORT_FUNC(udelay, void, udelay, unsigned long) diff --git a/include/asm-generic/bitsperlong.h b/include/asm-generic/bitsperlong.h new file mode 100644 index 0000000..75ee21e --- /dev/null +++ b/include/asm-generic/bitsperlong.h @@ -0,0 +1,8 @@ +#ifndef __ASM_GENERIC_BITS_PER_LONG +#define __ASM_GENERIC_BITS_PER_LONG + +#ifndef BITS_PER_LONG_LONG +#define BITS_PER_LONG_LONG 64 +#endif + +#endif /* __ASM_GENERIC_BITS_PER_LONG */ diff --git a/include/axp152.h b/include/axp152.h index c3aef77..1643266 100644 --- a/include/axp152.h +++ b/include/axp152.h @@ -25,9 +25,3 @@ enum axp152_reg { #define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ #define AXP_GPIO_STATE 0x97 #define AXP_GPIO_STATE_OFFSET 0 - -int axp152_set_dcdc2(int mvolt); -int axp152_set_dcdc3(int mvolt); -int axp152_set_dcdc4(int mvolt); -int axp152_set_ldo2(int mvolt); -int axp152_init(void); diff --git a/include/axp209.h b/include/axp209.h index 6170202..e1b22e3 100644 --- a/include/axp209.h +++ b/include/axp209.h @@ -7,6 +7,7 @@ enum axp209_reg { AXP209_POWER_STATUS = 0x00, AXP209_CHIP_VERSION = 0x03, + AXP209_OUTPUT_CTRL = 0x12, AXP209_DCDC2_VOLTAGE = 0x23, AXP209_DCDC3_VOLTAGE = 0x27, AXP209_LDO24_VOLTAGE = 0x28, @@ -23,6 +24,13 @@ enum axp209_reg { #define AXP209_POWER_STATUS_ON_BY_DC (1 << 0) #define AXP209_POWER_STATUS_VBUS_USABLE (1 << 4) +#define AXP209_OUTPUT_CTRL_EXTEN (1 << 0) +#define AXP209_OUTPUT_CTRL_DCDC3 (1 << 1) +#define AXP209_OUTPUT_CTRL_LDO2 (1 << 2) +#define AXP209_OUTPUT_CTRL_LDO4 (1 << 3) +#define AXP209_OUTPUT_CTRL_DCDC2 (1 << 4) +#define AXP209_OUTPUT_CTRL_LDO3 (1 << 6) + #define AXP209_IRQ5_PEK_UP (1 << 6) #define AXP209_IRQ5_PEK_DOWN (1 << 5) @@ -39,12 +47,3 @@ enum axp209_reg { #define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ #define AXP_GPIO_STATE 0x94 #define AXP_GPIO_STATE_OFFSET 4 - -extern int axp209_set_dcdc2(int mvolt); -extern int axp209_set_dcdc3(int mvolt); -extern int axp209_set_ldo2(int mvolt); -extern int axp209_set_ldo3(int mvolt); -extern int axp209_set_ldo4(int mvolt); -extern int axp209_init(void); -extern int axp209_poweron_by_dc(void); -extern int axp209_power_button(void); diff --git a/include/axp221.h b/include/axp221.h index 9c87162..0ee21b6 100644 --- a/include/axp221.h +++ b/include/axp221.h @@ -62,19 +62,3 @@ #define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ #define AXP_GPIO_STATE 0x94 #define AXP_GPIO_STATE_OFFSET 0 - -int axp221_set_dcdc1(unsigned int mvolt); -int axp221_set_dcdc2(unsigned int mvolt); -int axp221_set_dcdc3(unsigned int mvolt); -int axp221_set_dcdc4(unsigned int mvolt); -int axp221_set_dcdc5(unsigned int mvolt); -int axp221_set_dldo1(unsigned int mvolt); -int axp221_set_dldo2(unsigned int mvolt); -int axp221_set_dldo3(unsigned int mvolt); -int axp221_set_dldo4(unsigned int mvolt); -int axp221_set_aldo1(unsigned int mvolt); -int axp221_set_aldo2(unsigned int mvolt); -int axp221_set_aldo3(unsigned int mvolt); -int axp221_set_eldo(int eldo_num, unsigned int mvolt); -int axp221_init(void); -int axp221_get_sid(unsigned int *sid); diff --git a/include/axp_pmic.h b/include/axp_pmic.h new file mode 100644 index 0000000..ef339c4 --- /dev/null +++ b/include/axp_pmic.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * + * X-Powers AX Power Management IC support header + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _AXP_PMIC_H_ + +#ifdef CONFIG_AXP152_POWER +#include <axp152.h> +#endif +#ifdef CONFIG_AXP209_POWER +#include <axp209.h> +#endif +#ifdef CONFIG_AXP221_POWER +#include <axp221.h> +#endif + +int axp_set_dcdc1(unsigned int mvolt); +int axp_set_dcdc2(unsigned int mvolt); +int axp_set_dcdc3(unsigned int mvolt); +int axp_set_dcdc4(unsigned int mvolt); +int axp_set_dcdc5(unsigned int mvolt); +int axp_set_aldo1(unsigned int mvolt); +int axp_set_aldo2(unsigned int mvolt); +int axp_set_aldo3(unsigned int mvolt); +int axp_set_aldo4(unsigned int mvolt); +int axp_set_dldo1(unsigned int mvolt); +int axp_set_dldo2(unsigned int mvolt); +int axp_set_dldo3(unsigned int mvolt); +int axp_set_dldo4(unsigned int mvolt); +int axp_set_eldo(int eldo_num, unsigned int mvolt); +int axp_init(void); +int axp_get_sid(unsigned int *sid); + +#endif diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index 4c46dda..8832552 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -29,7 +29,6 @@ #define CONFIG_CMD_DOC /* Disk-On-Chip Support */ #define CONFIG_CMD_DTT /* Digital Therm and Thermostat */ #define CONFIG_CMD_EEPROM /* EEPROM read/write support */ -#define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */ #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_FDC /* Floppy Disk Support */ diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 3a360ca4..d2f49a1 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -191,11 +191,12 @@ BOOTENV_BOOT_TARGETS \ \ "boot_extlinux=" \ - "sysboot ${devtype} ${devnum}:${bootpart} any " \ + "sysboot ${devtype} ${devnum}:${distro_bootpart} any " \ "${scriptaddr} ${prefix}extlinux/extlinux.conf\0" \ \ "scan_dev_for_extlinux=" \ - "if test -e ${devtype} ${devnum}:${bootpart} " \ + "if test -e ${devtype} " \ + "${devnum}:${distro_bootpart} " \ "${prefix}extlinux/extlinux.conf; then " \ "echo Found ${prefix}extlinux/extlinux.conf; " \ "run boot_extlinux; " \ @@ -203,13 +204,14 @@ "fi\0" \ \ "boot_a_script=" \ - "load ${devtype} ${devnum}:${bootpart} " \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ "${scriptaddr} ${prefix}${script}; " \ "source ${scriptaddr}\0" \ \ "scan_dev_for_scripts=" \ "for script in ${boot_scripts}; do " \ - "if test -e ${devtype} ${devnum}:${bootpart} " \ + "if test -e ${devtype} " \ + "${devnum}:${distro_bootpart} " \ "${prefix}${script}; then " \ "echo Found U-Boot script " \ "${prefix}${script}; " \ @@ -219,7 +221,8 @@ "done\0" \ \ "scan_dev_for_boot=" \ - "echo Scanning ${devtype} ${devnum}:${bootpart}...; " \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ "for prefix in ${boot_prefixes}; do " \ "run scan_dev_for_extlinux; " \ "run scan_dev_for_scripts; " \ @@ -228,8 +231,9 @@ "scan_dev_for_boot_part=" \ "part list ${devtype} ${devnum} -bootable devplist; " \ "env exists devplist || setenv devplist 1; " \ - "for bootpart in ${devplist}; do " \ - "if fstype ${devtype} ${devnum}:${bootpart} " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ "bootfstype; then " \ "run scan_dev_for_boot; " \ "fi; " \ diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h index d8165cc..9d1de55 100644 --- a/include/config_distro_defaults.h +++ b/include/config_distro_defaults.h @@ -49,7 +49,6 @@ #define CONFIG_CMD_BOOTZ #endif #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_EXT4 #define CONFIG_CMD_FAT diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 1e458f4..858e25d 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -756,7 +756,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA #define CONFIG_CMD_GREPENV #define CONFIG_CMD_IRQ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index a7c9277..226a170 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -342,7 +342,6 @@ extern unsigned long get_sdram_size(void); */ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ERRATA -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_IRQ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 804493e..e545447 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -580,7 +580,6 @@ combinations. this should be removed later */ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 6c39b1e..f574994 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -494,7 +494,6 @@ * Command line configuration. */ #define CONFIG_CMD_ERRATA -#define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_MII #define CONFIG_CMD_PING diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 638a586..ce7bc35 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -55,7 +55,6 @@ */ #define CONFIG_CMD_PCI #define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_BSP #define CONFIG_CMD_EEPROM diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 9c25751..2827a04 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -72,7 +72,6 @@ #define CONFIG_CMD_IRQ #define CONFIG_CMD_IDE #define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF #define CONFIG_CMD_DATE #define CONFIG_CMD_I2C #define CONFIG_CMD_MII diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 5e15dd9..b38a349 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -23,7 +23,6 @@ /* Command line configuration */ #define CONFIG_CMD_CACHE -#define CONFIG_CMD_ELF #undef CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index d1cadc0..ffee225 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -39,7 +39,6 @@ /* Command line configuration */ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_REGINFO diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 1472672..2a198e5 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -37,7 +37,6 @@ /* Command line configuration */ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PCI diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 006f2d8..718f31f 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -59,7 +59,6 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_MII #define CONFIG_CMD_PING -#define CONFIG_CMD_ELF #define CONFIG_BOOTDELAY 5 diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 116e8e2..195595f 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -58,7 +58,6 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_PING #define CONFIG_CMD_MII -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_DHCP diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index a48ae6b..42cbb0f 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -29,7 +29,6 @@ /* Command line configuration */ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF #undef CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index e806b7a..b2d544c 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -29,7 +29,6 @@ /* Command line configuration */ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 1df98f7..a906204 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -29,7 +29,6 @@ /* Command line configuration */ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index db0ddcd..927b7da 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -41,7 +41,6 @@ #define CONFIG_CMD_CACHE #undef CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #undef CONFIG_CMD_I2C #undef CONFIG_CMD_JFFS2 #undef CONFIG_CMD_UBI diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index de747a4..61ebb24 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -42,7 +42,6 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #undef CONFIG_CMD_JFFS2 #define CONFIG_CMD_MII diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 06da5f0..f813dab 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -42,7 +42,6 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_I2C diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index e30b645..81ecbc8 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -31,7 +31,6 @@ /* Command line configuration */ #define CONFIG_CMD_CACHE #undef CONFIG_CMD_DATE -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PCI diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 051c940..8621d7a 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -31,7 +31,6 @@ /* Command line configuration */ #define CONFIG_CMD_CACHE #undef CONFIG_CMD_DATE -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PCI diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index cb21b73..0757e67 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -55,7 +55,6 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 1312438..7c51eef 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -638,7 +638,6 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index a42c936..dc6e395 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -353,7 +353,6 @@ */ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C -#define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 8942aae..bf03603 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -372,7 +372,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 67fac70..bef28b3 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -387,7 +387,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 842afe1..2bea604 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -496,7 +496,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 2e8db5a..80b14cb 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -370,7 +370,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index fabe6bf..e1bc8cc 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -389,7 +389,6 @@ */ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C -#define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 7a2131b..064bd85 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -392,7 +392,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 9e38724..0af670b 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -482,7 +482,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index f3334ad..4b5467b 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -597,7 +597,6 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#define CONFIG_CMD_ELF #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 8ac7000..b85e195 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -813,7 +813,6 @@ extern unsigned long get_sdram_size(void); */ #define CONFIG_CMD_DATE #define CONFIG_CMD_ERRATA -#define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_MII #define CONFIG_CMD_PING diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 06b293f..95c81ab 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -678,7 +678,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA #define CONFIG_CMD_IRQ #define CONFIG_CMD_I2C diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 5468495..de205e8 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -618,7 +618,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); * Command line configuration. */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA #define CONFIG_CMD_GREPENV #define CONFIG_CMD_IRQ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index c9d08e6..4601bc8 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -53,7 +53,6 @@ #define CONFIG_CMD_SCSI #define CONFIG_CMD_FAT #define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF #define CONFIG_CMD_USB #define CONFIG_CMD_MII #define CONFIG_CMD_SDRAM diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 3a71ff8..d5d3092 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -66,7 +66,6 @@ #define CONFIG_CMD_IRQ #define CONFIG_CMD_IDE #define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF #define CONFIG_CMD_NAND #define CONFIG_CMD_DATE #define CONFIG_CMD_I2C diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 5712298..2f35ca9 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -59,7 +59,6 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ #define CONFIG_CMD_MII diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 17bd180..fad5744 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -276,7 +276,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_DTT #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_I2C #define CONFIG_CMD_MII diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 92f51f6..c9e5ea9 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -850,7 +850,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA #define CONFIG_CMD_GREPENV #define CONFIG_CMD_IRQ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 324f710..0601d73 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -852,7 +852,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA #define CONFIG_CMD_GREPENV #define CONFIG_CMD_IRQ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 1f46160..4b735b5 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -723,7 +723,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA #define CONFIG_CMD_GREPENV #define CONFIG_CMD_IRQ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 5b61b56..7f8d110 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -787,7 +787,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #define CONFIG_CMD_DATE #endif #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA #define CONFIG_CMD_GREPENV #define CONFIG_CMD_IRQ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 23ca0cf..a804cbe 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -792,7 +792,6 @@ unsigned long get_board_ddr_clk(void); * Command line configuration. */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA #define CONFIG_CMD_GREPENV #define CONFIG_CMD_IRQ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index ef42b88..307a0ea 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -748,7 +748,6 @@ unsigned long get_board_ddr_clk(void); * Command line configuration. */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA #define CONFIG_CMD_MII #define CONFIG_CMD_I2C diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index d43f6b7..754d182 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -318,7 +318,6 @@ * Command line configuration. */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA #define CONFIG_CMD_GREPENV #define CONFIG_CMD_IRQ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 9b9217e..cea3149 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -109,7 +109,6 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 5240e0f..85215b1 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -107,7 +107,6 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index edadf55..97a9fa7 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -97,7 +97,6 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index 166bb2c..636ffc8 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -97,7 +97,6 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 8b16ad2..3c82c73 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -100,7 +100,6 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 8a05fa4..66f9a88 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -129,7 +129,6 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_EEPROM #define CONFIG_CMD_IDE diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index bf3a25b..3e20c71 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -100,7 +100,6 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 47e5c6c..be1cd3a 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -100,7 +100,6 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index fa892a9..f07b903 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -103,7 +103,6 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 13319f2..c887a39 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -103,7 +103,6 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index 0e378f2..a037b4f 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -143,7 +143,6 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 629be99..0801117 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -494,7 +494,6 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ #define CONFIG_CMD_MII diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 5b2e092..bfcfb40 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -55,7 +55,6 @@ #define CONFIG_CMD_USB #define CONFIG_CMD_REGINFO #define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_BSP diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index ddd6377..99ee78b 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -62,7 +62,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_BSP #define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 3cf768e..d58816d 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -18,6 +18,10 @@ #include <configs/ti_am335x_common.h> +/* Don't override the distro default bootdelay */ +#undef CONFIG_BOOTDELAY +#include <config_distro_defaults.h> + #ifndef CONFIG_SPL_BUILD #ifndef CONFIG_FIT # define CONFIG_FIT @@ -67,6 +71,37 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance"; "\ + "setenv bootpart " #instance":2 ; "\ + "run mmcboot\0" + +#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel "=" \ + "run nandboot\0" + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) \ + func(MMC, mmc, 1) \ + func(LEGACY_MMC, legacy_mmc, 1) \ + func(NAND, nand, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run distro_bootcmd" + +#include <config_distro_bootcmd.h> + #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ @@ -160,16 +195,10 @@ "echo WARNING: Could not determine device tree to use; fi; \0" \ NANDARGS \ NETARGS \ - DFUARGS + DFUARGS \ + BOOTENV #endif -#define CONFIG_BOOTCOMMAND \ - "run findfdt; " \ - "run mmcboot;" \ - "setenv mmcdev 1; " \ - "setenv bootpart 1:2; " \ - "run mmcboot;" \ - "run nandboot;" /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ @@ -309,9 +338,12 @@ #endif #ifdef CONFIG_USB_MUSB_GADGET +/* Removing USB gadget and can be enabled adter adding support usb DM */ +#ifndef CONFIG_DM_ETH #define CONFIG_USB_ETHER #define CONFIG_USB_ETH_RNDIS #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" +#endif /* CONFIG_DM_ETH */ /* USB TI's IDs */ #define CONFIG_G_DNL_VENDOR_NUM 0x0451 @@ -319,6 +351,14 @@ #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" #endif /* CONFIG_USB_MUSB_GADGET */ +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_MMC +#endif + #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) /* Remove other SPL modes. */ #undef CONFIG_SPL_YMODEM_SUPPORT diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 67d5c48..d93e3e7 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -23,9 +23,13 @@ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550 +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000 +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#else +#define CONFIG_OMAP_SERIAL +#endif /* I2C Configuration */ #define CONFIG_CMD_EEPROM @@ -136,6 +140,14 @@ #define CONFIG_USB_GADGET_DUALSPEED #endif +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_MMC +#endif + #ifndef CONFIG_SPL_BUILD /* USB Device Firmware Update support */ #define CONFIG_USB_FUNCTION_DFU diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 37dac7d..c5ef650 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -60,7 +60,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_DIAG #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_GREPENV #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h index a342d7e..63f61ae 100644 --- a/include/configs/arcangel4.h +++ b/include/configs/arcangel4.h @@ -41,7 +41,6 @@ /* * Command line configuration */ -#define CONFIG_CMD_ELF #define CONFIG_OF_LIBFDT diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 1c3a1c9..8606151 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -61,7 +61,6 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #if ENABLE_JFFS #define CONFIG_CMD_JFFS2 diff --git a/include/configs/axs101.h b/include/configs/axs101.h index 7cb8853..450291c 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -123,7 +123,6 @@ */ #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_I2C #define CONFIG_CMD_MMC diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h index 6674d28..c57c862 100644 --- a/include/configs/bf537-minotaur.h +++ b/include/configs/bf537-minotaur.h @@ -153,7 +153,6 @@ #define CONFIG_CMD_BOOTLDR #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_SF diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h index 15d912e..90aeeec 100644 --- a/include/configs/bf537-srv1.h +++ b/include/configs/bf537-srv1.h @@ -152,7 +152,6 @@ #define CONFIG_CMD_BOOTLDR #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_SF diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 7b2faf2..a075050 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -80,7 +80,6 @@ # define CONFIG_CMD_BOOTLDR # define CONFIG_CMD_CACHE # define CONFIG_CMD_CPLBINFO -# define CONFIG_CMD_ELF # define CONFIG_CMD_GPIO # define CONFIG_CMD_KGDB # define CONFIG_CMD_LDRINFO diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h index c0197ca..3b7a47f 100644 --- a/include/configs/blackstamp.h +++ b/include/configs/blackstamp.h @@ -117,7 +117,6 @@ #define CONFIG_CMD_CPLBINFO #define CONFIG_CMD_DATE #define CONFIG_CMD_SF -#define CONFIG_CMD_ELF #define CONFIG_BOOTDELAY 5 #define CONFIG_BOOTCOMMAND "run ramboot" diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h index 4752b07..5b15e0e 100644 --- a/include/configs/blackvme.h +++ b/include/configs/blackvme.h @@ -156,7 +156,6 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_CPLBINFO #define CONFIG_CMD_SF -#define CONFIG_CMD_ELF /* * Default: boot from SPI flash. diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 9a1f6d0..c879048 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -388,7 +388,6 @@ #ifndef CONFIG_TRAILBLAZER -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 2919220..878fda2 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -628,7 +628,6 @@ * Command line configuration. */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA #define CONFIG_CMD_GREPENV #define CONFIG_CMD_IRQ diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 3153a74..7f91fff 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -15,6 +15,7 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_ARCH_MISC_INIT #define CONFIG_SMSC_LPC47M diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 1dd4182..74e5b47 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -16,7 +16,9 @@ #define CONFIG_SYS_L2_PL310 +#ifdef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#endif #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO_LATE @@ -48,7 +50,6 @@ #define CONFIG_CMD_SPI #define CONFIG_CMD_TFTPPUT #define CONFIG_CMD_TIME -#define CONFIG_CMD_USB /* I2C */ #define CONFIG_SYS_I2C @@ -91,9 +92,6 @@ #define CONFIG_SUPPORT_VFAT /* USB/EHCI configuration */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI_MARVELL #define CONFIG_EHCI_IS_TDI /* Environment in SPI NOR flash */ diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index f612e72..672518b 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -13,7 +13,9 @@ #define CONFIG_ARMADA_XP /* SOC Family Name */ #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ +#ifdef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#endif #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO_LATE @@ -40,7 +42,6 @@ #define CONFIG_CMD_SPI #define CONFIG_CMD_TFTPPUT #define CONFIG_CMD_TIME -#define CONFIG_CMD_USB /* I2C */ #define CONFIG_SYS_I2C @@ -50,9 +51,6 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* USB/EHCI configuration */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI_MARVELL #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index 46e3a6c..3be44d4 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -75,7 +75,6 @@ * Command line configuration. */ #undef CONFIG_CMD_BEDBUG -#undef CONFIG_CMD_ELF #undef CONFIG_CMD_FAT #undef CONFIG_CMD_MII diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index a7af351..02b8f91 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -107,7 +107,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_DIAG #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_I2C diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index e6bfe58..e39f8ba 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -68,7 +68,6 @@ #undef CONFIG_CMD_DHCP #undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_ELF #undef CONFIG_CMD_I2C #undef CONFIG_CMD_IRQ diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h index 0299d16..3c05534 100644 --- a/include/configs/dlvision.h +++ b/include/configs/dlvision.h @@ -64,7 +64,6 @@ #undef CONFIG_CMD_DHCP #undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_ELF #undef CONFIG_CMD_I2C #undef CONFIG_CMD_IRQ diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index a62f4e3..6ebd703 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -57,8 +57,8 @@ * it has to be rounded to sector size */ #define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x60000 -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ +#define CONFIG_ENV_ADDR 0x80000 +#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ /* * Default environment variables diff --git a/include/configs/io.h b/include/configs/io.h index f5b09b6..7d863fa 100644 --- a/include/configs/io.h +++ b/include/configs/io.h @@ -68,7 +68,6 @@ #undef CONFIG_CMD_DHCP #undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_ELF #undef CONFIG_CMD_I2C #undef CONFIG_CMD_IRQ diff --git a/include/configs/iocon.h b/include/configs/iocon.h index f7ae663..a4d05e5 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -64,7 +64,6 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_FPGAD #undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_ELF #undef CONFIG_CMD_I2C #undef CONFIG_CMD_IRQ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h new file mode 100644 index 0000000..d9ad8cf --- /dev/null +++ b/include/configs/k2g_evm.h @@ -0,0 +1,59 @@ +/* + * Configuration header file for TI's k2g-evm + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_K2G_EVM_H +#define __CONFIG_K2G_EVM_H + +/* Platform type */ +#define CONFIG_SOC_K2G +#define CONFIG_K2G_EVM + +/* U-Boot general configuration */ +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + DEFAULT_MMC_TI_ARGS \ + "console=ttyS0,115200n8\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "addr_mon=0x0c040000\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ + "name_fdt=k2g-evm.dtb\0" \ + "name_mon=skern-k2g.bin\0" \ + "name_ubi=k2g-evm-ubifs.ubi\0" \ + "name_uboot=u-boot-spi-k2g-evm.gph\0" \ + "init_mmc=run args_all args_mmc\0" \ + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0"\ + "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_kern}\0" \ + "get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\ + +#include <configs/ti_armv7_keystone2.h> + +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE 0x0c080000 + +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_2K + +/* Network */ +#define CONFIG_KSNET_NETCP_V1_5 +#define CONFIG_KSNET_CPSW_NUM_PORTS 2 +#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE +#define CONFIG_PHY_MICREL + +/* MMC/SD */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC + +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_CS 0 + +#endif /* __CONFIG_K2G_EVM_H */ diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 15fca1a..5e0f483 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -122,7 +122,6 @@ /* * Commands configuration */ -#define CONFIG_CMD_ELF #define CONFIG_CMD_MTDPARTS /* diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 1837258..a57e328 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -55,7 +55,6 @@ */ #define CONFIG_CMD_BOOTZ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_ENV #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 26136a5..2d93d44 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -415,7 +415,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_DIAG #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ diff --git a/include/configs/malta.h b/include/configs/malta.h index 2f33f63..4d3751a 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -122,7 +122,6 @@ */ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE #define CONFIG_CMD_PCI #define CONFIG_CMD_PING diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 3530a26..3bed9c7 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -11,7 +11,9 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_ARMADA_XP /* SOC Family Name */ +#ifdef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#endif #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO_LATE diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index a8b4b24..84f1a40 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -309,7 +309,6 @@ #undef CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_ELF #define CONFIG_DOS_PARTITION /* diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 3b97d91..6eb6e51 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -41,7 +41,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_DTT #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE diff --git a/include/configs/munices.h b/include/configs/munices.h index b1b6acd..072bd95 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -28,7 +28,6 @@ * Command line configuration. */ #define CONFIG_CMD_ASKENV -#define CONFIG_CMD_ELF #define CONFIG_CMD_IMMAP #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 92e5429..1ecbd35 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -39,11 +39,17 @@ /* * NS16550 Configuration */ +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL) +#define CONFIG_DW_SERIAL +#endif + #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#if !defined(CONFIG_DM_SERIAL) +#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE +#endif /* * Serial Port configuration @@ -128,7 +134,7 @@ /* * Common USB/EHCI configuration */ -#ifdef CONFIG_CMD_USB +#if defined(CONFIG_CMD_USB) && !defined(CONFIG_DM) #define CONFIG_USB_EHCI /* Enable EHCI USB support */ #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION diff --git a/include/configs/neo.h b/include/configs/neo.h index 33cee43..f178366 100644 --- a/include/configs/neo.h +++ b/include/configs/neo.h @@ -67,7 +67,6 @@ #undef CONFIG_CMD_DHCP #undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_ELF #undef CONFIG_CMD_I2C #undef CONFIG_CMD_IRQ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index b113771..9160971 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -330,7 +330,6 @@ #define CONFIG_PCIE_IMX #endif -#define CONFIG_CMD_ELF #define CONFIG_USB_GADGET #define CONFIG_CMD_USB_MASS_STORAGE diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 1afe04a..4c85e85 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -108,11 +108,13 @@ * 2. ROOT: - */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadkernel=fatload mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ + "loadbootscript=load mmc ${mmcbootdev}:${mmcbootpart} ${scriptaddr} " \ + "boot.scr\0" \ + "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ "${kernelname}\0" \ - "loadinitrd=fatload mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ + "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ "${initrdname}\0" \ - "loaddtb=fatload mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \ + "loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \ "${fdtfile}\0" \ "check_ramdisk=" \ "if run loadinitrd; then " \ @@ -129,6 +131,9 @@ "kernel_args=" \ "setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \ " rootwait ${console} ${opts}\0" \ + "boot_script=" \ + "run loadbootscript;" \ + "source ${scriptaddr}\0" \ "boot_fit=" \ "setenv kerneladdr 0x42000000;" \ "setenv kernelname Image.itb;" \ @@ -152,7 +157,9 @@ "run kernel_args;" \ "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ "autoboot=" \ - "if test -e mmc 0 Image.itb; then; " \ + "if test -e mmc 0 boot.scr; then; " \ + "run boot_script; " \ + "elif test -e mmc 0 Image.itb; then; " \ "run boot_fit;" \ "elif test -e mmc 0 zImage; then; " \ "run boot_zimg;" \ @@ -171,6 +178,7 @@ "consoleoff=set console console=ram; save; reset\0" \ "initrdname=uInitrd\0" \ "initrdaddr=42000000\0" \ + "scriptaddr=0x42000000\0" \ "fdtaddr=40800000\0" /* I2C */ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 4409103..cf2bc3e 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -160,12 +160,20 @@ #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } #define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_BCH + #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 /* NAND: SPL falcon mode configs */ #ifdef CONFIG_SPL_OS_BOOT diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h index 23929c2..d53e419 100644 --- a/include/configs/openrisc-generic.h +++ b/include/configs/openrisc-generic.h @@ -115,7 +115,6 @@ * Command line configuration. */ #define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF #define CONFIG_CMD_BSP #define CONFIG_CMD_MII diff --git a/include/configs/origen.h b/include/configs/origen.h index 21d8e7a..ef80bf6 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -51,7 +51,6 @@ #define S5P_CHECK_LPA 0xABAD0000 #undef CONFIG_CMD_PING -#define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FS_GENERIC diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index af89e6b..362cf30 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -895,7 +895,6 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF #define CONFIG_CMD_REGINFO /* diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index e9cc274..588a6c5 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -425,7 +425,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#define CONFIG_CMD_ELF #define CONFIG_CMD_REGINFO /* diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 516d381..41b7393 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -168,13 +168,11 @@ * Command line configuration. */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_MII #define CONFIG_CMD_PING #undef CONFIG_CMD_FAT #undef CONFIG_CMD_IDE -#undef CONFIG_CMD_ELF #undef CONFIG_CMD_BEDBUG #endif /* __CONFIG_H */ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 150698e..18f45af 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -216,9 +216,6 @@ "nand erase.part ramdisk; " \ "nand write ${ram_addr} ramdisk ${filesize}; fi\0" -/* miscellaneous commands */ -#define CONFIG_CMD_ELF - /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index a7ec8f5..9395bda 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -45,7 +45,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT2 #define CONFIG_CMD_DHCP diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index 4de15bf..53ff802 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -45,7 +45,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT2 #define CONFIG_CMD_DHCP diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 45f5e78..5cd0906 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -158,7 +158,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); * Command line configuration. */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_BOOTZ #define CONFIG_CMD_GREPENV #define CONFIG_CMD_IRQ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 32e3a9b..c96ec90 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -141,7 +141,6 @@ #define CONFIG_IP_DEFRAG /* Can't boot elf images */ -#undef CONFIG_CMD_ELF #define CONFIG_CMD_HASH #define CONFIG_HASH_VERIFY diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 0717156..87e562e 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -539,7 +539,6 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#define CONFIG_CMD_ELF #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 00aab6b..eed0f49 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -20,6 +20,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD + /* High Level Configuration Options */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ @@ -241,8 +243,8 @@ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -472,8 +474,8 @@ * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -494,6 +496,7 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index a6bfa76..fb38502 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -79,7 +79,6 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 4ec9c65..1d9ce92 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -68,7 +68,6 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_REGINFO #define CONFIG_CMD_ONENAND -#define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_MTDPARTS diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index dbba88b..217cfc0 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -43,7 +43,6 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_CMD_PING -#define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP /* MMC SPL */ diff --git a/include/configs/som-6896.h b/include/configs/som-6896.h new file mode 100644 index 0000000..300e9df --- /dev/null +++ b/include/configs/som-6896.h @@ -0,0 +1,38 @@ +/* + * Configuration settings for the SOM-6896 + * + * Copyright (C) 2015 NovaTech LLC + * George McCollister <george.mccollister@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI} + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP + +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x00ff0000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index e1ba791..ddcfe94 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -73,7 +73,10 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */ #define CONFIG_SYS_TEXT_BASE 0x2a000000 #define CONFIG_PRE_CON_BUF_ADDR 0x2f000000 -#define CONFIG_SYS_SPL_MALLOC_START 0x2ff00000 +/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here + * since it needs to fit in with the other values. By also #defining it + * we get warnings if the Kconfig value mismatches. */ +#define CONFIG_SPL_STACK_R_ADDR 0x2fe00000 #define CONFIG_SPL_BSS_START_ADDR 0x2ff80000 #else #define SDRAM_OFFSET(x) 0x4##x @@ -81,12 +84,14 @@ #define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */ #define CONFIG_SYS_TEXT_BASE 0x4a000000 #define CONFIG_PRE_CON_BUF_ADDR 0x4f000000 -#define CONFIG_SYS_SPL_MALLOC_START 0x4ff00000 +/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here + * since it needs to fit in with the other values. By also #defining it + * we get warnings if the Kconfig value mismatches. */ +#define CONFIG_SPL_STACK_R_ADDR 0x4fe00000 #define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 #endif #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */ #ifdef CONFIG_MACH_SUN9I /* @@ -135,8 +140,7 @@ #endif /* mmc config */ -#if !defined(CONFIG_UART0_PORT_F) -#define CONFIG_MMC +#ifdef CONFIG_MMC #define CONFIG_GENERIC_MMC #define CONFIG_CMD_MMC #define CONFIG_MMC_SUNXI @@ -192,7 +196,7 @@ #define CONFIG_SPL_LIBDISK_SUPPORT -#if !defined(CONFIG_UART0_PORT_F) +#ifdef CONFIG_MMC #define CONFIG_SPL_MMC_SUPPORT #endif @@ -347,11 +351,15 @@ extern int soft_i2c_gpio_scl; #define CONFIG_CMD_FASTBOOT #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_FASTBOOT_BUF_SIZE 0x2000000 +#define CONFIG_ANDROID_BOOT_IMAGE #define CONFIG_FASTBOOT_FLASH + +#ifdef CONFIG_MMC #define CONFIG_FASTBOOT_FLASH_MMC_DEV 0 #define CONFIG_EFI_PARTITION #endif +#endif #ifdef CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_CMD_USB_MASS_STORAGE @@ -430,6 +438,22 @@ extern int soft_i2c_gpio_scl; func(PXE, pxe, na) \ func(DHCP, dhcp, na) +#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT +#define BOOTCMD_SUNXI_COMPAT \ + "bootcmd_sunxi_compat=" \ + "setenv root /dev/mmcblk0p3 rootwait; " \ + "if ext2load mmc 0 0x44000000 uEnv.txt; then " \ + "echo Loaded environment from uEnv.txt; " \ + "env import -t 0x44000000 ${filesize}; " \ + "fi; " \ + "setenv bootargs console=${console} root=${root} ${extraargs}; " \ + "ext2load mmc 0 0x43000000 script.bin && " \ + "ext2load mmc 0 0x48000000 uImage && " \ + "bootm 0x48000000\0" +#else +#define BOOTCMD_SUNXI_COMPAT +#endif + #include <config_distro_bootcmd.h> #ifdef CONFIG_USB_KEYBOARD @@ -460,6 +484,7 @@ extern int soft_i2c_gpio_scl; MEM_LAYOUT_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "console=ttyS0,115200\0" \ + BOOTCMD_SUNXI_COMPAT \ BOOTENV #else /* ifndef CONFIG_SPL_BUILD */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index d3138fe..26028df 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -273,7 +273,6 @@ * Command line configuration. */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA #define CONFIG_CMD_GREPENV #define CONFIG_CMD_IRQ diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 41c2c72..e3c41ef 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -69,7 +69,6 @@ * Command line configuration */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_PING #define CONFIG_OF_LIBFDT diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 6dc6515..586bd2b 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -56,6 +56,8 @@ "fdt_addr_r=0x88000000\0" \ "rdaddr=0x88080000\0" \ "ramdisk_addr_r=0x88080000\0" \ + "scriptaddr=0x80000000\0" \ + "pxefile_addr_r=0x80100000\0" \ "bootm_size=0x10000000\0" #define DEFAULT_MMC_TI_ARGS \ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 58c98ce..ed86561 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -32,6 +32,12 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \ GENERATED_GBL_DATA_SIZE) +#ifdef CONFIG_SYS_MALLOC_F_LEN +#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN +#else +#define SPL_MALLOC_F_SIZE 0 +#endif + /* SPL SPI Loader Configuration */ #define CONFIG_SPL_PAD_TO 65536 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) @@ -44,6 +50,7 @@ #define CONFIG_SPL_STACK_SIZE (8 * 1024) #define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ CONFIG_SYS_SPL_MALLOC_SIZE + \ + SPL_MALLOC_F_SIZE + \ CONFIG_SPL_STACK_SIZE - 4) #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_SUPPORT @@ -52,14 +59,23 @@ /* UART Configuration */ #define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_MEM32 +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) +#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 +#else +#define CONFIG_KEYSTONE_SERIAL +#endif #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE -#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6) #define CONFIG_CONS_INDEX 1 +#ifndef CONFIG_SOC_K2G +#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6) +#else +#define CONFIG_SYS_NS16550_CLK clk_get_rate(uart_pll_clk) / 2 +#endif + /* SPI Configuration */ #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_DAVINCI_SPI @@ -291,6 +307,10 @@ /* we may include files below only after all above definitions */ #include <asm/arch/hardware.h> #include <asm/arch/clock.h> +#ifndef CONFIG_SOC_K2G #define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6) +#else +#define CONFIG_SYS_HZ_CLOCK external_clk[sys_clk] +#endif #endif /* __CONFIG_KS2_EVM_H */ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 1cd7dae..741f71f 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -58,11 +58,15 @@ * Hardware drivers */ #define CONFIG_SYS_NS16550 +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000 -#define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 UART3_BASE +#else +#define CONFIG_OMAP_SERIAL +#endif +#define CONFIG_CONS_INDEX 3 /* TWL6030 */ #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 189ea7e..5acbc92 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -51,9 +51,13 @@ * Hardware drivers */ #define CONFIG_SYS_NS16550 +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000 +#else +#define CONFIG_OMAP_SERIAL +#endif /* * Environment setup @@ -157,4 +161,12 @@ #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ #endif +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_MMC +#endif + #endif /* __CONFIG_TI_OMAP5_COMMON_H */ diff --git a/include/configs/vct.h b/include/configs/vct.h index 80f6a60..92726c8 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -84,7 +84,6 @@ * Commands */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C @@ -288,7 +287,6 @@ int vct_gpio_get(int pin); #undef CONFIG_CMD_DHCP #undef CONFIG_CMD_EEPROM #undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_ELF #undef CONFIG_CMD_FAT #undef CONFIG_CMD_I2C #undef CONFIG_CMD_I2C diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index ef3014d..0f2f1a3 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -168,11 +168,13 @@ #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) /* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_2 (0x880000000) /* Top 16MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x01000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE +#define PHYS_SDRAM_2_SIZE 0x180000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Enable memtest */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index bc4a998..a6f5d6a 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -373,7 +373,6 @@ #undef CONFIG_CMD_ENV #endif -#define CONFIG_CMD_ELF /* Pass Ethernet MAC to VxWorks */ #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 3f153f2..faadab8 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -115,7 +115,6 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_ZBOOT -#define CONFIG_CMD_ELF #define CONFIG_BOOTARGS \ "root=/dev/sdb3 init=/sbin/init rootwait ro" @@ -217,7 +216,7 @@ /* Default environment */ #define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_HOSTNAME "x86" +#define CONFIG_HOSTNAME x86 #define CONFIG_BOOTFILE "bzImage" #define CONFIG_LOADADDR 0x1000000 diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h index 309d68d..6bd6be8 100644 --- a/include/configs/xilinx-ppc.h +++ b/include/configs/xilinx-ppc.h @@ -29,7 +29,6 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_CACHE #define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #undef CONFIG_CMD_JFFS2 diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index da87188..ed09b7f 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -73,7 +73,6 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_FS_GENERIC #define CONFIG_DOS_PARTITION -#define CONFIG_CMD_ELF #define CONFIG_MP #define CONFIG_CMD_MII diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h index 4fafb5a..37a31c4 100644 --- a/include/configs/xpedite1000.h +++ b/include/configs/xpedite1000.h @@ -191,7 +191,6 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ #define CONFIG_CMD_JFFS2 diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index b5d1126..51781da 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -532,7 +532,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_DS4510_INFO #define CONFIG_CMD_DTT #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ #define CONFIG_CMD_JFFS2 diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index 34a124c..e48960b 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -315,7 +315,6 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MII diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 0d24234..3645cb2 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -387,7 +387,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_DS4510_INFO #define CONFIG_CMD_DTT #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MII diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index f30d199..7bf0cca 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -371,7 +371,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_DHCP #define CONFIG_CMD_DTT #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_I2C #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MII diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 81b9ce4..b7134eb 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -84,7 +84,6 @@ */ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING -#define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_USB diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index e7ab50a..873c42d 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -289,7 +289,6 @@ /* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) # define CONFIG_API -# define CONFIG_CMD_ELF # define CONFIG_SYS_MMC_MAX_DEVICE 1 #endif diff --git a/include/cpsw.h b/include/cpsw.h index 547b40c..cf1d30b 100644 --- a/include/cpsw.h +++ b/include/cpsw.h @@ -31,6 +31,8 @@ enum { struct cpsw_platform_data { u32 mdio_base; u32 cpsw_base; + u32 mac_id; + u32 gmii_sel; int mdio_div; int channels; /* number of cpdma channels (symmetric) */ u32 cpdma_reg_ofs; /* cpdma register offset */ diff --git a/include/debug_uart.h b/include/debug_uart.h index a75e377..5d5349b 100644 --- a/include/debug_uart.h +++ b/include/debug_uart.h @@ -38,10 +38,15 @@ * To enable the debug UART in your serial driver: * * - #include <debug_uart.h> - * - Define debug_uart_init(), trying to avoid using the stack + * - Define _debug_uart_init(), trying to avoid using the stack * - Define _debug_uart_putc() as static inline (avoiding stack usage) * - Immediately afterwards, add DEBUG_UART_FUNCS to define the rest of the * functionality (printch(), etc.) + * + * If your board needs additional init for the UART to work, enable + * CONFIG_DEBUG_UART_BOARD_INIT and write a function called + * board_debug_uart_init() to perform that init. When debug_uart_init() is + * called, the init will happen automatically. */ /** @@ -57,6 +62,14 @@ */ void debug_uart_init(void); +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void); +#else +static inline void board_debug_uart_init(void) +{ +} +#endif + /** * printch() - Output a character to the debug UART * @@ -92,6 +105,12 @@ void printhex4(uint value); */ void printhex8(uint value); +#ifdef CONFIG_DEBUG_UART_ANNOUNCE +#define _DEBUG_UART_ANNOUNCE printascii("<debug_uart> "); +#else +#define _DEBUG_UART_ANNOUNCE +#endif + /* * Now define some functions - this should be inserted into the serial driver */ @@ -132,6 +151,13 @@ void printhex8(uint value); void printhex8(uint value) \ { \ printhex(value, 8); \ - } + } \ +\ + void debug_uart_init(void) \ + { \ + board_debug_uart_init(); \ + _debug_uart_init(); \ + _DEBUG_UART_ANNOUNCE \ + } \ #endif diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 1eeec74..da41499 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -49,6 +49,7 @@ enum uclass_id { UCLASS_PMIC, /* PMIC I/O device */ UCLASS_REGULATOR, /* Regulator device */ UCLASS_RESET, /* Reset device */ + UCLASS_REMOTEPROC, /* Remote Processor device */ UCLASS_RTC, /* Real time clock device */ UCLASS_SERIAL, /* Serial UART */ UCLASS_SPI, /* SPI bus */ diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h new file mode 100644 index 0000000..7203687 --- /dev/null +++ b/include/dt-bindings/pinctrl/am43xx.h @@ -0,0 +1,33 @@ +/* + * This header provides constants specific to AM43XX pinctrl bindings. + */ + +#ifndef _DT_BINDINGS_PINCTRL_AM43XX_H +#define _DT_BINDINGS_PINCTRL_AM43XX_H + +#define MUX_MODE0 0 +#define MUX_MODE1 1 +#define MUX_MODE2 2 +#define MUX_MODE3 3 +#define MUX_MODE4 4 +#define MUX_MODE5 5 +#define MUX_MODE6 6 +#define MUX_MODE7 7 +#define MUX_MODE8 8 + +#define PULL_DISABLE (1 << 16) +#define PULL_UP (1 << 17) +#define INPUT_EN (1 << 18) +#define SLEWCTRL_SLOW (1 << 19) +#define SLEWCTRL_FAST 0 +#define DS0_PULL_UP_DOWN_EN (1 << 27) +#define WAKEUP_ENABLE (1 << 29) + +#define PIN_OUTPUT (PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN 0 +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN) + +#endif diff --git a/include/dt-bindings/pwm/pwm.h b/include/dt-bindings/pwm/pwm.h new file mode 100644 index 0000000..96f49e8 --- /dev/null +++ b/include/dt-bindings/pwm/pwm.h @@ -0,0 +1,14 @@ +/* + * This header provides constants for most PWM bindings. + * + * Most PWM bindings can include a flags cell as part of the PWM specifier. + * In most cases, the format of the flags cell uses the standard values + * defined in this header. + */ + +#ifndef _DT_BINDINGS_PWM_PWM_H +#define _DT_BINDINGS_PWM_PWM_H + +#define PWM_POLARITY_INVERTED (1 << 0) + +#endif diff --git a/include/exports.h b/include/exports.h index a3e0469..deef8fb 100644 --- a/include/exports.h +++ b/include/exports.h @@ -19,7 +19,7 @@ int printf(const char* fmt, ...); void install_hdlr(int, interrupt_handler_t, void*); void free_hdlr(int); void *malloc(size_t); -#ifndef CONFIG_SYS_MALLOC_SIMPLE +#if !CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) void free(void*); #endif void __udelay(unsigned long); diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 7d30ace..7b4011f 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -3,7 +3,20 @@ #include <asm/types.h> -#define BIT(nr) (1UL << (nr)) +#define BIT(nr) (1UL << (nr)) +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) + +/* + * Create a contiguous bitmask starting at bit position @l and ending at + * position @h. For example + * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. + */ +#define GENMASK(h, l) \ + (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define GENMASK_ULL(h, l) \ + (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) /* * ffs: find first bit set. This is defined the same way as @@ -106,9 +119,6 @@ static inline unsigned int generic_hweight8(unsigned int w) return (res & 0x0F) + ((res >> 4) & 0x0F); } -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) - #include <asm/bitops.h> /* linux/include/asm-generic/bitops/non-atomic.h */ diff --git a/include/malloc.h b/include/malloc.h index f4da9e6..f20e4d3 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -872,7 +872,7 @@ extern Void_t* sbrk(); #else -#ifdef CONFIG_SYS_MALLOC_SIMPLE +#if CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) #define malloc malloc_simple #define realloc realloc_simple #define memalign memalign_simple diff --git a/include/pci_ids.h b/include/pci_ids.h index 49f7d7d..17a01a0 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -3022,6 +3022,8 @@ #define PCI_DEVICE_ID_INTEL_IXP2800 0x9004 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI 0x9c03 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC 0x9c45 +#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI 0x9c83 +#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LPC 0x9cc3 #define PCI_DEVICE_ID_INTEL_S21152BB 0xb152 #define PCI_VENDOR_ID_SCALEMP 0x8686 diff --git a/include/remoteproc.h b/include/remoteproc.h new file mode 100644 index 0000000..c6e044d --- /dev/null +++ b/include/remoteproc.h @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2015 + * Texas Instruments Incorporated - http://www.ti.com/ + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _RPROC_H_ +#define _RPROC_H_ + +/* + * Note: The platform data support is not meant for use with newer + * platforms. This is meant only for legacy devices. This mode of + * initialization *will* be eventually removed once all necessary + * platforms have moved to dm/fdt. + */ +#include <dm/platdata.h> /* For platform data support - non dt world */ + +/** + * enum rproc_mem_type - What type of memory model does the rproc use + * @RPROC_INTERNAL_MEMORY_MAPPED: Remote processor uses own memory and is memory + * mapped to the host processor over an address range. + * + * Please note that this is an enumeration of memory model of different types + * of remote processors. Few of the remote processors do have own internal + * memories, while others use external memory for instruction and data. + */ +enum rproc_mem_type { + RPROC_INTERNAL_MEMORY_MAPPED = 0, +}; + +/** + * struct dm_rproc_uclass_pdata - platform data for a CPU + * @name: Platform-specific way of naming the Remote proc + * @mem_type: one of 'enum rproc_mem_type' + * @driver_plat_data: driver specific platform data that may be needed. + * + * This can be accessed with dev_get_uclass_platdata() for any UCLASS_REMOTEPROC + * device. + * + */ +struct dm_rproc_uclass_pdata { + const char *name; + enum rproc_mem_type mem_type; + void *driver_plat_data; +}; + +/** + * struct dm_rproc_ops - Operations that are provided by remote proc driver + * @init: Initialize the remoteproc device invoked after probe (optional) + * Return 0 on success, -ve error on fail + * @load: Load the remoteproc device using data provided(mandatory) + * This takes the following additional arguments. + * addr- Address of the binary image to be loaded + * size- Size of the binary image to be loaded + * Return 0 on success, -ve error on fail + * @start: Start the remoteproc device (mandatory) + * Return 0 on success, -ve error on fail + * @stop: Stop the remoteproc device (optional) + * Return 0 on success, -ve error on fail + * @reset: Reset the remote proc device (optional) + * Return 0 on success, -ve error on fail + * @is_running: Check if the remote processor is running(optional) + * Return 0 on success, 1 if not running, -ve on others errors + * @ping: Ping the remote device for basic communication check(optional) + * Return 0 on success, 1 if not responding, -ve on other errors + */ +struct dm_rproc_ops { + int (*init)(struct udevice *dev); + int (*load)(struct udevice *dev, ulong addr, ulong size); + int (*start)(struct udevice *dev); + int (*stop)(struct udevice *dev); + int (*reset)(struct udevice *dev); + int (*is_running)(struct udevice *dev); + int (*ping)(struct udevice *dev); +}; + +/* Accessor */ +#define rproc_get_ops(dev) ((struct dm_rproc_ops *)(dev)->driver->ops) + +#ifdef CONFIG_REMOTEPROC +/** + * rproc_init() - Initialize all bound remote proc devices + * + * Return: 0 if all ok, else appropriate error value. + */ +int rproc_init(void); + +/** + * rproc_is_initialized() - check to see if remoteproc devices are initialized + * + * Return: 0 if all devices are initialized, else appropriate error value. + */ +bool rproc_is_initialized(void); + +/** + * rproc_load() - load binary to a remote processor + * @id: id of the remote processor + * @addr: address in memory where the binary image is located + * @size: size of the binary image + * + * Return: 0 if all ok, else appropriate error value. + */ +int rproc_load(int id, ulong addr, ulong size); + +/** + * rproc_start() - Start a remote processor + * @id: id of the remote processor + * + * Return: 0 if all ok, else appropriate error value. + */ +int rproc_start(int id); + +/** + * rproc_stop() - Stop a remote processor + * @id: id of the remote processor + * + * Return: 0 if all ok, else appropriate error value. + */ +int rproc_stop(int id); + +/** + * rproc_reset() - reset a remote processor + * @id: id of the remote processor + * + * Return: 0 if all ok, else appropriate error value. + */ +int rproc_reset(int id); + +/** + * rproc_ping() - ping a remote processor to check if it can communicate + * @id: id of the remote processor + * + * NOTE: this might need communication path available, which is not implemented + * as part of remoteproc framework - hook on to appropriate bus architecture to + * do the same + * + * Return: 0 if all ok, else appropriate error value. + */ +int rproc_ping(int id); + +/** + * rproc_is_running() - check to see if remote processor is running + * @id: id of the remote processor + * + * NOTE: this may not involve actual communication capability of the remote + * processor, but just ensures that it is out of reset and executing code. + * + * Return: 0 if all ok, else appropriate error value. + */ +int rproc_is_running(int id); +#else +static inline int rproc_init(void) { return -ENOSYS; } +static inline bool rproc_is_initialized(void) { return false; } +static inline int rproc_load(int id, ulong addr, ulong size) { return -ENOSYS; } +static inline int rproc_start(int id) { return -ENOSYS; } +static inline int rproc_stop(int id) { return -ENOSYS; } +static inline int rproc_reset(int id) { return -ENOSYS; } +static inline int rproc_ping(int id) { return -ENOSYS; } +static inline int rproc_is_running(int id) { return -ENOSYS; } +#endif + +#endif /* _RPROC_H_ */ diff --git a/include/vxworks.h b/include/vxworks.h index 122043c..f69b008 100644 --- a/include/vxworks.h +++ b/include/vxworks.h @@ -8,31 +8,38 @@ #ifndef _VXWORKS_H_ #define _VXWORKS_H_ -int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); -void boot_prep_vxworks(bootm_headers_t *images); -void boot_jump_vxworks(bootm_headers_t *images); -void do_bootvx_fdt(bootm_headers_t *images); - /* - * Use bootaddr to find the location in memory that VxWorks - * will look for the bootline string. The default value for - * PowerPC is LOCAL_MEM_LOCAL_ADRS + BOOT_LINE_OFFSET which - * defaults to 0x4200 + * VxWorks x86 E820 related stuff + * + * VxWorks on x86 gets E820 information from pre-defined address @ + * 0x4a00 and 0x4000. At 0x4a00 it's an information table defined + * by VxWorks and the actual E820 table entries starts from 0x4000. + * As defined by the BIOS E820 spec, the maximum number of E820 table + * entries is 128 and each entry occupies 20 bytes, so it's 128 * 20 + * = 2560 (0xa00) bytes in total. That's where VxWorks stores some + * information that is retrieved from the BIOS E820 call and saved + * later for sanity test during the kernel boot-up. */ -#ifndef CONFIG_SYS_VXWORKS_BOOT_ADDR -#define CONFIG_SYS_VXWORKS_BOOT_ADDR 0x4200 -#endif +#define VXWORKS_E820_DATA_ADDR 0x4000 +#define VXWORKS_E820_INFO_ADDR 0x4a00 -#ifndef CONFIG_SYS_VXWORKS_BOOT_DEVICE -#if defined(CONFIG_4xx) -#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "emac(0,0)" -#else -#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "eth(0,0)" -#endif -#endif +/* E820 info signatiure "SMAP" - System MAP */ +#define E820_SIGNATURE 0x534d4150 -#ifndef CONFIG_SYS_VXWORKS_SERVERNAME -#define CONFIG_SYS_VXWORKS_SERVERNAME "srv" -#endif +struct e820info { + u32 sign; /* "SMAP" signature */ + u32 x0; /* don't care, used by VxWorks */ + u32 x1; /* don't care, used by VxWorks */ + u32 x2; /* don't care, used by VxWorks */ + u32 addr; /* last e820 table entry addr */ + u32 x3; /* don't care, used by VxWorks */ + u32 entries; /* e820 table entry count */ + u32 error; /* must be zero */ +}; + +int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +void boot_prep_vxworks(bootm_headers_t *images); +void boot_jump_vxworks(bootm_headers_t *images); +void do_bootvx_fdt(bootm_headers_t *images); #endif diff --git a/lib/efi/efi_stub.c b/lib/efi/efi_stub.c index d4d3e49..e138709 100644 --- a/lib/efi/efi_stub.c +++ b/lib/efi/efi_stub.c @@ -59,7 +59,7 @@ struct __packed desctab_info { * considering if we start needing more U-Boot functionality. Note that we * could then move get_codeseg32() to arch/x86/cpu/cpu.c. */ -void debug_uart_init(void) +void _debug_uart_init(void) { } diff --git a/test/dm/Makefile b/test/dm/Makefile index eda9643..7b3626c 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_DM_MMC) += mmc.o obj-$(CONFIG_DM_PCI) += pci.o obj-$(CONFIG_RAM) += ram.o obj-y += regmap.o +obj-$(CONFIG_REMOTEPROC) += remoteproc.o obj-$(CONFIG_RESET) += reset.o obj-$(CONFIG_DM_RTC) += rtc.o obj-$(CONFIG_DM_SPI_FLASH) += sf.o diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c new file mode 100644 index 0000000..0e5f330 --- /dev/null +++ b/test/dm/remoteproc.c @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2015 + * Texas Instruments Incorporated - http://www.ti.com/ + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <remoteproc.h> +#include <dm/test.h> +#include <test/ut.h> +/** + * dm_test_remoteproc_base() - test the operations after initializations + * @uts: unit test state + * + * Return: 0 if test passed, else error + */ +static int dm_test_remoteproc_base(struct unit_test_state *uts) +{ + if (!rproc_is_initialized()) + ut_assertok(rproc_init()); + + /* Ensure we are initialized */ + ut_asserteq(true, rproc_is_initialized()); + + + /* platform data device 1 */ + ut_assertok(rproc_stop(0)); + ut_assertok(rproc_reset(0)); + /* -> invalid attempt tests */ + ut_asserteq(-EINVAL, rproc_start(0)); + ut_asserteq(-EINVAL, rproc_ping(0)); + /* Valid tests */ + ut_assertok(rproc_load(0, 1, 0)); + ut_assertok(rproc_start(0)); + ut_assertok(rproc_is_running(0)); + ut_assertok(rproc_ping(0)); + ut_assertok(rproc_reset(0)); + ut_assertok(rproc_stop(0)); + + /* dt device device 1 */ + ut_assertok(rproc_stop(1)); + ut_assertok(rproc_reset(1)); + ut_assertok(rproc_load(1, 1, 0)); + ut_assertok(rproc_start(1)); + ut_assertok(rproc_is_running(1)); + ut_assertok(rproc_ping(1)); + ut_assertok(rproc_reset(1)); + ut_assertok(rproc_stop(1)); + + /* dt device device 2 */ + ut_assertok(rproc_stop(0)); + ut_assertok(rproc_reset(0)); + /* -> invalid attempt tests */ + ut_asserteq(-EINVAL, rproc_start(0)); + ut_asserteq(-EINVAL, rproc_ping(0)); + /* Valid tests */ + ut_assertok(rproc_load(2, 1, 0)); + ut_assertok(rproc_start(2)); + ut_assertok(rproc_is_running(2)); + ut_assertok(rproc_ping(2)); + ut_assertok(rproc_reset(2)); + ut_assertok(rproc_stop(2)); + + return 0; +} +DM_TEST(dm_test_remoteproc_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/tools/kwbimage.c b/tools/kwbimage.c index 5e62d08..d33f1b6 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -681,6 +681,9 @@ static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd, exit(EXIT_FAILURE); } + /* The MVEBU BootROM does not allow non word aligned payloads */ + sbuf->st_size = ALIGN_SUP(sbuf->st_size, 4); + version = image_get_version(); switch (version) { /* |