diff options
| -rw-r--r-- | arch/x86/dts/Makefile | 3 | ||||
| -rw-r--r-- | arch/x86/dts/bayleybay.dts | 134 | ||||
| -rw-r--r-- | board/intel/Kconfig | 9 | ||||
| -rw-r--r-- | board/intel/bayleybay/Kconfig | 27 | ||||
| -rw-r--r-- | board/intel/bayleybay/MAINTAINERS | 6 | ||||
| -rw-r--r-- | board/intel/bayleybay/Makefile | 7 | ||||
| -rw-r--r-- | board/intel/bayleybay/bayleybay.c | 19 | ||||
| -rw-r--r-- | board/intel/bayleybay/start.S | 9 | ||||
| -rw-r--r-- | configs/bayleybay_defconfig | 25 | ||||
| -rw-r--r-- | include/configs/bayleybay.h | 45 |
10 files changed, 283 insertions, 1 deletions
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index f86514c..44e2829 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,4 +1,5 @@ -dtb-y += chromebook_link.dtb \ +dtb-y += bayleybay.dtb \ + chromebook_link.dtb \ chromebox_panther.dtb \ crownbay.dtb \ galileo.dtb \ diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts new file mode 100644 index 0000000..cbbdee2 --- /dev/null +++ b/arch/x86/dts/bayleybay.dts @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include <dt-bindings/gpio/x86-gpio.h> + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "rtc.dtsi" + +/ { + model = "Intel Bayley Bay"; + compatible = "intel,bayleybay", "intel,baytrail"; + + aliases { + serial0 = &serial; + spi0 = "/spi"; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <1>; + intel,apic-id = <2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <2>; + intel,apic-id = <4>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <3>; + intel,apic-id = <6>; + }; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + reg = <0>; + compatible = "winbond,w25q64dw", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + }; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x20>; + bank-name = "C"; + }; + + gpiod { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x60 0x20>; + bank-name = "D"; + }; + + gpioe { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x80 0x20>; + bank-name = "E"; + }; + + gpiof { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0xA0 0x20>; + bank-name = "F"; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + }; + + microcode { + update@0 { +#include "microcode/m0230671117.dtsi" + }; + }; + +}; diff --git a/board/intel/Kconfig b/board/intel/Kconfig index 3d9ecf0..f7d71c3 100644 --- a/board/intel/Kconfig +++ b/board/intel/Kconfig @@ -10,6 +10,14 @@ choice prompt "Mainboard model" optional +config TARGET_BAYLEYBAY + bool "Bayley Bay" + help + This is the Intel Bayley Bay Customer Reference Board. It contains an + Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM + 4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC, + PCIe and some other sensor interfaces. + config TARGET_CROWNBAY bool "Crown Bay" help @@ -45,6 +53,7 @@ config TARGET_MINNOWMAX endchoice +source "board/intel/bayleybay/Kconfig" source "board/intel/crownbay/Kconfig" source "board/intel/galileo/Kconfig" source "board/intel/minnowmax/Kconfig" diff --git a/board/intel/bayleybay/Kconfig b/board/intel/bayleybay/Kconfig new file mode 100644 index 0000000..597228f --- /dev/null +++ b/board/intel/bayleybay/Kconfig @@ -0,0 +1,27 @@ +if TARGET_BAYLEYBAY + +config SYS_BOARD + default "bayleybay" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "baytrail" + +config SYS_CONFIG_NAME + default "bayleybay" + +config SYS_TEXT_BASE + default 0xfff00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + +config PCIE_ECAM_BASE + default 0xe0000000 + +endif diff --git a/board/intel/bayleybay/MAINTAINERS b/board/intel/bayleybay/MAINTAINERS new file mode 100644 index 0000000..85fa516 --- /dev/null +++ b/board/intel/bayleybay/MAINTAINERS @@ -0,0 +1,6 @@ +Intel Bayley Bay +M: Bin Meng <bmeng.cn@gmail.com> +S: Maintained +F: board/intel/bayleybay +F: include/configs/bayleybay.h +F: configs/bayleybay_defconfig diff --git a/board/intel/bayleybay/Makefile b/board/intel/bayleybay/Makefile new file mode 100644 index 0000000..88b5aad --- /dev/null +++ b/board/intel/bayleybay/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += bayleybay.o start.o diff --git a/board/intel/bayleybay/bayleybay.c b/board/intel/bayleybay/bayleybay.c new file mode 100644 index 0000000..7844796 --- /dev/null +++ b/board/intel/bayleybay/bayleybay.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/gpio.h> +#include <netdev.h> + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/intel/bayleybay/start.S b/board/intel/bayleybay/start.S new file mode 100644 index 0000000..a71db69 --- /dev/null +++ b/board/intel/bayleybay/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig new file mode 100644 index 0000000..e10e86a --- /dev/null +++ b/configs/bayleybay_defconfig @@ -0,0 +1,25 @@ +CONFIG_X86=y +CONFIG_VENDOR_INTEL=y +CONFIG_DEFAULT_DEVICE_TREE="bayleybay" +CONFIG_TARGET_BAYLEYBAY=y +CONFIG_HAVE_INTEL_ME=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_OF_CONTROL=y +CONFIG_CPU=y +CONFIG_DM_PCI=y +CONFIG_SPI_FLASH=y +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_DM_RTC=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_SYS_VSNPRINTF=y diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h new file mode 100644 index 0000000..cc95aec --- /dev/null +++ b/include/configs/bayleybay.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_X86_SERIAL + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP +#define CONFIG_E1000 + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA} + +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_CMD_MMC + +/* BayTrail IGD support */ +#define CONFIG_VGA_AS_SINGLE_DEVICE + +/* Environment configuration */ +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x006ff000 + +#endif /* __CONFIG_H */ |