diff options
| -rw-r--r-- | arch/arm/cpu/armv7/mx7/clock.c | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx7/soc.c | 18 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7/sys_proto.h | 1 | ||||
| -rw-r--r-- | board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c | 8 | ||||
| -rw-r--r-- | board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c | 6 |
5 files changed, 34 insertions, 5 deletions
diff --git a/arch/arm/cpu/armv7/mx7/clock.c b/arch/arm/cpu/armv7/mx7/clock.c index 00ff806..be42f79 100644 --- a/arch/arm/cpu/armv7/mx7/clock.c +++ b/arch/arm/cpu/armv7/mx7/clock.c @@ -707,9 +707,9 @@ static void init_clk_wdog(void) /* enable the clock gate */ clock_enable(CCGR_WDOG1, 1); - clock_enable(CCGR_WDOG2, 2); - clock_enable(CCGR_WDOG3, 3); - clock_enable(CCGR_WDOG4, 4); + clock_enable(CCGR_WDOG2, 1); + clock_enable(CCGR_WDOG3, 1); + clock_enable(CCGR_WDOG4, 1); } diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index f150569..829e30c 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -356,6 +356,24 @@ void boot_mode_apply(uint32_t cfg_val) writel(reg, &src_reg->gpr10); } +void set_wdog_reset(struct wdog_regs *wdog) +{ + u32 reg = readw(&wdog->wcr); + /* + * Output WDOG_B signal to reset external pmic or POR_B decided by + * the board desgin. Without external reset, the peripherals/DDR/ + * PMIC are not reset, that may cause system working abnormal. + */ + reg = readw(&wdog->wcr); + reg |= 1 << 3; + /* + * WDZST bit is write-once only bit. Align this bit in kernel, + * otherwise kernel code will have no chance to set this bit. + */ + reg |= 1 << 0; + writew(reg, &wdog->wcr); +} + /* * cfg_val will be used for * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h b/arch/arm/include/asm/arch-mx7/sys_proto.h index eb6771b..ac97f5e 100644 --- a/arch/arm/include/asm/arch-mx7/sys_proto.h +++ b/arch/arm/include/asm/arch-mx7/sys_proto.h @@ -22,6 +22,7 @@ u32 get_cpu_rev(void); const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); +void set_wdog_reset(struct wdog_regs *wdog); int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data); int arch_auxiliary_core_check_up(u32 core_id); diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c b/board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c index 1dfac25..cd1dabe 100644 --- a/board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c @@ -261,6 +261,10 @@ static iomux_v3_cfg_t const per_rst_pads[] = { MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + #ifdef CONFIG_FEC_MXC static iomux_v3_cfg_t const fec1_pads[] = { MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), @@ -641,6 +645,10 @@ int board_late_init(void) board_late_mmc_init(); #endif + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + return 0; } diff --git a/board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c b/board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c index b76760c..5c108f2 100644 --- a/board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c +++ b/board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c @@ -559,8 +559,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - /* Reset peripherals */ imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads)); @@ -653,6 +651,10 @@ int board_late_init(void) board_late_mmc_init(); #endif + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + return 0; } |