diff options
53 files changed, 2312 insertions, 134 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2b0d2c9..5eb1d03 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -800,6 +800,7 @@ config ARCH_UNIPHIER bool "Panasonic UniPhier platform" select CPU_V7 select SUPPORT_SPL + select SPL select OF_CONTROL if !SPL_BUILD endchoice diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/cpu/armv7/socfpga/freeze_controller.c index b8c9bce..0be643c 100644 --- a/arch/arm/cpu/armv7/socfpga/freeze_controller.c +++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c @@ -38,8 +38,7 @@ void sys_mgr_frzctrl_freeze_req(void) /* Freeze channel 0 to 2 */ for (channel_id = 0; channel_id <= 2; channel_id++) { ioctrl_reg_offset = (u32)( - &freeze_controller_base->vioctrl + - (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + &freeze_controller_base->vioctrl + channel_id); /* * Assert active low enrnsl, plniotri @@ -120,8 +119,7 @@ void sys_mgr_frzctrl_thaw_req(void) /* Thaw channel 0 to 2 */ for (channel_id = 0; channel_id <= 2; channel_id++) { ioctrl_reg_offset - = (u32)(&freeze_controller_base->vioctrl - + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + = (u32)(&freeze_controller_base->vioctrl + channel_id); /* * Assert active low bhniotri signal and diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index af9db85..25921e7 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -110,6 +110,6 @@ void socfpga_spim_enable(void) { const void *reset = &reset_manager_base->per_mod_reset; - clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB); - clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB); + clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) | + (1 << RSTMGR_PERMODRST_SPIM1_LSB)); } diff --git a/arch/arm/cpu/armv7/uniphier/init_page_table.c b/arch/arm/cpu/armv7/uniphier/init_page_table.c index a0d10a9..febb3c8 100644 --- a/arch/arm/cpu/armv7/uniphier/init_page_table.c +++ b/arch/arm/cpu/armv7/uniphier/init_page_table.c @@ -17,11 +17,7 @@ #define REG DEVICE /* IO Register: Device */ #define DDR DEVICE /* DDR SDRAM: Device */ -#ifdef CONFIG_SPL_BUILD #define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SPL_TEXT_BASE) >> 20)) -#else -#define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SYS_TEXT_BASE) >> 20)) -#endif #define IS_INIT_STACK_AREA(x) ((x) == ((CONFIG_SYS_INIT_SP_ADDR) >> 20)) diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 4472fd9..969e5ad 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -1,18 +1,7 @@ /* * Copyright (C) 2012 Altera <www.altera.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #include "skeleton.dtsi" @@ -639,6 +628,49 @@ clock-names = "biu", "ciu"; }; + qspi: spi@ff705000 { + compatible = "cadence,qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + ext-decoder = <0>; /* external decoder */ + num-chipselect = <4>; + fifo-depth = <128>; + bus-num = <2>; + status = "disabled"; + }; + + spi0: spi@fff00000 { + compatible = "snps,dw-spi-mmio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfff00000 0x1000>; + interrupts = <0 154 4>; + num-chipselect = <4>; + bus-num = <0>; + tx-dma-channel = <&pdma 16>; + rx-dma-channel = <&pdma 17>; + clocks = <&per_base_clk>; + status = "disabled"; + }; + + spi1: spi@fff01000 { + compatible = "snps,dw-spi-mmio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfff01000 0x1000>; + interrupts = <0 156 4>; + num-chipselect = <4>; + bus-num = <1>; + tx-dma-channel = <&pdma 20>; + rx-dma-channel = <&pdma 21>; + clocks = <&per_base_clk>; + status = "disabled"; + }; + /* Local timer */ timer@fffec600 { compatible = "arm,cortex-a9-twd-timer"; diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi index 28c05e7..234a901 100644 --- a/arch/arm/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -1,18 +1,7 @@ /* * Copyright (C) 2012 Altera Corporation <www.altera.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index a1814b4..ea30483 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -1,18 +1,7 @@ /* * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #include "socfpga_cyclone5.dtsi" @@ -25,6 +14,12 @@ bootargs = "console=ttyS0,115200"; }; + aliases { + spi0 = "/spi@ff705000"; /* QSPI */ + spi1 = "/spi@fff00000"; + spi2 = "/spi@fff01000"; + }; + memory { name = "memory"; device_type = "memory"; @@ -48,3 +43,23 @@ &mmc { status = "okay"; }; + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts index 08bbd03..6855878 100644 --- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts @@ -25,10 +25,10 @@ }; aliases { - uart0 = &uart0; - uart1 = &uart1; - uart2 = &uart2; - uart3 = &uart3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts index 23add7c..1227b62 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts @@ -25,10 +25,10 @@ }; aliases { - uart0 = &uart0; - uart1 = &uart1; - uart2 = &uart2; - uart3 = &uart3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts index 91b4dbe..fefc592 100644 --- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts @@ -25,9 +25,9 @@ }; aliases { - uart0 = &uart0; - uart1 = &uart1; - uart2 = &uart2; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts index a8ce049..9b6d95c 100644 --- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts @@ -25,10 +25,10 @@ }; aliases { - uart0 = &uart0; - uart1 = &uart1; - uart2 = &uart2; - uart3 = &uart3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h index fa49f6a..5449726 100644 --- a/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -14,6 +14,7 @@ unsigned long cm_get_sdram_clk_hz(void); unsigned int cm_get_l4_sp_clk_hz(void); unsigned int cm_get_mmc_controller_clk_hz(void); unsigned int cm_get_qspi_controller_clk_hz(void); +unsigned int cm_get_spi_controller_clk_hz(void); #endif typedef struct { diff --git a/arch/arm/include/asm/arch-socfpga/freeze_controller.h b/arch/arm/include/asm/arch-socfpga/freeze_controller.h index 120f20e..f19ad87 100644 --- a/arch/arm/include/asm/arch-socfpga/freeze_controller.h +++ b/arch/arm/include/asm/arch-socfpga/freeze_controller.h @@ -42,7 +42,6 @@ typedef enum { #define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001 #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2 #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1 -#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2 void sys_mgr_frzctrl_freeze_req(void); void sys_mgr_frzctrl_thaw_req(void); diff --git a/arch/arm/include/asm/arch-socfpga/scan_manager.h b/arch/arm/include/asm/arch-socfpga/scan_manager.h index b2686d3..1155fd3 100644 --- a/arch/arm/include/asm/arch-socfpga/scan_manager.h +++ b/arch/arm/include/asm/arch-socfpga/scan_manager.h @@ -13,6 +13,7 @@ struct socfpga_scan_manager { u32 padding[2]; u32 fifo_single_byte; u32 fifo_double_byte; + u32 fifo_triple_byte; u32 fifo_quad_byte; }; diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index d4343ef..98a568f 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -49,23 +49,23 @@ int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN struct liodn_id_table fman1_liodn_tbl[] = { - SET_FMAN_RX_1G_LIODN(1, 0, 6), - SET_FMAN_RX_1G_LIODN(1, 1, 7), - SET_FMAN_RX_1G_LIODN(1, 2, 8), - SET_FMAN_RX_1G_LIODN(1, 3, 9), - SET_FMAN_RX_1G_LIODN(1, 4, 10), - SET_FMAN_RX_10G_LIODN(1, 0, 11), + SET_FMAN_RX_1G_LIODN(1, 0, 11), + SET_FMAN_RX_1G_LIODN(1, 1, 12), + SET_FMAN_RX_1G_LIODN(1, 2, 13), + SET_FMAN_RX_1G_LIODN(1, 3, 14), + SET_FMAN_RX_1G_LIODN(1, 4, 15), + SET_FMAN_RX_10G_LIODN(1, 0, 16), }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #if (CONFIG_SYS_NUM_FMAN == 2) struct liodn_id_table fman2_liodn_tbl[] = { - SET_FMAN_RX_1G_LIODN(2, 0, 12), - SET_FMAN_RX_1G_LIODN(2, 1, 13), - SET_FMAN_RX_1G_LIODN(2, 2, 14), - SET_FMAN_RX_1G_LIODN(2, 3, 15), - SET_FMAN_RX_1G_LIODN(2, 4, 16), - SET_FMAN_RX_10G_LIODN(2, 0, 17), + SET_FMAN_RX_1G_LIODN(2, 0, 17), + SET_FMAN_RX_1G_LIODN(2, 1, 18), + SET_FMAN_RX_1G_LIODN(2, 2, 19), + SET_FMAN_RX_1G_LIODN(2, 3, 20), + SET_FMAN_RX_1G_LIODN(2, 4, 21), + SET_FMAN_RX_10G_LIODN(2, 0, 22), }; int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl); #endif diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index 98815f8..ec3b292 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -14,9 +14,46 @@ #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> +#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE) +#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE) +static void inhibit_portals(void __iomem *addr, int max_portals, + int arch_max_portals, int portal_cinh_size) +{ + uint32_t val; + int i; + + /* arch_max_portals is the maximum based on memory size. This includes + * the reserved memory in the SoC. max_portals the number of physical + * portals in the SoC */ + if (max_portals > arch_max_portals) { + printf("ERROR: portal config error\n"); + max_portals = arch_max_portals; + } + + for (i = 0; i < max_portals; i++) { + out_be32(addr, -1); + val = in_be32(addr); + if (!val) { + printf("ERROR: Stopped after %d portals\n", i); + goto done; + } + addr += portal_cinh_size; + } +#ifdef DEBUG + printf("Cleared %d portals\n", i); +#endif +done: + + return; +} + void setup_portals(void) { ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; + void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE + + CONFIG_SYS_BMAN_SWP_ISDR_REG; + void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE + + CONFIG_SYS_QMAN_SWP_ISDR_REG; #ifdef CONFIG_FSL_CORENET int i; @@ -38,6 +75,12 @@ void setup_portals(void) out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); #endif out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); + + /* Change default state of BMan ISDR portals to all 1s */ + inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS, + CONFIG_SYS_BMAN_SP_CINH_SIZE); + inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS, + CONFIG_SYS_QMAN_SP_CINH_SIZE); } /* Update portal containter to match LAW setup of portal in phy map */ diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 4adba95..8e0508f 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -299,12 +299,16 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, { unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; u64 memsize = (u64)memsize_in_meg << 20; + u64 size; - memsize = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED); - memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM); + size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED); + size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM); - if (memsize) - print_size(memsize, " left unmapped\n"); + if (size || memsize > CONFIG_MAX_MEM_MAPPED) { + print_size(memsize > CONFIG_MAX_MEM_MAPPED ? + memsize - CONFIG_MAX_MEM_MAPPED + size : size, + " left unmapped\n"); + } return memsize_in_meg; } diff --git a/board/altera/socfpga/MAINTAINERS b/board/altera/socfpga/MAINTAINERS index 626c0f7..0482581 100644 --- a/board/altera/socfpga/MAINTAINERS +++ b/board/altera/socfpga/MAINTAINERS @@ -5,3 +5,8 @@ S: Maintained F: board/altera/socfpga/ F: include/configs/socfpga_cyclone5.h F: configs/socfpga_cyclone5_defconfig + +SOCRATES BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: configs/socfpga_socrates_defconfig diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index ce625e5..459d82f 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -12,7 +12,9 @@ #include <usb/s3c_udc.h> #include <usb_mass_storage.h> +#include <micrel.h> #include <netdev.h> +#include <phy.h> DECLARE_GLOBAL_DATA_PTR; @@ -44,6 +46,42 @@ int board_init(void) return 0; } +/* + * PHY configuration + */ +#ifdef CONFIG_PHY_MICREL_KSZ9021 +int board_phy_config(struct phy_device *phydev) +{ + int ret; + /* + * These skew settings for the KSZ9021 ethernet phy is required for ethernet + * to work reliably on most flavors of cyclone5 boards. + */ + ret = ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, + 0x0); + if (ret) + return ret; + + ret = ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, + 0x0); + if (ret) + return ret; + + ret = ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, + 0xf0f0); + if (ret) + return ret; + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} +#endif + #ifdef CONFIG_USB_GADGET struct s3c_plat_otg_data socfpga_otg_data = { .regs_otg = CONFIG_USB_DWC2_REG_ADDR, diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index 2c331ee..5aa11b1 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -11,6 +11,7 @@ #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> #include <asm/fsl_law.h> +#include <asm/mpc85xx_gpio.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; @@ -109,6 +110,19 @@ found: popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); } +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(cpld_base + 0x17, 0x40); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + phys_size_t initdram(int board_type) { phys_size_t dram_size; @@ -124,5 +138,10 @@ phys_size_t initdram(int board_type) #else dram_size = fsl_ddr_sdram_size(); #endif + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + return dram_size; } diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index e394b12..4e8735b 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -11,7 +11,7 @@ #include <mmc.h> #include <fsl_esdhc.h> #include <spi_flash.h> -#include <asm/mpc85xx_gpio.h> +#include "../common/sleep.h" DECLARE_GLOBAL_DATA_PTR; @@ -64,8 +64,8 @@ void board_init_f(ulong bootflag) #ifdef CONFIG_DEEP_SLEEP /* disable the console if boot from deep sleep */ - if (in_be32(&gur->scrtsr[0]) & (1 << 3)) - gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; + if (is_warm_boot()) + fsl_dp_disable_console(); #endif /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("" : : : "memory"); @@ -132,16 +132,3 @@ void board_init_r(gd_t *gd, ulong dest_addr) nand_boot(); #endif } - -#ifdef CONFIG_DEEP_SLEEP -void board_mem_sleep_setup(void) -{ - void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; - - /* does not provide HW signals for power management */ - clrbits_8(cpld_base + 0x17, 0x40); - /* Disable MCKE isolation */ - gpio_set_value(2, 0); - udelay(1); -} -#endif diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 4734f9d..9cd5e15 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -17,8 +17,7 @@ #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> -#include <asm/mpc85xx_gpio.h> - +#include "../common/sleep.h" #include "t104xrdb.h" #include "cpld.h" @@ -44,6 +43,16 @@ int checkboard(void) return 0; } +int board_early_init_f(void) +{ +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + int board_early_init_r(void) { #ifdef CONFIG_SYS_FLASH_BASE @@ -113,14 +122,3 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } - -#ifdef CONFIG_DEEP_SLEEP -void board_mem_sleep_setup(void) -{ - /* does not provide HW signals for power management */ - CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40)); - /* Disable MCKE isolation */ - gpio_set_value(2, 0); - udelay(1); -} -#endif diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index 3155340..2e9dd00 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -1,4 +1,3 @@ -CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +S:CONFIG_ARM=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 7ea4e6e..5dca64b 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -1,4 +1,3 @@ -CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +S:CONFIG_ARM=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index ddf210c..2a6e334 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -1,4 +1,3 @@ -CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +S:CONFIG_ARM=y diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 29681e1..f9d4938 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -246,7 +246,7 @@ int run_descriptor_jr(uint32_t *desc) struct result op; int ret = 0; - memset(&op, sizeof(op), 0); + memset(&op, 0, sizeof(op)); ret = jr_enqueue(desc, desc_done, &op); if (ret) { diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index fe8aa98..03d7ff1 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -324,6 +324,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, #elif defined(CONFIG_SYS_FSL_DDR3) unsigned int data_rate = get_ddr_freq(0); int txp; + unsigned int ip_rev; int odt_overlap; /* * (tXARD and tXARDS). Empirical? @@ -336,7 +337,25 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, */ txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000)); - tmrd_mclk = 4; + ip_rev = fsl_ddr_get_version(); + if (ip_rev >= 0x40700) { + /* + * MRS_CYC = max(tMRD, tMOD) + * tMRD = 4nCK (8nCK for RDIMM) + * tMOD = max(12nCK, 15ns) + */ + tmrd_mclk = max((unsigned int)12, picos_to_mclk(15000)); + } else { + /* + * MRS_CYC = tMRD + * tMRD = 4nCK (8nCK for RDIMM) + */ + if (popts->registered_dimm_en) + tmrd_mclk = 8; + else + tmrd_mclk = 4; + } + /* set the turnaround time */ /* diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 5d82f29..9a8a007 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -247,17 +247,17 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) } #ifdef CONFIG_SYS_FMAN_V3 +#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION /* - * Physically FM1_DTSEC9 and FM1_10GEC1 use the same dual-role MAC, when - * FM1_10GEC1 is enabled and FM1_DTSEC9 is disabled, ensure that the - * dual-role MAC is not disabled, ditto for other dual-role MACs. + * On T2/T4 SoCs, physically FM1_DTSEC9 and FM1_10GEC1 use the same + * dual-role MAC, when FM1_10GEC1 is enabled and FM1_DTSEC9 + * is disabled, ensure that the dual-role MAC is not disabled, + * ditto for other dual-role MACs. */ if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) || ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) || - ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) || ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) || ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) || - ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) || ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) || ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) || ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) || @@ -269,6 +269,17 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) ((info->port == FM2_10GEC1) && (PORT_IS_ENABLED(FM2_DTSEC9))) || ((info->port == FM2_10GEC2) && (PORT_IS_ENABLED(FM2_DTSEC10))) #endif +#else + /* FM1_DTSECx and FM1_10GECx use the same dual-role MAC */ + if (((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) || + ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC2))) || + ((info->port == FM1_DTSEC3) && (PORT_IS_ENABLED(FM1_10GEC3))) || + ((info->port == FM1_DTSEC4) && (PORT_IS_ENABLED(FM1_10GEC4))) || + ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) || + ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC2))) || + ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC3))) || + ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC4))) +#endif ) return; #endif diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index bc94673..d24651b 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -13,6 +13,9 @@ #include "asm/io.h" #include "linux/immap_qe.h" #include "qe.h" +#ifdef CONFIG_LS102XA +#include <asm/arch/immap_ls102xa.h> +#endif #define MPC85xx_DEVDISR_QE_DISABLE 0x1 @@ -335,8 +338,12 @@ int qe_upload_firmware(const struct qe_firmware *firmware) size_t length; const struct qe_header *hdr; #ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_LS102XA + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; +#else ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif +#endif if (!firmware) { printf("Invalid address\n"); return -EINVAL; @@ -470,8 +477,12 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware) size_t length; const struct qe_header *hdr; #ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_LS102XA + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; +#else ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif +#endif if (!firmware) { printf("Invalid address\n"); return -EINVAL; diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index eabbf27..edbd520 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -23,9 +23,11 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BFIN_SPI) += bfin_spi.o obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o +obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o obj-$(CONFIG_CF_SPI) += cf_spi.o obj-$(CONFIG_CF_QSPI) += cf_qspi.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o +obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o obj-$(CONFIG_ICH_SPI) += ich.o diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c new file mode 100644 index 0000000..fa95b19 --- /dev/null +++ b/drivers/spi/cadence_qspi.c @@ -0,0 +1,345 @@ +/* + * Copyright (C) 2012 + * Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <malloc.h> +#include <spi.h> +#include <asm/errno.h> +#include "cadence_qspi.h" + +#define CQSPI_STIG_READ 0 +#define CQSPI_STIG_WRITE 1 +#define CQSPI_INDIRECT_READ 2 +#define CQSPI_INDIRECT_WRITE 3 + +DECLARE_GLOBAL_DATA_PTR; + +static int cadence_spi_write_speed(struct udevice *bus, uint hz) +{ + struct cadence_spi_platdata *plat = bus->platdata; + struct cadence_spi_priv *priv = dev_get_priv(bus); + + cadence_qspi_apb_config_baudrate_div(priv->regbase, + CONFIG_CQSPI_REF_CLK, hz); + + /* Reconfigure delay timing if speed is changed. */ + cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz, + plat->tshsl_ns, plat->tsd2d_ns, + plat->tchsh_ns, plat->tslch_ns); + + return 0; +} + +/* Calibration sequence to determine the read data capture delay register */ +static int spi_calibration(struct udevice *bus) +{ + struct cadence_spi_platdata *plat = bus->platdata; + struct cadence_spi_priv *priv = dev_get_priv(bus); + void *base = priv->regbase; + u8 opcode_rdid = 0x9F; + unsigned int idcode = 0, temp = 0; + int err = 0, i, range_lo = -1, range_hi = -1; + + /* start with slowest clock (1 MHz) */ + cadence_spi_write_speed(bus, 1000000); + + /* configure the read data capture delay register to 0 */ + cadence_qspi_apb_readdata_capture(base, 1, 0); + + /* Enable QSPI */ + cadence_qspi_apb_controller_enable(base); + + /* read the ID which will be our golden value */ + err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid, + 3, (u8 *)&idcode); + if (err) { + puts("SF: Calibration failed (read)\n"); + return err; + } + + /* use back the intended clock and find low range */ + cadence_spi_write_speed(bus, plat->max_hz); + for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { + /* Disable QSPI */ + cadence_qspi_apb_controller_disable(base); + + /* reconfigure the read data capture delay register */ + cadence_qspi_apb_readdata_capture(base, 1, i); + + /* Enable back QSPI */ + cadence_qspi_apb_controller_enable(base); + + /* issue a RDID to get the ID value */ + err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid, + 3, (u8 *)&temp); + if (err) { + puts("SF: Calibration failed (read)\n"); + return err; + } + + /* search for range lo */ + if (range_lo == -1 && temp == idcode) { + range_lo = i; + continue; + } + + /* search for range hi */ + if (range_lo != -1 && temp != idcode) { + range_hi = i - 1; + break; + } + range_hi = i; + } + + if (range_lo == -1) { + puts("SF: Calibration failed (low range)\n"); + return err; + } + + /* Disable QSPI for subsequent initialization */ + cadence_qspi_apb_controller_disable(base); + + /* configure the final value for read data capture delay register */ + cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2); + debug("SF: Read data capture delay calibrated to %i (%i - %i)\n", + (range_hi + range_lo) / 2, range_lo, range_hi); + + /* just to ensure we do once only when speed or chip select change */ + priv->qspi_calibrated_hz = plat->max_hz; + priv->qspi_calibrated_cs = spi_chip_select(bus); + + return 0; +} + +static int cadence_spi_set_speed(struct udevice *bus, uint hz) +{ + struct cadence_spi_platdata *plat = bus->platdata; + struct cadence_spi_priv *priv = dev_get_priv(bus); + int err; + + /* Disable QSPI */ + cadence_qspi_apb_controller_disable(priv->regbase); + + cadence_spi_write_speed(bus, hz); + + /* Calibration required for different SCLK speed or chip select */ + if (priv->qspi_calibrated_hz != plat->max_hz || + priv->qspi_calibrated_cs != spi_chip_select(bus)) { + err = spi_calibration(bus); + if (err) + return err; + } + + /* Enable QSPI */ + cadence_qspi_apb_controller_enable(priv->regbase); + + debug("%s: speed=%d\n", __func__, hz); + + return 0; +} + +static int cadence_spi_probe(struct udevice *bus) +{ + struct cadence_spi_platdata *plat = bus->platdata; + struct cadence_spi_priv *priv = dev_get_priv(bus); + + priv->regbase = plat->regbase; + priv->ahbbase = plat->ahbbase; + + if (!priv->qspi_is_init) { + cadence_qspi_apb_controller_init(plat); + priv->qspi_is_init = 1; + } + + return 0; +} + +static int cadence_spi_set_mode(struct udevice *bus, uint mode) +{ + struct cadence_spi_priv *priv = dev_get_priv(bus); + unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0; + unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0; + + /* Disable QSPI */ + cadence_qspi_apb_controller_disable(priv->regbase); + + /* Set SPI mode */ + cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha); + + /* Enable QSPI */ + cadence_qspi_apb_controller_enable(priv->regbase); + + return 0; +} + +static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct cadence_spi_platdata *plat = bus->platdata; + struct cadence_spi_priv *priv = dev_get_priv(bus); + void *base = priv->regbase; + u8 *cmd_buf = priv->cmd_buf; + size_t data_bytes; + int err = 0; + u32 mode = CQSPI_STIG_WRITE; + + if (flags & SPI_XFER_BEGIN) { + /* copy command to local buffer */ + priv->cmd_len = bitlen / 8; + memcpy(cmd_buf, dout, priv->cmd_len); + } + + if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { + /* if start and end bit are set, the data bytes is 0. */ + data_bytes = 0; + } else { + data_bytes = bitlen / 8; + } + debug("%s: len=%d [bytes]\n", __func__, data_bytes); + + /* Set Chip select */ + cadence_qspi_apb_chipselect(base, spi_chip_select(dev), + CONFIG_CQSPI_DECODER); + + if ((flags & SPI_XFER_END) || (flags == 0)) { + if (priv->cmd_len == 0) { + printf("QSPI: Error, command is empty.\n"); + return -1; + } + + if (din && data_bytes) { + /* read */ + /* Use STIG if no address. */ + if (!CQSPI_IS_ADDR(priv->cmd_len)) + mode = CQSPI_STIG_READ; + else + mode = CQSPI_INDIRECT_READ; + } else if (dout && !(flags & SPI_XFER_BEGIN)) { + /* write */ + if (!CQSPI_IS_ADDR(priv->cmd_len)) + mode = CQSPI_STIG_WRITE; + else + mode = CQSPI_INDIRECT_WRITE; + } + + switch (mode) { + case CQSPI_STIG_READ: + err = cadence_qspi_apb_command_read( + base, priv->cmd_len, cmd_buf, + data_bytes, din); + + break; + case CQSPI_STIG_WRITE: + err = cadence_qspi_apb_command_write(base, + priv->cmd_len, cmd_buf, + data_bytes, dout); + break; + case CQSPI_INDIRECT_READ: + err = cadence_qspi_apb_indirect_read_setup(plat, + priv->cmd_len, cmd_buf); + if (!err) { + err = cadence_qspi_apb_indirect_read_execute + (plat, data_bytes, din); + } + break; + case CQSPI_INDIRECT_WRITE: + err = cadence_qspi_apb_indirect_write_setup + (plat, priv->cmd_len, cmd_buf); + if (!err) { + err = cadence_qspi_apb_indirect_write_execute + (plat, data_bytes, dout); + } + break; + default: + err = -1; + break; + } + + if (flags & SPI_XFER_END) { + /* clear command buffer */ + memset(cmd_buf, 0, sizeof(priv->cmd_buf)); + priv->cmd_len = 0; + } + } + + return err; +} + +static int cadence_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct cadence_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + int subnode; + u32 data[4]; + int ret; + + /* 2 base addresses are needed, lets get them from the DT */ + ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data)); + if (ret) { + printf("Error: Can't get base addresses (ret=%d)!\n", ret); + return -ENODEV; + } + + plat->regbase = (void *)data[0]; + plat->ahbbase = (void *)data[2]; + + /* Use 500KHz as a suitable default */ + plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + 500000); + + /* All other paramters are embedded in the child node */ + subnode = fdt_first_subnode(blob, node); + if (!subnode) { + printf("Error: subnode with SPI flash config missing!\n"); + return -ENODEV; + } + + /* Read other parameters from DT */ + plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256); + plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16); + plat->tshsl_ns = fdtdec_get_int(blob, subnode, "tshsl-ns", 200); + plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255); + plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20); + plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); + + debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", + __func__, plat->regbase, plat->ahbbase, plat->max_hz, + plat->page_size); + + return 0; +} + +static const struct dm_spi_ops cadence_spi_ops = { + .xfer = cadence_spi_xfer, + .set_speed = cadence_spi_set_speed, + .set_mode = cadence_spi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id cadence_spi_ids[] = { + { .compatible = "cadence,qspi" }, + { } +}; + +U_BOOT_DRIVER(cadence_spi) = { + .name = "cadence_spi", + .id = UCLASS_SPI, + .of_match = cadence_spi_ids, + .ops = &cadence_spi_ops, + .ofdata_to_platdata = cadence_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata), + .priv_auto_alloc_size = sizeof(struct cadence_spi_priv), + .per_child_auto_alloc_size = sizeof(struct spi_slave), + .probe = cadence_spi_probe, +}; diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h new file mode 100644 index 0000000..c9a6142 --- /dev/null +++ b/drivers/spi/cadence_qspi.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2012 + * Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CADENCE_QSPI_H__ +#define __CADENCE_QSPI_H__ + +#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0) + +#define CQSPI_NO_DECODER_MAX_CS 4 +#define CQSPI_DECODER_MAX_CS 16 +#define CQSPI_READ_CAPTURE_MAX_DELAY 16 + +struct cadence_spi_platdata { + unsigned int max_hz; + void *regbase; + void *ahbbase; + + u32 page_size; + u32 block_size; + u32 tshsl_ns; + u32 tsd2d_ns; + u32 tchsh_ns; + u32 tslch_ns; +}; + +struct cadence_spi_priv { + void *regbase; + void *ahbbase; + size_t cmd_len; + u8 cmd_buf[32]; + size_t data_len; + + int qspi_is_init; + unsigned int qspi_calibrated_hz; + unsigned int qspi_calibrated_cs; +}; + +/* Functions call declaration */ +void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat); +void cadence_qspi_apb_controller_enable(void *reg_base_addr); +void cadence_qspi_apb_controller_disable(void *reg_base_addr); + +int cadence_qspi_apb_command_read(void *reg_base_addr, + unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf); +int cadence_qspi_apb_command_write(void *reg_base_addr, + unsigned int cmdlen, const u8 *cmdbuf, + unsigned int txlen, const u8 *txbuf); + +int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, + unsigned int cmdlen, const u8 *cmdbuf); +int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, + unsigned int rxlen, u8 *rxbuf); +int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, + unsigned int cmdlen, const u8 *cmdbuf); +int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, + unsigned int txlen, const u8 *txbuf); + +void cadence_qspi_apb_chipselect(void *reg_base, + unsigned int chip_select, unsigned int decoder_enable); +void cadence_qspi_apb_set_clk_mode(void *reg_base_addr, + unsigned int clk_pol, unsigned int clk_pha); +void cadence_qspi_apb_config_baudrate_div(void *reg_base, + unsigned int ref_clk_hz, unsigned int sclk_hz); +void cadence_qspi_apb_delay(void *reg_base, + unsigned int ref_clk, unsigned int sclk_hz, + unsigned int tshsl_ns, unsigned int tsd2d_ns, + unsigned int tchsh_ns, unsigned int tslch_ns); +void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy); +void cadence_qspi_apb_readdata_capture(void *reg_base, + unsigned int bypass, unsigned int delay); + +#endif /* __CADENCE_QSPI_H__ */ diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c new file mode 100644 index 0000000..00a115f --- /dev/null +++ b/drivers/spi/cadence_qspi_apb.c @@ -0,0 +1,898 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of the Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include "cadence_qspi.h" + +#define CQSPI_REG_POLL_US (1) /* 1us */ +#define CQSPI_REG_RETRY (10000) +#define CQSPI_POLL_IDLE_RETRY (3) + +#define CQSPI_FIFO_WIDTH (4) + +/* Controller sram size in word */ +#define CQSPI_REG_SRAM_SIZE_WORD (128) +#define CQSPI_REG_SRAM_RESV_WORDS (2) +#define CQSPI_REG_SRAM_PARTITION_WR (1) +#define CQSPI_REG_SRAM_PARTITION_RD \ + (CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS) +#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) + +/* Transfer mode */ +#define CQSPI_INST_TYPE_SINGLE (0) +#define CQSPI_INST_TYPE_DUAL (1) +#define CQSPI_INST_TYPE_QUAD (2) + +#define CQSPI_STIG_DATA_LEN_MAX (8) +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF) + +#define CQSPI_DUMMY_CLKS_PER_BYTE (8) +#define CQSPI_DUMMY_BYTES_MAX (4) + + +#define CQSPI_REG_SRAM_FILL_THRESHOLD \ + ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH) +/**************************************************************************** + * Controller's configuration and status register (offset from QSPI_BASE) + ****************************************************************************/ +#define CQSPI_REG_CONFIG 0x00 +#define CQSPI_REG_CONFIG_CLK_POL_LSB 1 +#define CQSPI_REG_CONFIG_CLK_PHA_LSB 2 +#define CQSPI_REG_CONFIG_ENABLE_MASK (1 << 0) +#define CQSPI_REG_CONFIG_DIRECT_MASK (1 << 7) +#define CQSPI_REG_CONFIG_DECODE_MASK (1 << 9) +#define CQSPI_REG_CONFIG_XIP_IMM_MASK (1 << 18) +#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 +#define CQSPI_REG_CONFIG_BAUD_LSB 19 +#define CQSPI_REG_CONFIG_IDLE_LSB 31 +#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF +#define CQSPI_REG_CONFIG_BAUD_MASK 0xF + +#define CQSPI_REG_RD_INSTR 0x04 +#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 +#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 +#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 +#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F + +#define CQSPI_REG_WR_INSTR 0x08 +#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 + +#define CQSPI_REG_DELAY 0x0C +#define CQSPI_REG_DELAY_TSLCH_LSB 0 +#define CQSPI_REG_DELAY_TCHSH_LSB 8 +#define CQSPI_REG_DELAY_TSD2D_LSB 16 +#define CQSPI_REG_DELAY_TSHSL_LSB 24 +#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF +#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF +#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF +#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF + +#define CQSPI_READLCAPTURE 0x10 +#define CQSPI_READLCAPTURE_BYPASS_LSB 0 +#define CQSPI_READLCAPTURE_DELAY_LSB 1 +#define CQSPI_READLCAPTURE_DELAY_MASK 0xF + +#define CQSPI_REG_SIZE 0x14 +#define CQSPI_REG_SIZE_ADDRESS_LSB 0 +#define CQSPI_REG_SIZE_PAGE_LSB 4 +#define CQSPI_REG_SIZE_BLOCK_LSB 16 +#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF +#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF +#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F + +#define CQSPI_REG_SRAMPARTITION 0x18 +#define CQSPI_REG_INDIRECTTRIGGER 0x1C + +#define CQSPI_REG_REMAP 0x24 +#define CQSPI_REG_MODE_BIT 0x28 + +#define CQSPI_REG_SDRAMLEVEL 0x2C +#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 +#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 +#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF +#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF + +#define CQSPI_REG_IRQSTATUS 0x40 +#define CQSPI_REG_IRQMASK 0x44 + +#define CQSPI_REG_INDIRECTRD 0x60 +#define CQSPI_REG_INDIRECTRD_START_MASK (1 << 0) +#define CQSPI_REG_INDIRECTRD_CANCEL_MASK (1 << 1) +#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK (1 << 2) +#define CQSPI_REG_INDIRECTRD_DONE_MASK (1 << 5) + +#define CQSPI_REG_INDIRECTRDWATERMARK 0x64 +#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 +#define CQSPI_REG_INDIRECTRDBYTES 0x6C + +#define CQSPI_REG_CMDCTRL 0x90 +#define CQSPI_REG_CMDCTRL_EXECUTE_MASK (1 << 0) +#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK (1 << 1) +#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 +#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 +#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 +#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 +#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 +#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 +#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 +#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F +#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 +#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 +#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF + +#define CQSPI_REG_INDIRECTWR 0x70 +#define CQSPI_REG_INDIRECTWR_START_MASK (1 << 0) +#define CQSPI_REG_INDIRECTWR_CANCEL_MASK (1 << 1) +#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK (1 << 2) +#define CQSPI_REG_INDIRECTWR_DONE_MASK (1 << 5) + +#define CQSPI_REG_INDIRECTWRWATERMARK 0x74 +#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 +#define CQSPI_REG_INDIRECTWRBYTES 0x7C + +#define CQSPI_REG_CMDADDRESS 0x94 +#define CQSPI_REG_CMDREADDATALOWER 0xA0 +#define CQSPI_REG_CMDREADDATAUPPER 0xA4 +#define CQSPI_REG_CMDWRITEDATALOWER 0xA8 +#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC + +#define CQSPI_REG_IS_IDLE(base) \ + ((readl(base + CQSPI_REG_CONFIG) >> \ + CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) + +#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \ + ((((tdelay_ns) - (tsclk_ns)) / (tref_ns))) + +#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ + (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ + CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK) + +#define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ + (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ + CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK) + +static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf, + unsigned int addr_width) +{ + unsigned int addr; + + addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2]; + + if (addr_width == 4) + addr = (addr << 8) | addr_buf[3]; + + return addr; +} + +static void cadence_qspi_apb_read_fifo_data(void *dest, + const void *src_ahb_addr, unsigned int bytes) +{ + unsigned int temp; + int remaining = bytes; + unsigned int *dest_ptr = (unsigned int *)dest; + unsigned int *src_ptr = (unsigned int *)src_ahb_addr; + + while (remaining > 0) { + if (remaining >= CQSPI_FIFO_WIDTH) { + *dest_ptr = readl(src_ptr); + remaining -= CQSPI_FIFO_WIDTH; + } else { + /* dangling bytes */ + temp = readl(src_ptr); + memcpy(dest_ptr, &temp, remaining); + break; + } + dest_ptr++; + } + + return; +} + +static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr, + const void *src, unsigned int bytes) +{ + unsigned int temp; + int remaining = bytes; + unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr; + unsigned int *src_ptr = (unsigned int *)src; + + while (remaining > 0) { + if (remaining >= CQSPI_FIFO_WIDTH) { + writel(*src_ptr, dest_ptr); + remaining -= sizeof(unsigned int); + } else { + /* dangling bytes */ + memcpy(&temp, src_ptr, remaining); + writel(temp, dest_ptr); + break; + } + src_ptr++; + } + + return; +} + +/* Read from SRAM FIFO with polling SRAM fill level. */ +static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr, + const void *src_addr, unsigned int num_bytes) +{ + unsigned int remaining = num_bytes; + unsigned int retry; + unsigned int sram_level = 0; + unsigned char *dest = (unsigned char *)dest_addr; + + while (remaining > 0) { + retry = CQSPI_REG_RETRY; + while (retry--) { + sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base); + if (sram_level) + break; + udelay(1); + } + + if (!retry) { + printf("QSPI: No receive data after polling for %d times\n", + CQSPI_REG_RETRY); + return -1; + } + + sram_level *= CQSPI_FIFO_WIDTH; + sram_level = sram_level > remaining ? remaining : sram_level; + + /* Read data from FIFO. */ + cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level); + dest += sram_level; + remaining -= sram_level; + udelay(1); + } + return 0; +} + +/* Write to SRAM FIFO with polling SRAM fill level. */ +static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat, + const void *src_addr, unsigned int num_bytes) +{ + const void *reg_base = plat->regbase; + void *dest_addr = plat->ahbbase; + unsigned int retry = CQSPI_REG_RETRY; + unsigned int sram_level; + unsigned int wr_bytes; + unsigned char *src = (unsigned char *)src_addr; + int remaining = num_bytes; + unsigned int page_size = plat->page_size; + unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS; + + while (remaining > 0) { + retry = CQSPI_REG_RETRY; + while (retry--) { + sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base); + if (sram_level <= sram_threshold_words) + break; + } + if (!retry) { + printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)", + sram_level, sram_threshold_words); + return -1; + } + /* Write a page or remaining bytes. */ + wr_bytes = (remaining > page_size) ? + page_size : remaining; + + cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes); + src += wr_bytes; + remaining -= wr_bytes; + } + + return 0; +} + +void cadence_qspi_apb_controller_enable(void *reg_base) +{ + unsigned int reg; + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg |= CQSPI_REG_CONFIG_ENABLE_MASK; + writel(reg, reg_base + CQSPI_REG_CONFIG); + return; +} + +void cadence_qspi_apb_controller_disable(void *reg_base) +{ + unsigned int reg; + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; + writel(reg, reg_base + CQSPI_REG_CONFIG); + return; +} + +/* Return 1 if idle, otherwise return 0 (busy). */ +static unsigned int cadence_qspi_wait_idle(void *reg_base) +{ + unsigned int start, count = 0; + /* timeout in unit of ms */ + unsigned int timeout = 5000; + + start = get_timer(0); + for ( ; get_timer(start) < timeout ; ) { + if (CQSPI_REG_IS_IDLE(reg_base)) + count++; + else + count = 0; + /* + * Ensure the QSPI controller is in true idle state after + * reading back the same idle status consecutively + */ + if (count >= CQSPI_POLL_IDLE_RETRY) + return 1; + } + + /* Timeout, still in busy mode. */ + printf("QSPI: QSPI is still busy after poll for %d times.\n", + CQSPI_REG_RETRY); + return 0; +} + +void cadence_qspi_apb_readdata_capture(void *reg_base, + unsigned int bypass, unsigned int delay) +{ + unsigned int reg; + cadence_qspi_apb_controller_disable(reg_base); + + reg = readl(reg_base + CQSPI_READLCAPTURE); + + if (bypass) + reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB); + else + reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB); + + reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK + << CQSPI_READLCAPTURE_DELAY_LSB); + + reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK) + << CQSPI_READLCAPTURE_DELAY_LSB); + + writel(reg, reg_base + CQSPI_READLCAPTURE); + + cadence_qspi_apb_controller_enable(reg_base); + return; +} + +void cadence_qspi_apb_config_baudrate_div(void *reg_base, + unsigned int ref_clk_hz, unsigned int sclk_hz) +{ + unsigned int reg; + unsigned int div; + + cadence_qspi_apb_controller_disable(reg_base); + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); + + div = ref_clk_hz / sclk_hz; + + if (div > 32) + div = 32; + + /* Check if even number. */ + if ((div & 1)) { + div = (div / 2); + } else { + if (ref_clk_hz % sclk_hz) + /* ensure generated SCLK doesn't exceed user + specified sclk_hz */ + div = (div / 2); + else + div = (div / 2) - 1; + } + + debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__, + ref_clk_hz, sclk_hz, div); + + div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; + reg |= div; + writel(reg, reg_base + CQSPI_REG_CONFIG); + + cadence_qspi_apb_controller_enable(reg_base); + return; +} + +void cadence_qspi_apb_set_clk_mode(void *reg_base, + unsigned int clk_pol, unsigned int clk_pha) +{ + unsigned int reg; + + cadence_qspi_apb_controller_disable(reg_base); + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg &= ~(1 << + (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB)); + + reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB); + reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB); + + writel(reg, reg_base + CQSPI_REG_CONFIG); + + cadence_qspi_apb_controller_enable(reg_base); + return; +} + +void cadence_qspi_apb_chipselect(void *reg_base, + unsigned int chip_select, unsigned int decoder_enable) +{ + unsigned int reg; + + cadence_qspi_apb_controller_disable(reg_base); + + debug("%s : chipselect %d decode %d\n", __func__, chip_select, + decoder_enable); + + reg = readl(reg_base + CQSPI_REG_CONFIG); + /* docoder */ + if (decoder_enable) { + reg |= CQSPI_REG_CONFIG_DECODE_MASK; + } else { + reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; + /* Convert CS if without decoder. + * CS0 to 4b'1110 + * CS1 to 4b'1101 + * CS2 to 4b'1011 + * CS3 to 4b'0111 + */ + chip_select = 0xF & ~(1 << chip_select); + } + + reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK + << CQSPI_REG_CONFIG_CHIPSELECT_LSB); + reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) + << CQSPI_REG_CONFIG_CHIPSELECT_LSB; + writel(reg, reg_base + CQSPI_REG_CONFIG); + + cadence_qspi_apb_controller_enable(reg_base); + return; +} + +void cadence_qspi_apb_delay(void *reg_base, + unsigned int ref_clk, unsigned int sclk_hz, + unsigned int tshsl_ns, unsigned int tsd2d_ns, + unsigned int tchsh_ns, unsigned int tslch_ns) +{ + unsigned int ref_clk_ns; + unsigned int sclk_ns; + unsigned int tshsl, tchsh, tslch, tsd2d; + unsigned int reg; + + cadence_qspi_apb_controller_disable(reg_base); + + /* Convert to ns. */ + ref_clk_ns = (1000000000) / ref_clk; + + /* Convert to ns. */ + sclk_ns = (1000000000) / sclk_hz; + + /* Plus 1 to round up 1 clock cycle. */ + tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1; + tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1; + tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1; + tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1; + + reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK) + << CQSPI_REG_DELAY_TSHSL_LSB); + reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK) + << CQSPI_REG_DELAY_TCHSH_LSB); + reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK) + << CQSPI_REG_DELAY_TSLCH_LSB); + reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) + << CQSPI_REG_DELAY_TSD2D_LSB); + writel(reg, reg_base + CQSPI_REG_DELAY); + + cadence_qspi_apb_controller_enable(reg_base); + return; +} + +void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) +{ + unsigned reg; + + cadence_qspi_apb_controller_disable(plat->regbase); + + /* Configure the device size and address bytes */ + reg = readl(plat->regbase + CQSPI_REG_SIZE); + /* Clear the previous value */ + reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); + reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); + reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB); + reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB); + writel(reg, plat->regbase + CQSPI_REG_SIZE); + + /* Configure the remap address register, no remap */ + writel(0, plat->regbase + CQSPI_REG_REMAP); + + /* Disable all interrupts */ + writel(0, plat->regbase + CQSPI_REG_IRQMASK); + + cadence_qspi_apb_controller_enable(plat->regbase); + return; +} + +static int cadence_qspi_apb_exec_flash_cmd(void *reg_base, + unsigned int reg) +{ + unsigned int retry = CQSPI_REG_RETRY; + + /* Write the CMDCTRL without start execution. */ + writel(reg, reg_base + CQSPI_REG_CMDCTRL); + /* Start execute */ + reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; + writel(reg, reg_base + CQSPI_REG_CMDCTRL); + + while (retry--) { + reg = readl(reg_base + CQSPI_REG_CMDCTRL); + if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0) + break; + udelay(1); + } + + if (!retry) { + printf("QSPI: flash command execution timeout\n"); + return -EIO; + } + + /* Polling QSPI idle status. */ + if (!cadence_qspi_wait_idle(reg_base)) + return -EIO; + + return 0; +} + +/* For command RDID, RDSR. */ +int cadence_qspi_apb_command_read(void *reg_base, + unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, + u8 *rxbuf) +{ + unsigned int reg; + unsigned int read_len; + int status; + + if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) { + printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n", + cmdlen, rxlen); + return -EINVAL; + } + + reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; + + reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); + + /* 0 means 1 byte. */ + reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) + << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); + status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg); + if (status != 0) + return status; + + reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); + + /* Put the read value into rx_buf */ + read_len = (rxlen > 4) ? 4 : rxlen; + memcpy(rxbuf, ®, read_len); + rxbuf += read_len; + + if (rxlen > 4) { + reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); + + read_len = rxlen - read_len; + memcpy(rxbuf, ®, read_len); + } + return 0; +} + +/* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */ +int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen, + const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf) +{ + unsigned int reg = 0; + unsigned int addr_value; + unsigned int wr_data; + unsigned int wr_len; + + if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) { + printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n", + cmdlen, txlen); + return -EINVAL; + } + + reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; + + if (cmdlen == 4 || cmdlen == 5) { + /* Command with address */ + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + /* Number of bytes to write. */ + reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) + << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; + /* Get address */ + addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], + cmdlen >= 5 ? 4 : 3); + + writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS); + } + + if (txlen) { + /* writing data = yes */ + reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); + reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) + << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; + + wr_len = txlen > 4 ? 4 : txlen; + memcpy(&wr_data, txbuf, wr_len); + writel(wr_data, reg_base + + CQSPI_REG_CMDWRITEDATALOWER); + + if (txlen > 4) { + txbuf += wr_len; + wr_len = txlen - wr_len; + memcpy(&wr_data, txbuf, wr_len); + writel(wr_data, reg_base + + CQSPI_REG_CMDWRITEDATAUPPER); + } + } + + /* Execute the command */ + return cadence_qspi_apb_exec_flash_cmd(reg_base, reg); +} + +/* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */ +int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, + unsigned int cmdlen, const u8 *cmdbuf) +{ + unsigned int reg; + unsigned int rd_reg; + unsigned int addr_value; + unsigned int dummy_clk; + unsigned int dummy_bytes; + unsigned int addr_bytes; + + /* + * Identify addr_byte. All NOR flash device drivers are using fast read + * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte. + * With that, the length is in value of 5 or 6. Only FRAM chip from + * ramtron using normal read (which won't need dummy byte). + * Unlikely NOR flash using normal read due to performance issue. + */ + if (cmdlen >= 5) + /* to cater fast read where cmd + addr + dummy */ + addr_bytes = cmdlen - 2; + else + /* for normal read (only ramtron as of now) */ + addr_bytes = cmdlen - 1; + + /* Setup the indirect trigger address */ + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + plat->regbase + CQSPI_REG_INDIRECTTRIGGER); + + /* Configure SRAM partition for read. */ + writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase + + CQSPI_REG_SRAMPARTITION); + + /* Configure the opcode */ + rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB; + +#if (CONFIG_SPI_FLASH_QUAD == 1) + /* Instruction and address at DQ0, data at DQ0-3. */ + rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; +#endif + + /* Get address */ + addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); + writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); + + /* The remaining lenght is dummy bytes. */ + dummy_bytes = cmdlen - addr_bytes - 1; + if (dummy_bytes) { + if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX) + dummy_bytes = CQSPI_DUMMY_BYTES_MAX; + + rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB); +#if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD) + writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT); +#else + writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT); +#endif + + /* Convert to clock cycles. */ + dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE; + /* Need to minus the mode byte (8 clocks). */ + dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE; + + if (dummy_clk) + rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) + << CQSPI_REG_RD_INSTR_DUMMY_LSB; + } + + writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR); + + /* set device size */ + reg = readl(plat->regbase + CQSPI_REG_SIZE); + reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; + reg |= (addr_bytes - 1); + writel(reg, plat->regbase + CQSPI_REG_SIZE); + return 0; +} + +int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, + unsigned int rxlen, u8 *rxbuf) +{ + unsigned int reg; + + writel(rxlen, plat->regbase + CQSPI_REG_INDIRECTRDBYTES); + + /* Start the indirect read transfer */ + writel(CQSPI_REG_INDIRECTRD_START_MASK, + plat->regbase + CQSPI_REG_INDIRECTRD); + + if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf, + (const void *)plat->ahbbase, rxlen)) + goto failrd; + + /* Check flash indirect controller */ + reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD); + if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) { + reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD); + printf("QSPI: indirect completion status error with reg 0x%08x\n", + reg); + goto failrd; + } + + /* Clear indirect completion status */ + writel(CQSPI_REG_INDIRECTRD_DONE_MASK, + plat->regbase + CQSPI_REG_INDIRECTRD); + return 0; + +failrd: + /* Cancel the indirect read */ + writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, + plat->regbase + CQSPI_REG_INDIRECTRD); + return -1; +} + +/* Opcode + Address (3/4 bytes) */ +int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, + unsigned int cmdlen, const u8 *cmdbuf) +{ + unsigned int reg; + unsigned int addr_bytes = cmdlen > 4 ? 4 : 3; + + if (cmdlen < 4 || cmdbuf == NULL) { + printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n", + cmdlen, (unsigned int)cmdbuf); + return -EINVAL; + } + /* Setup the indirect trigger address */ + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + plat->regbase + CQSPI_REG_INDIRECTTRIGGER); + + writel(CQSPI_REG_SRAM_PARTITION_WR, + plat->regbase + CQSPI_REG_SRAMPARTITION); + + /* Configure the opcode */ + reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB; + writel(reg, plat->regbase + CQSPI_REG_WR_INSTR); + + /* Setup write address. */ + reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); + writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR); + + reg = readl(plat->regbase + CQSPI_REG_SIZE); + reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; + reg |= (addr_bytes - 1); + writel(reg, plat->regbase + CQSPI_REG_SIZE); + return 0; +} + +int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, + unsigned int txlen, const u8 *txbuf) +{ + unsigned int reg = 0; + unsigned int retry; + + /* Configure the indirect read transfer bytes */ + writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES); + + /* Start the indirect write transfer */ + writel(CQSPI_REG_INDIRECTWR_START_MASK, + plat->regbase + CQSPI_REG_INDIRECTWR); + + if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen)) + goto failwr; + + /* Wait until last write is completed (FIFO empty) */ + retry = CQSPI_REG_RETRY; + while (retry--) { + reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase); + if (reg == 0) + break; + + udelay(1); + } + + if (reg != 0) { + printf("QSPI: timeout for indirect write\n"); + goto failwr; + } + + /* Check flash indirect controller status */ + retry = CQSPI_REG_RETRY; + while (retry--) { + reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR); + if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK) + break; + udelay(1); + } + + if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) { + printf("QSPI: indirect completion status error with reg 0x%08x\n", + reg); + goto failwr; + } + + /* Clear indirect completion status */ + writel(CQSPI_REG_INDIRECTWR_DONE_MASK, + plat->regbase + CQSPI_REG_INDIRECTWR); + return 0; + +failwr: + /* Cancel the indirect write */ + writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, + plat->regbase + CQSPI_REG_INDIRECTWR); + return -1; +} + +void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy) +{ + unsigned int reg; + + /* enter XiP mode immediately and enable direct mode */ + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg |= CQSPI_REG_CONFIG_ENABLE_MASK; + reg |= CQSPI_REG_CONFIG_DIRECT_MASK; + reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK; + writel(reg, reg_base + CQSPI_REG_CONFIG); + + /* keep the XiP mode */ + writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT); + + /* Enable mode bit at devrd */ + reg = readl(reg_base + CQSPI_REG_RD_INSTR); + reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB); + writel(reg, reg_base + CQSPI_REG_RD_INSTR); +} diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c new file mode 100644 index 0000000..98c9f03 --- /dev/null +++ b/drivers/spi/designware_spi.c @@ -0,0 +1,426 @@ +/* + * Designware master SPI core controller driver + * + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * Very loosely based on the Linux driver: + * drivers/spi/spi-dw.c, which is: + * Copyright (c) 2009, Intel Corporation. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <malloc.h> +#include <spi.h> +#include <fdtdec.h> +#include <linux/compat.h> +#include <asm/io.h> +#include <asm/arch/clock_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Register offsets */ +#define DW_SPI_CTRL0 0x00 +#define DW_SPI_CTRL1 0x04 +#define DW_SPI_SSIENR 0x08 +#define DW_SPI_MWCR 0x0c +#define DW_SPI_SER 0x10 +#define DW_SPI_BAUDR 0x14 +#define DW_SPI_TXFLTR 0x18 +#define DW_SPI_RXFLTR 0x1c +#define DW_SPI_TXFLR 0x20 +#define DW_SPI_RXFLR 0x24 +#define DW_SPI_SR 0x28 +#define DW_SPI_IMR 0x2c +#define DW_SPI_ISR 0x30 +#define DW_SPI_RISR 0x34 +#define DW_SPI_TXOICR 0x38 +#define DW_SPI_RXOICR 0x3c +#define DW_SPI_RXUICR 0x40 +#define DW_SPI_MSTICR 0x44 +#define DW_SPI_ICR 0x48 +#define DW_SPI_DMACR 0x4c +#define DW_SPI_DMATDLR 0x50 +#define DW_SPI_DMARDLR 0x54 +#define DW_SPI_IDR 0x58 +#define DW_SPI_VERSION 0x5c +#define DW_SPI_DR 0x60 + +/* Bit fields in CTRLR0 */ +#define SPI_DFS_OFFSET 0 + +#define SPI_FRF_OFFSET 4 +#define SPI_FRF_SPI 0x0 +#define SPI_FRF_SSP 0x1 +#define SPI_FRF_MICROWIRE 0x2 +#define SPI_FRF_RESV 0x3 + +#define SPI_MODE_OFFSET 6 +#define SPI_SCPH_OFFSET 6 +#define SPI_SCOL_OFFSET 7 + +#define SPI_TMOD_OFFSET 8 +#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) +#define SPI_TMOD_TR 0x0 /* xmit & recv */ +#define SPI_TMOD_TO 0x1 /* xmit only */ +#define SPI_TMOD_RO 0x2 /* recv only */ +#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ + +#define SPI_SLVOE_OFFSET 10 +#define SPI_SRL_OFFSET 11 +#define SPI_CFS_OFFSET 12 + +/* Bit fields in SR, 7 bits */ +#define SR_MASK 0x7f /* cover 7 bits */ +#define SR_BUSY (1 << 0) +#define SR_TF_NOT_FULL (1 << 1) +#define SR_TF_EMPT (1 << 2) +#define SR_RF_NOT_EMPT (1 << 3) +#define SR_RF_FULL (1 << 4) +#define SR_TX_ERR (1 << 5) +#define SR_DCOL (1 << 6) + +#define RX_TIMEOUT 1000 /* timeout in ms */ + +struct dw_spi_platdata { + s32 frequency; /* Default clock frequency, -1 for none */ + void __iomem *regs; +}; + +struct dw_spi_priv { + void __iomem *regs; + unsigned int freq; /* Default frequency */ + unsigned int mode; + + int bits_per_word; + u8 cs; /* chip select pin */ + u8 tmode; /* TR/TO/RO/EEPROM */ + u8 type; /* SPI/SSP/MicroWire */ + int len; + + u32 fifo_len; /* depth of the FIFO buffer */ + void *tx; + void *tx_end; + void *rx; + void *rx_end; +}; + +static inline u32 dw_readl(struct dw_spi_priv *priv, u32 offset) +{ + return __raw_readl(priv->regs + offset); +} + +static inline void dw_writel(struct dw_spi_priv *priv, u32 offset, u32 val) +{ + __raw_writel(val, priv->regs + offset); +} + +static inline u16 dw_readw(struct dw_spi_priv *priv, u32 offset) +{ + return __raw_readw(priv->regs + offset); +} + +static inline void dw_writew(struct dw_spi_priv *priv, u32 offset, u16 val) +{ + __raw_writew(val, priv->regs + offset); +} + +static int dw_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct dw_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + + plat->regs = (struct dw_spi *)fdtdec_get_addr(blob, node, "reg"); + + /* Use 500KHz as a suitable default */ + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", + 500000); + debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs, + plat->frequency); + + return 0; +} + +static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable) +{ + dw_writel(priv, DW_SPI_SSIENR, (enable ? 1 : 0)); +} + +/* Restart the controller, disable all interrupts, clean rx fifo */ +static void spi_hw_init(struct dw_spi_priv *priv) +{ + spi_enable_chip(priv, 0); + dw_writel(priv, DW_SPI_IMR, 0xff); + spi_enable_chip(priv, 1); + + /* + * Try to detect the FIFO depth if not set by interface driver, + * the depth could be from 2 to 256 from HW spec + */ + if (!priv->fifo_len) { + u32 fifo; + + for (fifo = 2; fifo <= 257; fifo++) { + dw_writew(priv, DW_SPI_TXFLTR, fifo); + if (fifo != dw_readw(priv, DW_SPI_TXFLTR)) + break; + } + + priv->fifo_len = (fifo == 257) ? 0 : fifo; + dw_writew(priv, DW_SPI_TXFLTR, 0); + } + debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); +} + +static int dw_spi_probe(struct udevice *bus) +{ + struct dw_spi_platdata *plat = dev_get_platdata(bus); + struct dw_spi_priv *priv = dev_get_priv(bus); + + priv->regs = plat->regs; + priv->freq = plat->frequency; + + /* Currently only bits_per_word == 8 supported */ + priv->bits_per_word = 8; + + priv->tmode = 0; /* Tx & Rx */ + + /* Basic HW init */ + spi_hw_init(priv); + + return 0; +} + +/* Return the max entries we can fill into tx fifo */ +static inline u32 tx_max(struct dw_spi_priv *priv) +{ + u32 tx_left, tx_room, rxtx_gap; + + tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3); + tx_room = priv->fifo_len - dw_readw(priv, DW_SPI_TXFLR); + + /* + * Another concern is about the tx/rx mismatch, we + * thought about using (priv->fifo_len - rxflr - txflr) as + * one maximum value for tx, but it doesn't cover the + * data which is out of tx/rx fifo and inside the + * shift registers. So a control from sw point of + * view is taken. + */ + rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) / + (priv->bits_per_word >> 3); + + return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap)); +} + +/* Return the max entries we should read out of rx fifo */ +static inline u32 rx_max(struct dw_spi_priv *priv) +{ + u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3); + + return min_t(u32, rx_left, dw_readw(priv, DW_SPI_RXFLR)); +} + +static void dw_writer(struct dw_spi_priv *priv) +{ + u32 max = tx_max(priv); + u16 txw = 0; + + while (max--) { + /* Set the tx word if the transfer's original "tx" is not null */ + if (priv->tx_end - priv->len) { + if (priv->bits_per_word == 8) + txw = *(u8 *)(priv->tx); + else + txw = *(u16 *)(priv->tx); + } + dw_writew(priv, DW_SPI_DR, txw); + debug("%s: tx=0x%02x\n", __func__, txw); + priv->tx += priv->bits_per_word >> 3; + } +} + +static int dw_reader(struct dw_spi_priv *priv) +{ + unsigned start = get_timer(0); + u32 max; + u16 rxw; + + /* Wait for rx data to be ready */ + while (rx_max(priv) == 0) { + if (get_timer(start) > RX_TIMEOUT) + return -ETIMEDOUT; + } + + max = rx_max(priv); + + while (max--) { + rxw = dw_readw(priv, DW_SPI_DR); + debug("%s: rx=0x%02x\n", __func__, rxw); + + /* + * Care about rx only if the transfer's original "rx" is + * not null + */ + if (priv->rx_end - priv->len) { + if (priv->bits_per_word == 8) + *(u8 *)(priv->rx) = rxw; + else + *(u16 *)(priv->rx) = rxw; + } + priv->rx += priv->bits_per_word >> 3; + } + + return 0; +} + +static int poll_transfer(struct dw_spi_priv *priv) +{ + int ret; + + do { + dw_writer(priv); + ret = dw_reader(priv); + if (ret < 0) + return ret; + } while (priv->rx_end > priv->rx); + + return 0; +} + +static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct dw_spi_priv *priv = dev_get_priv(bus); + const u8 *tx = dout; + u8 *rx = din; + int ret = 0; + u32 cr0 = 0; + u32 cs; + + /* spi core configured to do 8 bit transfers */ + if (bitlen % 8) { + debug("Non byte aligned SPI transfer.\n"); + return -1; + } + + cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) | + (priv->mode << SPI_MODE_OFFSET) | + (priv->tmode << SPI_TMOD_OFFSET); + + if (rx && tx) + priv->tmode = SPI_TMOD_TR; + else if (rx) + priv->tmode = SPI_TMOD_RO; + else + priv->tmode = SPI_TMOD_TO; + + cr0 &= ~SPI_TMOD_MASK; + cr0 |= (priv->tmode << SPI_TMOD_OFFSET); + + priv->len = bitlen >> 3; + debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len); + + priv->tx = (void *)tx; + priv->tx_end = priv->tx + priv->len; + priv->rx = rx; + priv->rx_end = priv->rx + priv->len; + + /* Disable controller before writing control registers */ + spi_enable_chip(priv, 0); + + debug("%s: cr0=%08x\n", __func__, cr0); + /* Reprogram cr0 only if changed */ + if (dw_readw(priv, DW_SPI_CTRL0) != cr0) + dw_writew(priv, DW_SPI_CTRL0, cr0); + + /* + * Configure the desired SS (slave select 0...3) in the controller + * The DW SPI controller will activate and deactivate this CS + * automatically. So no cs_activate() etc is needed in this driver. + */ + cs = spi_chip_select(dev); + dw_writel(priv, DW_SPI_SER, 1 << cs); + + /* Enable controller after writing control registers */ + spi_enable_chip(priv, 1); + + /* Start transfer in a polling loop */ + ret = poll_transfer(priv); + + return ret; +} + +static int dw_spi_set_speed(struct udevice *bus, uint speed) +{ + struct dw_spi_platdata *plat = bus->platdata; + struct dw_spi_priv *priv = dev_get_priv(bus); + u16 clk_div; + + if (speed > plat->frequency) + speed = plat->frequency; + + /* Disable controller before writing control registers */ + spi_enable_chip(priv, 0); + + /* clk_div doesn't support odd number */ + clk_div = cm_get_spi_controller_clk_hz() / speed; + clk_div = (clk_div + 1) & 0xfffe; + dw_writel(priv, DW_SPI_BAUDR, clk_div); + + /* Enable controller after writing control registers */ + spi_enable_chip(priv, 1); + + priv->freq = speed; + debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs, + priv->freq, clk_div); + + return 0; +} + +static int dw_spi_set_mode(struct udevice *bus, uint mode) +{ + struct dw_spi_priv *priv = dev_get_priv(bus); + + /* + * Can't set mode yet. Since this depends on if rx, tx, or + * rx & tx is requested. So we have to defer this to the + * real transfer function. + */ + priv->mode = mode; + debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); + + return 0; +} + +static const struct dm_spi_ops dw_spi_ops = { + .xfer = dw_spi_xfer, + .set_speed = dw_spi_set_speed, + .set_mode = dw_spi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id dw_spi_ids[] = { + { .compatible = "snps,dw-spi-mmio" }, + { } +}; + +U_BOOT_DRIVER(dw_spi) = { + .name = "dw_spi", + .id = UCLASS_SPI, + .of_match = dw_spi_ids, + .ops = &dw_spi_ops, + .ofdata_to_platdata = dw_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata), + .priv_auto_alloc_size = sizeof(struct dw_spi_priv), + .per_child_auto_alloc_size = sizeof(struct spi_slave), + .probe = dw_spi_probe, +}; diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 9e8e319..838a0b1 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -641,6 +641,14 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE #endif #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #ifdef CONFIG_PHYS_64BIT @@ -649,6 +657,14 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index adb8146..eeb0671 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -11,6 +11,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifdef CONFIG_BSC9131RDB #define CONFIG_BSC9131 #define CONFIG_NAND_FSL_IFC diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 2722a32..e8a8d29 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -11,6 +11,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifdef CONFIG_BSC9132QDS #define CONFIG_BSC9132 #endif diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 2ce186e..a8b7817 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -347,9 +347,25 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 /* For FM */ #define CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 2e11aaa..d8d30bb 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -13,6 +13,8 @@ #define CONFIG_P2041RDB #define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_PPC_P2041 #ifdef CONFIG_RAMBOOT_PBL @@ -489,6 +491,14 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE #endif #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 #ifdef CONFIG_PHYS_64BIT @@ -497,6 +507,14 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 78ed243..c2bdbb9 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -720,7 +720,7 @@ unsigned long get_board_ddr_clk(void); /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 25 +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull @@ -728,7 +728,15 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE #endif #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_NUM_PORTALS 25 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull @@ -736,6 +744,14 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 6f1fcd6..82b669b 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -677,7 +677,7 @@ unsigned long get_board_ddr_clk(void); /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 25 +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull @@ -685,7 +685,15 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE #endif #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_NUM_PORTALS 25 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull @@ -693,6 +701,14 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 6b396bb..b70bdfe 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -605,14 +605,30 @@ unsigned long get_board_ddr_clk(void); /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 25 +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_NUM_PORTALS 25 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 1eb1371..57cdf72 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -104,7 +104,10 @@ /* support deep sleep */ #define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) +#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_SILENT_CONSOLE +#endif #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff40000 @@ -636,14 +639,30 @@ /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 25 +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_NUM_PORTALS 25 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index d1fe78e..ff6d2c1 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -634,10 +634,26 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 47b3bd5..db6b42e 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -567,10 +567,26 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h index 53c69b0..e8ba5d6 100644 --- a/include/configs/T4240EMU.h +++ b/include/configs/T4240EMU.h @@ -85,10 +85,26 @@ #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 1e0f5ec..dd7d52f 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -417,10 +417,26 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index db03993..b644a6c 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -12,6 +12,8 @@ #define CONFIG_T4240RDB #define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 @@ -577,10 +579,26 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 72b7efa..225ffdd 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -495,6 +495,14 @@ #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE #endif #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 #ifdef CONFIG_PHYS_64BIT @@ -503,6 +511,14 @@ #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 864e5f1..949b3da 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -339,10 +339,26 @@ int get_scl(void); #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c4ac94d..6bb9473 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -159,7 +159,7 @@ #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ #endif - /* +/* * I2C support */ #define CONFIG_SYS_I2C @@ -187,6 +187,37 @@ unsigned int cm_get_l4_sp_clk_hz(void); #define CONFIG_CMD_I2C /* + * QSPI support + */ +#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ +#define CONFIG_CMD_DM +#define CONFIG_DM +#define CONFIG_DM_SPI +#define CONFIG_DM_SPI_FLASH +#define CONFIG_CADENCE_QSPI +/* Enable multiple SPI NOR flash manufacturers */ +#define CONFIG_SPI_FLASH /* SPI flash subsystem */ +#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ +#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */ +#define CONFIG_SPI_FLASH_MTD +/* QSPI reference clock */ +#ifndef __ASSEMBLY__ +unsigned int cm_get_qspi_controller_clk_hz(void); +#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() +#endif +#define CONFIG_CQSPI_DECODER 0 +#define CONFIG_CMD_SF +#endif + +#ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */ +#define CONFIG_CMD_DM +#define CONFIG_DM +#define CONFIG_DM_SPI +#define CONFIG_DESIGNWARE_SPI +#define CONFIG_CMD_SPI +#endif + +/* * Serial Driver */ #define CONFIG_SYS_NS16550 diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index dd022fb..5a53c50 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -187,6 +187,8 @@ #define CONFIG_FAT_WRITE #define CONFIG_DOS_PARTITION +#define CONFIG_CMD_DM + /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) @@ -273,7 +275,11 @@ #define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000) #define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000) +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000) +#else +#define CONFIG_SYS_INIT_SP_ADDR ((CONFIG_SYS_TEXT_BASE) - 0x00001000) +#endif #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_NAND_SUPPORT diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h index 3f04908..351d8cd 100644 --- a/include/dt-bindings/reset/altr,rst-mgr.h +++ b/include/dt-bindings/reset/altr,rst-mgr.h @@ -1,14 +1,7 @@ /* * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H |