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-rw-r--r--common/env_onenand.c1
-rw-r--r--doc/README.mpc8641hpcn10
-rw-r--r--include/configs/MPC8610HPCD.h14
-rw-r--r--include/configs/sbc8641d.h14
4 files changed, 34 insertions, 5 deletions
diff --git a/common/env_onenand.c b/common/env_onenand.c
index 3c65b3e..dbccc79 100644
--- a/common/env_onenand.c
+++ b/common/env_onenand.c
@@ -97,6 +97,7 @@ int saveenv(void)
instr.len = CONFIG_ENV_SIZE;
instr.addr = env_addr;
+ instr.mtd = &onenand_mtd;
if (onenand_erase(&onenand_mtd, &instr)) {
printf("OneNAND: erase failed at 0x%08lx\n", env_addr);
return 1;
diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn
index 5ac39e6..d8fe0a4 100644
--- a/doc/README.mpc8641hpcn
+++ b/doc/README.mpc8641hpcn
@@ -134,15 +134,15 @@ For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit.
However, the physical map is altered to reside in 36-bit space, as follows.
Addresses are no longer mapped with VA == PA. All accesses from
software use the VA; the PA is only used for setting up windows
-and mappings. Note that the low 32 bits are the same as the VA above;
-only the top 4 bits vary:
+and mappings. Note that with the exception of PCI MEM and RIO, the low
+ 32 bits are the same as the VA above; only the top 4 bits vary:
Memory Range Device Size
------------ ------ ----
0x0_0000_0000 0x0_7fff_ffff DDR 2G
- 0xc_8000_0000 0xc_9fff_ffff RIO MEM 512M
- 0xc_8000_0000 0xc_9fff_ffff PCI1/PEX1 MEM 512M
- 0xc_a000_0000 0xc_bfff_ffff PCI2/PEX2 MEM 512M
+ 0xc_0000_0000 0xc_1fff_ffff RIO MEM 512M
+ 0xc_0000_0000 0xc_1fff_ffff PCI1/PEX1 MEM 512M
+ 0xc_2000_0000 0xc_3fff_ffff PCI2/PEX2 MEM 512M
0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M
0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K
0xf_ffdf_8000 0xf_ffdf_ffff CF 8K
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 7d57c1c..27517e5 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -81,6 +81,9 @@
#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
+
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
@@ -387,6 +390,17 @@
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
/*
* BAT4 32M Cache-inhibited, guarded
* 0xe200_0000 1M PCI-Express 2 I/O
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 752a905..0012945 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -104,6 +104,9 @@
#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
+
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
@@ -432,6 +435,17 @@
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
/*
* BAT4 32M Cache-inhibited, guarded
* 0xe200_0000 16M PCI-Express 1 I/O