diff options
80 files changed, 1666 insertions, 118 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index c3e04af..7c8eff9 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -198,6 +198,15 @@ void clock_set_pll3(unsigned int clk) CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg); } +unsigned int clock_get_pll3(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll3_cfg); + int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT); + return 3000000 * m; +} + unsigned int clock_get_pll5p(void) { struct sunxi_ccm_reg *const ccm = diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 3bfa122..3ab3b31 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -170,6 +170,47 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) udelay(5500); } +#ifdef CONFIG_MACH_SUN6I +void clock_set_mipi_pll(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + unsigned int k, m, n, value, diff; + unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff; + unsigned int src = clock_get_pll3(); + + /* All calculations are in KHz to avoid overflows */ + clk /= 1000; + src /= 1000; + + /* Pick the closest lower clock */ + for (k = 1; k <= 4; k++) { + for (m = 1; m <= 16; m++) { + for (n = 1; n <= 16; n++) { + value = src * n * k / m; + if (value > clk) + continue; + + diff = clk - value; + if (diff < best_diff) { + best_diff = diff; + best_k = k; + best_m = m; + best_n = n; + } + if (diff == 0) + goto done; + } + } + } + +done: + writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN | + CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) | + CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg); +} +#endif + #ifdef CONFIG_MACH_SUN8I_A33 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable) { @@ -188,6 +229,18 @@ void clock_set_pll11(unsigned int clk, bool sigma_delta_enable) } #endif +unsigned int clock_get_pll3(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll3_cfg); + int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1; + int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1; + + /* Multiply by 1000 after dividing by m to avoid integer overflows */ + return (24000 * n / m) * 1000; +} + unsigned int clock_get_pll6(void) { struct sunxi_ccm_reg *const ccm = @@ -198,6 +251,20 @@ unsigned int clock_get_pll6(void) return 24000000 * n * k / 2; } +unsigned int clock_get_mipi_pll(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->mipi_pll_cfg); + unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1; + unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1; + unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1; + unsigned int src = clock_get_pll3(); + + /* Multiply by 1000 after dividing by m to avoid integer overflows */ + return ((src / 1000) * n * k / m) * 1000; +} + void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) { int pll = clock_get_pll6() * 2; diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ff86891..d9a2f5f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -77,6 +77,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-inet-3f.dtb \ sun4i-a10-inet-3w.dtb \ sun4i-a10-inet97fv2.dtb \ + sun4i-a10-itead-iteaduino-plus.dtb \ sun4i-a10-jesurun-q5.dtb \ sun4i-a10-marsboard.dtb \ sun4i-a10-mini-xplus.dtb \ @@ -85,6 +86,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-olinuxino-lime.dtb \ sun4i-a10-pcduino.dtb dtb-$(CONFIG_MACH_SUN5I) += \ + sun5i-a10s-auxtek-t003.dtb \ sun5i-a10s-auxtek-t004.dtb \ sun5i-a10s-mk802.dtb \ sun5i-a10s-olinuxino-micro.dtb \ diff --git a/arch/arm/dts/axp152.dtsi b/arch/arm/dts/axp152.dtsi new file mode 100644 index 0000000..f90ad6c --- /dev/null +++ b/arch/arm/dts/axp152.dtsi @@ -0,0 +1,49 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&axp152 { + compatible = "x-powers,axp152"; + interrupt-controller; + #interrupt-cells = <1>; +}; diff --git a/arch/arm/dts/axp209.dtsi b/arch/arm/dts/axp209.dtsi index c20cf53..24c935c 100644 --- a/arch/arm/dts/axp209.dtsi +++ b/arch/arm/dts/axp209.dtsi @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person diff --git a/arch/arm/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/dts/sun4i-a10-ba10-tvbox.dts index 93d4356..f3cb297 100644 --- a/arch/arm/dts/sun4i-a10-ba10-tvbox.dts +++ b/arch/arm/dts/sun4i-a10-ba10-tvbox.dts @@ -125,12 +125,21 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { usb2_vbus_pin_a: usb2_vbus_pin@0 { allwinner,pins = "PH12"; }; }; +®_usb0_vbus { + regulator-boot-on; + status = "okay"; +}; + ®_usb1_vbus { status = "okay"; }; @@ -146,7 +155,13 @@ status = "okay"; }; +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + &usbphy { + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts index 5878a0b..1430568 100644 --- a/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts +++ b/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts @@ -114,6 +114,30 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + +&pio { + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PH5"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; +}; + +®_usb0_vbus { + status = "okay"; +}; + ®_usb2_vbus { status = "okay"; }; @@ -124,7 +148,17 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-cubieboard.dts b/arch/arm/dts/sun4i-a10-cubieboard.dts index 9afb4e0..046a84d 100644 --- a/arch/arm/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/dts/sun4i-a10-cubieboard.dts @@ -155,6 +155,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { led_pins_cubieboard: led_pins@0 { allwinner,pins = "PH20", "PH21"; @@ -162,6 +166,13 @@ allwinner,drive = <SUN4I_PINCTRL_20_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; }; ®_ahci_5v { @@ -216,7 +227,15 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts new file mode 100644 index 0000000..985e155 --- /dev/null +++ b/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts @@ -0,0 +1,202 @@ +/* + * Copyright 2015 Josef Gajdusek <atx@atx.name> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Iteaduino Plus A10"; + compatible = "itead,iteaduino-plus-a10", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mdio { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +®_ahci_5v { + status = "okay"; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>, + <&spi0_cs0_pins_a>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun4i-a10-mini-xplus.dts b/arch/arm/dts/sun4i-a10-mini-xplus.dts index ebe2a04..a7dd86d 100644 --- a/arch/arm/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/dts/sun4i-a10-mini-xplus.dts @@ -114,6 +114,15 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + +®_usb0_vbus { + regulator-boot-on; + status = "okay"; +}; + ®_usb1_vbus { status = "okay"; }; @@ -128,7 +137,13 @@ status = "okay"; }; +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + &usbphy { + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/dts/sun4i-a10-olinuxino-lime.dts index b64aa4e..28e32ad 100644 --- a/arch/arm/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/dts/sun4i-a10-olinuxino-lime.dts @@ -150,6 +150,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { allwinner,pins = "PC3"; @@ -164,6 +168,20 @@ allwinner,drive = <SUN4I_PINCTRL_20_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PH5"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; }; ®_ahci_5v { @@ -172,6 +190,10 @@ status = "okay"; }; +®_usb0_vbus { + status = "okay"; +}; + ®_usb1_vbus { status = "okay"; }; @@ -186,7 +208,17 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/dts/sun4i-a10.dtsi b/arch/arm/dts/sun4i-a10.dtsi index 61c03d1..463bacd 100644 --- a/arch/arm/dts/sun4i-a10.dtsi +++ b/arch/arm/dts/sun4i-a10.dtsi @@ -611,6 +611,19 @@ #size-cells = <0>; }; + usb_otg: usb@01c13000 { + compatible = "allwinner,sun4i-a10-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ahb_gates 0>; + interrupts = <38>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun4i-a10-usb-phy"; @@ -713,8 +726,7 @@ clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; pwm0_pins_a: pwm0@0 { diff --git a/arch/arm/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/dts/sun5i-a10s-auxtek-t003.dts new file mode 100644 index 0000000..d4ad021 --- /dev/null +++ b/arch/arm/dts/sun5i-a10s-auxtek-t003.dts @@ -0,0 +1,159 @@ +/* + * Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a10s.dtsi" +#include "sunxi-common-regulators.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Auxtek t003 A10s hdmi tv-stick"; + compatible = "allwinner,auxtek-t003", "allwinner,sun5i-a10s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_t003>; + + red { + label = "t003-tv-dongle:red:usr"; + gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ + default-state = "on"; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp152: pmic@30 { + compatible = "x-powers,axp152"; + reg = <0x30>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t003>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + mmc0_cd_pin_t003: mmc0_cd_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + led_pins_t003: led_pins@0 { + allwinner,pins = "PB2"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_20_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +®_usb0_vbus { + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb0_vbus_pin_a { + allwinner,pins = "PG13"; +}; + +&usb1_vbus_pin_a { + allwinner,pins = "PB10"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts index a7e19e4..5a422c1 100644 --- a/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts @@ -96,8 +96,15 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp152: pmic@30 { + reg = <0x30>; + interrupts = <0>; + }; }; +#include "axp152.dtsi" + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins_a>; @@ -189,6 +196,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 { allwinner,pins = "PG1"; @@ -217,6 +228,18 @@ allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PG12"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + +®_usb0_vbus { + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + status = "okay"; }; ®_usb1_vbus { @@ -243,8 +266,20 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb0_vbus_pin_a { + allwinner,pins = "PG11"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; - diff --git a/arch/arm/dts/sun5i-a13-hsg-h702.dts b/arch/arm/dts/sun5i-a13-hsg-h702.dts index 990f9d6..3724b98 100644 --- a/arch/arm/dts/sun5i-a13-hsg-h702.dts +++ b/arch/arm/dts/sun5i-a13-hsg-h702.dts @@ -45,6 +45,7 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/sun4i-a10.h> / { @@ -96,6 +97,25 @@ status = "okay"; }; +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <200000>; + }; + + button@400 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <400000>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>; @@ -110,6 +130,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { mmc0_cd_pin_h702: mmc0_cd_pin@0 { allwinner,pins = "PG0"; @@ -117,6 +141,20 @@ allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; #include "axp209.dtsi" @@ -152,13 +190,33 @@ regulator-name = "vcc-wifi"; }; +®_usb0_vbus { + pinctrl-0 = <&usb0_vbus_pin_a>; + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins_b>; status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb0_vbus_pin_a { + allwinner,pins = "PG12"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_ldo3>; status = "okay"; }; diff --git a/arch/arm/dts/sun5i-a13-olinuxino.dts b/arch/arm/dts/sun5i-a13-olinuxino.dts index 4232400..b3c234c 100644 --- a/arch/arm/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/dts/sun5i-a13-olinuxino.dts @@ -159,6 +159,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { allwinner,pins = "PG0"; @@ -174,6 +178,20 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; + usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 { allwinner,pins = "PG11"; allwinner,function = "gpio_out"; @@ -182,6 +200,11 @@ }; }; +®_usb0_vbus { + status = "okay"; + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +}; + ®_usb1_vbus { pinctrl-0 = <&usb1_vbus_pin_olinuxino>; gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; @@ -194,7 +217,21 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb0_vbus_pin_a { + allwinner,pins = "PG12"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; diff --git a/arch/arm/dts/sun5i-a13-utoo-p66.dts b/arch/arm/dts/sun5i-a13-utoo-p66.dts index 514f159..eb793d5 100644 --- a/arch/arm/dts/sun5i-a13-utoo-p66.dts +++ b/arch/arm/dts/sun5i-a13-utoo-p66.dts @@ -93,7 +93,7 @@ compatible = "chipone,icn8318"; reg = <0x40>; interrupt-parent = <&pio>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ + interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ pinctrl-names = "default"; pinctrl-0 = <&ts_wake_pin_p66>; wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ @@ -153,6 +153,10 @@ }; }; +&otg_sram { + status = "okay"; +}; + &pio { mmc0_cd_pin_p66: mmc0_cd_pin@0 { allwinner,pins = "PG0"; @@ -161,6 +165,20 @@ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + i2c_lcd_pins: i2c_lcd_pin@0 { allwinner,pins = "PG10", "PG12"; allwinner,function = "gpio_out"; @@ -219,7 +237,16 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_ldo3>; status = "okay"; diff --git a/arch/arm/dts/sun5i.dtsi b/arch/arm/dts/sun5i.dtsi index 54b0978..759117d 100644 --- a/arch/arm/dts/sun5i.dtsi +++ b/arch/arm/dts/sun5i.dtsi @@ -416,6 +416,19 @@ #size-cells = <0>; }; + usb_otg: usb@01c13000 { + compatible = "allwinner,sun4i-a10-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ahb_gates 0>; + interrupts = <38>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy"; @@ -475,8 +488,7 @@ clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; i2c0_pins_a: i2c0@0 { diff --git a/arch/arm/dts/sun6i-a31-colombus.dts b/arch/arm/dts/sun6i-a31-colombus.dts index 0cf9926..0d0b6f2 100644 --- a/arch/arm/dts/sun6i-a31-colombus.dts +++ b/arch/arm/dts/sun6i-a31-colombus.dts @@ -66,6 +66,18 @@ status = "okay"; }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/dts/sun6i-a31-m9.dts b/arch/arm/dts/sun6i-a31-m9.dts index a5660d6..6e0e568 100644 --- a/arch/arm/dts/sun6i-a31-m9.dts +++ b/arch/arm/dts/sun6i-a31-m9.dts @@ -48,7 +48,7 @@ #include <dt-bindings/pinctrl/sun4i-a10.h> / { - model = "Mele M9 / A1000G Quad top set box"; + model = "Mele M9 top set box"; compatible = "mele,m9", "allwinner,sun6i-a31"; aliases { diff --git a/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts index 4404f37..4dd70cc 100644 --- a/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts +++ b/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts @@ -143,6 +143,11 @@ status = "okay"; }; +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + &usbphy { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/dts/sun6i-a31.dtsi b/arch/arm/dts/sun6i-a31.dtsi index 008047a..39953e7 100644 --- a/arch/arm/dts/sun6i-a31.dtsi +++ b/arch/arm/dts/sun6i-a31.dtsi @@ -512,6 +512,19 @@ #size-cells = <0>; }; + usb_otg: usb@01c19000 { + compatible = "allwinner,sun6i-a31-musb"; + reg = <0x01c19000 0x0400>; + clocks = <&ahb1_gates 24>; + resets = <&ahb1_rst 24>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + usbphy: phy@01c19400 { compatible = "allwinner,sun6i-a31-usb-phy"; reg = <0x01c19400 0x10>, @@ -599,8 +612,7 @@ clocks = <&apb1_gates 5>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; uart0_pins_a: uart0@0 { diff --git a/arch/arm/dts/sun6i-a31s-cs908.dts b/arch/arm/dts/sun6i-a31s-cs908.dts index 1e2411a..5e8f8c4 100644 --- a/arch/arm/dts/sun6i-a31s-cs908.dts +++ b/arch/arm/dts/sun6i-a31s-cs908.dts @@ -93,6 +93,11 @@ status = "okay"; }; +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + &usbphy { status = "okay"; }; diff --git a/arch/arm/dts/sun7i-a20-cubietruck.dts b/arch/arm/dts/sun7i-a20-cubietruck.dts index 4611e2f..e6b0192 100644 --- a/arch/arm/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/dts/sun7i-a20-cubietruck.dts @@ -88,15 +88,11 @@ }; }; - reg_vmmc3: vmmc3 { - compatible = "regulator-fixed"; + mmc3_pwrseq: mmc3_pwrseq { + compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; - pinctrl-0 = <&vmmc3_pin_cubietruck>; - regulator-name = "vmmc3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&mmc3_pwrseq_pin_cubietruck>; + reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ }; }; @@ -172,7 +168,8 @@ &mmc3 { pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vmmc3>; + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc3_pwrseq>; bus-width = <4>; non-removable; status = "okay"; @@ -181,7 +178,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ + interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ interrupt-names = "host-wake"; }; }; @@ -199,23 +196,27 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { - vmmc3_pin_cubietruck: vmmc3_pin@0 { - allwinner,pins = "PH9"; + ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { + allwinner,pins = "PH12"; allwinner,function = "gpio_out"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { - allwinner,pins = "PH12"; + led_pins_cubietruck: led_pins@0 { + allwinner,pins = "PH7", "PH11", "PH20", "PH21"; allwinner,function = "gpio_out"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - led_pins_cubietruck: led_pins@0 { - allwinner,pins = "PH7", "PH11", "PH20", "PH21"; + mmc3_pwrseq_pin_cubietruck: mmc3_pwrseq_pin@0 { + allwinner,pins = "PH9"; allwinner,function = "gpio_out"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; @@ -227,6 +228,20 @@ allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH19"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PH22"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; &pwm { @@ -288,7 +303,16 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ + usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/dts/sun7i-a20-i12-tvbox.dts index f32f6f2..1e6bd36 100644 --- a/arch/arm/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/dts/sun7i-a20-i12-tvbox.dts @@ -178,7 +178,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ + interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ interrupt-names = "host-wake"; }; }; diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts index 769726d..0423708 100644 --- a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts @@ -135,6 +135,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { allwinner,pins = "PC3"; @@ -149,6 +153,20 @@ allwinner,drive = <SUN4I_PINCTRL_20_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PH5"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; }; ®_ahci_5v { @@ -157,6 +175,10 @@ status = "okay"; }; +®_usb0_vbus { + status = "okay"; +}; + ®_usb1_vbus { status = "okay"; }; @@ -171,7 +193,17 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts index 00f8f25..c5d70ca 100644 --- a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts @@ -215,6 +215,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { allwinner,pins = "PH11"; @@ -229,12 +233,30 @@ allwinner,drive = <SUN4I_PINCTRL_20_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PH5"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; }; ®_ahci_5v { status = "okay"; }; +®_usb0_vbus { + status = "okay"; +}; + ®_usb1_vbus { status = "okay"; }; @@ -275,7 +297,17 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi index 6a63f30..71ab6b8 100644 --- a/arch/arm/dts/sun7i-a20.dtsi +++ b/arch/arm/dts/sun7i-a20.dtsi @@ -699,6 +699,19 @@ #size-cells = <0>; }; + usb_otg: usb@01c13000 { + compatible = "allwinner,sun4i-a10-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ahb_gates 0>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun7i-a20-usb-phy"; @@ -794,8 +807,7 @@ clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; pwm0_pins_a: pwm0@0 { diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi index 5cd2e92..9c4a55c 100644 --- a/arch/arm/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/dts/sun8i-a23-a33.dtsi @@ -338,6 +338,8 @@ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ahb1_gates 26>; resets = <&ahb1_rst 26>; + phys = <&usbphy 1>; + phy-names = "usb"; status = "disabled"; }; @@ -347,6 +349,8 @@ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ahb1_gates 29>, <&usb_clk 16>; resets = <&ahb1_rst 29>; + phys = <&usbphy 1>; + phy-names = "usb"; status = "disabled"; }; @@ -357,8 +361,7 @@ clocks = <&apb1_gates 5>; gpio-controller; interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; uart0_pins_a: uart0@0 { diff --git a/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts index 95134c6..8d9da68 100644 --- a/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts +++ b/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts @@ -125,3 +125,12 @@ pinctrl-0 = <&r_uart_pins_a>; status = "okay"; }; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-a23.dtsi b/arch/arm/dts/sun8i-a23.dtsi index 8698f7a..2cc27c7 100644 --- a/arch/arm/dts/sun8i-a23.dtsi +++ b/arch/arm/dts/sun8i-a23.dtsi @@ -58,6 +58,39 @@ clock-output-names = "mbus"; }; }; + + soc@01c00000 { + usb_otg: usb@01c19000 { + compatible = "allwinner,sun6i-a31-musb"; + reg = <0x01c19000 0x0400>; + clocks = <&ahb1_gates 24>; + resets = <&ahb1_rst 24>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: phy@01c19400 { + compatible = "allwinner,sun8i-a23-usb-phy"; + reg = <0x01c19400 0x10>, + <0x01c1a800 0x4>; + reg-names = "phy_ctrl", + "pmu1"; + clocks = <&usb_clk 8>, + <&usb_clk 9>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&usb_clk 0>, + <&usb_clk 1>; + reset-names = "usb0_reset", + "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + }; }; &pio { diff --git a/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts index da16343..1aefc67 100644 --- a/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts +++ b/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts @@ -131,3 +131,12 @@ pinctrl-0 = <&r_uart_pins_a>; status = "okay"; }; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts b/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts index 9777149..a438975 100644 --- a/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts +++ b/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts @@ -1,17 +1,56 @@ /* * Copyright 2015 Hans de Goede <hdegoede@redhat.com> * - * Minimal dts file for the Ippo Q8H V1.2 (A33, 1024x600) for u-boot only + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * SPDX-License-Identifier: GPL-2.0+ or X11 + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> / { - model = "Ippo Q8H V1.2 (A33, 1024x600)"; - compatible = "ippo,q8h-v1.2-a33-lcd1024x600", "allwinner,sun8i-a23"; + model = "Ippo Q8H Quad Core Tablet (v1.2)"; + compatible = "ippo,a33-q8h-v1.2", "allwinner,sun8i-a33"; aliases { serial0 = &r_uart; @@ -22,8 +61,73 @@ }; }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <200000>; + }; + + button@400 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <400000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&pio { + mmc0_cd_pin_q8h: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + &r_uart { pinctrl-names = "default"; pinctrl-0 = <&r_uart_pins_a>; status = "okay"; }; + +/* + * FIXME for now we only support host mode and rely on u-boot to have + * turned on Vbus which is controlled by the axp223 pmic on the board. + * + * Once we have axp223 support we should switch to fully supporting otg. + */ +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts index 5788c29..1d5390d 100644 --- a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts @@ -63,6 +63,10 @@ }; }; +&ehci0 { + status = "okay"; +}; + &lradc { vref-supply = <®_vcc3v0>; status = "okay"; @@ -113,6 +117,10 @@ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; +&ohci0 { + status = "okay"; +}; + &pio { mmc0_cd_pin_sina33: mmc0_cd_pin@0 { allwinner,pins = "PB4"; @@ -127,3 +135,8 @@ pinctrl-0 = <&uart0_pins_b>; status = "okay"; }; + +&usbphy { + status = "okay"; + usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ +}; diff --git a/arch/arm/dts/sun8i-a33.dtsi b/arch/arm/dts/sun8i-a33.dtsi index 85ee080..faa7d3c 100644 --- a/arch/arm/dts/sun8i-a33.dtsi +++ b/arch/arm/dts/sun8i-a33.dtsi @@ -80,6 +80,39 @@ clock-output-names = "mbus"; }; }; + + soc@01c00000 { + usb_otg: usb@01c19000 { + compatible = "allwinner,sun8i-a33-musb"; + reg = <0x01c19000 0x0400>; + clocks = <&ahb1_gates 24>; + resets = <&ahb1_rst 24>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: phy@01c19400 { + compatible = "allwinner,sun8i-a33-usb-phy"; + reg = <0x01c19400 0x14>, + <0x01c1a800 0x4>; + reg-names = "phy_ctrl", + "pmu1"; + clocks = <&usb_clk 8>, + <&usb_clk 9>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&usb_clk 0>, + <&usb_clk 1>; + reset-names = "usb0_reset", + "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + }; }; &pio { diff --git a/arch/arm/dts/sunxi-common-regulators.dtsi b/arch/arm/dts/sunxi-common-regulators.dtsi index 51cc838..f1953b0 100644 --- a/arch/arm/dts/sunxi-common-regulators.dtsi +++ b/arch/arm/dts/sunxi-common-regulators.dtsi @@ -108,6 +108,7 @@ regulator-name = "usb1-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + regulator-boot-on; enable-active-high; gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; status = "disabled"; @@ -120,6 +121,7 @@ regulator-name = "usb2-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + regulator-boot-on; enable-active-high; gpio = <&pio 7 3 GPIO_ACTIVE_HIGH>; status = "disabled"; diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index a7e25f4..0088bb9 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -208,6 +208,8 @@ struct sunxi_ccm_reg { #define CCM_AHB_GATE_DLL (0x1 << 15) #define CCM_AHB_GATE_ACE (0x1 << 16) +#define CCM_PLL3_CTRL_M_SHIFT 0 +#define CCM_PLL3_CTRL_M_MASK (0x7f << CCM_PLL3_CTRL_M_SHIFT) #define CCM_PLL3_CTRL_M(n) (((n) & 0x7f) << 0) #define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 15) #define CCM_PLL3_CTRL_EN (0x1 << 31) @@ -287,6 +289,12 @@ struct sunxi_ccm_reg { #define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) #define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) #define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) +#define CCM_LCD_CH0_CTRL_MIPI_PLL 0 /* No mipi pll on sun4i/5i/7i */ +#ifdef CONFIG_MACH_SUN5I +#define CCM_LCD_CH0_CTRL_TVE_RST (0x1 << 29) +#else +#define CCM_LCD_CH0_CTRL_TVE_RST 0 /* No separate tve-rst on sun4i/7i */ +#endif #define CCM_LCD_CH0_CTRL_RST (0x1 << 30) #define CCM_LCD_CH0_CTRL_GATE (0x1 << 31) @@ -342,6 +350,7 @@ struct sunxi_ccm_reg { #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int hz); void clock_set_pll3(unsigned int hz); +unsigned int clock_get_pll3(void); unsigned int clock_get_pll5p(void); unsigned int clock_get_pll6(void); #endif diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 06c6feb..9b7b90c 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -179,7 +179,11 @@ struct sunxi_ccm_reg { #define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16) #define CCM_PLL1_CTRL_EN (0x1 << 31) +#define CCM_PLL3_CTRL_M_SHIFT 0 +#define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT) #define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_PLL3_CTRL_N_SHIFT 8 +#define CCM_PLL3_CTRL_N_MASK (0x7f << CCM_PLL3_CTRL_N_SHIFT) #define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8) #define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24) #define CCM_PLL3_CTRL_EN (0x1 << 31) @@ -198,6 +202,18 @@ struct sunxi_ccm_reg { #define CCM_PLL6_CTRL_K_SHIFT 4 #define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) +#define CCM_MIPI_PLL_CTRL_M_SHIFT 0 +#define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT) +#define CCM_MIPI_PLL_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_MIPI_PLL_CTRL_K_SHIFT 4 +#define CCM_MIPI_PLL_CTRL_K_MASK (0x3 << CCM_MIPI_PLL_CTRL_K_SHIFT) +#define CCM_MIPI_PLL_CTRL_K(n) ((((n) - 1) & 0x3) << 4) +#define CCM_MIPI_PLL_CTRL_N_SHIFT 8 +#define CCM_MIPI_PLL_CTRL_N_MASK (0xf << CCM_MIPI_PLL_CTRL_N_SHIFT) +#define CCM_MIPI_PLL_CTRL_N(n) ((((n) - 1) & 0xf) << 8) +#define CCM_MIPI_PLL_CTRL_LDO_EN (0x3 << 22) +#define CCM_MIPI_PLL_CTRL_EN (0x1 << 31) + #define CCM_PLL11_CTRL_N(n) ((((n) - 1) & 0x3f) << 8) #define CCM_PLL11_CTRL_SIGMA_DELTA_EN (0x1 << 24) #define CCM_PLL11_CTRL_UPD (0x1 << 30) @@ -360,7 +376,10 @@ void clock_set_pll1(unsigned int hz); void clock_set_pll3(unsigned int hz); void clock_set_pll5(unsigned int clk, bool sigma_delta_enable); void clock_set_pll11(unsigned int clk, bool sigma_delta_enable); +void clock_set_mipi_pll(unsigned int hz); +unsigned int clock_get_pll3(void); unsigned int clock_get_pll6(void); +unsigned int clock_get_mipi_pll(void); #endif #endif /* _SUNXI_CLOCK_SUN6I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h index 2cc3916..b64f310 100644 --- a/arch/arm/include/asm/arch-sunxi/display.h +++ b/arch/arm/include/asm/arch-sunxi/display.h @@ -196,7 +196,9 @@ struct sunxi_lcdc_reg { u8 res3[0x44]; /* 0xac */ u32 tcon1_io_polarity; /* 0xf0 */ u32 tcon1_io_tristate; /* 0xf4 */ - u8 res4[0x128]; /* 0xf8 */ + u8 res4[0x108]; /* 0xf8 */ + u32 mux_ctrl; /* 0x200 */ + u8 res5[0x1c]; /* 0x204 */ u32 lvds_ana0; /* 0x220 */ u32 lvds_ana1; /* 0x224 */ }; @@ -385,6 +387,10 @@ struct sunxi_tve_reg { #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) #define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16) +#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0) +#define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0) +#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4) +#define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4) #ifdef CONFIG_SUNXI_GEN_SUN6I #define SUNXI_LCDC_LVDS_ANA0 0x40040320 #define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31) @@ -506,7 +512,11 @@ struct sunxi_tve_reg { #define SUNXI_TVE_CFG0_PAL 0x07030001 #define SUNXI_TVE_CFG0_NTSC 0x07030000 #define SUNXI_TVE_DAC_CFG0_VGA 0x403e1ac7 +#ifdef CONFIG_MACH_SUN5I +#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x433f0009 +#else #define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x403f0008 +#endif #define SUNXI_TVE_FILTER_COMPOSITE 0x00000120 #define SUNXI_TVE_CHROMA_FREQ_PAL_M 0x21e6efe3 #define SUNXI_TVE_CHROMA_FREQ_PAL_NC 0x21f69446 diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c index 06d5023..2b92362 100644 --- a/board/cm5200/fwupdate.c +++ b/board/cm5200/fwupdate.c @@ -12,6 +12,7 @@ #include <common.h> #include <command.h> +#include <fat.h> #include <malloc.h> #include <image.h> #include <usb.h> @@ -19,9 +20,6 @@ #include "fwupdate.h" -extern long do_fat_read(const char *, void *, unsigned long, int); -extern int do_fat_fsload(cmd_tbl_t *, int, int, char * const []); - static int load_rescue_image(ulong); void cm5200_fwupdate(void) @@ -124,7 +122,7 @@ static int load_rescue_image(ulong addr) /* Check if rescue image is present */ FW_DEBUG("Looking for firmware directory '%s'" " on partition %d\n", fwdir, i); - if (do_fat_read(fwdir, NULL, 0, LS_NO) == -1) { + if (!fat_exists(fwdir)) { FW_DEBUG("No NX rescue image on " "partition %d.\n", i); partno = -2; diff --git a/board/inka4x0/MAINTAINERS b/board/inka4x0/MAINTAINERS index 246b2d4..e8cec73 100644 --- a/board/inka4x0/MAINTAINERS +++ b/board/inka4x0/MAINTAINERS @@ -1,5 +1,5 @@ INKA4X0 BOARD -M: Detlev Zundel <dzu@denx.de> +M: Anatolij Gustschin <agust@denx.de> S: Maintained F: board/inka4x0/ F: include/configs/inka4x0.h diff --git a/board/ipek01/MAINTAINERS b/board/ipek01/MAINTAINERS index 060f8a5..906d39e 100644 --- a/board/ipek01/MAINTAINERS +++ b/board/ipek01/MAINTAINERS @@ -1,5 +1,5 @@ IPEK01 BOARD -M: Wolfgang Grandegger <wg@denx.de> +M: Anatolij Gustschin <agust@denx.de> S: Maintained F: board/ipek01/ F: include/configs/ipek01.h diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 13f4537..fd6668f 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -526,7 +526,16 @@ config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 select VIDEO_LCD_SSD2828 select VIDEO_LCD_IF_PARALLEL ---help--- - 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 + 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 + +config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 + bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" + select VIDEO_LCD_ANX9804 + select VIDEO_LCD_IF_PARALLEL + select VIDEO_LCD_PANEL_I2C + ---help--- + Select this for eDP LCD panels with 4 lanes running at 1.62G, + connected via an ANX9804 bridge chip. config VIDEO_LCD_PANEL_HITACHI_TX18D42VM bool "Hitachi tx18d42vm LCD panel" diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 1f12a64..1b44ce8 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -19,6 +19,7 @@ F: include/configs/sun5i.h F: configs/A10s-OLinuXino-M_defconfig F: configs/A13-OLinuXino_defconfig F: configs/A13-OLinuXinoM_defconfig +F: configs/Auxtek-T003_defconfig F: configs/Auxtek-T004_defconfig F: configs/mk802_a10s_defconfig F: configs/r7-tv-dongle_defconfig diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index 1d36919..3aaf029 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -6,6 +6,7 @@ CONFIG_MMC0_CD_PIN="PG0" CONFIG_USB0_VBUS_PIN="PG12" CONFIG_USB0_VBUS_DET="PG1" CONFIG_AXP_GPIO=y +# CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig new file mode 100644 index 0000000..b9692dc --- /dev/null +++ b/configs/Auxtek-T003_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_EMR1=0 +CONFIG_USB1_VBUS_PIN="PB10" +CONFIG_VIDEO_COMPOSITE=y +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_USB_EHCI_HCD=y diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 4b9ef35..560295f 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 CONFIG_GMAC_TX_DELAY=3 +CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index 5506ab3..346db34 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -5,6 +5,7 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="PH0" CONFIG_USB2_VBUS_PIN="PH1" CONFIG_GMAC_TX_DELAY=3 +CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index 1ae8c16..35f644a 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -4,13 +4,24 @@ CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=240 CONFIG_DRAM_ZQ=251 CONFIG_USB1_VBUS_PIN="" +CONFIG_I2C0_ENABLE=y +CONFIG_AXP_GPIO=y +CONFIG_VIDEO_LCD_MODE="x:2048,y:1536,depth:24,pclk_khz:208000,le:5,ri:150,up:9,lo:24,hs:5,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_DCLK_PHASE=0 +CONFIG_VIDEO_LCD_POWER="PH27" +CONFIG_VIDEO_LCD_BL_EN="PM1" +CONFIG_VIDEO_LCD_BL_PWM="PH13" +CONFIG_VIDEO_LCD_PANEL_I2C_SDA="PA23" +CONFIG_VIDEO_LCD_PANEL_I2C_SCL="PA24" +CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC" +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_ETH_DESIGNWARE=y CONFIG_AXP221_ALDO1_VOLT=3300 +CONFIG_AXP221_ELDO3_VOLT=1800 CONFIG_USB_EHCI_HCD=y diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index 5e66d43..b983c8c 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y CONFIG_VIDEO_VGA=y +CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig index 40f5daa..0d1ba15 100644 --- a/configs/Mele_M5_defconfig +++ b/configs/Mele_M5_defconfig @@ -4,6 +4,7 @@ CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_ZQ=122 CONFIG_MMC0_CD_PIN="PH1" +CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index 00b6c63..c88eb9b 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y +CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index f9408b1..d67bb90 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -5,6 +5,7 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="PH26" CONFIG_USB2_VBUS_PIN="PH22" CONFIG_VIDEO_VGA=y +CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index 1dc0e76..71d236b 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -7,6 +7,7 @@ CONFIG_MMC3_CD_PIN="PH11" CONFIG_MMC_SUNXI_SLOT_EXTRA=3 CONFIG_USB1_VBUS_PIN="PH26" CONFIG_USB2_VBUS_PIN="PH22" +CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/TZX-Q8-713B7_defconfig b/configs/TZX-Q8-713B7_defconfig index 3508834..4ef80db 100644 --- a/configs/TZX-Q8-713B7_defconfig +++ b/configs/TZX-Q8-713B7_defconfig @@ -6,6 +6,7 @@ CONFIG_MMC0_CD_PIN="PG0" CONFIG_USB0_VBUS_PIN="PG12" CONFIG_USB0_VBUS_DET="PG1" CONFIG_AXP_GPIO=y +# CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index 169c2e8..99a8c31 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -9,6 +9,7 @@ CONFIG_USB0_VBUS_PIN="PB04" CONFIG_USB0_VBUS_DET="PG01" CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y +# CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_LCD_MODE="x:480,y:800,depth:18,pclk_khz:25000,le:2,ri:93,up:2,lo:93,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PG4" diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index 5b5fc12..cdcd9de 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -4,6 +4,7 @@ CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=384 CONFIG_DRAM_EMR1=4 CONFIG_USB2_VBUS_PIN="PH12" +CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/forfun_q88db_defconfig b/configs/forfun_q88db_defconfig index 6fff725..610a062 100644 --- a/configs/forfun_q88db_defconfig +++ b/configs/forfun_q88db_defconfig @@ -5,6 +5,7 @@ CONFIG_DRAM_CLK=384 CONFIG_USB0_VBUS_PIN="PG12" CONFIG_USB0_VBUS_DET="PG1" CONFIG_AXP_GPIO=y +# CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig index 99e78ba..d4d9524 100644 --- a/configs/i12-tvbox_defconfig +++ b/configs/i12-tvbox_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 +CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index 33162d1..f958c31 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -5,6 +5,7 @@ CONFIG_DRAM_CLK=408 CONFIG_USB0_VBUS_PIN="PG12" CONFIG_USB0_VBUS_DET="PG1" CONFIG_AXP_GPIO=y +# CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index b0d8621..46c38e5 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=312 +CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/doc/README.video b/doc/README.video index 4f7a4b5..62ac17b 100644 --- a/doc/README.video +++ b/doc/README.video @@ -68,6 +68,11 @@ The sunxi u-boot driver supports the following video-mode options: overrides the xres, yres and refresh from the video-mode env. variable. Defaults to edid=1. +- overscan_x/overscan_y=<int> - Set x/y overscan value + This configures a black border on the left and right resp. top and bottom + to deal with overscanning displays. Defaults to overscan_x=32 and + overscan_y=20 for composite monitors, 0 for other monitors. + For example to always use the hdmi connector, even if no cable is inserted, using edid info when available and otherwise initalizing it at 1024x768@60Hz, use: "setenv video-mode sunxi:1024x768-24@60,monitor=dvi,hpd=0,edid=1". diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index afa165a..57b78e5 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -266,16 +266,28 @@ static int gpio_sunxi_bind(struct udevice *parent) { struct sunxi_gpio_platdata *plat = parent->platdata; struct sunxi_gpio_reg *ctlr; - int bank; - int ret; + int bank, no_banks, ret, start; /* If this is a child device, there is nothing to do here */ if (plat) return 0; + if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset, + "allwinner,sun6i-a31-r-pinctrl") == 0) { + start = 'L' - 'A'; + no_banks = 2; /* L & M */ + } else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset, + "allwinner,sun8i-a23-r-pinctrl") == 0) { + start = 'L' - 'A'; + no_banks = 1; /* L only */ + } else { + start = 0; + no_banks = SUNXI_GPIO_BANKS; + } + ctlr = (struct sunxi_gpio_reg *)fdtdec_get_addr(gd->fdt_blob, parent->of_offset, "reg"); - for (bank = 0; bank < SUNXI_GPIO_BANKS; bank++) { + for (bank = 0; bank < no_banks; bank++) { struct sunxi_gpio_platdata *plat; struct udevice *dev; @@ -283,7 +295,7 @@ static int gpio_sunxi_bind(struct udevice *parent) if (!plat) return -ENOMEM; plat->regs = &ctlr->gpio_bank[bank]; - plat->bank_name = gpio_bank_name(bank); + plat->bank_name = gpio_bank_name(start + bank); plat->gpio_count = SUNXI_GPIOS_PER_BANK; ret = device_bind(parent, parent->driver, @@ -306,6 +318,8 @@ static const struct udevice_id sunxi_gpio_ids[] = { { .compatible = "allwinner,sun8i-a23-pinctrl" }, { .compatible = "allwinner,sun8i-a33-pinctrl" }, { .compatible = "allwinner,sun9i-a80-pinctrl" }, + { .compatible = "allwinner,sun6i-a31-r-pinctrl" }, + { .compatible = "allwinner,sun8i-a23-r-pinctrl" }, { } }; diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 5cb3685..1dc082a 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -151,6 +151,14 @@ config FRAMEBUFFER_VESA_MODE default 0x11B if FRAMEBUFFER_VESA_MODE_11B default 0x117 if FRAMEBUFFER_VESA_MODE_USER +config VIDEO_LCD_ANX9804 + bool "ANX9804 bridge chip" + default n + ---help--- + Support for the ANX9804 bridge chip, which can take pixel data coming + from a parallel LCD interface and translate it on the fy into a DP + interface for driving eDP TFT displays. It uses I2C for configuration. + config VIDEO_LCD_SSD2828 bool "SSD2828 bridge chip" default n diff --git a/drivers/video/Makefile b/drivers/video/Makefile index c2c4dfc..e85fd8a 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o +obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o diff --git a/drivers/video/anx9804.c b/drivers/video/anx9804.c new file mode 100755 index 0000000..83d60d6 --- /dev/null +++ b/drivers/video/anx9804.c @@ -0,0 +1,188 @@ +/* + * (C) 2015 Hans de Goede <hdegoede@redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Support for the ANX9804 bridge chip, which can take pixel data coming + * from a parallel LCD interface and translate it on the flight into a DP + * interface for driving eDP TFT displays. + */ + +#include <common.h> +#include <i2c.h> +#include "anx9804.h" + +#define BIT(x) (1 << (x)) + +/* Registers at i2c address 0x38 */ + +#define ANX9804_HDCP_CONTROL_0_REG 0x01 + +#define ANX9804_SYS_CTRL2_REG 0x81 +#define ANX9804_SYS_CTRL2_CHA_STA 0x04 + +#define ANX9804_SYS_CTRL3_REG 0x82 +#define ANX9804_SYS_CTRL3_VALID_CTRL BIT(0) +#define ANX9804_SYS_CTRL3_F_VALID BIT(1) +#define ANX9804_SYS_CTRL3_HPD_CTRL BIT(4) +#define ANX9804_SYS_CTRL3_F_HPD BIT(5) + +#define ANX9804_LINK_BW_SET_REG 0xa0 +#define ANX9804_LANE_COUNT_SET_REG 0xa1 +#define ANX9804_TRAINING_PTN_SET_REG 0xa2 +#define ANX9804_TRAINING_LANE0_SET_REG 0xa3 +#define ANX9804_TRAINING_LANE1_SET_REG 0xa4 +#define ANX9804_TRAINING_LANE2_SET_REG 0xa5 +#define ANX9804_TRAINING_LANE3_SET_REG 0xa6 + +#define ANX9804_LINK_TRAINING_CTRL_REG 0xa8 +#define ANX9804_LINK_TRAINING_CTRL_EN BIT(0) + +#define ANX9804_LINK_DEBUG_REG 0xb8 +#define ANX9804_PLL_CTRL_REG 0xc7 +#define ANX9804_ANALOG_POWER_DOWN_REG 0xc8 + +/* Registers at i2c address 0x39 */ + +#define ANX9804_DEV_IDH_REG 0x03 + +#define ANX9804_POWERD_CTRL_REG 0x05 +#define ANX9804_POWERD_AUDIO BIT(4) + +#define ANX9804_RST_CTRL_REG 0x06 + +#define ANX9804_RST_CTRL2_REG 0x07 +#define ANX9804_RST_CTRL2_AUX BIT(2) +#define ANX9804_RST_CTRL2_AC_MODE BIT(6) + +#define ANX9804_VID_CTRL1_REG 0x08 +#define ANX9804_VID_CTRL1_VID_EN BIT(7) +#define ANX9804_VID_CTRL1_EDGE BIT(0) + +#define ANX9804_VID_CTRL2_REG 0x09 +#define ANX9804_ANALOG_DEBUG_REG1 0xdc +#define ANX9804_ANALOG_DEBUG_REG3 0xde +#define ANX9804_PLL_FILTER_CTRL1 0xdf +#define ANX9804_PLL_FILTER_CTRL3 0xe1 +#define ANX9804_PLL_FILTER_CTRL 0xe2 +#define ANX9804_PLL_CTRL3 0xe6 + +/** + * anx9804_init() - Init anx9804 parallel lcd to edp bridge chip + * + * This function will init an anx9804 parallel lcd to dp bridge chip + * using the passed in parameters. + * + * @i2c_bus: Number of the i2c bus to which the anx9804 is connected. + * @lanes: Number of displayport lanes to use + * @data_rate: Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G + * @bpp: Bits per pixel, must be 18 or 24 + */ +void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp) +{ + unsigned int orig_i2c_bus = i2c_get_bus_num(); + u8 c, colordepth; + int i; + + i2c_set_bus_num(i2c_bus); + + if (bpp == 18) + colordepth = 0x00; /* 6 bit */ + else + colordepth = 0x10; /* 8 bit */ + + /* Reset */ + i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1); + mdelay(100); + i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0); + + /* Write 0 to the powerdown reg (powerup everything) */ + i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0); + + c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG); + if (c != 0x98) { + printf("Error anx9804 chipid mismatch\n"); + i2c_set_bus_num(orig_i2c_bus); + return; + } + + for (i = 0; i < 100; i++) { + c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG); + i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c); + c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG); + if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0) + break; + + mdelay(5); + } + if (i == 100) + printf("Error anx9804 clock is not stable\n"); + + i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth); + + /* Set a bunch of analog related register values */ + i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07); + i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19); + i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9); + i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE); + i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0); + i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99); + i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b); + i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30); + i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06); + + /* Force HPD */ + i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG, + ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL); + + /* Power up and configure lanes */ + i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00); + i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00); + i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00); + i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00); + i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00); + + /* Reset AUX CH */ + i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, + ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX); + i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, + ANX9804_RST_CTRL2_AC_MODE); + + /* Powerdown audio and some other unused bits */ + i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO); + i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00); + i2c_reg_write(0x38, 0xa7, 0x00); + + /* Set data-rate / lanes */ + i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate); + i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes); + + /* Link training */ + i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG, + ANX9804_LINK_TRAINING_CTRL_EN); + mdelay(5); + for (i = 0; i < 100; i++) { + c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG); + if ((c & 0x01) == 0) + break; + + mdelay(5); + } + if(i == 100) { + printf("Error anx9804 link training timeout\n"); + i2c_set_bus_num(orig_i2c_bus); + return; + } + + /* Enable */ + i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG, + ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE); + /* Force stream valid */ + i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG, + ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL | + ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL); + + i2c_set_bus_num(orig_i2c_bus); +} diff --git a/drivers/video/anx9804.h b/drivers/video/anx9804.h new file mode 100644 index 0000000..6c5daf9 --- /dev/null +++ b/drivers/video/anx9804.h @@ -0,0 +1,25 @@ +/* + * (C) 2015 Hans de Goede <hdegoede@redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Support for the ANX9804 bridge chip, which can take pixel data coming + * from a parallel LCD interface and translate it on the flight into a DP + * interface for driving eDP TFT displays. + */ + +#ifndef _ANX9804_H +#define _ANX9804_H + +#define ANX9804_DATA_RATE_1620M 0x06 +#define ANX9804_DATA_RATE_2700M 0x0a + +#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 +void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp); +#else +static inline void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, + int bpp) {} +#endif +#endif diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 7f2ddc1..30e0317 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -283,9 +283,10 @@ void console_cursor(int state); #define VIDEO_COLS VIDEO_VISIBLE_COLS #define VIDEO_ROWS VIDEO_VISIBLE_ROWS -#define VIDEO_SIZE (VIDEO_ROWS*VIDEO_COLS*VIDEO_PIXEL_SIZE) -#define VIDEO_PIX_BLOCKS (VIDEO_SIZE >> 2) -#define VIDEO_LINE_LEN (VIDEO_COLS*VIDEO_PIXEL_SIZE) +#ifndef VIDEO_LINE_LEN +#define VIDEO_LINE_LEN (VIDEO_COLS * VIDEO_PIXEL_SIZE) +#endif +#define VIDEO_SIZE (VIDEO_ROWS * VIDEO_LINE_LEN) #define VIDEO_BURST_LEN (VIDEO_COLS/8) #ifdef CONFIG_VIDEO_LOGO @@ -1306,7 +1307,7 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff, struct palette p[256]; struct bmp_color_table_entry cte; int green_shift, red_off; - int limit = VIDEO_COLS * VIDEO_ROWS; + int limit = (VIDEO_LINE_LEN / VIDEO_PIXEL_SIZE) * VIDEO_ROWS; int pixels = 0; x = 0; @@ -1314,7 +1315,8 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff, ncolors = __le32_to_cpu(img->header.colors_used); bpp = VIDEO_PIXEL_SIZE; fbp = (unsigned char *) ((unsigned int) video_fb_address + - (((y + yoff) * VIDEO_COLS) + xoff) * bpp); + (y + yoff) * VIDEO_LINE_LEN + + xoff * bpp); bm = (uchar *) img + __le32_to_cpu(img->header.data_offset); @@ -1368,8 +1370,8 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff, y--; fbp = (unsigned char *) ((unsigned int) video_fb_address + - (((y + yoff) * VIDEO_COLS) + - xoff) * bpp); + (y + yoff) * VIDEO_LINE_LEN + + xoff * bpp); continue; case 1: /* end of bitmap data marker */ @@ -1381,8 +1383,8 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff, y -= bm[3]; fbp = (unsigned char *) ((unsigned int) video_fb_address + - (((y + yoff) * VIDEO_COLS) + - x + xoff) * bpp); + (y + yoff) * VIDEO_LINE_LEN + + xoff * bpp); bm += 4; break; default: @@ -1561,7 +1563,7 @@ int video_display_bitmap(ulong bmp_image, int x, int y) bmap = (uchar *) bmp + le32_to_cpu(bmp->header.data_offset); fb = (uchar *) (video_fb_address + - ((y + height - 1) * VIDEO_COLS * VIDEO_PIXEL_SIZE) + + ((y + height - 1) * VIDEO_LINE_LEN) + x * VIDEO_PIXEL_SIZE); #ifdef CONFIG_VIDEO_BMP_RLE8 @@ -1597,7 +1599,7 @@ int video_display_bitmap(ulong bmp_image, int x, int y) cte.blue); } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * + fb -= VIDEO_LINE_LEN + width * VIDEO_PIXEL_SIZE; } break; @@ -1628,8 +1630,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y) *fb++ = *bmap++; } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * - VIDEO_PIXEL_SIZE; + fb -= VIDEO_LINE_LEN + width * + VIDEO_PIXEL_SIZE; } break; case GDF__8BIT_332RGB: @@ -1642,8 +1644,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y) cte.blue); } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * - VIDEO_PIXEL_SIZE; + fb -= VIDEO_LINE_LEN + width * + VIDEO_PIXEL_SIZE; } break; case GDF_15BIT_555RGB: @@ -1666,8 +1668,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y) #endif } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * - VIDEO_PIXEL_SIZE; + fb -= VIDEO_LINE_LEN + width * + VIDEO_PIXEL_SIZE; } break; case GDF_16BIT_565RGB: @@ -1680,8 +1682,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y) cte.blue); } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * - VIDEO_PIXEL_SIZE; + fb -= VIDEO_LINE_LEN + width * + VIDEO_PIXEL_SIZE; } break; case GDF_32BIT_X888RGB: @@ -1694,8 +1696,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y) cte.blue); } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * - VIDEO_PIXEL_SIZE; + fb -= VIDEO_LINE_LEN + width * + VIDEO_PIXEL_SIZE; } break; case GDF_24BIT_888RGB: @@ -1708,8 +1710,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y) cte.blue); } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * - VIDEO_PIXEL_SIZE; + fb -= VIDEO_LINE_LEN + width * + VIDEO_PIXEL_SIZE; } break; } @@ -1728,8 +1730,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y) bmap += 3; } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * - VIDEO_PIXEL_SIZE; + fb -= VIDEO_LINE_LEN + width * + VIDEO_PIXEL_SIZE; } break; case GDF_15BIT_555RGB: @@ -1751,8 +1753,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y) bmap += 3; } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * - VIDEO_PIXEL_SIZE; + fb -= VIDEO_LINE_LEN + width * + VIDEO_PIXEL_SIZE; } break; case GDF_16BIT_565RGB: @@ -1765,8 +1767,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y) bmap += 3; } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * - VIDEO_PIXEL_SIZE; + fb -= VIDEO_LINE_LEN + width * + VIDEO_PIXEL_SIZE; } break; case GDF_32BIT_X888RGB: @@ -1779,8 +1781,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y) bmap += 3; } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * - VIDEO_PIXEL_SIZE; + fb -= VIDEO_LINE_LEN + width * + VIDEO_PIXEL_SIZE; } break; case GDF_24BIT_888RGB: @@ -1793,8 +1795,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y) bmap += 3; } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * - VIDEO_PIXEL_SIZE; + fb -= VIDEO_LINE_LEN + width * + VIDEO_PIXEL_SIZE; } break; default: @@ -1826,20 +1828,16 @@ int video_display_bitmap(ulong bmp_image, int x, int y) static int video_logo_xpos; static int video_logo_ypos; -static void plot_logo_or_black(void *screen, int width, int x, int y, \ - int black); +static void plot_logo_or_black(void *screen, int x, int y, int black); -static void logo_plot(void *screen, int width, int x, int y) +static void logo_plot(void *screen, int x, int y) { - plot_logo_or_black(screen, width, x, y, 0); + plot_logo_or_black(screen, x, y, 0); } static void logo_black(void) { - plot_logo_or_black(video_fb_address, \ - VIDEO_COLS, \ - video_logo_xpos, \ - video_logo_ypos, \ + plot_logo_or_black(video_fb_address, video_logo_xpos, video_logo_ypos, 1); } @@ -1858,11 +1856,11 @@ U_BOOT_CMD( " " ); -static void plot_logo_or_black(void *screen, int width, int x, int y, int black) +static void plot_logo_or_black(void *screen, int x, int y, int black) { int xcount, i; - int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE; + int skip = VIDEO_LINE_LEN - VIDEO_LOGO_WIDTH * VIDEO_PIXEL_SIZE; int ycount = video_logo_height; unsigned char r, g, b, *logo_red, *logo_blue, *logo_green; unsigned char *source; @@ -1880,7 +1878,7 @@ static void plot_logo_or_black(void *screen, int width, int x, int y, int black) y = max(0, (int)(VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT + y + 1)); #endif /* CONFIG_SPLASH_SCREEN_ALIGN */ - dest = (unsigned char *)screen + (y * width + x) * VIDEO_PIXEL_SIZE; + dest = (unsigned char *)screen + y * VIDEO_LINE_LEN + x * VIDEO_PIXEL_SIZE; #ifdef CONFIG_VIDEO_BMP_LOGO source = bmp_logo_bitmap; @@ -2009,8 +2007,7 @@ static void *video_logo(void) } #endif /* CONFIG_SPLASH_SCREEN */ - logo_plot(video_fb_address, VIDEO_COLS, - video_logo_xpos, video_logo_ypos); + logo_plot(video_fb_address, video_logo_xpos, video_logo_ypos); #ifdef CONFIG_SPLASH_SCREEN_ALIGN /* diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index 1868185..fc1aea3 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -15,12 +15,15 @@ #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/io.h> +#include <axp221.h> #include <errno.h> #include <fdtdec.h> #include <fdt_support.h> #include <i2c.h> +#include <malloc.h> #include <video_fb.h> #include "videomodes.h" +#include "anx9804.h" #include "hitachi_tx18d42vm_lcd.h" #include "ssd2828.h" @@ -51,6 +54,7 @@ struct sunxi_display { GraphicDevice graphic_device; enum sunxi_monitor monitor; unsigned int depth; + unsigned int fb_addr; unsigned int fb_size; } sunxi_display; @@ -483,7 +487,9 @@ static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode, setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE); if (mode->vmode == FB_VMODE_INTERLACED) setbits_le32(&de_be->mode, +#ifndef CONFIG_MACH_SUN5I SUNXI_DE_BE_MODE_DEFLICKER_ENABLE | +#endif SUNXI_DE_BE_MODE_INTERLACE_ENABLE); if (sunxi_is_composite()) { @@ -517,6 +523,7 @@ static void sunxi_lcdc_pll_set(int tcon, int dotclock, int value, n, m, min_m, max_m, diff; int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF; int best_double = 0; + bool use_mipi_pll = false; if (tcon == 0) { #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL @@ -567,16 +574,42 @@ static void sunxi_lcdc_pll_set(int tcon, int dotclock, } } - debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n", - dotclock, (best_double + 1) * 3000 * best_n / best_m, - best_double + 1, best_n, best_m); +#ifdef CONFIG_MACH_SUN6I + /* + * Use the MIPI pll if we've been unable to find any matching setting + * for PLL3, this happens with high dotclocks because of min_m = 6. + */ + if (tcon == 0 && best_n == 0) { + use_mipi_pll = true; + best_m = 6; /* Minimum m for tcon0 */ + } - clock_set_pll3(best_n * 3000000); + if (use_mipi_pll) { + clock_set_pll3(297000000); /* Fix the video pll at 297 MHz */ + clock_set_mipi_pll(best_m * dotclock * 1000); + debug("dotclock: %dkHz = %dkHz via mipi pll\n", + dotclock, clock_get_mipi_pll() / best_m / 1000); + } else +#endif + { + clock_set_pll3(best_n * 3000000); + debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n", + dotclock, + (best_double + 1) * clock_get_pll3() / best_m / 1000, + best_double + 1, best_n, best_m); + } if (tcon == 0) { - writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | - (best_double ? CCM_LCD_CH0_CTRL_PLL3_2X : - CCM_LCD_CH0_CTRL_PLL3), + u32 pll; + + if (use_mipi_pll) + pll = CCM_LCD_CH0_CTRL_MIPI_PLL; + else if (best_double) + pll = CCM_LCD_CH0_CTRL_PLL3_2X; + else + pll = CCM_LCD_CH0_CTRL_PLL3; + + writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | pll, &ccm->lcd0_ch0_clk_cfg); } else { writel(CCM_LCD_CH1_CTRL_GATE | @@ -734,13 +767,17 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode, (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; int bp, clk_delay, clk_div, clk_double, pin, total, val; - for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) + for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) { #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0); #endif #ifdef CONFIG_VIDEO_LCD_IF_LVDS sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LVDS0); #endif +#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 + sunxi_gpio_set_drv(pin, 3); +#endif + } sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double); @@ -872,6 +909,13 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode, SUNXI_LCDC_TCON_VSYNC_MASK | SUNXI_LCDC_TCON_HSYNC_MASK); } + +#ifdef CONFIG_MACH_SUN5I + if (sunxi_is_composite()) + clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK, + SUNXI_LCDC_MUX_CTRL_SRC0(1)); +#endif + sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double); } #endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */ @@ -997,6 +1041,8 @@ static void sunxi_tvencoder_mode_set(void) struct sunxi_tve_reg * const tve = (struct sunxi_tve_reg *)SUNXI_TVE0_BASE; + /* Reset off */ + setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST); /* Clock on */ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0); @@ -1168,6 +1214,17 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode, break; case sunxi_monitor_lcd: sunxi_lcdc_panel_enable(); + if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) { + /* + * The anx9804 needs 1.8V from eldo3, we do this here + * and not via CONFIG_AXP221_ELDO3 from board_init() + * to avoid turning this on when using hdmi output. + */ + axp221_set_eldo(3, 1800); + anx9804_init(CONFIG_VIDEO_LCD_I2C_BUS, 4, + ANX9804_DATA_RATE_1620M, + sunxi_display.depth); + } if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) { mdelay(50); /* Wait for lcd controller power on */ hitachi_tx18d42vm_init(); @@ -1297,9 +1354,10 @@ void *video_hw_init(void) #ifdef CONFIG_VIDEO_HDMI int ret, hpd, hpd_delay, edid; #endif + int i, overscan_offset, overscan_x, overscan_y; + unsigned int fb_dma_addr; char mon[16]; char *lcd_mode = CONFIG_VIDEO_LCD_MODE; - int i; memset(&sunxi_display, 0, sizeof(struct sunxi_display)); @@ -1310,6 +1368,8 @@ void *video_hw_init(void) hpd_delay = video_get_option_int(options, "hpd_delay", 500); edid = video_get_option_int(options, "edid", 1); #endif + overscan_x = video_get_option_int(options, "overscan_x", -1); + overscan_y = video_get_option_int(options, "overscan_y", -1); sunxi_display.monitor = sunxi_get_default_mon(true); video_get_option_string(options, "monitor", mon, sizeof(mon), sunxi_get_mon_desc(sunxi_display.monitor)); @@ -1386,8 +1446,20 @@ void *video_hw_init(void) break; } + /* Yes these defaults are quite high, overscan on composite sucks... */ + if (overscan_x == -1) + overscan_x = sunxi_is_composite() ? 32 : 0; + if (overscan_y == -1) + overscan_y = sunxi_is_composite() ? 20 : 0; + sunxi_display.fb_size = (mode->xres * mode->yres * 4 + 0xfff) & ~0xfff; + overscan_offset = (overscan_y * mode->xres + overscan_x) * 4; + /* We want to keep the fb_base for simplefb page aligned, where as + * the sunxi dma engines will happily accept an unaligned address. */ + if (overscan_offset) + sunxi_display.fb_size += 0x1000; + if (sunxi_display.fb_size > CONFIG_SUNXI_MAX_FB_SIZE) { printf("Error need %dkB for fb, but only %dkB is reserved\n", sunxi_display.fb_size >> 10, @@ -1395,25 +1467,36 @@ void *video_hw_init(void) return NULL; } - printf("Setting up a %dx%d%s %s console\n", mode->xres, mode->yres, + printf("Setting up a %dx%d%s %s console (overscan %dx%d)\n", + mode->xres, mode->yres, (mode->vmode == FB_VMODE_INTERLACED) ? "i" : "", - sunxi_get_mon_desc(sunxi_display.monitor)); + sunxi_get_mon_desc(sunxi_display.monitor), + overscan_x, overscan_y); gd->fb_base = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sunxi_display.fb_size; sunxi_engines_init(); - sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE); + + fb_dma_addr = gd->fb_base - CONFIG_SYS_SDRAM_BASE; + sunxi_display.fb_addr = gd->fb_base; + if (overscan_offset) { + fb_dma_addr += 0x1000 - (overscan_offset & 0xfff); + sunxi_display.fb_addr += (overscan_offset + 0xfff) & ~0xfff; + memset((void *)gd->fb_base, 0, sunxi_display.fb_size); + flush_cache(gd->fb_base, sunxi_display.fb_size); + } + sunxi_mode_set(mode, fb_dma_addr); /* * These are the only members of this structure that are used. All the - * others are driver specific. There is nothing to decribe pitch or - * stride, but we are lucky with our hw. + * others are driver specific. The pitch is stored in plnSizeX. */ - graphic_device->frameAdrs = gd->fb_base; + graphic_device->frameAdrs = sunxi_display.fb_addr; graphic_device->gdfIndex = GDF_32BIT_X888RGB; graphic_device->gdfBytesPP = 4; - graphic_device->winSizeX = mode->xres; - graphic_device->winSizeY = mode->yres; + graphic_device->winSizeX = mode->xres - 2 * overscan_x; + graphic_device->winSizeY = mode->yres - 2 * overscan_y; + graphic_device->plnSizeX = mode->xres * graphic_device->gdfBytesPP; return graphic_device; } @@ -1490,10 +1573,9 @@ int sunxi_simplefb_setup(void *blob) return ret; } - ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base, + ret = fdt_setup_simplefb_node(blob, offset, sunxi_display.fb_addr, graphic_device->winSizeX, graphic_device->winSizeY, - graphic_device->winSizeX * graphic_device->gdfBytesPP, - "x8r8g8b8"); + graphic_device->plnSizeX, "x8r8g8b8"); if (ret) eprintf("Cannot setup simplefb: Error setting properties\n"); diff --git a/include/configs/canmb.h b/include/configs/canmb.h index c656378..36cd50b 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -15,6 +15,8 @@ #define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO /* * allowed and functional CONFIG_SYS_TEXT_BASE values: diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index c7bf531..d3034cf 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -18,6 +18,8 @@ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_INKA4X0 1 /* INKA4x0 board */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO /* * Valid values for CONFIG_SYS_TEXT_BASE are: diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h index 230f2c4..3f6f8dd 100644 --- a/include/configs/ipek01.h +++ b/include/configs/ipek01.h @@ -19,6 +19,8 @@ #define CONFIG_MPX5200 1 /* MPX5200 board */ #define CONFIG_MPC5200_DDR 1 /* use DDR RAM */ #define CONFIG_IPEK01 /* Motherboard is ipek01 */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0xfc000000 diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 65b3df6..5601cb4 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -15,6 +15,8 @@ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_JUPITER 1 /* ... on Jupiter board */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO /* * Valid values for CONFIG_SYS_TEXT_BASE are: diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 6dc84eb..3b97d91 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -17,6 +17,8 @@ /* CPU and board */ #define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_HIGH_BATS 1 /* High BATs supported */ diff --git a/include/configs/munices.h b/include/configs/munices.h index 42ac029..b1b6acd 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -14,6 +14,7 @@ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ #define CONFIG_MUNICES 1 /* ... on MUNICes board */ +#define CONFIG_SYS_GENERIC_BOARD #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFF00000 diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h index 29feb7b..4ea617a 100644 --- a/include/configs/pcm030.h +++ b/include/configs/pcm030.h @@ -15,6 +15,7 @@ #define __CONFIG_H #define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny" +#define CONFIG_SYS_GENERIC_BOARD /*----------------------------------------------------------------------------- High Level Configuration Options diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 292b514..50911ae 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -27,6 +27,8 @@ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC8544 1 #define CONFIG_SOCRATES 1 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 0ecb91b..1abf73c 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -288,7 +288,11 @@ extern int soft_i2c_gpio_scl; * The amount of RAM to keep free at the top of RAM when relocating u-boot, * to use as framebuffer. This must be a multiple of 4096. */ +#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 +#define CONFIG_SUNXI_MAX_FB_SIZE (12 << 20) +#else #define CONFIG_SUNXI_MAX_FB_SIZE (9 << 20) +#endif /* Do we want to initialize a simple FB? */ #define CONFIG_VIDEO_DT_SIMPLEFB @@ -300,6 +304,7 @@ extern int soft_i2c_gpio_scl; #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_STD_TIMINGS #define CONFIG_I2C_EDID +#define VIDEO_LINE_LEN (pGD->plnSizeX) /* allow both serial and cfb console. */ #define CONFIG_CONSOLE_MUX diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index fe04692..1c1f8c0 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -79,6 +79,7 @@ "vram=16M\0" \ "partitions=" PARTS_DEFAULT "\0" \ "optargs=\0" \ + "dofastboot=0\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ "mmcrootfstype=ext4 rootwait\0" \ diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 63049ab..3e51b9f 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -14,6 +14,8 @@ */ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_V38B 1 /* ...on V38B board */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0xFF000000 |