diff options
| -rw-r--r-- | drivers/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/Makefile | 1 | ||||
| -rw-r--r-- | drivers/phy/marvell/Kconfig | 9 | ||||
| -rw-r--r-- | drivers/phy/marvell/Makefile | 7 | ||||
| -rw-r--r-- | drivers/phy/marvell/comphy.h | 139 | ||||
| -rw-r--r-- | drivers/phy/marvell/comphy_a3700.c | 962 | ||||
| -rw-r--r-- | drivers/phy/marvell/comphy_a3700.h | 275 | ||||
| -rw-r--r-- | drivers/phy/marvell/comphy_core.c | 197 | ||||
| -rw-r--r-- | drivers/phy/marvell/comphy_hpipe.h | 382 | ||||
| -rw-r--r-- | drivers/phy/marvell/comphy_mux.c | 118 | ||||
| -rw-r--r-- | include/dt-bindings/comphy/comphy_data.h | 61 |
11 files changed, 2153 insertions, 0 deletions
diff --git a/drivers/Kconfig b/drivers/Kconfig index 4c555a0..e8c9e0a 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -48,6 +48,8 @@ source "drivers/pci/Kconfig" source "drivers/pcmcia/Kconfig" +source "drivers/phy/marvell/Kconfig" + source "drivers/pinctrl/Kconfig" source "drivers/power/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index ca98273..761d0b3 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -70,6 +70,7 @@ obj-y += misc/ obj-y += pcmcia/ obj-y += dfu/ obj-$(CONFIG_X86) += pch/ +obj-y += phy/marvell/ obj-y += rtc/ obj-y += sound/ obj-y += spmi/ diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig new file mode 100644 index 0000000..4240028 --- /dev/null +++ b/drivers/phy/marvell/Kconfig @@ -0,0 +1,9 @@ +config MVEBU_COMPHY_SUPPORT + bool "ComPhy SerDes driver" + default n + help + Choose this option to add support + for Comphy driver. + This driver passes over the lanes + and initialize the lane depends on the + type and speed. diff --git a/drivers/phy/marvell/Makefile b/drivers/phy/marvell/Makefile new file mode 100644 index 0000000..91df554 --- /dev/null +++ b/drivers/phy/marvell/Makefile @@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_MVEBU_COMPHY_SUPPORT) += comphy_core.o +obj-$(CONFIG_MVEBU_COMPHY_SUPPORT) += comphy_mux.o +obj-$(CONFIG_ARMADA_3700) += comphy_a3700.o diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h new file mode 100644 index 0000000..5c50e9c --- /dev/null +++ b/drivers/phy/marvell/comphy.h @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2015-2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _COMPHY_H_ +#define _COMPHY_H_ + +#include <dt-bindings/comphy/comphy_data.h> +#include <fdtdec.h> + +#if defined(DEBUG) +#define debug_enter() printf("----> Enter %s\n", __func__); +#define debug_exit() printf("<---- Exit %s\n", __func__); +#else +#define debug_enter() +#define debug_exit() +#endif + +/* COMPHY registers */ +#define COMMON_PHY_CFG1_REG 0x0 +#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1 +#define COMMON_PHY_CFG1_PWR_UP_MASK \ + (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET) +#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2 +#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \ + (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET) +#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13 +#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \ + (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET) +#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14 +#define COMMON_PHY_CFG1_CORE_RSTN_MASK \ + (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET) +#define COMMON_PHY_PHY_MODE_OFFSET 15 +#define COMMON_PHY_PHY_MODE_MASK \ + (0x1 << COMMON_PHY_PHY_MODE_OFFSET) + +#define COMMON_PHY_CFG6_REG 0x14 +#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18 +#define COMMON_PHY_CFG6_IF_40_SEL_MASK \ + (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET) + +#define COMMON_SELECTOR_PHY_OFFSET 0x140 +#define COMMON_SELECTOR_PIPE_OFFSET 0x144 + +#define COMMON_PHY_SD_CTRL1 0x148 +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0 +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24 +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET) +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25 +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET) +#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26 +#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET) +#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27 +#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET) + +#define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280) +#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7 +#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \ + (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET) + +#define MAX_LANE_OPTIONS 10 +#define MAX_UTMI_PHY_COUNT 2 + +struct comphy_mux_options { + u32 type; + u32 mux_value; +}; + +struct comphy_mux_data { + u32 max_lane_values; + struct comphy_mux_options mux_values[MAX_LANE_OPTIONS]; +}; + +struct comphy_map { + u32 type; + u32 speed; + u32 invert; + bool clk_src; +}; + +struct chip_serdes_phy_config { + struct comphy_mux_data *mux_data; + int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *, + struct comphy_map *); + void __iomem *comphy_base_addr; + void __iomem *hpipe3_base_addr; + u32 comphy_lanes_count; + u32 comphy_mux_bitcount; + u32 comphy_index; +}; + +/* Register helper functions */ +void reg_set(void __iomem *addr, u32 data, u32 mask); +void reg_set_silent(void __iomem *addr, u32 data, u32 mask); +void reg_set16(void __iomem *addr, u16 data, u16 mask); +void reg_set_silent16(void __iomem *addr, u16 data, u16 mask); + +/* SoC specific init functions */ +#ifdef CONFIG_ARMADA_3700 +int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg, + struct comphy_map *serdes_map); +#else +static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg, + struct comphy_map *serdes_map) +{ + /* + * This function should never be called in this configuration, so + * lets return an error here. + */ + return -1; +} +#endif +int comphy_ap806_init(struct chip_serdes_phy_config *ptr_chip_cfg, + struct comphy_map *serdes_map); +int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, + struct comphy_map *serdes_map); + +void comphy_dedicated_phys_init(void); + +/* MUX function */ +void comphy_mux_init(struct chip_serdes_phy_config *ptr_chip_cfg, + struct comphy_map *comphy_map_data, + void __iomem *selector_base); + +void comphy_pcie_config_set(u32 comphy_max_count, + struct comphy_map *serdes_map); +void comphy_pcie_config_detect(u32 comphy_max_count, + struct comphy_map *serdes_map); +void comphy_pcie_unit_general_config(u32 pex_index); + +#endif /* _COMPHY_H_ */ + diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c new file mode 100644 index 0000000..faa62f9 --- /dev/null +++ b/drivers/phy/marvell/comphy_a3700.c @@ -0,0 +1,962 @@ +/* + * Copyright (C) 2015-2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +#include "comphy_a3700.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct sgmii_phy_init_data_fix { + u16 addr; + u16 value; +}; + +/* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ +static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = { + {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000}, + {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030}, + {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC}, + {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA}, + {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550}, + {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0}, + {0x104, 0x0C10} +}; + +/* 40M1G25 mode init data */ +static u16 sgmii_phy_init[512] = { + /* 0 1 2 3 4 5 6 7 */ + /*-----------------------------------------------------------*/ + /* 8 9 A B C D E F */ + 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ + 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ + 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ + 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ + 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ + 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ + 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ + 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ + 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ + 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ + 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ + 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ + 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ + 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ + 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ + 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ + 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ + 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ + 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ + 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ + 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ + 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ + 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ + 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ + 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ + 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ + 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ + 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ + 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ + 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ + 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ + 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ + 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ + 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ +}; + +/* + * comphy_poll_reg + * + * return: 1 on success, 0 on timeout + */ +static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u32 timeout, + u8 op_type) +{ + u32 rval = 0xDEAD; + + for (; timeout > 0; timeout--) { + if (op_type == POLL_16B_REG) + rval = readw(addr); /* 16 bit */ + else + rval = readl(addr) ; /* 32 bit */ + + if ((rval & mask) == val) + return 1; + + udelay(10000); + } + + debug("Time out waiting (%p = %#010x)\n", addr, rval); + return 0; +} + +/* + * comphy_pcie_power_up + * + * return: 1 if PLL locked (OK), 0 otherwise (FAIL) + */ +static int comphy_pcie_power_up(u32 speed, u32 invert) +{ + int ret; + + debug_enter(); + + /* + * 1. Enable max PLL. + */ + reg_set16((void __iomem *)LANE_CFG1_ADDR(PCIE), + bf_use_max_pll_rate, 0); + + /* + * 2. Select 20 bit SERDES interface. + */ + reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(PCIE), + bf_cfg_sel_20b, 0); + + /* + * 3. Force to use reg setting for PCIe mode + */ + reg_set16((void __iomem *)MISC_REG1_ADDR(PCIE), + bf_sel_bits_pcie_force, 0); + + /* + * 4. Change RX wait + */ + reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0xFFFF); + + /* + * 5. Enable idle sync + */ + reg_set16((void __iomem *)UNIT_CTRL_ADDR(PCIE), + 0x60 | rb_idle_sync_en, 0xFFFF); + + /* + * 6. Enable the output of 100M/125M/500M clock + */ + reg_set16((void __iomem *)MISC_REG0_ADDR(PCIE), + 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF); + + /* + * 7. Enable TX + */ + reg_set((void __iomem *)PHY_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF); + + /* + * 8. Check crystal jumper setting and program the Power and PLL + * Control accordingly + */ + if (get_ref_clk() == 40) { + reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE), + 0xFC63, 0xFFFF); /* 40 MHz */ + } else { + reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE), + 0xFC62, 0xFFFF); /* 25 MHz */ + } + + /* + * 9. Override Speed_PLL value and use MAC PLL + */ + reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(PCIE), + 0x0040 | rb_use_max_pll_rate, 0xFFFF); + + /* + * 10. Check the Polarity invert bit + */ + if (invert & PHY_POLARITY_TXD_INVERT) { + reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE), + phy_txd_inv, 0); + } + + if (invert & PHY_POLARITY_RXD_INVERT) { + reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE), + phy_rxd_inv, 0); + } + + /* + * 11. Release SW reset + */ + reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(PCIE), + rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32, + bf_soft_rst | bf_mode_refdiv); + + /* Wait for > 55 us to allow PCLK be enabled */ + udelay(PLL_SET_DELAY_US); + + /* Assert PCLK enabled */ + ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(PCIE), /* address */ + rb_txdclk_pclk_en, /* value */ + rb_txdclk_pclk_en, /* mask */ + PLL_LOCK_TIMEOUT, /* timeout */ + POLL_16B_REG); /* 16bit */ + if (ret == 0) + printf("Failed to lock PCIe PLL\n"); + + debug_exit(); + + /* Return the status of the PLL */ + return ret; +} + +/* + * comphy_sata_power_up + * + * return: 1 if PLL locked (OK), 0 otherwise (FAIL) + */ +static int comphy_sata_power_up(void) +{ + int ret; + + debug_enter(); + + /* + * 0. Swap SATA TX lines + */ + reg_set((void __iomem *)rh_vsreg_addr, + vphy_sync_pattern_reg, 0xFFFFFFFF); + reg_set((void __iomem *)rh_vsreg_data, bs_txd_inv, bs_txd_inv); + + /* + * 1. Select 40-bit data width width + */ + reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); + reg_set((void __iomem *)rh_vsreg_data, 0x800, bs_phyintf_40bit); + + /* + * 2. Select reference clock and PHY mode (SATA) + */ + reg_set((void __iomem *)rh_vsreg_addr, vphy_power_reg0, 0xFFFFFFFF); + if (get_ref_clk() == 40) { + reg_set((void __iomem *)rh_vsreg_data, + 0x3, 0x00FF); /* 40 MHz */ + } else { + reg_set((void __iomem *)rh_vsreg_data, + 0x1, 0x00FF); /* 25 MHz */ + } + + /* + * 3. Use maximum PLL rate (no power save) + */ + reg_set((void __iomem *)rh_vsreg_addr, vphy_calctl_reg, 0xFFFFFFFF); + reg_set((void __iomem *)rh_vsreg_data, + bs_max_pll_rate, bs_max_pll_rate); + + /* + * 4. Reset reserved bit (??) + */ + reg_set((void __iomem *)rh_vsreg_addr, vphy_reserve_reg, 0xFFFFFFFF); + reg_set((void __iomem *)rh_vsreg_data, 0, bs_phyctrl_frm_pin); + + /* + * 5. Set vendor-specific configuration (??) + */ + reg_set((void __iomem *)rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF); + reg_set((void __iomem *)rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll); + + /* Wait for > 55 us to allow PLL be enabled */ + udelay(PLL_SET_DELAY_US); + + /* Assert SATA PLL enabled */ + reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); + ret = comphy_poll_reg((void *)rh_vsreg_data, /* address */ + bs_pll_ready_tx, /* value */ + bs_pll_ready_tx, /* mask */ + PLL_LOCK_TIMEOUT, /* timeout */ + POLL_32B_REG); /* 32bit */ + if (ret == 0) + printf("Failed to lock SATA PLL\n"); + + debug_exit(); + + return ret; +} + +/* + * comphy_usb3_power_up + * + * return: 1 if PLL locked (OK), 0 otherwise (FAIL) + */ +static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) +{ + int ret; + + debug_enter(); + + /* + * 1. Power up OTG module + */ + reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); + + /* + * 2. Set counter for 100us pulse in USB3 Host and Device + * restore default burst size limit (Reference Clock 31:24) + */ + reg_set((void __iomem *)USB3_CTRPUL_VAL_REG, + 0x8 << 24, rb_usb3_ctr_100ns); + + + /* 0xd005c300 = 0x1001 */ + /* set PRD_TXDEEMPH (3.5db de-emph) */ + reg_set16((void __iomem *)LANE_CFG0_ADDR(USB3), 0x1, 0xFF); + + /* + * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in + * low impedance mode during electrical idle + */ + /* unset BIT4: set G2 Tx Datapath with no Delayed Latency */ + /* unset BIT6: set Tx Detect Rx Mode at LoZ mode */ + reg_set16((void __iomem *)LANE_CFG1_ADDR(USB3), 0x0, 0xFFFF); + + + /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */ + reg_set16((void __iomem *)LANE_CFG4_ADDR(USB3), + bf_spread_spectrum_clock_en, 0x80); + + /* + * set Override Margining Controls From the MAC: Use margining signals + * from lane configuration + */ + reg_set16((void __iomem *)TEST_MODE_CTRL_ADDR(USB3), + rb_mode_margin_override, 0xFFFF); + + /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */ + /* set Mode Clock Source = PCLK is generated from REFCLK */ + reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(USB3), 0x0, 0xFF); + + /* set G2 Spread Spectrum Clock Amplitude at 4K */ + reg_set16((void __iomem *)GEN2_SETTING_2_ADDR(USB3), g2_tx_ssc_amp, + 0xF000); + + /* + * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register + * Master Current Select + */ + reg_set16((void __iomem *)GEN2_SETTING_3_ADDR(USB3), 0x0, 0xFFFF); + + /* + * 3. Check crystal jumper setting and program the Power and PLL + * Control accordingly + */ + if (get_ref_clk() == 40) { + reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA3, + 0xFFFF); /* 40 MHz */ + } else { + reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA2, + 0xFFFF); /* 25 MHz */ + } + + /* + * 4. Change RX wait + */ + reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(USB3), 0x10C, 0xFFFF); + + /* + * 5. Enable idle sync + */ + reg_set16((void __iomem *)UNIT_CTRL_ADDR(USB3), 0x60 | rb_idle_sync_en, + 0xFFFF); + + /* + * 6. Enable the output of 500M clock + */ + reg_set16((void __iomem *)MISC_REG0_ADDR(USB3), 0xA00D | rb_clk500m_en, + 0xFFFF); + + /* + * 7. Set 20-bit data width + */ + reg_set16((void __iomem *)DIG_LB_EN_ADDR(USB3), 0x0400, 0xFFFF); + + /* + * 8. Override Speed_PLL value and use MAC PLL + */ + reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(USB3), + 0x0040 | rb_use_max_pll_rate, 0xFFFF); + + /* + * 9. Check the Polarity invert bit + */ + if (invert & PHY_POLARITY_TXD_INVERT) { + reg_set16((void __iomem *)SYNC_PATTERN_ADDR(USB3), + phy_txd_inv, 0); + } + + if (invert & PHY_POLARITY_RXD_INVERT) { + reg_set16((void __iomem *)SYNC_PATTERN_ADDR(USB3), + phy_rxd_inv, 0); + } + + /* + * 10. Release SW reset + */ + reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(USB3), + rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 | 0x20, + 0xFFFF); + + /* Wait for > 55 us to allow PCLK be enabled */ + udelay(PLL_SET_DELAY_US); + + /* Assert PCLK enabled */ + ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(USB3), /* address */ + rb_txdclk_pclk_en, /* value */ + rb_txdclk_pclk_en, /* mask */ + PLL_LOCK_TIMEOUT, /* timeout */ + POLL_16B_REG); /* 16bit */ + if (ret == 0) + printf("Failed to lock USB3 PLL\n"); + + /* + * Set Soft ID for Host mode (Device mode works with Hard ID + * detection) + */ + if (type == PHY_TYPE_USB3_HOST0) { + /* + * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1) + * clear BIT1: set SOFT_ID = Host + * set BIT4: set INT_MODE = ID. Interrupt Mode: enable + * interrupt by ID instead of using both interrupts + * of HOST and Device ORed simultaneously + * INT_MODE=ID in order to avoid unexpected + * behaviour or both interrupts together + */ + reg_set((void __iomem *)USB32_CTRL_BASE, + usb32_ctrl_id_mode | usb32_ctrl_int_mode, + usb32_ctrl_id_mode | usb32_ctrl_soft_id | + usb32_ctrl_int_mode); + } + + debug_exit(); + + return ret; +} + +/* + * comphy_usb2_power_up + * + * return: 1 if PLL locked (OK), 0 otherwise (FAIL) + */ +static int comphy_usb2_power_up(u8 usb32) +{ + int ret; + + debug_enter(); + + if (usb32 != 0 && usb32 != 1) { + printf("invalid usb32 value: (%d), should be either 0 or 1\n", + usb32); + debug_exit(); + return 0; + } + + /* + * 0. Setup PLL. 40MHz clock uses defaults. + * See "PLL Settings for Typical REFCLK" table + */ + if (get_ref_clk() == 25) { + reg_set((void __iomem *)USB2_PHY_BASE(usb32), + 5 | (96 << 16), 0x3F | (0xFF << 16) | (0x3 << 28)); + } + + /* + * 1. PHY pull up and disable USB2 suspend + */ + reg_set((void __iomem *)USB2_PHY_CTRL_ADDR(usb32), + RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU(usb32), 0); + + if (usb32 != 0) { + /* + * 2. Power up OTG module + */ + reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); + + /* + * 3. Configure PHY charger detection + */ + reg_set((void __iomem *)USB2_PHY_CHRGR_DET_ADDR, 0, + rb_cdp_en | rb_dcp_en | rb_pd_en | rb_cdp_dm_auto | + rb_enswitch_dp | rb_enswitch_dm | rb_pu_chrg_dtc); + } + + /* Assert PLL calibration done */ + ret = comphy_poll_reg((void *)USB2_PHY_CAL_CTRL_ADDR(usb32), + rb_usb2phy_pllcal_done, /* value */ + rb_usb2phy_pllcal_done, /* mask */ + PLL_LOCK_TIMEOUT, /* timeout */ + POLL_32B_REG); /* 32bit */ + if (ret == 0) + printf("Failed to end USB2 PLL calibration\n"); + + /* Assert impedance calibration done */ + ret = comphy_poll_reg((void *)USB2_PHY_CAL_CTRL_ADDR(usb32), + rb_usb2phy_impcal_done, /* value */ + rb_usb2phy_impcal_done, /* mask */ + PLL_LOCK_TIMEOUT, /* timeout */ + POLL_32B_REG); /* 32bit */ + if (ret == 0) + printf("Failed to end USB2 impedance calibration\n"); + + /* Assert squetch calibration done */ + ret = comphy_poll_reg((void *)USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32), + rb_usb2phy_sqcal_done, /* value */ + rb_usb2phy_sqcal_done, /* mask */ + PLL_LOCK_TIMEOUT, /* timeout */ + POLL_32B_REG); /* 32bit */ + if (ret == 0) + printf("Failed to end USB2 unknown calibration\n"); + + /* Assert PLL is ready */ + ret = comphy_poll_reg((void *)USB2_PHY_PLL_CTRL0_ADDR(usb32), + rb_usb2phy_pll_ready, /* value */ + rb_usb2phy_pll_ready, /* mask */ + PLL_LOCK_TIMEOUT, /* timeout */ + POLL_32B_REG); /* 32bit */ + + if (ret == 0) + printf("Failed to lock USB2 PLL\n"); + + debug_exit(); + + return ret; +} + +/* + * comphy_emmc_power_up + * + * return: 1 if PLL locked (OK), 0 otherwise (FAIL) + */ +static int comphy_emmc_power_up(void) +{ + debug_enter(); + + /* + * 1. Bus power ON, Bus voltage 1.8V + */ + reg_set((void __iomem *)SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00); + + /* + * 2. Set FIFO parameters + */ + reg_set((void __iomem *)SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF); + + /* + * 3. Set Capabilities 1_2 + */ + reg_set((void __iomem *)SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF); + + /* + * 4. Set Endian + */ + reg_set((void __iomem *)SDIO_ENDIAN_ADDR, 0x00c00000, 0); + + /* + * 4. Init PHY + */ + reg_set((void __iomem *)SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000); + reg_set((void __iomem *)SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000, + 0xF0000000); + + /* + * 5. DLL reset + */ + reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0); + reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0x00010000, 0); + + debug_exit(); + + return 1; +} + +/* + * comphy_sgmii_power_up + * + * return: + */ +static void comphy_sgmii_phy_init(u32 lane, u32 speed) +{ + const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix); + int addr, fix_idx; + u16 val; + + fix_idx = 0; + for (addr = 0; addr < 512; addr++) { + /* + * All PHY register values are defined in full for 3.125Gbps + * SERDES speed. The values required for 1.25 Gbps are almost + * the same and only few registers should be "fixed" in + * comparison to 3.125 Gbps values. These register values are + * stored in "sgmii_phy_init_fix" array. + */ + if ((speed != PHY_SPEED_1_25G) && + (sgmii_phy_init_fix[fix_idx].addr == addr)) { + /* Use new value */ + val = sgmii_phy_init_fix[fix_idx].value; + if (fix_idx < fix_arr_sz) + fix_idx++; + } else { + val = sgmii_phy_init[addr]; + } + + phy_write16(lane, addr, val, 0xFFFF); + } +} + +/* + * comphy_sgmii_power_up + * + * return: 1 if PLL locked (OK), 0 otherwise (FAIL) + */ +static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) +{ + int ret; + + debug_enter(); + + /* + * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0 + */ + reg_set((void __iomem *)COMPHY_SEL_ADDR, 0, rf_compy_select(lane)); + + /* + * 2. Reset PHY by setting PHY input port PIN_RESET=1. + * 3. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep + * PHY TXP/TXN output to idle state during PHY initialization + * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. + */ + reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), + rb_pin_reset_comphy | rb_pin_tx_idle | rb_pin_pu_iveref, + rb_pin_reset_core | rb_pin_pu_pll | + rb_pin_pu_rx | rb_pin_pu_tx); + + /* + * 5. Release reset to the PHY by setting PIN_RESET=0. + */ + reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), + 0, rb_pin_reset_comphy); + + /* + * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide + * COMPHY bit rate + */ + if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */ + reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), + (0x8 << rf_gen_rx_sel_shift) | + (0x8 << rf_gen_tx_sel_shift), + rf_gen_rx_select | rf_gen_tx_select); + + } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */ + reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), + (0x6 << rf_gen_rx_sel_shift) | + (0x6 << rf_gen_tx_sel_shift), + rf_gen_rx_select | rf_gen_tx_select); + } else { + printf("Unsupported COMPHY speed!\n"); + return 0; + } + + /* + * 8. Wait 1mS for bandgap and reference clocks to stabilize; + * then start SW programming. + */ + mdelay(10); + + /* 9. Program COMPHY register PHY_MODE */ + phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, + PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask); + + /* + * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK + * source + */ + phy_write16(lane, PHY_MISC_REG0_ADDR, 0, rb_ref_clk_sel); + + /* + * 11. Set correct reference clock frequency in COMPHY register + * REF_FREF_SEL. + */ + if (get_ref_clk() == 40) { + phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, + 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); + } else { + /* 25MHz */ + phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, + 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); + } + + /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */ + /* + * This step is mentioned in the flow received from verification team. + * However the PHY_GEN_MAX value is only meaningful for other + * interfaces (not SGMII). For instance, it selects SATA speed + * 1.5/3/6 Gbps or PCIe speed 2.5/5 Gbps + */ + + /* + * 13. Program COMPHY register SEL_BITS to set correct parallel data + * bus width + */ + /* 10bit */ + phy_write16(lane, PHY_DIG_LB_EN_ADDR, 0, rf_data_width_mask); + + /* + * 14. As long as DFE function needs to be enabled in any mode, + * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F + * for real chip during COMPHY power on. + */ + /* + * The step 14 exists (and empty) in the original initialization flow + * obtained from the verification team. According to the functional + * specification DFE_UPDATE_EN already has the default value 0x3F + */ + + /* + * 15. Program COMPHY GEN registers. + * These registers should be programmed based on the lab testing + * result to achieve optimal performance. Please contact the CEA + * group to get the related GEN table during real chip bring-up. + * We only requred to run though the entire registers programming + * flow defined by "comphy_sgmii_phy_init" when the REF clock is + * 40 MHz. For REF clock 25 MHz the default values stored in PHY + * registers are OK. + */ + debug("Running C-DPI phy init %s mode\n", + speed == PHY_SPEED_3_125G ? "2G5" : "1G"); + if (get_ref_clk() == 40) + comphy_sgmii_phy_init(lane, speed); + + /* + * 16. [Simulation Only] should not be used for real chip. + * By pass power up calibration by programming EXT_FORCE_CAL_DONE + * (R02h[9]) to 1 to shorten COMPHY simulation time. + */ + /* + * 17. [Simulation Only: should not be used for real chip] + * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX + * training simulation time. + */ + + /* + * 18. Check the PHY Polarity invert bit + */ + if (invert & PHY_POLARITY_TXD_INVERT) + phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_txd_inv, 0); + + if (invert & PHY_POLARITY_RXD_INVERT) + phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_rxd_inv, 0); + + /* + * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 + * to start PHY power up sequence. All the PHY register + * programming should be done before PIN_PU_PLL=1. There should be + * no register programming for normal PHY operation from this point. + */ + reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), + rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx, + rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx); + + /* + * 20. Wait for PHY power up sequence to finish by checking output ports + * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. + */ + ret = comphy_poll_reg((void *)COMPHY_PHY_STAT1_ADDR(lane), /* address */ + rb_pll_ready_tx | rb_pll_ready_rx, /* value */ + rb_pll_ready_tx | rb_pll_ready_rx, /* mask */ + PLL_LOCK_TIMEOUT, /* timeout */ + POLL_32B_REG); /* 32bit */ + if (ret == 0) + printf("Failed to lock PLL for SGMII PHY %d\n", lane); + + /* + * 21. Set COMPHY input port PIN_TX_IDLE=0 + */ + reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), + 0x0, rb_pin_tx_idle); + + /* + * 22. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. + * to start RX initialization. PIN_RX_INIT_DONE will be cleared to + * 0 by the PHY. After RX initialization is done, PIN_RX_INIT_DONE + * will be set to 1 by COMPHY. Set PIN_RX_INIT=0 after + * PIN_RX_INIT_DONE= 1. + * Please refer to RX initialization part for details. + */ + reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, + 0x0); + + ret = comphy_poll_reg((void *)COMPHY_PHY_STAT1_ADDR(lane), /* address */ + rb_rx_init_done, /* value */ + rb_rx_init_done, /* mask */ + PLL_LOCK_TIMEOUT, /* timeout */ + POLL_32B_REG); /* 32bit */ + if (ret == 0) + printf("Failed to init RX of SGMII PHY %d\n", lane); + + debug_exit(); + + return ret; +} + +void comphy_dedicated_phys_init(void) +{ + int node, usb32, ret = 1; + const void *blob = gd->fdt_blob; + + debug_enter(); + + for (usb32 = 0; usb32 <= 1; usb32++) { + /* + * There are 2 UTMI PHYs in this SOC. + * One is independendent and one is paired with USB3 port (OTG) + */ + if (usb32 == 0) { + node = fdt_node_offset_by_compatible( + blob, -1, "marvell,armada-3700-ehci"); + } else { + node = fdt_node_offset_by_compatible( + blob, -1, "marvell,armada3700-xhci"); + } + + if (node > 0) { + if (fdtdec_get_is_enabled(blob, node)) { + ret = comphy_usb2_power_up(usb32); + if (ret == 0) + printf("Failed to initialize UTMI PHY\n"); + else + debug("UTMI PHY init succeed\n"); + } else { + debug("USB%d node is disabled\n", + usb32 == 0 ? 2 : 3); + } + } else { + debug("No USB%d node in DT\n", usb32 == 0 ? 2 : 3); + } + } + + node = fdt_node_offset_by_compatible(blob, -1, + "marvell,armada-3700-ahci"); + if (node > 0) { + if (fdtdec_get_is_enabled(blob, node)) { + ret = comphy_sata_power_up(); + if (ret == 0) + printf("Failed to initialize SATA PHY\n"); + else + debug("SATA PHY init succeed\n"); + } else { + debug("SATA node is disabled\n"); + } + } else { + debug("No SATA node in DT\n"); + } + + node = fdt_node_offset_by_compatible(blob, -1, + "marvell,armada-3700-sdio"); + if (node <= 0) { + debug("No SDIO node in DT, looking for MMC one\n"); + node = fdt_node_offset_by_compatible(blob, -1, + "marvell,xenon-sdhci"); + } + + if (node > 0) { + if (fdtdec_get_is_enabled(blob, node)) { + ret = comphy_emmc_power_up(); + if (ret == 0) + printf("Failed to initialize SDIO/eMMC PHY\n"); + else + debug("SDIO/eMMC PHY init succeed\n"); + } else { + debug("SDIO/eMMC node is disabled\n"); + } + } else { + debug("No SDIO/eMMC node in DT\n"); + } + + debug_exit(); +} + +int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, + struct comphy_map *serdes_map) +{ + struct comphy_map *comphy_map; + u32 comphy_max_count = chip_cfg->comphy_lanes_count; + u32 lane, ret = 0; + + debug_enter(); + + for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count; + lane++, comphy_map++) { + debug("Initialize serdes number %d\n", lane); + debug("Serdes type = 0x%x invert=%d\n", + comphy_map->type, comphy_map->invert); + + switch (comphy_map->type) { + case PHY_TYPE_UNCONNECTED: + continue; + break; + + case PHY_TYPE_PEX0: + ret = comphy_pcie_power_up(comphy_map->speed, + comphy_map->invert); + break; + + case PHY_TYPE_USB3_HOST0: + case PHY_TYPE_USB3_DEVICE: + ret = comphy_usb3_power_up(comphy_map->type, + comphy_map->speed, + comphy_map->invert); + break; + + case PHY_TYPE_SGMII0: + case PHY_TYPE_SGMII1: + ret = comphy_sgmii_power_up(lane, comphy_map->speed, + comphy_map->invert); + break; + + default: + debug("Unknown SerDes type, skip initialize SerDes %d\n", + lane); + ret = 1; + break; + } + if (ret == 0) + printf("PLL is not locked - Failed to initialize lane %d\n", + lane); + } + + debug_exit(); + return ret; +} diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h new file mode 100644 index 0000000..eb2ed7b --- /dev/null +++ b/drivers/phy/marvell/comphy_a3700.h @@ -0,0 +1,275 @@ +/* + * Copyright (C) 2015-2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _COMPHY_A3700_H_ +#define _COMPHY_A3700_H_ + +#include "comphy.h" +#include "comphy_hpipe.h" + +#define MVEBU_REG(offs) ((uintptr_t)MVEBU_REGISTER(offs)) + +#define DEFAULT_REFCLK_MHZ 25 +#define PLL_SET_DELAY_US 600 +#define PLL_LOCK_TIMEOUT 1000 +#define POLL_16B_REG 1 +#define POLL_32B_REG 0 + +/* + * COMPHY SB definitions + */ +#define COMPHY_SEL_ADDR MVEBU_REG(0x0183FC) +#define rf_compy_select(lane) (0x1 << (((lane) == 1) ? 4 : 0)) + +#define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (lane) * 0x28) +#define rb_pin_pu_iveref BIT(1) +#define rb_pin_reset_core BIT(11) +#define rb_pin_reset_comphy BIT(12) +#define rb_pin_pu_pll BIT(16) +#define rb_pin_pu_rx BIT(17) +#define rb_pin_pu_tx BIT(18) +#define rb_pin_tx_idle BIT(19) +#define rf_gen_rx_sel_shift 22 +#define rf_gen_rx_select (0xFF << rf_gen_rx_sel_shift) +#define rf_gen_tx_sel_shift 26 +#define rf_gen_tx_select (0xFF << rf_gen_tx_sel_shift) +#define rb_phy_rx_init BIT(30) + +#define COMPHY_PHY_STAT1_ADDR(lane) MVEBU_REG(0x018318 + (lane) * 0x28) +#define rb_rx_init_done BIT(0) +#define rb_pll_ready_rx BIT(2) +#define rb_pll_ready_tx BIT(3) + +/* + * PCIe/USB/SGMII definitions + */ +#define PCIE_BASE MVEBU_REG(0x070000) +#define PCIETOP_BASE MVEBU_REG(0x080000) +#define PCIE_RAMBASE MVEBU_REG(0x08C000) +#define PCIEPHY_BASE MVEBU_REG(0x01F000) +#define PCIEPHY_SHFT 2 + +#define USB32_BASE MVEBU_REG(0x050000) /* usb3 device */ +#define USB32H_BASE MVEBU_REG(0x058000) /* usb3 host */ +#define USB3PHY_BASE MVEBU_REG(0x05C000) +#define USB2PHY_BASE MVEBU_REG(0x05D000) +#define USB2PHY2_BASE MVEBU_REG(0x05F000) +#define USB32_CTRL_BASE MVEBU_REG(0x05D800) +#define USB3PHY_SHFT 2 + +#define SGMIIPHY_BASE(l) (l == 1 ? USB3PHY_BASE : PCIEPHY_BASE) +#define SGMIIPHY_ADDR(l, a) (((a & 0x00007FF) * 2) | SGMIIPHY_BASE(l)) + +#define phy_read16(l, a) read16((void __iomem *)SGMIIPHY_ADDR(l, a)) +#define phy_write16(l, a, data, mask) \ + reg_set16((void __iomem *)SGMIIPHY_ADDR(l, a), data, mask) + +/* units */ +#define PCIE 1 +#define USB3 2 + +#define PHY_BASE(unit) ((unit == PCIE) ? PCIEPHY_BASE : USB3PHY_BASE) +#define PHY_SHFT(unit) ((unit == PCIE) ? PCIEPHY_SHFT : USB3PHY_SHFT) + +/* bit definition for USB32_CTRL_BASE (USB32 Control Mode) */ +#define usb32_ctrl_id_mode BIT(0) +#define usb32_ctrl_soft_id BIT(1) +#define usb32_ctrl_int_mode BIT(4) + + +#define PHY_PWR_PLL_CTRL_ADDR 0x01 /* for phy_read16 and phy_write16 */ +#define PWR_PLL_CTRL_ADDR(unit) \ + (PHY_PWR_PLL_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define rf_phy_mode_shift 5 +#define rf_phy_mode_mask (0x7 << rf_phy_mode_shift) +#define rf_ref_freq_sel_shift 0 +#define rf_ref_freq_sel_mask (0x1F << rf_ref_freq_sel_shift) +#define PHY_MODE_SGMII 0x4 + +/* for phy_read16 and phy_write16 */ +#define PHY_REG_KVCO_CAL_CTRL_ADDR 0x02 +#define KVCO_CAL_CTRL_ADDR(unit) \ + (PHY_REG_KVCO_CAL_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define rb_use_max_pll_rate BIT(12) +#define rb_force_calibration_done BIT(9) + +/* for phy_read16 and phy_write16 */ +#define PHY_DIG_LB_EN_ADDR 0x23 +#define DIG_LB_EN_ADDR(unit) \ + (PHY_DIG_LB_EN_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define rf_data_width_shift 10 +#define rf_data_width_mask (0x3 << rf_data_width_shift) + +/* for phy_read16 and phy_write16 */ +#define PHY_SYNC_PATTERN_ADDR 0x24 +#define SYNC_PATTERN_ADDR(unit) \ + (PHY_SYNC_PATTERN_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define phy_txd_inv BIT(10) +#define phy_rxd_inv BIT(11) + +/* for phy_read16 and phy_write16 */ +#define PHY_REG_UNIT_CTRL_ADDR 0x48 +#define UNIT_CTRL_ADDR(unit) \ + (PHY_REG_UNIT_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define rb_idle_sync_en BIT(12) + +/* for phy_read16 and phy_write16 */ +#define PHY_REG_GEN2_SETTINGS_2 0x3e +#define GEN2_SETTING_2_ADDR(unit) \ + (PHY_REG_GEN2_SETTINGS_2 * PHY_SHFT(unit) + PHY_BASE(unit)) +#define g2_tx_ssc_amp BIT(14) + +/* for phy_read16 and phy_write16 */ +#define PHY_REG_GEN2_SETTINGS_3 0x3f +#define GEN2_SETTING_3_ADDR(unit) \ + (PHY_REG_GEN2_SETTINGS_3 * PHY_SHFT(unit) + PHY_BASE(unit)) + +/* for phy_read16 and phy_write16 */ +#define PHY_MISC_REG0_ADDR 0x4f +#define MISC_REG0_ADDR(unit) \ + (PHY_MISC_REG0_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define rb_clk100m_125m_en BIT(4) +#define rb_clk500m_en BIT(7) +#define rb_ref_clk_sel BIT(10) + +/* for phy_read16 and phy_write16 */ +#define PHY_REG_IFACE_REF_CLK_CTRL_ADDR 0x51 +#define UNIT_IFACE_REF_CLK_CTRL_ADDR(unit) \ + (PHY_REG_IFACE_REF_CLK_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define rb_ref1m_gen_div_force BIT(8) +#define rf_ref1m_gen_div_value_shift 0 +#define rf_ref1m_gen_div_value_mask (0xFF << rf_ref1m_gen_div_value_shift) + +/* for phy_read16 and phy_write16 */ +#define PHY_REG_ERR_CNT_CONST_CTRL_ADDR 0x6A +#define UNIT_ERR_CNT_CONST_CTRL_ADDR(unit) \ + (PHY_REG_ERR_CNT_CONST_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit)) +#define rb_fast_dfe_enable BIT(13) + +#define MISC_REG1_ADDR(u) (0x73 * PHY_SHFT(u) + PHY_BASE(u)) +#define bf_sel_bits_pcie_force BIT(15) + +#define LANE_CFG0_ADDR(u) (0x180 * PHY_SHFT(u) + PHY_BASE(u)) +#define bf_use_max_pll_rate BIT(9) +#define LANE_CFG1_ADDR(u) (0x181 * PHY_SHFT(u) + PHY_BASE(u)) +#define bf_use_max_pll_rate BIT(9) +/* 0x5c310 = 0x93 (set BIT7) */ +#define LANE_CFG4_ADDR(u) (0x188 * PHY_SHFT(u) + PHY_BASE(u)) +#define bf_spread_spectrum_clock_en BIT(7) + +#define LANE_STAT1_ADDR(u) (0x183 * PHY_SHFT(u) + PHY_BASE(u)) +#define rb_txdclk_pclk_en BIT(0) + +#define GLOB_PHY_CTRL0_ADDR(u) (0x1c1 * PHY_SHFT(u) + PHY_BASE(u)) +#define bf_soft_rst BIT(0) +#define bf_mode_refdiv 0x30 +#define rb_mode_core_clk_freq_sel BIT(9) +#define rb_mode_pipe_width_32 BIT(3) + +#define TEST_MODE_CTRL_ADDR(u) (0x1c2 * PHY_SHFT(u) + PHY_BASE(u)) +#define rb_mode_margin_override BIT(2) + +#define GLOB_CLK_SRC_LO_ADDR(u) (0x1c3 * PHY_SHFT(u) + PHY_BASE(u)) +#define bf_cfg_sel_20b BIT(15) + +#define PWR_MGM_TIM1_ADDR(u) (0x1d0 * PHY_SHFT(u) + PHY_BASE(u)) + +#define PHY_REF_CLK_ADDR (0x4814 + PCIE_BASE) + +#define USB3_CTRPUL_VAL_REG (0x20 + USB32_BASE) +#define USB3H_CTRPUL_VAL_REG (0x3454 + USB32H_BASE) +#define rb_usb3_ctr_100ns 0xff000000 + +#define USB2_OTG_PHY_CTRL_ADDR (0x820 + USB2PHY_BASE) +#define rb_usb2phy_suspm BIT(14) +#define rb_usb2phy_pu BIT(0) + +#define USB2_PHY_OTG_CTRL_ADDR (0x34 + USB2PHY_BASE) +#define rb_pu_otg BIT(4) + +#define USB2_PHY_CHRGR_DET_ADDR (0x38 + USB2PHY_BASE) +#define rb_cdp_en BIT(2) +#define rb_dcp_en BIT(3) +#define rb_pd_en BIT(4) +#define rb_pu_chrg_dtc BIT(5) +#define rb_cdp_dm_auto BIT(7) +#define rb_enswitch_dp BIT(12) +#define rb_enswitch_dm BIT(13) + +#define USB2_CAL_CTRL_ADDR (0x8 + USB2PHY_BASE) +#define rb_usb2phy_pllcal_done BIT(31) +#define rb_usb2phy_impcal_done BIT(23) + +#define USB2_PLL_CTRL0_ADDR (0x0 + USB2PHY_BASE) +#define rb_usb2phy_pll_ready BIT(31) + +#define USB2_RX_CHAN_CTRL1_ADDR (0x18 + USB2PHY_BASE) +#define rb_usb2phy_sqcal_done BIT(31) + +#define USB2_PHY2_CTRL_ADDR (0x804 + USB2PHY2_BASE) +#define rb_usb2phy2_suspm BIT(7) +#define rb_usb2phy2_pu BIT(0) +#define USB2_PHY2_CAL_CTRL_ADDR (0x8 + USB2PHY2_BASE) +#define USB2_PHY2_PLL_CTRL0_ADDR (0x0 + USB2PHY2_BASE) +#define USB2_PHY2_RX_CHAN_CTRL1_ADDR (0x18 + USB2PHY2_BASE) + +#define USB2_PHY_BASE(usb32) (usb32 == 0 ? USB2PHY2_BASE : USB2PHY_BASE) +#define USB2_PHY_CTRL_ADDR(usb32) \ + (usb32 == 0 ? USB2_PHY2_CTRL_ADDR : USB2_OTG_PHY_CTRL_ADDR) +#define RB_USB2PHY_SUSPM(usb32) \ + (usb32 == 0 ? rb_usb2phy2_suspm : rb_usb2phy_suspm) +#define RB_USB2PHY_PU(usb32) \ + (usb32 == 0 ? rb_usb2phy2_pu : rb_usb2phy_pu) +#define USB2_PHY_CAL_CTRL_ADDR(usb32) \ + (usb32 == 0 ? USB2_PHY2_CAL_CTRL_ADDR : USB2_CAL_CTRL_ADDR) +#define USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32) \ + (usb32 == 0 ? USB2_PHY2_RX_CHAN_CTRL1_ADDR : USB2_RX_CHAN_CTRL1_ADDR) +#define USB2_PHY_PLL_CTRL0_ADDR(usb32) \ + (usb32 == 0 ? USB2_PHY2_PLL_CTRL0_ADDR : USB2_PLL_CTRL0_ADDR) + +/* + * SATA definitions + */ +#define AHCI_BASE MVEBU_REG(0xE0000) + +#define rh_vsreg_addr (AHCI_BASE + 0x178) +#define rh_vsreg_data (AHCI_BASE + 0x17C) +#define rh_vs0_a (AHCI_BASE + 0xA0) +#define rh_vs0_d (AHCI_BASE + 0xA4) + +#define vphy_sync_pattern_reg 0x224 +#define bs_txd_inv BIT(10) +#define bs_rxd_inv BIT(11) + +#define vphy_loopback_reg0 0x223 +#define bs_phyintf_40bit 0x0C00 +#define bs_pll_ready_tx 0x10 + +#define vphy_power_reg0 0x201 + +#define vphy_calctl_reg 0x202 +#define bs_max_pll_rate BIT(12) + +#define vphy_reserve_reg 0x0e +#define bs_phyctrl_frm_pin BIT(13) + +#define vsata_ctrl_reg 0x00 +#define bs_phy_pu_pll BIT(6) + +/* + * SDIO/eMMC definitions + */ +#define SDIO_BASE MVEBU_REG(0xD8000) + +#define SDIO_HOST_CTRL1_ADDR (SDIO_BASE + 0x28) +#define SDIO_SDHC_FIFO_ADDR (SDIO_BASE + 0x12C) +#define SDIO_CAP_12_ADDR (SDIO_BASE + 0x40) +#define SDIO_ENDIAN_ADDR (SDIO_BASE + 0x1A4) +#define SDIO_PHY_TIMING_ADDR (SDIO_BASE + 0x170) +#define SDIO_PHY_PAD_CTRL0_ADDR (SDIO_BASE + 0x178) +#define SDIO_DLL_RST_ADDR (SDIO_BASE + 0x148) + +#endif /* _COMPHY_A3700_H_ */ diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c new file mode 100644 index 0000000..67eb139 --- /dev/null +++ b/drivers/phy/marvell/comphy_core.c @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2015-2016 Marvell International Ltd. + * + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <linux/errno.h> +#include <asm/io.h> + +#include "comphy.h" + +#define COMPHY_MAX_CHIP 4 + +DECLARE_GLOBAL_DATA_PTR; + +static char *get_speed_string(u32 speed) +{ + char *speed_strings[] = {"1.25 Gbps", "1.5 Gbps", "2.5 Gbps", + "3.0 Gbps", "3.125 Gbps", "5 Gbps", "6 Gbps", + "6.25 Gbps", "10.31 Gbps" }; + + if (speed < 0 || speed > PHY_SPEED_MAX) + return "invalid"; + + return speed_strings[speed]; +} + +static char *get_type_string(u32 type) +{ + char *type_strings[] = {"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3", + "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0", + "SGMII1", "SGMII2", "SGMII3", "QSGMII", + "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE", + "XAUI0", "XAUI1", "XAUI2", "XAUI3", + "RXAUI0", "RXAUI1", "KR"}; + + if (type < 0 || type > PHY_TYPE_MAX) + return "invalid"; + + return type_strings[type]; +} + +void reg_set(void __iomem *addr, u32 data, u32 mask) +{ + debug("Write to address = %#010lx, data = %#010x (mask = %#010x) - ", + (unsigned long)addr, data, mask); + debug("old value = %#010x ==> ", readl(addr)); + reg_set_silent(addr, data, mask); + debug("new value %#010x\n", readl(addr)); +} + +void reg_set_silent(void __iomem *addr, u32 data, u32 mask) +{ + u32 reg_data; + + reg_data = readl(addr); + reg_data &= ~mask; + reg_data |= data; + writel(reg_data, addr); +} + +void reg_set16(void __iomem *addr, u16 data, u16 mask) +{ + debug("Write to address = %#010lx, data = %#06x (mask = %#06x) - ", + (unsigned long)addr, data, mask); + debug("old value = %#06x ==> ", readw(addr)); + reg_set_silent16(addr, data, mask); + debug("new value %#06x\n", readw(addr)); +} + +void reg_set_silent16(void __iomem *addr, u16 data, u16 mask) +{ + u16 reg_data; + + reg_data = readw(addr); + reg_data &= ~mask; + reg_data |= data; + writew(reg_data, addr); +} + +void comphy_print(struct chip_serdes_phy_config *chip_cfg, + struct comphy_map *comphy_map_data) +{ + u32 lane; + + for (lane = 0; lane < chip_cfg->comphy_lanes_count; + lane++, comphy_map_data++) { + if (comphy_map_data->type == PHY_TYPE_UNCONNECTED) + continue; + + if (comphy_map_data->speed == PHY_SPEED_INVALID) { + printf("Comphy-%d: %-13s\n", lane, + get_type_string(comphy_map_data->type)); + } else { + printf("Comphy-%d: %-13s %-10s\n", lane, + get_type_string(comphy_map_data->type), + get_speed_string(comphy_map_data->speed)); + } + } +} + +static int comphy_probe(struct udevice *dev) +{ + const void *blob = gd->fdt_blob; + int node = dev->of_offset; + struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev); + struct comphy_map comphy_map_data[MAX_LANE_OPTIONS]; + int subnode; + int lane; + + /* Save base addresses for later use */ + chip_cfg->comphy_base_addr = (void *)dev_get_addr_index(dev, 0); + if (IS_ERR(chip_cfg->comphy_base_addr)) + return PTR_ERR(chip_cfg->comphy_base_addr); + + chip_cfg->hpipe3_base_addr = (void *)dev_get_addr_index(dev, 1); + if (IS_ERR(chip_cfg->hpipe3_base_addr)) + return PTR_ERR(chip_cfg->hpipe3_base_addr); + + chip_cfg->comphy_lanes_count = fdtdec_get_int(blob, node, + "max-lanes", 0); + if (chip_cfg->comphy_lanes_count <= 0) { + dev_err(&dev->dev, "comphy max lanes is wrong\n"); + return -EINVAL; + } + + chip_cfg->comphy_mux_bitcount = fdtdec_get_int(blob, node, + "mux-bitcount", 0); + if (chip_cfg->comphy_mux_bitcount <= 0) { + dev_err(&dev->dev, "comphy mux bit count is wrong\n"); + return -EINVAL; + } + + if (of_device_is_compatible(dev, "marvell,comphy-armada-3700")) + chip_cfg->ptr_comphy_chip_init = comphy_a3700_init; + + /* + * Bail out if no chip_init function is defined, e.g. no + * compatible node is found + */ + if (!chip_cfg->ptr_comphy_chip_init) { + dev_err(&dev->dev, "comphy: No compatible DT node found\n"); + return -ENODEV; + } + + lane = 0; + fdt_for_each_subnode(blob, subnode, node) { + /* Skip disabled ports */ + if (!fdtdec_get_is_enabled(blob, subnode)) + continue; + + comphy_map_data[lane].speed = fdtdec_get_int( + blob, subnode, "phy-speed", PHY_TYPE_INVALID); + comphy_map_data[lane].type = fdtdec_get_int( + blob, subnode, "phy-type", PHY_SPEED_INVALID); + comphy_map_data[lane].invert = fdtdec_get_int( + blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT); + comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode, + "clk-src"); + if (comphy_map_data[lane].type == PHY_TYPE_INVALID) { + printf("no phy type for lane %d, setting lane as unconnected\n", + lane + 1); + } + + lane++; + } + + /* Save comphy index for MultiCP devices (A8K) */ + chip_cfg->comphy_index = dev->seq; + /* PHY power UP sequence */ + chip_cfg->ptr_comphy_chip_init(chip_cfg, comphy_map_data); + /* PHY print SerDes status */ + comphy_print(chip_cfg, comphy_map_data); + + /* Initialize dedicated PHYs (not muxed SerDes lanes) */ + comphy_dedicated_phys_init(); + + return 0; +} + +static const struct udevice_id comphy_ids[] = { + { .compatible = "marvell,mvebu-comphy" }, + { } +}; + +U_BOOT_DRIVER(mvebu_comphy) = { + .name = "mvebu_comphy", + .id = UCLASS_MISC, + .of_match = comphy_ids, + .probe = comphy_probe, + .priv_auto_alloc_size = sizeof(struct chip_serdes_phy_config), +}; diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h new file mode 100644 index 0000000..0c9b500 --- /dev/null +++ b/drivers/phy/marvell/comphy_hpipe.h @@ -0,0 +1,382 @@ +/* + * Copyright (C) 2015-2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _COMPHY_HPIPE_H_ +#define _COMPHY_HPIPE_H_ + +/* SerDes IP register */ +#define SD_EXTERNAL_CONFIG0_REG 0 +#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 +#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \ + (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3 +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \ + (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7 +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \ + (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11 +#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \ + (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12 +#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \ + (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) +#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 +#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \ + (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) +#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15 +#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \ + (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET) + +#define SD_EXTERNAL_CONFIG1_REG 0x4 +#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 +#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \ + (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) +#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4 +#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \ + (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) +#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5 +#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \ + (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) +#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 +#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \ + (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) + +#define SD_EXTERNAL_CONFIG2_REG 0x8 +#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 +#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \ + (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) + +#define SD_EXTERNAL_STATUS0_REG 0x18 +#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 +#define SD_EXTERNAL_STATUS0_PLL_TX_MASK \ + (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) +#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3 +#define SD_EXTERNAL_STATUS0_PLL_RX_MASK \ + (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) +#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4 +#define SD_EXTERNAL_STATUS0_RX_INIT_MASK \ + (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) +#define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6 +#define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \ + (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET) + +/* HPIPE register */ +#define HPIPE_PWR_PLL_REG 0x4 +#define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 +#define HPIPE_PWR_PLL_REF_FREQ_MASK \ + (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) +#define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 +#define HPIPE_PWR_PLL_PHY_MODE_MASK \ + (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) + +#define HPIPE_KVCO_CALIB_CTRL_REG 0x8 +#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12 +#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \ + (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET) + +#define HPIPE_SQUELCH_FFE_SETTING_REG 0x018 + +#define HPIPE_DFE_REG0 0x01C +#define HPIPE_DFE_RES_FORCE_OFFSET 15 +#define HPIPE_DFE_RES_FORCE_MASK \ + (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) + +#define HPIPE_DFE_F3_F5_REG 0x028 +#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 +#define HPIPE_DFE_F3_F5_DFE_EN_MASK \ + (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) +#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 +#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \ + (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) + +#define HPIPE_G1_SET_0_REG 0x034 +#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 +#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \ + (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) + +#define HPIPE_G1_SET_1_REG 0x038 +#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 +#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \ + (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 +#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \ + (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 +#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \ + (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) + +#define HPIPE_G2_SETTINGS_1_REG 0x040 + +#define HPIPE_G3_SETTINGS_1_REG 0x048 +#define HPIPE_G3_RX_SELMUPI_OFFSET 0 +#define HPIPE_G3_RX_SELMUPI_MASK \ + (0x7 << HPIPE_G3_RX_SELMUPI_OFFSET) +#define HPIPE_G3_RX_SELMUPF_OFFSET 3 +#define HPIPE_G3_RX_SELMUPF_MASK \ + (0x7 << HPIPE_G3_RX_SELMUPF_OFFSET) +#define HPIPE_G3_SETTING_BIT_OFFSET 13 +#define HPIPE_G3_SETTING_BIT_MASK \ + (0x1 << HPIPE_G3_SETTING_BIT_OFFSET) + +#define HPIPE_LOOPBACK_REG 0x08c +#define HPIPE_LOOPBACK_SEL_OFFSET 1 +#define HPIPE_LOOPBACK_SEL_MASK \ + (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) + +#define HPIPE_SYNC_PATTERN_REG 0x090 + +#define HPIPE_INTERFACE_REG 0x94 +#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 +#define HPIPE_INTERFACE_GEN_MAX_MASK \ + (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) +#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 +#define HPIPE_INTERFACE_LINK_TRAIN_MASK \ + (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) + +#define HPIPE_ISOLATE_MODE_REG 0x98 +#define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0 +#define HPIPE_ISOLATE_MODE_GEN_RX_MASK \ + (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET) +#define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4 +#define HPIPE_ISOLATE_MODE_GEN_TX_MASK \ + (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET) + +#define HPIPE_VTHIMPCAL_CTRL_REG 0x104 + +#define HPIPE_PCIE_REG0 0x120 +#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 +#define HPIPE_PCIE_IDLE_SYNC_MASK \ + (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) +#define HPIPE_PCIE_SEL_BITS_OFFSET 13 +#define HPIPE_PCIE_SEL_BITS_MASK \ + (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) + +#define HPIPE_LANE_ALIGN_REG 0x124 +#define HPIPE_LANE_ALIGN_OFF_OFFSET 12 +#define HPIPE_LANE_ALIGN_OFF_MASK \ + (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) + +#define HPIPE_MISC_REG 0x13C +#define HPIPE_MISC_CLK100M_125M_OFFSET 4 +#define HPIPE_MISC_CLK100M_125M_MASK \ + (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) +#define HPIPE_MISC_TXDCLK_2X_OFFSET 6 +#define HPIPE_MISC_TXDCLK_2X_MASK \ + (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) +#define HPIPE_MISC_CLK500_EN_OFFSET 7 +#define HPIPE_MISC_CLK500_EN_MASK \ + (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) +#define HPIPE_MISC_REFCLK_SEL_OFFSET 10 +#define HPIPE_MISC_REFCLK_SEL_MASK \ + (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) + +#define HPIPE_RX_CONTROL_1_REG 0x140 +#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11 +#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \ + (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) +#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12 +#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \ + (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) + +#define HPIPE_PWR_CTR_REG 0x148 +#define HPIPE_PWR_CTR_RST_DFE_OFFSET 0 +#define HPIPE_PWR_CTR_RST_DFE_MASK \ + (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) +#define HPIPE_PWR_CTR_SFT_RST_OFFSET 10 +#define HPIPE_PWR_CTR_SFT_RST_MASK \ + (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) + +#define HPIPE_PLLINTP_REG1 0x150 + +#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C +#define HPIPE_SMAPLER_OFFSET 12 +#define HPIPE_SMAPLER_MASK \ + (0x1 << HPIPE_SMAPLER_OFFSET) + +#define HPIPE_PWR_CTR_DTL_REG 0x184 +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ + (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) + +#define HPIPE_RX_REG3 0x188 + +#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 +#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 +#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ + (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) + +#define HPIPE_TX_TRAIN_CTRL_REG 0x26C +#define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 +#define HPIPE_TX_TRAIN_CTRL_G1_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 +#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 +#define HPIPE_TX_TRAIN_CTRL_G0_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) + +#define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 +#define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 +#define HPIPE_TRX_TRAIN_TIMER_MASK \ + (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) + +#define HPIPE_PCIE_REG1 0x288 +#define HPIPE_PCIE_REG3 0x290 + +#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 +#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 +#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 +#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 +#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) +#define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 +#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) + +#define HPIPE_TX_TRAIN_REG 0x31C +#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 +#define HPIPE_TX_TRAIN_CHK_INIT_MASK \ + (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) +#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 +#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ + (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) + +#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 +#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 +#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ + (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) +#define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 +#define HPIPE_TX_NUM_OF_PRESET_MASK \ + (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) +#define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 +#define HPIPE_TX_SWEEP_PRESET_EN_MASK \ + (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) + +#define HPIPE_G1_SETTINGS_3_REG 0x440 + +#define HPIPE_G1_SETTINGS_4_REG 0x444 +#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8 +#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \ + (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET) + +#define HPIPE_G2_SETTINGS_3_REG 0x448 +#define HPIPE_G2_SETTINGS_4_REG 0x44C + +#define HPIPE_G3_SETTING_3_REG 0x450 +#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 +#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ + (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) +#define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 +#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \ + (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) + +#define HPIPE_G3_SETTING_4_REG 0x454 +#define HPIPE_G3_DFE_RES_OFFSET 8 +#define HPIPE_G3_DFE_RES_MASK \ + (0x3 << HPIPE_G3_DFE_RES_OFFSET) + +#define HPIPE_DFE_CTRL_28_REG 0x49C +#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 +#define HPIPE_DFE_CTRL_28_PIPE4_MASK \ + (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) + +#define HPIPE_LANE_CONFIG0_REG 0x600 +#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0 +#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \ + (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET) + +#define HPIPE_LANE_CONFIG1_REG 0x604 +#define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9 +#define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \ + (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET) +#define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10 +#define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \ + (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET) + +#define HPIPE_LANE_STATUS1_REG 0x60C +#define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0 +#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \ + (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) + +#define HPIPE_LANE_CFG4_REG 0x620 +#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 +#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \ + (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) +#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 +#define HPIPE_LANE_CFG4_DFE_OVER_MASK \ + (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) +#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 +#define HPIPE_LANE_CFG4_SSC_CTRL_MASK \ + (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) + +#define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C +#define HPIPE_CFG_PHY_RC_EP_OFFSET 12 +#define HPIPE_CFG_PHY_RC_EP_MASK \ + (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) + +#define HPIPE_LANE_EQ_CFG1_REG 0x6a0 +#define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 +#define HPIPE_CFG_UPDATE_POLARITY_MASK \ + (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) + +#define HPIPE_RST_CLK_CTRL_REG 0x704 +#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 +#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) +#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 +#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) +#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 +#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) + +#define HPIPE_TST_MODE_CTRL_REG 0x708 +#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2 +#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \ + (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET) + +#define HPIPE_CLK_SRC_LO_REG 0x70c +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \ + (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \ + (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \ + (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) + +#define HPIPE_CLK_SRC_HI_REG 0x710 +#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 +#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 +#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 +#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) +#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 +#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) + +#define HPIPE_GLOBAL_MISC_CTRL 0x718 +#define HPIPE_GLOBAL_PM_CTRL 0x740 +#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 +#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \ + (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) + +#endif /* _COMPHY_HPIPE_H_ */ + diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c new file mode 100644 index 0000000..1dc7426 --- /dev/null +++ b/drivers/phy/marvell/comphy_mux.c @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2015-2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> + +#include "comphy.h" +#include "comphy_hpipe.h" + +/* + * comphy_mux_check_config() + * description: this function passes over the COMPHY lanes and check if the type + * is valid for specific lane. If the type is not valid, + * the function update the struct and set the type of the lane as + * PHY_TYPE_UNCONNECTED + */ +static void comphy_mux_check_config(struct comphy_mux_data *mux_data, + struct comphy_map *comphy_map_data, int comphy_max_lanes) +{ + struct comphy_mux_options *mux_opt; + int lane, opt, valid; + + debug_enter(); + + for (lane = 0; lane < comphy_max_lanes; + lane++, comphy_map_data++, mux_data++) { + mux_opt = mux_data->mux_values; + for (opt = 0, valid = 0; opt < mux_data->max_lane_values; + opt++, mux_opt++) { + if (mux_opt->type == comphy_map_data->type) { + valid = 1; + break; + } + } + if (valid == 0) { + debug("lane number %d, had invalid type %d\n", + lane, comphy_map_data->type); + debug("set lane %d as type %d\n", lane, + PHY_TYPE_UNCONNECTED); + comphy_map_data->type = PHY_TYPE_UNCONNECTED; + } else { + debug("lane number %d, has type %d\n", + lane, comphy_map_data->type); + } + } + + debug_exit(); +} + +static u32 comphy_mux_get_mux_value(struct comphy_mux_data *mux_data, + u32 type, int lane) +{ + struct comphy_mux_options *mux_opt; + int opt; + u32 value = 0; + + debug_enter(); + + mux_opt = mux_data->mux_values; + for (opt = 0 ; opt < mux_data->max_lane_values; opt++, mux_opt++) { + if (mux_opt->type == type) { + value = mux_opt->mux_value; + break; + } + } + + debug_exit(); + + return value; +} + +static void comphy_mux_reg_write(struct comphy_mux_data *mux_data, + struct comphy_map *comphy_map_data, + int comphy_max_lanes, + void __iomem *selector_base, u32 bitcount) +{ + u32 lane, value, offset, mask; + + debug_enter(); + + for (lane = 0; lane < comphy_max_lanes; + lane++, comphy_map_data++, mux_data++) { + offset = lane * bitcount; + mask = (((1 << bitcount) - 1) << offset); + value = (comphy_mux_get_mux_value(mux_data, + comphy_map_data->type, + lane) << offset); + reg_set(selector_base, value, mask); + } + + debug_exit(); +} + +void comphy_mux_init(struct chip_serdes_phy_config *chip_cfg, + struct comphy_map *comphy_map_data, + void __iomem *selector_base) +{ + struct comphy_mux_data *mux_data; + u32 mux_bitcount; + u32 comphy_max_lanes; + + debug_enter(); + + comphy_max_lanes = chip_cfg->comphy_lanes_count; + mux_data = chip_cfg->mux_data; + mux_bitcount = chip_cfg->comphy_mux_bitcount; + + /* check if the configuration is valid */ + comphy_mux_check_config(mux_data, comphy_map_data, comphy_max_lanes); + /* Init COMPHY selectors */ + comphy_mux_reg_write(mux_data, comphy_map_data, comphy_max_lanes, + selector_base, mux_bitcount); + + debug_exit(); +} diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h new file mode 100644 index 0000000..a3a6b40 --- /dev/null +++ b/include/dt-bindings/comphy/comphy_data.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2015-2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _COMPHY_DATA_H_ +#define _COMPHY_DATA_H_ + +#define PHY_SPEED_1_25G 0 +#define PHY_SPEED_1_5G 1 +#define PHY_SPEED_2_5G 2 +#define PHY_SPEED_3G 3 +#define PHY_SPEED_3_125G 4 +#define PHY_SPEED_5G 5 +#define PHY_SPEED_6G 6 +#define PHY_SPEED_6_25G 7 +#define PHY_SPEED_10_3125G 8 +#define PHY_SPEED_MAX 9 +#define PHY_SPEED_INVALID 0xff + +#define PHY_TYPE_UNCONNECTED 0 +#define PHY_TYPE_PEX0 1 +#define PHY_TYPE_PEX1 2 +#define PHY_TYPE_PEX2 3 +#define PHY_TYPE_PEX3 4 +#define PHY_TYPE_SATA0 5 +#define PHY_TYPE_SATA1 6 +#define PHY_TYPE_SATA2 7 +#define PHY_TYPE_SATA3 8 +#define PHY_TYPE_SGMII0 9 +#define PHY_TYPE_SGMII1 10 +#define PHY_TYPE_SGMII2 11 +#define PHY_TYPE_SGMII3 12 +#define PHY_TYPE_QSGMII 13 +#define PHY_TYPE_USB3_HOST0 14 +#define PHY_TYPE_USB3_HOST1 15 +#define PHY_TYPE_USB3_DEVICE 16 +#define PHY_TYPE_XAUI0 17 +#define PHY_TYPE_XAUI1 18 +#define PHY_TYPE_XAUI2 19 +#define PHY_TYPE_XAUI3 20 +#define PHY_TYPE_RXAUI0 21 +#define PHY_TYPE_RXAUI1 22 +#define PHY_TYPE_KR 23 +#define PHY_TYPE_MAX 24 +#define PHY_TYPE_INVALID 0xff + +#define PHY_POLARITY_NO_INVERT 0 +#define PHY_POLARITY_TXD_INVERT 1 +#define PHY_POLARITY_RXD_INVERT 2 +#define PHY_POLARITY_ALL_INVERT \ + (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT) + +#define UTMI_PHY_TO_USB_HOST0 0 +#define UTMI_PHY_TO_USB_HOST1 1 +#define UTMI_PHY_TO_USB_DEVICE0 2 +#define UTMI_PHY_INVALID 0xff + +#endif /* _COMPHY_DATA_H_ */ + |