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-rw-r--r--arch/arm/dts/am4372.dtsi1
-rw-r--r--arch/arm/dts/dra7.dtsi3
-rw-r--r--arch/arm/include/asm/arch-omap5/cpu.h12
-rw-r--r--configs/am437x_gp_evm_defconfig1
-rw-r--r--configs/am437x_sk_evm_defconfig1
-rw-r--r--configs/dra74_evm_defconfig1
-rw-r--r--doc/device-tree-bindings/net/ti,dp83867.txt25
-rw-r--r--drivers/core/device.c14
-rw-r--r--drivers/net/Makefile2
-rw-r--r--drivers/net/cpsw-common.c121
-rw-r--r--drivers/net/cpsw.c77
-rw-r--r--drivers/net/phy/mv88e61xx.c1322
-rw-r--r--drivers/net/phy/mv88e61xx.h61
-rw-r--r--drivers/net/phy/phy.c3
-rw-r--r--drivers/net/phy/ti.c88
-rw-r--r--drivers/net/zynq_gem.c14
-rw-r--r--include/configs/ti_omap5_common.h1
-rw-r--r--include/cpsw.h2
-rw-r--r--include/dm/device.h23
-rw-r--r--include/dt-bindings/net/ti-dp83867.h35
-rw-r--r--include/netdev.h58
-rw-r--r--include/phy.h23
22 files changed, 1299 insertions, 589 deletions
diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
index c95d1d3..3ffa8e0 100644
--- a/arch/arm/dts/am4372.dtsi
+++ b/arch/arm/dts/am4372.dtsi
@@ -547,6 +547,7 @@
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
+ syscon = <&scm_conf>;
ranges;
davinci_mdio: mdio@4a101000 {
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index e7fecf7..0f242e6 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -1411,7 +1411,7 @@
ti,irqs-safe-map = <0>;
};
- mac: ethernet@4a100000 {
+ mac: ethernet@48484000 {
compatible = "ti,cpsw";
ti,hwmods = "gmac";
clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
@@ -1426,6 +1426,7 @@
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
+ syscon = <&scm_conf>;
reg = <0x48484000 0x1000
0x48485200 0x2E00>;
#address-cells = <1>;
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index b1513e9..683d905 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -116,4 +116,16 @@ struct watchdog {
#define CPSW_BASE 0x48484000
#define CPSW_MDIO_BASE 0x48485000
+/* gmii_sel register defines */
+#define GMII1_SEL_MII 0x0
+#define GMII1_SEL_RMII 0x1
+#define GMII1_SEL_RGMII 0x2
+#define GMII2_SEL_MII (GMII1_SEL_MII << 4)
+#define GMII2_SEL_RMII (GMII1_SEL_RMII << 4)
+#define GMII2_SEL_RGMII (GMII1_SEL_RGMII << 4)
+
+#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
+
#endif /* _CPU_H */
diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index 03b02ac..f098fd3 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -47,3 +47,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_DM_ETH=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index 48ec91f..8be0412 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -51,3 +51,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_DM_ETH=y
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index a11dcd5..32ffce7 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -50,3 +50,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_DM_ETH=y
diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt
new file mode 100644
index 0000000..cb77fdf
--- /dev/null
+++ b/doc/device-tree-bindings/net/ti,dp83867.txt
@@ -0,0 +1,25 @@
+* Texas Instruments - dp83867 Giga bit ethernet phy
+
+Required properties:
+ - reg - The ID number for the phy, usually a small integer
+ - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
+ for applicable values
+ - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
+ for applicable values
+ - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
+ for applicable values
+
+Default child nodes are standard Ethernet PHY device
+nodes as described in doc/devicetree/bindings/net/ethernet.txt
+
+Example:
+
+ ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+
+Datasheet can be found:
+http://www.ti.com/product/DP83867IR/datasheet
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 5c2dc70..45d5e3e 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -721,3 +721,17 @@ int device_set_name(struct udevice *dev, const char *name)
return 0;
}
+
+bool of_device_is_compatible(struct udevice *dev, const char *compat)
+{
+ const void *fdt = gd->fdt_blob;
+
+ return !fdt_node_check_compatible(fdt, dev->of_offset, compat);
+}
+
+bool of_machine_is_compatible(const char *compat)
+{
+ const void *fdt = gd->fdt_blob;
+
+ return !fdt_node_check_compatible(fdt, 0, compat);
+}
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index fbedd04..d5e4a97 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -59,7 +59,7 @@ obj-$(CONFIG_SMC91111) += smc91111.o
obj-$(CONFIG_SMC911X) += smc911x.o
obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
-obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
+obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o
obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o
obj-$(CONFIG_ULI526X) += uli526x.o
diff --git a/drivers/net/cpsw-common.c b/drivers/net/cpsw-common.c
new file mode 100644
index 0000000..e828e85
--- /dev/null
+++ b/drivers/net/cpsw-common.c
@@ -0,0 +1,121 @@
+/*
+ * CPSW common - libs used across TI ethernet devices.
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <cpsw.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CTRL_MAC_REG(offset, id) ((offset) + 0x8 * (id))
+
+static int davinci_emac_3517_get_macid(struct udevice *dev, u16 offset,
+ int slave, u8 *mac_addr)
+{
+ void *fdt = (void *)gd->fdt_blob;
+ int node = dev->of_offset;
+ u32 macid_lsb;
+ u32 macid_msb;
+ fdt32_t gmii = 0;
+ int syscon;
+ u32 addr;
+
+ syscon = fdtdec_lookup_phandle(fdt, node, "syscon");
+ if (syscon < 0) {
+ error("Syscon offset not found\n");
+ return -ENOENT;
+ }
+
+ addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii),
+ sizeof(u32), MAP_NOCACHE);
+ if (addr == FDT_ADDR_T_NONE) {
+ error("Not able to get syscon address to get mac efuse address\n");
+ return -ENOENT;
+ }
+
+ addr += CTRL_MAC_REG(offset, slave);
+
+ /* try reading mac address from efuse */
+ macid_lsb = readl(addr);
+ macid_msb = readl(addr + 4);
+
+ mac_addr[0] = (macid_msb >> 16) & 0xff;
+ mac_addr[1] = (macid_msb >> 8) & 0xff;
+ mac_addr[2] = macid_msb & 0xff;
+ mac_addr[3] = (macid_lsb >> 16) & 0xff;
+ mac_addr[4] = (macid_lsb >> 8) & 0xff;
+ mac_addr[5] = macid_lsb & 0xff;
+
+ return 0;
+}
+
+static int cpsw_am33xx_cm_get_macid(struct udevice *dev, u16 offset, int slave,
+ u8 *mac_addr)
+{
+ void *fdt = (void *)gd->fdt_blob;
+ int node = dev->of_offset;
+ u32 macid_lo;
+ u32 macid_hi;
+ fdt32_t gmii = 0;
+ int syscon;
+ u32 addr;
+
+ syscon = fdtdec_lookup_phandle(fdt, node, "syscon");
+ if (syscon < 0) {
+ error("Syscon offset not found\n");
+ return -ENOENT;
+ }
+
+ addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii),
+ sizeof(u32), MAP_NOCACHE);
+ if (addr == FDT_ADDR_T_NONE) {
+ error("Not able to get syscon address to get mac efuse address\n");
+ return -ENOENT;
+ }
+
+ addr += CTRL_MAC_REG(offset, slave);
+
+ /* try reading mac address from efuse */
+ macid_lo = readl(addr);
+ macid_hi = readl(addr + 4);
+
+ mac_addr[5] = (macid_lo >> 8) & 0xff;
+ mac_addr[4] = macid_lo & 0xff;
+ mac_addr[3] = (macid_hi >> 24) & 0xff;
+ mac_addr[2] = (macid_hi >> 16) & 0xff;
+ mac_addr[1] = (macid_hi >> 8) & 0xff;
+ mac_addr[0] = macid_hi & 0xff;
+
+ return 0;
+}
+
+int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr)
+{
+ if (of_machine_is_compatible("ti,dm8148"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+ if (of_machine_is_compatible("ti,am33xx"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+ if (of_device_is_compatible(dev, "ti,am3517-emac"))
+ return davinci_emac_3517_get_macid(dev, 0x110, slave, mac_addr);
+
+ if (of_device_is_compatible(dev, "ti,dm816-emac"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x30, slave, mac_addr);
+
+ if (of_machine_is_compatible("ti,am4372"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+ if (of_machine_is_compatible("ti,dra7"))
+ return davinci_emac_3517_get_macid(dev, 0x514, slave, mac_addr);
+
+ dev_err(dev, "incompatible machine/device type for reading mac address\n");
+ return -ENOENT;
+}
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 7104754..2ce4ec6 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -26,6 +26,7 @@
#include <phy.h>
#include <asm/arch/cpu.h>
#include <dm.h>
+#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -965,6 +966,11 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
phydev->supported &= supported;
phydev->advertising = phydev->supported;
+#ifdef CONFIG_DM_ETH
+ if (slave->data->phy_of_handle)
+ phydev->dev->of_offset = slave->data->phy_of_handle;
+#endif
+
priv->phydev = phydev;
phy_config(phydev);
@@ -1137,6 +1143,11 @@ static const struct eth_ops cpsw_eth_ops = {
.stop = cpsw_eth_stop,
};
+static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
+{
+ return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL);
+}
+
static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
@@ -1146,9 +1157,8 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
int node = dev->of_offset;
int subnode;
int slave_index = 0;
- uint32_t mac_hi, mac_lo;
- fdt32_t gmii = 0;
int active_slave;
+ int ret;
pdata->iobase = dev_get_addr(dev);
priv->data.version = CPSW_CTRL_VERSION_2;
@@ -1202,29 +1212,52 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
name = fdt_get_name(fdt, subnode, &len);
if (!strncmp(name, "mdio", 4)) {
- priv->data.mdio_base = fdtdec_get_addr(fdt, subnode,
- "reg");
+ u32 mdio_base;
+
+ mdio_base = cpsw_get_addr_by_node(fdt, subnode);
+ if (mdio_base == FDT_ADDR_T_NONE) {
+ error("Not able to get MDIO address space\n");
+ return -ENOENT;
+ }
+ priv->data.mdio_base = mdio_base;
}
if (!strncmp(name, "slave", 5)) {
u32 phy_id[2];
- if (slave_index >= priv->data.slaves) {
- printf("error: num slaves and slave nodes did not match\n");
- return -EINVAL;
- }
+ if (slave_index >= priv->data.slaves)
+ continue;
phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
if (phy_mode)
priv->data.slave_data[slave_index].phy_if =
phy_get_interface_by_name(phy_mode);
- fdtdec_get_int_array(fdt, subnode, "phy_id", phy_id, 2);
- priv->data.slave_data[slave_index].phy_addr = phy_id[1];
+
+ priv->data.slave_data[slave_index].phy_of_handle =
+ fdtdec_lookup_phandle(fdt, subnode,
+ "phy-handle");
+
+ if (priv->data.slave_data[slave_index].phy_of_handle >= 0) {
+ priv->data.slave_data[slave_index].phy_addr =
+ fdtdec_get_int(gd->fdt_blob,
+ priv->data.slave_data[slave_index].phy_of_handle,
+ "reg", -1);
+ } else {
+ fdtdec_get_int_array(fdt, subnode, "phy_id",
+ phy_id, 2);
+ priv->data.slave_data[slave_index].phy_addr =
+ phy_id[1];
+ }
slave_index++;
}
if (!strncmp(name, "cpsw-phy-sel", 12)) {
- priv->data.gmii_sel = fdtdec_get_addr(fdt, subnode,
- "reg");
+ priv->data.gmii_sel = cpsw_get_addr_by_node(fdt,
+ subnode);
+
+ if (priv->data.gmii_sel == FDT_ADDR_T_NONE) {
+ error("Not able to get gmii_sel reg address\n");
+ return -ENOENT;
+ }
}
}
@@ -1236,20 +1269,11 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
}
- subnode = fdtdec_lookup_phandle(fdt, node, "syscon");
- priv->data.mac_id = fdt_translate_address((void *)fdt, subnode, &gmii);
- priv->data.mac_id += AM335X_GMII_SEL_OFFSET;
- priv->data.mac_id += active_slave * 8;
-
- /* try reading mac address from efuse */
- mac_lo = readl(priv->data.mac_id);
- mac_hi = readl(priv->data.mac_id + 4);
- pdata->enetaddr[0] = mac_hi & 0xFF;
- pdata->enetaddr[1] = (mac_hi & 0xFF00) >> 8;
- pdata->enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
- pdata->enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
- pdata->enetaddr[4] = mac_lo & 0xFF;
- pdata->enetaddr[5] = (mac_lo & 0xFF00) >> 8;
+ ret = ti_cm_get_macid(dev, active_slave, pdata->enetaddr);
+ if (ret < 0) {
+ error("cpsw read efuse mac failed\n");
+ return ret;
+ }
pdata->phy_interface = priv->data.slave_data[active_slave].phy_if;
if (pdata->phy_interface == -1) {
@@ -1270,6 +1294,7 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
writel(RGMII_MODE_ENABLE, priv->data.gmii_sel);
break;
}
+
return 0;
}
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
index 302abe8..74d5609 100644
--- a/drivers/net/phy/mv88e61xx.c
+++ b/drivers/net/phy/mv88e61xx.c
@@ -1,4 +1,9 @@
/*
+ * (C) Copyright 2015
+ * Elecsys Corporation <www.elecsyscorp.com>
+ * Kevin Smith <kevin.smith@elecsyscorp.com>
+ *
+ * Original driver:
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Prafulla Wadaskar <prafulla@marvell.com>
@@ -6,532 +11,1007 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+/*
+ * PHY driver for mv88e61xx ethernet switches.
+ *
+ * This driver configures the mv88e61xx for basic use as a PHY. The switch
+ * supports a VLAN configuration that determines how traffic will be routed
+ * between the ports. This driver uses a simple configuration that routes
+ * traffic from each PHY port only to the CPU port, and from the CPU port to
+ * any PHY port.
+ *
+ * The configuration determines which PHY ports to activate using the
+ * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit
+ * 1 activates port 1, etc. Do not set the bit for the port the CPU is
+ * connected to unless it is connected over a PHY interface (not MII).
+ *
+ * This driver was written for and tested on the mv88e6176 with an SGMII
+ * connection. Other configurations should be supported, but some additions or
+ * changes may be required.
+ */
+
#include <common.h>
+
+#include <bitfield.h>
+#include <errno.h>
+#include <malloc.h>
+#include <miiphy.h>
#include <netdev.h>
-#include "mv88e61xx.h"
+
+#define PHY_AUTONEGOTIATE_TIMEOUT 5000
+
+#define PORT_COUNT 7
+#define PORT_MASK ((1 << PORT_COUNT) - 1)
+
+/* Device addresses */
+#define DEVADDR_PHY(p) (p)
+#define DEVADDR_PORT(p) (0x10 + (p))
+#define DEVADDR_SERDES 0x0F
+#define DEVADDR_GLOBAL_1 0x1B
+#define DEVADDR_GLOBAL_2 0x1C
+
+/* SMI indirection registers for multichip addressing mode */
+#define SMI_CMD_REG 0x00
+#define SMI_DATA_REG 0x01
+
+/* Global registers */
+#define GLOBAL1_STATUS 0x00
+#define GLOBAL1_CTRL 0x04
+#define GLOBAL1_MON_CTRL 0x1A
+
+/* Global 2 registers */
+#define GLOBAL2_REG_PHY_CMD 0x18
+#define GLOBAL2_REG_PHY_DATA 0x19
+
+/* Port registers */
+#define PORT_REG_STATUS 0x00
+#define PORT_REG_PHYS_CTRL 0x01
+#define PORT_REG_SWITCH_ID 0x03
+#define PORT_REG_CTRL 0x04
+#define PORT_REG_VLAN_MAP 0x06
+#define PORT_REG_VLAN_ID 0x07
+
+/* Phy registers */
+#define PHY_REG_CTRL1 0x10
+#define PHY_REG_STATUS1 0x11
+#define PHY_REG_PAGE 0x16
+
+/* Serdes registers */
+#define SERDES_REG_CTRL_1 0x10
+
+/* Phy page numbers */
+#define PHY_PAGE_COPPER 0
+#define PHY_PAGE_SERDES 1
+
+/* Register fields */
+#define GLOBAL1_CTRL_SWRESET BIT(15)
+
+#define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4
+#define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4
+
+#define PORT_REG_STATUS_LINK BIT(11)
+#define PORT_REG_STATUS_DUPLEX BIT(10)
+
+#define PORT_REG_STATUS_SPEED_SHIFT 8
+#define PORT_REG_STATUS_SPEED_WIDTH 2
+#define PORT_REG_STATUS_SPEED_10 0
+#define PORT_REG_STATUS_SPEED_100 1
+#define PORT_REG_STATUS_SPEED_1000 2
+
+#define PORT_REG_STATUS_CMODE_MASK 0xF
+#define PORT_REG_STATUS_CMODE_100BASE_X 0x8
+#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
+#define PORT_REG_STATUS_CMODE_SGMII 0xa
+
+#define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
+#define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
+
+#define PORT_REG_CTRL_PSTATE_SHIFT 0
+#define PORT_REG_CTRL_PSTATE_WIDTH 2
+
+#define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0
+#define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12
+
+#define PORT_REG_VLAN_MAP_TABLE_SHIFT 0
+#define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
+
+#define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
+
+#define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8
+#define PHY_REG_CTRL1_ENERGY_DET_WIDTH 2
+
+/* Field values */
+#define PORT_REG_CTRL_PSTATE_DISABLED 0
+#define PORT_REG_CTRL_PSTATE_FORWARD 3
+
+#define PHY_REG_CTRL1_ENERGY_DET_OFF 0
+#define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2
+#define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3
+
+/* PHY Status Register */
+#define PHY_REG_STATUS1_SPEED 0xc000
+#define PHY_REG_STATUS1_GBIT 0x8000
+#define PHY_REG_STATUS1_100 0x4000
+#define PHY_REG_STATUS1_DUPLEX 0x2000
+#define PHY_REG_STATUS1_SPDDONE 0x0800
+#define PHY_REG_STATUS1_LINK 0x0400
+#define PHY_REG_STATUS1_ENERGY 0x0010
/*
- * Uncomment either of the following line for local debug control;
- * otherwise global debug control will apply.
+ * Macros for building commands for indirect addressing modes. These are valid
+ * for both the indirect multichip addressing mode and the PHY indirection
+ * required for the writes to any PHY register.
*/
+#define SMI_BUSY BIT(15)
+#define SMI_CMD_CLAUSE_22 BIT(12)
+#define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
+#define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
+
+#define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
+ SMI_CMD_CLAUSE_22_OP_READ)
+#define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
+ SMI_CMD_CLAUSE_22_OP_WRITE)
+
+#define SMI_CMD_ADDR_SHIFT 5
+#define SMI_CMD_ADDR_WIDTH 5
+#define SMI_CMD_REG_SHIFT 0
+#define SMI_CMD_REG_WIDTH 5
+
+/* Check for required macros */
+#ifndef CONFIG_MV88E61XX_PHY_PORTS
+#error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
+ to activate
+#endif
+#ifndef CONFIG_MV88E61XX_CPU_PORT
+#error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
+#endif
-/* #undef DEBUG */
-/* #define DEBUG */
+/* ID register values for different switch models */
+#define PORT_SWITCH_ID_6172 0x1720
+#define PORT_SWITCH_ID_6176 0x1760
+#define PORT_SWITCH_ID_6240 0x2400
+#define PORT_SWITCH_ID_6352 0x3520
-#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-/* Chip Address mode
- * The Switch support two modes of operation
- * 1. single chip mode and
- * 2. Multi-chip mode
- * Refer section 9.2 &9.3 in chip datasheet-02 for more details
- *
- * By default single chip mode is configured
- * multichip mode operation can be configured in board header
- */
-static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
+struct mv88e61xx_phy_priv {
+ struct mii_dev *mdio_bus;
+ int smi_addr;
+ int id;
+};
+
+static inline int smi_cmd(int cmd, int addr, int reg)
{
- u16 reg = 0;
- u32 timeout = MV88E61XX_PHY_TIMEOUT;
+ cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
+ addr);
+ cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
+ return cmd;
+}
- /* Poll till SMIBusy bit is clear */
- do {
- miiphy_read(name, devaddr, 0x0, &reg);
- if (timeout-- == 0) {
- printf("SMI busy timeout\n");
- return -1;
- }
- } while (reg & (1 << 15));
- return 0;
+static inline int smi_cmd_read(int addr, int reg)
+{
+ return smi_cmd(SMI_CMD_READ, addr, reg);
}
-static void mv88e61xx_switch_write(char *name, u32 phy_adr,
- u32 reg_ofs, u16 data)
+static inline int smi_cmd_write(int addr, int reg)
{
- u16 mii_dev_addr;
+ return smi_cmd(SMI_CMD_WRITE, addr, reg);
+}
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
- printf("Error..could not read PHY dev address\n");
- return;
- }
- mv88e61xx_busychk_multic(name, mii_dev_addr);
- /* Write data to Switch indirect data register */
- miiphy_write(name, mii_dev_addr, 0x1, data);
- /* Write command to Switch indirect command register (write) */
- miiphy_write(name, mii_dev_addr, 0x0,
- reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
- 15));
+__weak int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+ return 0;
}
-static void mv88e61xx_switch_read(char *name, u32 phy_adr,
- u32 reg_ofs, u16 *data)
+/* Wait for the current SMI indirect command to complete */
+static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
{
- u16 mii_dev_addr;
+ int val;
+ u32 timeout = 100;
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
- printf("Error..could not read PHY dev address\n");
- return;
- }
- mv88e61xx_busychk_multic(name, mii_dev_addr);
- /* Write command to Switch indirect command register (read) */
- miiphy_write(name, mii_dev_addr, 0x0,
- reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 <<
- 15));
- mv88e61xx_busychk_multic(name, mii_dev_addr);
- /* Read data from Switch indirect data register */
- miiphy_read(name, mii_dev_addr, 0x1, data);
+ do {
+ val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
+ if (val >= 0 && (val & SMI_BUSY) == 0)
+ return 0;
+
+ mdelay(1);
+ } while (--timeout);
+
+ puts("SMI busy timeout\n");
+ return -ETIMEDOUT;
}
-#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
/*
- * Convenience macros for switch device/port reads/writes
- * These macros output valid 'mv88e61xx' U_BOOT_CMDs
+ * The mv88e61xx has three types of addresses: the smi bus address, the device
+ * address, and the register address. The smi bus address distinguishes it on
+ * the smi bus from other PHYs or switches. The device address determines
+ * which on-chip register set you are reading/writing (the various PHYs, their
+ * associated ports, or global configuration registers). The register address
+ * is the offset of the register you are reading/writing.
+ *
+ * When the mv88e61xx is hardware configured to have address zero, it behaves in
+ * single-chip addressing mode, where it responds to all SMI addresses, using
+ * the smi address as its device address. This obviously only works when this
+ * is the only chip on the SMI bus. This allows the driver to access device
+ * registers without using indirection. When the chip is configured to a
+ * non-zero address, it only responds to that SMI address and requires indirect
+ * writes to access the different device addresses.
*/
-
-#ifndef DEBUG
-#define WR_SWITCH_REG wr_switch_reg
-#define RD_SWITCH_REG rd_switch_reg
-#define WR_SWITCH_PORT_REG(n, p, r, d) \
- WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
-#define RD_SWITCH_PORT_REG(n, p, r, d) \
- RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
-#else
-static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data)
+static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
{
- printf("mv88e61xx %s dev %02x reg %02x write %04x\n",
- name, dev_adr, reg_ofs, data);
- wr_switch_reg(name, dev_adr, reg_ofs, data);
+ struct mv88e61xx_phy_priv *priv = phydev->priv;
+ struct mii_dev *mdio_bus = priv->mdio_bus;
+ int smi_addr = priv->smi_addr;
+ int res;
+
+ /* In single-chip mode, the device can be addressed directly */
+ if (smi_addr == 0)
+ return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
+
+ /* Wait for the bus to become free */
+ res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+ if (res < 0)
+ return res;
+
+ /* Issue the read command */
+ res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
+ smi_cmd_read(dev, reg));
+ if (res < 0)
+ return res;
+
+ /* Wait for the read command to complete */
+ res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+ if (res < 0)
+ return res;
+
+ /* Read the data */
+ res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
+ if (res < 0)
+ return res;
+
+ return bitfield_extract(res, 0, 16);
}
-static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data)
+
+/* See the comment above mv88e61xx_reg_read */
+static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
+ u16 val)
{
- rd_switch_reg(name, dev_adr, reg_ofs, data);
- printf("mv88e61xx %s dev %02x reg %02x read %04x\n",
- name, dev_adr, reg_ofs, *data);
+ struct mv88e61xx_phy_priv *priv = phydev->priv;
+ struct mii_dev *mdio_bus = priv->mdio_bus;
+ int smi_addr = priv->smi_addr;
+ int res;
+
+ /* In single-chip mode, the device can be addressed directly */
+ if (smi_addr == 0) {
+ return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
+ val);
+ }
+
+ /* Wait for the bus to become free */
+ res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+ if (res < 0)
+ return res;
+
+ /* Set the data to write */
+ res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
+ SMI_DATA_REG, val);
+ if (res < 0)
+ return res;
+
+ /* Issue the write command */
+ res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
+ smi_cmd_write(dev, reg));
+ if (res < 0)
+ return res;
+
+ /* Wait for the write command to complete */
+ res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+ if (res < 0)
+ return res;
+
+ return 0;
}
-static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
- u16 data)
+
+static int mv88e61xx_phy_wait(struct phy_device *phydev)
{
- printf("mv88e61xx %s port %02x reg %02x write %04x\n",
- name, prt_adr, reg_ofs, data);
- wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
+ int val;
+ u32 timeout = 100;
+
+ do {
+ val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_CMD);
+ if (val >= 0 && (val & SMI_BUSY) == 0)
+ return 0;
+
+ mdelay(1);
+ } while (--timeout);
+
+ return -ETIMEDOUT;
}
-static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
- u16 *data)
+
+static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
+ int devad, int reg)
{
- rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
- printf("mv88e61xx %s port %02x reg %02x read %04x\n",
- name, prt_adr, reg_ofs, *data);
+ struct phy_device *phydev;
+ int res;
+
+ phydev = (struct phy_device *)smi_wrapper->priv;
+
+ /* Issue command to read */
+ res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_CMD,
+ smi_cmd_read(dev, reg));
+
+ /* Wait for data to be read */
+ res = mv88e61xx_phy_wait(phydev);
+ if (res < 0)
+ return res;
+
+ /* Read retrieved data */
+ return mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_DATA);
}
-#endif
-/*
- * Local functions to read/write registers on the switch PHYs.
- * NOTE! This goes through switch, not direct miiphy, writes and reads!
- */
+static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
+ int devad, int reg, u16 data)
+{
+ struct phy_device *phydev;
+ int res;
+
+ phydev = (struct phy_device *)smi_wrapper->priv;
+
+ /* Set the data to write */
+ res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_DATA, data);
+ if (res < 0)
+ return res;
+ /* Issue the write command */
+ res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_CMD,
+ smi_cmd_write(dev, reg));
+ if (res < 0)
+ return res;
+
+ /* Wait for command to complete */
+ return mv88e61xx_phy_wait(phydev);
+}
-/*
- * Make sure SMIBusy bit cleared before another
- * SMI operation can take place
- */
-static int mv88e61xx_busychk(char *name)
+/* Wrapper function to make calls to phy_read_indirect simpler */
+static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
{
- u16 reg = 0;
- u32 timeout = MV88E61XX_PHY_TIMEOUT;
- do {
- rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR,
- MV88E61XX_PHY_CMD, &reg);
- if (timeout-- == 0) {
- printf("SMI busy timeout\n");
- return -1;
- }
- } while (reg & 1 << 15); /* busy mask */
- return 0;
+ return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
+ MDIO_DEVAD_NONE, reg);
}
-static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy,
- u32 reg, u16 data)
+/* Wrapper function to make calls to phy_read_indirect simpler */
+static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
+ int reg, u16 val)
{
- /* write switch data reg then cmd reg then check completion */
- wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA,
- data);
- wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
- (MV88E61XX_PHY_WRITE_CMD | (phy << 5) | reg));
- return mv88e61xx_busychk(name);
+ return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
+ MDIO_DEVAD_NONE, reg, val);
}
-static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy,
- u32 reg, u16 *data)
+static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
{
- /* write switch cmd reg, check for completion */
- wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
- (MV88E61XX_PHY_READ_CMD | (phy << 5) | reg));
- if (mv88e61xx_busychk(name))
- return -1;
- /* read switch data reg and return success */
- rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data);
- return 0;
+ return mv88e61xx_reg_read(phydev, DEVADDR_PORT(port), reg);
}
-/*
- * Convenience macros for switch PHY reads/writes
- */
+static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
+ u16 val)
+{
+ return mv88e61xx_reg_write(phydev, DEVADDR_PORT(port), reg, val);
+}
-#ifndef DEBUG
-#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write
-#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read
-#else
-static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr,
- u32 reg_ofs, u16 data)
-{
- int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data);
- if (r)
- printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n",
- name, phy_adr, reg_ofs);
- else
- printf("mv88e61xx %s phy %02x reg %02x write %04x\n",
- name, phy_adr, reg_ofs, data);
- return r;
+static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
+{
+ return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
}
-static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr,
- u32 reg_ofs, u16 *data)
+
+static int mv88e61xx_get_switch_id(struct phy_device *phydev)
{
- int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data);
- if (r)
- printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n",
- name, phy_adr, reg_ofs);
- else
- printf("mv88e61xx %s phy %02x reg %02x read %04x\n",
- name, phy_adr, reg_ofs, *data);
- return r;
+ int res;
+
+ res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
+ if (res < 0)
+ return res;
+ return res & 0xfff0;
}
-#endif
-static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig)
-{
- u32 prt;
- u16 reg;
- char *name = swconfig->name;
- u32 port_mask = swconfig->ports_enabled;
-
- /* apply internal vlan config */
- for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
- /* only for enabled ports */
- if ((1 << prt) & port_mask) {
- /* take vlan map from swconfig */
- u8 vlanmap = swconfig->vlancfg[prt];
- /* remove disabled ports from vlan map */
- vlanmap &= swconfig->ports_enabled;
- /* apply vlan map to port */
- RD_SWITCH_PORT_REG(name, prt,
- MV88E61XX_PRT_VMAP_REG, &reg);
- reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1);
- reg |= vlanmap;
- WR_SWITCH_PORT_REG(name, prt,
- MV88E61XX_PRT_VMAP_REG, reg);
- }
+static bool mv88e61xx_6352_family(struct phy_device *phydev)
+{
+ struct mv88e61xx_phy_priv *priv = phydev->priv;
+
+ switch (priv->id) {
+ case PORT_SWITCH_ID_6172:
+ case PORT_SWITCH_ID_6176:
+ case PORT_SWITCH_ID_6240:
+ case PORT_SWITCH_ID_6352:
+ return true;
}
+ return false;
}
-/*
- * Power up the specified port and reset PHY
- */
-static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy)
+static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
{
- char *name = swconfig->name;
+ int res;
- /* Write Copper Specific control reg1 (0x10) for-
- * Enable Phy power up
- * Energy Detect on (sense&Xmit NLP Periodically
- * reset other settings default
- */
- if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360))
- return -1;
+ res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
+ if (res < 0)
+ return res;
+ return res & PORT_REG_STATUS_CMODE_MASK;
+}
- /* Write PHY ctrl reg (0x0) to apply
- * Phy reset (set bit 15 low)
- * reset other default values
- */
- if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140))
- return -1;
+static int mv88e61xx_parse_status(struct phy_device *phydev)
+{
+ unsigned int speed;
+ unsigned int mii_reg;
+
+ mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
+
+ if ((mii_reg & PHY_REG_STATUS1_LINK) &&
+ !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
+ int i = 0;
+
+ puts("Waiting for PHY realtime link");
+ while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
+ /* Timeout reached ? */
+ if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+ puts(" TIMEOUT !\n");
+ phydev->link = 0;
+ break;
+ }
+
+ if ((i++ % 1000) == 0)
+ putc('.');
+ udelay(1000);
+ mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
+ PHY_REG_STATUS1);
+ }
+ puts(" done\n");
+ udelay(500000); /* another 500 ms (results in faster booting) */
+ } else {
+ if (mii_reg & PHY_REG_STATUS1_LINK)
+ phydev->link = 1;
+ else
+ phydev->link = 0;
+ }
+
+ if (mii_reg & PHY_REG_STATUS1_DUPLEX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+
+ speed = mii_reg & PHY_REG_STATUS1_SPEED;
+
+ switch (speed) {
+ case PHY_REG_STATUS1_GBIT:
+ phydev->speed = SPEED_1000;
+ break;
+ case PHY_REG_STATUS1_100:
+ phydev->speed = SPEED_100;
+ break;
+ default:
+ phydev->speed = SPEED_10;
+ break;
+ }
return 0;
}
-/*
- * Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3)
- * is set to "On-1000Mb/s Link, Off Else"
- * This function sets it to "On-Link, Blink-Activity, Off-NoLink"
- *
- * This is optional settings may be needed on some boards
- * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s
- * Link status
- */
-static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy)
+static int mv88e61xx_switch_reset(struct phy_device *phydev)
{
- char *name = swconfig->name;
+ int time;
+ int val;
+ u8 port;
+
+ /* Disable all ports */
+ for (port = 0; port < PORT_COUNT; port++) {
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
+ if (val < 0)
+ return val;
+ val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
+ PORT_REG_CTRL_PSTATE_WIDTH,
+ PORT_REG_CTRL_PSTATE_DISABLED);
+ val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
+ if (val < 0)
+ return val;
+ }
- if (swconfig->led_init != MV88E61XX_LED_INIT_EN)
- return 0;
+ /* Wait 2 ms for queues to drain */
+ udelay(2000);
+
+ /* Reset switch */
+ val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_CTRL);
+ if (val < 0)
+ return val;
+ val |= GLOBAL1_CTRL_SWRESET;
+ val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
+ GLOBAL1_CTRL, val);
+ if (val < 0)
+ return val;
+
+ /* Wait up to 1 second for switch reset complete */
+ for (time = 1000; time; time--) {
+ val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1,
+ GLOBAL1_CTRL);
+ if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
+ break;
+ udelay(1000);
+ }
+ if (!time)
+ return -ETIMEDOUT;
- /* set page address to 3 */
- if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003))
- return -1;
+ return 0;
+}
- /*
- * set LED Func Ctrl reg
- * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink
- */
- if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001))
- return -1;
+static int mv88e61xx_serdes_init(struct phy_device *phydev)
+{
+ int val;
- /* set page address to 0 */
- if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000))
- return -1;
+ val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
+ if (val < 0)
+ return val;
+
+ /* Power up serdes module */
+ val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
+ if (val < 0)
+ return val;
+ val &= ~(BMCR_PDOWN);
+ val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
+ if (val < 0)
+ return val;
return 0;
}
-/*
- * Reverse Transmit polarity for Media Dependent Interface
- * Pins (MDIP) bits in Copper Specific Control Register 3
- * (Page 0, Reg 20 for each phy (except cpu port)
- * Reference: Section 1.1 Switch datasheet-3
- *
- * This is optional settings may be needed on some boards
- * for PHY<->magnetics h/w tuning
- */
-static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy)
+static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
{
- char *name = swconfig->name;
+ int val;
+
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
+ if (val < 0)
+ return val;
+ val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
+ PORT_REG_CTRL_PSTATE_WIDTH,
+ PORT_REG_CTRL_PSTATE_FORWARD);
+ val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
+ if (val < 0)
+ return val;
- if (swconfig->mdip != MV88E61XX_MDIP_REVERSE)
- return 0;
+ return 0;
+}
- /*Reverse MDIP/N[3:0] bits */
- if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f))
- return -1;
+static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
+ u8 mask)
+{
+ int val;
+
+ /* Set VID to port number plus one */
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
+ if (val < 0)
+ return val;
+ val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
+ PORT_REG_VLAN_ID_DEF_VID_WIDTH,
+ port + 1);
+ val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
+ if (val < 0)
+ return val;
+
+ /* Set VID mask */
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
+ if (val < 0)
+ return val;
+ val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
+ PORT_REG_VLAN_MAP_TABLE_WIDTH,
+ mask);
+ val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
+ if (val < 0)
+ return val;
return 0;
}
-/*
- * Marvell 88E61XX Switch initialization
- */
-int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
+static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
{
- u32 prt;
- u16 reg;
- char *idstr;
- char *name = swconfig->name;
- int time;
-
- if (miiphy_set_current_dev(name)) {
- printf("%s failed\n", __FUNCTION__);
- return -1;
+ int res;
+ int val;
+ bool forced = false;
+
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
+ if (val < 0)
+ return val;
+ if (!(val & PORT_REG_STATUS_LINK)) {
+ /* Temporarily force link to read port configuration */
+ u32 timeout = 100;
+ forced = true;
+
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
+ if (val < 0)
+ return val;
+ val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
+ PORT_REG_PHYS_CTRL_LINK_VALUE);
+ val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
+ val);
+ if (val < 0)
+ return val;
+
+ /* Wait for status register to reflect forced link */
+ do {
+ val = mv88e61xx_port_read(phydev, port,
+ PORT_REG_STATUS);
+ if (val < 0)
+ goto unforce;
+ if (val & PORT_REG_STATUS_LINK)
+ break;
+ } while (--timeout);
+
+ if (timeout == 0) {
+ res = -ETIMEDOUT;
+ goto unforce;
+ }
}
- if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) {
- swconfig->cpuport = (1 << 5);
- printf("Invalid cpu port config, using default port5\n");
- }
+ if (val & PORT_REG_STATUS_DUPLEX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
- RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, &reg);
- switch (reg &= 0xfff0) {
- case 0x1610:
- idstr = "88E6161";
- break;
- case 0x1650:
- idstr = "88E6165";
+ val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
+ PORT_REG_STATUS_SPEED_WIDTH);
+ switch (val) {
+ case PORT_REG_STATUS_SPEED_1000:
+ phydev->speed = SPEED_1000;
break;
- case 0x1210:
- idstr = "88E6123";
- /* ports 2,3,4 not available */
- swconfig->ports_enabled &= 0x023;
+ case PORT_REG_STATUS_SPEED_100:
+ phydev->speed = SPEED_100;
break;
default:
- /* Could not detect switch id */
- idstr = "88E61??";
+ phydev->speed = SPEED_10;
break;
}
- /* be sure all ports are disabled */
- for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
- RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, &reg);
- reg &= ~0x3;
- WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg);
+ res = 0;
+
+unforce:
+ if (forced) {
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
+ if (val < 0)
+ return val;
+ val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
+ PORT_REG_PHYS_CTRL_LINK_VALUE);
+ val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
+ val);
+ if (val < 0)
+ return val;
}
- /* wait 2 ms for queues to drain */
- udelay(2000);
-
- /* reset switch */
- RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, &reg);
- reg |= 0x8000;
- WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg);
+ return res;
+}
- /* wait up to 1 second for switch reset complete */
- for (time = 1000; time; time--) {
- RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR,
- &reg);
- if ((reg & 0xc800) == 0xc800)
- break;
- udelay(1000);
- }
- if (!time)
- return -1;
-
- /* Port based VLANs configuration */
- mv88e61xx_port_vlan_config(swconfig);
-
- if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 9.5 of chip datasheet-02
- */
- /*Force port link down */
- WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10);
- /* configure port RGMII delay */
- WR_SWITCH_PORT_REG(name, 4,
- MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7);
- RD_SWITCH_PORT_REG(name, 5,
- MV88E61XX_RGMII_TIMECTRL_REG, &reg);
- WR_SWITCH_PORT_REG(name, 5,
- MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18);
- WR_SWITCH_PORT_REG(name, 4,
- MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
- /* Force port to RGMII FDX 1000Base then up */
- WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e);
- WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e);
+static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
+{
+ int val;
+
+ /* Set CPUDest */
+ val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_MON_CTRL);
+ if (val < 0)
+ return val;
+ val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
+ GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
+ CONFIG_MV88E61XX_CPU_PORT);
+ val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
+ GLOBAL1_MON_CTRL, val);
+ if (val < 0)
+ return val;
+
+ /* Allow CPU to route to any port */
+ val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
+ val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
+ if (val < 0)
+ return val;
+
+ /* Enable CPU port */
+ val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
+ if (val < 0)
+ return val;
+
+ val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
+ if (val < 0)
+ return val;
+
+ /* If CPU is connected to serdes, initialize serdes */
+ if (mv88e61xx_6352_family(phydev)) {
+ val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
+ if (val < 0)
+ return val;
+ if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
+ val == PORT_REG_STATUS_CMODE_1000BASE_X ||
+ val == PORT_REG_STATUS_CMODE_SGMII) {
+ val = mv88e61xx_serdes_init(phydev);
+ if (val < 0)
+ return val;
+ }
}
- for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
-
- /* configure port's PHY */
- if (!((1 << prt) & swconfig->cpuport)) {
- /* port 4 has phy 6, not 4 */
- int phy = (prt == 4) ? 6 : prt;
- if (mv88361xx_powerup(swconfig, phy))
- return -1;
- if (mv88361xx_reverse_mdipn(swconfig, phy))
- return -1;
- if (mv88361xx_led_init(swconfig, phy))
- return -1;
- }
+ return 0;
+}
- /* set port VID to port+1 except for cpu port */
- if (!((1 << prt) & swconfig->cpuport)) {
- RD_SWITCH_PORT_REG(name, prt,
- MV88E61XX_PRT_VID_REG, &reg);
- WR_SWITCH_PORT_REG(name, prt,
- MV88E61XX_PRT_VID_REG,
- (reg & ~1023) | (prt+1));
- }
+static int mv88e61xx_switch_init(struct phy_device *phydev)
+{
+ static int init;
+ int res;
- /*Program port state */
- RD_SWITCH_PORT_REG(name, prt,
- MV88E61XX_PRT_CTRL_REG, &reg);
- WR_SWITCH_PORT_REG(name, prt,
- MV88E61XX_PRT_CTRL_REG,
- reg | (swconfig->portstate & 0x03));
+ if (init)
+ return 0;
- }
+ res = mv88e61xx_switch_reset(phydev);
+ if (res < 0)
+ return res;
+
+ res = mv88e61xx_set_cpu_port(phydev);
+ if (res < 0)
+ return res;
+
+ init = 1;
- printf("%s Initialized on %s\n", idstr, name);
return 0;
}
-#ifdef CONFIG_MV88E61XX_CMD
-static int
-do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
{
- char *name, *endp;
- int write = 0;
- enum { dev, prt, phy } target = dev;
- u32 addrlo, addrhi, addr;
- u32 reglo, reghi, reg;
- u16 data, rdata;
+ int val;
- if (argc < 7)
- return -1;
+ val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
+ if (val < 0)
+ return val;
+ val &= ~(BMCR_PDOWN);
+ val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
+ if (val < 0)
+ return val;
- name = argv[1];
+ return 0;
+}
- if (strcmp(argv[2], "phy") == 0)
- target = phy;
- else if (strcmp(argv[2], "port") == 0)
- target = prt;
- else if (strcmp(argv[2], "dev") != 0)
- return 1;
+static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
+{
+ int val;
- addrlo = simple_strtoul(argv[3], &endp, 16);
+ /*
+ * Enable energy-detect sensing on PHY, used to determine when a PHY
+ * port is physically connected
+ */
+ val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
+ if (val < 0)
+ return val;
+ val = bitfield_replace(val, PHY_REG_CTRL1_ENERGY_DET_SHIFT,
+ PHY_REG_CTRL1_ENERGY_DET_WIDTH,
+ PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT);
+ val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
+ if (val < 0)
+ return val;
- if (!*endp) {
- addrhi = addrlo;
- } else {
- while (*endp < '0' || *endp > '9')
- endp++;
- addrhi = simple_strtoul(endp, NULL, 16);
- }
+ return 0;
+}
- reglo = simple_strtoul(argv[5], &endp, 16);
- if (!*endp) {
- reghi = reglo;
- } else {
- while (*endp < '0' || *endp > '9')
- endp++;
- reghi = simple_strtoul(endp, NULL, 16);
+static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
+{
+ int val;
+
+ val = mv88e61xx_port_enable(phydev, phy);
+ if (val < 0)
+ return val;
+
+ val = mv88e61xx_port_set_vlan(phydev, phy,
+ 1 << CONFIG_MV88E61XX_CPU_PORT);
+ if (val < 0)
+ return val;
+
+ return 0;
+}
+
+static int mv88e61xx_probe(struct phy_device *phydev)
+{
+ struct mii_dev *smi_wrapper;
+ struct mv88e61xx_phy_priv *priv;
+ int res;
+
+ res = mv88e61xx_hw_reset(phydev);
+ if (res < 0)
+ return res;
+
+ priv = malloc(sizeof(*priv));
+ if (!priv)
+ return -ENOMEM;
+
+ memset(priv, 0, sizeof(*priv));
+
+ /*
+ * This device requires indirect reads/writes to the PHY registers
+ * which the generic PHY code can't handle. Make a wrapper MII device
+ * to handle reads/writes
+ */
+ smi_wrapper = mdio_alloc();
+ if (!smi_wrapper) {
+ free(priv);
+ return -ENOMEM;
}
- if (strcmp(argv[6], "write") == 0)
- write = 1;
- else if (strcmp(argv[6], "read") != 0)
- return 1;
-
- data = simple_strtoul(argv[7], NULL, 16);
-
- for (addr = addrlo; addr <= addrhi; addr++) {
- for (reg = reglo; reg <= reghi; reg++) {
- if (write) {
- if (target == phy)
- mv88e61xx_switch_miiphy_write(
- name, addr, reg, data);
- else if (target == prt)
- wr_switch_reg(name,
- addr+MV88E61XX_PRT_OFST,
- reg, data);
- else
- wr_switch_reg(name, addr, reg, data);
- } else {
- if (target == phy)
- mv88e61xx_switch_miiphy_read(
- name, addr, reg, &rdata);
- else if (target == prt)
- rd_switch_reg(name,
- addr+MV88E61XX_PRT_OFST,
- reg, &rdata);
- else
- rd_switch_reg(name, addr, reg, &rdata);
- printf("%s %s %s %02x %s %02x %s %04x\n",
- argv[0], argv[1], argv[2], addr,
- argv[4], reg, argv[6], rdata);
- if (write && argc == 7 && rdata != data)
- return 1;
+ /*
+ * Store the mdio bus in the private data, as we are going to replace
+ * the bus with the wrapper bus
+ */
+ priv->mdio_bus = phydev->bus;
+
+ /*
+ * Store the smi bus address in private data. This lets us use the
+ * phydev addr field for device address instead, as the genphy code
+ * expects.
+ */
+ priv->smi_addr = phydev->addr;
+
+ /*
+ * Store the phy_device in the wrapper mii device. This lets us get it
+ * back when genphy functions call phy_read/phy_write.
+ */
+ smi_wrapper->priv = phydev;
+ strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
+ smi_wrapper->read = mv88e61xx_phy_read_indirect;
+ smi_wrapper->write = mv88e61xx_phy_write_indirect;
+
+ /* Replace the bus with the wrapper device */
+ phydev->bus = smi_wrapper;
+
+ phydev->priv = priv;
+
+ priv->id = mv88e61xx_get_switch_id(phydev);
+
+ return 0;
+}
+
+static int mv88e61xx_phy_config(struct phy_device *phydev)
+{
+ int res;
+ int i;
+ int ret = -1;
+
+ res = mv88e61xx_switch_init(phydev);
+ if (res < 0)
+ return res;
+
+ for (i = 0; i < PORT_COUNT; i++) {
+ if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
+ phydev->addr = i;
+
+ res = mv88e61xx_phy_enable(phydev, i);
+ if (res < 0) {
+ printf("Error enabling PHY %i\n", i);
+ continue;
+ }
+ res = mv88e61xx_phy_setup(phydev, i);
+ if (res < 0) {
+ printf("Error setting up PHY %i\n", i);
+ continue;
}
+ res = mv88e61xx_phy_config_port(phydev, i);
+ if (res < 0) {
+ printf("Error configuring PHY %i\n", i);
+ continue;
+ }
+
+ res = genphy_config_aneg(phydev);
+ if (res < 0) {
+ printf("Error setting PHY %i autoneg\n", i);
+ continue;
+ }
+ res = phy_reset(phydev);
+ if (res < 0) {
+ printf("Error resetting PHY %i\n", i);
+ continue;
+ }
+
+ /* Return success if any PHY succeeds */
+ ret = 0;
}
}
+
+ return ret;
+}
+
+static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
+{
+ int val;
+
+ val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
+ if (val < 0)
+ return 0;
+
+ /*
+ * After reset, the energy detect signal remains high for a few seconds
+ * regardless of whether a cable is connected. This function will
+ * return false positives during this time.
+ */
+ return (val & PHY_REG_STATUS1_ENERGY) == 0;
+}
+
+static int mv88e61xx_phy_startup(struct phy_device *phydev)
+{
+ int i;
+ int link = 0;
+ int res;
+ int speed = phydev->speed;
+ int duplex = phydev->duplex;
+
+ for (i = 0; i < PORT_COUNT; i++) {
+ if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
+ phydev->addr = i;
+ if (!mv88e61xx_phy_is_connected(phydev))
+ continue;
+ res = genphy_update_link(phydev);
+ if (res < 0)
+ continue;
+ res = mv88e61xx_parse_status(phydev);
+ if (res < 0)
+ continue;
+ link = (link || phydev->link);
+ }
+ }
+ phydev->link = link;
+
+ /* Restore CPU interface speed and duplex after it was changed for
+ * other ports */
+ phydev->speed = speed;
+ phydev->duplex = duplex;
+
+ return 0;
+}
+
+static struct phy_driver mv88e61xx_driver = {
+ .name = "Marvell MV88E61xx",
+ .uid = 0x01410eb1,
+ .mask = 0xfffffff0,
+ .features = PHY_GBIT_FEATURES,
+ .probe = mv88e61xx_probe,
+ .config = mv88e61xx_phy_config,
+ .startup = mv88e61xx_phy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+int phy_mv88e61xx_init(void)
+{
+ phy_register(&mv88e61xx_driver);
+
return 0;
}
-U_BOOT_CMD(mv88e61xx, 8, 0, do_switch,
- "Read or write mv88e61xx switch registers",
- "<ethdevice> dev|port|phy <addr> reg <reg> write <data>\n"
- "<ethdevice> dev|port|phy <addr> reg <reg> read [<data>]\n"
- " - read/write switch device, port or phy at (addr,reg)\n"
- " addr=0..0x1C for dev, 0..5 for port or phy.\n"
- " reg=0..0x1F.\n"
- " data=0..0xFFFF (tested if present against actual read).\n"
- " All numeric parameters are assumed to be hex.\n"
- " <addr> and <<reg> arguments can be ranges (x..y)"
-);
-#endif /* CONFIG_MV88E61XX_CMD */
+/*
+ * Overload weak get_phy_id definition since we need non-standard functions
+ * to read PHY registers
+ */
+int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
+{
+ struct phy_device temp_phy;
+ struct mv88e61xx_phy_priv temp_priv;
+ struct mii_dev temp_mii;
+ int val;
+
+ /*
+ * Buid temporary data structures that the chip reading code needs to
+ * read the ID
+ */
+ temp_priv.mdio_bus = bus;
+ temp_priv.smi_addr = smi_addr;
+ temp_phy.priv = &temp_priv;
+ temp_mii.priv = &temp_phy;
+
+ val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
+ if (val < 0)
+ return -EIO;
+
+ *phy_id = val << 16;
+
+ val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
+ if (val < 0)
+ return -EIO;
+
+ *phy_id |= (val & 0xffff);
+
+ return 0;
+}
diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h
deleted file mode 100644
index 9c62e4a..0000000
--- a/drivers/net/phy/mv88e61xx.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _MV88E61XX_H
-#define _MV88E61XX_H
-
-#include <miiphy.h>
-
-#define MV88E61XX_CPU_PORT 0x5
-
-#define MV88E61XX_PHY_TIMEOUT 100000
-
-/* port dev-addr (= port + 0x10) */
-#define MV88E61XX_PRT_OFST 0x10
-/* port registers */
-#define MV88E61XX_PCS_CTRL_REG 0x1
-#define MV88E61XX_PRT_CTRL_REG 0x4
-#define MV88E61XX_PRT_VMAP_REG 0x6
-#define MV88E61XX_PRT_VID_REG 0x7
-#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A
-
-/* global registers dev-addr */
-#define MV88E61XX_GLBREG_DEVADR 0x1B
-/* global registers */
-#define MV88E61XX_SGSR 0x00
-#define MV88E61XX_SGCR 0x04
-
-/* global 2 registers dev-addr */
-#define MV88E61XX_GLB2REG_DEVADR 0x1C
-/* global 2 registers */
-#define MV88E61XX_PHY_CMD 0x18
-#define MV88E61XX_PHY_DATA 0x19
-/* global 2 phy commands */
-#define MV88E61XX_PHY_WRITE_CMD 0x9400
-#define MV88E61XX_PHY_READ_CMD 0x9800
-
-#define MV88E61XX_BUSY_OFST 15
-#define MV88E61XX_MODE_OFST 12
-#define MV88E61XX_OP_OFST 10
-#define MV88E61XX_ADDR_OFST 5
-
-#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-static int mv88e61xx_busychk_multic(char *name, u32 devaddr);
-static void mv88e61xx_switch_write(char *name, u32 phy_adr,
- u32 reg_ofs, u16 data);
-static void mv88e61xx_switch_read(char *name, u32 phy_adr,
- u32 reg_ofs, u16 *data);
-#define wr_switch_reg mv88e61xx_switch_write
-#define rd_switch_reg mv88e61xx_switch_read
-#else
-/* switch appears a s simple PHY and can thus use miiphy */
-#define wr_switch_reg miiphy_write
-#define rd_switch_reg miiphy_read
-#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
-
-#endif /* _MV88E61XX_H */
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 4b6c09f..80bdfb6 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -461,6 +461,9 @@ static LIST_HEAD(phy_drivers);
int phy_init(void)
{
+#ifdef CONFIG_MV88E61XX_SWITCH
+ phy_mv88e61xx_init();
+#endif
#ifdef CONFIG_PHY_AQUANTIA
phy_aquantia_init();
#endif
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index 937426b..c55dd97 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -6,6 +6,14 @@
*/
#include <common.h>
#include <phy.h>
+#include <linux/compat.h>
+#include <malloc.h>
+
+#include <fdtdec.h>
+#include <dm.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+DECLARE_GLOBAL_DATA_PTR;
/* TI DP83867 */
#define DP83867_DEVADDR 0x1f
@@ -71,6 +79,17 @@
#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
+/* User setting - can be taken from DTS */
+#define DEFAULT_RX_ID_DELAY DP83867_RGMIIDCTL_2_25_NS
+#define DEFAULT_TX_ID_DELAY DP83867_RGMIIDCTL_2_75_NS
+#define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
+
+struct dp83867_private {
+ int rx_id_delay;
+ int tx_id_delay;
+ int fifo_depth;
+};
+
/**
* phy_read_mmd_indirect - reads data from the MMD registers
* @phydev: The PHY device bus
@@ -137,27 +156,60 @@ void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
phy_write(phydev, addr, MII_MMD_DATA, data);
}
+#if defined(CONFIG_DM_ETH)
/**
- * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
- * is RGMII (all variants)
+ * dp83867_data_init - Convenience function for setting PHY specific data
+ *
* @phydev: the phy_device struct
*/
-static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
+static int dp83867_of_init(struct phy_device *phydev)
{
- return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
- phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
+ struct dp83867_private *dp83867 = phydev->priv;
+ struct udevice *dev = phydev->dev;
+
+ dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ "ti,rx-internal-delay", -1);
+
+ dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ "ti,tx-internal-delay", -1);
+
+ dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ "ti,fifo-depth", -1);
+
+ return 0;
}
+#else
+static int dp83867_of_init(struct phy_device *phydev)
+{
+ struct dp83867_private *dp83867 = phydev->priv;
-/* User setting - can be taken from DTS */
-#define RX_ID_DELAY 8
-#define TX_ID_DELAY 0xa
-#define FIFO_DEPTH 1
+ dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
+ dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
+ dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
+
+ return 0;
+}
+#endif
static int dp83867_config(struct phy_device *phydev)
{
+ struct dp83867_private *dp83867;
unsigned int val, delay, cfg2;
int ret;
+ if (!phydev->priv) {
+ dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
+ if (!dp83867)
+ return -ENOMEM;
+
+ phydev->priv = dp83867;
+ ret = dp83867_of_init(phydev);
+ if (ret)
+ goto err_out;
+ } else {
+ dp83867 = (struct dp83867_private *)phydev->priv;
+ }
+
/* Restart the PHY. */
val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
@@ -166,10 +218,10 @@ static int dp83867_config(struct phy_device *phydev)
if (phy_interface_is_rgmii(phydev)) {
ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
- (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
+ (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
if (ret)
- return ret;
- } else {
+ goto err_out;
+ } else if (phy_interface_is_sgmii(phydev)) {
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
(BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
@@ -189,8 +241,8 @@ static int dp83867_config(struct phy_device *phydev)
DP83867_PHYCTRL_SGMIIEN |
(DP83867_MDI_CROSSOVER_MDIX <<
DP83867_MDI_CROSSOVER) |
- (FIFO_DEPTH << DP83867_PHYCTRL_RXFIFO_SHIFT) |
- (FIFO_DEPTH << DP83867_PHYCTRL_TXFIFO_SHIFT));
+ (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
+ (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
}
@@ -212,8 +264,8 @@ static int dp83867_config(struct phy_device *phydev)
phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
DP83867_DEVADDR, phydev->addr, val);
- delay = (RX_ID_DELAY |
- (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
+ delay = (dp83867->rx_id_delay |
+ (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
DP83867_DEVADDR, phydev->addr, delay);
@@ -221,6 +273,10 @@ static int dp83867_config(struct phy_device *phydev)
genphy_config_aneg(phydev);
return 0;
+
+err_out:
+ kfree(dp83867);
+ return ret;
}
static struct phy_driver DP83867_driver = {
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 4d9c296..519699d 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -179,6 +179,7 @@ struct zynq_gem_priv {
struct zynq_gem_regs *iobase;
phy_interface_t interface;
struct phy_device *phydev;
+ int phy_of_handle;
struct mii_dev *bus;
};
@@ -353,6 +354,9 @@ static int zynq_phy_init(struct udevice *dev)
ADVERTISED_Asym_Pause;
priv->phydev->advertising = priv->phydev->supported;
+ if (priv->phy_of_handle > 0)
+ priv->phydev->dev->of_offset = priv->phy_of_handle;
+
return phy_config(priv->phydev);
}
@@ -677,7 +681,6 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
- int offset = 0;
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
@@ -686,10 +689,11 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
priv->emio = 0;
priv->phyaddr = -1;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
- "phy-handle");
- if (offset > 0)
- priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
+ priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob,
+ dev->of_offset, "phy-handle");
+ if (priv->phy_of_handle > 0)
+ priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
+ priv->phy_of_handle, "reg", -1);
phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
if (phy_mode)
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index b049be4..2135af0 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -153,6 +153,7 @@
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_MMC
#undef CONFIG_TIMER
+#undef CONFIG_DM_ETH
#endif
#endif /* __CONFIG_TI_OMAP5_COMMON_H */
diff --git a/include/cpsw.h b/include/cpsw.h
index cf1d30b..257d12a 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -21,6 +21,7 @@ struct cpsw_slave_data {
u32 sliver_reg_ofs;
int phy_addr;
int phy_if;
+ int phy_of_handle;
};
enum {
@@ -51,5 +52,6 @@ struct cpsw_platform_data {
};
int cpsw_register(struct cpsw_platform_data *data);
+int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr);
#endif /* _CPSW_H_ */
diff --git a/include/dm/device.h b/include/dm/device.h
index e9a8ec7..f03bcd3 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -548,6 +548,29 @@ int device_set_name(struct udevice *dev, const char *name);
void device_set_name_alloced(struct udevice *dev);
/**
+ * of_device_is_compatible() - check if the device is compatible with the compat
+ *
+ * This allows to check whether the device is comaptible with the compat.
+ *
+ * @dev: udevice pointer for which compatible needs to be verified.
+ * @compat: Compatible string which needs to verified in the given
+ * device
+ * @return true if OK, false if the compatible is not found
+ */
+bool of_device_is_compatible(struct udevice *dev, const char *compat);
+
+/**
+ * of_machine_is_compatible() - check if the machine is compatible with
+ * the compat
+ *
+ * This allows to check whether the machine is comaptible with the compat.
+ *
+ * @compat: Compatible string which needs to verified
+ * @return true if OK, false if the compatible is not found
+ */
+bool of_machine_is_compatible(const char *compat);
+
+/**
* device_is_on_pci_bus - Test if a device is on a PCI bus
*
* @dev: device to test
diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
new file mode 100644
index 0000000..1843757
--- /dev/null
+++ b/include/dt-bindings/net/ti-dp83867.h
@@ -0,0 +1,35 @@
+/*
+ * TI DP83867 PHY drivers
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#ifndef _DT_BINDINGS_TI_DP83867_H
+#define _DT_BINDINGS_TI_DP83867_H
+
+/* PHY CTRL bits */
+#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
+#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
+#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
+#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
+
+/* RGMIIDCTL internal delay for rx and tx */
+#define DP83867_RGMIIDCTL_250_PS 0x0
+#define DP83867_RGMIIDCTL_500_PS 0x1
+#define DP83867_RGMIIDCTL_750_PS 0x2
+#define DP83867_RGMIIDCTL_1_NS 0x3
+#define DP83867_RGMIIDCTL_1_25_NS 0x4
+#define DP83867_RGMIIDCTL_1_50_NS 0x5
+#define DP83867_RGMIIDCTL_1_75_NS 0x6
+#define DP83867_RGMIIDCTL_2_00_NS 0x7
+#define DP83867_RGMIIDCTL_2_25_NS 0x8
+#define DP83867_RGMIIDCTL_2_50_NS 0x9
+#define DP83867_RGMIIDCTL_2_75_NS 0xa
+#define DP83867_RGMIIDCTL_3_00_NS 0xb
+#define DP83867_RGMIIDCTL_3_25_NS 0xc
+#define DP83867_RGMIIDCTL_3_50_NS 0xd
+#define DP83867_RGMIIDCTL_3_75_NS 0xe
+#define DP83867_RGMIIDCTL_4_00_NS 0xf
+
+#endif
diff --git a/include/netdev.h b/include/netdev.h
index 244f23f..7a211bc 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -134,64 +134,6 @@ static inline int pci_eth_init(bd_t *bis)
return num;
}
-/*
- * Boards with mv88e61xx switch can use this by defining
- * CONFIG_MV88E61XX_SWITCH in respective board configheader file
- * the stuct and enums here are used to specify switch configuration params
- */
-#if defined(CONFIG_MV88E61XX_SWITCH)
-
-/* constants for any 88E61xx switch */
-#define MV88E61XX_MAX_PORTS_NUM 6
-
-enum mv88e61xx_cfg_mdip {
- MV88E61XX_MDIP_NOCHANGE,
- MV88E61XX_MDIP_REVERSE
-};
-
-enum mv88e61xx_cfg_ledinit {
- MV88E61XX_LED_INIT_DIS,
- MV88E61XX_LED_INIT_EN
-};
-
-enum mv88e61xx_cfg_rgmiid {
- MV88E61XX_RGMII_DELAY_DIS,
- MV88E61XX_RGMII_DELAY_EN
-};
-
-enum mv88e61xx_cfg_prtstt {
- MV88E61XX_PORTSTT_DISABLED,
- MV88E61XX_PORTSTT_BLOCKING,
- MV88E61XX_PORTSTT_LEARNING,
- MV88E61XX_PORTSTT_FORWARDING
-};
-
-struct mv88e61xx_config {
- char *name;
- u8 vlancfg[MV88E61XX_MAX_PORTS_NUM];
- enum mv88e61xx_cfg_rgmiid rgmii_delay;
- enum mv88e61xx_cfg_prtstt portstate;
- enum mv88e61xx_cfg_ledinit led_init;
- enum mv88e61xx_cfg_mdip mdip;
- u32 ports_enabled;
- u8 cpuport;
-};
-
-/*
- * Common mappings for Internal VLANs
- * These mappings consider that all ports are useable; the driver
- * will mask inexistent/unused ports.
- */
-
-/* Switch mode : routes any port to any port */
-#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F }
-
-/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */
-#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F }
-
-int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
-#endif /* CONFIG_MV88E61XX_SWITCH */
-
struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id);
#ifdef CONFIG_PHYLIB
struct phy_device;
diff --git a/include/phy.h b/include/phy.h
index 21459a8..268d9a1 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -249,6 +249,7 @@ int gen10g_startup(struct phy_device *phydev);
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);
+int phy_mv88e61xx_init(void);
int phy_aquantia_init(void);
int phy_atheros_init(void);
int phy_broadcom_init(void);
@@ -277,6 +278,28 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
*/
int phy_get_interface_by_name(const char *str);
+/**
+ * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
+ * is RGMII (all variants)
+ * @phydev: the phy_device struct
+ */
+static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
+{
+ return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
+ phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
+}
+
+/**
+ * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
+ * is SGMII (all variants)
+ * @phydev: the phy_device struct
+ */
+static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
+{
+ return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
+ phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
+}
+
/* PHY UIDs for various PHYs that are referenced in external code */
#define PHY_UID_CS4340 0x13e51002
#define PHY_UID_TN2020 0x00a19410
generated by cgit v1.1 at 2024-12-29 09:17:19 +0000