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-rw-r--r--CHANGELOG69
-rw-r--r--CREDITS7
-rw-r--r--MAINTAINERS13
-rwxr-xr-xMAKEALL34
-rw-r--r--Makefile17
-rw-r--r--board/at91rm9200dk/flash.c5
-rw-r--r--board/cogent/README.cma2862
-rw-r--r--board/esd/du405/du405.c14
-rw-r--r--board/esd/pci405/pci405.c67
-rw-r--r--board/esd/wuh405/fpgadata.c3543
-rw-r--r--board/hmi1001/hmi1001.c10
-rw-r--r--board/pm854/flash.c541
-rw-r--r--board/sandburst/common/flash.c512
-rw-r--r--board/sandburst/common/ppc440gx_i2c.c512
-rw-r--r--board/sandburst/common/ppc440gx_i2c.h64
-rw-r--r--board/sandburst/common/sb_common.c451
-rw-r--r--board/sandburst/common/sb_common.h76
-rw-r--r--board/sandburst/karef/Makefile59
-rw-r--r--board/sandburst/karef/config.mk43
-rw-r--r--board/sandburst/karef/hal_ka_of_auto.h324
-rw-r--r--board/sandburst/karef/hal_ka_sc_auto.h836
-rw-r--r--board/sandburst/karef/init.S101
-rw-r--r--board/sandburst/karef/karef.c577
-rw-r--r--board/sandburst/karef/karef.h76
-rw-r--r--board/sandburst/karef/karef_version.h26
-rw-r--r--board/sandburst/karef/u-boot.lds156
-rw-r--r--board/sandburst/karef/u-boot.lds.debug145
-rw-r--r--board/sandburst/metrobox/Makefile57
-rw-r--r--board/sandburst/metrobox/config.mk38
-rw-r--r--board/sandburst/metrobox/hal_xc_auto.h553
-rw-r--r--board/sandburst/metrobox/init.S99
-rw-r--r--board/sandburst/metrobox/metrobox.c543
-rw-r--r--board/sandburst/metrobox/metrobox.h45
-rw-r--r--board/sandburst/metrobox/metrobox_version.h27
-rw-r--r--board/sandburst/metrobox/u-boot.lds156
-rw-r--r--board/sandburst/metrobox/u-boot.lds.debug145
-rw-r--r--board/stxxtc/Makefile40
-rw-r--r--board/stxxtc/config.mk28
-rw-r--r--board/stxxtc/stxxtc.c638
-rw-r--r--board/stxxtc/u-boot.lds138
-rw-r--r--board/stxxtc/u-boot.lds.debug135
-rw-r--r--board/voiceblue/Makefile8
-rw-r--r--board/voiceblue/eeprom.c143
-rw-r--r--board/voiceblue/eeprom.lds51
-rw-r--r--board/voiceblue/eeprom_start.S11
-rw-r--r--common/cmd_jffs2.c10
-rw-r--r--common/cmd_nand.c3
-rw-r--r--common/hush.c18
-rw-r--r--common/miiphybb.c328
-rw-r--r--common/miiphyutil.c8
-rw-r--r--cpu/arm920t/at91rm9200/serial.c2
-rw-r--r--cpu/mips/config.mk12
-rw-r--r--cpu/mpc8xx/speed.c2
-rw-r--r--cpu/ppc4xx/440gx_enet.c29
-rw-r--r--doc/README.stxxtc59
-rw-r--r--drivers/cfi_flash.c4
-rw-r--r--fs/jffs2/jffs2_1pass.c4
-rw-r--r--include/common.h3
-rw-r--r--include/configs/DU405.h2
-rw-r--r--include/configs/KAREF.h309
-rw-r--r--include/configs/METROBOX.h377
-rw-r--r--include/configs/MIP405.h2
-rw-r--r--include/configs/PCI405.h1
-rw-r--r--include/configs/PIP405.h2
-rw-r--r--include/configs/VCMA9.h2
-rw-r--r--include/configs/WUH405.h1
-rw-r--r--include/configs/hmi1001.h18
-rw-r--r--include/configs/stxxtc.h592
-rw-r--r--include/ppc440.h2
-rw-r--r--include/status_led.h3
-rw-r--r--include/version.h2
-rw-r--r--lib_ppc/board.c4
-rw-r--r--net/net.c72
-rw-r--r--tools/bddb/README2
-rw-r--r--tools/bddb/badsubmit.php2
-rw-r--r--tools/bddb/brlog.php15
-rw-r--r--tools/bddb/browse.php55
-rw-r--r--tools/bddb/config.php2
-rw-r--r--tools/bddb/create_tables.sql82
-rw-r--r--tools/bddb/defs.php101
-rw-r--r--tools/bddb/dodelete.php5
-rw-r--r--tools/bddb/dodellog.php8
-rw-r--r--tools/bddb/doedit.php58
-rw-r--r--tools/bddb/doedlog.php19
-rw-r--r--tools/bddb/donew.php6
-rw-r--r--tools/bddb/donewlog.php17
-rw-r--r--tools/bddb/edit.php18
-rw-r--r--tools/bddb/edlog.php8
-rw-r--r--tools/bddb/execute.php10
-rw-r--r--tools/bddb/index.php2
-rw-r--r--tools/bddb/new.php19
-rw-r--r--tools/bddb/newlog.php15
-rw-r--r--tools/gdb/Makefile2
93 files changed, 10730 insertions, 2722 deletions
diff --git a/CHANGELOG b/CHANGELOG
index b0ff46e..2d24962 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,7 +1,76 @@
======================================================================
+Changes for U-Boot 1.1.4:
+======================================================================
+
+* Enable PCI on hmi1001 board
+
+* Fix return values of the jffs2 commands ls/fsload/fsinfo,
+ so we can use them to, e.g., check the existence of a file with
+ "if ls foo; then this; else that; fi" in the hush shell
+ Patch by Andreas Engel, 16 August 2005
+
+* Coding style cleanup
+
+* Add support for Silicon Turnkey eXpress XTc (mpc87x/88x) board.
+ Patch by Dan Malek and Pantelis Antoniou, 15 Aug 2005
+
+* Check return value of malloc in 440gx_enet.c
+ Patch by Travis B. Sawyer, 18 Jul 2005
+
+* Add Sandburst Metrobox and Sandburst Karef board support packages.
+ Second serial port on 440GX now defined as a system device.
+ Add 'Short Etch' code for Cicada PHY within 440gx_enet.c
+ Patch by Travis B. Sawyer, 12 Jul 2005
+
+======================================================================
Changes for U-Boot 1.1.3:
======================================================================
+* Minor code cleanup
+
+* Add forgotten new fils from latest VoiceBlue update
+
+* Make bootretry feature work with hush shell.
+ Caveat: this currently *requires* CONFIG_RESET_TO_RETRY to be set, too.
+ Patch by Andreas Engel, 19 Jul 2005
+
+* Update Hymod Board Database PHP code in "tools" directory
+ Patch by Murray Jensen, 01 Jul 2005
+
+* Make "tr" command use POSIX compliant; export HOSTOS make variable
+ Patch by Murray Jensen, 30 Jun 2005
+
+* Fix Murray Jensen's mail address.
+ Patch by Murray Jensen, 30 Jun 2005
+
+* Preserve PHY_BMCR during a soft reset.
+ Patch by Carl Riechers, 24 Jun 2005
+
+* VoiceBlue update: eeprom tool can also store firmware version now.
+ eeprom.bin is runable by jumping at load address.
+ Patch by Ladislav Michl, 23 May 2005
+
+* Move the AT91RM9200DK to the ARM Systems list.
+ Patch by Anders Larsen, 26 Apr 2005
+
+* Eliminate calls of ARM libgcc.a helper functions _divsi3 and _modsi3
+ Patch by Anders Larsen, 26 Apr 2005
+
+* measure_gclk() is needed when DEBUG is enabled
+ Patch by Bryan O'Donoghue, 25 Apr 2005
+
+* Add UPD-Checksum code, fix problem in net.c (return instead of break)
+ Patch by Reinhard Arlt, 12 Aug 2005
+
+* esd PCI405 board updated
+ Patch by Matthias Fuchs, 28 Jul 2005
+
+* esd WUH405 and DU405 board updated
+ Patch by Matthias Fuchs, 27 Jul 2005
+
+* Fix problem in cmd_nand.c (only when defined CFG_NAND_SKIP_BAD_DOT_I)
+ Patch by Matthias Fuchs, 4 May 2005
+
* Update AMCC Yosemite to get a consistent setup for all AMCC eval
boards (baudrate, environment...). Flash driver fixed.
Patch by Stefan Roese, 11 Aug 2005
diff --git a/CREDITS b/CREDITS
index 948043e..f717d54 100644
--- a/CREDITS
+++ b/CREDITS
@@ -29,6 +29,7 @@ D: ERIC Support
N: Pantelis Antoniou
E: panto@intracom.gr
D: NETVIA & NETPHONE board support, ARTOS support.
+D: Support for Silicon Turnkey eXpress XTc
N: Pierre Aubert
E: <p.aubert@staubli.com>
@@ -198,10 +199,9 @@ D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB"
W: www.denx.de
N: Murray Jensen
-E: Murray.Jensen@cmst.csiro.au
+E: Murray.Jensen@csiro.au
D: Initial 8260 support; GDB support
D: Port to Cogent+Hymod boards; Hymod Board Database
-W: http://www.msa.cmst.csiro.au/ourstaff/MurrayJensen/mjj.html
N: Yoo. Jonghoon
E: yooth@ipone.co.kr
@@ -269,8 +269,9 @@ E: lo@routefree.com
D: Support for DOS partitions
N: Dan Malek
-E: dan@netx4.com
+E: dan@embeddedalley.com
D: FADSROM, the grandfather of all of this
+D: Support for Silicon Turnkey eXpress XTc
N: Andrea "llandre" Marson
E: andrea.marson@dave-tech.it
diff --git a/MAINTAINERS b/MAINTAINERS
index 2f1d10b..67f8bb4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -42,10 +42,6 @@ Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
sacsng MPC8260
-Rick Bronson <rick@efn.org>
-
- AT91RM9200DK at91rm9200
-
Oliver Brown <obrown@adventnetworks.com>
gw8260 MPC8260
@@ -182,7 +178,7 @@ Klaus Heydeck <heydeck@kieback-peter.de>
KUP4K MPC855
KUP4X MPC859
-Murray Jensen <Murray.Jensen@cmst.csiro.au>
+Murray Jensen <Murray.Jensen@csiro.au>
cogent_mpc8xx MPC8xx
@@ -219,6 +215,7 @@ Jon Loeliger <jdl@freescale.com>
Dan Malek <dan@embeddededge.com>
STxGP3 MPC85xx
+ STxXTc MPC8xx
Eran Man <eran@nbase.co.il>
@@ -281,6 +278,8 @@ Yusdi Santoso <yusdi_santoso@adaptec.com>
Travis Sawyer (travis.sawyer@sandburst.com>
+ KAREF PPC440GX
+ METROBOX PPC440GX
XPEDITE1K PPC440GX
Peter De Schrijver <p2@mind.be>
@@ -352,6 +351,10 @@ Rishi Bhattacharya <rishi@ti.com>
omap5912osk ARM926EJS
+Rick Bronson <rick@efn.org>
+
+ AT91RM9200DK at91rm9200
+
George G. Davis <gdavis@mvista.com>
assabet SA1100
diff --git a/MAKEALL b/MAKEALL
index f8baa8a..6829aa9 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -61,17 +61,17 @@ LIST_8xx=" \
#########################################################################
LIST_4xx=" \
- ADCIOP AR405 ASH405 bubinga \
+ ADCIOP AR405 ASH405 bubinga \
CANBT CPCI405 CPCI4052 CPCI405AB \
CPCI440 CPCIISER4 CRAYL1 csb272 \
csb472 DASA_SIM DP405 DU405 \
ebony ERIC EXBITGEN HUB405 \
- JSE MIP405 MIP405T ML2 \
- ml300 ocotea OCRTC ORSG \
- PCI405 PIP405 PLU405 PMC405 \
- PPChameleonEVB VOH405 W7OLMC W7OLMG \
- walnut WUH405 XPEDITE1K yellowstone \
- yosemite \
+ JSE KAREF METROBOX MIP405 \
+ MIP405T ML2 ml300 ocotea \
+ OCRTC ORSG PCI405 PIP405 \
+ PLU405 PMC405 PPChameleonEVB VOH405 \
+ W7OLMC W7OLMG walnut WUH405 \
+ XPEDITE1K yellowstone yosemite \
"
#########################################################################
@@ -91,7 +91,7 @@ LIST_824x=" \
debris eXalion HIDDEN_DRAGON MOUSSE \
MUSENKI MVBLUE OXC PN62 \
Sandpoint8240 Sandpoint8245 SL8245 utx8245 \
- sbc8240 \
+ sbc8240 \
"
#########################################################################
@@ -165,7 +165,7 @@ LIST_ARM7="B2 ep7312 evb4510 impa7 modnet50"
#########################################################################
LIST_ARM9=" \
- at91rm9200dk cmc_pu2 integratorcp integratorap \
+ at91rm9200dk cmc_pu2 integratorcp integratorap \
lpd7a400 mx1ads mx1fs2 omap1510inn \
omap1610h2 omap1610inn omap730p2 scb9328 \
smdk2400 smdk2410 trab VCMA9 \
@@ -197,7 +197,7 @@ LIST_arm=" \
"
#########################################################################
-## MIPS Systems
+## MIPS Systems (default = big endian)
#########################################################################
LIST_mips4kc="incaip"
@@ -209,6 +209,18 @@ LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el"
LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"
#########################################################################
+## MIPS Systems (little endian)
+#########################################################################
+
+LIST_mips4kc_el=""
+
+LIST_mips5kc_el=""
+
+LIST_au1xx0_el="dbau1550_el"
+
+LIST_mips_el="${LIST_mips4kc_el} ${LIST_mips5kc_el} ${LIST_au1xx0_el}"
+
+#########################################################################
## i386 Systems
#########################################################################
@@ -264,7 +276,7 @@ do
ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
arm|SA|ARM7|ARM9|ARM11|pxa|ixp| \
microblaze| \
- mips| \
+ mips|mips_el| \
nios|nios2| \
x86|I486)
for target in `eval echo '$LIST_'${arg}`
diff --git a/Makefile b/Makefile
index 12c0e84..e6b42ab 100644
--- a/Makefile
+++ b/Makefile
@@ -29,10 +29,10 @@ HOSTARCH := $(shell uname -m | \
-e s/powerpc/ppc/ \
-e s/macppc/ppc/)
-HOSTOS := $(shell uname -s | tr A-Z a-z | \
+HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
sed -e 's/\(cygwin\).*/cygwin/')
-export HOSTARCH
+export HOSTARCH HOSTOS
# Deal with colliding definitions from tcsh etc.
VENDOR=
@@ -647,6 +647,9 @@ SM850_config : unconfig
SPD823TS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx spd8xx
+stxxtc_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc8xx stxxtc
+
svm_sc8xx_config: unconfig
@ >include/config.h
@./mkconfig $(@:_config=) ppc mpc8xx svm_sc8xx
@@ -797,6 +800,12 @@ HUB405_config: unconfig
JSE_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx jse
+KAREF_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx karef sandburst
+
+METROBOX_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx metrobox sandburst
+
MIP405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx mip405 mpl
@@ -1626,7 +1635,7 @@ dbau1550_config : unconfig
dbau1550_el_config : unconfig
@ >include/config.h
@echo "#define CONFIG_DBAU1550 1" >>include/config.h
- @./mkconfig -a dbau1x00 mips mips dbau1x00 "" little
+ @./mkconfig -a dbau1x00 mips mips dbau1x00
#########################################################################
## MIPS64 5Kc
@@ -1740,7 +1749,7 @@ clean:
rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
rm -f tools/env/fw_printenv tools/env/fw_setenv
rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
- rm -f board/trab/trab_fkt
+ rm -f board/trab/trab_fkt board/voiceblue/eeprom
clobber: clean
find . -type f \( -name .depend \
diff --git a/board/at91rm9200dk/flash.c b/board/at91rm9200dk/flash.c
index 5220fcf..f6228ef 100644
--- a/board/at91rm9200dk/flash.c
+++ b/board/at91rm9200dk/flash.c
@@ -259,8 +259,7 @@ void flash_print_info (flash_info_t * info)
break;
default:
printf ("Unknown Chip Type\n");
- goto Done;
- break;
+ return;
}
printf (" Size: %ld MB in %d Sectors\n",
@@ -275,8 +274,6 @@ void flash_print_info (flash_info_t * info)
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
-
-Done: ;
}
/*-----------------------------------------------------------------------
diff --git a/board/cogent/README.cma286 b/board/cogent/README.cma286
index aeebc85..0345fea 100644
--- a/board/cogent/README.cma286
+++ b/board/cogent/README.cma286
@@ -65,5 +65,5 @@ PITRTCLK=65103.515625 (bloody hell!).
If anyone finds anything wrong with the stuff above, I would appreciate
an email about it.
-Murray Jensen <Murray.Jensen@cmst.csiro.au>
+Murray Jensen <Murray.Jensen@csiro.au>
21-Aug-00
diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c
index 2aa2b57..7db2a60 100644
--- a/board/esd/du405/du405.c
+++ b/board/esd/du405/du405.c
@@ -141,6 +141,20 @@ int board_early_init_f (void)
}
+int misc_init_r (void)
+{
+ unsigned long cntrl0Reg;
+
+ /*
+ * Setup UART1 handshaking: use CTS instead of DSR
+ */
+ cntrl0Reg = mfdcr(cntrl0);
+ mtdcr(cntrl0, cntrl0Reg | 0x00001000);
+
+ return (0);
+}
+
+
/*
* Check Board Identity:
*/
diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
index cb458eb..d1b6807 100644
--- a/board/esd/pci405/pci405.c
+++ b/board/esd/pci405/pci405.c
@@ -77,10 +77,10 @@ int board_revision(void)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
- out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
+ out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200);
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200);
udelay(1000); /* wait some time before reading input */
- value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
+ value = in32(GPIO0_IR) & 0x00100200; /* get config bits */
/*
* Restore GPIO settings
@@ -88,18 +88,18 @@ int board_revision(void)
mtdcr(cntrl0, cntrl0Reg);
switch (value) {
- case 0x00180000:
- /* CS2==1 && CS3==1 -> version 1.0 and 1.1 */
+ case 0x00100200:
+ /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
return 1;
- case 0x00080000:
- /* CS2==0 && CS3==1 -> version 1.2 */
+ case 0x00000200:
+ /* CS2==0 && IRQ5==1 -> version 1.2 */
return 2;
+ case 0x00000000:
+ /* CS2==0 && IRQ5==0 -> version 1.3 */
+ return 3;
#if 0 /* not yet manufactured ! */
case 0x00100000:
- /* CS2==1 && CS3==0 -> version 1.3 */
- return 3;
- case 0x00000000:
- /* CS2==0 && CS3==0 -> version 1.4 */
+ /* CS2==1 && IRQ5==0 -> version 1.4 */
return 4;
#endif
default:
@@ -393,3 +393,48 @@ int testdram (void)
}
/* ------------------------------------------------------------------------- */
+int wpeeprom(int wp)
+{
+ int wp_state = wp;
+ volatile unsigned char *uart1_mcr = (volatile unsigned char *)0xef600404;
+
+ if (wp == 1) {
+ *uart1_mcr &= ~0x02;
+ } else if (wp == 0) {
+ *uart1_mcr |= 0x02;
+ } else {
+ if (*uart1_mcr & 0x02) {
+ wp_state = 0;
+ } else {
+ wp_state = 1;
+ }
+ }
+ return wp_state;
+}
+
+int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int wp = -1;
+ if (argc >= 2) {
+ if (argv[1][0] == '1') {
+ wp = 1;
+ } else if (argv[1][0] == '0') {
+ wp = 0;
+ }
+ }
+
+ wp = wpeeprom(wp);
+ printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
+ return 0;
+}
+
+U_BOOT_CMD(
+ wpeeprom, 2, 1, do_wpeeprom,
+ "wpeeprom - Check/Enable/Disable I2C EEPROM write protection\n",
+ "wpeeprom\n"
+ " - check I2C EEPROM write protection state\n"
+ "wpeeprom 1\n"
+ " - enable I2C EEPROM write protection\n"
+ "wpeeprom 0\n"
+ " - disable I2C EEPROM write protection\n"
+ );
diff --git a/board/esd/wuh405/fpgadata.c b/board/esd/wuh405/fpgadata.c
index 71fde48..fdc02e3 100644
--- a/board/esd/wuh405/fpgadata.c
+++ b/board/esd/wuh405/fpgadata.c
@@ -1,1725 +1,1818 @@
- 0x1f,0x8b,0x08,0x08,0x72,0xdc,0x88,0x41,0x00,0x03,0x77,0x75,0x68,0x34,0x30,0x35,
- 0x5f,0x31,0x5f,0x30,0x30,0x2e,0x62,0x69,0x74,0x00,0xec,0xbd,0x7b,0x78,0x14,0xd7,
- 0x95,0x2f,0xba,0x7a,0x57,0x21,0x4a,0xdd,0x2d,0x75,0x59,0x40,0x46,0x31,0x36,0x94,
- 0x5a,0x82,0x34,0x72,0xab,0x69,0x1a,0x22,0xcb,0xb2,0xdc,0x2a,0x04,0x93,0x28,0x40,
- 0x82,0xc6,0xc9,0x9c,0xcf,0x33,0xc9,0x75,0xda,0x0e,0xc9,0x61,0x7c,0x70,0x8e,0xe2,
- 0xc9,0xbd,0x87,0x38,0x1e,0xa7,0xf4,0x30,0x88,0xc7,0x98,0x36,0x78,0x12,0x9c,0xf8,
- 0x66,0x8a,0x47,0x62,0xec,0x90,0x9c,0x06,0xd9,0x46,0x18,0xc6,0x2e,0xb0,0xe2,0x88,
- 0x87,0x41,0x71,0x3c,0x19,0x6c,0x13,0xd2,0x38,0xb2,0x2d,0x63,0x19,0xcb,0x98,0x38,
- 0x92,0x85,0xd1,0x5d,0x7b,0xd7,0xa3,0xab,0xaa,0xab,0x05,0x99,0xf9,0xee,0xfd,0xe6,
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+ 0xe6,0xb3,0x66,0x0d,0x39,0x37,0x41,0x14,0x31,0xc4,0xac,0xd7,0x0b,0x25,0x88,0x78,
+ 0x5e,0xf0,0x21,0x87,0x2a,0x43,0x1a,0xa4,0xb1,0x32,0x43,0x50,0xa4,0x2a,0x28,0x86,
+ 0x26,0xea,0xcd,0xf2,0xaf,0x91,0x49,0x46,0x1f,0x9c,0x7d,0xc5,0x6d,0x49,0xb4,0xb1,
+ 0xf5,0x07,0x9d,0x87,0x53,0x2d,0xf1,0x49,0x34,0x03,0x87,0x8d,0xd7,0xea,0x46,0xc9,
+ 0x3f,0x78,0xbd,0x3d,0x17,0x33,0x4b,0xc8,0x87,0xef,0xfe,0xbe,0x47,0xec,0xfe,0x7b,
+ 0xbc,0x74,0x2d,0x31,0x23,0x79,0xa0,0xbd,0x01,0x06,0x4a,0xfe,0x01,0xf8,0xda,0x5b,
+ 0x23,0x0f,0xdf,0xbd,0xbd,0xfc,0x9d,0x1b,0x2f,0xbe,0x35,0x26,0xf8,0xf0,0xfd,0x3a,
+ 0x1f,0x2e,0x47,0x7c,0xb8,0xeb,0x19,0xf7,0x50,0xc4,0x87,0xc7,0x05,0x1f,0xee,0xd4,
+ 0xf9,0xf0,0x69,0xc4,0x87,0xbb,0x78,0xec,0xf3,0xea,0xab,0x02,0x0b,0xff,0x5a,0xd9,
+ 0xd9,0x1e,0xda,0xaa,0x83,0x22,0x12,0xe3,0x73,0xf8,0x50,0xfe,0xf4,0xbf,0x6f,0x62,
+ 0xff,0x4f,0x1b,0xa0,0x78,0xf9,0x79,0x7c,0x38,0xd8,0xe0,0xc3,0xee,0x03,0xe3,0x1b,
+ 0xf3,0xfd,0x9b,0x4f,0x1e,0x0f,0x5d,0x7a,0xa6,0xff,0xe3,0x2f,0x1e,0xbd,0x0f,0x1e,
+ 0x11,0x2f,0x28,0x7c,0xc8,0xa6,0xbe,0xf8,0x59,0xb4,0xb4,0xb4,0xb4,0xb4,0xb4,0xb4,
+ 0xb4,0xb4,0xb4,0xb4,0xfe,0xdf,0x25,0x6b,0x07,0xaa,0x6b,0x07,0x2d,0x2d,0x2d,0x2d,
+ 0x2d,0x2d,0x2d,0x2d,0x2d,0x2d,0xad,0xe7,0x4b,0xd6,0x0e,0x09,0x5d,0x3b,0x68,0x69,
+ 0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x3d,0x5f,0xb2,0x76,0x30,0x65,0xed,
+ 0xf0,0xbf,0x0e,0x45,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0xeb,0xbf,
+ 0x28,0x5f,0xfc,0xd1,0x24,0xf8,0xe7,0x79,0x1f,0xb8,0xf8,0xce,0x53,0xdc,0x07,0xf6,
+ 0xb9,0xdf,0x27,0xd4,0x3f,0x6b,0xf8,0x50,0x25,0xd1,0x39,0x1f,0x9f,0x7e,0xb6,0xdf,
+ 0xbf,0x00,0x34,0x34,0xbf,0x69,0xee,0x33,0x01,0x00,
diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c
index 8980209..fca11d0 100644
--- a/board/hmi1001/hmi1001.c
+++ b/board/hmi1001/hmi1001.c
@@ -170,3 +170,13 @@ int board_early_init_r (void)
*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
return 0;
}
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
diff --git a/board/pm854/flash.c b/board/pm854/flash.c
deleted file mode 100644
index d714589..0000000
--- a/board/pm854/flash.c
+++ /dev/null
@@ -1,541 +0,0 @@
-/*
- * (C) Copyright 2003 Motorola Inc.
- * Xianghua Xiao,(X.Xiao@motorola.com)
- *
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Add support the Sharp chips on the mpc8260ads.
- * I started with board/ip860/flash.c and made changes I found in
- * the MTD project by David Schleef.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if !defined(CFG_NO_FLASH)
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CFG_ENV_IS_IN_FLASH)
-# ifndef CFG_ENV_ADDR
-# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
-# endif
-# ifndef CFG_ENV_SIZE
-# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
-# endif
-# ifndef CFG_ENV_SECT_SIZE
-# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
-# endif
-#endif
-
-#undef DEBUG
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static int clear_block_lock_bit(vu_long * addr);
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size;
- int i;
-
- /* Init: enable write,
- * or we cannot even write flash commands
- */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- /* set the default sector offset */
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
- }
-
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size;
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-
-#ifdef CFG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
-#endif
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- case FLASH_MAN_SHARP: printf ("Sharp "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
- break;
- case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
- break;
- case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
- break;
- case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
- break;
- case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
- break;
- case FLASH_28F128J3A: printf ("28F128J3A (128 Mbit, 128 x 128K)\n");
- break;
-
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
- ulong sector_offset;
-
-#ifdef DEBUG
- printf("Check flash at 0x%08x\n",(uint)addr);
-#endif
- /* Write "Intelligent Identifier" command: read Manufacturer ID */
- *addr = 0x90909090;
- udelay(20);
- asm("sync");
-
- value = addr[0] & 0x00FF00FF;
-
-#ifdef DEBUG
- printf("manufacturer=0x%x\n",(uint)value);
-#endif
- switch (value) {
- case MT_MANUFACT: /* SHARP, MT or => Intel */
- case INTEL_ALT_MANU:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- printf("unknown manufacturer: %x\n", (unsigned int)value);
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1] & 0x00FF00FF; /* device ID */
-
-#ifdef DEBUG
- printf("deviceID=0x%x\n",(uint)value);
-#endif
- switch (value) {
- case (INTEL_ID_28F016S):
- info->flash_id += FLASH_28F016SV;
- info->sector_count = 32;
- info->size = 0x00400000;
- sector_offset = 0x20000;
- break; /* => 2x2 MB */
-
- case (INTEL_ID_28F160S3):
- info->flash_id += FLASH_28F160S3;
- info->sector_count = 32;
- info->size = 0x00400000;
- sector_offset = 0x20000;
- break; /* => 2x2 MB */
-
- case (INTEL_ID_28F320S3):
- info->flash_id += FLASH_28F320S3;
- info->sector_count = 64;
- info->size = 0x00800000;
- sector_offset = 0x20000;
- break; /* => 2x4 MB */
-
- case (INTEL_ID_28F640J3A):
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x01000000;
- sector_offset = 0x40000;
- break; /* => 2x8 MB */
-
- case (INTEL_ID_28F128J3A):
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x02000000;
- sector_offset = 0x40000;
- break; /* => 2x16 MB */
-
-
- case SHARP_ID_28F016SCL:
- case SHARP_ID_28F016SCZ:
- info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
- info->sector_count = 32;
- info->size = 0x00800000;
- sector_offset = 0x40000;
- break; /* => 4x2 MB */
-
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- base += sector_offset;
- /* don't know how to check sector protection */
- info->protect[i] = 0;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (vu_long *)info->start[0];
- *addr = 0xFFFFFF; /* reset bank to read array mode */
- asm("sync");
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
- && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
-#ifdef DEBUG
- printf("\nFlash Erase:\n");
-#endif
- /* Make Sure Block Lock Bit is not set. */
- if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
- return 1;
- }
-
- /* Start erase on unprotected sectors */
-#if defined(DEBUG)
- printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
-#endif
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *)(info->start[sect]);
- asm("sync");
-
- last = start = get_timer (0);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Reset Array */
- *addr = 0xffffffff;
- asm("sync");
- /* Clear Status Register */
- *addr = 0x50505050;
- asm("sync");
- /* Single Block Erase Command */
- *addr = 0x20202020;
- asm("sync");
- /* Confirm */
- *addr = 0xD0D0D0D0;
- asm("sync");
-
- if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
- /* Resume Command, as per errata update */
- *addr = 0xD0D0D0D0;
- asm("sync");
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
- while ((*addr & 0x00800080) != 0x00800080) {
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0xFFFFFFFF; /* reset bank */
- asm("sync");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- /* reset to read mode */
- *addr = 0xFFFFFFFF;
- asm("sync");
- }
- }
-
- printf ("flash erase done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *)dest;
- ulong start, csr;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Write Command */
- *addr = 0x10101010;
- asm("sync");
-
- /* Write Data */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- flag = 0;
-
- while (((csr = *addr) & 0x00800080) != 0x00800080) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- flag = 1;
- break;
- }
- }
- if (csr & 0x40404040) {
- printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
- flag = 1;
- }
-
- /* Clear Status Registers Command */
- *addr = 0x50505050;
- asm("sync");
- /* Reset to read array mode */
- *addr = 0xFFFFFFFF;
- asm("sync");
-
- return (flag);
-}
-
-/*-----------------------------------------------------------------------
- * Clear Block Lock Bit, returns:
- * 0 - OK
- * 1 - Timeout
- */
-
-static int clear_block_lock_bit(vu_long * addr)
-{
- ulong start, now;
-
- /* Reset Array */
- *addr = 0xffffffff;
- asm("sync");
- /* Clear Status Register */
- *addr = 0x50505050;
- asm("sync");
-
- *addr = 0x60606060;
- asm("sync");
- *addr = 0xd0d0d0d0;
- asm("sync");
-
- start = get_timer (0);
- while((*addr & 0x00800080) != 0x00800080){
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout on clearing Block Lock Bit\n");
- *addr = 0xFFFFFFFF; /* reset bank */
- asm("sync");
- return 1;
- }
- }
- return 0;
-}
-
-#endif /* !CFG_NO_FLASH */
diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c
new file mode 100644
index 0000000..762fb73
--- /dev/null
+++ b/board/sandburst/common/flash.c
@@ -0,0 +1,512 @@
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * Ported from Ebony flash support
+ * Travis B. Sawyer
+ * Sandburst Corporation
+ */
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+ {0xfff80000} /* Boot Flash */
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+
+#define ADDR0 0x5555
+#define ADDR1 0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned short index = 0;
+ int i;
+
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size(
+ (vu_long *)flash_addr_table[index][i], &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i]<<20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count-1))
+ size = info->start[i+1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k=0; k<size; k++)
+ {
+ if (*flash++ != 0xffffffff)
+ {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ",
+ info->protect[i] ? "RO " : " "
+ );
+ }
+ printf ("\n");
+ return;
+ }
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ FLASH_WORD_SIZE value;
+ ulong base = (ulong)addr;
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
+
+ /* Write auto select command: read Manufacturer ID */
+ udelay(10000);
+ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ udelay(1000);
+ addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ udelay(1000);
+ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (FLASH_WORD_SIZE)AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (FLASH_WORD_SIZE)AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x00080000; /* => 512 kb */
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ if (info->flash_id == FLASH_AM040) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* reset to return to reading data */
+ addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr2 = (FLASH_WORD_SIZE *)info->start[0];
+ *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+int wait_for_DQ7(flash_info_t *info, int sect)
+{
+ ulong start, now, last;
+ volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+ start = get_timer (0);
+ last = start;
+ while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+ volatile FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+ DEBUGF("Erasing sector %p\n", addr2);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
+ for (i=0; i<50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /* reset to read mode */
+ addr = (FLASH_WORD_SIZE *)info->start[0];
+ addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
+ volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+ volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((volatile FLASH_WORD_SIZE *) dest) &
+ (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c
new file mode 100644
index 0000000..858b38c
--- /dev/null
+++ b/board/sandburst/common/ppc440gx_i2c.c
@@ -0,0 +1,512 @@
+/*
+ * Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by
+ * Travis B. Sawyer
+ * Sandburst Corporation.
+ */
+#include <common.h>
+#include <ppc4xx.h>
+#if defined(CONFIG_440)
+# include <440_i2c.h>
+#else
+# include <405gp_i2c.h>
+#endif
+#include <i2c.h>
+#include <440_i2c.h>
+#include <command.h>
+#include "ppc440gx_i2c.h"
+
+#ifdef CONFIG_I2C_BUS1
+
+#define IIC_OK 0
+#define IIC_NOK 1
+#define IIC_NOK_LA 2 /* Lost arbitration */
+#define IIC_NOK_ICT 3 /* Incomplete transfer */
+#define IIC_NOK_XFRA 4 /* Transfer aborted */
+#define IIC_NOK_DATA 5 /* No data in buffer */
+#define IIC_NOK_TOUT 6 /* Transfer timeout */
+
+#define IIC_TIMEOUT 1 /* 1 second */
+#if defined(CFG_I2C_NOPROBES)
+static uchar i2c_no_probes[] = CFG_I2C_NOPROBES;
+#endif
+
+static void _i2c_bus1_reset (void)
+{
+ int i, status;
+
+ /* Reset status register */
+ /* write 1 in SCMP and IRQA to clear these fields */
+ out8 (IIC_STS1, 0x0A);
+
+ /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
+ out8 (IIC_EXTSTS1, 0x8F);
+ __asm__ volatile ("eieio");
+
+ /*
+ * Get current state, reset bus
+ * only if no transfers are pending.
+ */
+ i = 10;
+ do {
+ /* Get status */
+ status = in8 (IIC_STS1);
+ udelay (500); /* 500us */
+ i--;
+ } while ((status & IIC_STS_PT) && (i > 0));
+ /* Soft reset controller */
+ status = in8 (IIC_XTCNTLSS1);
+ out8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST));
+ __asm__ volatile ("eieio");
+
+ /* make sure where in initial state, data hi, clock hi */
+ out8 (IIC_DIRECTCNTL1, 0xC);
+ for (i = 0; i < 10; i++) {
+ if ((in8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
+ /* clock until we get to known state */
+ out8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */
+ udelay (100); /* 100us */
+ out8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */
+ udelay (100); /* 100us */
+ } else {
+ break;
+ }
+ }
+ /* send start condition */
+ out8 (IIC_DIRECTCNTL1, 0x4);
+ udelay (1000); /* 1ms */
+ /* send stop condition */
+ out8 (IIC_DIRECTCNTL1, 0xC);
+ udelay (1000); /* 1ms */
+ /* Unreset controller */
+ out8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
+ udelay (1000); /* 1ms */
+}
+
+void i2c1_init (int speed, int slaveadd)
+{
+ sys_info_t sysInfo;
+ unsigned long freqOPB;
+ int val, divisor;
+
+#ifdef CFG_I2C_INIT_BOARD
+ /* call board specific i2c bus reset routine before accessing the */
+ /* environment, which might be in a chip on that bus. For details */
+ /* about this problem see doc/I2C_Edge_Conditions. */
+ i2c_init_board();
+#endif
+
+ /* Handle possible failed I2C state */
+ /* FIXME: put this into i2c_init_board()? */
+ _i2c_bus1_reset ();
+
+ /* clear lo master address */
+ out8 (IIC_LMADR1, 0);
+
+ /* clear hi master address */
+ out8 (IIC_HMADR1, 0);
+
+ /* clear lo slave address */
+ out8 (IIC_LSADR1, 0);
+
+ /* clear hi slave address */
+ out8 (IIC_HSADR1, 0);
+
+ /* Clock divide Register */
+ /* get OPB frequency */
+ get_sys_info (&sysInfo);
+ freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
+ /* set divisor according to freqOPB */
+ divisor = (freqOPB - 1) / 10000000;
+ if (divisor == 0)
+ divisor = 1;
+ out8 (IIC_CLKDIV1, divisor);
+
+ /* no interrupts */
+ out8 (IIC_INTRMSK1, 0);
+
+ /* clear transfer count */
+ out8 (IIC_XFRCNT1, 0);
+
+ /* clear extended control & stat */
+ /* write 1 in SRC SRS SWC SWS to clear these fields */
+ out8 (IIC_XTCNTLSS1, 0xF0);
+
+ /* Mode Control Register
+ Flush Slave/Master data buffer */
+ out8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
+ __asm__ volatile ("eieio");
+
+
+ val = in8(IIC_MDCNTL1);
+ __asm__ volatile ("eieio");
+
+ /* Ignore General Call, slave transfers are ignored,
+ disable interrupts, exit unknown bus state, enable hold
+ SCL
+ 100kHz normaly or FastMode for 400kHz and above
+ */
+
+ val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
+ if( speed >= 400000 ){
+ val |= IIC_MDCNTL_FSM;
+ }
+ out8 (IIC_MDCNTL1, val);
+
+ /* clear control reg */
+ out8 (IIC_CNTL1, 0x00);
+ __asm__ volatile ("eieio");
+
+}
+
+/*
+ This code tries to use the features of the 405GP i2c
+ controller. It will transfer up to 4 bytes in one pass
+ on the loop. It only does out8(lbz) to the buffer when it
+ is possible to do out16(lhz) transfers.
+
+ cmd_type is 0 for write 1 for read.
+
+ addr_len can take any value from 0-255, it is only limited
+ by the char, we could make it larger if needed. If it is
+ 0 we skip the address write cycle.
+
+ Typical case is a Write of an addr followd by a Read. The
+ IBM FAQ does not cover this. On the last byte of the write
+ we don't set the creg CHT bit, and on the first bytes of the
+ read we set the RPST bit.
+
+ It does not support address only transfers, there must be
+ a data part. If you want to write the address yourself, put
+ it in the data pointer.
+
+ It does not support transfer to/from address 0.
+
+ It does not check XFRCNT.
+*/
+static
+int i2c_transfer1(unsigned char cmd_type,
+ unsigned char chip,
+ unsigned char addr[],
+ unsigned char addr_len,
+ unsigned char data[],
+ unsigned short data_len )
+{
+ unsigned char* ptr;
+ int reading;
+ int tran,cnt;
+ int result;
+ int status;
+ int i;
+ uchar creg;
+
+ if( data == 0 || data_len == 0 ){
+ /*Don't support data transfer of no length or to address 0*/
+ printf( "i2c_transfer: bad call\n" );
+ return IIC_NOK;
+ }
+ if( addr && addr_len ){
+ ptr = addr;
+ cnt = addr_len;
+ reading = 0;
+ }else{
+ ptr = data;
+ cnt = data_len;
+ reading = cmd_type;
+ }
+
+ /*Clear Stop Complete Bit*/
+ out8(IIC_STS1,IIC_STS_SCMP);
+ /* Check init */
+ i=10;
+ do {
+ /* Get status */
+ status = in8(IIC_STS1);
+ __asm__ volatile("eieio");
+ i--;
+ } while ((status & IIC_STS_PT) && (i>0));
+
+ if (status & IIC_STS_PT) {
+ result = IIC_NOK_TOUT;
+ return(result);
+ }
+ /*flush the Master/Slave Databuffers*/
+ out8(IIC_MDCNTL1, ((in8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
+ /*need to wait 4 OPB clocks? code below should take that long*/
+
+ /* 7-bit adressing */
+ out8(IIC_HMADR1,0);
+ out8(IIC_LMADR1, chip);
+ __asm__ volatile("eieio");
+
+ tran = 0;
+ result = IIC_OK;
+ creg = 0;
+
+ while ( tran != cnt && (result == IIC_OK)) {
+ int bc,j;
+
+ /* Control register =
+ Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
+ Transfer is a sequence of transfers
+ */
+ creg |= IIC_CNTL_PT;
+
+ bc = (cnt - tran) > 4 ? 4 :
+ cnt - tran;
+ creg |= (bc-1)<<4;
+ /* if the real cmd type is write continue trans*/
+ if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
+ creg |= IIC_CNTL_CHT;
+
+ if (reading)
+ creg |= IIC_CNTL_READ;
+ else {
+ for(j=0; j<bc; j++) {
+ /* Set buffer */
+ out8(IIC_MDBUF1,ptr[tran+j]);
+ __asm__ volatile("eieio");
+ }
+ }
+ out8(IIC_CNTL1, creg );
+ __asm__ volatile("eieio");
+
+ /* Transfer is in progress
+ we have to wait for upto 5 bytes of data
+ 1 byte chip address+r/w bit then bc bytes
+ of data.
+ udelay(10) is 1 bit time at 100khz
+ Doubled for slop. 20 is too small.
+ */
+ i=2*5*8;
+ do {
+ /* Get status */
+ status = in8(IIC_STS1);
+ __asm__ volatile("eieio");
+ udelay (10);
+ i--;
+ } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
+ && (i>0));
+
+ if (status & IIC_STS_ERR) {
+ result = IIC_NOK;
+ status = in8 (IIC_EXTSTS1);
+ /* Lost arbitration? */
+ if (status & IIC_EXTSTS_LA)
+ result = IIC_NOK_LA;
+ /* Incomplete transfer? */
+ if (status & IIC_EXTSTS_ICT)
+ result = IIC_NOK_ICT;
+ /* Transfer aborted? */
+ if (status & IIC_EXTSTS_XFRA)
+ result = IIC_NOK_XFRA;
+ } else if ( status & IIC_STS_PT) {
+ result = IIC_NOK_TOUT;
+ }
+ /* Command is reading => get buffer */
+ if ((reading) && (result == IIC_OK)) {
+ /* Are there data in buffer */
+ if (status & IIC_STS_MDBS) {
+ /*
+ even if we have data we have to wait 4OPB clocks
+ for it to hit the front of the FIFO, after that
+ we can just read. We should check XFCNT here and
+ if the FIFO is full there is no need to wait.
+ */
+ udelay (1);
+ for(j=0;j<bc;j++) {
+ ptr[tran+j] = in8(IIC_MDBUF1);
+ __asm__ volatile("eieio");
+ }
+ } else
+ result = IIC_NOK_DATA;
+ }
+ creg = 0;
+ tran+=bc;
+ if( ptr == addr && tran == cnt ) {
+ ptr = data;
+ cnt = data_len;
+ tran = 0;
+ reading = cmd_type;
+ if( reading )
+ creg = IIC_CNTL_RPST;
+ }
+ }
+ return (result);
+}
+
+int i2c_probe1 (uchar chip)
+{
+ uchar buf[1];
+
+ buf[0] = 0;
+
+ /*
+ * What is needed is to send the chip address and verify that the
+ * address was <ACK>ed (i.e. there was a chip at that address which
+ * drove the data line low).
+ */
+ return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0);
+}
+
+
+int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+ uchar xaddr[4];
+ int ret;
+
+ if ( alen > 4 ) {
+ printf ("I2C read: addr len %d not supported\n", alen);
+ return 1;
+ }
+
+ if ( alen > 0 ) {
+ xaddr[0] = (addr >> 24) & 0xFF;
+ xaddr[1] = (addr >> 16) & 0xFF;
+ xaddr[2] = (addr >> 8) & 0xFF;
+ xaddr[3] = addr & 0xFF;
+ }
+
+
+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+ /*
+ * EEPROM chips that implement "address overflow" are ones
+ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+ * address and the extra bits end up in the "chip address"
+ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+ * four 256 byte chips.
+ *
+ * Note that we consider the length of the address field to
+ * still be one byte because the extra address bits are
+ * hidden in the chip address.
+ */
+ if( alen > 0 )
+ chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+#endif
+ if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
+ printf( "I2c read: failed %d\n", ret);
+ return 1;
+ }
+ return 0;
+}
+
+int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+ uchar xaddr[4];
+
+ if ( alen > 4 ) {
+ printf ("I2C write: addr len %d not supported\n", alen);
+ return 1;
+
+ }
+ if ( alen > 0 ) {
+ xaddr[0] = (addr >> 24) & 0xFF;
+ xaddr[1] = (addr >> 16) & 0xFF;
+ xaddr[2] = (addr >> 8) & 0xFF;
+ xaddr[3] = addr & 0xFF;
+ }
+
+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+ /*
+ * EEPROM chips that implement "address overflow" are ones
+ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+ * address and the extra bits end up in the "chip address"
+ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+ * four 256 byte chips.
+ *
+ * Note that we consider the length of the address field to
+ * still be one byte because the extra address bits are
+ * hidden in the chip address.
+ */
+ if( alen > 0 )
+ chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+#endif
+
+ return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
+}
+
+/*-----------------------------------------------------------------------
+ * Read a register
+ */
+uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
+{
+ char buf;
+
+ i2c_read1(i2c_addr, reg, 1, &buf, 1);
+
+ return(buf);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a register
+ */
+void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val)
+{
+ i2c_write1(i2c_addr, reg, 1, &val, 1);
+}
+
+
+int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int j;
+#if defined(CFG_I2C_NOPROBES)
+ int k, skip;
+#endif
+
+ puts ("Valid chip addresses:");
+ for(j = 0; j < 128; j++) {
+#if defined(CFG_I2C_NOPROBES)
+ skip = 0;
+ for (k = 0; k < sizeof(i2c_no_probes); k++){
+ if (j == i2c_no_probes[k]){
+ skip = 1;
+ break;
+ }
+ }
+ if (skip)
+ continue;
+#endif
+ if(i2c_probe1(j) == 0) {
+ printf(" %02X", j);
+ }
+ }
+ putc ('\n');
+
+#if defined(CFG_I2C_NOPROBES)
+ puts ("Excluded chip addresses:");
+ for( k = 0; k < sizeof(i2c_no_probes); k++ )
+ printf(" %02X", i2c_no_probes[k] );
+ putc ('\n');
+#endif
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ iprobe1, 1, 1, do_i2c1_probe,
+ "iprobe1 - probe to discover valid I2C chip addresses\n",
+ "\n -discover valid I2C chip addresses\n"
+);
+
+#endif /* CONFIG_I2C_BUS1 */
diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h
new file mode 100644
index 0000000..cd4fc86
--- /dev/null
+++ b/board/sandburst/common/ppc440gx_i2c.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Ported from i2c driver for ppc4xx by AS HARNOIS by
+ * Travis B. Sawyer
+ * Sandburst Corporation
+ */
+#include <common.h>
+#include <ppc4xx.h>
+#if defined(CONFIG_440)
+# include <440_i2c.h>
+#else
+# include <405gp_i2c.h>
+#endif
+#include <i2c.h>
+
+#ifdef CONFIG_HARD_I2C
+
+#define I2C_BUS1_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000500)
+#define I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR
+#define IIC_MDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDBUF)
+#define IIC_SDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSDBUF)
+#define IIC_LMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLMADR)
+#define IIC_HMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHMADR)
+#define IIC_CNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCNTL)
+#define IIC_MDCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDCNTL)
+#define IIC_STS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSTS)
+#define IIC_EXTSTS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS)
+#define IIC_LSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR)
+#define IIC_HSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR)
+#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCLKDIV)
+#define IIC_INTRMSK1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK)
+#define IIC_XFRCNT1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT)
+#define IIC_XTCNTLSS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS)
+#define IIC_DIRECTCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICDIRECTCNTL)
+
+void i2c1_init (int speed, int slaveadd);
+int i2c_probe1 (uchar chip);
+int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len);
+int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len);
+uchar i2c_reg_read1(uchar i2c_addr, uchar reg);
+void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val);
+
+#endif /* CONFIG_HARD_I2C */
diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c
new file mode 100644
index 0000000..3530416
--- /dev/null
+++ b/board/sandburst/common/sb_common.c
@@ -0,0 +1,451 @@
+/*
+ * Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "ppc440gx_i2c.h"
+#include "sb_common.h"
+
+long int fixed_sdram (void);
+
+/*************************************************************************
+ * metrobox_get_master
+ *
+ * PRI_N - active low signal. If the GPIO pin is low we are the master
+ *
+ ************************************************************************/
+int sbcommon_get_master(void)
+{
+ ppc440_gpio_regs_t *gpio_regs;
+
+ gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+
+ if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) {
+ return 0;
+ }
+ else {
+ return 1;
+ }
+}
+
+/*************************************************************************
+ * metrobox_secondary_present
+ *
+ * Figure out if secondary/slave board is present
+ *
+ ************************************************************************/
+int sbcommon_secondary_present(void)
+{
+ ppc440_gpio_regs_t *gpio_regs;
+
+ gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+
+ if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES)
+ return 0;
+ else
+ return 1;
+}
+
+/*************************************************************************
+ * sbcommon_get_serial_number
+ *
+ * Retrieve the board serial number via the mac address in eeprom
+ *
+ ************************************************************************/
+unsigned short sbcommon_get_serial_number(void)
+{
+ unsigned char buff[0x100];
+ unsigned short sernum;
+
+ /* Get the board serial number from eeprom */
+ /* Initialize I2C */
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+ /* Read 256 bytes in EEPROM */
+ i2c_read (0x50, 0, 1, buff, 0x100);
+
+ memcpy(&sernum, &buff[0xF4], 2);
+ sernum /= 32;
+
+ return (sernum);
+}
+
+/*************************************************************************
+ * sbcommon_fans
+ *
+ * Spin up fans 2 & 3 to get some air moving. OS will take care
+ * of the rest. This is mostly a precaution...
+ *
+ * Assumes i2c bus 1 is ready.
+ *
+ ************************************************************************/
+void sbcommon_fans(void)
+{
+ /*
+ * Attempt to turn on 2 of the fans...
+ * Need to go through the bridge
+ */
+ puts ("FANS: ");
+
+ /* select fan4 through the bridge */
+ i2c_reg_write1(0x73, /* addr */
+ 0x00, /* reg */
+ 0x08); /* val = bus 4 */
+
+ /* Turn on FAN 4 */
+ i2c_reg_write1(0x2e,
+ 1,
+ 0x80);
+
+ i2c_reg_write1(0x2e,
+ 0,
+ 0x19);
+
+ /* Deselect bus 4 on the bridge */
+ i2c_reg_write1(0x73,
+ 0x00,
+ 0x00);
+
+ /* select fan3 through the bridge */
+ i2c_reg_write1(0x73, /* addr */
+ 0x00, /* reg */
+ 0x04); /* val = bus 3 */
+
+ /* Turn on FAN 3 */
+ i2c_reg_write1(0x2e,
+ 1,
+ 0x80);
+
+ i2c_reg_write1(0x2e,
+ 0,
+ 0x19);
+
+ /* Deselect bus 3 on the bridge */
+ i2c_reg_write1(0x73,
+ 0x00,
+ 0x00);
+
+ /* select fan2 through the bridge */
+ i2c_reg_write1(0x73, /* addr */
+ 0x00, /* reg */
+ 0x02); /* val = bus 4 */
+
+ /* Turn on FAN 2 */
+ i2c_reg_write1(0x2e,
+ 1,
+ 0x80);
+
+ i2c_reg_write1(0x2e,
+ 0,
+ 0x19);
+
+ /* Deselect bus 2 on the bridge */
+ i2c_reg_write1(0x73,
+ 0x00,
+ 0x00);
+
+ /* select fan1 through the bridge */
+ i2c_reg_write1(0x73, /* addr */
+ 0x00, /* reg */
+ 0x01); /* val = bus 0 */
+
+ /* Turn on FAN 1 */
+ i2c_reg_write1(0x2e,
+ 1,
+ 0x80);
+
+ i2c_reg_write1(0x2e,
+ 0,
+ 0x19);
+
+ /* Deselect bus 1 on the bridge */
+ i2c_reg_write1(0x73,
+ 0x00,
+ 0x00);
+
+ puts ("on\n");
+
+ return;
+
+}
+
+/*************************************************************************
+ * initdram
+ *
+ * Initialize sdram
+ *
+ ************************************************************************/
+long int initdram (int board_type)
+{
+ long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram (0);
+#else
+ dram_size = fixed_sdram ();
+#endif
+ return dram_size;
+}
+
+
+/*************************************************************************
+ * testdram
+ *
+ *
+ ************************************************************************/
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("Testing SDRAM: ");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("OK\n");
+ return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ *
+ * Assumes: 128 MB, non-ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup some default
+ *------------------------------------------------------------------*/
+ mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
+ mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+
+ /*--------------------------------------------------------------------
+ * Setup for board-specific specific mem
+ *------------------------------------------------------------------*/
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+ /* RA=10 RD=3 */
+ mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
+ mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
+ mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
+ udelay (400); /* Delay 200 usecs (min) */
+
+ /*--------------------------------------------------------------------
+ * Enable the controller, then wait for DCEN to complete
+ *------------------------------------------------------------------*/
+ mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ for (;;) {
+ mfsdram (mem_mcsts, reg);
+ if (reg & 0x80000000)
+ break;
+ }
+
+ return (128 * 1024 * 1024); /* 128 MB */
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+ unsigned long strap;
+
+ /*--------------------------------------------------------------------------+
+ * The metrobox is always configured as the host & requires the
+ * PCI arbiter to be enabled.
+ *--------------------------------------------------------------------------*/
+ mfsdr(sdr_sdstp1, strap);
+ if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
+ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+ return 0;
+ }
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /*--------------------------------------------------------------------------+
+ * Disable everything
+ *--------------------------------------------------------------------------*/
+ out32r( PCIX0_PIM0SA, 0 ); /* disable */
+ out32r( PCIX0_PIM1SA, 0 ); /* disable */
+ out32r( PCIX0_PIM2SA, 0 ); /* disable */
+ out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+ /*--------------------------------------------------------------------------+
+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+ * options to not support sizes such as 128/256 MB.
+ *--------------------------------------------------------------------------*/
+ out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+ out32r( PCIX0_PIM0LAH, 0 );
+ out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+ out32r( PCIX0_BAR0, 0 );
+
+ /*--------------------------------------------------------------------------+
+ * Program the board's subsystem id/vendor id
+ *--------------------------------------------------------------------------*/
+ out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+ out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+ out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+
+/*************************************************************************
+ * is_pci_host
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ /* The metrobox is always configured as host. */
+ return(1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ * board_get_enetaddr
+ *
+ * Get the ethernet MAC address for the management ethernet from the
+ * strap EEPROM. Note that is the BASE address for the range of
+ * external ethernet MACs on the board. The base + 31 is the actual
+ * mgmt mac address.
+ *
+ ************************************************************************/
+static int macaddr_idx = 0;
+
+void board_get_enetaddr (uchar * enet)
+{
+ int i;
+ unsigned short tmp;
+ unsigned char buff[0x100], *cp;
+
+ if (0 == macaddr_idx) {
+
+ /* Initialize I2C */
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+ /* Read 256 bytes in EEPROM */
+ i2c_read (0x50, 0, 1, buff, 0x100);
+
+ cp = &buff[0xF0];
+
+ for (i = 0; i < 6; i++,cp++)
+ enet[i] = *cp;
+
+ memcpy(&tmp, &enet[4], 2);
+ tmp += 31;
+ memcpy(&enet[4], &tmp, 2);
+
+ macaddr_idx++;
+ } else {
+ enet[0] = 0x02;
+ enet[1] = 0x00;
+ enet[2] = 0x00;
+ enet[3] = 0x00;
+ enet[4] = 0x00;
+ if (1 == sbcommon_get_master() ) {
+ /* Master/Primary card */
+ enet[5] = 0x01;
+ } else {
+ /* Slave/Secondary card */
+ enet [5] = 0x02;
+ }
+ }
+
+ return;
+}
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+
+ return (ctrlc());
+}
+#endif
diff --git a/board/sandburst/common/sb_common.h b/board/sandburst/common/sb_common.h
new file mode 100644
index 0000000..888e4f0
--- /dev/null
+++ b/board/sandburst/common/sb_common.h
@@ -0,0 +1,76 @@
+#ifndef __SBCOMMON_H__
+#define __SBCOMMON_H__
+/*
+ * Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "ppc440gx_i2c.h"
+
+/*
+ * GPIO Settings
+ */
+/* Chassis settings */
+#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */
+#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */
+
+/* Debug LEDs */
+#define SBCOMMON_GPIO_DBGLED_0 0x00000400
+#define SBCOMMON_GPIO_DBGLED_1 0x00000200
+#define SBCOMMON_GPIO_DBGLED_2 0x00100000
+#define SBCOMMON_GPIO_DBGLED_3 0x00000100
+
+#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \
+ SBCOMMON_GPIO_DBGLED_1 | \
+ SBCOMMON_GPIO_DBGLED_2 | \
+ SBCOMMON_GPIO_DBGLED_3)
+
+#define SBCOMMON_GPIO_SYS_FAULT 0x00000080
+#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040
+#define SBCOMMON_GPIO_SYS_STATUS 0x00000020
+
+#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS)
+
+#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \
+ SBCOMMON_GPIO_DBGLED_1 | \
+ SBCOMMON_GPIO_DBGLED_2 | \
+ SBCOMMON_GPIO_DBGLED_3 | \
+ SBCOMMON_GPIO_SYS_STATUS)
+
+typedef struct ppc440_gpio_regs {
+ volatile unsigned long out;
+ volatile unsigned long tri_state;
+ volatile unsigned long dummy[4];
+ volatile unsigned long open_drain;
+ volatile unsigned long in;
+} __attribute__((packed)) ppc440_gpio_regs_t;
+
+int sbcommon_get_master(void);
+int sbcommon_secondary_present(void);
+unsigned short sbcommon_get_serial_number(void);
+void sbcommon_fans(void);
+
+#endif /* __SBCOMMON_H__ */
diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile
new file mode 100644
index 0000000..8b3173c
--- /dev/null
+++ b/board/sandburst/karef/Makefile
@@ -0,0 +1,59 @@
+#
+# (C) Copyright 2005
+# Sandburst Corporation
+# Travis B. Sawyer
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# TBS: add for debugging purposes
+BUILDUSER := $(shell whoami)
+FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o)
+
+CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
+# TBS: end debugging
+
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
+ ../common/sb_common.o
+
+SOBJS = init.o
+
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/sandburst/karef/config.mk b/board/sandburst/karef/config.mk
new file mode 100644
index 0000000..65c1e48
--- /dev/null
+++ b/board/sandburst/karef/config.mk
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2005
+# Sandburst Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Sandburst Corporation Metrobox Reference Design
+# Travis B. Sawyer
+#
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/sandburst/karef/hal_ka_of_auto.h b/board/sandburst/karef/hal_ka_of_auto.h
new file mode 100644
index 0000000..cc501c9
--- /dev/null
+++ b/board/sandburst/karef/hal_ka_of_auto.h
@@ -0,0 +1,324 @@
+/* ****************************************************************
+ * Common defs for reg spec for chip ka_of
+ * Auto-generated by trex2: DO NOT HAND-EDIT!!
+ * ****************************************************************
+ */
+
+#ifndef HAL_KA_OF_AUTO_H
+#define HAL_KA_OF_AUTO_H
+
+
+/* ----------------------------------------------------------------
+ * For block: 'ofem'
+ */
+
+/* ---- Block instance addressing (for block-select) */
+#define OFEM_BLOCK_ADDR_BIT_L 6
+#define OFEM_BLOCK_ADDR_BIT_H 9
+#define OFEM_BLOCK_ADDR_WIDTH 4
+
+#define OFEM_ADDR 0x0
+
+/* ---- Reg addressing (within block) */
+#define OFEM_REG_ADDR_BIT_L 2
+#define OFEM_REG_ADDR_BIT_H 5
+#define OFEM_REG_ADDR_WIDTH 4
+
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_REVISION */
+#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET 0x000
+#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_REVISION_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_REVISION_MSB 31
+#define SAND_HAL_KA_OF_OFEM_REVISION_LSB 0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_RESET */
+#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET 0x004
+#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_RESET_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_RESET_MSB 31
+#define SAND_HAL_KA_OF_OFEM_RESET_LSB 0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_CNTL */
+#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET 0x018
+#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_CNTL_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_CNTL_MSB 31
+#define SAND_HAL_KA_OF_OFEM_CNTL_LSB 0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET 0x01c
+#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB 31
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB 0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_INTERRUPT */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET 0x008
+#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB 31
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB 0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_INTERRUPT_MASK */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET 0x00c
+#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB 31
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB 0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_SCRATCH */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET 0x010
+#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB 31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB 0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_SCRATCH_MASK */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET 0x014
+#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB 31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB 0
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_REVISION */
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK 0x0000ff00
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT 8
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB 15
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB 8
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT 0x00000024
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK 0x000000ff
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB 7
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB 0
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_RESET */
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK 0x00000004
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT 2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB 2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB 2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK 0x00000002
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT 1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB 1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB 1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK 0x00000001
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB 0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB 0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_CNTL */
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK 0x000000c0
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT 6
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB 7
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB 6
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK 0x00000030
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT 4
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB 5
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB 4
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK 0x0000000c
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT 2
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB 3
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB 2
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK 0x00000003
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB 1
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB 0
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK 0x00000100
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT 8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB 8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB 8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_INTERRUPT */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK 0x00000100
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT 8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB 8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB 8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000080
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT 7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB 7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB 7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000040
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT 6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB 6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB 6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK 0x00000020
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT 5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB 5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB 5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK 0x00000010
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT 4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB 4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB 4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK 0x00000008
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT 3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB 3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB 3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK 0x00000004
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT 2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB 2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB 2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK 0x00000002
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT 1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB 1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB 1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB 0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB 0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_INTERRUPT_MASK */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00000100
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000080
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000040
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000020
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000010
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000008
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000004
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_SCRATCH */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB 31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB 0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_SCRATCH_MASK */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
+
+#endif /* matches #ifndef HAL_KA_OF_AUTO_H */
diff --git a/board/sandburst/karef/hal_ka_sc_auto.h b/board/sandburst/karef/hal_ka_sc_auto.h
new file mode 100644
index 0000000..db1cec2
--- /dev/null
+++ b/board/sandburst/karef/hal_ka_sc_auto.h
@@ -0,0 +1,836 @@
+/* ****************************************************************
+ * Common defs for reg spec for chip ka_sc
+ * Auto-generated by trex2: DO NOT HAND-EDIT!!
+ * ****************************************************************
+ */
+
+#ifndef HAL_KA_SC_AUTO_H
+#define HAL_KA_SC_AUTO_H
+
+
+/* ----------------------------------------------------------------
+ * For block: 'scan'
+ */
+
+/* ---- Block instance addressing (for block-select) */
+#define SCAN_BLOCK_ADDR_BIT_L 7
+#define SCAN_BLOCK_ADDR_BIT_H 9
+#define SCAN_BLOCK_ADDR_WIDTH 3
+
+#define SCAN_ADDR 0x0
+
+/* ---- Reg addressing (within block) */
+#define SCAN_REG_ADDR_BIT_L 2
+#define SCAN_REG_ADDR_BIT_H 6
+#define SCAN_REG_ADDR_WIDTH 5
+
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_REVISION */
+#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000
+#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31
+#define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_RESET */
+#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004
+#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_RESET_MSB 31
+#define SAND_HAL_KA_SC_SCAN_RESET_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_STATUS */
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008
+#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31
+#define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_CNTL */
+#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c
+#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31
+#define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_INFO */
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_FROM_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_FROM_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_TO_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_TO_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_CTRL */
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_PLL_CTRL */
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038
+#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c
+#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_DR_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040
+#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044
+#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_IN */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_MISC */
+#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054
+#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_MISC_MSB 31
+#define SAND_HAL_KA_SC_SCAN_MISC_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_INTERRUPT */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c
+#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB 31
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_INTERRUPT_MASK */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET 0x010
+#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB 31
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCRATCH */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET 0x014
+#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB 0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCRATCH_MASK */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET 0x018
+#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB 0
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_REVISION */
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK 0x0000ff00
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT 8
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB 15
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB 8
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT 0x00000023
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK 0x000000ff
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB 7
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB 0
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_RESET */
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK 0x00000200
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT 9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB 9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB 9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK 0x00000100
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT 8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB 8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB 8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK 0x00000080
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT 7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB 7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB 7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK 0x00000040
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT 6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB 6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB 6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK 0x00000020
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT 5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB 5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB 5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK 0x00000010
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT 4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB 4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB 4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK 0x00000008
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT 3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB 3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB 3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK 0x00000002
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT 1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB 1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB 1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK 0x00000001
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB 0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB 0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_STATUS */
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK 0x00000040
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT 6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB 6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB 6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK 0x00000020
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT 5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB 5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB 5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK 0x00000010
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT 4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB 4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB 4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK 0x00000008
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT 3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB 3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB 3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK 0x00000004
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT 2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB 2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB 2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK 0x00000002
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT 1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB 1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB 1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK 0x00000001
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB 0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB 0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_CNTL */
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK 0x00000400
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT 10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB 10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB 10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK 0x00000200
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT 9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB 9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB 9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK 0x00000100
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT 8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB 8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB 8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT 0x00000001
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK 0x000000c0
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT 6
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB 7
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB 6
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK 0x00000030
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT 4
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB 5
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB 4
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK 0x0000000c
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT 2
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB 3
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB 2
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK 0x00000003
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB 1
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB 0
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_INFO */
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK 0x0000f000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT 12
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB 15
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB 12
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK 0x00000300
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT 8
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB 9
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB 8
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK 0x000000f0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT 4
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB 7
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB 4
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK 0x00000003
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB 1
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB 0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_FROM_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_FROM_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_TO_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_TO_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_CTRL */
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK 0x04000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT 26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB 26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB 26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK 0x03000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT 24
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB 25
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB 24
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK 0x00100000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT 20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB 20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB 20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK 0x00080000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT 19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB 19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB 19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK 0x00040000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT 18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB 18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB 18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK 0x00020000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT 17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB 17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB 17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK 0x00010000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT 16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB 16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB 16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK 0x00001000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT 12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB 12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB 12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK 0x00000800
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT 11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB 11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB 11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK 0x00000400
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT 10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB 10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB 10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK 0x00000200
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT 9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB 9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB 9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK 0x00000100
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT 8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB 8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB 8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK 0x00000018
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT 3
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB 4
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB 3
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK 0x00000004
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT 2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB 2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB 2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK 0x00000002
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT 1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB 1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB 1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK 0x00000001
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_PLL_CTRL */
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK 0x00002000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT 13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB 13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB 13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK 0x00001000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT 12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB 12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB 12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK 0x00000800
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT 11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB 11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB 11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK 0x00000400
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT 10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB 10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB 10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK 0x00000200
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT 9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB 9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB 9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK 0x00000100
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT 8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB 8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB 8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK 0x00000080
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT 7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB 7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB 7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK 0x00000040
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT 6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB 6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB 6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK 0x00000020
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT 5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB 5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB 5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK 0x00000010
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT 4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB 4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB 4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK 0x00000008
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT 3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB 3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB 3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK 0x00000007
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB 2
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB 0
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB 23
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_DR_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB 23
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB 23
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK 0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB 20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK 0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB 20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB 0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_IN */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK 0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB 20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB 0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_MISC */
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK 0x00000002
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT 1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB 1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB 1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK 0x00000001
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB 0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB 0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_INTERRUPT */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK 0x00000010
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT 4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB 4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB 4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK 0x00000008
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT 3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB 3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB 3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK 0x00000004
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT 2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB 2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB 2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK 0x00000002
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT 1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB 1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB 1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK 0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB 0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB 0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_INTERRUPT_MASK */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00000010
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000008
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000004
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000002
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCRATCH */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCRATCH_MASK */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
+
+#endif /* matches #ifndef HAL_KA_SC_AUTO_H */
diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S
new file mode 100644
index 0000000..b1d47a4
--- /dev/null
+++ b/board/sandburst/karef/init.S
@@ -0,0 +1,101 @@
+/*
+* Copyright (C) 2005 Sandburst Corporation
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+/*
+ * Ported from Ebony init.S by Travis B. Sawyer
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbtab_end
diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c
new file mode 100644
index 0000000..3856a39
--- /dev/null
+++ b/board/sandburst/karef/karef.c
@@ -0,0 +1,577 @@
+/*
+ * Copyright (C) 2005 Sandburst Corporation
+ * Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include "karef.h"
+#include "karef_version.h"
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "../common/sb_common.h"
+#include "../common/ppc440gx_i2c.h"
+
+void fpga_init (void);
+
+KAREF_BOARD_ID_ST board_id_as[] =
+{
+ {"Undefined"}, /* Not specified */
+ {"Kamino Reference Design"},
+ {"Reserved"}, /* Reserved for future use */
+ {"Reserved"}, /* Reserved for future use */
+};
+
+KAREF_BOARD_ID_ST ofem_board_id_as[] =
+{
+ {"Undefined"},
+ {"1x10 + 10x2"},
+ {"Reserved"},
+ {"Reserved"},
+};
+
+/*************************************************************************
+ * board_early_init_f
+ *
+ * Setup chip selects, initialize the Opto-FPGA, initialize
+ * interrupt polarity and triggers.
+ ************************************************************************/
+int board_early_init_f (void)
+{
+ ppc440_gpio_regs_t *gpio_regs;
+
+ /* Enable GPIO interrupts */
+ mtsdr(sdr_pfc0, 0x00103E00);
+
+ /* Setup access for LEDs, and system topology info */
+ gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+ gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
+ gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
+
+ /* Turn on all the leds for now */
+ gpio_regs->out = SBCOMMON_GPIO_LEDS;
+
+ /*--------------------------------------------------------------------+
+ | Initialize EBC CONFIG
+ +-------------------------------------------------------------------*/
+ mtebc(xbcfg,
+ EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
+ EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
+ EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
+ EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
+ EBC_CFG_PR_32);
+
+ /*--------------------------------------------------------------------+
+ | 1/2 MB FLASH. Initialize bank 0 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb0ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+ /*--------------------------------------------------------------------+
+ | 8KB NVRAM/RTC. Initialize bank 1 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb1ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+
+ /*--------------------------------------------------------------------+
+ | Compact Flash, uses 2 Chip Selects (2 & 6)
+ +-------------------------------------------------------------------*/
+ mtebc(pb2ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+ /*--------------------------------------------------------------------+
+ | KaRef Scan FPGA. Initialize bank 3 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb5ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+ mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*--------------------------------------------------------------------+
+ | MAC A & B for Kamino. OFEM FPGA decodes the addresses
+ | Initialize bank 4 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb4ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+ mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
+ EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*--------------------------------------------------------------------+
+ | OFEM FPGA Initialize bank 5 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb3ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+
+ mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+
+ /*--------------------------------------------------------------------+
+ | Compact Flash, uses 2 Chip Selects (2 & 6)
+ +-------------------------------------------------------------------*/
+ mtebc(pb6ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+ /*--------------------------------------------------------------------+
+ | BME-32. Initialize bank 7 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb7ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+ mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*--------------------------------------------------------------------+
+ * Setup the interrupt controller polarities, triggers, etc.
+ +-------------------------------------------------------------------*/
+ mtdcr (uic0sr, 0xffffffff); /* clear all */
+ mtdcr (uic0er, 0x00000000); /* disable all */
+ mtdcr (uic0cr, 0x00000000); /* all non- critical */
+ mtdcr (uic0pr, 0xfffffe03); /* polarity */
+ mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
+ mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic1sr, 0xffffffff); /* clear all */
+ mtdcr (uic1er, 0x00000000); /* disable all */
+ mtdcr (uic1cr, 0x00000000); /* all non-critical */
+ mtdcr (uic1pr, 0xffffc8ff); /* polarity */
+ mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
+ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic1sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic2sr, 0xffffffff); /* clear all */
+ mtdcr (uic2er, 0x00000000); /* disable all */
+ mtdcr (uic2cr, 0x00000000); /* all non-critical */
+ mtdcr (uic2pr, 0xffff83ff); /* polarity */
+ mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
+ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic2sr, 0xffffffff); /* clear all */
+
+ mtdcr (uicb0sr, 0xfc000000); /* clear all */
+ mtdcr (uicb0er, 0x00000000); /* disable all */
+ mtdcr (uicb0cr, 0x00000000); /* all non-critical */
+ mtdcr (uicb0pr, 0xfc000000);
+ mtdcr (uicb0tr, 0x00000000);
+ mtdcr (uicb0vr, 0x00000001);
+
+ fpga_init();
+
+ return 0;
+}
+
+
+/*************************************************************************
+ * checkboard
+ *
+ * Dump pertinent info to the console
+ ************************************************************************/
+int checkboard (void)
+{
+ sys_info_t sysinfo;
+ unsigned char brd_rev, brd_id;
+ unsigned short sernum;
+ unsigned char scan_rev, scan_id, ofem_rev, ofem_id;
+ unsigned char ofem_brd_rev, ofem_brd_id;
+ KAREF_FPGA_REGS_ST *karef_ps;
+ OFEM_FPGA_REGS_ST *ofem_ps;
+
+ karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+ ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+
+ scan_id = (unsigned char)((karef_ps->revision_ul &
+ SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
+ >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
+
+ scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
+ >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
+
+ brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
+ >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
+
+ brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
+ >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
+
+ ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
+ >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
+
+ ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
+ >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
+
+ if (0xF != ofem_brd_id) {
+ ofem_id = (unsigned char)((ofem_ps->revision_ul &
+ SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
+ >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
+
+ ofem_rev = (unsigned char)((ofem_ps->revision_ul &
+ SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
+ >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
+ }
+
+ get_sys_info (&sysinfo);
+
+ sernum = sbcommon_get_serial_number();
+
+ printf ("Board: Sandburst Corporation Kamino Reference Design "
+ "Serial Number: %d\n", sernum);
+ printf ("%s\n", KAREF_U_BOOT_REL_STR);
+
+ printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
+ if (sbcommon_get_master()) {
+ printf("Slot 0 - Master\nSlave board");
+ if (sbcommon_secondary_present())
+ printf(" present\n");
+ else
+ printf(" not detected\n");
+ } else {
+ printf("Slot 1 - Slave\n\n");
+ }
+
+ printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev);
+ printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id);
+ if(0xF != ofem_brd_id) {
+ printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev);
+ printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev);
+ }
+
+ printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+ printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+ printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+ printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+
+ /* Fix the ack in the bme 32 */
+ udelay(5000);
+ out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
+ asm("eieio");
+
+
+ return (0);
+}
+
+/*************************************************************************
+ * misc_init_f
+ *
+ * Initialize I2C bus one to gain access to the fans
+ ************************************************************************/
+int misc_init_f (void)
+{
+ /* Turn on i2c bus 1 */
+ puts ("I2C1: ");
+ i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ puts ("ready\n");
+
+ /* Turn on fans 3 & 4 */
+ sbcommon_fans();
+
+ return (0);
+}
+
+/*************************************************************************
+ * misc_init_r
+ *
+ * Do nothing.
+ ************************************************************************/
+int misc_init_r (void)
+{
+ unsigned short sernum;
+ char envstr[255];
+ KAREF_FPGA_REGS_ST *karef_ps;
+ OFEM_FPGA_REGS_ST *ofem_ps;
+ unsigned char ofem_id;
+
+ if(NULL != getenv("secondserial")) {
+ puts("secondserial is set, switching to second serial port\n");
+ setenv("stderr", "serial1");
+ setenv("stdout", "serial1");
+ setenv("stdin", "serial1");
+ }
+
+ setenv("ubrelver", KAREF_U_BOOT_REL_STR);
+
+ memset(envstr, 0, 255);
+ sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
+ setenv("bldstr", envstr);
+ saveenv();
+
+ if( getenv("autorecover")) {
+ setenv("autorecover", NULL);
+ saveenv();
+ sernum = sbcommon_get_serial_number();
+
+ printf("\nSetting up environment for automatic filesystem recovery\n");
+ /*
+ * Setup default bootargs
+ */
+ memset(envstr, 0, 255);
+
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+ "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
+ sernum, sernum);
+ setenv("bootargs", envstr);
+
+ /*
+ * Setup Default boot command
+ */
+ setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
+ "fatload ide 0 8100000 pramdisk;"
+ "bootm 8000000 8100000");
+
+ printf("Done. Please type allow the system to continue to boot\n");
+ }
+
+ if( getenv("fakeled")) {
+ karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+ ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+ ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
+ karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
+ setenv("bootdelay", "-1");
+ saveenv();
+ printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
+ }
+
+ return (0);
+}
+
+/*************************************************************************
+ * ide_set_reset
+ ************************************************************************/
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+ KAREF_FPGA_REGS_ST *karef_ps;
+ /* TODO: ide reset */
+ karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+
+ if (on) {
+ karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
+ } else {
+ karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
+ }
+}
+#endif /* CONFIG_IDE_RESET */
+
+/*************************************************************************
+ * fpga_init
+ ************************************************************************/
+void fpga_init(void)
+{
+ KAREF_FPGA_REGS_ST *karef_ps;
+ OFEM_FPGA_REGS_ST *ofem_ps;
+ unsigned char ofem_id;
+ unsigned long tmp;
+
+ /* Ensure we have power all around */
+ udelay(500);
+
+ karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+ tmp =
+ SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
+ SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
+
+ karef_ps->reset_ul = tmp;
+
+ /*
+ * Wait a bit to allow the ofem fpga to get its brains
+ */
+ udelay(5000);
+
+ /*
+ * Check to see if the ofem is there
+ */
+ ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
+ >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
+ if(0xF != ofem_id) {
+ tmp =
+ SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
+ SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
+ SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
+
+ ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+ ofem_ps->reset_ul = tmp;
+
+ ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
+ }
+
+ karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
+
+ asm("eieio");
+
+ return;
+}
+
+int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned short sernum;
+ char envstr[255];
+
+ sernum = sbcommon_get_serial_number();
+
+ memset(envstr, 0, 255);
+ /*
+ * Setup our ip address
+ */
+ sprintf(envstr, "10.100.70.%d", sernum);
+
+ setenv("ipaddr", envstr);
+ /*
+ * Setup the host ip address
+ */
+ setenv("serverip", "10.100.17.10");
+
+ /*
+ * Setup default bootargs
+ */
+ memset(envstr, 0, 255);
+
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
+ "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
+ "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
+ "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
+ sernum, sernum, sernum);
+
+ setenv("bootargs_nfs", envstr);
+ setenv("bootargs", envstr);
+
+ /*
+ * Setup CF bootargs
+ */
+ memset(envstr, 0, 255);
+
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
+ "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
+ sernum, sernum);
+
+ setenv("bootargs_cf", envstr);
+
+ /*
+ * Setup Default boot command
+ */
+ setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
+ setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
+
+ /*
+ * Setup compact flash boot command
+ */
+ setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
+
+ saveenv();
+
+ return(1);
+}
+
+int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned short sernum;
+ char envstr[255];
+
+ sernum = sbcommon_get_serial_number();
+
+ printf("\nSetting up environment for filesystem recovery\n");
+ /*
+ * Setup default bootargs
+ */
+ memset(envstr, 0, 255);
+
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+ "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
+ sernum, sernum);
+ setenv("bootargs", envstr);
+
+ /*
+ * Setup Default boot command
+ */
+
+ setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
+ "fatload ide 0 8100000 pramdisk;"
+ "bootm 8000000 8100000");
+
+ printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
+ " please type fsrecover.sh<cr>\n");
+
+ return(1);
+}
+
+U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
+ "kasetup - Set environment to factory defaults\n", NULL);
+
+U_BOOT_CMD(karecover, 1, 1, karefRecover,
+ "karecover - Set environment to allow for fs recovery\n", NULL);
diff --git a/board/sandburst/karef/karef.h b/board/sandburst/karef/karef.h
new file mode 100644
index 0000000..7790819
--- /dev/null
+++ b/board/sandburst/karef/karef.h
@@ -0,0 +1,76 @@
+#ifndef __KAREF_H__
+#define __KAREF_H__
+/*
+ * (C) Copyright 2005
+ * Sandburst Corporation
+ * Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Ka Reference Design OFEM FPGA Registers & definitions */
+#include "hal_ka_sc_auto.h"
+#include "hal_ka_of_auto.h"
+
+typedef struct karef_board_id_s {
+ const char name[40];
+} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST;
+
+/* SCAN FPGA */
+typedef struct karef_fpga_regs_s
+{
+ volatile unsigned long revision_ul; /* Read Only */
+ volatile unsigned long reset_ul; /* Read/Write */
+ volatile unsigned long interrupt_ul; /* Read Only */
+ volatile unsigned long mask_ul; /* Read/Write */
+ volatile unsigned long scratch_ul; /* Read/Write */
+ volatile unsigned long scrmask_ul; /* Read/Write */
+ volatile unsigned long status_ul; /* Read Only */
+ volatile unsigned long control_ul; /* Read/Write */
+ volatile unsigned long boardinfo_ul; /* Read Only */
+ volatile unsigned long scan_from0_ul; /* Read Only */
+ volatile unsigned long scan_from1_ul; /* Read Only */
+ volatile unsigned long scan_to0_ul; /* Read/Write */
+ volatile unsigned long scan_to1_ul; /* Read/Write */
+ volatile unsigned long scan_control_ul; /* Read/Write */
+ volatile unsigned long pll_control_ul; /* Read/Write */
+ volatile unsigned long core_clock_cnt_ul; /* Read/Write */
+ volatile unsigned long dr_clock_cnt_ul; /* Read/Write */
+ volatile unsigned long spi_clock_cnt_ul; /* Read/Write */
+ volatile unsigned long brdout_data_ul; /* Read/Write */
+ volatile unsigned long brdout_enable_ul; /* Read/Write */
+ volatile unsigned long brdin_data_ul; /* Read Only */
+ volatile unsigned long misc_ul; /* Read/Write */
+} KAREF_FPGA_REGS_ST __attribute__((packed)), * KAREF_FPGA_REGS_PST;
+
+/* OFEM FPGA */
+typedef struct ofem_fpga_regs_s
+{
+ volatile unsigned long revision_ul; /* Read Only */
+ volatile unsigned long reset_ul; /* Read/Write */
+ volatile unsigned long interrupt_ul; /* Read Only */
+ volatile unsigned long mask_ul; /* Read/Write */
+ volatile unsigned long scratch_ul; /* Read/Write */
+ volatile unsigned long scrmask_ul; /* Read/Write */
+ volatile unsigned long control_ul; /* Read/Write */
+ volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */
+} OFEM_FPGA_REGS_ST __attribute__((packed)), * OFEM_FPGA_REGS_PST;
+
+
+#endif /* __KAREF_H__ */
diff --git a/board/sandburst/karef/karef_version.h b/board/sandburst/karef/karef_version.h
new file mode 100644
index 0000000..9960b9a
--- /dev/null
+++ b/board/sandburst/karef/karef_version.h
@@ -0,0 +1,26 @@
+#ifndef _KAREF_VERSION_H_
+#define _KAREF_VERSION_H_
+/*
+ * Copyright (C) 2005 Sandburst Corporation
+ * Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#define KAREF_U_BOOT_REL_STR "Release 0.0.7"
+#endif
diff --git a/board/sandburst/karef/u-boot.lds b/board/sandburst/karef/u-boot.lds
new file mode 100644
index 0000000..ff8658f
--- /dev/null
+++ b/board/sandburst/karef/u-boot.lds
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/sandburst/karef/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/440gx_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug
new file mode 100644
index 0000000..c6522b9
--- /dev/null
+++ b/board/sandburst/karef/u-boot.lds.debug
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/sandburst/karef/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/440gx_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* common/environment.o(.text) */
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile
new file mode 100644
index 0000000..06a9a22
--- /dev/null
+++ b/board/sandburst/metrobox/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2005
+# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# TBS: add for debugging purposes
+BUILDUSER := $(shell whoami)
+FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o)
+
+CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
+# TBS: end debugging
+
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
+ ../common/sb_common.o
+SOBJS = init.o
+
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk
new file mode 100644
index 0000000..91aee2f
--- /dev/null
+++ b/board/sandburst/metrobox/config.mk
@@ -0,0 +1,38 @@
+#
+# (C) Copyright 2005
+# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/sandburst/metrobox/hal_xc_auto.h b/board/sandburst/metrobox/hal_xc_auto.h
new file mode 100644
index 0000000..c99b38c
--- /dev/null
+++ b/board/sandburst/metrobox/hal_xc_auto.h
@@ -0,0 +1,553 @@
+/* ****************************************************************
+ * Common defs for reg spec for chip xc
+ * Auto-generated by trex2: DO NOT HAND-EDIT!!
+ * ****************************************************************
+ */
+
+#ifndef HAL_XC_AUTO_H
+#define HAL_XC_AUTO_H
+
+/* ----------------------------------------------------------------
+ * For block: 'xcvr_cntl'
+ */
+
+/* ---- Block instance addressing (for block-select) */
+#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6
+#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9
+#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4
+
+#define XCVR_CNTL_ADDR 0x0
+
+/* ---- Reg addressing (within block) */
+#define XCVR_CNTL_REG_ADDR_BIT_L 2
+#define XCVR_CNTL_REG_ADDR_BIT_H 5
+#define XCVR_CNTL_REG_ADDR_WIDTH 4
+
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_REVISION */
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET 0x000
+#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_RESET */
+#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET 0x004
+#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_STATUS */
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET 0x008
+#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_CNTL */
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET 0x01c
+#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_BRD_INFO */
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET 0x020
+#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET 0x024
+#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_INTERRUPT */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET 0x00c
+#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET 0x010
+#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_SCRATCH */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET 0x014
+#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB 0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET 0x018
+#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK 0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB 0
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_REVISION */
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK 0x0000ff00
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT 8
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB 15
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB 8
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK 0x000000ff
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB 7
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_RESET */
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK 0x00020000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT 17
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB 17
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB 17
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK 0x00010000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT 16
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB 16
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB 16
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK 0x00008000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT 15
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB 15
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB 15
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK 0x00004000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT 14
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB 14
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB 14
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK 0x00002000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT 13
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB 13
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB 13
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK 0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT 12
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB 12
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB 12
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK 0x00000800
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT 11
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB 11
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB 11
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK 0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT 10
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB 10
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB 10
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK 0x00000200
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT 9
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB 9
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB 9
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK 0x00000100
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT 8
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB 8
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB 8
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK 0x00000080
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT 7
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB 7
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB 7
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK 0x00000040
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT 6
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB 6
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB 6
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK 0x00000020
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT 5
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB 5
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB 5
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK 0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT 4
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB 4
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB 4
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK 0x00000008
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT 3
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB 3
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB 3
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK 0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT 2
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB 2
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB 2
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK 0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT 1
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB 1
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB 1
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB 0
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_STATUS */
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK 0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT 2
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB 2
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB 2
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK 0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT 1
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB 1
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB 1
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB 0
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_CNTL */
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK 0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT 10
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB 10
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB 10
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK 0x00000300
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT 8
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB 9
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB 8
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK 0x000000c0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT 6
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB 7
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB 6
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK 0x00000030
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT 4
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB 5
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB 4
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK 0x0000000c
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT 2
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB 3
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB 2
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK 0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT 1
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB 1
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB 1
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB 0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT 0x00000001
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_BRD_INFO */
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK 0x000000f0
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT 4
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB 7
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB 4
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK 0x00000003
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB 1
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK 0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT 12
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB 12
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB 12
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK 0x00000f00
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT 8
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB 11
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB 8
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_INTERRUPT */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK 0x00002000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT 13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB 13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB 13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK 0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT 12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB 12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB 12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000800
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT 11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB 11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB 11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT 10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB 10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB 10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK 0x00000200
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT 9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB 9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB 9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK 0x00000100
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT 8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB 8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB 8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK 0x00000080
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT 7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB 7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB 7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK 0x00000040
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT 6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB 6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB 6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK 0x00000020
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT 5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB 5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB 5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK 0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT 4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB 4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB 4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK 0x00000008
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT 3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB 3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB 3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK 0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT 2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB 2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB 2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK 0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT 1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB 1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB 1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB 0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00002000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000800
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000200
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000100
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000080
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000040
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000020
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000008
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_SCRATCH */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT 0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
+
+#endif /* matches #ifndef HAL_XC_AUTO_H */
diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S
new file mode 100644
index 0000000..e398f00
--- /dev/null
+++ b/board/sandburst/metrobox/init.S
@@ -0,0 +1,99 @@
+/*
+* Copyright (C) 2005
+* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbtab_end
diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
new file mode 100644
index 0000000..869367d
--- /dev/null
+++ b/board/sandburst/metrobox/metrobox.c
@@ -0,0 +1,543 @@
+/*
+ * Copyright (c) 2005
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include "metrobox.h"
+#include "metrobox_version.h"
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "../common/ppc440gx_i2c.h"
+#include "../common/sb_common.h"
+
+void fpga_init (void);
+
+METROBOX_BOARD_ID_ST board_id_as[] =
+{ {"Undefined"}, /* Not specified */
+ {"2x10Gb"}, /* 2 ports, 10 GbE */
+ {"20x1Gb"}, /* 20 ports, 1 GbE */
+ {"Reserved"}, /* Reserved for future use */
+};
+
+/*************************************************************************
+ * board_early_init_f
+ *
+ * Setup chip selects, initialize the Opto-FPGA, initialize
+ * interrupt polarity and triggers.
+ ************************************************************************/
+int board_early_init_f (void)
+{
+ ppc440_gpio_regs_t *gpio_regs;
+
+ /* Enable GPIO interrupts */
+ mtsdr(sdr_pfc0, 0x00103E00);
+
+ /* Setup access for LEDs, and system topology info */
+ gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+ gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
+ gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
+
+ /* Turn on all the leds for now */
+ gpio_regs->out = SBCOMMON_GPIO_LEDS;
+
+ /*--------------------------------------------------------------------+
+ | Initialize EBC CONFIG
+ +-------------------------------------------------------------------*/
+ mtebc(xbcfg,
+ EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
+ EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
+ EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
+ EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
+ EBC_CFG_PR_32);
+
+ /*--------------------------------------------------------------------+
+ | 1/2 MB FLASH. Initialize bank 0 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb0ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+ /*--------------------------------------------------------------------+
+ | 8KB NVRAM/RTC. Initialize bank 1 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb1ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+
+ /*--------------------------------------------------------------------+
+ | Compact Flash, uses 2 Chip Selects (2 & 6)
+ +-------------------------------------------------------------------*/
+ mtebc(pb2ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+ /*--------------------------------------------------------------------+
+ | OPTO & OFEM FPGA. Initialize bank 3 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb3ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+ mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*--------------------------------------------------------------------+
+ | MAC A for metrobox
+ | MAC A & B for Kamino. OFEM FPGA decodes the addresses
+ | Initialize bank 4 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb4ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+ mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*--------------------------------------------------------------------+
+ | Metrobox MAC B Initialize bank 5 with default values.
+ | KA REF FPGA Initialize bank 5 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb5ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+ mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*--------------------------------------------------------------------+
+ | Compact Flash, uses 2 Chip Selects (2 & 6)
+ +-------------------------------------------------------------------*/
+ mtebc(pb6ap,
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
+ EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+ EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+
+ mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+ /*--------------------------------------------------------------------+
+ | BME-32. Initialize bank 7 with default values.
+ +-------------------------------------------------------------------*/
+ mtebc(pb7ap,
+ EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+ EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+ mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*--------------------------------------------------------------------+
+ * Setup the interrupt controller polarities, triggers, etc.
+ +-------------------------------------------------------------------*/
+ mtdcr (uic0sr, 0xffffffff); /* clear all */
+ mtdcr (uic0er, 0x00000000); /* disable all */
+ mtdcr (uic0cr, 0x00000000); /* all non- critical */
+ mtdcr (uic0pr, 0xfffffe03); /* polarity */
+ mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
+ mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic1sr, 0xffffffff); /* clear all */
+ mtdcr (uic1er, 0x00000000); /* disable all */
+ mtdcr (uic1cr, 0x00000000); /* all non-critical */
+ mtdcr (uic1pr, 0xffffc8ff); /* polarity */
+ mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
+ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic1sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic2sr, 0xffffffff); /* clear all */
+ mtdcr (uic2er, 0x00000000); /* disable all */
+ mtdcr (uic2cr, 0x00000000); /* all non-critical */
+ mtdcr (uic2pr, 0xffff83ff); /* polarity */
+ mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
+ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic2sr, 0xffffffff); /* clear all */
+
+ mtdcr (uicb0sr, 0xfc000000); /* clear all */
+ mtdcr (uicb0er, 0x00000000); /* disable all */
+ mtdcr (uicb0cr, 0x00000000); /* all non-critical */
+ mtdcr (uicb0pr, 0xfc000000);
+ mtdcr (uicb0tr, 0x00000000);
+ mtdcr (uicb0vr, 0x00000001);
+
+ fpga_init();
+
+ return 0;
+}
+
+/*************************************************************************
+ * checkboard
+ *
+ * Dump pertinent info to the console
+ ************************************************************************/
+int checkboard (void)
+{
+ sys_info_t sysinfo;
+ unsigned char brd_rev, brd_id;
+ unsigned short sernum;
+ unsigned char opto_rev, opto_id;
+ OPTO_FPGA_REGS_ST *opto_ps;
+
+ opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+
+ opto_rev = (unsigned char)((opto_ps->revision_ul &
+ SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
+ >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
+
+ opto_id = (unsigned char)((opto_ps->revision_ul &
+ SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
+ >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
+
+ brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
+ SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
+ >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
+
+ brd_id = (unsigned char)((opto_ps->boardinfo_ul &
+ SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
+ >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
+
+ get_sys_info (&sysinfo);
+
+ sernum = sbcommon_get_serial_number();
+ printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
+ printf ("%s\n", METROBOX_U_BOOT_REL_STR);
+
+ printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
+ if (sbcommon_get_master()) {
+ printf("Slot 0 - Master\nSlave board");
+ if (sbcommon_secondary_present())
+ printf(" present\n");
+ else
+ printf(" not detected\n");
+ } else {
+ printf("Slot 1 - Slave\n\n");
+ }
+
+ printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
+ printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]);
+
+ printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+ printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+ printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+ printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+
+
+ /* Fix the ack in the bme 32 */
+ udelay(5000);
+ out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
+ asm("eieio");
+
+
+ return (0);
+}
+
+/*************************************************************************
+ * misc_init_f
+ *
+ * Initialize I2C bus one to gain access to the fans
+ ************************************************************************/
+int misc_init_f (void)
+{
+ /* Turn on i2c bus 1 */
+ puts ("I2C1: ");
+ i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ puts ("ready\n");
+
+ /* Turn on fans */
+ sbcommon_fans();
+
+ return (0);
+}
+
+/*************************************************************************
+ * misc_init_r
+ *
+ * Do nothing.
+ ************************************************************************/
+int misc_init_r (void)
+{
+ unsigned short sernum;
+ char envstr[255];
+ unsigned char opto_rev;
+ OPTO_FPGA_REGS_ST *opto_ps;
+
+ opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+
+ if(NULL != getenv("secondserial")) {
+ puts("secondserial is set, switching to second serial port\n");
+ setenv("stderr", "serial1");
+ setenv("stdout", "serial1");
+ setenv("stdin", "serial1");
+ }
+
+ setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
+
+ memset(envstr, 0, 255);
+ sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
+ setenv("bldstr", envstr);
+ saveenv();
+
+ if( getenv("autorecover")) {
+ setenv("autorecover", NULL);
+ saveenv();
+ sernum = sbcommon_get_serial_number();
+
+ printf("\nSetting up environment for automatic filesystem recovery\n");
+ /*
+ * Setup default bootargs
+ */
+ memset(envstr, 0, 255);
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+ "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
+ sernum, sernum);
+ setenv("bootargs", envstr);
+
+ /*
+ * Setup Default boot command
+ */
+ setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
+ "fatload ide 0 8100000 pramdisk;"
+ "bootm 8000000 8100000");
+
+ printf("Done. Please type allow the system to continue to boot\n");
+ }
+
+ if( getenv("fakeled")) {
+ setenv("bootdelay", "-1");
+ saveenv();
+ printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
+ opto_rev = (unsigned char)((opto_ps->revision_ul &
+ SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
+ >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
+
+ if(0x12 <= opto_rev) {
+ opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
+ }
+ }
+
+ return (0);
+}
+
+/*************************************************************************
+ * ide_set_reset
+ ************************************************************************/
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+ OPTO_FPGA_REGS_ST *opto_ps;
+ opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+
+ if (on) { /* assert RESET */
+ opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
+ } else { /* release RESET */
+ opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
+ }
+}
+#endif /* CONFIG_IDE_RESET */
+
+/*************************************************************************
+ * fpga_init
+ ************************************************************************/
+void fpga_init(void)
+{
+ OPTO_FPGA_REGS_ST *opto_ps;
+ unsigned char opto_rev;
+ unsigned long tmp;
+
+ /* Ensure we have power all around */
+ udelay(500);
+
+ /*
+ * Take appropriate hw bits out of reset
+ */
+ opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+
+ tmp =
+ SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
+ SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
+ opto_ps->reset_ul = tmp;
+ /*
+ * Turn on the 'Slow Blink' for the System Error Led.
+ * Ensure FPGA rev is up to at least rev 0x12
+ */
+ opto_rev = (unsigned char)((opto_ps->revision_ul &
+ SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
+ >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
+ if(0x12 <= opto_rev) {
+ opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
+ }
+
+ asm("eieio");
+
+ return;
+}
+
+int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned short sernum;
+ char envstr[255];
+
+ sernum = sbcommon_get_serial_number();
+
+ memset(envstr, 0, 255);
+ /*
+ * Setup our ip address
+ */
+ sprintf(envstr, "10.100.60.%d", sernum);
+
+ setenv("ipaddr", envstr);
+ /*
+ * Setup the host ip address
+ */
+ setenv("serverip", "10.100.17.10");
+
+ /*
+ * Setup default bootargs
+ */
+ memset(envstr, 0, 255);
+
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
+ "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
+ "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
+ ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
+ sernum, sernum, sernum);
+
+ setenv("bootargs_nfs", envstr);
+ setenv("bootargs", envstr);
+
+ /*
+ * Setup CF bootargs
+ */
+ memset(envstr, 0, 255);
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
+ "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
+ sernum, sernum);
+
+ setenv("bootargs_cf", envstr);
+
+ /*
+ * Setup Default boot command
+ */
+ setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
+ setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
+
+ /*
+ * Setup compact flash boot command
+ */
+ setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
+
+ saveenv();
+
+
+ return(1);
+}
+
+int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned short sernum;
+ char envstr[255];
+
+ sernum = sbcommon_get_serial_number();
+
+ printf("\nSetting up environment for filesystem recovery\n");
+ /*
+ * Setup default bootargs
+ */
+ memset(envstr, 0, 255);
+ sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+ "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
+ sernum, sernum);
+
+ setenv("bootargs", envstr);
+
+ /*
+ * Setup Default boot command
+ */
+ setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
+ "fatload ide 0 8100000 pramdisk;"
+ "bootm 8000000 8100000");
+
+ printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
+ " please type fsrecover.sh<cr>\n");
+
+ return(1);
+}
+
+U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
+ "mbsetup - Set environment to factory defaults\n", NULL);
+
+U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
+ "mbrecover - Set environment to allow for fs recovery\n", NULL);
diff --git a/board/sandburst/metrobox/metrobox.h b/board/sandburst/metrobox/metrobox.h
new file mode 100644
index 0000000..cb7a83c
--- /dev/null
+++ b/board/sandburst/metrobox/metrobox.h
@@ -0,0 +1,45 @@
+#ifndef __METROBOX_H__
+#define __METROBOX_H__
+/*
+ * (C) Copyright 2005
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+typedef struct metrobox_board_id_s {
+ const char name[40];
+} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST;
+
+
+/* Metrobox Opto-FPGA registers and definitions */
+#include "hal_xc_auto.h"
+typedef struct opto_fpga_regs_s {
+ volatile unsigned long revision_ul; /* Read Only */
+ volatile unsigned long reset_ul; /* Read/Write */
+ volatile unsigned long status_ul; /* Read Only */
+ volatile unsigned long interrupt_ul; /* Read Only */
+ volatile unsigned long mask_ul; /* Read/Write */
+ volatile unsigned long scratch_ul; /* Read/Write */
+ volatile unsigned long scrmask_ul; /* Read/Write */
+ volatile unsigned long control_ul; /* Read/Write */
+ volatile unsigned long boardinfo_ul; /* Read Only */
+} OPTO_FPGA_REGS_ST __attribute__ ((packed)), *OPTO_FPGA_REGS_PST;
+
+#endif /* __METROBOX_H__ */
diff --git a/board/sandburst/metrobox/metrobox_version.h b/board/sandburst/metrobox/metrobox_version.h
new file mode 100644
index 0000000..1b6fee5
--- /dev/null
+++ b/board/sandburst/metrobox/metrobox_version.h
@@ -0,0 +1,27 @@
+#ifndef _METROBOX_VERSION_H_
+#define _METROBOX_VERSION_H_
+/*
+ * (C) Copyright 2005
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#define METROBOX_U_BOOT_REL_STR "Release 2.0.3"
+
+#endif
diff --git a/board/sandburst/metrobox/u-boot.lds b/board/sandburst/metrobox/u-boot.lds
new file mode 100644
index 0000000..0fdb166
--- /dev/null
+++ b/board/sandburst/metrobox/u-boot.lds
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/sandburst/metrobox/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/440gx_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug
new file mode 100644
index 0000000..459a1d8
--- /dev/null
+++ b/board/sandburst/metrobox/u-boot.lds.debug
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/sandburst/metrobox/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/440gx_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* common/environment.o(.text) */
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/stxxtc/Makefile b/board/stxxtc/Makefile
new file mode 100644
index 0000000..8c529a0
--- /dev/null
+++ b/board/stxxtc/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/stxxtc/config.mk b/board/stxxtc/config.mk
new file mode 100644
index 0000000..f5dc034
--- /dev/null
+++ b/board/stxxtc/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# STx XTc
+#
+
+TEXT_BASE = 0x40F00000
diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c
new file mode 100644
index 0000000..b38b4be
--- /dev/null
+++ b/board/stxxtc/stxxtc.c
@@ -0,0 +1,638 @@
+/*
+ * (C) Copyright 2000-2004
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2005
+ * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * U-Boot port on STx XTc board
+ * Mostly copied from Netta
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include "mpc8xx.h"
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b) (1U << (31-(_b)))
+#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b) (1U << (15-(_b)))
+#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b) (1U << (7-(_b)))
+#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b) _BD(_b)
+#define _BR(_l, _h) _BDR(_l, _h)
+
+/****************************************************************/
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+ printf ("Silicon Turnkey eXpress XTc\n");
+ return (0);
+}
+
+/****************************************************************/
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000 0x00000000
+#define CS_0001 0x10000000
+#define CS_0010 0x20000000
+#define CS_0011 0x30000000
+#define CS_0100 0x40000000
+#define CS_0101 0x50000000
+#define CS_0110 0x60000000
+#define CS_0111 0x70000000
+#define CS_1000 0x80000000
+#define CS_1001 0x90000000
+#define CS_1010 0xA0000000
+#define CS_1011 0xB0000000
+#define CS_1100 0xC0000000
+#define CS_1101 0xD0000000
+#define CS_1110 0xE0000000
+#define CS_1111 0xF0000000
+
+#define BS_0000 0x00000000
+#define BS_0001 0x01000000
+#define BS_0010 0x02000000
+#define BS_0011 0x03000000
+#define BS_0100 0x04000000
+#define BS_0101 0x05000000
+#define BS_0110 0x06000000
+#define BS_0111 0x07000000
+#define BS_1000 0x08000000
+#define BS_1001 0x09000000
+#define BS_1010 0x0A000000
+#define BS_1011 0x0B000000
+#define BS_1100 0x0C000000
+#define BS_1101 0x0D000000
+#define BS_1110 0x0E000000
+#define BS_1111 0x0F000000
+
+#define GPL0_AAAA 0x00000000
+#define GPL0_AAA0 0x00200000
+#define GPL0_AAA1 0x00300000
+#define GPL0_000A 0x00800000
+#define GPL0_0000 0x00A00000
+#define GPL0_0001 0x00B00000
+#define GPL0_111A 0x00C00000
+#define GPL0_1110 0x00E00000
+#define GPL0_1111 0x00F00000
+
+#define GPL1_0000 0x00000000
+#define GPL1_0001 0x00040000
+#define GPL1_1110 0x00080000
+#define GPL1_1111 0x000C0000
+
+#define GPL2_0000 0x00000000
+#define GPL2_0001 0x00010000
+#define GPL2_1110 0x00020000
+#define GPL2_1111 0x00030000
+
+#define GPL3_0000 0x00000000
+#define GPL3_0001 0x00004000
+#define GPL3_1110 0x00008000
+#define GPL3_1111 0x0000C000
+
+#define GPL4_0000 0x00000000
+#define GPL4_0001 0x00001000
+#define GPL4_1110 0x00002000
+#define GPL4_1111 0x00003000
+
+#define GPL5_0000 0x00000000
+#define GPL5_0001 0x00000400
+#define GPL5_1110 0x00000800
+#define GPL5_1111 0x00000C00
+#define LOOP 0x00000080
+
+#define EXEN 0x00000040
+
+#define AMX_COL 0x00000000
+#define AMX_ROW 0x00000020
+#define AMX_MAR 0x00000030
+
+#define NA 0x00000008
+
+#define UTA 0x00000004
+
+#define TODT 0x00000002
+
+#define LAST 0x00000001
+
+#define A10_AAAA GPL0_AAAA
+#define A10_AAA0 GPL0_AAA0
+#define A10_AAA1 GPL0_AAA1
+#define A10_000A GPL0_000A
+#define A10_0000 GPL0_0000
+#define A10_0001 GPL0_0001
+#define A10_111A GPL0_111A
+#define A10_1110 GPL0_1110
+#define A10_1111 GPL0_1111
+
+#define RAS_0000 GPL1_0000
+#define RAS_0001 GPL1_0001
+#define RAS_1110 GPL1_1110
+#define RAS_1111 GPL1_1111
+
+#define CAS_0000 GPL2_0000
+#define CAS_0001 GPL2_0001
+#define CAS_1110 GPL2_1110
+#define CAS_1111 GPL2_1111
+
+#define WE_0000 GPL3_0000
+#define WE_0001 GPL3_0001
+#define WE_1110 GPL3_1110
+#define WE_1111 GPL3_1111
+
+/* #define CAS_LATENCY 3 */
+#define CAS_LATENCY 2
+
+const uint sdram_table[0x40] = {
+
+#if CAS_LATENCY == 3
+ /* RSS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
+ CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
+ _NOT_USED_, _NOT_USED_,
+
+ /* RBS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* WSS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* WBS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+
+#if CAS_LATENCY == 2
+ /* RSS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
+ CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_,
+
+ /* RBS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
+ CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* WSS */
+ CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
+ CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_,
+ _NOT_USED_,
+
+ /* WBS */
+ CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
+ CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
+ CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
+ CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
+ CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_,
+
+#endif
+
+ /* UPT */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
+ CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_,
+
+ /* EXC */
+ CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
+ _NOT_USED_,
+
+ /* REG */
+ CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
+ CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
+};
+
+static const uint nandcs_table[0x40] = {
+ /* RSS */
+ CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
+ CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
+ CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+ CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+ CS_0000 | GPL4_0000 | GPL5_1111,
+ CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
+ CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+ CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
+
+ /* RBS */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* WSS */
+ CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
+ CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+ CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+ CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+ CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
+ CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+ CS_0000 | GPL4_1111 | GPL5_1111,
+ CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
+
+ /* WBS */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* UPT */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+ /* EXC */
+ CS_0001 | LAST,
+ _NOT_USED_,
+
+ /* REG */
+ CS_1110 ,
+ CS_0001 | LAST,
+};
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
+#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
+
+/* 9 */
+#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+void check_ram(unsigned int addr, unsigned int size)
+{
+ unsigned int i, j, v, vv;
+ volatile unsigned int *p;
+ unsigned int pv;
+
+ p = (unsigned int *)addr;
+ pv = (unsigned int)p;
+ for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
+ *p++ = pv;
+
+ p = (unsigned int *)addr;
+ for (i = 0; i < size / sizeof(unsigned int); i++) {
+ v = (unsigned int)p;
+ vv = *p;
+ if (vv != v) {
+ printf("%p: read %08x instead of %08x\n", p, vv, v);
+ hang();
+ }
+ p++;
+ }
+
+ for (j = 0; j < 5; j++) {
+ switch (j) {
+ case 0: v = 0x00000000; break;
+ case 1: v = 0xffffffff; break;
+ case 2: v = 0x55555555; break;
+ case 3: v = 0xaaaaaaaa; break;
+ default:v = 0xdeadbeef; break;
+ }
+ p = (unsigned int *)addr;
+ for (i = 0; i < size / sizeof(unsigned int); i++) {
+ *p = v;
+ vv = *p;
+ if (vv != v) {
+ printf("%p: read %08x instead of %08x\n", p, vv, v);
+ hang();
+ }
+ *p = ~v;
+ p++;
+ }
+ }
+}
+
+#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0)
+
+long int initdram(int board_type)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size;
+ u32 d1, d2;
+
+ upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
+
+ /*
+ * Preliminary prescaler for refresh
+ */
+ memctl->memc_mptpr = MPTPR_PTP_DIV8;
+
+ memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+ /*
+ * Map controller bank 3 to the SDRAM bank at preliminary address.
+ */
+ memctl->memc_or4 = CFG_OR4_PRELIM;
+ memctl->memc_br4 = CFG_BR4_PRELIM;
+
+ memctl->memc_mamr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */
+
+ udelay(200);
+
+ /* perform SDRAM initialisation sequence */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
+ udelay(1);
+
+ memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
+ udelay(1);
+
+ memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
+ udelay(1);
+
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+
+ udelay(10000);
+
+
+ d1 = 0xAA55AA55;
+ *(volatile u32 *)0 = d1;
+ d2 = *(volatile u32 *)0;
+ if (d1 != d2) {
+ printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+ DO_LOOP;
+ }
+
+ d1 = 0x55AA55AA;
+ *(volatile u32 *)0 = d1;
+ d2 = *(volatile u32 *)0;
+ if (d1 != d2) {
+ printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+ DO_LOOP;
+ }
+
+ d1 = 0x12345678;
+ *(volatile u32 *)0 = d1;
+ d2 = *(volatile u32 *)0;
+ if (d1 != d2) {
+ printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+ DO_LOOP;
+ }
+
+ size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
+
+ return size;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phys(void)
+{
+ int phyno;
+ unsigned short v;
+
+ udelay(10000);
+ /* reset the damn phys */
+ mii_init();
+
+ for (phyno = 0; phyno < 32; ++phyno) {
+ miiphy_read(phyno, PHY_PHYIDR1, &v);
+ if (v == 0xFFFF)
+ continue;
+ miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
+ udelay(10000);
+ miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+ udelay(10000);
+ }
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK _BW(6)
+#define PA_GP_OUTMASK (_BW(7))
+#define PA_SP_MASK 0
+#define PA_ODR_VAL 0
+#define PA_GP_OUTVAL (_BW(7))
+#define PA_SP_DIRVAL 0
+
+#define PB_GP_INMASK 0
+#define PB_GP_OUTMASK (_B(23))
+#define PB_SP_MASK 0
+#define PB_ODR_VAL 0
+#define PB_GP_OUTVAL (_B(23))
+#define PB_SP_DIRVAL 0
+
+#define PC_GP_INMASK 0
+#define PC_GP_OUTMASK (_BW(15))
+
+#define PC_SP_MASK 0
+#define PC_SOVAL 0
+#define PC_INTVAL 0
+#define PC_GP_OUTVAL 0
+#define PC_SP_DIRVAL 0
+
+#define PE_GP_INMASK 0
+#define PE_GP_OUTMASK 0
+#define PE_GP_OUTVAL 0
+
+#define PE_SP_MASK 0
+#define PE_ODR_VAL 0
+#define PE_SP_DIRVAL 0
+
+int board_early_init_f(void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile iop8xx_t *ioport = &immap->im_ioport;
+ volatile cpm8xx_t *cpm = &immap->im_cpm;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ (void)ioport;
+ (void)cpm;
+#if 1
+ /* NAND chip select */
+ upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
+ memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
+ memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB);
+ memctl->memc_mbmr = 0; /* all clear */
+#endif
+
+ memctl->memc_br5 &= ~BR_V;
+ memctl->memc_br6 &= ~BR_V;
+ memctl->memc_br7 &= ~BR_V;
+
+#if 1
+ ioport->iop_padat = PA_GP_OUTVAL;
+ ioport->iop_paodr = PA_ODR_VAL;
+ ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
+ ioport->iop_papar = PA_SP_MASK;
+
+ cpm->cp_pbdat = PB_GP_OUTVAL;
+ cpm->cp_pbodr = PB_ODR_VAL;
+ cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
+ cpm->cp_pbpar = PB_SP_MASK;
+
+ ioport->iop_pcdat = PC_GP_OUTVAL;
+ ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
+ ioport->iop_pcso = PC_SOVAL;
+ ioport->iop_pcint = PC_INTVAL;
+ ioport->iop_pcpar = PC_SP_MASK;
+
+ cpm->cp_pedat = PE_GP_OUTVAL;
+ cpm->cp_peodr = PE_ODR_VAL;
+ cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
+ cpm->cp_pepar = PE_SP_MASK;
+#endif
+
+ return 0;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <linux/mtd/nand.h>
+
+extern ulong nand_probe(ulong physadr);
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+ unsigned long totlen;
+
+ totlen = nand_probe(CFG_NAND_BASE);
+ printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
+
+#ifdef CONFIG_HW_WATCHDOG
+
+void hw_watchdog_reset(void)
+{
+ /* XXX add here the really funky stuff */
+}
+
+#endif
+
+#ifdef CONFIG_SHOW_ACTIVITY
+
+/* called from timer interrupt every 1/CFG_HZ sec */
+void board_show_activity(ulong timestamp)
+{
+}
+
+/* called when looping */
+void show_activity(int arg)
+{
+}
+
+#endif
+
+#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+ /* printf("overwrite_console called\n"); */
+ return 0;
+}
+#endif
+
+extern int drv_phone_init(void);
+extern int drv_phone_use_me(void);
+extern int drv_phone_is_idle(void);
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ reset_phys();
+
+ return 0;
+}
diff --git a/board/stxxtc/u-boot.lds b/board/stxxtc/u-boot.lds
new file mode 100644
index 0000000..c3dac0e
--- /dev/null
+++ b/board/stxxtc/u-boot.lds
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc8xx/start.o (.text)
+ cpu/mpc8xx/traps.o (.text)
+ common/dlmalloc.o (.text)
+ lib_ppc/ppcstring.o (.text)
+ lib_generic/vsprintf.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_generic/zlib.o (.text)
+ lib_ppc/cache.o (.text)
+ lib_ppc/time.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/stxxtc/u-boot.lds.debug b/board/stxxtc/u-boot.lds.debug
new file mode 100644
index 0000000..21b7e6a
--- /dev/null
+++ b/board/stxxtc/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/vsprintf.o (.text)
+ lib_generic/crc32.o (.text)
+
+ . = env_offset;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/voiceblue/Makefile b/board/voiceblue/Makefile
index 44be6ca..6302fa8 100644
--- a/board/voiceblue/Makefile
+++ b/board/voiceblue/Makefile
@@ -32,21 +32,23 @@ SOBJS := setup.o
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds
all: $(LIB) eeprom.srec eeprom.bin
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
-eeprom.srec: eeprom.o
- $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $^ \
+eeprom.srec: eeprom.o eeprom_start.o
+ $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
+ -o $(<:.o=) -e $(<:.o=) $^ \
-L../../examples -lstubs \
-L../../lib_generic -lgeneric \
-L$(gcclibdir) -lgcc
$(OBJCOPY) -O srec $(<:.o=) $@
eeprom.bin: eeprom.srec
- $(OBJCOPY) -O binary $< $@ 2>/dev/null
+ $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
clean:
rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin
diff --git a/board/voiceblue/eeprom.c b/board/voiceblue/eeprom.c
index 6383a02..0ad1b66 100644
--- a/board/voiceblue/eeprom.c
+++ b/board/voiceblue/eeprom.c
@@ -30,40 +30,6 @@
#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
-static int verify_macaddr(char *);
-static int set_mac(char *);
-
-int eeprom(int argc, char *argv[])
-{
- app_startup(argv);
- if (get_version() != XF_VERSION) {
- printf("Wrong XF_VERSION.\n");
- printf("Application expects ABI version %d\n", XF_VERSION);
- printf("Actual U-Boot ABI version %d\n", (int)get_version());
- return 1;
- }
-
- if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
- printf("SMSC91111 not found.\n");
- return 2;
- }
-
- if (argc != 2) {
- printf("VoiceBlue EEPROM writer\n");
- printf("Built: %s at %s\n", __DATE__ , __TIME__ );
- printf("Usage:\n\t<mac_address>");
- return 3;
- }
-
- set_mac(argv[1]);
- if (verify_macaddr(argv[1])) {
- printf("*** ERROR ***\n");
- return 4;
- }
-
- return 0;
-}
-
static u16 read_eeprom_reg(u16 reg)
{
int timeout;
@@ -106,17 +72,28 @@ static int write_eeprom_reg(u16 value, u16 reg)
return 1;
}
+static int write_data(u16 *buf, int len)
+{
+ u16 reg = 0x23;
+
+ while (len--)
+ write_eeprom_reg(*buf++, reg++);
+
+ return 0;
+}
+
static int verify_macaddr(char *s)
{
u16 reg;
int i, err = 0;
- printf("Verifying MAC Address: ");
+ printf("MAC Address: ");
err = i = 0;
for (i = 0; i < 3; i++) {
reg = read_eeprom_reg(0x20 + i);
printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
- err |= reg != ((u16 *)s)[i];
+ if (s)
+ err |= reg != ((u16 *)s)[i];
}
return err ? 0 : 1;
@@ -138,3 +115,97 @@ static int set_mac(char *s)
return 0;
}
+
+static int parse_element(char *s, unsigned char *buf, int len)
+{
+ int cnt;
+ char *p, num[3];
+ unsigned char id;
+
+ id = simple_strtoul(s, &p, 16);
+ if (*p++ != ':')
+ return -1;
+ cnt = 2;
+ num[2] = 0;
+ for (; *p; p += 2) {
+ if (p[1] == 0)
+ return -2;
+ if (cnt + 3 > len)
+ return -3;
+ num[0] = p[0];
+ num[1] = p[1];
+ buf[cnt++] = simple_strtoul(num, NULL, 16);
+ }
+ buf[0] = id;
+ buf[1] = cnt - 2;
+
+ return cnt;
+}
+
+int eeprom(int argc, char *argv[])
+{
+ int i, len, ret;
+ unsigned char buf[58], *p;
+
+ app_startup(argv);
+ if (get_version() != XF_VERSION) {
+ printf("Wrong XF_VERSION.\n");
+ printf("Application expects ABI version %d\n", XF_VERSION);
+ printf("Actual U-Boot ABI version %d\n", (int)get_version());
+ return 1;
+ }
+
+ if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
+ printf("SMSC91111 not found.\n");
+ return 2;
+ }
+
+ /* Called without parameters - print MAC address */
+ if (argc < 2) {
+ verify_macaddr(NULL);
+ return 0;
+ }
+
+ /* Print help message */
+ if (argv[1][1] == 'h') {
+ printf("VoiceBlue EEPROM writer\n");
+ printf("Built: %s at %s\n", __DATE__ , __TIME__ );
+ printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
+ return 0;
+ }
+
+ /* Try to parse information elements */
+ len = sizeof(buf);
+ p = buf;
+ for (i = 2; i < argc; i++) {
+ ret = parse_element(argv[i], p, len);
+ switch (ret) {
+ case -1:
+ printf("Element %d: malformed\n", i - 1);
+ return 3;
+ case -2:
+ printf("Element %d: odd character count\n", i - 1);
+ return 3;
+ case -3:
+ printf("Out of EEPROM memory\n");
+ return 3;
+ default:
+ p += ret;
+ len -= ret;
+ }
+ }
+
+ /* First argument (MAC) is mandatory */
+ set_mac(argv[1]);
+ if (verify_macaddr(argv[1])) {
+ printf("*** MAC address does not match! ***\n");
+ return 4;
+ }
+
+ while (len--)
+ *p++ = 0;
+
+ write_data((u16 *)buf, sizeof(buf) >> 1);
+
+ return 0;
+}
diff --git a/board/voiceblue/eeprom.lds b/board/voiceblue/eeprom.lds
new file mode 100644
index 0000000..317550d
--- /dev/null
+++ b/board/voiceblue/eeprom.lds
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ * (C) Copyright 2005
+ * Ladislav Michl, 2N Telekomunikace, <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = ALIGN(4);
+ .text :
+ {
+ eeprom_start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/board/voiceblue/eeprom_start.S b/board/voiceblue/eeprom_start.S
new file mode 100644
index 0000000..8f88de5
--- /dev/null
+++ b/board/voiceblue/eeprom_start.S
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2005 2N Telekomunikace
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+.globl _start
+_start: b eeprom
diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c
index 16f5b7a..7ab6e9c 100644
--- a/common/cmd_jffs2.c
+++ b/common/cmd_jffs2.c
@@ -1810,7 +1810,7 @@ int do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return !(size > 0);
}
- return 0;
+ return 1;
}
/**
@@ -1846,9 +1846,9 @@ int do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
ret = jffs2_1pass_ls(part, filename);
}
- return (ret == 1);
+ return ret ? 0 : 1;
}
- return 0;
+ return 1;
}
/**
@@ -1884,9 +1884,9 @@ int do_jffs2_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
ret = jffs2_1pass_info(part);
}
- return (ret == 1);
+ return ret ? 0 : 1;
}
- return 0;
+ return 1;
}
/* command line only */
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 4499917..5648ab2 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -225,10 +225,11 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#ifdef CFG_NAND_SKIP_BAD_DOT_I
/* need ".i" same as ".jffs2s" for compatibility with older units (esd) */
/* ".i" for image -> read skips bad block (no 0xff) */
- else if (cmdtail && !strcmp(cmdtail, ".i"))
+ else if (cmdtail && !strcmp(cmdtail, ".i")) {
cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
if (cmd & NANDRW_READ)
cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */
+ }
#endif /* CFG_NAND_SKIP_BAD_DOT_I */
else if (cmdtail) {
printf ("Usage:\n%s\n", cmdtp->usage);
diff --git a/common/hush.c b/common/hush.c
index 47680ed..eb7f7f1 100644
--- a/common/hush.c
+++ b/common/hush.c
@@ -1022,12 +1022,30 @@ static void get_user_input(struct in_str *i)
int n;
static char the_command[CFG_CBSIZE];
+#ifdef CONFIG_BOOT_RETRY_TIME
+# ifdef CONFIG_RESET_TO_RETRY
+ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+# else
+# error "This currently only works with CONFIG_RESET_TO_RETRY enabled"
+# endif
+ reset_cmd_timeout();
+#endif
i->__promptme = 1;
if (i->promptmode == 1) {
n = readline(CFG_PROMPT);
} else {
n = readline(CFG_PROMPT_HUSH_PS2);
}
+#ifdef CONFIG_BOOT_RETRY_TIME
+ if (n == -2) {
+ puts("\nTimeout waiting for command\n");
+# ifdef CONFIG_RESET_TO_RETRY
+ do_reset(NULL, 0, 0, NULL);
+# else
+# error "This currently only works with CONFIG_RESET_TO_RETRY enabled"
+# endif
+ }
+#endif
if (n == -1 ) {
flag_repeat = 0;
i->__promptme = 0;
diff --git a/common/miiphybb.c b/common/miiphybb.c
index b4cbb70..b6af88f 100644
--- a/common/miiphybb.c
+++ b/common/miiphybb.c
@@ -38,72 +38,79 @@
* Utility to send the preamble, address, and register (common to read
* and write).
*/
-static void miiphy_pre(char read,
- unsigned char addr,
- unsigned char reg)
+static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
{
- int j; /* counter */
- volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT);
-
- /*
- * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
- * The IEEE spec says this is a PHY optional requirement. The AMD
- * 79C874 requires one after power up and one after a MII communications
- * error. This means that we are doing more preambles than we need,
- * but it is safer and will be much more robust.
- */
-
- MDIO_ACTIVE;
- MDIO(1);
- for(j = 0; j < 32; j++)
- {
- MDC(0);
- MIIDELAY;
- MDC(1);
- MIIDELAY;
- }
-
- /* send the start bit (01) and the read opcode (10) or write (10) */
- MDC(0); MDIO(0); MIIDELAY; MDC(1); MIIDELAY;
- MDC(0); MDIO(1); MIIDELAY; MDC(1); MIIDELAY;
- MDC(0); MDIO(read); MIIDELAY; MDC(1); MIIDELAY;
- MDC(0); MDIO(!read); MIIDELAY; MDC(1); MIIDELAY;
-
- /* send the PHY address */
- for(j = 0; j < 5; j++)
- {
- MDC(0);
- if((addr & 0x10) == 0)
- {
- MDIO(0);
- }
- else
- {
- MDIO(1);
- }
- MIIDELAY;
- MDC(1);
- MIIDELAY;
- addr <<= 1;
- }
-
- /* send the register address */
- for(j = 0; j < 5; j++)
- {
- MDC(0);
- if((reg & 0x10) == 0)
- {
- MDIO(0);
- }
- else
- {
- MDIO(1);
- }
- MIIDELAY;
- MDC(1);
- MIIDELAY;
- reg <<= 1;
- }
+ int j; /* counter */
+#ifndef CONFIG_EP8248
+ volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
+#endif
+
+ /*
+ * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
+ * The IEEE spec says this is a PHY optional requirement. The AMD
+ * 79C874 requires one after power up and one after a MII communications
+ * error. This means that we are doing more preambles than we need,
+ * but it is safer and will be much more robust.
+ */
+
+ MDIO_ACTIVE;
+ MDIO (1);
+ for (j = 0; j < 32; j++) {
+ MDC (0);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ }
+
+ /* send the start bit (01) and the read opcode (10) or write (10) */
+ MDC (0);
+ MDIO (0);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ MDC (0);
+ MDIO (1);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ MDC (0);
+ MDIO (read);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ MDC (0);
+ MDIO (!read);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+
+ /* send the PHY address */
+ for (j = 0; j < 5; j++) {
+ MDC (0);
+ if ((addr & 0x10) == 0) {
+ MDIO (0);
+ } else {
+ MDIO (1);
+ }
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ addr <<= 1;
+ }
+
+ /* send the register address */
+ for (j = 0; j < 5; j++) {
+ MDC (0);
+ if ((reg & 0x10) == 0) {
+ MDIO (0);
+ } else {
+ MDIO (1);
+ }
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ reg <<= 1;
+ }
}
@@ -114,66 +121,63 @@ static void miiphy_pre(char read,
* Returns:
* 0 on success
*/
-int miiphy_read(unsigned char addr,
- unsigned char reg,
- unsigned short *value)
+int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
{
- short rdreg; /* register working value */
- int j; /* counter */
- volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT);
-
- miiphy_pre(1, addr, reg);
-
- /* tri-state our MDIO I/O pin so we can read */
- MDC(0);
- MDIO_TRISTATE;
- MIIDELAY;
- MDC(1);
- MIIDELAY;
-
- /* check the turnaround bit: the PHY should be driving it to zero */
- if(MDIO_READ != 0)
- {
- /* puts ("PHY didn't drive TA low\n"); */
- for(j = 0; j < 32; j++)
- {
- MDC(0);
- MIIDELAY;
- MDC(1);
- MIIDELAY;
- }
- return(-1);
- }
-
- MDC(0);
- MIIDELAY;
-
- /* read 16 bits of register data, MSB first */
- rdreg = 0;
- for(j = 0; j < 16; j++)
- {
- MDC(1);
- MIIDELAY;
- rdreg <<= 1;
- rdreg |= MDIO_READ;
- MDC(0);
- MIIDELAY;
- }
-
- MDC(1);
- MIIDELAY;
- MDC(0);
- MIIDELAY;
- MDC(1);
- MIIDELAY;
-
- *value = rdreg;
+ short rdreg; /* register working value */
+ int j; /* counter */
+#ifndef CONFIG_EP8248
+ volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
+#endif
+
+ miiphy_pre (1, addr, reg);
+
+ /* tri-state our MDIO I/O pin so we can read */
+ MDC (0);
+ MDIO_TRISTATE;
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+
+ /* check the turnaround bit: the PHY should be driving it to zero */
+ if (MDIO_READ != 0) {
+ /* puts ("PHY didn't drive TA low\n"); */
+ for (j = 0; j < 32; j++) {
+ MDC (0);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ }
+ return (-1);
+ }
+
+ MDC (0);
+ MIIDELAY;
+
+ /* read 16 bits of register data, MSB first */
+ rdreg = 0;
+ for (j = 0; j < 16; j++) {
+ MDC (1);
+ MIIDELAY;
+ rdreg <<= 1;
+ rdreg |= MDIO_READ;
+ MDC (0);
+ MIIDELAY;
+ }
+
+ MDC (1);
+ MIIDELAY;
+ MDC (0);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+
+ *value = rdreg;
#ifdef DEBUG
- printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
+ printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
#endif
- return 0;
+ return 0;
}
@@ -184,47 +188,51 @@ int miiphy_read(unsigned char addr,
* Returns:
* 0 on success
*/
-int miiphy_write(unsigned char addr,
- unsigned char reg,
- unsigned short value)
+int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
{
- int j; /* counter */
- volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT);
-
- miiphy_pre(0, addr, reg);
-
- /* send the turnaround (10) */
- MDC(0); MDIO(1); MIIDELAY; MDC(1); MIIDELAY;
- MDC(0); MDIO(0); MIIDELAY; MDC(1); MIIDELAY;
-
- /* write 16 bits of register data, MSB first */
- for(j = 0; j < 16; j++)
- {
- MDC(0);
- if((value & 0x00008000) == 0)
- {
- MDIO(0);
- }
- else
- {
- MDIO(1);
- }
- MIIDELAY;
- MDC(1);
- MIIDELAY;
- value <<= 1;
- }
-
- /*
- * Tri-state the MDIO line.
- */
- MDIO_TRISTATE;
- MDC(0);
- MIIDELAY;
- MDC(1);
- MIIDELAY;
-
- return 0;
+ int j; /* counter */
+#ifndef CONFIG_EP8248
+ volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
+#endif
+
+ miiphy_pre (0, addr, reg);
+
+ /* send the turnaround (10) */
+ MDC (0);
+ MDIO (1);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ MDC (0);
+ MDIO (0);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+
+ /* write 16 bits of register data, MSB first */
+ for (j = 0; j < 16; j++) {
+ MDC (0);
+ if ((value & 0x00008000) == 0) {
+ MDIO (0);
+ } else {
+ MDIO (1);
+ }
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+ value <<= 1;
+ }
+
+ /*
+ * Tri-state the MDIO line.
+ */
+ MDIO_TRISTATE;
+ MDC (0);
+ MIIDELAY;
+ MDC (1);
+ MIIDELAY;
+
+ return 0;
}
#endif /* CONFIG_BITBANGMII */
diff --git a/common/miiphyutil.c b/common/miiphyutil.c
index 2b0dcf4..13b9c65 100644
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -93,7 +93,13 @@ int miiphy_reset (unsigned char addr)
unsigned short reg;
int loop_cnt;
- if (miiphy_write (addr, PHY_BMCR, 0x8000) != 0) {
+ if (miiphy_read (addr, PHY_BMCR, &reg) != 0) {
+#ifdef DEBUG
+ printf ("PHY status read failed\n");
+#endif
+ return (-1);
+ }
+ if (miiphy_write (addr, PHY_BMCR, reg | 0x8000) != 0) {
#ifdef DEBUG
puts ("PHY reset failed\n");
#endif
diff --git a/cpu/arm920t/at91rm9200/serial.c b/cpu/arm920t/at91rm9200/serial.c
index b529cfa..a281932 100644
--- a/cpu/arm920t/at91rm9200/serial.c
+++ b/cpu/arm920t/at91rm9200/serial.c
@@ -56,7 +56,7 @@ void serial_setbrg (void)
if ((baudrate = gd->baudrate) <= 0)
baudrate = CONFIG_BAUDRATE;
/* MASTER_CLOCK/(16 * baudrate) */
- us->US_BRGR = (AT91C_MASTER_CLOCK >> 4)/baudrate;
+ us->US_BRGR = (AT91C_MASTER_CLOCK >> 4) / (unsigned)baudrate;
}
int serial_init (void)
diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk
index 3c9aab8..fd10747 100644
--- a/cpu/mips/config.mk
+++ b/cpu/mips/config.mk
@@ -24,9 +24,17 @@ v=$(shell \
mips-linux-as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}')
MIPSFLAGS=$(shell \
if [ "$v" -lt "14" ]; then \
- echo "-mcpu=4kc -EB -mabicalls"; \
+ echo "-mcpu=4kc"; \
else \
- echo "-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined -EB -mabicalls"; \
+ echo "-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined"; \
fi)
+ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
+ENDIANNESS = -EL
+else
+ENDIANNESS = -EB
+endif
+
+MIPSFLAGS += $(ENDIANNESS) -mabicalls
+
PLATFORM_CPPFLAGS += $(MIPSFLAGS)
diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c
index 95003ed..f038316 100644
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -25,7 +25,7 @@
#include <mpc8xx.h>
#include <asm/processor.h>
-#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK)
+#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK) || defined(DEBUG)
#define PITC_SHIFT 16
#define PITR_SHIFT 16
diff --git a/cpu/ppc4xx/440gx_enet.c b/cpu/ppc4xx/440gx_enet.c
index 68cbf34..d0b6c15 100644
--- a/cpu/ppc4xx/440gx_enet.c
+++ b/cpu/ppc4xx/440gx_enet.c
@@ -269,7 +269,7 @@ int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis)
static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
{
- int i;
+ int i, j;
unsigned long reg;
unsigned long msr;
unsigned long speed;
@@ -448,7 +448,11 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
* for RGMII mode.
*/
if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
- miiphy_write (reg, 23, 0x1200);
+#if defined(CONFIG_CIS8201_SHORT_ETCH)
+ miiphy_write (reg, 23, 0x1300);
+#else
+ miiphy_write (reg, 23, 0x1000);
+#endif
/*
* Vitesse VSC8201/Cicada CIS8201 errata:
* Interoperability problem with Intel 82547EI phys
@@ -567,6 +571,8 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
hw_p->alloc_tx_buf =
(mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
((2 * CFG_CACHELINE_SIZE) - 2));
+ if (NULL == hw_p->alloc_tx_buf)
+ return -1;
if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
hw_p->tx =
(mal_desc_t *) ((int) hw_p->alloc_tx_buf +
@@ -580,6 +586,12 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
hw_p->alloc_rx_buf =
(mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
((2 * CFG_CACHELINE_SIZE) - 2));
+ if (NULL == hw_p->alloc_rx_buf) {
+ free(hw_p->alloc_tx_buf);
+ hw_p->alloc_tx_buf = NULL;
+ return -1;
+ }
+
if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
hw_p->rx =
(mal_desc_t *) ((int) hw_p->alloc_rx_buf +
@@ -593,9 +605,20 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
for (i = 0; i < NUM_TX_BUFF; i++) {
hw_p->tx[i].ctrl = 0;
hw_p->tx[i].data_len = 0;
- if (hw_p->first_init == 0)
+ if (hw_p->first_init == 0) {
hw_p->txbuf_ptr =
(char *) malloc (ENET_MAX_MTU_ALIGNED);
+ if (NULL == hw_p->txbuf_ptr) {
+ free(hw_p->alloc_rx_buf);
+ free(hw_p->alloc_tx_buf);
+ hw_p->alloc_rx_buf = NULL;
+ hw_p->alloc_tx_buf = NULL;
+ for(j = 0; j < i; j++) {
+ free(hw_p->tx[i].data_ptr);
+ hw_p->tx[i].data_ptr = NULL;
+ }
+ }
+ }
hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
if ((NUM_TX_BUFF - 1) == i)
hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
diff --git a/doc/README.stxxtc b/doc/README.stxxtc
new file mode 100644
index 0000000..7d9d4d3
--- /dev/null
+++ b/doc/README.stxxtc
@@ -0,0 +1,59 @@
+
+
+First, some build notes on the Silicon Turnkey eXpress XTc.
+
+This board has both 87x/88x procesor options at various
+frequencies. The configuration file has some macros for setting
+the clock speed, not all have been tested. They all have
+a 10MHz input clock. Please do not check in a configuration
+file that selects a high speed not available on all processors.
+We chose the 66MHz core and bus speed, which should be OK on
+all boards. If you have a processor, lucky you! :-)
+Just build a new configuration with that speed, check
+the macro configuration to ensure it's correct. If the
+macro is updated, please check that in, but keep default
+processor speed.
+
+The board is likely to have more than 1Mbyte of NOR boot flash.
+It was also configured with a high boot vector (Dan's fault)
+so the standard 8xx mapping doesn't work well. We had to move
+the addresses around a little bit so one copy would work. The
+flash got fragmented, and we are working on a better solution.
+There is an "xtc.cfg" floating around for the BDI2000, use
+that for programming a new version of U-Boot. You can probably
+find it on the Silicon Turnkey eXpress (www.silicontkx.com),
+Embedded Alley Solutions (embeddedalley.com), or Denx (denx.de)
+servers.
+
+The board will also have various SDRAM sizes, but the code
+should automatically determine the amount of memory.
+
+There are a couple of different board versions, visually
+they use different BGA or surface mount memory parts. However,
+they are logically the same board.
+
+Now, some operational notes.
+
+The board has the option of sporting two FEC Ethernet ports.
+The second port isn't configured to be automatically available
+because it would cause U-Boot to generate a board data structure
+(the bd_t) with multiple MAC addresses and be incompatible with
+standard 8xx kernel builds. You can use/test the second FEC
+in U-Boot by assigning an 'eth1addr' and selecting the second
+FEC as the port to use.
+
+Since this is just a development board and not a product, STx
+does not assign unique MAC addresses. We just pilfer the
+"default" ones used by Wolfgang on some other boards. Please
+ensure you assign unique MAC addresses when using these boards.
+
+The serial port baud rate is 38400, because that's the way
+I like it :-)
+
+Thanks to Pantelis for lots of the work on this board port.
+
+Have Fun!
+
+ -- Dan
+
+15 August 2005
diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c
index d8489d46..3d0f204 100644
--- a/drivers/cfi_flash.c
+++ b/drivers/cfi_flash.c
@@ -557,7 +557,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
i = buffered_size > cnt ? cnt : buffered_size;
if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
return rc;
- i -= (i % info->portwidth);
+ i -= i & (info->portwidth - 1);
wp += i;
src += i;
cnt -= i;
@@ -805,7 +805,7 @@ static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
uchar *cp = (uchar *) cmdbuf;
for (i = 0; i < info->portwidth; i++)
- *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
+ *cp++ = ((i + 1) & (info->chipwidth - 1)) ? '\0' : cmd;
#if defined(__LITTLE_ENDIAN)
switch (info->portwidth) {
case FLASH_CFI_8BIT:
diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index 667ae15..e53aa31 100644
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -1288,7 +1288,7 @@ u32
jffs2_1pass_ls(struct part_info * part, const char *fname)
{
struct b_lists *pl;
- long ret = 0;
+ long ret = 1;
u32 inode;
if (! (pl = jffs2_get_list(part, "ls")))
@@ -1315,7 +1315,7 @@ jffs2_1pass_load(char *dest, struct part_info * part, const char *fname)
{
struct b_lists *pl;
- long ret = 0;
+ long ret = 1;
u32 inode;
if (! (pl = jffs2_get_list(part, "load")))
diff --git a/include/common.h b/include/common.h
index efc638d..8536a99 100644
--- a/include/common.h
+++ b/include/common.h
@@ -302,7 +302,8 @@ void board_ether_init (void);
#endif
#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || \
- defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K)
+ defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K) || \
+ defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
void board_get_enetaddr (uchar *addr);
#endif
diff --git a/include/configs/DU405.h b/include/configs/DU405.h
index b917092..a251298 100644
--- a/include/configs/DU405.h
+++ b/include/configs/DU405.h
@@ -32,12 +32,14 @@
* High Level Configuration Options
* (easy to change)
*/
+#define CONFIG_IDENT_STRING " $Name: $"
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_DU405 1 /* ...on a DU405 board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h
new file mode 100644
index 0000000..331131a
--- /dev/null
+++ b/include/configs/KAREF.h
@@ -0,0 +1,309 @@
+/*
+ * (C) Copyright 2004 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
+ * design.
+ ***********************************************************************/
+
+/*
+ * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
+#define CONFIG_440GX 1 /* Specifc GX support */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
+#undef CFG_DRAM_TEST /* Disable-takes long time!*/
+#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
+
+#define CONFIG_VERY_BIG_RAM 1
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
+#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
+#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+#define CFG_KAREF_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000)
+#define CFG_OFEM_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08400000)
+#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000)
+#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700)
+
+/* Here for completeness */
+#define CFG_OFEMAC_BASE (CFG_PERIPHERAL_BASE + 0x08600000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM 1
+#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_BAUDRATE 9600
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
+#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 8 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
+#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C hardware support */
+#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */
+#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
+
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
+#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
+#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
+#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
+
+#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */
+#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR)
+
+#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*-----------------------------------------------------------------------
+ * Networking
+ *----------------------------------------------------------------------*/
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
+#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
+#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
+#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
+#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
+#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
+#define CONFIG_PHY_RESET_DELAY 1000
+#define CONFIG_NETMASK 255.255.0.0
+#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
+#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
+#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
+
+
+/*-----------------------------------------------------------------------
+ * Console/Commands/Parser
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_PCI | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_I2C | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DATE | \
+ CFG_CMD_BEDBUG | \
+ CFG_CMD_PING | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_ELF | \
+ CFG_CMD_IDE | \
+ CFG_CMD_FAT)
+
+/* Include NetConsole support */
+#define CONFIG_NETCONSOLE
+
+/* Include auto complete with tabs */
+#define CONFIG_AUTO_COMPLETE 1
+#define CFG_AUTO_COMPLETE 1
+#define CFG_ALT_MEMTEST 1 /* use real memory test */
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
+
+#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+
+/*-----------------------------------------------------------------------
+ * Console Buffer
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+ /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of cmd args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */
+
+/*-----------------------------------------------------------------------
+ * Memory Test
+ *----------------------------------------------------------------------*/
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+/*-----------------------------------------------------------------------
+ * Compact Flash (in true IDE mode)
+ *----------------------------------------------------------------------*/
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
+#undef CONFIG_IDE_LED /* no led for ide supported */
+
+#define CONFIG_IDE_RESET /* reset for ide supported */
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR 0xF0000000
+#define CFG_ATA_IDE0_OFFSET 0x0000
+#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
+#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
+
+#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride
+ to get to the correct offset */
+#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
+
+/*-----------------------------------------------------------------------
+ * PCI
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
+#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
+#define CFG_PCI_TARGET_INIT /* let board init pci target*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
+#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CFG_LOAD_ADDR 0x8000000 /* default load address */
+#define CFG_EXTBDINFO 1 /* use extended board_info */
+
+#define CFG_HZ 100 /* decr freq: 1 ms ticks */
+
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h
new file mode 100644
index 0000000..2b4a33f
--- /dev/null
+++ b/include/configs/METROBOX.h
@@ -0,0 +1,377 @@
+/*
+ * (C) Copyright 2004 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * METROBOX.h - configuration Sandburst MetroBox
+ ***********************************************************************/
+
+/*
+ * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $
+ *
+ *
+ * $Log: METROBOX.h,v $
+ * Revision 1.21 2005/06/03 15:05:25 tsawyer
+ * MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB
+ *
+ * Revision 1.20 2005/04/11 20:51:11 tsawyer
+ * fix ethernet
+ *
+ * Revision 1.19 2005/04/06 15:13:36 tsawyer
+ * Update appropriate files to coincide with u-boot 1.1.3
+ *
+ * Revision 1.18 2005/03/10 14:16:02 tsawyer
+ * add def'n for cis8201 short etch option.
+ *
+ * Revision 1.17 2005/03/09 19:49:51 tsawyer
+ * Remove KGDB to allow use of 2nd serial port
+ *
+ * Revision 1.16 2004/12/02 19:00:23 tsawyer
+ * Add misc_init_f to turn on i2c-1 and all four fans before sdram init
+ *
+ * Revision 1.15 2004/09/15 18:04:12 tsawyer
+ * add multiple serial port support
+ *
+ * Revision 1.14 2004/09/03 15:27:51 tsawyer
+ * All metrobox boards are at 66.66 sys clock
+ *
+ * Revision 1.13 2004/08/05 20:27:46 tsawyer
+ * Remove system ace definitions, add net console support
+ *
+ * Revision 1.12 2004/07/29 20:00:13 tsawyer
+ * Add i2c bus 1
+ *
+ * Revision 1.11 2004/07/21 13:44:18 tsawyer
+ * SystemACE is out, CF direct to local bus is in
+ *
+ * Revision 1.10 2004/06/29 19:08:55 tsawyer
+ * Add CONFIG_MISC_INIT_R
+ *
+ * Revision 1.9 2004/06/28 21:30:53 tsawyer
+ * Fix default BOOTARGS
+ *
+ * Revision 1.8 2004/06/17 15:51:08 tsawyer
+ * auto complete
+ *
+ * Revision 1.7 2004/06/17 15:08:49 tsawyer
+ * Add autocomplete
+ *
+ * Revision 1.6 2004/06/15 12:33:57 tsawyer
+ * debugging checkpoint
+ *
+ * Revision 1.5 2004/06/12 19:48:28 tsawyer
+ * Debugging checkpoint
+ *
+ * Revision 1.4 2004/06/02 13:03:06 tsawyer
+ * Fix eth addrs
+ *
+ * Revision 1.3 2004/05/18 19:56:10 tsawyer
+ * Change default bootcommand to pImage.metrobox
+ *
+ * Revision 1.2 2004/05/18 14:13:44 tsawyer
+ * Add bringup values for bootargs and bootcommand.
+ * Remove definition of ipaddress and serverip addresses.
+ *
+ * Revision 1.1 2004/04/16 15:08:54 tsawyer
+ * Initial Revision
+ *
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_METROBOX 1 /* Board is Metrobox */
+#define CONFIG_440GX 1 /* Specifc GX support */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
+#undef CFG_DRAM_TEST /* Disable-takes long time!*/
+#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
+
+#define CONFIG_VERY_BIG_RAM 1
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_IDENT_STRING " Sandburst Metrobox"
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
+#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
+#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000)
+#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000)
+#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM 1
+#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_BAUDRATE 9600
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
+#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 8 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
+#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C hardware support */
+#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */
+#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
+
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
+#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
+#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
+#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
+
+#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */
+#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR)
+
+#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none "
+#define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000"
+#define CONFIG_BOOTDELAY 5 /* disable autoboot */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*-----------------------------------------------------------------------
+ * Networking
+ *----------------------------------------------------------------------*/
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
+#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
+#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
+#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
+#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
+#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
+#define CONFIG_PHY_RESET_DELAY 1000
+#define CONFIG_NETMASK 255.255.0.0
+#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
+#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
+#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
+
+
+/*-----------------------------------------------------------------------
+ * Console/Commands/Parser
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_PCI | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_I2C | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DATE | \
+ CFG_CMD_BEDBUG | \
+ CFG_CMD_PING | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_ELF | \
+ CFG_CMD_IDE | \
+ CFG_CMD_FAT)
+
+/* tbs 09-March-2005 Removed to be able to use 2nd serial */
+/* CFG_CMD_KGDB | \ */
+
+
+/* Include NetConsole support */
+#define CONFIG_NETCONSOLE
+
+/* Include auto complete with tabs */
+#define CONFIG_AUTO_COMPLETE 1
+#define CFG_AUTO_COMPLETE 1
+#define CFG_ALT_MEMTEST 1 /* use real memory test */
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "MetroBox=> " /* Monitor Command Prompt */
+
+#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+
+/*-----------------------------------------------------------------------
+ * Console Buffer
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+ /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of cmd args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */
+
+/*-----------------------------------------------------------------------
+ * Memory Test
+ *----------------------------------------------------------------------*/
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+/*-----------------------------------------------------------------------
+ * Compact Flash (in true IDE mode)
+ *----------------------------------------------------------------------*/
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
+#undef CONFIG_IDE_LED /* no led for ide supported */
+
+#define CONFIG_IDE_RESET /* reset for ide supported */
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR 0xF0000000
+#define CFG_ATA_IDE0_OFFSET 0x0000
+#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
+#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
+
+#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride
+ to get to the correct offset */
+#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
+
+/*-----------------------------------------------------------------------
+ * PCI
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
+#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
+#define CFG_PCI_TARGET_INIT /* let board init pci target*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
+#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CFG_LOAD_ADDR 0x8000000 /* default load address */
+#define CFG_EXTBDINFO 1 /* use extended board_info */
+
+#define CFG_HZ 100 /* decr freq: 1 ms ticks */
+
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 0af9c68..6c2f17d 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -128,7 +128,7 @@
#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
#define CONFIG_BOOTDELAY 5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
+/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 2671125..469d88f 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -32,6 +32,7 @@
* High Level Configuration Options
* (easy to change)
*/
+#define CONFIG_IDENT_STRING " $Name: esd_PCI405_05_07_28 $"
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index dbec242..9ac5715 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -112,7 +112,7 @@
#define CONFIG_BOOTDELAY 5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
+/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index bde12e1..3f29190 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -138,7 +138,7 @@
#define CONFIG_BOOTDELAY 5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
+/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
#define CONFIG_NETMASK 255.255.255.0
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index b4dfdf4..5c9950f 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -32,6 +32,7 @@
* High Level Configuration Options
* (easy to change)
*/
+#define CONFIG_IDENT_STRING " $Name: $"
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index 7f9fea5..9da15ed 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -65,6 +65,7 @@
CFG_CMD_I2C | \
CFG_CMD_IDE | \
CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
CFG_CMD_SNTP)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -307,4 +308,21 @@
#define CONFIG_ATAPI 1
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+#define CONFIG_PCI_SCAN_SHOW 1
+
+#define CONFIG_PCI_MEM_BUS 0x40000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x50000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x01000000
+
#endif /* __CONFIG_H */
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
new file mode 100644
index 0000000..a0e1ba7
--- /dev/null
+++ b/include/configs/stxxtc.h
@@ -0,0 +1,592 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
+ * U-Boot port on STx XTc 8xx board
+ * Mostly copied from Panto's NETTA2 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC875 1 /* This is a MPC875 CPU */
+#define CONFIG_STXXTC 1 /* ...on a STx XTc board */
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
+
+#define CONFIG_XIN 10000000 /* 10 MHz input xtal */
+
+/* Select one of few clock rates defined later in this file.
+*/
+/* #define MPC8XX_HZ 50000000 */
+#define MPC8XX_HZ 66666666
+
+#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+ "tftpboot; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "bootm"
+
+#define CONFIG_AUTOSCRIPT
+#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
+#define FEC_ENET 1 /* eth.c needs it that way... */
+#undef CFG_DISCOVER_PHY
+#define CONFIG_MII 1
+#undef CONFIG_RMII
+
+#define CONFIG_ETHER_ON_FEC1 1
+#define CONFIG_FEC1_PHY 1 /* phy address of FEC */
+#undef CONFIG_FEC1_PHY_NORXERR
+
+#define CONFIG_ETHER_ON_FEC2 1
+#define CONFIG_FEC2_PHY 3
+#undef CONFIG_FEC2_PHY_NORXERR
+
+#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_NAND | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_PING | \
+ CFG_CMD_MII | \
+ CFG_CMD_NFS)
+
+#define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_MISC_INIT_R
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "xtc> " /* Monitor Command Prompt */
+
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0300000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x40000000
+#if defined(DEBUG)
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#else
+#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
+#endif
+
+/* yes this is weird, I know :) */
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE | 0x00F00000)
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+#define CFG_RESET_ADDRESS 0x80000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SECT_SIZE 0x10000
+
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000)
+#define CFG_ENV_OFFSET 0
+#define CFG_ENV_SIZE 0x4000
+
+#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x00010000)
+#define CFG_ENV_OFFSET_REDUND 0
+#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
+
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + 0x2000000 }
+
+#define CFG_FLASH_PROTECTION
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+#if CONFIG_XIN == 10000000
+
+#if MPC8XX_HZ == 50000000
+#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+ (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+ PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 66666666
+#define CFG_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
+ (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+ PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 10MHz
+#endif
+#else
+#error unsupported freq for XIN (must be 10MHz)
+#endif
+
+
+/*
+ *-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ *
+ * Note: When TBS == 0 the timebase is independent of current cpu clock.
+ */
+
+#define SCCR_MASK SCCR_EBDF11
+#if MPC8XX_HZ > 66666666
+#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00 | SCCR_EBDF01)
+#else
+#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define CFG_DER 0x2002000F*/
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+
+#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */
+
+#define CFG_REMAP_OR_AM 0x80000000
+#define CFG_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+#define CFG_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CFG_OR_TIMING_FLASH)
+#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/*
+ * BR4 and OR4 (SDRAM)
+ *
+ */
+#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
+#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
+#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
+
+#define CFG_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
+#define CFG_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ * gclk CPU clock (not bus clock!)
+ * Trefresh Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096 Rows from SDRAM example configuration
+ * 1000 factor s -> ms
+ * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4 Number of refresh cycles per period
+ * 64 Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider = 98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_MAMR_PTA 234
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
+ * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
+
+/****************************************************************/
+
+#define NAND_SIZE 0x00010000 /* 64K */
+#define NAND_BASE 0xF1000000
+
+/****************************************************************/
+
+/* NAND */
+#define CFG_NAND_BASE NAND_BASE
+#define CONFIG_MTD_NAND_ECC_JFFS2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_MTD_NAND_UNSAFE
+
+#define CFG_MAX_NAND_DEVICE 1
+#undef NAND_NO_RB
+
+#define SECTORSIZE 512
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
+#define NAND_DISABLE_CE(nand) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \
+ } while(0)
+
+#define NAND_ENABLE_CE(nand) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
+ } while(0)
+
+#define NAND_CTL_CLRALE(nandptr) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
+ } while(0)
+
+#define NAND_CTL_SETALE(nandptr) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \
+ } while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
+ } while(0)
+
+#define NAND_CTL_SETCLE(nandptr) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \
+ } while(0)
+
+#ifndef NAND_NO_RB
+#define NAND_WAIT_READY(nand) \
+ do { \
+ int _tries = 0; \
+ while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
+ if (++_tries > 100000) \
+ break; \
+ } while (0)
+#else
+#define NAND_WAIT_READY(nand) udelay(12)
+#endif
+
+#define WRITE_NAND_COMMAND(d, adr) \
+ do { \
+ *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+ } while(0)
+
+#define WRITE_NAND_ADDRESS(d, adr) \
+ do { \
+ *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+ } while(0)
+
+#define WRITE_NAND(d, adr) \
+ do { \
+ *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+ } while(0)
+
+#define READ_NAND(adr) \
+ ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
+
+/*****************************************************************************/
+
+#define CFG_DIRECT_FLASH_TFTP
+#define CFG_DIRECT_NAND_TFTP
+
+/*****************************************************************************/
+
+/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
+ * CxOE and CxRESET. We use the CxOE.
+ */
+#define STATUS_LED_BIT 0x00000080 /* bit 24 */
+
+#define STATUS_LED_PERIOD (CFG_HZ / 2)
+#define STATUS_LED_STATE STATUS_LED_BLINKING
+
+#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
+#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
+#ifndef __ASSEMBLY__
+
+/* LEDs */
+
+/* led_id_t is unsigned int mask */
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+ do { \
+ ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
+ } while(0)
+
+#define __led_set(_msk, _st) \
+ do { \
+ if ((_st)) \
+ ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
+ else \
+ ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
+ } while(0)
+
+#define __led_init(msk, st) __led_set(msk, st)
+
+#endif
+
+/******************************************************************************/
+
+#define CFG_CONSOLE_IS_IN_ENV 1
+#define CFG_CONSOLE_OVERWRITE_ROUTINE 1
+#define CFG_CONSOLE_ENV_OVERWRITE 1
+
+/******************************************************************************/
+
+/* use board specific hardware */
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_SHOW_ACTIVITY
+
+/*****************************************************************************/
+
+#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_CRC32_VERIFY 1
+#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
+
+/* Note: change below for your network setting!!!
+ * This was done just to facilitate manufacturing test and configuration.
+ */
+#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
+
+#define CONFIG_SERVERIP 192.168.08.1
+#define CONFIG_IPADDR 192.168.08.85
+#define CONFIG_GATEWAYIP 192.168.08.1
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_HOSTNAME stx_xtc
+#define CONFIG_ROOTPATH /xtcroot
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_LOADADDR 0x1000000
+
+
+#endif /* __CONFIG_H */
diff --git a/include/ppc440.h b/include/ppc440.h
index 02f0a2e..a5024e6 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -842,7 +842,7 @@
#define EBC_BXCR_BW_MASK 0x00006000
#define EBC_BXCR_BW_8BIT 0x00000000
#define EBC_BXCR_BW_16BIT 0x00002000
-
+#define EBC_BXCR_BW_32BIT 0x00006000
#define EBC_BXAP_BME_ENABLED 0x80000000
#define EBC_BXAP_BME_DISABLED 0x00000000
#define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23)
diff --git a/include/status_led.h b/include/status_led.h
index b80780a..a56883b 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -336,6 +336,9 @@ void status_led_set (int led, int state);
/***** NetPhone ********************************************************/
#elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
/* XXX empty just to avoid the error */
+/***** STx XTc ********************************************************/
+#elif defined(CONFIG_STXXTC)
+/* XXX empty just to avoid the error */
/***** sbc8240 ********************************************************/
#elif defined(CONFIG_WRSBC8240)
/* XXX empty just to avoid the error */
diff --git a/include/version.h b/include/version.h
index 2b9b617..4f8b498 100644
--- a/include/version.h
+++ b/include/version.h
@@ -24,6 +24,6 @@
#ifndef __VERSION_H__
#define __VERSION_H__
-#define U_BOOT_VERSION "U-Boot 1.1.3"
+#define U_BOOT_VERSION "U-Boot 1.1.4"
#endif /* __VERSION_H__ */
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 09c4f64..dab268e 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -828,7 +828,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
/* handle the 3rd ethernet address */
s = getenv ("eth2addr");
-#if defined(CONFIG_XPEDITE1K)
+#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
if (s == NULL)
board_get_enetaddr(bd->bi_enet2addr);
else
@@ -843,7 +843,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
#ifdef CONFIG_HAS_ETH3
/* handle 4th ethernet address */
s = getenv("eth3addr");
-#if defined(CONFIG_XPEDITE1K)
+#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
if (s == NULL)
board_get_enetaddr(bd->bi_enet3addr);
else
diff --git a/net/net.c b/net/net.c
index 5b06495..00217be 100644
--- a/net/net.c
+++ b/net/net.c
@@ -40,10 +40,10 @@
*
* DHCP:
*
- * Prerequisites: - own ethernet address
- * We want: - IP, Netmask, ServerIP, Gateway IP
- * - bootfilename, lease time
- * Next step: - TFTP
+ * Prerequisites: - own ethernet address
+ * We want: - IP, Netmask, ServerIP, Gateway IP
+ * - bootfilename, lease time
+ * Next step: - TFTP
*
* TFTP:
*
@@ -67,7 +67,7 @@
*
* SNTP:
*
- * Prerequisites: - own ethernet address
+ * Prerequisites: - own ethernet address
* - own IP address
* We want: - network time
* Next step: none
@@ -185,7 +185,7 @@ static int net_check_prereq (proto_t protocol);
IPaddr_t NetArpWaitPacketIP;
IPaddr_t NetArpWaitReplyIP;
uchar *NetArpWaitPacketMAC; /* MAC address of waiting packet's destination */
-uchar *NetArpWaitTxPacket; /* THE transmit packet */
+uchar *NetArpWaitTxPacket; /* THE transmit packet */
int NetArpWaitTxPacketSize;
uchar NetArpWaitPacketBuf[PKTSIZE_ALIGN + PKTALIGN];
ulong NetArpWaitTimerStart;
@@ -212,8 +212,8 @@ void ArpRequest (void)
arp->ar_pln = 4;
arp->ar_op = htons (ARPOP_REQUEST);
- memcpy (&arp->ar_data[0], NetOurEther, 6); /* source ET addr */
- NetWriteIP ((uchar *) & arp->ar_data[6], NetOurIP); /* source IP addr */
+ memcpy (&arp->ar_data[0], NetOurEther, 6); /* source ET addr */
+ NetWriteIP ((uchar *) & arp->ar_data[6], NetOurIP); /* source IP addr */
for (i = 10; i < 16; ++i) {
arp->ar_data[i] = 0; /* dest ET addr = 0 */
}
@@ -372,11 +372,11 @@ restart:
*/
NetOurIP = 0;
NetServerIP = getenv_IPaddr ("serverip");
- NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */
- NetOurNativeVLAN = getenv_VLAN("nvlan");
- case CDP:
- NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */
- NetOurNativeVLAN = getenv_VLAN("nvlan");
+ NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */
+ NetOurNativeVLAN = getenv_VLAN("nvlan");
+ case CDP:
+ NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */
+ NetOurNativeVLAN = getenv_VLAN("nvlan");
break;
default:
break;
@@ -1410,7 +1410,7 @@ NetReceive(volatile uchar * inpkt, int len)
puts (" ICMP Host Redirect to ");
print_IPaddr(icmph->un.gateway);
putc(' ');
- break;
+ return;
#if (CONFIG_COMMANDS & CFG_CMD_PING)
case ICMP_ECHO_REPLY:
/*
@@ -1418,7 +1418,7 @@ NetReceive(volatile uchar * inpkt, int len)
*/
/* XXX point to ip packet */
(*packetHandler)((uchar *)ip, 0, 0, 0);
- break;
+ return;
#endif
default:
return;
@@ -1427,6 +1427,46 @@ NetReceive(volatile uchar * inpkt, int len)
return;
}
+#ifdef CONFIG_UDP_CHECKSUM
+ if (ip->udp_xsum != 0) {
+ ulong xsum;
+ ushort *sumptr;
+ ushort sumlen;
+
+ xsum = ip->ip_p;
+ xsum += (ntohs(ip->udp_len));
+ xsum += (ntohl(ip->ip_src) >> 16) & 0x0000ffff;
+ xsum += (ntohl(ip->ip_src) >> 0) & 0x0000ffff;
+ xsum += (ntohl(ip->ip_dst) >> 16) & 0x0000ffff;
+ xsum += (ntohl(ip->ip_dst) >> 0) & 0x0000ffff;
+
+ sumlen = ntohs(ip->udp_len);
+ sumptr = (ushort *) &(ip->udp_src);
+
+ while (sumlen > 1) {
+ ushort sumdata;
+
+ sumdata = *sumptr++;
+ xsum += ntohs(sumdata);
+ sumlen -= 2;
+ }
+ if (sumlen > 0) {
+ ushort sumdata;
+
+ sumdata = *(unsigned char *) sumptr;
+ sumdata = (sumdata << 8) & 0xff00;
+ xsum += sumdata;
+ }
+ while ((xsum >> 16) != 0) {
+ xsum = (xsum & 0x0000ffff) + ((xsum >> 16) & 0x0000ffff);
+ }
+ if ((xsum != 0x00000000) && (xsum != 0x0000ffff)) {
+ printf(" UDP wrong checksum %08x %08x\n", xsum, ntohs(ip->udp_xsum));
+ return;
+ }
+ }
+#endif
+
#ifdef CONFIG_NETCONSOLE
nc_input_packet((uchar *)ip +IP_HDR_SIZE,
ntohs(ip->udp_dst),
@@ -1477,7 +1517,7 @@ static int net_check_prereq (proto_t protocol)
return (1);
}
#if (CONFIG_COMMANDS & (CFG_CMD_PING | CFG_CMD_SNTP))
- common:
+ common:
#endif
if (NetOurIP == 0) {
diff --git a/tools/bddb/README b/tools/bddb/README
index 778e41c..9bee59a 100644
--- a/tools/bddb/README
+++ b/tools/bddb/README
@@ -1,7 +1,7 @@
Hymod Board Database
(C) Copyright 2001
-Murray Jensen <Murray.Jensen@cmst.csiro.au>
+Murray Jensen <Murray.Jensen@csiro.au>
CSIRO Manufacturing Science and Technology, Preston Lab
25-Jun-01
diff --git a/tools/bddb/badsubmit.php b/tools/bddb/badsubmit.php
index af0a962..5092a31 100644
--- a/tools/bddb/badsubmit.php
+++ b/tools/bddb/badsubmit.php
@@ -1,7 +1,7 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
require("defs.php");
diff --git a/tools/bddb/brlog.php b/tools/bddb/brlog.php
index fa651ae..fccfbd0 100644
--- a/tools/bddb/brlog.php
+++ b/tools/bddb/brlog.php
@@ -1,7 +1,7 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// list page (hymod_bddb / boards)
@@ -10,8 +10,9 @@
pg_head("$bddb_label - Browse Board Log");
- if (!isset($serno) || $serno == 0)
- die("serial number not specified!");
+ $serno=intval($serno);
+ if ($serno == 0)
+ die("serial number not specified or invalid!");
function print_cell($str) {
if ($str == '')
@@ -55,16 +56,16 @@
<hr></hr>
<p></p>
<?php
- $limit=abs(isset($limit)?$limit:20);
- $offset=abs(isset($offset)?$offset:0);
+ $limit=abs(isset($_REQUEST['limit'])?$_REQUEST['limit']:20);
+ $offset=abs(isset($_REQUEST['offset'])?$_REQUEST['offset']:0);
$lr=mysql_query("select count(*) as n from log where serno=$serno");
$lrow=mysql_fetch_array($lr);
if($lrow['n']>$limit){
$preoffset=max(0,$offset-$limit);
$postoffset=$offset+$limit;
echo "<table width=\"100%\">\n<tr align=center>\n";
- printf("<td><%sa href=\"%s?serno=$serno&offset=%d\"><img border=0 alt=\"&lt;\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset);
- printf("<td><%sa href=\"%s?serno=$serno&offset=%d\"><img border=0 alt=\"&gt;\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset);
+ printf("<td><%sa href=\"%s?submit=Log&serno=$serno&offset=%d\"><img border=0 alt=\"&lt;\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset);
+ printf("<td><%sa href=\"%s?submit=Log&serno=$serno&offset=%d\"><img border=0 alt=\"&gt;\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset);
echo "</tr>\n</table>\n";
}
mysql_free_result($lr);
diff --git a/tools/bddb/browse.php b/tools/bddb/browse.php
index b7cd508..675dfab 100644
--- a/tools/bddb/browse.php
+++ b/tools/bddb/browse.php
@@ -1,36 +1,38 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// list page (hymod_bddb / boards)
require("defs.php");
- if (!isset($verbose))
- $verbose = 0;
+ $serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:'';
- if (!isset($serno))
- $serno = 0;
+ $verbose=isset($_REQUEST['verbose'])?intval($_REQUEST['verbose']):0;
pg_head("$bddb_label - Browse database" . ($verbose?" (verbose)":""));
?>
<p></p>
<?php
- if ($serno == 0) {
- $limit=abs(isset($limit)?$limit:20);
- $offset=abs(isset($offset)?$offset:0);
+ $limit=isset($_REQUEST['limit'])?abs(intval($_REQUEST['limit'])):20;
+ $offset=isset($_REQUEST['offset'])?abs(intval($_REQUEST['offset'])):0;
+
+ if ($serno == '') {
+
$lr=mysql_query("select count(*) as n from boards");
$lrow=mysql_fetch_array($lr);
+
if($lrow['n']>$limit){
$preoffset=max(0,$offset-$limit);
$postoffset=$offset+$limit;
- echo "<table width=\"100%\">\n<tr align=center>\n";
- printf("<td><%sa href=\"%s?offset=%d\"><img border=0 alt=\"&lt;\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset);
- printf("<td><%sa href=\"%s?offset=%d\"><img border=0 alt=\"&gt;\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset);
+ echo "<table width=\"100%\">\n<tr>\n";
+ printf("<td align=left><%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\"><img border=0 alt=\"&lt;\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset, $verbose);
+ printf("<td align=right><%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\"><img border=0 alt=\"&gt;\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset, $offset);
echo "</tr>\n</table>\n";
}
+
mysql_free_result($lr);
}
?>
@@ -65,10 +67,28 @@
?>
</tr>
<?php
- if ($serno == 0)
- $r=mysql_query("select * from boards order by serno limit $offset,$limit");
- else
- $r=mysql_query("select * from boards where serno=$serno");
+ $query = "select * from boards";
+ if ($serno != '') {
+ $pre = " where ";
+ foreach (preg_split("/[\s,]+/", $serno) as $s) {
+ if (preg_match('/^[0-9]+$/',$s))
+ $query .= $pre . "serno=" . $s;
+ else if (preg_match('/^([0-9]+)-([0-9]+)$/',$s,$m)) {
+ $m1 = intval($m[1]); $m2 = intval($m[2]);
+ if ($m2 <= $m1)
+ die("bad serial number range ($s)");
+ $query .= $pre . "(serno>=$m[1] and serno<=$m[2])";
+ }
+ else
+ die("illegal serial number ($s)");
+ $pre = " or ";
+ }
+ }
+ $query .= " order by serno";
+ if ($serno == '')
+ $query .= " limit $offset,$limit";
+
+ $r = mysql_query($query);
function print_cell($str) {
if ($str == '')
@@ -117,10 +137,7 @@
<table width="100%">
<tr>
<td align=center><?php
- if ($verbose)
- echo "<a href=\"browse.php?verbose=0\">Terse Listing</a>";
- else
- echo "<a href=\"browse.php?verbose=1\">Verbose Listing</a>";
+ printf("<a href=\"%s?submit=Browse&offset=%d&verbose=%d%s\">%s Listing</a>\n", $PHP_SELF, $offset, $verbose?0:1, $serno!=''?"&serno=$serno":'', $verbose?"Terse":"Verbose");
?></td>
<td align=center><a href="index.php">Back to Start</a></td>
</tr>
diff --git a/tools/bddb/config.php b/tools/bddb/config.php
index 8d54993..6725757 100644
--- a/tools/bddb/config.php
+++ b/tools/bddb/config.php
@@ -1,6 +1,6 @@
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// mysql database access info
diff --git a/tools/bddb/create_tables.sql b/tools/bddb/create_tables.sql
index aa007c1..a2a5788 100644
--- a/tools/bddb/create_tables.sql
+++ b/tools/bddb/create_tables.sql
@@ -4,8 +4,8 @@
# Host: localhost Database : hymod_bddb
# (C) Copyright 2001
-# Murray Jensen <Murray.Jensen@cmst.csiro.au>
-# CSIRO Manufacturing Science and Technology, Preston Lab
+# Murray Jensen <Murray.Jensen@csiro.au>
+# CSIRO Manufacturing and Infrastructure Technology, Preston Lab
# --------------------------------------------------------
#
@@ -22,38 +22,38 @@ CREATE TABLE boards (
rev tinyint(3) unsigned zerofill NOT NULL,
location char(64),
comments text,
- sdram0 enum('32M','64M','128M','256M'),
- sdram1 enum('32M','64M','128M','256M'),
- sdram2 enum('32M','64M','128M','256M'),
- sdram3 enum('32M','64M','128M','256M'),
- flash0 enum('4M','8M','16M','32M','64M'),
- flash1 enum('4M','8M','16M','32M','64M'),
- flash2 enum('4M','8M','16M','32M','64M'),
- flash3 enum('4M','8M','16M','32M','64M'),
- zbt0 enum('512K','1M','2M','4M'),
- zbt1 enum('512K','1M','2M','4M'),
- zbt2 enum('512K','1M','2M','4M'),
- zbt3 enum('512K','1M','2M','4M'),
- zbt4 enum('512K','1M','2M','4M'),
- zbt5 enum('512K','1M','2M','4M'),
- zbt6 enum('512K','1M','2M','4M'),
- zbt7 enum('512K','1M','2M','4M'),
- zbt8 enum('512K','1M','2M','4M'),
- zbt9 enum('512K','1M','2M','4M'),
- zbta enum('512K','1M','2M','4M'),
- zbtb enum('512K','1M','2M','4M'),
- zbtc enum('512K','1M','2M','4M'),
- zbtd enum('512K','1M','2M','4M'),
- zbte enum('512K','1M','2M','4M'),
- zbtf enum('512K','1M','2M','4M'),
- xlxtyp0 enum('XCV300E','XCV400E','XCV600E'),
- xlxtyp1 enum('XCV300E','XCV400E','XCV600E'),
- xlxtyp2 enum('XCV300E','XCV400E','XCV600E'),
- xlxtyp3 enum('XCV300E','XCV400E','XCV600E'),
- xlxspd0 enum('6','7','8'),
- xlxspd1 enum('6','7','8'),
- xlxspd2 enum('6','7','8'),
- xlxspd3 enum('6','7','8'),
+ sdram0 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
+ sdram1 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
+ sdram2 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
+ sdram3 enum('32M','64M','128M','256M','512M','1G','2G','4G'),
+ flash0 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
+ flash1 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
+ flash2 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
+ flash3 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'),
+ zbt0 enum('512K','1M','2M','4M','8M','16M'),
+ zbt1 enum('512K','1M','2M','4M','8M','16M'),
+ zbt2 enum('512K','1M','2M','4M','8M','16M'),
+ zbt3 enum('512K','1M','2M','4M','8M','16M'),
+ zbt4 enum('512K','1M','2M','4M','8M','16M'),
+ zbt5 enum('512K','1M','2M','4M','8M','16M'),
+ zbt6 enum('512K','1M','2M','4M','8M','16M'),
+ zbt7 enum('512K','1M','2M','4M','8M','16M'),
+ zbt8 enum('512K','1M','2M','4M','8M','16M'),
+ zbt9 enum('512K','1M','2M','4M','8M','16M'),
+ zbta enum('512K','1M','2M','4M','8M','16M'),
+ zbtb enum('512K','1M','2M','4M','8M','16M'),
+ zbtc enum('512K','1M','2M','4M','8M','16M'),
+ zbtd enum('512K','1M','2M','4M','8M','16M'),
+ zbte enum('512K','1M','2M','4M','8M','16M'),
+ zbtf enum('512K','1M','2M','4M','8M','16M'),
+ xlxtyp0 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
+ xlxtyp1 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
+ xlxtyp2 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
+ xlxtyp3 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'),
+ xlxspd0 enum('6','7','8','4','5','9','10','11','12'),
+ xlxspd1 enum('6','7','8','4','5','9','10','11','12'),
+ xlxspd2 enum('6','7','8','4','5','9','10','11','12'),
+ xlxspd3 enum('6','7','8','4','5','9','10','11','12'),
xlxtmp0 enum('COM','IND'),
xlxtmp1 enum('COM','IND'),
xlxtmp2 enum('COM','IND'),
@@ -62,13 +62,13 @@ CREATE TABLE boards (
xlxgrd1 enum('NORMAL','ENGSAMP'),
xlxgrd2 enum('NORMAL','ENGSAMP'),
xlxgrd3 enum('NORMAL','ENGSAMP'),
- cputyp enum('MPC8260'),
- cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ'),
- cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ'),
- busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ'),
- hstype enum('AMCC-S2064A'),
- hschin enum('0','1','2','3','4'),
- hschout enum('0','1','2','3','4'),
+ cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560'),
+ cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'),
+ cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'),
+ busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'),
+ hstype enum('AMCC-S2064A','Xilinx-Rockets'),
+ hschin enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'),
+ hschout enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'),
PRIMARY KEY (serno),
KEY serno (serno),
UNIQUE serno_2 (serno)
diff --git a/tools/bddb/defs.php b/tools/bddb/defs.php
index 9361419..b7518e3 100644
--- a/tools/bddb/defs.php
+++ b/tools/bddb/defs.php
@@ -1,13 +1,13 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// contains mysql user id and password - keep secret
require("config.php");
- if (isset($logout)) {
+ if (isset($_REQUEST['logout'])) {
Header("status: 401 Unauthorized");
Header("HTTP/1.0 401 Unauthorized");
Header("WWW-authenticate: basic realm=\"$bddb_label\"");
@@ -45,32 +45,40 @@
// board type
$type_vals = array('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY');
- // sdram sizes (nbits array is for write into eeprom config file)
- $sdram_vals = array('','32M','64M','128M','256M');
- $sdram_nbits = array(0,25,26,27,28);
+ // Xilinx fpga types
+ $xlxtyp_vals = array('','XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140');
- // flash sizes (nbits array is for write into eeprom config file)
- $flash_vals = array('','4M','8M','16M','32M','64M');
- $flash_nbits = array(0,22,23,24,25,26);
+ // Xilinx fpga speeds
+ $xlxspd_vals = array('','6','7','8','4','5','9','10','11','12');
- // zbt ram sizes (nbits array is for write into eeprom config file)
- $zbt_vals = array('','512K','1M','2M','4M');
- $zbt_nbits = array(0,19,20,21,22);
-
- // Xilinx attributes
- $xlxtyp_vals = array('','XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000');
- $xlxspd_vals = array('','6','7','8','4','5');
+ // Xilinx fpga temperatures (commercial or industrial)
$xlxtmp_vals = array('','COM','IND');
+
+ // Xilinx fpga grades (normal or engineering sample)
$xlxgrd_vals = array('','NORMAL','ENGSAMP');
- // processor attributes
- $cputyp_vals = array('','MPC8260');
- $clk_vals = array('','33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ');
+ // CPU types
+ $cputyp_vals = array('','MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560');
+
+ // CPU/BUS/CPM clock speeds
+ $clk_vals = array('','33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ');
+
+ // sdram sizes (nbits array is for eeprom config file)
+ $sdram_vals = array('','32M','64M','128M','256M','512M','1G','2G','4G');
+ $sdram_nbits = array(0,25,26,27,28,29,30,31,32);
+
+ // flash sizes (nbits array is for eeprom config file)
+ $flash_vals = array('','4M','8M','16M','32M','64M','128M','256M','512M','1G');
+ $flash_nbits = array(0,22,23,24,25,26,27,28,29,30);
+
+ // zbt ram sizes (nbits array is for write into eeprom config file)
+ $zbt_vals = array('','512K','1M','2M','4M','8M','16M');
+ $zbt_nbits = array(0,19,20,21,22,23,24);
// high-speed serial attributes
- $hstype_vals = array('','AMCC-S2064A');
- $hschin_vals = array('0','1','2','3','4');
- $hschout_vals = array('0','1','2','3','4');
+ $hstype_vals = array('','AMCC-S2064A','Xilinx-Rockets');
+ $hschin_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16');
+ $hschout_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16');
// value filters - used when outputting html
function rev_filter($num) {
@@ -108,7 +116,7 @@
echo "<hr></hr>\n";
echo "<table width=\"100%\"><tr><td align=left>\n<address>" .
"If you have any problems, email " .
- "<a href=\"mailto:Murray.Jensen@cmst.csiro.au\">" .
+ "<a href=\"mailto:Murray.Jensen@csiro.au\">" .
"Murray Jensen" .
"</a></address>\n" .
"</td><td align=right>\n" .
@@ -310,6 +318,38 @@
end_field();
}
+ // print a mysql ENUM as an html SELECT INPUT
+ function print_enum_select($name, $array, $vals, $def = -1) {
+
+ begin_field($name);
+
+ echo "\t\t<select name=$name>\n";
+
+ if (key_in_array($name, $array))
+ $chk = array_search($array[$name], $vals, FALSE);
+ else
+ $chk = $def;
+
+ $nval = count($vals);
+
+ for ($i = 0; $i < $nval; $i++) {
+
+ $val = $vals[$i];
+ if ($val == '')
+ $pval = "none";
+ else
+ $pval = "$val";
+
+ printf("\t\t\t<option " .
+ "value=\"%s\"%s>%s</option>\n",
+ $val, $i == $chk ? " selected" : "", $pval);
+ }
+
+ echo "\t\t</select>\n";
+
+ end_field();
+ }
+
// print a group of mysql ENUMs (e.g. name0,name1,...) as an html SELECT
function print_enum_multi($base, $array, $vals, $cnt, $defs, $grp = 0) {
@@ -375,9 +415,9 @@
$name = sprintf("%s%x", $base, $i);
- if (isset($GLOBALS[$name])) {
+ if (isset($_REQUEST[$name])) {
$retval .= sprintf(", %s='%s'",
- $name, $GLOBALS[$name]);
+ $name, $_REQUEST[$name]);
}
}
@@ -437,7 +477,7 @@
$name = sprintf("%s%x", $base, $i);
- if (isset($GLOBALS[$name]))
+ if (isset($_REQUEST[$name]))
$retval++;
}
@@ -458,13 +498,14 @@
function gen_eth_addr($serno) {
- $ethaddr_high = (mt_rand(0, 65535) & 0xfeff) | 0x0200;
- $ethaddr_low = mt_rand(0, 4294967295);
+ $ethaddr_hgh = (mt_rand(0, 65535) & 0xfeff) | 0x0200;
+ $ethaddr_mid = mt_rand(0, 65535);
+ $ethaddr_low = mt_rand(0, 65535);
return sprintf("%02lx:%02lx:%02lx:%02lx:%02lx:%02lx",
- $ethaddr_high >> 8, $ethaddr_high & 0xff,
- $ethaddr_low >> 24, ($ethaddr_low >> 16) & 0xff,
- ($ethaddr_low >> 8) & 0xff, $ethaddr_low & 0xff);
+ $ethaddr_hgh >> 8, $ethaddr_hgh & 0xff,
+ $ethaddr_mid >> 8, $ethaddr_mid & 0xff,
+ $ethaddr_low >> 8, $ethaddr_low & 0xff);
}
// check that an ethernet address is valid
diff --git a/tools/bddb/dodelete.php b/tools/bddb/dodelete.php
index 839ad8c..4839e36 100644
--- a/tools/bddb/dodelete.php
+++ b/tools/bddb/dodelete.php
@@ -1,7 +1,7 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// dodelete page (hymod_bddb / boards)
@@ -10,8 +10,9 @@
pg_head("$bddb_label - Delete Board Results");
- if (!($serno=intval($serno)))
+ if (!isset($_REQUEST['serno']))
die("the board serial number was not specified");
+ $serno=intval($_REQUEST['serno']);
mysql_query("delete from boards where serno=$serno");
diff --git a/tools/bddb/dodellog.php b/tools/bddb/dodellog.php
index d5822c5..9dd78c1 100644
--- a/tools/bddb/dodellog.php
+++ b/tools/bddb/dodellog.php
@@ -1,7 +1,7 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// dodelete page (hymod_bddb / boards)
@@ -10,11 +10,13 @@
pg_head("$bddb_label - Delete Log Entry Results");
- if (!($serno=intval($serno)))
+ if (!isset($_REQUEST['serno']))
die("the board serial number was not specified");
+ $serno=intval($_REQUEST['serno']);
- if (!isset($logno) || $logno == 0)
+ if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == 0)
die("the log entry number not specified!");
+ $logno=$_REQUEST['logno'];
mysql_query("delete from log where serno=$serno and logno=$logno");
diff --git a/tools/bddb/doedit.php b/tools/bddb/doedit.php
index 110ecf3..13fbb69 100644
--- a/tools/bddb/doedit.php
+++ b/tools/bddb/doedit.php
@@ -1,7 +1,7 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// doedit page (hymod_bddb / boards)
@@ -10,18 +10,21 @@
pg_head("$bddb_label - Edit Board Results");
- if ($serno == 0)
+ if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
die("the board serial number was not specified");
+ $serno=intval($_REQUEST['serno']);
$query="update boards set";
- if (isset($ethaddr)) {
+ if (isset($_REQUEST['ethaddr'])) {
+ $ethaddr=$_REQUEST['ethaddr'];
if (!eth_addr_is_valid($ethaddr))
die("ethaddr is invalid ('$ethaddr')");
$query.=" ethaddr='$ethaddr',";
}
- if (isset($date)) {
+ if (isset($_REQUEST['date'])) {
+ $date=$_REQUEST['date'];
list($y, $m, $d) = split("-", $date);
if (!checkdate($m, $d, $y) || $y < 1999)
die("date is invalid (input '$date', " .
@@ -29,31 +32,36 @@
$query.=" date='$date'";
}
- if (isset($batch)) {
+ if (isset($_REQUEST['batch'])) {
+ $batch=$_REQUEST['batch'];
if (strlen($batch) > 32)
die("batch field too long (>32)");
$query.=", batch='$batch'";
}
- if (isset($type)) {
+ if (isset($_REQUEST['type'])) {
+ $type=$_REQUEST['type'];
if (!in_array($type, $type_vals))
die("Invalid type ($type) specified");
$query.=", type='$type'";
}
- if (isset($rev)) {
+ if (isset($_REQUEST['rev'])) {
+ $rev=$_REQUEST['rev'];
if (($rev = intval($rev)) <= 0 || $rev > 255)
die("Revision number is invalid ($rev)");
$query.=sprintf(", rev=%d", $rev);
}
- if (isset($location)) {
+ if (isset($_REQUEST['location'])) {
+ $location=$_REQUEST['location'];
if (strlen($location) > 64)
die("location field too long (>64)");
$query.=", location='$location'";
}
- if (isset($comments))
+ if (isset($_REQUEST['comments']))
+ $comments=$_REQUEST['comments'];
$query.=", comments='" . rawurlencode($comments) . "'";
$query.=gather_enum_multi_query("sdram", 4);
@@ -77,46 +85,54 @@
if (count_enum_multi("xlxgrd", 4) != $nxlx)
die("number of xilinx grades not same as number of types");
- if (isset($cputyp)) {
+ if (isset($_REQUEST['cputyp'])) {
+ $cputyp=$_REQUEST['cputyp'];
$query.=", cputyp='$cputyp'";
- if ($cpuspd == '')
+ if (!isset($_REQUEST['cpuspd']) || $_REQUEST['cpuspd'] == '')
die("must specify cpu speed if cpu type is defined");
+ $cpuspd=$_REQUEST['cpuspd'];
$query.=", cpuspd='$cpuspd'";
- if ($cpmspd == '')
+ if (!isset($_REQUEST['cpmspd']) || $_REQUEST['cpmspd'] == '')
die("must specify cpm speed if cpu type is defined");
+ $cpmspd=$_REQUEST['cpmspd'];
$query.=", cpmspd='$cpmspd'";
- if ($busspd == '')
+ if (!isset($_REQUEST['busspd']) || $_REQUEST['busspd'] == '')
die("must specify bus speed if cpu type is defined");
+ $busspd=$_REQUEST['busspd'];
$query.=", busspd='$busspd'";
}
else {
- if (isset($cpuspd))
+ if (isset($_REQUEST['cpuspd']))
die("can't specify cpu speed if there is no cpu");
- if (isset($cpmspd))
+ if (isset($_REQUEST['cpmspd']))
die("can't specify cpm speed if there is no cpu");
- if (isset($busspd))
+ if (isset($_REQUEST['busspd']))
die("can't specify bus speed if there is no cpu");
}
- if (isset($hschin)) {
+ if (isset($_REQUEST['hschin'])) {
+ $hschin=$_REQUEST['hschin'];
if (($hschin = intval($hschin)) < 0 || $hschin > 4)
die("Invalid number of hs input chans ($hschin)");
}
else
$hschin = 0;
- if (isset($hschout)) {
+ if (isset($_REQUEST['hschout'])) {
+ $hschout=$_REQUEST['hschout'];
if (($hschout = intval($hschout)) < 0 || $hschout > 4)
die("Invalid number of hs output chans ($hschout)");
}
else
$hschout = 0;
- if (isset($hstype))
+ if (isset($_REQUEST['hstype'])) {
+ $hstype=$_REQUEST['hstype'];
$query.=", hstype='$hstype'";
+ }
else {
- if ($hschin != 0)
+ if ($_REQUEST['hschin'] != 0)
die("number of high-speed input channels must be zero"
. " if high-speed chip is not present");
- if ($hschout != 0)
+ if ($_REQUEST['hschout'] != 0)
die("number of high-speed output channels must be zero"
. " if high-speed chip is not present");
}
diff --git a/tools/bddb/doedlog.php b/tools/bddb/doedlog.php
index f800471..7009aa7 100644
--- a/tools/bddb/doedlog.php
+++ b/tools/bddb/doedlog.php
@@ -1,7 +1,7 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// doedit page (hymod_bddb / boards)
@@ -10,15 +10,18 @@
pg_head("$bddb_label - Edit Log Entry Results");
- if ($serno == 0)
+ if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
die("the board serial number was not specified");
+ $serno=intval($_REQUEST['serno']);
- if (!isset($logno) || $logno == 0)
+ if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '')
die("log number not specified!");
+ $logno=intval($_REQUEST['logno']);
$query="update log set";
- if (isset($date)) {
+ if (isset($_REQUEST['date'])) {
+ $date=$_REQUEST['date'];
list($y, $m, $d) = split("-", $date);
if (!checkdate($m, $d, $y) || $y < 1999)
die("date is invalid (input '$date', " .
@@ -26,11 +29,15 @@
$query.=" date='$date'";
}
- if (isset($who))
+ if (isset($_REQUEST['who'])) {
+ $who=$_REQUEST['who'];
$query.=", who='" . $who . "'";
+ }
- if (isset($details))
+ if (isset($_REQUEST['details'])) {
+ $details=$_REQUEST['details'];
$query.=", details='" . rawurlencode($details) . "'";
+ }
$query.=" where serno=$serno and logno=$logno";
diff --git a/tools/bddb/donew.php b/tools/bddb/donew.php
index 0f6e0d7..39b2c78 100644
--- a/tools/bddb/donew.php
+++ b/tools/bddb/donew.php
@@ -1,7 +1,7 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// doedit page (hymod_bddb / boards)
@@ -10,8 +10,10 @@
pg_head("$bddb_label - Board Registration Results");
- if (($serno=intval($serno)) != 0)
+ if (isset($_REQUEST['serno'])) {
+ $serno=$_REQUEST['serno'];
die("serial number must not be set ($serno) when Creating!");
+ }
$query="update boards set";
diff --git a/tools/bddb/donewlog.php b/tools/bddb/donewlog.php
index 35ba125..7635d29 100644
--- a/tools/bddb/donewlog.php
+++ b/tools/bddb/donewlog.php
@@ -1,7 +1,7 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// doedit page (hymod_bddb / boards)
@@ -10,11 +10,14 @@
pg_head("$bddb_label - Add Log Entry Results");
- if ($serno == 0)
+ if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
die("serial number not specified!");
+ $serno=intval($_REQUEST['serno']);
- if (isset($logno))
+ if (isset($_REQUEST['logno'])) {
+ $logno=$_REQUEST['logno'];
die("log number must not be set ($logno) when Creating!");
+ }
$query="update log set serno=$serno";
@@ -23,11 +26,15 @@
die("date is invalid (input '$date', yyyy-mm-dd '$y-$m-$d')");
$query.=", date='$date'";
- if (isset($who))
+ if (isset($_REQUEST['who'])) {
+ $who=$_REQUEST['who'];
$query.=", who='" . $who . "'";
+ }
- if (isset($details))
+ if (isset($_REQUEST['details'])) {
+ $details=$_REQUEST['details'];
$query.=", details='" . rawurlencode($details) . "'";
+ }
// echo "final query = '$query'<br>\n";
diff --git a/tools/bddb/edit.php b/tools/bddb/edit.php
index f7d4830..dd8c26c 100644
--- a/tools/bddb/edit.php
+++ b/tools/bddb/edit.php
@@ -1,7 +1,7 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// edit page (hymod_bddb / boards)
@@ -11,7 +11,7 @@
pg_head("$bddb_label - Edit Board Registration");
if ($serno == 0)
- die("serial number not specified!");
+ die("serial number not specified or invalid!");
$pserno = sprintf("%010d", $serno);
@@ -73,17 +73,17 @@
// xlxgrd[0-3] enum('NORMAL','ENGSAMP')
print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(), 1);
- // cputyp enum('MPC8260')
+ // cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)')
print_enum("cputyp", $row, $cputyp_vals);
- // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ')
- print_enum("cpuspd", $row, $clk_vals);
+ // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
+ print_enum_select("cpuspd", $row, $clk_vals);
- // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ')
- print_enum("cpmspd", $row, $clk_vals);
+ // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
+ print_enum_select("cpmspd", $row, $clk_vals);
- // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ')
- print_enum("busspd", $row, $clk_vals);
+ // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
+ print_enum_select("busspd", $row, $clk_vals);
// hstype enum('AMCC-S2064A')
print_enum("hstype", $row, $hstype_vals);
diff --git a/tools/bddb/edlog.php b/tools/bddb/edlog.php
index 7f311bf..8befd35 100644
--- a/tools/bddb/edlog.php
+++ b/tools/bddb/edlog.php
@@ -1,7 +1,7 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// edit page (hymod_bddb / boards)
@@ -10,11 +10,13 @@
pg_head("$bddb_label - Edit Board Log Entry");
- if ($serno == 0)
+ if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
die("serial number not specified!");
+ $serno=intval($_REQUEST['serno']);
- if (!isset($logno) || $logno == 0)
+ if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '')
die("log number not specified!");
+ $logno=intval($_REQUEST['logno']);
$pserno = sprintf("%010d", $serno);
$plogno = sprintf("%010d", $logno);
diff --git a/tools/bddb/execute.php b/tools/bddb/execute.php
index 7adcfec..0b62882 100644
--- a/tools/bddb/execute.php
+++ b/tools/bddb/execute.php
@@ -1,16 +1,12 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
- if (!isset($serno))
- $serno = 0;
- else
- $serno = intval($serno);
+ $serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:'';
- if (!isset($submit))
- $submit = "[NOT SET]";
+ $submit=isset($_REQUEST['submit'])?$_REQUEST['submit']:"[NOT SET]";
switch ($submit) {
diff --git a/tools/bddb/index.php b/tools/bddb/index.php
index 9d6c7f5..842aed5 100644
--- a/tools/bddb/index.php
+++ b/tools/bddb/index.php
@@ -1,7 +1,7 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
require("defs.php");
diff --git a/tools/bddb/new.php b/tools/bddb/new.php
index 889c6ae..30323ff 100644
--- a/tools/bddb/new.php
+++ b/tools/bddb/new.php
@@ -1,7 +1,7 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// edit page (hymod_bddb / boards)
@@ -13,6 +13,7 @@
<form action=donew.php method=POST>
<p></p>
<?php
+ $serno=intval($serno);
// if a serial number was supplied, fetch the record
// and use its contents as defaults
if ($serno != 0) {
@@ -23,8 +24,6 @@
else
$row = array();
- echo "<input type=hidden name=serno value=0>\n";
-
begin_table(5);
// date date
@@ -60,17 +59,17 @@
// xlxgrd[0-3] enum('NORMAL','ENGSAMP')
print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(1), 1);
- // cputyp enum('MPC8260')
+ // cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)')
print_enum("cputyp", $row, $cputyp_vals, 1);
- // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ')
- print_enum("cpuspd", $row, $clk_vals, 4);
+ // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
+ print_enum_select("cpuspd", $row, $clk_vals, 4);
- // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ')
- print_enum("cpmspd", $row, $clk_vals, 4);
+ // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
+ print_enum_select("cpmspd", $row, $clk_vals, 4);
- // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ')
- print_enum("busspd", $row, $clk_vals, 2);
+ // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ')
+ print_enum_select("busspd", $row, $clk_vals, 2);
// hstype enum('AMCC-S2064A')
print_enum("hstype", $row, $hstype_vals, 1);
diff --git a/tools/bddb/newlog.php b/tools/bddb/newlog.php
index 3f51639..609bb85 100644
--- a/tools/bddb/newlog.php
+++ b/tools/bddb/newlog.php
@@ -1,7 +1,7 @@
<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?>
<?php
// (C) Copyright 2001
- // Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ // Murray Jensen <Murray.Jensen@csiro.au>
// CSIRO Manufacturing Science and Technology, Preston Lab
// edit page (hymod_bddb / boards)
@@ -10,11 +10,14 @@
pg_head("$bddb_label - New Log Entry");
- if ($serno == 0)
- die("serial number not specified!");
+ if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '')
+ die("serial number not specified or invalid!");
+ $serno=intval($_REQUEST['serno']);
- if (isset($logno))
- die("log number must not be specified when adding!");
+ if (isset($_REQUEST['logno'])) {
+ $logno=$_REQUEST['logno'];
+ die("log number must not be specified when adding! ($logno)");
+ }
?>
<form action=donewlog.php method=POST>
<p></p>
@@ -27,7 +30,7 @@
print_field("date", array('date' => date("Y-m-d")));
// who char(20)
- print_field("who", "");
+ print_field("who", array());
// details text
print_field_multiline("details", array(), 60, 10, 'text_filter');
diff --git a/tools/gdb/Makefile b/tools/gdb/Makefile
index faff120..e7618b7 100644
--- a/tools/gdb/Makefile
+++ b/tools/gdb/Makefile
@@ -1,6 +1,6 @@
#
# (C) Copyright 2000
-# Murray Jensen <Murray.Jensen@cmst.csiro.au>
+# Murray Jensen <Murray.Jensen@csiro.au>
#
# See file CREDITS for list of people who contributed to this
# project.