diff options
1222 files changed, 19121 insertions, 8211 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 067fb22..bf60c67 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -376,18 +376,13 @@ T: git git://git.denx.de/u-boot-sparc.git F: arch/sparc/ SPI -M: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> +M: Jagan Teki <jteki@openedev.com> S: Maintained T: git git://git.denx.de/u-boot-spi.git F: drivers/mtd/spi/ F: drivers/spi/ F: include/spi* -TESTING -M: Detlev Zundel <dzu@denx.de> -S: Maintained -T: git git://git.denx.de/u-boot-testing.git - TQ GROUP M: Martin Krause <martin.krause@tq-systems.de> S: Maintained @@ -645,7 +645,8 @@ libs-y += drivers/power/ \ drivers/power/fuel_gauge/ \ drivers/power/mfd/ \ drivers/power/pmic/ \ - drivers/power/battery/ + drivers/power/battery/ \ + drivers/power/regulator/ libs-y += drivers/spi/ libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/ libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ @@ -1272,6 +1273,7 @@ FINDFLAGS := -L tags ctags: ctags -w -o ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ -name '*.[chS]' -print` + ln -s ctags tags etags: etags -a -o etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ @@ -5473,7 +5473,7 @@ loaded to, and "Flash Location" gives the image's address in NOR flash or offset in NAND flash. *Note* - these variables don't have to be defined for all boards, some -boards currenlty use other variables for these purposes, and some +boards currently use other variables for these purposes, and some boards use these variables for other purposes. Image File Name RAM Address Flash Location diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index c044ad4..67d28d3 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -132,14 +132,7 @@ config ARC_CACHE_LINE_SHIFT choice prompt "Target select" - -config TARGET_DUMMY - bool "Dummy target" - help - Please select one of real target boards below! - This target is only meant to force "makedefconfig" to put - TARGET_xxx in defconfig even this is the first target from the list - below. + optional config TARGET_TB100 bool "Support tb100" diff --git a/arch/arc/config.mk b/arch/arc/config.mk index 04c034b..74943d9 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -11,13 +11,13 @@ CONFIG_SYS_BIG_ENDIAN = 1 endif ifdef CONFIG_SYS_LITTLE_ENDIAN -ARC_CROSS_COMPILE := arc-buildroot-linux-uclibc- +ARC_CROSS_COMPILE := arc-linux- PLATFORM_LDFLAGS += -EL PLATFORM_CPPFLAGS += -mlittle-endian endif ifdef CONFIG_SYS_BIG_ENDIAN -ARC_CROSS_COMPILE := arceb-buildroot-linux-uclibc- +ARC_CROSS_COMPILE := arceb-linux- PLATFORM_LDFLAGS += -EB PLATFORM_CPPFLAGS += -mbig-endian endif diff --git a/arch/arc/dts/.gitignore b/arch/arc/dts/.gitignore new file mode 100644 index 0000000..b60ed20 --- /dev/null +++ b/arch/arc/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 49bcad1..6727423 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -64,6 +64,7 @@ config SEMIHOSTING choice prompt "Target select" + optional config ARCH_AT91 bool "Atmel AT91" @@ -561,10 +562,6 @@ config TARGET_GW_VENTANA select CPU_V7 select SUPPORT_SPL -config TARGET_HUMMINGBOARD - bool "Support hummingboard" - select CPU_V7 - config TARGET_KOSAGI_NOVENA bool "Support Kosagi Novena" select CPU_V7 @@ -619,16 +616,8 @@ config TARGET_CM_FX6 select DM_SERIAL select DM_GPIO -config TARGET_SOCFPGA_ARRIA5 - bool "Support socfpga_arria5" - select CPU_V7 - select SUPPORT_SPL - select DM - select DM_SPI_FLASH - select DM_SPI - -config TARGET_SOCFPGA_CYCLONE5 - bool "Support socfpga_cyclone5" +config ARCH_SOCFPGA + bool "Altera SOCFPGA family" select CPU_V7 select SUPPORT_SPL select DM @@ -841,6 +830,8 @@ source "arch/arm/cpu/armv7/rmobile/Kconfig" source "arch/arm/cpu/armv7/s5pc1xx/Kconfig" +source "arch/arm/mach-socfpga/Kconfig" + source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-uniphier/Kconfig" @@ -863,7 +854,6 @@ source "board/Marvell/aspenite/Kconfig" source "board/Marvell/db-88f6820-gp/Kconfig" source "board/Marvell/db-mv784mp-gp/Kconfig" source "board/Marvell/gplugd/Kconfig" -source "board/altera/socfpga/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" @@ -939,7 +929,6 @@ source "board/siemens/pxm2/Kconfig" source "board/siemens/rut/Kconfig" source "board/silica/pengwyn/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" -source "board/solidrun/hummingboard/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 8ff94a3..6f30098 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -53,6 +53,7 @@ machine-$(CONFIG_ARMADA_XP) += mvebu machine-$(CONFIG_ARCH_NOMADIK) += nomadik # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x +machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_TEGRA) += tegra machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_VERSATILE) += versatile diff --git a/arch/arm/config.mk b/arch/arm/config.mk index c005ce4..0550225 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -112,7 +112,8 @@ endif ifdef CONFIG_ARM64 OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn else -OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn +OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j \ + .got -j .got.plt -j .u_boot_list -j .rel.dyn endif ifdef CONFIG_OF_EMBED diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index 61e7c82..6c5d5dd 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -16,7 +16,7 @@ config ARMV7_NONSEC config ARMV7_BOOT_SEC_DEFAULT boolean "Boot in secure mode by default" if EXPERT depends on ARMV7_NONSEC - default n + default y if TEGRA ---help--- Say Y here to boot in secure mode by default even if non-secure mode is supported. This option is useful to boot kernels which do not diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index d335845..5a76100 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,13 +12,13 @@ obj-y += cache_v7.o obj-y += cpu.o cp15.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_SOCFPGA),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif endif -ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),) +ifneq ($(CONFIG_ARMV7_NONSEC),) obj-y += nonsec_virt.o obj-y += virt-v7.o obj-y += virt-dt.o @@ -50,7 +50,6 @@ obj-$(CONFIG_OMAP44XX) += omap4/ obj-$(CONFIG_OMAP54XX) += omap5/ obj-$(CONFIG_RMOBILE) += rmobile/ obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/ -obj-$(CONFIG_SOCFPGA) += socfpga/ obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_U8500) += u8500/ diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index f6084ac..c614425 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -2,6 +2,7 @@ if ARCH_EXYNOS choice prompt "EXYNOS board select" + optional config TARGET_SMDKV310 select SUPPORT_SPL diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 1a640bb..75f0d8c 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -329,7 +329,7 @@ int arch_cpu_init(void) return 0; } -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +#ifdef CONFIG_ARMV7_NONSEC /* Set the address at which the secondary core starts from.*/ void smp_set_core_boot_addr(unsigned long addr, int corenr) { diff --git a/arch/arm/cpu/armv7/mx5/Kconfig b/arch/arm/cpu/armv7/mx5/Kconfig index 2d6c0ce..9f250c6 100644 --- a/arch/arm/cpu/armv7/mx5/Kconfig +++ b/arch/arm/cpu/armv7/mx5/Kconfig @@ -12,6 +12,7 @@ config MX53 choice prompt "MX5 board select" + optional config TARGET_USBARMORY bool "Support USB armory" diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 076ba52..1282be3 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -27,6 +27,7 @@ config MX6SX choice prompt "MX6 board select" + optional config TARGET_SECOMX6 bool "Support secomx6 boards" diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 653d58e..5d5bd0f 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -265,24 +265,40 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */ u8 coladdr; int clkper; /* clock period in picoseconds */ - int clock; /* clock freq in mHz */ + int clock; /* clock freq in MHz */ int cs; + u16 mem_speed = ddr3_cfg->mem_speed; mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; #ifndef CONFIG_MX6SX mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; #endif - /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */ + /* Limit mem_speed for MX6D/MX6Q */ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { - clock = 528; + if (mem_speed > 1066) + mem_speed = 1066; /* 1066 MT/s */ + tcwl = 4; } - /* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */ + /* Limit mem_speed for MX6S/MX6DL */ else { - clock = 400; + if (mem_speed > 800) + mem_speed = 800; /* 800 MT/s */ + tcwl = 3; } + + clock = mem_speed / 2; + /* + * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports + * up to 528 MHz, so reduce the clock to fit chip specs + */ + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { + if (clock > 528) + clock = 528; /* 528 MHz */ + } + clkper = (1000 * 1000) / clock; /* pico seconds */ todtlon = tcwl; taxpd = tcwl; @@ -313,7 +329,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, } txpr = txs; - switch (ddr3_cfg->mem_speed) { + switch (mem_speed) { case 800: txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; @@ -336,28 +352,6 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; } break; - case 1333: - txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1; - tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1; - if (ddr3_cfg->pagesz == 1) { - tfaw = DIV_ROUND_UP(30000, clkper) - 1; - trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1; - } else { - tfaw = DIV_ROUND_UP(45000, clkper) - 1; - trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1; - } - break; - case 1600: - txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1; - tcke = DIV_ROUND_UP(max(3 * clkper, 5000), clkper) - 1; - if (ddr3_cfg->pagesz == 1) { - tfaw = DIV_ROUND_UP(30000, clkper) - 1; - trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1; - } else { - tfaw = DIV_ROUND_UP(40000, clkper) - 1; - trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1; - } - break; default: puts("invalid memory speed\n"); hang(); @@ -382,7 +376,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, debug("density:%d Gb (%d Gb per chip)\n", sysinfo->cs_density, ddr3_cfg->density); debug("clock: %dMHz (%d ps)\n", clock, clkper); - debug("memspd:%d\n", ddr3_cfg->mem_speed); + debug("memspd:%d\n", mem_speed); debug("tcke=%d\n", tcke); debug("tcksrx=%d\n", tcksrx); debug("tcksre=%d\n", tcksre); diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index dd34138..21ef9d0 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -523,6 +523,14 @@ void v7_outer_cache_enable(void) struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; unsigned int val; + + /* + * Set bit 22 in the auxiliary control register. If this bit + * is cleared, PL310 treats Normal Shared Non-cacheable + * accesses as Cacheable no-allocate. + */ + setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE); + #if defined CONFIG_MX6SL struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; val = readl(&iomux->gpr[11]); diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index cc82c50..b32a6b0 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -2,6 +2,7 @@ if OMAP34XX choice prompt "OMAP3 board select" + optional config TARGET_AM3517_EVM bool "AM3517 EVM" diff --git a/arch/arm/cpu/armv7/omap4/Kconfig b/arch/arm/cpu/armv7/omap4/Kconfig index eccf897..df27ea1 100644 --- a/arch/arm/cpu/armv7/omap4/Kconfig +++ b/arch/arm/cpu/armv7/omap4/Kconfig @@ -2,6 +2,7 @@ if OMAP44XX choice prompt "OMAP4 board select" + optional config TARGET_DUOVERO bool "OMAP4430 Gumstix Duovero" diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index aca862d..20c3bd9 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -2,6 +2,7 @@ if OMAP54XX choice prompt "OMAP5 board select" + optional config TARGET_CM_T54 bool "CompuLab CM-T54" diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index bf11a34..87c0c0b 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -17,6 +17,7 @@ #include <config.h> #include <linux/linkage.h> +#include <asm/macro.h> #include <asm/psci.h> .pushsection ._secure.text, "ax" @@ -99,4 +100,124 @@ _smc_psci: pop {r4-r7, lr} movs pc, lr @ Return to the kernel +@ Requires dense and single-cluster CPU ID space +ENTRY(psci_get_cpu_id) + mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */ + and r0, r0, #0xff /* return CPU ID in cluster */ + bx lr +ENDPROC(psci_get_cpu_id) +.weak psci_get_cpu_id + +/* Imported from Linux kernel */ +LENTRY(v7_flush_dcache_all) + dmb @ ensure ordering with previous memory accesses + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished @ if loc is 0, then no need to clean + mov r10, #0 @ start clean at cache level 0 +flush_levels: + add r2, r10, r10, lsr #1 @ work out 3x current cache level + mov r1, r0, lsr r2 @ extract cache type bits from clidr + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt skip @ skip if no cache, or just i-cache + mrs r9, cpsr @ make cssr&csidr read atomic + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + isb @ isb to sych the new cssr&csidr + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + msr cpsr_c, r9 + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the way size + clz r5, r4 @ find bit position of way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the index size +loop1: + mov r9, r7 @ create working copy of max index +loop2: + orr r11, r10, r4, lsl r5 @ factor way and cache number into r11 + orr r11, r11, r9, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + subs r9, r9, #1 @ decrement the index + bge loop2 + subs r4, r4, #1 @ decrement the way + bge loop1 +skip: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt flush_levels +finished: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + dsb st + isb + bx lr +ENDPROC(v7_flush_dcache_all) + +ENTRY(psci_disable_smp) + mrc p15, 0, r0, c1, c0, 1 @ ACTLR + bic r0, r0, #(1 << 6) @ Clear SMP bit + mcr p15, 0, r0, c1, c0, 1 @ ACTLR + isb + dsb + bx lr +ENDPROC(psci_disable_smp) +.weak psci_disable_smp + +ENTRY(psci_enable_smp) + mrc p15, 0, r0, c1, c0, 1 @ ACTLR + orr r0, r0, #(1 << 6) @ Set SMP bit + mcr p15, 0, r0, c1, c0, 1 @ ACTLR + isb + bx lr +ENDPROC(psci_enable_smp) +.weak psci_enable_smp + +ENTRY(psci_cpu_off_common) + push {lr} + + mrc p15, 0, r0, c1, c0, 0 @ SCTLR + bic r0, r0, #(1 << 2) @ Clear C bit + mcr p15, 0, r0, c1, c0, 0 @ SCTLR + isb + dsb + + bl v7_flush_dcache_all + + clrex @ Why??? + + bl psci_disable_smp + + pop {lr} + bx lr +ENDPROC(psci_cpu_off_common) + +@ expects CPU ID in r0 and returns stack top in r0 +ENTRY(psci_get_cpu_stack_top) + mov r5, #0x400 @ 1kB of stack per CPU + mul r0, r0, r5 + + ldr r5, =psci_text_end @ end of monitor text + add r5, r5, #0x2000 @ Skip two pages + lsr r5, r5, #12 @ Align to start of page + lsl r5, r5, #12 + sub r5, r5, #4 @ reserve 1 word for target PC + sub r0, r5, r0 @ here's our stack! + + bx lr +ENDPROC(psci_get_cpu_stack_top) + +ENTRY(psci_cpu_entry) + bl psci_enable_smp + + bl _nonsec_init + + bl psci_get_cpu_id @ CPU ID => r0 + bl psci_get_cpu_stack_top @ stack top => r0 + ldr r0, [r0] @ target PC at stack top + b _do_nonsec_entry +ENDPROC(psci_cpu_entry) + .popsection diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig index 57dccec..ae23078 100644 --- a/arch/arm/cpu/armv7/rmobile/Kconfig +++ b/arch/arm/cpu/armv7/rmobile/Kconfig @@ -2,6 +2,7 @@ if RMOBILE choice prompt "Renesus ARM SoCs board select" + optional config TARGET_ARMADILLO_800EVA bool "armadillo 800 eva board" diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig index bc73813..04acdaa 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig +++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig @@ -2,6 +2,7 @@ if ARCH_S5PC1XX choice prompt "S5PC1XX board select" + optional config TARGET_S5P_GONI bool "S5P Goni board" diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk deleted file mode 100644 index 2a99c72..0000000 --- a/arch/arm/cpu/armv7/socfpga/config.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# -ifndef CONFIG_SPL_BUILD -ALL-y += u-boot.img -endif - -# Added for handoff support -PLATFORM_RELFLAGS += -Iboard/$(VENDOR)/$(BOARD) diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index 07b2d76..7ec0500 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -19,6 +19,7 @@ #include <config.h> #include <asm/gic.h> +#include <asm/macro.h> #include <asm/psci.h> #include <asm/arch/cpu.h> @@ -138,8 +139,11 @@ out: mcr p15, 0, r7, c1, c1, 0 @ r2 = target PC .globl psci_cpu_on psci_cpu_on: - adr r0, _target_pc - str r2, [r0] + push {lr} + + mov r0, r1 + bl psci_get_cpu_stack_top @ get stack top of target CPU + str r2, [r0] @ store target PC at stack top dsb movw r0, #(SUN7I_CPUCFG_BASE & 0xffff) @@ -150,7 +154,7 @@ psci_cpu_on: mov r4, #1 lsl r4, r4, r1 - adr r6, _sunxi_cpu_entry + ldr r6, =psci_cpu_entry str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector) @ Assert reset on target CPU @@ -194,88 +198,11 @@ psci_cpu_on: str r6, [r0, #0x1e4] mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS - mov pc, lr - -_target_pc: - .word 0 - -/* Imported from Linux kernel */ -v7_flush_dcache_all: - dmb @ ensure ordering with previous memory accesses - mrc p15, 1, r0, c0, c0, 1 @ read clidr - ands r3, r0, #0x7000000 @ extract loc from clidr - mov r3, r3, lsr #23 @ left align loc bit field - beq finished @ if loc is 0, then no need to clean - mov r10, #0 @ start clean at cache level 0 -flush_levels: - add r2, r10, r10, lsr #1 @ work out 3x current cache level - mov r1, r0, lsr r2 @ extract cache type bits from clidr - and r1, r1, #7 @ mask of the bits for current cache only - cmp r1, #2 @ see what cache we have at this level - blt skip @ skip if no cache, or just i-cache - mrs r9, cpsr @ make cssr&csidr read atomic - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - isb @ isb to sych the new cssr&csidr - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr - msr cpsr_c, r9 - and r2, r1, #7 @ extract the length of the cache lines - add r2, r2, #4 @ add 4 (line length offset) - ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 @ find maximum number on the way size - clz r5, r4 @ find bit position of way size increment - ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 @ extract max number of the index size -loop1: - mov r9, r7 @ create working copy of max index -loop2: - orr r11, r10, r4, lsl r5 @ factor way and cache number into r11 - orr r11, r11, r9, lsl r2 @ factor index number into r11 - mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way - subs r9, r9, #1 @ decrement the index - bge loop2 - subs r4, r4, #1 @ decrement the way - bge loop1 -skip: - add r10, r10, #2 @ increment cache number - cmp r3, r10 - bgt flush_levels -finished: - mov r10, #0 @ swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - dsb st - isb - bx lr - -_sunxi_cpu_entry: - @ Set SMP bit - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #0x40 - mcr p15, 0, r0, c1, c0, 1 - isb - - bl _nonsec_init - - adr r0, _target_pc - ldr r0, [r0] - b _do_nonsec_entry + pop {pc} .globl psci_cpu_off psci_cpu_off: - mrc p15, 0, r0, c1, c0, 0 @ SCTLR - bic r0, r0, #(1 << 2) @ Clear C bit - mcr p15, 0, r0, c1, c0, 0 @ SCTLR - isb - dsb - - bl v7_flush_dcache_all - - clrex @ Why??? - - mrc p15, 0, r0, c1, c0, 1 @ ACTLR - bic r0, r0, #(1 << 6) @ Clear SMP bit - mcr p15, 0, r0, c1, c0, 1 @ ACTLR - isb - dsb + bl psci_cpu_off_common @ Ask CPU0 to pull the rug... movw r0, #(GICD_BASE & 0xffff) @@ -290,6 +217,8 @@ psci_cpu_off: .globl psci_arch_init psci_arch_init: + mov r6, lr + movw r4, #(GICD_BASE & 0xffff) movt r4, #(GICD_BASE >> 16) @@ -315,18 +244,12 @@ psci_arch_init: mcr p15, 0, r5, c1, c1, 0 @ Write SCR isb - mrc p15, 0, r4, c0, c0, 5 @ MPIDR - and r4, r4, #3 @ cpu number in cluster - mov r5, #0x400 @ 1kB of stack per CPU - mul r4, r4, r5 - - adr r5, text_end @ end of text - add r5, r5, #0x2000 @ Skip two pages - lsr r5, r5, #12 @ Align to start of page - lsl r5, r5, #12 - sub sp, r5, r4 @ here's our stack! + bl psci_get_cpu_id @ CPU ID => r0 + bl psci_get_cpu_stack_top @ stack top => r0 + mov sp, r0 - bx lr + bx r6 -text_end: + .globl psci_text_end +psci_text_end: .popsection diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c index 9408e33..32c368f 100644 --- a/arch/arm/cpu/armv7/virt-dt.c +++ b/arch/arm/cpu/armv7/virt-dt.c @@ -16,6 +16,7 @@ */ #include <common.h> +#include <errno.h> #include <stdio_dev.h> #include <linux/ctype.h> #include <linux/types.h> @@ -88,9 +89,37 @@ static int fdt_psci(void *fdt) return 0; } +int armv7_apply_memory_carveout(u64 *start, u64 *size) +{ +#ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE + if (*start + *size < CONFIG_ARMV7_SECURE_BASE || + *start >= (u64)CONFIG_ARMV7_SECURE_BASE + + CONFIG_ARMV7_SECURE_RESERVE_SIZE) + return 0; + + /* carveout must be at the beginning or the end of the bank */ + if (*start == CONFIG_ARMV7_SECURE_BASE || + *start + *size == (u64)CONFIG_ARMV7_SECURE_BASE + + CONFIG_ARMV7_SECURE_RESERVE_SIZE) { + if (*size < CONFIG_ARMV7_SECURE_RESERVE_SIZE) { + debug("Secure monitor larger than RAM bank!?\n"); + return -EINVAL; + } + *size -= CONFIG_ARMV7_SECURE_RESERVE_SIZE; + if (*start == CONFIG_ARMV7_SECURE_BASE) + *start += CONFIG_ARMV7_SECURE_RESERVE_SIZE; + return 0; + } + debug("Secure monitor not located at beginning or end of RAM bank\n"); + return -EINVAL; +#else /* !CONFIG_ARMV7_SECURE_RESERVE_SIZE */ + return 0; +#endif +} + int psci_update_dt(void *fdt) { -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +#ifdef CONFIG_ARMV7_NONSEC if (!armv7_boot_nonsec()) return 0; #endif diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 4cb8806..9c53306 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -46,6 +46,10 @@ static unsigned long get_gicd_base_address(void) #endif } +/* Define a specific version of this function to enable any available + * hardware protections for the reserved region */ +void __weak protect_secure_section(void) {} + static void relocate_secure_section(void) { #ifdef CONFIG_ARMV7_SECURE_BASE @@ -54,6 +58,7 @@ static void relocate_secure_section(void) memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz); flush_dcache_range(CONFIG_ARMV7_SECURE_BASE, CONFIG_ARMV7_SECURE_BASE + sz + 1); + protect_secure_section(); invalidate_icache_all(); #endif } @@ -75,6 +80,10 @@ void __weak smp_kick_all_cpus(void) kick_secondary_cpus_gic(gic_dist_addr); } +__weak void psci_board_init(void) +{ +} + int armv7_init_nonsec(void) { unsigned int reg; @@ -112,6 +121,8 @@ int armv7_init_nonsec(void) for (i = 1; i <= itlinesnr; i++) writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); + psci_board_init(); + /* * Relocate secure section before any cpu runs in secure ram. * smp_kick_all_cpus may enable other cores and runs into secure diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 7336162..03cd9f6 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -25,7 +25,7 @@ SECTIONS *(.text*) } -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) || defined(CONFIG_ARMV7_PSCI) +#ifdef CONFIG_ARMV7_NONSEC #ifndef CONFIG_ARMV7_SECURE_BASE #define CONFIG_ARMV7_SECURE_BASE diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 15d60b9..267fd17 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -49,10 +49,11 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb -dtb-$(CONFIG_SOCFPGA) += \ +dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_socrates.dtb +dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ ls1021a-twr.dtb diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts index 582f6e5..415dfea 100644 --- a/arch/arm/dts/exynos4412-odroid.dts +++ b/arch/arm/dts/exynos4412-odroid.dts @@ -36,10 +36,263 @@ status = "okay"; max77686_pmic@09 { - compatible = "maxim,max77686_pmic"; + compatible = "maxim,max77686"; interrupts = <7 0>; reg = <0x09 0 0>; #clock-cells = <1>; + + voltage-regulators { + ldo1_reg: ldo1 { + regulator-compatible = "LDO1"; + regulator-name = "VDD_ALIVE_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo2_reg: ldo2 { + regulator-compatible = "LDO2"; + regulator-name = "VDDQ_VM1M2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3_reg: ldo3 { + regulator-compatible = "LDO3"; + regulator-name = "VCC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo4_reg: ldo4 { + regulator-compatible = "LDO4"; + regulator-name = "VDDQ_MMC2_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5_reg: ldo5 { + regulator-compatible = "LDO5"; + regulator-name = "VDDQ_MMC0/1/3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo6_reg: ldo6 { + regulator-compatible = "LDO6"; + regulator-name = "VMPLL_1.0V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + ldo7_reg: ldo7 { + regulator-compatible = "LDO7"; + regulator-name = "VPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + ldo8_reg: ldo8 { + regulator-compatible = "LDO8"; + regulator-name = "VDD_MIPI/HDMI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo9_reg: ldo9 { + regulator-compatible = "LDO9"; + regulator-name = "nc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo10_reg: ldo10 { + regulator-compatible = "LDO10"; + regulator-name = "VDD_MIPI/HDMI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo11_reg: ldo11 { + regulator-compatible = "LDO11"; + regulator-name = "VDD_ABB1_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo12_reg: ldo12 { + regulator-compatible = "LDO12"; + regulator-name = "VDD_UOTG_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo13_reg: ldo13 { + regulator-compatible = "LDO13"; + regulator-name = "VDD_C2C_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo14_reg: ldo14 { + regulator-compatible = "LDO14"; + regulator-name = "VDD_ABB02_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo15_reg: ldo15 { + regulator-compatible = "LDO15"; + regulator-name = "VDD_HSIC/OTG_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo16_reg: ldo16 { + regulator-compatible = "LDO16"; + regulator-name = "VDD_HSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo17_reg: ldo17 { + regulator-compatible = "LDO17"; + regulator-name = "VDDQ_CAM_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo18_reg: ldo18 { + regulator-compatible = "LDO18"; + regulator-name = "nc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: ldo19 { + regulator-compatible = "LDO19"; + regulator-name = "nc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo20_reg: ldo20 { + regulator-compatible = "LDO20"; + regulator-name = "VDDQ_EMMC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo21_reg: ldo21 { + regulator-compatible = "LDO21"; + regulator-name = "TFLASH_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo22_reg: ldo22 { + regulator-compatible = "LDO22"; + regulator-name = "VDDQ_EMMC_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo23_reg: ldo23 { + regulator-compatible = "LDO23"; + regulator-name = "nc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo24_reg: ldo24 { + regulator-compatible = "LDO24"; + regulator-name = "nc"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo25_reg: ldo25 { + regulator-compatible = "LDO25"; + regulator-name = "VDDQ_LCD_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo26_reg: ldo26 { + regulator-compatible = "LDO26"; + regulator-name = "nc"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + buck1_reg: buck@1 { + regulator-compatible = "BUCK1"; + regulator-name = "VDD_MIF_1.0V"; + regulator-min-microvolt = <8500000>; + regulator-max-microvolt = <1100000>; + }; + + buck2_reg: buck@2 { + regulator-compatible = "BUCK2"; + regulator-name = "VDD_ARM_1.0V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1500000>; + }; + + buck3_reg: buck3 { + regulator-compatible = "BUCK3"; + regulator-name = "VDD_INT_1.1V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + }; + + buck4_reg: buck4 { + regulator-compatible = "BUCK4"; + regulator-name = "VDD_G3D_1.0V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + }; + + buck5_reg: buck5 { + regulator-compatible = "BUCK5"; + regulator-name = "VDDQ_AP_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + buck6_reg: buck6 { + regulator-compatible = "BUCK6"; + regulator-name = "VCC_INL1/7_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + }; + + buck7_reg: buck7 { + regulator-compatible = "BUCK7"; + regulator-name = "VCC_INL2/3/5_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + }; + + buck8_reg: buck8 { + regulator-compatible = "BUCK8"; + regulator-name = "VCC_P3V3_2.85V"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + }; + + buck9_reg: buck9 { + regulator-compatible = "BUCK9"; + regulator-name = "nc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; }; }; diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts index dd238df..5c0bb91 100644 --- a/arch/arm/dts/exynos4412-trats2.dts +++ b/arch/arm/dts/exynos4412-trats2.dts @@ -41,7 +41,7 @@ status = "okay"; max77686_pmic@09 { - compatible = "maxim,max77686_pmic"; + compatible = "maxim,max77686"; interrupts = <7 0>; reg = <0x09 0 0>; #clock-cells = <1>; diff --git a/arch/arm/dts/exynos5250-smdk5250.dts b/arch/arm/dts/exynos5250-smdk5250.dts index 9273562..3cebfc2 100644 --- a/arch/arm/dts/exynos5250-smdk5250.dts +++ b/arch/arm/dts/exynos5250-smdk5250.dts @@ -68,7 +68,7 @@ i2c@12c60000 { pmic@9 { reg = <0x9>; - compatible = "maxim,max77686_pmic"; + compatible = "maxim,max77686"; }; }; diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts index e89a94f..e4b3dc2 100644 --- a/arch/arm/dts/exynos5250-snow.dts +++ b/arch/arm/dts/exynos5250-snow.dts @@ -108,7 +108,7 @@ i2c@12c60000 { pmic@9 { reg = <0x9>; - compatible = "maxim,max77686_pmic"; + compatible = "maxim,max77686"; }; }; diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 7d8fa28..6fe762d 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -79,7 +79,7 @@ i2c@12e10000 { /* i2c9 */ clock-frequency = <400000>; tpm@20 { - compatible = "infineon,slb9645-tpm"; + compatible = "infineon,slb9645tt"; reg = <0x20>; }; }; diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index 8c1f616..176ce55 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -72,7 +72,7 @@ i2c@12e10000 { /* i2c9 */ clock-frequency = <400000>; tpm@20 { - compatible = "infineon,slb9645-tpm"; + compatible = "infineon,slb9645tt"; reg = <0x20>; }; }; diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts new file mode 100644 index 0000000..b25c48b --- /dev/null +++ b/arch/arm/dts/stv0991.dts @@ -0,0 +1,23 @@ +/dts-v1/; + +/ { + model = "ST STV0991 application board"; + compatible = "st,stv0991"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + stdout-path = &uart0; + }; + + memory { + device_type="memory"; + reg = <0x0 0x198000>; + }; + + uart0: serial@0x80406000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80406000 0x1000>; + clock = <2700000>; + }; +}; diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts index 9367193..5a39e93 100644 --- a/arch/arm/dts/tegra124-nyan-big.dts +++ b/arch/arm/dts/tegra124-nyan-big.dts @@ -29,6 +29,35 @@ reg = <0x80000000 0x80000000>; }; + host1x@50000000 { + dc@54200000 { + display-timings { + timing@0 { + clock-frequency = <69500000>; + hactive = <1366>; + vactive = <768>; + hsync-len = <32>; + hfront-porch = <48>; + hback-porch = <20>; + vfront-porch = <3>; + vback-porch = <13>; + vsync-len = <6>; + }; + }; + }; + + sor@54540000 { + status = "okay"; + + nvidia,dpaux = <&dpaux>; + nvidia,panel = <&panel>; + }; + + dpaux@545c0000 { + status = "okay"; + }; + }; + serial@70006000 { /* Debug connector on the bottom of the board near SD card. */ status = "okay"; @@ -258,6 +287,7 @@ compatible = "pwm-backlight"; enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_led>; pwms = <&pwm 1 1000000>; default-brightness-level = <224>; @@ -310,6 +340,10 @@ }; }; + gpio@6000d000 { + u-boot,dm-pre-reloc; + }; + gpio-keys { compatible = "gpio-keys"; @@ -337,6 +371,19 @@ backlight = <&backlight>; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + vdd_led: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "+VDD_LED"; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + sound { compatible = "nvidia,tegra-audio-max98090-nyan-big", "nvidia,tegra-audio-max98090"; diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index 9fa141d..43b7f22 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -76,6 +76,85 @@ }; }; + host1x@50000000 { + compatible = "nvidia,tegra124-host1x", "simple-bus"; + reg = <0x50000000 0x00034000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ + clocks = <&tegra_car TEGRA124_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x01000000>; + + dc@54200000 { + compatible = "nvidia,tegra124-dc"; + reg = <0x54200000 0x00040000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_DISP1>, + <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; + + nvidia,head = <0>; + }; + + dc@54240000 { + compatible = "nvidia,tegra124-dc"; + reg = <0x54240000 0x00040000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_DISP2>, + <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; + + nvidia,head = <1>; + }; + + hdmi@54280000 { + compatible = "nvidia,tegra124-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_HDMI>, + <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; + status = "disabled"; + }; + + sor@54540000 { + compatible = "nvidia,tegra124-sor"; + reg = <0x54540000 0x00040000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SOR0>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, + <&tegra_car TEGRA124_CLK_PLL_DP>, + <&tegra_car TEGRA124_CLK_CLK_M>; + clock-names = "sor", "parent", "dp", "safe"; + resets = <&tegra_car 182>; + reset-names = "sor"; + status = "disabled"; + }; + + dpaux: dpaux@545c0000 { + compatible = "nvidia,tegra124-dpaux"; + reg = <0x545c0000 0x00040000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_DPAUX>, + <&tegra_car TEGRA124_CLK_PLL_DP>; + clock-names = "dpaux", "parent"; + resets = <&tegra_car 181>; + reset-names = "dpaux"; + status = "disabled"; + }; + }; + gic: interrupt-controller@50041000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; @@ -349,6 +428,11 @@ clocks = <&tegra_car 105>; }; + pmc@7000e400 { + compatible = "nvidia,tegra124-pmc"; + reg = <0x7000e400 0x400>; + }; + padctl: padctl@7009f000 { compatible = "nvidia,tegra124-xusb-padctl"; reg = <0x7009f000 0x1000>; diff --git a/arch/arm/imx-common/cmd_dek.c b/arch/arm/imx-common/cmd_dek.c index d93d5fb..ada8adf 100644 --- a/arch/arm/imx-common/cmd_dek.c +++ b/arch/arm/imx-common/cmd_dek.c @@ -14,6 +14,7 @@ #include <linux/compiler.h> #include <fsl_sec.h> #include <asm/arch/clock.h> +#include <mapmem.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/imx-common/i2c-mxv7.c b/arch/arm/imx-common/i2c-mxv7.c index 1a632e7..f3a5c3f 100644 --- a/arch/arm/imx-common/i2c-mxv7.c +++ b/arch/arm/imx-common/i2c-mxv7.c @@ -12,7 +12,7 @@ #include <asm/imx-common/mxc_i2c.h> #include <watchdog.h> -static int force_idle_bus(void *priv) +int force_idle_bus(void *priv) { int i; int sda, scl; @@ -99,8 +99,9 @@ int setup_i2c(unsigned i2c_index, int speed, int slave_addr, if (ret) goto err_idle; - bus_i2c_init(i2c_bases[i2c_index], speed, slave_addr, - force_idle_bus, p); +#ifndef CONFIG_DM_I2C + bus_i2c_init(i2c_index, speed, slave_addr, force_idle_bus, p); +#endif return 0; diff --git a/arch/arm/include/asm/arch-mx27/gpio.h b/arch/arm/include/asm/arch-mx27/gpio.h index 1e38b93..a8a1ed6 100644 --- a/arch/arm/include/asm/arch-mx27/gpio.h +++ b/arch/arm/include/asm/arch-mx27/gpio.h @@ -36,4 +36,24 @@ struct gpio_port_regs { struct gpio_regs port[6]; }; +/* + * GPIO Module and I/O Multiplexer + */ +#define PORTA 0 +#define PORTB 1 +#define PORTC 2 +#define PORTD 3 +#define PORTE 4 +#define PORTF 5 + +#define GPIO_PIN_MASK 0x1f +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) +#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT) +#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT) +#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT) +#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT) +#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT) +#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT) + #endif diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index 92c847e..7402e31 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -138,16 +138,6 @@ struct gpt_regs { u32 gpt_tstat; }; -/* - * GPIO Module and I/O Multiplexer - */ -#define PORTA 0 -#define PORTB 1 -#define PORTC 2 -#define PORTD 3 -#define PORTE 4 -#define PORTF 5 - /* IIM Control Registers */ struct iim_regs { u32 iim_stat; @@ -449,18 +439,6 @@ struct fuse_bank0_regs { #define GPIO5_BASE_ADDR 0x10015400 #define GPIO6_BASE_ADDR 0x10015500 -#define GPIO_PIN_MASK 0x1f - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) - -#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT) -#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT) -#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT) -#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT) -#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT) -#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT) - #define GPIO_OUT (1 << 8) #define GPIO_IN (0 << 8) #define GPIO_PUEN (1 << 9) diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h index 7cd866e..dd33b96 100644 --- a/arch/arm/include/asm/arch-stm32f4/gpio.h +++ b/arch/arm/include/asm/arch-stm32f4/gpio.h @@ -11,6 +11,38 @@ #ifndef _STM32_GPIO_H_ #define _STM32_GPIO_H_ +#if (CONFIG_STM32_USART == 1) +#define STM32_GPIO_PORT_X STM32_GPIO_PORT_A +#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_9 +#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_10 +#define STM32_GPIO_USART STM32_GPIO_AF7 + +#elif (CONFIG_STM32_USART == 2) +#define STM32_GPIO_PORT_X STM32_GPIO_PORT_D +#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_5 +#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_6 +#define STM32_GPIO_USART STM32_GPIO_AF7 + +#elif (CONFIG_STM32_USART == 3) +#define STM32_GPIO_PORT_X STM32_GPIO_PORT_C +#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_10 +#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_11 +#define STM32_GPIO_USART STM32_GPIO_AF7 + +#elif (CONFIG_STM32_USART == 6) +#define STM32_GPIO_PORT_X STM32_GPIO_PORT_G +#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_14 +#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_9 +#define STM32_GPIO_USART STM32_GPIO_AF8 + +#else +#define STM32_GPIO_PORT_X STM32_GPIO_PORT_A +#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_9 +#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_10 +#define STM32_GPIO_USART STM32_GPIO_AF7 + +#endif + enum stm32_gpio_port { STM32_GPIO_PORT_A = 0, STM32_GPIO_PORT_B, diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index c28ee05..63c3319 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -320,6 +320,8 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY0_RST (0x1 << 0) #define CCM_USB_CTRL_PHY1_RST (0x1 << 1) #define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 6) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 7) #define CCM_USB_CTRL_PHYGATE (0x1 << 8) /* These 3 are sun6i only, define them as 0 on sun4i */ #define CCM_USB_CTRL_PHY0_CLK 0 diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 04c6d58..bacd70a 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -246,6 +246,8 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) #define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 #define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 7d28e16..de50e08 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -202,9 +202,13 @@ struct clk_rst_ctlr { uint crc_reserved52[1]; /* _reserved_52, 0x554 */ uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */ - - /* Tegra124 - skip to 0x600 here for new CLK_SOURCE_ regs */ - uint crc_reserved60[40]; /* _reserved_60, 0x560 - 0x5FC */ + u32 _rsv32[4]; /* 0x560-0x56c */ + u32 crc_plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ + u32 _rsv32_1[7]; /* 0x574-58c */ + struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */ + u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ + u32 _rsrv32_2[25]; + /* Tegra124 */ uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */ }; @@ -440,4 +444,9 @@ enum { #define PLLX_IDDQ_SHIFT 3 #define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT) +/* CLK_RST_PLLDP_SS_CFG */ +#define PLLDP_SS_CFG_CLAMP (1 << 22) +#define PLLDP_SS_CFG_UNDOCUMENTED (1 << 24) +#define PLLDP_SS_CFG_DITHER (1 << 28) + #endif /* _TEGRA_CLK_RST_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 9d8114c..04011ae 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -156,6 +156,17 @@ void reset_cmplx_set_enable(int cpu, int which, int reset); void clock_ll_set_source(enum periph_id periph_id, unsigned source); /** + * This function is similar to clock_ll_set_source() except that it can be + * used for clocks with more than 2 mux bits. + * + * @param periph_id peripheral to adjust + * @param mux_bits number of mux bits for the clock + * @param source source clock (0-15 depending on mux_bits) + */ +int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits, + unsigned source); + +/** * Set the source and divisor for a peripheral clock. This sets the * clock rate. You need to look up the datasheet to see the meaning of the * source parameter as it changes for each peripheral. @@ -265,6 +276,9 @@ void clock_early_init(void); /* Returns a pointer to the clock source register for a peripheral */ u32 *get_periph_source_reg(enum periph_id periph_id); +/* Returns a pointer to the given 'simple' PLL */ +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid); + /** * Given a peripheral ID and the required source clock, this returns which * value should be programmed into the source mux for that peripheral. diff --git a/arch/arm/include/asm/arch-tegra20/dc.h b/arch/arm/include/asm/arch-tegra/dc.h index 20790b6..6ffb468 100644 --- a/arch/arm/include/asm/arch-tegra20/dc.h +++ b/arch/arm/include/asm/arch-tegra/dc.h @@ -234,7 +234,7 @@ struct dc_disp_reg { uint cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */ uint seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */ - /* Address 0x442 ~ 0x446 */ + /* Address 0x443 ~ 0x446 */ uint spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */ uint spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */ uint spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */ @@ -254,6 +254,11 @@ struct dc_disp_reg { /* Address 0x4c0 ~ 0x4c1 */ uint dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */ uint disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */ + + u32 rsvd_4c2[34]; /* 4c2 - 4e3 */ + + /* Address 0x4e4 */ + u32 blend_background_color; /* _DISP_BLEND_BACKGROUND_COLOR_0 */ }; enum dc_winc_filter_p { @@ -289,9 +294,9 @@ struct dc_winc_reg { uint v_filter_p[WINC_FILTER_COUNT]; }; -/* WIN A/B/C Register 0x700 ~ 0x714*/ +/* WIN A/B/C Register 0x700 ~ 0x719*/ struct dc_win_reg { - /* Address 0x700 ~ 0x714 */ + /* Address 0x700 ~ 0x719 */ uint win_opt; /* _WIN_WIN_OPTIONS_0 */ uint byte_swap; /* _WIN_BYTE_SWAP_0 */ uint buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */ @@ -313,11 +318,16 @@ struct dc_win_reg { uint blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */ uint blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */ uint hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */ + uint global_alpha; /* _WIN_GLOBAL_ALPHA */ + uint blend_layer_ctrl; /* _WINBUF_BLEND_LAYER_CONTROL_0 */ + uint blend_match_select; /* _WINBUF_BLEND_MATCH_SELECT_0 */ + uint blend_nomatch_select; /* _WINBUF_BLEND_NOMATCH_SELECT_0 */ + uint blend_alpha_1bit; /* _WINBUF_BLEND_ALPHA_1BIT_0 */ }; -/* WINBUF A/B/C Register 0x800 ~ 0x80a */ +/* WINBUF A/B/C Register 0x800 ~ 0x80d */ struct dc_winbuf_reg { - /* Address 0x800 ~ 0x80a */ + /* Address 0x800 ~ 0x80d */ uint start_addr; /* _WINBUF_START_ADDR_0 */ uint start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */ uint start_addr_u; /* _WINBUF_START_ADDR_U_0 */ @@ -329,6 +339,9 @@ struct dc_winbuf_reg { uint addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */ uint addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */ uint uflow_status; /* _WINBUF_UFLOW_STATUS_0 */ + uint buffer_surface_kind; /* DC_WIN_BUFFER_SURFACE_KIND */ + uint rsvd_80c; + uint start_addr_hi; /* DC_WINBUF_START_ADDR_HI_0 */ }; /* Display Controller (DC_) regs */ @@ -339,16 +352,16 @@ struct dc_ctlr { struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */ uint reserved1[0xd6]; - struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4c1 */ - uint reserved2[0x3e]; + struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4e4 */ + uint reserved2[0x1b]; struct dc_winc_reg winc; /* Window A/B/C 0x500 ~ 0x628 */ uint reserved3[0xd7]; - struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x714*/ - uint reserved4[0xeb]; + struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x719*/ + uint reserved4[0xe6]; - struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80a */ + struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */ }; #define BIT(pos) (1U << pos) @@ -399,20 +412,45 @@ enum win_color_depth_id { #define SPI_ENABLE BIT(24) #define HSPI_ENABLE BIT(25) +/* DC_CMD_STATE_ACCESS 0x040 */ +#define READ_MUX_ASSEMBLY (0 << 0) +#define READ_MUX_ACTIVE (1 << 0) +#define WRITE_MUX_ASSEMBLY (0 << 2) +#define WRITE_MUX_ACTIVE (1 << 2) + /* DC_CMD_STATE_CONTROL 0x041 */ #define GENERAL_ACT_REQ BIT(0) #define WIN_A_ACT_REQ BIT(1) #define WIN_B_ACT_REQ BIT(2) #define WIN_C_ACT_REQ BIT(3) +#define WIN_D_ACT_REQ BIT(4) +#define WIN_H_ACT_REQ BIT(5) +#define CURSOR_ACT_REQ BIT(7) #define GENERAL_UPDATE BIT(8) #define WIN_A_UPDATE BIT(9) #define WIN_B_UPDATE BIT(10) #define WIN_C_UPDATE BIT(11) +#define WIN_D_UPDATE BIT(12) +#define WIN_H_UPDATE BIT(13) +#define CURSOR_UPDATE BIT(15) +#define NC_HOST_TRIG BIT(24) /* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */ #define WINDOW_A_SELECT BIT(4) #define WINDOW_B_SELECT BIT(5) #define WINDOW_C_SELECT BIT(6) +#define WINDOW_D_SELECT BIT(7) +#define WINDOW_H_SELECT BIT(8) + +/* DC_DISP_DISP_WIN_OPTIONS 0x402 */ +#define CURSOR_ENABLE BIT(16) +#define SOR_ENABLE BIT(25) +#define TVO_ENABLE BIT(28) +#define DSI_ENABLE BIT(29) +#define HDMI_ENABLE BIT(30) + +/* DC_DISP_DISP_TIMING_OPTIONS 0x405 */ +#define VSYNC_H_POSITION(x) ((x) & 0xfff) /* DC_DISP_DISP_CLOCK_CONTROL 0x42e */ #define SHIFT_CLK_DIVIDER_SHIFT 0 @@ -526,4 +564,13 @@ enum { #define V_DDA_INC_SHIFT 16 #define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT) +#define DC_POLL_TIMEOUT_MS 50 +#define DC_N_WINDOWS 5 +#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5) + +struct display_timing; + +int display_init(void *lcdbase, int fb_bits_per_pixel, + struct display_timing *timing); + #endif /* __ASM_ARCH_TEGRA_DC_H */ diff --git a/arch/arm/include/asm/arch-tegra/powergate.h b/arch/arm/include/asm/arch-tegra/powergate.h index 130b58b..2e491f1 100644 --- a/arch/arm/include/asm/arch-tegra/powergate.h +++ b/arch/arm/include/asm/arch-tegra/powergate.h @@ -33,6 +33,7 @@ enum tegra_powergate { int tegra_powergate_sequence_power_up(enum tegra_powergate id, enum periph_id periph); +int tegra_powergate_power_on(enum tegra_powergate id); int tegra_powergate_power_off(enum tegra_powergate id); #endif diff --git a/arch/arm/include/asm/arch-tegra/pwm.h b/arch/arm/include/asm/arch-tegra/pwm.h new file mode 100644 index 0000000..92dced4 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/pwm.h @@ -0,0 +1,60 @@ +/* + * Tegra pulse width frequency modulator definitions + * + * Copyright (c) 2011 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_TEGRA_PWM_H +#define __ASM_ARCH_TEGRA_PWM_H + +/* This is a single PWM channel */ +struct pwm_ctlr { + uint control; /* Control register */ + uint reserved[3]; /* Space space */ +}; + +#define PWM_NUM_CHANNELS 4 + +/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */ +#define PWM_ENABLE_SHIFT 31 +#define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT) + +#define PWM_WIDTH_SHIFT 16 +#define PWM_WIDTH_MASK (0x7FFF << PWM_WIDTH_SHIFT) + +#define PWM_DIVIDER_SHIFT 0 +#define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT) + +/** + * Program the PWM with the given parameters. + * + * @param channel PWM channel to update + * @param rate Clock rate to use for PWM, or 0 to leave alone + * @param pulse_width high pulse width: 0=always low, 1=1/256 pulse high, + * n = n/256 pulse high + * @param freq_divider frequency divider value (1 to use rate as is) + */ +void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider); + +/** + * Request a pwm channel as referenced by a device tree node. + * + * This channel can then be passed to pwm_enable(). + * + * @param blob Device tree blob + * @param node Node containing reference to pwm + * @param prop_name Property name of pwm reference + * @return channel number, if ok, else -1 + */ +int pwm_request(const void *blob, int node, const char *prop_name); + +/** + * Set up the pwm controller, by looking it up in the fdt. + * + * @return 0 if ok, -1 if the device tree node was not found or invalid. + */ +int pwm_init(const void *blob); + +#endif /* __ASM_ARCH_TEGRA_PWM_H */ diff --git a/arch/arm/include/asm/arch-tegra/sys_proto.h b/arch/arm/include/asm/arch-tegra/sys_proto.h index 8b3fbe1..83f9f47 100644 --- a/arch/arm/include/asm/arch-tegra/sys_proto.h +++ b/arch/arm/include/asm/arch-tegra/sys_proto.h @@ -8,12 +8,21 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -struct tegra_sysinfo { - char *board_string; -}; - void invalidate_dcache(void); -extern const struct tegra_sysinfo sysinfo; +/** + * tegra_board_id() - Get the board iD + * + * @return a board ID, or -ve on error + */ +int tegra_board_id(void); + +/** + * tegra_lcd_pmic_init() - Set up the PMIC for a board + * + * @board_id: Board ID which may be used to select LCD type + * @return 0 if OK, -ve on error + */ +int tegra_lcd_pmic_init(int board_id); #endif diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h index daf9a2b..7005855 100644 --- a/arch/arm/include/asm/arch-tegra124/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h @@ -25,6 +25,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DP, /* Special for Tegra124 */ /* These are the base clocks (inputs to the Tegra SoC) */ CLOCK_ID_32KHZ, @@ -424,7 +425,7 @@ enum periphc_internal_id { /* 0x58 */ PERIPHC_58h, - PERIPHC_59h, + PERIPHC_SOR, PERIPHC_5ah, PERIPHC_5bh, PERIPHC_SATAOOB, diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h index 8e65086..e202cc5 100644 --- a/arch/arm/include/asm/arch-tegra124/clock.h +++ b/arch/arm/include/asm/arch-tegra124/clock.h @@ -16,6 +16,27 @@ #define OSC_FREQ_SHIFT 28 #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) +/* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */ +#define SOR0_CLK_SEL0 (1 << 14) +#define SOR0_CLK_SEL1 (1 << 15) + int tegra_plle_enable(void); +void clock_sor_enable_edp_clock(void); + +/** + * clock_set_display_rate() - Set the display clock rate + * + * @frequency: the requested PLLD frequency + * + * Return the PLLD frequenc (which may not quite what was requested), or 0 + * on failure + */ +u32 clock_set_display_rate(u32 frequency); + +/** + * clock_set_up_plldp() - Set up the EDP clock ready for use + */ +void clock_set_up_plldp(void); + #endif /* _TEGRA124_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/display.h b/arch/arm/include/asm/arch-tegra124/display.h new file mode 100644 index 0000000..ca6644a --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/display.h @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2010 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_TEGRA_DISPLAY_H +#define __ASM_ARCH_TEGRA_DISPLAY_H + +/** + * Register a new display based on device tree configuration. + * + * The frame buffer can be positioned by U-Boot or overriden by the fdt. + * You should pass in the U-Boot address here, and check the contents of + * struct fdt_disp_config to see what was actually chosen. + * + * @param blob Device tree blob + * @param default_lcd_base Default address of LCD frame buffer + * @return 0 if ok, -1 on error (unsupported bits per pixel) + */ +int tegra_display_probe(const void *blob, void *default_lcd_base); + +/** + * Return the current display configuration + * + * @return pointer to display configuration, or NULL if there is no valid + * config + */ +struct fdt_disp_config *tegra_display_get_config(void); + +/** + * Perform the next stage of the LCD init if it is time to do so. + * + * LCD init can be time-consuming because of the number of delays we need + * while waiting for the backlight power supply, etc. This function can + * be called at various times during U-Boot operation to advance the + * initialization of the LCD to the next stage if sufficient time has + * passed since the last stage. It keeps track of what stage it is up to + * and the time that it is permitted to move to the next stage. + * + * The final call should have wait=1 to complete the init. + * + * @param blob fdt blob containing LCD information + * @param wait 1 to wait until all init is complete, and then return + * 0 to return immediately, potentially doing nothing if it is + * not yet time for the next init. + */ +int tegra_lcd_check_next_stage(const void *blob, int wait); + +/** + * Set up the maximum LCD size so we can size the frame buffer. + * + * @param blob fdt blob containing LCD information + */ +void tegra_lcd_early_init(const void *blob); + +#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h index 0db1881..d6f515f 100644 --- a/arch/arm/include/asm/arch-tegra124/flow.h +++ b/arch/arm/include/asm/arch-tegra124/flow.h @@ -37,4 +37,10 @@ struct flow_ctlr { /* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ #define ACTIVE_LP (1 << 0) +/* CPUn_CSR_0 */ +#define CSR_ENABLE (1 << 0) +#define CSR_IMMEDIATE_WAKE (1 << 3) +#define CSR_WAIT_WFI_SHIFT 8 +#define CSR_PWR_OFF_STS (1 << 16) + #endif /* _TEGRA124_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h index d526dfe..37998a4 100644 --- a/arch/arm/include/asm/arch-tegra124/mc.h +++ b/arch/arm/include/asm/arch-tegra124/mc.h @@ -35,14 +35,47 @@ struct mc_ctlr { u32 mc_emem_adr_cfg; /* offset 0x54 */ u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ - u32 reserved3[12]; /* offset 0x60 - 0x8C */ + u32 reserved3[4]; /* offset 0x60 - 0x6C */ + u32 mc_security_cfg0; /* offset 0x70 */ + u32 mc_security_cfg1; /* offset 0x74 */ + u32 reserved4[6]; /* offset 0x7C - 0x8C */ u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ - u32 reserved4[338]; /* offset 0x100 - 0x644 */ + u32 reserved5[74]; /* offset 0x100 - 0x224 */ + u32 mc_smmu_translation_enable_0; /* offset 0x228 */ + u32 mc_smmu_translation_enable_1; /* offset 0x22C */ + u32 mc_smmu_translation_enable_2; /* offset 0x230 */ + u32 mc_smmu_translation_enable_3; /* offset 0x234 */ + u32 mc_smmu_afi_asid; /* offset 0x238 */ + u32 mc_smmu_avpc_asid; /* offset 0x23C */ + u32 mc_smmu_dc_asid; /* offset 0x240 */ + u32 mc_smmu_dcb_asid; /* offset 0x244 */ + u32 reserved6[2]; /* offset 0x248 - 0x24C */ + u32 mc_smmu_hc_asid; /* offset 0x250 */ + u32 mc_smmu_hda_asid; /* offset 0x254 */ + u32 mc_smmu_isp2_asid; /* offset 0x258 */ + u32 reserved7[2]; /* offset 0x25C - 0x260 */ + u32 mc_smmu_msenc_asid; /* offset 0x264 */ + u32 mc_smmu_nv_asid; /* offset 0x268 */ + u32 mc_smmu_nv2_asid; /* offset 0x26C */ + u32 mc_smmu_ppcs_asid; /* offset 0x270 */ + u32 mc_smmu_sata_asid; /* offset 0x274 */ + u32 reserved8[1]; /* offset 0x278 */ + u32 mc_smmu_vde_asid; /* offset 0x27C */ + u32 mc_smmu_vi_asid; /* offset 0x280 */ + u32 mc_smmu_vic_asid; /* offset 0x284 */ + u32 mc_smmu_xusb_host_asid; /* offset 0x288 */ + u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */ + u32 reserved9[1]; /* offset 0x290 */ + u32 mc_smmu_tsec_asid; /* offset 0x294 */ + u32 mc_smmu_ppcs1_asid; /* offset 0x298 */ + u32 reserved10[235]; /* offset 0x29C - 0x644 */ u32 mc_video_protect_bom; /* offset 0x648 */ u32 mc_video_protect_size_mb; /* offset 0x64c */ u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ }; +#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) + #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) diff --git a/arch/arm/include/asm/arch-tegra124/pwm.h b/arch/arm/include/asm/arch-tegra124/pwm.h new file mode 100644 index 0000000..3d2c432 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra124/pwm.h @@ -0,0 +1,14 @@ +/* + * Tegra pulse width frequency modulator definitions + * + * Copyright (c) 2011 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_TEGRA124_PWM_H +#define __ASM_ARCH_TEGRA124_PWM_H + +#include <asm/arch-tegra/pwm.h> + +#endif /* __ASM_ARCH_TEGRA124_PWM_H */ diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h index 6feeda3..018c9f9 100644 --- a/arch/arm/include/asm/arch-tegra20/display.h +++ b/arch/arm/include/asm/arch-tegra20/display.h @@ -8,7 +8,7 @@ #ifndef __ASM_ARCH_TEGRA_DISPLAY_H #define __ASM_ARCH_TEGRA_DISPLAY_H -#include <asm/arch/dc.h> +#include <asm/arch-tegra/dc.h> #include <fdtdec.h> #include <asm/gpio.h> diff --git a/arch/arm/include/asm/arch-tegra20/pwm.h b/arch/arm/include/asm/arch-tegra20/pwm.h index 8e7397d..2207d9c 100644 --- a/arch/arm/include/asm/arch-tegra20/pwm.h +++ b/arch/arm/include/asm/arch-tegra20/pwm.h @@ -6,55 +6,9 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __ASM_ARCH_TEGRA_PWM_H -#define __ASM_ARCH_TEGRA_PWM_H +#ifndef __ASM_ARCH_TEGRA20_PWM_H +#define __ASM_ARCH_TEGRA20_PWM_H -/* This is a single PWM channel */ -struct pwm_ctlr { - uint control; /* Control register */ - uint reserved[3]; /* Space space */ -}; +#include <asm/arch-tegra/pwm.h> -#define PWM_NUM_CHANNELS 4 - -/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */ -#define PWM_ENABLE_SHIFT 31 -#define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT) - -#define PWM_WIDTH_SHIFT 16 -#define PWM_WIDTH_MASK (0x7FFF << PWM_WIDTH_SHIFT) - -#define PWM_DIVIDER_SHIFT 0 -#define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT) - -/** - * Program the PWM with the given parameters. - * - * @param channel PWM channel to update - * @param rate Clock rate to use for PWM - * @param pulse_width high pulse width: 0=always low, 1=1/256 pulse high, - * n = n/256 pulse high - * @param freq_divider frequency divider value (1 to use rate as is) - */ -void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider); - -/** - * Request a pwm channel as referenced by a device tree node. - * - * This channel can then be passed to pwm_enable(). - * - * @param blob Device tree blob - * @param node Node containing reference to pwm - * @param prop_name Property name of pwm reference - * @return channel number, if ok, else -1 - */ -int pwm_request(const void *blob, int node, const char *prop_name); - -/** - * Set up the pwm controller, by looking it up in the fdt. - * - * @return 0 if ok, -1 if the device tree node was not found or invalid. - */ -int pwm_init(const void *blob); - -#endif /* __ASM_ARCH_TEGRA_PWM_H */ +#endif /* __ASM_ARCH_TEGRA20_PWM_H */ diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index cbe7dc1..30e7939 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -131,9 +131,10 @@ void v7_outer_cache_inval_all(void); void v7_outer_cache_flush_range(u32 start, u32 end); void v7_outer_cache_inval_range(u32 start, u32 end); -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +#ifdef CONFIG_ARMV7_NONSEC int armv7_init_nonsec(void); +int armv7_apply_memory_carveout(u64 *start, u64 *size); bool armv7_boot_nonsec(void); /* defined in assembly file */ @@ -145,7 +146,7 @@ void _smp_pen(void); extern char __secure_start[]; extern char __secure_end[]; -#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */ +#endif /* CONFIG_ARMV7_NONSEC */ void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, u32 cpu_rev_comb, u32 cpu_variant, diff --git a/arch/arm/include/asm/imx-common/mxc_i2c.h b/arch/arm/include/asm/imx-common/mxc_i2c.h index af86163..355b25e 100644 --- a/arch/arm/include/asm/imx-common/mxc_i2c.h +++ b/arch/arm/include/asm/imx-common/mxc_i2c.h @@ -19,6 +19,36 @@ struct i2c_pads_info { struct i2c_pin_ctrl sda; }; +/* + * Information about i2c controller + * struct mxc_i2c_bus - information about the i2c[x] bus + * @index: i2c bus index + * @base: Address of I2C bus controller + * @driver_data: Flags for different platforms, such as I2C_QUIRK_FLAG. + * @speed: Speed of I2C bus + * @pads_info: pinctrl info for this i2c bus, will be used when pinctrl is ok. + * The following two is only to be compatible with non-DM part. + * @idle_bus_fn: function to force bus idle + * @idle_bus_data: parameter for idle_bus_fun + */ +struct mxc_i2c_bus { + /* + * board file can use this index to locate which i2c_pads_info is for + * i2c_idle_bus. When pinmux is implement, this entry can be + * discarded. Here we do not use dev->seq, because we do not want to + * export device to board file. + */ + int index; + ulong base; + ulong driver_data; + int speed; + struct i2c_pads_info *pads_info; +#ifndef CONFIG_DM_I2C + int (*idle_bus_fn)(void *p); + void *idle_bus_data; +#endif +}; + #if defined(CONFIG_MX6QDL) #define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \ struct i2c_pads_info mx6q_##name = { \ @@ -54,10 +84,8 @@ struct i2c_pads_info { int setup_i2c(unsigned i2c_index, int speed, int slave_addr, struct i2c_pads_info *p); -void bus_i2c_init(void *base, int speed, int slave_addr, +void bus_i2c_init(int index, int speed, int slave_addr, int (*idle_bus_fn)(void *p), void *p); -int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, - int len); -int bus_i2c_write(void *base, uchar chip, uint addr, int alen, - const uchar *buf, int len); +int force_idle_bus(void *priv); +int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus); #endif diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index ddc245b..de7650e 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -16,6 +16,8 @@ #define L2X0_STNDBY_MODE_EN (1 << 0) #define L2X0_CTRL_EN 1 +#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) + struct pl310_regs { u32 pl310_cache_id; u32 pl310_cache_type; diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index 50a3ca4..128a606 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -34,6 +34,7 @@ #ifndef __ASSEMBLY__ int psci_update_dt(void *fdt); +void psci_board_init(void); #endif /* ! __ASSEMBLY__ */ #endif /* __ARM_PSCI_H__ */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 9cd2f1e..760e8ab 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -77,6 +77,7 @@ void armv8_switch_to_el1(void); void gic_init(void); void gic_send_sgi(unsigned long sgino); void wait_for_wakeup(void); +void protect_secure_region(void); void smp_kick_all_cpus(void); void flush_l3_cache(void); @@ -158,6 +159,22 @@ void flush_l3_cache(void); * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3); */ +/** + * save_boot_params_ret() - Return from save_boot_params() + * + * If you provide save_boot_params(), then you should jump back to this + * function when done. Try to preserve all registers. + * + * If your implementation of save_boot_params() is in C then it is acceptable + * to simply call save_boot_params_ret() at the end of your function. Since + * there is no link register set up, you cannot just exit the function. U-Boot + * will return to the (initialised) value of lr, and likely crash/hang. + * + * If your implementation of save_boot_params() is in assembler then you + * should use 'b' or 'bx' to return to save_boot_params_ret. + */ +void save_boot_params_ret(void); + #define isb() __asm__ __volatile__ ("" : : : "memory") #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 665a3bc..7677358 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -17,6 +17,9 @@ #include <common.h> #include <fdt_support.h> +#ifdef CONFIG_ARMV7_NONSEC +#include <asm/armv7.h> +#endif #include <asm/psci.h> DECLARE_GLOBAL_DATA_PTR; @@ -31,10 +34,15 @@ int arch_fixup_fdt(void *blob) for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { start[bank] = bd->bi_dram[bank].start; size[bank] = bd->bi_dram[bank].size; +#ifdef CONFIG_ARMV7_NONSEC + ret = armv7_apply_memory_carveout(&start[bank], &size[bank]); + if (ret) + return ret; +#endif } ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +#ifdef CONFIG_ARMV7_NONSEC if (ret) return ret; diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index b1bff8c..ee56d74 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -26,7 +26,7 @@ #include <bootm.h> #include <vxworks.h> -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +#ifdef CONFIG_ARMV7_NONSEC #include <asm/armv7.h> #endif @@ -238,7 +238,7 @@ static void boot_prep_linux(bootm_headers_t *images) } } -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +#ifdef CONFIG_ARMV7_NONSEC bool armv7_boot_nonsec(void) { char *s = getenv("bootm_boot_mode"); @@ -305,7 +305,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) r2 = gd->bd->bi_boot_params; if (!fake) { -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +#ifdef CONFIG_ARMV7_NONSEC if (armv7_boot_nonsec()) { armv7_init_nonsec(); secure_ram_addr(_do_nonsec_entry)(kernel_entry, diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index b660a5b..bbf4228 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -2,6 +2,7 @@ if ARCH_AT91 choice prompt "Atmel AT91 board select" + optional config TARGET_AT91RM9200EK bool "Atmel AT91RM9200 evaluation kit" @@ -23,10 +24,6 @@ config TARGET_ETHERNUT5 bool "Ethernut5 board" select CPU_ARM926EJS -config TARGET_TNY_A9260 - bool "Caloa TNY A9260 board" - select CPU_ARM926EJS - config TARGET_SNAPPER9260 bool "Support snapper9260" select CPU_ARM926EJS @@ -34,10 +31,6 @@ config TARGET_SNAPPER9260 select DM_SERIAL select DM_GPIO -config TARGET_AFEB9260 - bool "Support afeb9260" - select CPU_ARM926EJS - config TARGET_AT91SAM9261EK bool "Atmel at91sam9261 reference board" select CPU_ARM926EJS @@ -58,10 +51,6 @@ config TARGET_PM9263 bool "Ronetix pm9263 board" select CPU_ARM926EJS -config TARGET_SBC35_A9G20 - bool "Support sbc35_a9g20" - select CPU_ARM926EJS - config TARGET_STAMP9G20 bool "Support stamp9g20" select CPU_ARM926EJS @@ -154,11 +143,8 @@ source "board/atmel/sama5d4_xplained/Kconfig" source "board/atmel/sama5d4ek/Kconfig" source "board/BuS/eb_cpux9k2/Kconfig" source "board/eukrea/cpuat91/Kconfig" -source "board/afeb9260/Kconfig" source "board/bluewater/snapper9260/Kconfig" source "board/BuS/vl_ma2sc/Kconfig" -source "board/calao/sbc35_a9g20/Kconfig" -source "board/calao/tny_a9260/Kconfig" source "board/calao/usb_a9263/Kconfig" source "board/egnite/ethernut5/Kconfig" source "board/esd/meesc/Kconfig" diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c index efb53d6..5e0c0f5 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c @@ -166,7 +166,7 @@ void at91_macb_hw_init(void) at91_set_b_periph(AT91_PIO_PORTA, 25, 0); /* ERX2 */ at91_set_b_periph(AT91_PIO_PORTA, 26, 0); /* ERX3 */ at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ERXCK */ -#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260) +#if defined(CONFIG_AT91SAM9260EK) /* * use PA10, PA11 for ETX2, ETX3. * PA23 and PA24 are for TWI EEPROM diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index c740180..99779df 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -3,6 +3,7 @@ menu "Broadcom BCM283X family" choice prompt "Broadcom BCM283X board select" + optional config TARGET_RPI bool "Raspberry Pi" diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 3ef55d3..e6cb390 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -2,6 +2,7 @@ if ARCH_DAVINCI choice prompt "DaVinci board select" + optional config TARGET_ENBW_CMC bool "EnBW CMC board" diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index 8ffc544..c54d69d 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig @@ -3,6 +3,7 @@ menu "Integrator Options" choice prompt "Integrator platform select" + optional config ARCH_INTEGRATOR_AP bool "Support Integrator/AP platform" @@ -18,6 +19,7 @@ config ARCH_CINTEGRATOR choice prompt "Integrator core module select" + optional config CM720T bool "Core Module for ARM720T" diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index 134ae87..67f1a33 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -2,6 +2,7 @@ if ARCH_KEYSTONE choice prompt "TI Keystone board select" + optional config TARGET_K2HK_EVM bool "TI Keystone 2 Kepler/Hawking EVM" diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 45c6687..1261885 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -2,6 +2,7 @@ if KIRKWOOD choice prompt "Marvell Kirkwood board select" + optional config TARGET_OPENRD bool "Marvell OpenRD Board" diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig index 265f336..ba72a41 100644 --- a/arch/arm/mach-nomadik/Kconfig +++ b/arch/arm/mach-nomadik/Kconfig @@ -2,6 +2,7 @@ if ARCH_NOMADIK choice prompt "Nomadik board select" + optional config NOMADIK_NHK8815 bool "ST 8815 Nomadik Hardware Kit" diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 291c511..7644b8d 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -2,6 +2,7 @@ if ORION5X choice prompt "Marvell Orion board select" + optional config TARGET_EDMINIV2 bool "LaCie Ethernet Disk mini V2" diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig new file mode 100644 index 0000000..e46c348 --- /dev/null +++ b/arch/arm/mach-socfpga/Kconfig @@ -0,0 +1,28 @@ +if ARCH_SOCFPGA + +choice + prompt "Altera SOCFPGA board select" + optional + +config TARGET_SOCFPGA_ARRIA5 + bool "Altera SOCFPGA Arria V" + +config TARGET_SOCFPGA_CYCLONE5 + bool "Altera SOCFPGA Cyclone V" + +endchoice + +config SYS_BOARD + default "socfpga" + +config SYS_VENDOR + default "altera" + +config SYS_SOC + default "socfpga" + +config SYS_CONFIG_NAME + default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5 + default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5 + +endif diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 7524ef9..7524ef9 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index fa3b93a..fa3b93a 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c diff --git a/arch/arm/cpu/armv7/socfpga/fpga_manager.c b/arch/arm/mach-socfpga/fpga_manager.c index 43fd2fe..43fd2fe 100644 --- a/arch/arm/cpu/armv7/socfpga/fpga_manager.c +++ b/arch/arm/mach-socfpga/fpga_manager.c diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c index 0be643c..0be643c 100644 --- a/arch/arm/cpu/armv7/socfpga/freeze_controller.c +++ b/arch/arm/mach-socfpga/freeze_controller.c diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 5449726..5449726 100644 --- a/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h diff --git a/arch/arm/include/asm/arch-socfpga/dwmmc.h b/arch/arm/mach-socfpga/include/mach/dwmmc.h index 945eb64..945eb64 100644 --- a/arch/arm/include/asm/arch-socfpga/dwmmc.h +++ b/arch/arm/mach-socfpga/include/mach/dwmmc.h diff --git a/arch/arm/include/asm/arch-socfpga/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h index a077e22..a077e22 100644 --- a/arch/arm/include/asm/arch-socfpga/fpga_manager.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h diff --git a/arch/arm/include/asm/arch-socfpga/freeze_controller.h b/arch/arm/mach-socfpga/include/mach/freeze_controller.h index f19ad87..f19ad87 100644 --- a/arch/arm/include/asm/arch-socfpga/freeze_controller.h +++ b/arch/arm/mach-socfpga/include/mach/freeze_controller.h diff --git a/arch/arm/include/asm/arch-socfpga/gpio.h b/arch/arm/mach-socfpga/include/mach/gpio.h index 6c61f18..6c61f18 100644 --- a/arch/arm/include/asm/arch-socfpga/gpio.h +++ b/arch/arm/mach-socfpga/include/mach/gpio.h diff --git a/arch/arm/include/asm/arch-socfpga/nic301.h b/arch/arm/mach-socfpga/include/mach/nic301.h index 3c8ab31..3c8ab31 100644 --- a/arch/arm/include/asm/arch-socfpga/nic301.h +++ b/arch/arm/mach-socfpga/include/mach/nic301.h diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index d63a285..d63a285 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h diff --git a/arch/arm/include/asm/arch-socfpga/scan_manager.h b/arch/arm/mach-socfpga/include/mach/scan_manager.h index 1155fd3..1155fd3 100644 --- a/arch/arm/include/asm/arch-socfpga/scan_manager.h +++ b/arch/arm/mach-socfpga/include/mach/scan_manager.h diff --git a/arch/arm/include/asm/arch-socfpga/scu.h b/arch/arm/mach-socfpga/include/mach/scu.h index 7a5b074..7a5b074 100644 --- a/arch/arm/include/asm/arch-socfpga/scu.h +++ b/arch/arm/mach-socfpga/include/mach/scu.h diff --git a/arch/arm/include/asm/arch-socfpga/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h index 4f6489d..4f6489d 100644 --- a/arch/arm/include/asm/arch-socfpga/sdram.h +++ b/arch/arm/mach-socfpga/include/mach/sdram.h diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h index 6534283..6534283 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 51d9815..51d9815 100644 --- a/arch/arm/include/asm/arch-socfpga/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h diff --git a/arch/arm/include/asm/arch-socfpga/timer.h b/arch/arm/mach-socfpga/include/mach/timer.h index ee6969b..ee6969b 100644 --- a/arch/arm/include/asm/arch-socfpga/timer.h +++ b/arch/arm/mach-socfpga/include/mach/timer.h diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 0f8b4d0..0f8b4d0 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c index 45b352b..45b352b 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/mach-socfpga/reset_manager.c diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c b/arch/arm/mach-socfpga/scan_manager.c index a820b1b..a820b1b 100644 --- a/arch/arm/cpu/armv7/socfpga/scan_manager.c +++ b/arch/arm/mach-socfpga/scan_manager.c diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index f994658..f994658 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c index 8126e0d..8126e0d 100644 --- a/arch/arm/cpu/armv7/socfpga/system_manager.c +++ b/arch/arm/mach-socfpga/system_manager.c diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/mach-socfpga/timer.c index 253cde3..253cde3 100644 --- a/arch/arm/cpu/armv7/socfpga/timer.c +++ b/arch/arm/mach-socfpga/timer.c diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/mach-socfpga/u-boot-spl.lds index 569fa41..569fa41 100644 --- a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds +++ b/arch/arm/mach-socfpga/u-boot-spl.lds diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 8bab594..9b42871 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -2,6 +2,7 @@ if TEGRA choice prompt "Tegra SoC select" + optional config TEGRA20 bool "Tegra20 family" diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 04cef0a..fefc180 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -12,10 +12,11 @@ obj-y += spl.o obj-y += cpu.o else obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o +obj-$(CONFIG_PWM_TEGRA) += pwm.o endif obj-y += ap.o -obj-y += board.o +obj-y += board.o board2.o obj-y += cache.o obj-y += clock.o obj-y += lowlevel_init.o @@ -24,6 +25,11 @@ obj-y += powergate.o obj-y += xusb-padctl.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-$(CONFIG_TEGRA124) += vpr.o +obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o + +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_ARMV7_PSCI) += psci.o +endif obj-$(CONFIG_TEGRA20) += tegra20/ obj-$(CONFIG_TEGRA30) += tegra30/ diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index a17dfd1..0b94e8a 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -10,6 +10,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/gp_padctrl.h> +#include <asm/arch/mc.h> #include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/clock.h> #include <asm/arch-tegra/fuse.h> @@ -154,6 +155,57 @@ static void init_pmc_scratch(void) writel(odmdata, &pmc->pmc_scratch20); } +#ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE +void protect_secure_section(void) +{ + struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; + + /* Must be MB aligned */ + BUILD_BUG_ON(CONFIG_ARMV7_SECURE_BASE & 0xFFFFF); + BUILD_BUG_ON(CONFIG_ARMV7_SECURE_RESERVE_SIZE & 0xFFFFF); + + writel(CONFIG_ARMV7_SECURE_BASE, &mc->mc_security_cfg0); + writel(CONFIG_ARMV7_SECURE_RESERVE_SIZE >> 20, &mc->mc_security_cfg1); +} +#endif + +#if defined(CONFIG_ARMV7_NONSEC) +static void smmu_flush(struct mc_ctlr *mc) +{ + (void)readl(&mc->mc_smmu_config); +} + +static void smmu_enable(void) +{ + struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; + u32 value; + + /* + * Enable translation for all clients since access to this register + * is restricted to TrustZone-secured requestors. The kernel will use + * the per-SWGROUP enable bits to enable or disable translations. + */ + writel(0xffffffff, &mc->mc_smmu_translation_enable_0); + writel(0xffffffff, &mc->mc_smmu_translation_enable_1); + writel(0xffffffff, &mc->mc_smmu_translation_enable_2); + writel(0xffffffff, &mc->mc_smmu_translation_enable_3); + + /* + * Enable SMMU globally since access to this register is restricted + * to TrustZone-secured requestors. + */ + value = readl(&mc->mc_smmu_config); + value |= TEGRA_MC_SMMU_CONFIG_ENABLE; + writel(value, &mc->mc_smmu_config); + + smmu_flush(mc); +} +#else +static void smmu_enable(void) +{ +} +#endif + void s_init(void) { /* Init PMC scratch memory */ @@ -164,6 +216,9 @@ void s_init(void) /* init the cache */ config_cache(); + /* enable SMMU */ + smmu_enable(); + /* init vpr */ config_vpr(); } diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 0ebaf19..222de6a 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -98,14 +98,6 @@ int dram_init(void) return 0; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - printf("Board: %s\n", sysinfo.board_string); - return 0; -} -#endif /* CONFIG_DISPLAY_BOARDINFO */ - static int uart_configs[] = { #if defined(CONFIG_TEGRA20) #if defined(CONFIG_TEGRA_UARTA_UAA_UAB) diff --git a/board/nvidia/common/board.c b/arch/arm/mach-tegra/board2.c index 018dddb..131802a 100644 --- a/board/nvidia/common/board.c +++ b/arch/arm/mach-tegra/board2.c @@ -7,6 +7,7 @@ #include <common.h> #include <dm.h> +#include <errno.h> #include <ns16550.h> #include <linux/compiler.h> #include <asm/io.h> @@ -40,6 +41,7 @@ #include <asm/arch-tegra/mmc.h> #endif #include <asm/arch-tegra/xusb-padctl.h> +#include <power/as3722.h> #include <i2c.h> #include <spi.h> #include "emc.h" @@ -53,10 +55,6 @@ U_BOOT_DEVICE(tegra_gpios) = { }; #endif -const struct tegra_sysinfo sysinfo = { - CONFIG_TEGRA_BOARD_STRING -}; - __weak void pinmux_init(void) {} __weak void pin_mux_usb(void) {} __weak void pin_mux_spi(void) {} @@ -85,6 +83,30 @@ static void power_det_init(void) #endif } +__weak int tegra_board_id(void) +{ + return -1; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + int board_id = tegra_board_id(); + + printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); + if (board_id != -1) + printf(", ID: %d\n", board_id); + printf("\n"); + + return 0; +} +#endif /* CONFIG_DISPLAY_BOARDINFO */ + +__weak int tegra_lcd_pmic_init(int board_it) +{ + return 0; +} + /* * Routine: board_init * Description: Early hardware init. @@ -92,6 +114,7 @@ static void power_det_init(void) int board_init(void) { __maybe_unused int err; + __maybe_unused int board_id; /* Do clocks and UART first so that printf() works */ clock_init(); @@ -124,6 +147,11 @@ int board_init(void) debug("Memory controller init failed: %d\n", err); # endif # endif /* CONFIG_TEGRA_PMU */ +#ifdef CONFIG_AS3722_POWER + err = as3722_init(NULL); + if (err && err != -ENODEV) + return err; +#endif #endif /* CONFIG_SYS_I2C_TEGRA */ #ifdef CONFIG_USB_EHCI_TEGRA @@ -132,6 +160,10 @@ int board_init(void) #endif #ifdef CONFIG_LCD + board_id = tegra_board_id(); + err = tegra_lcd_pmic_init(board_id); + if (err) + return err; tegra_lcd_check_next_stage(gd->fdt_blob, 0); #endif diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 7c274b5..cdd5438 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -81,9 +81,18 @@ static struct clk_pll *get_pll(enum clock_id clkid) (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; assert(clock_id_is_pll(clkid)); + if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) { + debug("%s: Invalid PLL\n", __func__); + return NULL; + } return &clkrst->crc_pll[clkid]; } +__weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + return NULL; +} + int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, u32 *divp, u32 *cpcon, u32 *lfcon) { @@ -110,7 +119,7 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, u32 divp, u32 cpcon, u32 lfcon) { struct clk_pll *pll = get_pll(clkid); - u32 data; + u32 misc_data, data; /* * We cheat by treating all PLL (except PLLU) in the same fashion. @@ -119,8 +128,7 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, * - DCCON is always 0, doesn't conflict * - M,N, P of PLLP values are ignored for PLLP */ - data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT); - writel(data, &pll->pll_misc); + misc_data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT); data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) | (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT); @@ -129,7 +137,19 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, data |= divp << PLLU_VCO_FREQ_SHIFT; else data |= divp << PLL_DIVP_SHIFT; - writel(data, &pll->pll_base); + if (pll) { + writel(misc_data, &pll->pll_misc); + writel(data, &pll->pll_base); + } else { + struct clk_pll_simple *pll = clock_get_simple_pll(clkid); + + if (!pll) { + debug("%s: Uknown simple PLL %d\n", __func__, clkid); + return 0; + } + writel(misc_data, &pll->pll_misc); + writel(data, &pll->pll_base); + } /* calculate the stable time */ return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US; @@ -152,12 +172,37 @@ void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, writel(value, reg); } -void clock_ll_set_source(enum periph_id periph_id, unsigned source) +int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits, + unsigned source) { u32 *reg = get_periph_source_reg(periph_id); - clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK, - source << OUT_CLK_SOURCE_31_30_SHIFT); + switch (mux_bits) { + case MASK_BITS_31_30: + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK, + source << OUT_CLK_SOURCE_31_30_SHIFT); + break; + + case MASK_BITS_31_29: + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK, + source << OUT_CLK_SOURCE_31_29_SHIFT); + break; + + case MASK_BITS_31_28: + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK, + source << OUT_CLK_SOURCE_31_28_SHIFT); + break; + + default: + return -1; + } + + return 0; +} + +void clock_ll_set_source(enum periph_id periph_id, unsigned source) +{ + clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source); } /** @@ -306,25 +351,7 @@ static int adjust_periph_pll(enum periph_id periph_id, int source, if (source < 0) return -1; - switch (mux_bits) { - case MASK_BITS_31_30: - clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK, - source << OUT_CLK_SOURCE_31_30_SHIFT); - break; - - case MASK_BITS_31_29: - clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK, - source << OUT_CLK_SOURCE_31_29_SHIFT); - break; - - case MASK_BITS_31_28: - clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK, - source << OUT_CLK_SOURCE_31_28_SHIFT); - break; - - default: - return -1; - } + clock_ll_set_source_bits(periph_id, mux_bits, source); udelay(2); return 0; @@ -431,6 +458,8 @@ unsigned clock_get_rate(enum clock_id clkid) return parent_rate; pll = get_pll(clkid); + if (!pll) + return 0; base = readl(&pll->pll_base); /* Oh for bf_unpack()... */ @@ -564,6 +593,7 @@ void clock_init(void) pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY); pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH); pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); + pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY); pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC); pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU); @@ -571,6 +601,7 @@ void clock_init(void) debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]); debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); + debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]); debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); /* Do any special system timer/TSC setup */ diff --git a/board/nvidia/common/emc.c b/arch/arm/mach-tegra/emc.c index 8c62f36..8c62f36 100644 --- a/board/nvidia/common/emc.c +++ b/arch/arm/mach-tegra/emc.c diff --git a/board/nvidia/common/emc.h b/arch/arm/mach-tegra/emc.h index 4095235..4095235 100644 --- a/board/nvidia/common/emc.h +++ b/arch/arm/mach-tegra/emc.h diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 439cff3..6331cd4 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -44,7 +44,7 @@ static int tegra_powergate_set(enum tegra_powergate id, bool state) return -ETIMEDOUT; } -static int tegra_powergate_power_on(enum tegra_powergate id) +int tegra_powergate_power_on(enum tegra_powergate id) { return tegra_powergate_set(id, true); } diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S new file mode 100644 index 0000000..b836da1 --- /dev/null +++ b/arch/arm/mach-tegra/psci.S @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2014, NVIDIA + * Copyright (C) 2015, Siemens AG + * + * Authors: + * Thierry Reding <treding@nvidia.com> + * Jan Kiszka <jan.kiszka@siemens.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> +#include <asm/macro.h> +#include <asm/psci.h> + + .pushsection ._secure.text, "ax" + .arch_extension sec + +#define TEGRA_SB_CSR_0 0x6000c200 +#define NS_RST_VEC_WR_DIS (1 << 1) + +#define TEGRA_RESET_EXCEPTION_VECTOR 0x6000f100 + +#define TEGRA_FLOW_CTRL_BASE 0x60007000 +#define FLOW_CTRL_CPU_CSR 0x08 +#define CSR_ENABLE (1 << 0) +#define CSR_IMMEDIATE_WAKE (1 << 3) +#define CSR_WAIT_WFI_SHIFT 8 +#define FLOW_CTRL_CPU1_CSR 0x18 + +@ converts CPU ID into FLOW_CTRL_CPUn_CSR offset +.macro get_csr_reg cpu, ofs, tmp + cmp \cpu, #0 @ CPU0? + lsl \tmp, \cpu, #3 @ multiple by 8 (register offset CPU1-3) + moveq \ofs, #FLOW_CTRL_CPU_CSR + addne \ofs, \tmp, #FLOW_CTRL_CPU1_CSR - 8 +.endm + +ENTRY(psci_arch_init) + mov r6, lr + + mrc p15, 0, r5, c1, c1, 0 @ Read SCR + bic r5, r5, #1 @ Secure mode + mcr p15, 0, r5, c1, c1, 0 @ Write SCR + isb + + @ lock reset vector for non-secure + ldr r4, =TEGRA_SB_CSR_0 + ldr r5, [r4] + orr r5, r5, #NS_RST_VEC_WR_DIS + str r5, [r4] + + bl psci_get_cpu_id @ CPU ID => r0 + + adr r5, _sys_clock_freq + cmp r0, #0 + + mrceq p15, 0, r7, c14, c0, 0 @ read CNTFRQ from CPU0 + streq r7, [r5] + + ldrne r7, [r5] + mcrne p15, 0, r7, c14, c0, 0 @ write CNTFRQ to CPU1..3 + + bl psci_get_cpu_stack_top @ stack top => r0 + mov sp, r0 + + bx r6 +ENDPROC(psci_arch_init) + +_sys_clock_freq: + .word 0 + +ENTRY(psci_cpu_off) + bl psci_cpu_off_common + + bl psci_get_cpu_id @ CPU ID => r0 + + get_csr_reg r0, r2, r3 + + ldr r6, =TEGRA_FLOW_CTRL_BASE + mov r5, #(CSR_ENABLE) + mov r4, #(1 << CSR_WAIT_WFI_SHIFT) + add r5, r4, lsl r0 + str r5, [r6, r2] + +_loop: wfi + b _loop +ENDPROC(psci_cpu_off) + +ENTRY(psci_cpu_on) + push {lr} + + mov r0, r1 + bl psci_get_cpu_stack_top @ get stack top of target CPU + str r2, [r0] @ store target PC at stack top + dsb + + ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR + ldr r5, =psci_cpu_entry + str r5, [r6] + + get_csr_reg r1, r2, r3 + + ldr r6, =TEGRA_FLOW_CTRL_BASE + mov r5, #(CSR_IMMEDIATE_WAKE | CSR_ENABLE) + str r5, [r6, r2] + + mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS + pop {pc} +ENDPROC(psci_cpu_on) + + .globl psci_text_end +psci_text_end: + .popsection diff --git a/arch/arm/mach-tegra/tegra20/pwm.c b/arch/arm/mach-tegra/pwm.c index 5b88636..1c38fc1 100644 --- a/arch/arm/mach-tegra/tegra20/pwm.c +++ b/arch/arm/mach-tegra/pwm.c @@ -1,5 +1,5 @@ /* - * Tegra2 pulse width frequency modulator definitions + * Tegra pulse width frequency modulator definitions * * Copyright (c) 2011 The Chromium OS Authors. * @@ -24,7 +24,10 @@ void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider) assert(channel < PWM_NUM_CHANNELS); /* TODO: Can we use clock_adjust_periph_pll_div() here? */ - clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, rate); + if (rate) { + clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, + rate); + } reg = PWM_ENABLE_MASK; reg |= pulse_width << PWM_WIDTH_SHIFT; diff --git a/arch/arm/mach-tegra/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig index 31012bc..1047b92 100644 --- a/arch/arm/mach-tegra/tegra114/Kconfig +++ b/arch/arm/mach-tegra/tegra114/Kconfig @@ -2,6 +2,7 @@ if TEGRA114 choice prompt "Tegra114 board select" + optional config TARGET_DALMORE bool "NVIDIA Tegra114 Dalmore evaluation board" diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig index 88f627c..6579e3f 100644 --- a/arch/arm/mach-tegra/tegra124/Kconfig +++ b/arch/arm/mach-tegra/tegra124/Kconfig @@ -2,9 +2,12 @@ if TEGRA124 choice prompt "Tegra124 board select" + optional config TARGET_JETSON_TK1 bool "NVIDIA Tegra124 Jetson TK1 board" + select CPU_V7_HAS_NONSEC if !SPL_BUILD + select CPU_V7_HAS_VIRT if !SPL_BUILD config TARGET_NYAN_BIG bool "Google/NVIDIA Nyan-big Chrombook" diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile index ef2da29..f577f45 100644 --- a/arch/arm/mach-tegra/tegra124/Makefile +++ b/arch/arm/mach-tegra/tegra124/Makefile @@ -11,3 +11,7 @@ obj-y += clock.o obj-y += funcmux.o obj-y += pinmux.o obj-y += xusb-padctl.o + +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_ARMV7_NONSEC) += psci.o +endif diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index fc8bd19..2d17550 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -42,6 +42,7 @@ enum clock_type_id { CLOCK_TYPE_ASPTE, CLOCK_TYPE_PMDACD2T, CLOCK_TYPE_PCST, + CLOCK_TYPE_DP, CLOCK_TYPE_PC2CC3M, CLOCK_TYPE_PC2CC3S_T, @@ -101,6 +102,10 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), MASK_BITS_31_28}, + /* CLOCK_TYPE_DP */ + { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_28}, /* Additional clock types on Tegra114+ */ /* CLOCK_TYPE_PC2CC3M */ @@ -259,7 +264,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { /* 0x58 */ TYPE(PERIPHC_58h, CLOCK_TYPE_NONE), - TYPE(PERIPHC_59h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SOR, CLOCK_TYPE_NONE), TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE), TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE), TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), @@ -546,7 +551,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { NONE(X_RESERVED19), NONE(ADX1), NONE(DPAUX), - NONE(SOR0), + PERIPHC_SOR, NONE(X_RESERVED23), /* 184 */ @@ -594,7 +599,10 @@ u32 *get_periph_source_reg(enum periph_id periph_id) assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT); internal_id = periph_id_to_internal_id[periph_id]; assert(internal_id != -1); - if (internal_id >= PERIPHC_VW_FIRST) { + if (internal_id >= PERIPHC_X_FIRST) { + internal_id -= PERIPHC_X_FIRST; + return &clkrst->crc_clk_src_x[internal_id]; + } else if (internal_id >= PERIPHC_VW_FIRST) { internal_id -= PERIPHC_VW_FIRST; return &clkrst->crc_clk_src_vw[internal_id]; } else { @@ -657,8 +665,10 @@ void clock_set_enable(enum periph_id periph_id, int enable) assert(clock_periph_id_isvalid(periph_id)); if ((int)periph_id < (int)PERIPH_ID_VW_FIRST) clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; - else + else if ((int)periph_id < PERIPH_ID_X_FIRST) clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; + else + clk = &clkrst->crc_clk_out_enb_x; reg = readl(clk); if (enable) reg |= PERIPH_MASK(periph_id); @@ -678,8 +688,10 @@ void reset_set_enable(enum periph_id periph_id, int enable) assert(clock_periph_id_isvalid(periph_id)); if (periph_id < PERIPH_ID_VW_FIRST) reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; - else + else if ((int)periph_id < PERIPH_ID_X_FIRST) reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; + else + reset = &clkrst->crc_rst_devices_x; reg = readl(reset); if (enable) reg |= PERIPH_MASK(periph_id); @@ -933,3 +945,122 @@ int tegra_plle_enable(void) return 0; } + +void clock_sor_enable_edp_clock(void) +{ + u32 *reg; + + /* uses PLLP, has a non-standard bit layout. */ + reg = get_periph_source_reg(PERIPH_ID_SOR0); + setbits_le32(reg, SOR0_CLK_SEL0); +} + +u32 clock_set_display_rate(u32 frequency) +{ + /** + * plld (fo) = vco >> p, where 500MHz < vco < 1000MHz + * = (cf * n) >> p, where 1MHz < cf < 6MHz + * = ((ref / m) * n) >> p + * + * Iterate the possible values of p (3 bits, 2^7) to find out a minimum + * safe vco, then find best (m, n). since m has only 5 bits, we can + * iterate all possible values. Note Tegra 124 supports 11 bits for n, + * but our pll_fields has only 10 bits for n. + * + * Note values undershoot or overshoot target output frequency may not + * work if the values are not in "safe" range by panel specification. + */ + u32 ref = clock_get_rate(CLOCK_ID_OSC); + u32 divm, divn, divp, cpcon; + u32 cf, vco, rounded_rate = frequency; + u32 diff, best_diff, best_m = 0, best_n = 0, best_p; + const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3, + mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz, + min_cf = 1 * mhz, max_cf = 6 * mhz; + int mux_bits, divider_bits, source; + + for (divp = 0, vco = frequency; vco < min_vco && divp < max_p; divp++) + vco <<= 1; + + if (vco < min_vco || vco > max_vco) { + printf("%s: Cannot find out a supported VCO for Frequency (%u)\n", + __func__, frequency); + return 0; + } + + best_p = divp; + best_diff = vco; + + for (divm = 1; divm < max_m && best_diff; divm++) { + cf = ref / divm; + if (cf < min_cf) + break; + if (cf > max_cf) + continue; + + divn = vco / cf; + if (divn >= max_n) + continue; + + diff = vco - divn * cf; + if (divn + 1 < max_n && diff > cf / 2) { + divn++; + diff = cf - diff; + } + + if (diff >= best_diff) + continue; + + best_diff = diff; + best_m = divm; + best_n = divn; + } + + if (best_n < 50) + cpcon = 2; + else if (best_n < 300) + cpcon = 3; + else if (best_n < 600) + cpcon = 8; + else + cpcon = 12; + + if (best_diff) { + printf("%s: Failed to match output frequency %u, best difference is %u\n", + __func__, frequency, best_diff); + rounded_rate = (ref / best_m * best_n) >> best_p; + } + + debug("%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n", + __func__, rounded_rate, ref, best_m, best_n, best_p, cpcon); + + source = get_periph_clock_source(PERIPH_ID_DISP1, CLOCK_ID_DISPLAY, + &mux_bits, ÷r_bits); + clock_ll_set_source_bits(PERIPH_ID_DISP1, mux_bits, source); + clock_set_rate(CLOCK_ID_DISPLAY, best_n, best_m, best_p, cpcon); + + return rounded_rate; +} + +void clock_set_up_plldp(void) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 value; + + value = PLLDP_SS_CFG_UNDOCUMENTED | PLLDP_SS_CFG_DITHER; + writel(value | PLLDP_SS_CFG_CLAMP, &clkrst->crc_plldp_ss_cfg); + clock_start_pll(CLOCK_ID_DP, 1, 90, 3, 0, 0); + writel(value, &clkrst->crc_plldp_ss_cfg); +} + +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + if (clkid == CLOCK_ID_DP) + return &clkrst->plldp; + + return NULL; +} diff --git a/arch/arm/mach-tegra/tegra124/psci.c b/arch/arm/mach-tegra/tegra124/psci.c new file mode 100644 index 0000000..16d1965 --- /dev/null +++ b/arch/arm/mach-tegra/tegra124/psci.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2015, Siemens AG + * Author: Jan Kiszka <jan.kiszka@siemens.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/psci.h> +#include <asm/arch/flow.h> +#include <asm/arch/powergate.h> +#include <asm/arch-tegra/ap.h> +#include <asm/arch-tegra/pmc.h> + +static void park_cpu(void) +{ + while (1) + asm volatile("wfi"); +} + +/** + * Initialize power management for application processors + */ +void psci_board_init(void) +{ + struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; + + writel((u32)park_cpu, EXCEP_VECTOR_CPU_RESET_VECTOR); + + /* + * The naturally expected order of putting these CPUs under Flow + * Controller regime would be + * - configure the Flow Controller + * - power up the CPUs + * - wait for the CPUs to hit wfi and be powered down again + * + * However, this doesn't work in practice. We rather need to power them + * up first and park them in wfi. While they are waiting there, we can + * indeed program the Flow Controller to powergate them on wfi, which + * will then happen immediately as they are already in that state. + */ + tegra_powergate_power_on(TEGRA_POWERGATE_CPU1); + tegra_powergate_power_on(TEGRA_POWERGATE_CPU2); + tegra_powergate_power_on(TEGRA_POWERGATE_CPU3); + + writel((2 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu1_csr); + writel((4 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu2_csr); + writel((8 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu3_csr); + + writel(EVENT_MODE_STOP, &flow->halt_cpu1_events); + writel(EVENT_MODE_STOP, &flow->halt_cpu2_events); + writel(EVENT_MODE_STOP, &flow->halt_cpu3_events); + + while (!(readl(&flow->cpu1_csr) & CSR_PWR_OFF_STS) || + !(readl(&flow->cpu2_csr) & CSR_PWR_OFF_STS) || + !(readl(&flow->cpu3_csr) & CSR_PWR_OFF_STS)) + /* wait */; +} diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index 7f09f81..1bb8dff 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -2,6 +2,7 @@ if TEGRA20 choice prompt "Tegra20 board select" + optional config TARGET_HARMONY bool "NVIDIA Tegra20 Harmony evaluation board" diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index d48f9bb..fc3fb4a 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -7,7 +7,6 @@ ifdef CONFIG_SPL_BUILD obj-y += cpu.o else -obj-$(CONFIG_PWM_TEGRA) += pwm.o obj-$(CONFIG_VIDEO_TEGRA) += display.o endif diff --git a/arch/arm/mach-tegra/tegra20/display.c b/arch/arm/mach-tegra/tegra20/display.c index 61efed6..b7605ff 100644 --- a/arch/arm/mach-tegra/tegra20/display.c +++ b/arch/arm/mach-tegra/tegra20/display.c @@ -10,7 +10,7 @@ #include <asm/arch/clock.h> #include <asm/arch/tegra.h> #include <asm/arch/display.h> -#include <asm/arch/dc.h> +#include <asm/arch-tegra/dc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/timer.h> diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index 3abdc7b..e78331e 100644 --- a/arch/arm/mach-tegra/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig @@ -2,6 +2,7 @@ if TEGRA30 choice prompt "Tegra30 board select" + optional config TARGET_APALIS_T30 bool "Toradex Apalis T30 board" diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 288e6ab..2d27c49 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -9,6 +9,7 @@ config UNIPHIER_SMP choice prompt "UniPhier SoC select" + optional config MACH_PH1_PRO4 bool "PH1-Pro4" diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 1046ece..483c3a0 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -2,6 +2,7 @@ if ARCH_ZYNQ choice prompt "Xilinx Zynq board select" + optional config TARGET_ZYNQ_ZED bool "Zynq ZedBoard" diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index 66de2ad..c69654c 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig @@ -6,6 +6,7 @@ config SYS_ARCH choice prompt "Target select" + optional config TARGET_ATNGW100 bool "Support atngw100" diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 31913fe..0a2fb4d 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -6,6 +6,7 @@ config SYS_ARCH choice prompt "Target select" + optional config TARGET_BCT_BRETTL2 bool "Support bct-brettl2" diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 69cb0f7..26509b7 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -114,6 +114,7 @@ config M548x choice prompt "Target select" + optional config TARGET_M52277EVB bool "Support M52277EVB" diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 6f419f0..077b2a7 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -6,6 +6,7 @@ config SYS_ARCH choice prompt "Target select" + optional config TARGET_MICROBLAZE_GENERIC bool "Support microblaze-generic" diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b0a8a43..feb2f68 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -13,6 +13,7 @@ config USE_PRIVATE_LIBGCC choice prompt "Target select" + optional config TARGET_QEMU_MIPS bool "Support qemu-mips" diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig index 81b0a01..98b0282 100644 --- a/arch/nds32/Kconfig +++ b/arch/nds32/Kconfig @@ -6,6 +6,7 @@ config SYS_ARCH choice prompt "Target select" + optional config TARGET_ADP_AG101 bool "Support adp-ag101" diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig index b3be7b5..8ae7f6e 100644 --- a/arch/nios2/Kconfig +++ b/arch/nios2/Kconfig @@ -6,6 +6,7 @@ config SYS_ARCH choice prompt "Target select" + optional config TARGET_NIOS2_GENERIC bool "Support nios2-generic" diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index 4d62b4c..11014d1 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -6,6 +6,7 @@ config SYS_ARCH choice prompt "Target select" + optional config TARGET_OPENRISC_GENERIC bool "Support openrisc-generic" diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 8e5a3e2..3b3f446 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -6,6 +6,7 @@ config SYS_ARCH choice prompt "CPU select" + optional config MPC512X bool "MPC512X" diff --git a/arch/powerpc/cpu/mpc512x/Kconfig b/arch/powerpc/cpu/mpc512x/Kconfig index a0f0ede..53450ae 100644 --- a/arch/powerpc/cpu/mpc512x/Kconfig +++ b/arch/powerpc/cpu/mpc512x/Kconfig @@ -6,6 +6,7 @@ config SYS_CPU choice prompt "Target select" + optional config TARGET_PDM360NG bool "Support pdm360ng" diff --git a/arch/powerpc/cpu/mpc5xx/Kconfig b/arch/powerpc/cpu/mpc5xx/Kconfig index aad4a7c..5275447 100644 --- a/arch/powerpc/cpu/mpc5xx/Kconfig +++ b/arch/powerpc/cpu/mpc5xx/Kconfig @@ -6,6 +6,7 @@ config SYS_CPU choice prompt "Target select" + optional config TARGET_CMI_MPC5XX bool "Support cmi_mpc5xx" diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig index eec9d7d..5d49228 100644 --- a/arch/powerpc/cpu/mpc5xxx/Kconfig +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -6,6 +6,7 @@ config SYS_CPU choice prompt "Target select" + optional config TARGET_A3M071 bool "Support a3m071" diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig index 55941c8..e93732d 100644 --- a/arch/powerpc/cpu/mpc8260/Kconfig +++ b/arch/powerpc/cpu/mpc8260/Kconfig @@ -6,6 +6,7 @@ config SYS_CPU choice prompt "Target select" + optional config TARGET_KM82XX bool "Support km82xx" diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 88a3bd6..3fb901f 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -6,6 +6,7 @@ config SYS_CPU choice prompt "Target select" + optional config TARGET_MPC8308_P1M bool "Support mpc8308_p1m" diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index aff5fdb..3e8d0b1 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -6,6 +6,7 @@ config SYS_CPU choice prompt "Target select" + optional config TARGET_SBC8548 bool "Support sbc8548" diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig index 14e8b1a..fe1859d 100644 --- a/arch/powerpc/cpu/mpc86xx/Kconfig +++ b/arch/powerpc/cpu/mpc86xx/Kconfig @@ -6,6 +6,7 @@ config SYS_CPU choice prompt "Target select" + optional config TARGET_SBC8641D bool "Support sbc8641d" diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index e8bcbe9..79cee35 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -6,6 +6,7 @@ config SYS_CPU choice prompt "Target select" + optional config TARGET_TQM823L bool "Support TQM823L" diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pci.c b/arch/powerpc/cpu/ppc4xx/4xx_pci.c index b26ec2a..30e6c65 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_pci.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_pci.c @@ -408,7 +408,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); } -#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3)) +#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) /* *As is these functs get called out of flash Not a horrible diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 89cb3e9..10b86e0 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -6,6 +6,7 @@ config SYS_CPU choice prompt "Target select" + optional config TARGET_CSB272 bool "Support csb272" @@ -23,9 +24,6 @@ config TARGET_PCS440EP config TARGET_SBC405 bool "Support sbc405" -config TARGET_SC3 - bool "Support sc3" - config TARGET_T3CORP bool "Support t3corp" @@ -202,7 +200,6 @@ source "board/pcs440ep/Kconfig" source "board/prodrive/alpr/Kconfig" source "board/prodrive/p3p440/Kconfig" source "board/sbc405/Kconfig" -source "board/sc3/Kconfig" source "board/t3corp/Kconfig" source "board/xes/xpedite1000/Kconfig" source "board/xilinx/ml507/Kconfig" diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 5ea29cc..4c9c3ac 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -75,10 +75,6 @@ extern int update_flash_size(int flash_size); #endif -#if defined(CONFIG_SC3) -extern void sc3_read_eeprom(void); -#endif - #if defined(CONFIG_CMD_DOC) void doc_init(void); #endif @@ -791,10 +787,6 @@ void board_init_r(gd_t *id, ulong dest_addr) #endif /* CONFIG_405GP, CONFIG_405EP */ #endif /* CONFIG_SYS_EXTBDINFO */ -#if defined(CONFIG_SC3) - sc3_read_eeprom(); -#endif - #if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET) mac_read_from_eeprom(); #endif diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 168f2ef..b6aae37 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -45,11 +45,6 @@ void __udelay(unsigned long usec) os_usleep(usec); } -unsigned long __attribute__((no_instrument_function)) timer_get_us(void) -{ - return os_get_nsec() / 1000; -} - int cleanup_before_linux(void) { return 0; diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 4d5f805..e6dd17e 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -24,6 +24,7 @@ #include <asm/sections.h> #include <asm/state.h> #include <os.h> +#include <rtc_def.h> /* Operating System Interface */ @@ -537,3 +538,20 @@ int os_jump_to_image(const void *dest, int size) return unlink(fname); } + +void os_localtime(struct rtc_time *rt) +{ + time_t t = time(NULL); + struct tm *tm; + + tm = localtime(&t); + rt->tm_sec = tm->tm_sec; + rt->tm_min = tm->tm_min; + rt->tm_hour = tm->tm_hour; + rt->tm_mday = tm->tm_mday; + rt->tm_mon = tm->tm_mon + 1; + rt->tm_year = tm->tm_year + 1900; + rt->tm_wday = tm->tm_wday; + rt->tm_yday = tm->tm_yday; + rt->tm_isdst = tm->tm_isdst; +} diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index ec01040..4c38fab 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <errno.h> #include <os.h> #include <cli.h> #include <malloc.h> @@ -77,12 +78,18 @@ int sandbox_main_loop_init(void) struct sandbox_state *state = state_get_current(); /* Execute command if required */ - if (state->cmd) { - int retval; + if (state->cmd || state->run_distro_boot) { + int retval = 0; cli_init(); - retval = run_command_list(state->cmd, -1, 0); + if (state->cmd) + retval = run_command_list(state->cmd, -1, 0); + + if (state->run_distro_boot) + retval = cli_simple_run_command("run distro_bootcmd", + 0); + if (!state->interactive) os_exit(retval); } @@ -90,6 +97,14 @@ int sandbox_main_loop_init(void) return 0; } +static int sandbox_cmdline_cb_boot(struct sandbox_state *state, + const char *arg) +{ + state->run_distro_boot = true; + return 0; +} +SANDBOX_CMDLINE_OPT_SHORT(boot, 'b', 0, "Run distro boot commands"); + static int sandbox_cmdline_cb_command(struct sandbox_state *state, const char *arg) { diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index 033958c..cae731c 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -51,7 +51,7 @@ static int state_read_file(struct sandbox_state *state, const char *fname) ret = os_get_filesize(fname, &size); if (ret < 0) { printf("Cannot find sandbox state file '%s'\n", fname); - return ret; + return -ENOENT; } state->state_fdt = os_malloc(size); if (!state->state_fdt) { diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile index a4c980b..562a078 100644 --- a/arch/sandbox/dts/Makefile +++ b/arch/sandbox/dts/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_SANDBOX) += sandbox.dtb +dtb-$(CONFIG_DM_TEST) += test.dtb targets += $(dtb-y) diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index efa2097..a3ebd80 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -8,7 +8,9 @@ aliases { eth5 = "/eth@90000000"; + i2c0 = &i2c_0; pci0 = &pci; + rtc0 = &rtc_0; }; chosen { @@ -70,8 +72,8 @@ lcd { compatible = "sandbox,lcd-sdl"; - xres = <800>; - yres = <600>; + xres = <1366>; + yres = <768>; }; gpio_a: gpios@0 { @@ -90,7 +92,7 @@ num-gpios = <10>; }; - i2c@0 { + i2c_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0 0>; @@ -105,6 +107,17 @@ sandbox,size = <128>; }; }; + + rtc_0: rtc@43 { + reg = <0x43>; + compatible = "sandbox-rtc"; + emul { + compatible = "sandbox,i2c-rtc"; + }; + }; + sandbox_pmic: sandbox_pmic { + reg = <0x40>; + }; }; spi@0 { @@ -195,3 +208,4 @@ }; #include "cros-ec-keyboard.dtsi" +#include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/dts/sandbox_pmic.dtsi b/arch/sandbox/dts/sandbox_pmic.dtsi new file mode 100644 index 0000000..44a26b1 --- /dev/null +++ b/arch/sandbox/dts/sandbox_pmic.dtsi @@ -0,0 +1,78 @@ +/* + * Sandbox PMIC dts node + * + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/pmic/sandbox_pmic.h> + +&sandbox_pmic { + compatible = "sandbox,pmic"; + + pmic_emul { + compatible = "sandbox,i2c-pmic"; + + /* + * Default PMICs register values are set by macro + * VAL2REG(min, step, value) [uV/uA] + * VAL2OMREG(mode id) + * reg-defaults - byte array + */ + reg-defaults = /bits/ 8 < + /* BUCK1 */ + VAL2REG(800000, 25000, 1000000) + VAL2REG(150000, 25000, 150000) + VAL2OMREG(BUCK_OM_OFF) + /* BUCK2 */ + VAL2REG(750000, 50000, 3000000) + VAL2REG(150000, 25000, 150000) + VAL2OMREG(0) + /* LDO1 */ + VAL2REG(800000, 25000, 1600000) + VAL2REG(100000, 50000, 150000) + VAL2OMREG(LDO_OM_OFF) + /* LDO2 */ + VAL2REG(750000, 50000, 3000000) + VAL2REG(150000, 25000, 150000) + VAL2OMREG(0) + /* reg[12:15] - not used */ + 0x00 + 0x00 + 0x00 + 0x00 + >; + }; + + buck1 { + regulator-name = "SUPPLY_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + buck2 { + regulator-name = "SUPPLY_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo1 { + regulator-name = "VDD_EMMC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-min-microamp = <100000>; + regulator-max-microamp = <100000>; + regulator-boot-on; + }; + + ldo2 { + regulator-name = "VDD_LCD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; diff --git a/test/dm/test.dts b/arch/sandbox/dts/test.dts index d0c40be..1bc3ca0 100644 --- a/test/dm/test.dts +++ b/arch/sandbox/dts/test.dts @@ -139,6 +139,10 @@ sandbox,size = <256>; }; }; + + sandbox_pmic: sandbox_pmic { + reg = <0x40>; + }; }; pci: pci-controller { @@ -228,3 +232,5 @@ }; }; + +#include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/include/asm/eth.h b/arch/sandbox/include/asm/eth.h index 4b79ede..88804fb 100644 --- a/arch/sandbox/include/asm/eth.h +++ b/arch/sandbox/include/asm/eth.h @@ -12,4 +12,6 @@ void sandbox_eth_disable_response(int index, bool disable); +void sandbox_eth_skip_timeout(void); + #endif /* __ETH_H */ diff --git a/arch/sandbox/include/asm/rtc.h b/arch/sandbox/include/asm/rtc.h new file mode 100644 index 0000000..5ed4584 --- /dev/null +++ b/arch/sandbox/include/asm/rtc.h @@ -0,0 +1,28 @@ +/* + * Simulate an I2C real time clock + * + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __asm_rtc_h +#define __asm_rtc_h + +/* Register numbers in the sandbox RTC */ +enum { + REG_SEC = 5, + REG_MIN, + REG_HOUR, + REG_MDAY, + REG_MON, + REG_YEAR, + REG_WDAY, + + REG_RESET = 0x20, + + REG_COUNT = 0x80, +}; + +#endif diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index a0c24ba..a57480a 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -42,6 +42,7 @@ struct sandbox_spi_info { struct sandbox_state { const char *cmd; /* Command to execute */ bool interactive; /* Enable cmdline after execute */ + bool run_distro_boot; /* Automatically run distro bootcommands */ const char *fdt_fname; /* Filename of FDT binary */ const char *parse_err; /* Error to report from parsing */ int argc; /* Program arguments */ diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 8e490e9..91a5c79 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -17,6 +17,16 @@ #define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM #define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL +/** + * sandbox_i2c_set_test_mode() - set test mode for running unit tests + * + * See sandbox_i2c_xfer() for the behaviour changes. + * + * @bus: sandbox I2C bus to adjust + * @test_mode: true to select test mode, false to run normally + */ +void sandbox_i2c_set_test_mode(struct udevice *bus, bool test_mode); + enum sandbox_i2c_eeprom_test_mode { SIE_TEST_MODE_NONE, /* Permits read/write of only one byte per I2C transaction */ @@ -28,4 +38,33 @@ void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev, void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len); +/* + * sandbox_timer_add_offset() + * + * Allow tests to add to the time reported through lib/time.c functions + * offset: number of milliseconds to advance the system time + */ +void sandbox_timer_add_offset(unsigned long offset); + +/** + * sandbox_i2c_rtc_set_offset() - set the time offset from system/base time + * + * @dev: RTC device to adjust + * @use_system_time: true to use system time, false to use @base_time + * @offset: RTC offset from current system/base time (-1 for no + * change) + * @return old value of RTC offset + */ +long sandbox_i2c_rtc_set_offset(struct udevice *dev, bool use_system_time, + int offset); + +/** + * sandbox_i2c_rtc_get_set_base_time() - get and set the base time + * + * @dev: RTC device to adjust + * @base_time: New base system time (set to -1 for no change) + * @return old base time + */ +long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time); + #endif diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 2128f23..2f7a2fe 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -29,6 +29,7 @@ config SH_32BIT choice prompt "Target select" + optional config TARGET_RSK7203 bool "RSK+ 7203" diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 2df09b2..04dc08f 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -14,6 +14,7 @@ config LEON3 choice prompt "Board select" + optional config TARGET_GRSIM_LEON2 bool "GRSIM simulating a LEON2 board" diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 23a98e4..5b356fb 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -34,6 +34,7 @@ #include "bur_common.h" #include "../../../drivers/video/am335x-fb.h" #include <nand.h> +#include <fdt_simplefb.h> static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; @@ -47,11 +48,72 @@ DECLARE_GLOBAL_DATA_PTR; /* --------------------------------------------------------------------------*/ #if defined(CONFIG_LCD) && defined(CONFIG_AM335X_LCD) && \ !defined(CONFIG_SPL_BUILD) +void lcdbacklight(int on) +{ +#ifdef CONFIG_USE_FDT + if (gd->fdt_blob == NULL) { + printf("%s: don't have a valid gd->fdt_blob!\n", __func__); + return; + } + unsigned int driver = FDTPROP(PATHINF, "brightdrv"); + unsigned int bright = FDTPROP(PATHINF, "brightdef"); + unsigned int pwmfrq = FDTPROP(PATHINF, "brightfdim"); +#else + unsigned int driver = getenv_ulong("ds1_bright_drv", 16, 0UL); + unsigned int bright = getenv_ulong("ds1_bright_def", 10, 50); + unsigned int pwmfrq = getenv_ulong("ds1_pwmfreq", 10, ~0UL); +#endif + unsigned int tmp; + + struct gptimer *const timerhw = (struct gptimer *)DM_TIMER6_BASE; + + if (on) + bright = bright != ~0UL ? bright : 50; + else + bright = 0; + + switch (driver) { + case 0: /* PMIC LED-Driver */ + /* brightness level */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL2, bright, 0xFF); + /* current sink */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, + bright != 0 ? 0x0A : 0x02, + 0xFF); + break; + case 1: /* PWM using timer6 */ + if (pwmfrq != ~0UL) { + timerhw->tiocp_cfg = TCFG_RESET; + udelay(10); + while (timerhw->tiocp_cfg & TCFG_RESET) + ; + tmp = ~0UL-(V_OSCK/pwmfrq); /* bottom value */ + timerhw->tldr = tmp; + timerhw->tcrr = tmp; + tmp = tmp + ((V_OSCK/pwmfrq)/100) * bright; + timerhw->tmar = tmp; + timerhw->tclr = (TCLR_PT | (2 << TCLR_TRG_SHIFT) | + TCLR_CE | TCLR_AR | TCLR_ST); + } else { + puts("invalid pwmfrq in env/dtb! skip PWM-setup.\n"); + } + break; + default: + puts("no suitable backlightdriver in env/dtb!\n"); + break; + } +} + int load_lcdtiming(struct am335x_lcdpanel *panel) { struct am335x_lcdpanel pnltmp; #ifdef CONFIG_USE_FDT u32 dtbprop; + char buf[32]; + const char *nodep = 0; + int nodeoff; if (gd->fdt_blob == NULL) { printf("%s: don't have a valid gd->fdt_blob!\n", __func__); @@ -97,6 +159,25 @@ int load_lcdtiming(struct am335x_lcdpanel *panel) dtbprop = FDTPROP(PATHTIM, "de-active"); if (dtbprop == 0) pnltmp.pol |= DE_INVERT; + + nodeoff = fdt_path_offset(gd->fdt_blob, "/factory-settings"); + if (nodeoff >= 0) { + nodep = fdt_getprop(gd->fdt_blob, nodeoff, "rotation", NULL); + if (nodep != 0) { + if (strcmp(nodep, "cw") == 0) + panel_info.vl_rot = 1; + else if (strcmp(nodep, "ud") == 0) + panel_info.vl_rot = 2; + else if (strcmp(nodep, "ccw") == 0) + panel_info.vl_rot = 3; + else + panel_info.vl_rot = 0; + } + } else { + puts("no 'factory-settings / rotation' in dtb!\n"); + } + snprintf(buf, sizeof(buf), "fbcon=rotate:%d", panel_info.vl_rot); + setenv("optargs_rot", buf); #else pnltmp.hactive = getenv_ulong("ds1_hactive", 10, ~0UL); pnltmp.vactive = getenv_ulong("ds1_vactive", 10, ~0UL); @@ -111,6 +192,7 @@ int load_lcdtiming(struct am335x_lcdpanel *panel) pnltmp.pol = getenv_ulong("ds1_pol", 16, ~0UL); pnltmp.pup_delay = getenv_ulong("ds1_pupdelay", 10, ~0UL); pnltmp.pon_delay = getenv_ulong("ds1_tondelay", 10, ~0UL); + panel_info.vl_rot = getenv_ulong("ds1_rotation", 10, 0); #endif if ( ~0UL == (pnltmp.hactive) || @@ -281,6 +363,32 @@ int ft_board_setup(void *blob, bd_t *bd) puts("set bootloader version 'bl-version' prop. not in dtb!\n"); return -1; } + /* + * if no simplefb is requested through environment, we don't set up + * one, instead we turn off backlight. + */ + if (getenv_ulong("simplefb", 10, 0) == 0) { + lcdbacklight(0); + return 0; + } + /* Setup simplefb devicetree node, also adapt memory-node, + * upper limit for kernel e.g. linux is memtop-framebuffer alligned + * to a full megabyte. + */ + u64 start = gd->bd->bi_dram[0].start; + u64 size = (gd->fb_base - start) & ~0xFFFFF; + int rc = fdt_fixup_memory_banks(blob, &start, &size, 1); + + if (rc) { + puts("cannot setup simplefb: Error reserving memory!\n"); + return rc; + } + rc = lcd_dt_simplefb_enable_existing_node(blob); + if (rc) { + puts("cannot setup simplefb: error enabling simplefb node!\n"); + return rc; + } + return 0; } #else @@ -389,55 +497,8 @@ void lcd_ctrl_init(void *lcdbase) void lcd_enable(void) { -#ifdef CONFIG_USE_FDT - if (gd->fdt_blob == NULL) { - printf("%s: don't have a valid gd->fdt_blob!\n", __func__); - return; - } - unsigned int driver = FDTPROP(PATHINF, "brightdrv"); - unsigned int bright = FDTPROP(PATHINF, "brightdef"); - unsigned int pwmfrq = FDTPROP(PATHINF, "brightfdim"); -#else - unsigned int driver = getenv_ulong("ds1_bright_drv", 16, 0UL); - unsigned int bright = getenv_ulong("ds1_bright_def", 10, 50); - unsigned int pwmfrq = getenv_ulong("ds1_pwmfreq", 10, ~0UL); -#endif - unsigned int tmp; - struct gptimer *const timerhw = (struct gptimer *)DM_TIMER6_BASE; - - bright = bright != ~0UL ? bright : 50; - - switch (driver) { - case 0: /* PMIC LED-Driver */ - /* brightness level */ - tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, - TPS65217_WLEDCTRL2, bright, 0xFF); - /* turn on light */ - tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, - TPS65217_WLEDCTRL1, 0x0A, 0xFF); - break; - case 1: /* PWM using timer6 */ - if (pwmfrq != ~0UL) { - timerhw->tiocp_cfg = TCFG_RESET; - udelay(10); - while (timerhw->tiocp_cfg & TCFG_RESET) - ; - tmp = ~0UL-(V_OSCK/pwmfrq); /* bottom value */ - timerhw->tldr = tmp; - timerhw->tcrr = tmp; - tmp = tmp + ((V_OSCK/pwmfrq)/100) * bright; - timerhw->tmar = tmp; - timerhw->tclr = (TCLR_PT | (2 << TCLR_TRG_SHIFT) | - TCLR_CE | TCLR_AR | TCLR_ST); - } else { - puts("invalid pwmfrq in env/dtb! skip PWM-setup.\n"); - } - break; - default: - puts("no suitable backlightdriver in env/dtb!\n"); - break; - } br_summaryscreen(); + lcdbacklight(1); } #elif CONFIG_SPL_BUILD #else diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c index 6eed7e0..01dd1d9 100644 --- a/board/BuR/kwb/board.c +++ b/board/BuR/kwb/board.c @@ -214,8 +214,8 @@ int board_late_init(void) gpio_get_value(PUSH_KEY) && 1 == cnt) { lcd_position_cursor(1, 8); lcd_puts( - "updating U-BOOT from USB ... "); - setenv("bootcmd", "run usbupdate"); + "starting u-boot script from USB ... "); + setenv("bootcmd", "run usbscript"); cnt = 4; break; } else if ((!gpio_get_value(ESC_KEY) && diff --git a/board/afeb9260/Kconfig b/board/afeb9260/Kconfig deleted file mode 100644 index fb64c9c..0000000 --- a/board/afeb9260/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_AFEB9260 - -config SYS_BOARD - default "afeb9260" - -config SYS_CONFIG_NAME - default "afeb9260" - -endif diff --git a/board/afeb9260/MAINTAINERS b/board/afeb9260/MAINTAINERS deleted file mode 100644 index 337f302..0000000 --- a/board/afeb9260/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -AFEB9260 BOARD -M: Sergey Lapin <slapin@ossfans.org> -S: Maintained -F: board/afeb9260/ -F: include/configs/afeb9260.h -F: configs/afeb9260_defconfig diff --git a/board/afeb9260/Makefile b/board/afeb9260/Makefile deleted file mode 100644 index e0c3cd5..0000000 --- a/board/afeb9260/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Stelian Pop <stelian@popies.net> -# Lead Tech Design <www.leadtechdesign.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += afeb9260.o -obj-y += partition.o diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c deleted file mode 100644 index ea9575d..0000000 --- a/board/afeb9260/afeb9260.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/at91sam9260.h> -#include <asm/arch/at91sam9260_matrix.h> -#include <asm/arch/at91sam9_smc.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/gpio.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) -#include <netdev.h> -#include <net.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -static void afeb9260_nand_hw_init(void) -{ - unsigned long csa; - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - - /* Assign CS3 to NAND/SmartMedia Interface */ - csa = readl(&matrix->ebicsa); - csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; - writel(csa, &matrix->ebicsa); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | - AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), - &smc->cs[3].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(2), - &smc->cs[3].mode); - - /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); - - /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); -} - -#ifdef CONFIG_MACB -static void afeb9260_macb_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - - - /* Enable EMAC clock */ - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); - - - /* - * Disable pull-up on: - * RXDV (PA17) => PHY normal mode (not Test mode) - * ERX0 (PA14) => PHY ADDR0 - * ERX1 (PA15) => PHY ADDR1 - * ERX2 (PA25) => PHY ADDR2 - * ERX3 (PA26) => PHY ADDR3 - * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 - * - * PHY has internal pull-down - */ - writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA17) | - pin_to_mask(AT91_PIN_PA25) | - pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), - &pioa->pudr); - - at91_phy_reset(); - - /* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA17) | - pin_to_mask(AT91_PIN_PA25) | - pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), - &pioa->puer); - - at91_macb_hw_init(); -} -#endif -int board_early_init_f(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - /* Enable clocks for all PIOs */ - writel((1 << ATMEL_ID_PIOA) | - (1 << ATMEL_ID_PIOB) | - (1 << ATMEL_ID_PIOC), - &pmc->pcer); - return 0; -} -int board_init(void) -{ - /* arch number of AT91SAM9260EK-Board */ - gd->bd->bi_arch_number = MACH_TYPE_AFEB9260; - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - at91_seriald_hw_init(); -#ifdef CONFIG_CMD_NAND - afeb9260_nand_hw_init(); -#endif - at91_spi0_hw_init((1 << 0) | (1 << 1)); -#ifdef CONFIG_MACB - afeb9260_macb_hw_init(); -#endif - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -void reset_phy(void) -{ -} -#endif - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x01); -#endif - return rc; -} diff --git a/board/afeb9260/config.mk b/board/afeb9260/config.mk deleted file mode 100644 index 2077692..0000000 --- a/board/afeb9260/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x21f00000 diff --git a/board/afeb9260/partition.c b/board/afeb9260/partition.c deleted file mode 100644 index 6b71477..0000000 --- a/board/afeb9260/partition.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <config.h> -#include <asm/hardware.h> -#include <dataflash.h> - -AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; - -struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { - {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ - {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1} -}; - -/*define the area offsets*/ -dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { - {0x00000000, 0x000041FF, FLAG_PROTECT_CLEAR, 0, "Bootstrap"}, - {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"}, -}; diff --git a/board/altera/socfpga/Kconfig b/board/altera/socfpga/Kconfig deleted file mode 100644 index cbed8d6..0000000 --- a/board/altera/socfpga/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -if TARGET_SOCFPGA_CYCLONE5 - -config SYS_BOARD - default "socfpga" - -config SYS_VENDOR - default "altera" - -config SYS_SOC - default "socfpga" - -config SYS_CONFIG_NAME - default "socfpga_cyclone5" - -endif - -if TARGET_SOCFPGA_ARRIA5 - -config SYS_BOARD - default "socfpga" - -config SYS_VENDOR - default "altera" - -config SYS_SOC - default "socfpga" - -config SYS_CONFIG_NAME - default "socfpga_arria5" - -endif diff --git a/board/altera/socfpga/iocsr_config.c b/board/altera/socfpga/iocsr_config.c index c79aa6d..3b202b5 100644 --- a/board/altera/socfpga/iocsr_config.c +++ b/board/altera/socfpga/iocsr_config.c @@ -6,7 +6,7 @@ /* This file is generated by Preloader Generator */ -#include <iocsr_config.h> +#include "iocsr_config.h" #ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 const unsigned long iocsr_scan_chain0_table[(( diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig index ef66ad4..a655dbc 100644 --- a/board/amcc/canyonlands/Kconfig +++ b/board/amcc/canyonlands/Kconfig @@ -11,6 +11,7 @@ config SYS_CONFIG_NAME choice BOARD_TYPE prompt "Select which board to build for" + optional config CANYONLANDS bool "Glacier" diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index cb2de2f..d3b3b31 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -181,7 +181,7 @@ ulong get_board_rev(void){ return readl((u32 *)SYS_ID); } -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +#ifdef CONFIG_ARMV7_NONSEC /* Setting the address at which secondary cores start from. * Versatile Express uses one address for all cores, so ignore corenr */ diff --git a/board/avionic-design/medcom-wide/Makefile b/board/avionic-design/medcom-wide/Makefile index bcf7ccf..1351d1f 100644 --- a/board/avionic-design/medcom-wide/Makefile +++ b/board/avionic-design/medcom-wide/Makefile @@ -8,5 +8,3 @@ # obj-y := ../common/tamonten.o - -include $(srctree)/board/nvidia/common/common.mk diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile index bcf7ccf..1351d1f 100644 --- a/board/avionic-design/plutux/Makefile +++ b/board/avionic-design/plutux/Makefile @@ -8,5 +8,3 @@ # obj-y := ../common/tamonten.o - -include $(srctree)/board/nvidia/common/common.mk diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile index a556b92..8ec9b88 100644 --- a/board/avionic-design/tec-ng/Makefile +++ b/board/avionic-design/tec-ng/Makefile @@ -6,5 +6,3 @@ # obj-y := ../common/tamonten-ng.o - -include $(srctree)/board/nvidia/common/common.mk diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile index bcf7ccf..1351d1f 100644 --- a/board/avionic-design/tec/Makefile +++ b/board/avionic-design/tec/Makefile @@ -8,5 +8,3 @@ # obj-y := ../common/tamonten.o - -include $(srctree)/board/nvidia/common/common.mk diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c index 6a70a2e..eaad0b3 100644 --- a/board/broadcom/bcm_ep/board.c +++ b/board/broadcom/bcm_ep/board.c @@ -54,7 +54,7 @@ int board_early_init_f(void) return status; } -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +#ifdef CONFIG_ARMV7_NONSEC void smp_set_core_boot_addr(unsigned long addr, int corenr) { } diff --git a/board/calao/sbc35_a9g20/Kconfig b/board/calao/sbc35_a9g20/Kconfig deleted file mode 100644 index 37ecfb5..0000000 --- a/board/calao/sbc35_a9g20/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SBC35_A9G20 - -config SYS_BOARD - default "sbc35_a9g20" - -config SYS_VENDOR - default "calao" - -config SYS_CONFIG_NAME - default "sbc35_a9g20" - -endif diff --git a/board/calao/sbc35_a9g20/MAINTAINERS b/board/calao/sbc35_a9g20/MAINTAINERS deleted file mode 100644 index 0ac8225..0000000 --- a/board/calao/sbc35_a9g20/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -SBC35_A9G20 BOARD -#M: Albin Tonnerre <albin.tonnerre@free-electrons.com> -S: Orphan (since 2014-06) -F: board/calao/sbc35_a9g20/ -F: include/configs/sbc35_a9g20.h -F: configs/sbc35_a9g20_eeprom_defconfig -F: configs/sbc35_a9g20_nandflash_defconfig diff --git a/board/calao/sbc35_a9g20/Makefile b/board/calao/sbc35_a9g20/Makefile deleted file mode 100644 index 9ae2d24..0000000 --- a/board/calao/sbc35_a9g20/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Stelian Pop <stelian@popies.net> -# Lead Tech Design <www.leadtechdesign.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += sbc35_a9g20.o -obj-$(CONFIG_ATMEL_SPI) += spi.o diff --git a/board/calao/sbc35_a9g20/config.mk b/board/calao/sbc35_a9g20/config.mk deleted file mode 100644 index e554a45..0000000 --- a/board/calao/sbc35_a9g20/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x23f00000 diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c deleted file mode 100644 index 2074a93..0000000 --- a/board/calao/sbc35_a9g20/sbc35_a9g20.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * - * Copyright (C) 2009 - * Albin Tonnerre, Free-Electrons <albin.tonnerre@free-electrons.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/at91sam9260_matrix.h> -#include <asm/arch/at91sam9_smc.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/gpio.h> - -#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) -#include <net.h> -#endif -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -#ifdef CONFIG_CMD_NAND -static void sbc35_a9g20_nand_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - unsigned long csa; - - /* Enable CS3 */ - csa = readl(&matrix->ebicsa); - csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; - writel(csa, &matrix->ebicsa); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | - AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), - &smc->cs[3].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | -#ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_MODE_DBW_16 | -#else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_MODE_DBW_8 | -#endif - AT91_SMC_MODE_TDF_CYCLE(2), - &smc->cs[3].mode); - - writel(1 << ATMEL_ID_PIOC, &pmc->pcer); - - /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); - - /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); -} -#endif - -#ifdef CONFIG_MACB -static void sbc35_a9g20_macb_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - - /* Enable EMAC clock */ - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); - - /* - * Disable pull-up on: - * RXDV (PA17) => PHY normal mode (not Test mode) - * ERX0 (PA14) => PHY ADDR0 - * ERX1 (PA15) => PHY ADDR1 - * ERX2 (PA25) => PHY ADDR2 - * ERX3 (PA26) => PHY ADDR3 - * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 - * - * PHY has internal pull-down - */ - writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA17) | - pin_to_mask(AT91_PIN_PA25) | - pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), - &pioa->pudr); - - at91_phy_reset(); - - /* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA17) | - pin_to_mask(AT91_PIN_PA25) | - pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), - &pioa->puer); - - at91_macb_hw_init(); -} -#endif - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - at91_seriald_hw_init(); - sbc35_a9g20_nand_hw_init(); -#ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 4 | 1 << 5); -#endif -#ifdef CONFIG_MACB - sbc35_a9g20_macb_hw_init(); -#endif - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -void reset_phy(void) -{ -} -#endif - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); -#endif - return rc; -} diff --git a/board/calao/sbc35_a9g20/spi.c b/board/calao/sbc35_a9g20/spi.c deleted file mode 100644 index 254c7a3..0000000 --- a/board/calao/sbc35_a9g20/spi.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (C) 2009 - * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/hardware.h> -#include <asm/arch/at91_spi.h> -#include <asm/arch/gpio.h> -#include <spi.h> - -#define SBC_A9260_CS0_PIN AT91_PIN_PA3 -#define SBC_A9260_CS1_PIN AT91_PIN_PC11 - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && (cs == 1 || cs == 0); -} - -void spi_cs_activate(struct spi_slave *slave) -{ - if(slave->cs == 0) - at91_set_gpio_value(SBC_A9260_CS0_PIN, 0); - else if(slave->cs == 1) - at91_set_gpio_value(SBC_A9260_CS1_PIN, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - if(slave->cs == 0) - at91_set_gpio_value(SBC_A9260_CS0_PIN, 1); - else if(slave->cs == 1) - at91_set_gpio_value(SBC_A9260_CS1_PIN, 1); -} - -void spi_init_f(void) -{ - /* everything done in board_init */ -} diff --git a/board/calao/tny_a9260/Kconfig b/board/calao/tny_a9260/Kconfig deleted file mode 100644 index 2b66329..0000000 --- a/board/calao/tny_a9260/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_TNY_A9260 - -config SYS_BOARD - default "tny_a9260" - -config SYS_VENDOR - default "calao" - -config SYS_CONFIG_NAME - default "tny_a9260" - -endif diff --git a/board/calao/tny_a9260/MAINTAINERS b/board/calao/tny_a9260/MAINTAINERS deleted file mode 100644 index 1f24e39..0000000 --- a/board/calao/tny_a9260/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -TNY_A9260 BOARD -#M: Albin Tonnerre <albin.tonnerre@free-electrons.com> -S: Orphan (since 2014-06) -F: board/calao/tny_a9260/ -F: include/configs/tny_a9260.h -F: configs/tny_a9260_eeprom_defconfig -F: configs/tny_a9260_nandflash_defconfig -F: configs/tny_a9g20_eeprom_defconfig -F: configs/tny_a9g20_nandflash_defconfig diff --git a/board/calao/tny_a9260/Makefile b/board/calao/tny_a9260/Makefile deleted file mode 100644 index 55a6157..0000000 --- a/board/calao/tny_a9260/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Stelian Pop <stelian@popies.net> -# Lead Tech Design <www.leadtechdesign.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += tny_a9260.o -obj-$(CONFIG_ATMEL_SPI) += spi.o diff --git a/board/calao/tny_a9260/config.mk b/board/calao/tny_a9260/config.mk deleted file mode 100644 index e554a45..0000000 --- a/board/calao/tny_a9260/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x23f00000 diff --git a/board/calao/tny_a9260/spi.c b/board/calao/tny_a9260/spi.c deleted file mode 100644 index 26ba5f5..0000000 --- a/board/calao/tny_a9260/spi.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2009 - * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/hardware.h> -#include <asm/arch/at91_spi.h> -#include <asm/arch/gpio.h> -#include <spi.h> - -#define TNY_A9260_CS_PIN AT91_PIN_PC11 - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 1; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - at91_set_gpio_value(TNY_A9260_CS_PIN, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - at91_set_gpio_value(TNY_A9260_CS_PIN, 1); -} - -void spi_init_f(void) -{ - /* everything done in board_init */ -} diff --git a/board/calao/tny_a9260/tny_a9260.c b/board/calao/tny_a9260/tny_a9260.c deleted file mode 100644 index 337be43..0000000 --- a/board/calao/tny_a9260/tny_a9260.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * - * Copyright (C) 2009 - * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/at91sam9_matrix.h> -#include <asm/arch/at91sam9_smc.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/hardware.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -static void tny_a9260_nand_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - unsigned long csa; - - /* Assign CS3 to NAND/SmartMedia Interface */ - csa = readl(&matrix->ebicsa); - csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; - writel(csa, &matrix->ebicsa); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | - AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), - &smc->cs[3].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | -#ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_MODE_DBW_16 | -#else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_MODE_DBW_8 | -#endif - AT91_SMC_MODE_TDF_CYCLE(2), - &smc->cs[3].mode); - - writel(1 << ATMEL_ID_PIOC, &pmc->pcer); - - /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); - - /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - at91_seriald_hw_init(); - tny_a9260_nand_hw_init(); - at91_spi0_hw_init(1 << 5); - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile index e6a0b29..b5fde8d 100644 --- a/board/compal/paz00/Makefile +++ b/board/compal/paz00/Makefile @@ -15,5 +15,3 @@ # obj-y := paz00.o - -include $(srctree)/board/nvidia/common/common.mk diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile index 311eb92..5396b21 100644 --- a/board/compulab/trimslice/Makefile +++ b/board/compulab/trimslice/Makefile @@ -6,5 +6,3 @@ # obj-y := trimslice.o - -include $(srctree)/board/nvidia/common/common.mk diff --git a/board/coreboot/Kconfig b/board/coreboot/Kconfig index dc9b70f..ede6065 100644 --- a/board/coreboot/Kconfig +++ b/board/coreboot/Kconfig @@ -8,6 +8,7 @@ if VENDOR_COREBOOT choice prompt "Mainboard model" + optional config TARGET_COREBOOT bool "coreboot" diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig index 1286e45..b813adb 100644 --- a/board/dbau1x00/Kconfig +++ b/board/dbau1x00/Kconfig @@ -13,6 +13,7 @@ menu "dbau1x00 board options" choice prompt "Select au1x00 SoC type" + optional config DBAU1100 bool "Select AU1100" diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index c06b862..8e8b7fa 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/io.h> -#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT) +#ifndef CONFIG_ARMV7_NONSEC #error " Deep sleep needs non-secure mode support. " #else #include <asm/secure.h> diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile index 33a1788..8fa691a 100644 --- a/board/gateworks/gw_ventana/Makefile +++ b/board/gateworks/gw_ventana/Makefile @@ -6,6 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := gw_ventana.o gsc.o eeprom.o +obj-y := gw_ventana.o gsc.o eeprom.o common.o obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c new file mode 100644 index 0000000..5fa5d6a --- /dev/null +++ b/board/gateworks/gw_ventana/common.c @@ -0,0 +1,827 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * Author: Tim Harvey <tharvey@gateworks.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/mxc_i2c.h> +#include <hwconfig.h> +#include <power/pmic.h> +#include <power/ltc3676_pmic.h> +#include <power/pfuze100_pmic.h> + +#include "common.h" + +/* UART1: Function varies per baseboard */ +static iomux_v3_cfg_t const uart1_pads[] = { + IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +/* UART2: Serial Console */ +static iomux_v3_cfg_t const uart2_pads[] = { + IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); + SETUP_IOMUX_PADS(uart2_pads); +} + +/* I2C1: GSC */ +static struct i2c_pads_info mx6q_i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; +static struct i2c_pads_info mx6dl_i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ +static struct i2c_pads_info mx6q_i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; +static struct i2c_pads_info mx6dl_i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* I2C3: Misc/Expansion */ +static struct i2c_pads_info mx6q_i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; +static struct i2c_pads_info mx6dl_i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +void setup_ventana_i2c(void) +{ + if (is_cpu_type(MXC_CPU_MX6Q)) { + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); + } else { + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); + } +} + +/* + * Baseboard specific GPIO + */ + +/* common to add baseboards */ +static iomux_v3_cfg_t const gw_gpio_pads[] = { + /* MSATA_EN */ + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), + /* RS232_EN# */ + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), +}; + +/* prototype */ +static iomux_v3_cfg_t const gwproto_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + /* VID_EN */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* DIOI2C_DIS# */ + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), + /* PCICK_SSON */ + IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + + /* GPS_SHDN */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), + /* VID_PWR */ + IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* GPS_SHDN */ + IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), + /* USBOTG_SEL */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), + /* VID_PWR */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* PCI_RST# (GW522x) */ + IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + /* DIOI2C_DIS# */ + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), + /* GPS_SHDN */ + IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), + /* VID_EN */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* MIPI_DIO */ + IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + /* DIOI2C_DIS# */ + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* VID_EN */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw551x_gpio_pads[] = { + /* PANLED# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw552x_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* MX6_DIO[4:9] */ + IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG), + /* PCIEGBE1_OFF# */ + IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), + /* PCIEGBE2_OFF# */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + + +/* + * Board Specific GPIO + */ +struct ventana gpio_cfg[GW_UNKNOWN] = { + /* GW5400proto */ + { + .gpio_pads = gw54xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, + IMX_GPIO_NR(1, 9), + { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, + 1 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, + IMX_GPIO_NR(2, 9), + { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, + IMX_GPIO_NR(2, 10), + { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, + 4 + }, + }, + .num_gpios = 4, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 10), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(4, 7), + .mezz_irq = IMX_GPIO_NR(4, 9), + .rs485en = IMX_GPIO_NR(3, 24), + .dioi2c_en = IMX_GPIO_NR(4, 5), + .pcie_sson = IMX_GPIO_NR(1, 20), + }, + + /* GW51xx */ + { + .gpio_pads = gw51xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, + IMX_GPIO_NR(1, 18), + { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, + 4 + }, + }, + .num_gpios = 4, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 10), + }, + .pcie_rst = IMX_GPIO_NR(1, 0), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 2), + .vidin_en = IMX_GPIO_NR(5, 20), + .wdis = IMX_GPIO_NR(7, 12), + }, + + /* GW52xx */ + { + .gpio_pads = gw52xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, + }, + .num_gpios = 4, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 27), + .vidin_en = IMX_GPIO_NR(3, 31), + .usb_sel = IMX_GPIO_NR(1, 2), + .wdis = IMX_GPIO_NR(7, 12), + }, + + /* GW53xx */ + { + .gpio_pads = gw53xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, + }, + .num_gpios = 4, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 27), + .vidin_en = IMX_GPIO_NR(3, 31), + .wdis = IMX_GPIO_NR(7, 12), + }, + + /* GW54xx */ + { + .gpio_pads = gw54xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, + IMX_GPIO_NR(1, 9), + { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, + 1 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, + IMX_GPIO_NR(2, 9), + { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, + IMX_GPIO_NR(2, 10), + { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, + 4 + }, + }, + .num_gpios = 4, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .rs485en = IMX_GPIO_NR(7, 1), + .vidin_en = IMX_GPIO_NR(3, 31), + .dioi2c_en = IMX_GPIO_NR(4, 5), + .pcie_sson = IMX_GPIO_NR(1, 20), + .wdis = IMX_GPIO_NR(5, 17), + }, + + /* GW551x */ + { + .gpio_pads = gw551x_gpio_pads, + .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, + IMX_GPIO_NR(1, 18), + { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, + 4 + }, + }, + .num_gpios = 2, + .leds = { + IMX_GPIO_NR(4, 7), + }, + .pcie_rst = IMX_GPIO_NR(1, 0), + .wdis = IMX_GPIO_NR(7, 12), + }, + + /* GW552x */ + { + .gpio_pads = gw552x_gpio_pads, + .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + }, + .num_gpios = 4, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .wdis = IMX_GPIO_NR(7, 12), + }, +}; + +void setup_iomux_gpio(int board, struct ventana_board_info *info) +{ + int i; + + /* iomux common to all Ventana boards */ + SETUP_IOMUX_PADS(gw_gpio_pads); + + /* OTG power off */ + gpio_request(GP_USB_OTG_PWR, "usbotg_pwr"); + gpio_direction_output(GP_USB_OTG_PWR, 0); + + /* MSATA Enable - default to PCI */ + gpio_request(GP_MSATA_SEL, "msata_en"); + gpio_direction_output(GP_MSATA_SEL, 0); + + /* RS232_EN# */ + gpio_request(GP_RS232_EN, "rs232_en"); + gpio_direction_output(GP_RS232_EN, 0); + + if (board >= GW_UNKNOWN) + return; + + /* board specific iomux */ + imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads, + gpio_cfg[board].num_pads); + + /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ + if (board == GW52xx && info->model[4] == '2') + gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23); + + /* assert PCI_RST# */ + gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#"); + gpio_direction_output(gpio_cfg[board].pcie_rst, 0); + + /* turn off (active-high) user LED's */ + for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { + char name[16]; + if (gpio_cfg[board].leds[i]) { + sprintf(name, "led_user%d", i); + gpio_request(gpio_cfg[board].leds[i], name); + gpio_direction_output(gpio_cfg[board].leds[i], 1); + } + } + + /* Expansion Mezzanine IO */ + if (gpio_cfg[board].mezz_pwren) { + gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr"); + gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); + } + if (gpio_cfg[board].mezz_irq) { + gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#"); + gpio_direction_input(gpio_cfg[board].mezz_irq); + } + + /* RS485 Transmit Enable */ + if (gpio_cfg[board].rs485en) { + gpio_request(gpio_cfg[board].rs485en, "rs485_en"); + gpio_direction_output(gpio_cfg[board].rs485en, 0); + } + + /* GPS_SHDN */ + if (gpio_cfg[board].gps_shdn) { + gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn"); + gpio_direction_output(gpio_cfg[board].gps_shdn, 1); + } + + /* Analog video codec power enable */ + if (gpio_cfg[board].vidin_en) { + gpio_request(gpio_cfg[board].vidin_en, "anavidin_en"); + gpio_direction_output(gpio_cfg[board].vidin_en, 1); + } + + /* DIOI2C_DIS# */ + if (gpio_cfg[board].dioi2c_en) { + gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#"); + gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); + } + + /* PCICK_SSON: disable spread-spectrum clock */ + if (gpio_cfg[board].pcie_sson) { + gpio_request(gpio_cfg[board].pcie_sson, "pci_sson"); + gpio_direction_output(gpio_cfg[board].pcie_sson, 0); + } + + /* USBOTG mux routing */ + if (gpio_cfg[board].usb_sel) { + gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel"); + gpio_direction_output(gpio_cfg[board].usb_sel, 0); + } + + /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ + if (gpio_cfg[board].wdis) { + gpio_request(gpio_cfg[board].wdis, "wlan_dis"); + gpio_direction_output(gpio_cfg[board].wdis, 1); + } +} + +/* setup GPIO pinmux and default configuration per baseboard and env */ +void setup_board_gpio(int board, struct ventana_board_info *info) +{ + const char *s; + char arg[10]; + size_t len; + int i; + int quiet = simple_strtol(getenv("quiet"), NULL, 10); + + if (board >= GW_UNKNOWN) + return; + + /* RS232_EN# */ + gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1); + + /* MSATA Enable */ + if (is_cpu_type(MXC_CPU_MX6Q) && + test_bit(EECONFIG_SATA, info->config)) { + gpio_direction_output(GP_MSATA_SEL, + (hwconfig("msata")) ? 1 : 0); + } + + /* USBOTG Select (PCISKT or FrontPanel) */ + if (gpio_cfg[board].usb_sel) { + gpio_direction_output(gpio_cfg[board].usb_sel, + (hwconfig("usb_pcisel")) ? 1 : 0); + } + + /* + * Configure DIO pinmux/padctl registers + * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions + */ + for (i = 0; i < 4; i++) { + struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; + iomux_v3_cfg_t ctrl = DIO_PAD_CFG; + unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; + + if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1]) + continue; + sprintf(arg, "dio%d", i); + if (!hwconfig(arg)) + continue; + s = hwconfig_subarg(arg, "padctrl", &len); + if (s) { + ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16) + & 0x1ffff) | MUX_MODE_SION; + } + if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { + if (!quiet) { + printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, + (cfg->gpio_param/32)+1, + cfg->gpio_param%32, + cfg->gpio_param); + } + imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | + ctrl); + gpio_requestf(cfg->gpio_param, "dio%d", i); + gpio_direction_input(cfg->gpio_param); + } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && + cfg->pwm_padmux) { + if (!quiet) + printf("DIO%d: pwm%d\n", i, cfg->pwm_param); + imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] | + MUX_PAD_CTRL(ctrl)); + } + } + + if (!quiet) { + if (is_cpu_type(MXC_CPU_MX6Q) && + (test_bit(EECONFIG_SATA, info->config))) { + printf("MSATA: %s\n", (hwconfig("msata") ? + "enabled" : "disabled")); + } + printf("RS232: %s\n", (hwconfig("rs232")) ? + "enabled" : "disabled"); + } +} + +/* setup board specific PMIC */ +void setup_pmic(void) +{ + struct pmic *p; + u32 reg; + + i2c_set_bus_num(CONFIG_I2C_PMIC); + + /* configure PFUZE100 PMIC */ + if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) { + debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR); + power_pfuze100_init(CONFIG_I2C_PMIC); + p = pmic_get("PFUZE100"); + if (p && !pmic_probe(p)) { + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set VGEN1 to 1.5V and enable */ + pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); + reg &= ~(LDO_VOL_MASK); + reg |= (LDOA_1_50V | LDO_EN); + pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); + + /* Set SWBST to 5.0V and enable */ + pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); + reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); + reg |= (SWBST_5_00V | SWBST_MODE_AUTO); + pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); + } + } + + /* configure LTC3676 PMIC */ + else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) { + debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR); + power_ltc3676_init(CONFIG_I2C_PMIC); + p = pmic_get("LTC3676_PMIC"); + if (p && !pmic_probe(p)) { + puts("PMIC: LTC3676\n"); + /* + * set board-specific scalar for max CPU frequency + * per CPU based on the LDO enabled Operating Ranges + * defined in the respective IMX6DQ and IMX6SDL + * datasheets. The voltage resulting from the R1/R2 + * feedback inputs on Ventana is 1308mV. Note that this + * is a bit shy of the Vmin of 1350mV in the datasheet + * for LDO enabled mode but is as high as we can go. + * + * We will rely on an OS kernel driver to properly + * regulate these per CPU operating point and use LDO + * bypass mode when using the higher frequency + * operating points to compensate as LDO bypass mode + * allows the rails be 125mV lower. + */ + /* mask PGOOD during SW1 transition */ + pmic_reg_write(p, LTC3676_DVB1B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW1 (VDD_SOC) */ + pmic_reg_write(p, LTC3676_DVB1A, 0x1f); + + /* mask PGOOD during SW3 transition */ + pmic_reg_write(p, LTC3676_DVB3B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW3 (VDD_ARM) */ + pmic_reg_write(p, LTC3676_DVB3A, 0x1f); + } + } +} diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h new file mode 100644 index 0000000..b7c0e96 --- /dev/null +++ b/board/gateworks/gw_ventana/common.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * Author: Tim Harvey <tharvey@gateworks.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _GWVENTANA_COMMON_H_ +#define _GWVENTANA_COMMON_H_ + +#include "ventana_eeprom.h" + +/* GPIO's common to all baseboards */ +#define GP_PHY_RST IMX_GPIO_NR(1, 30) +#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define GP_SD3_CD IMX_GPIO_NR(7, 0) +#define GP_RS232_EN IMX_GPIO_NR(2, 11) +#define GP_MSATA_SEL IMX_GPIO_NR(2, 8) + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) + +#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION) + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* + * each baseboard has 4 user configurable Digital IO lines which can + * be pinmuxed as a GPIO or in some cases a PWM + */ +struct dio_cfg { + iomux_v3_cfg_t gpio_padmux[2]; + unsigned gpio_param; + iomux_v3_cfg_t pwm_padmux[2]; + unsigned pwm_param; +}; + +struct ventana { + /* pinmux */ + iomux_v3_cfg_t const *gpio_pads; + int num_pads; + /* DIO pinmux/val */ + struct dio_cfg dio_cfg[4]; + int num_gpios; + /* various gpios (0 if non-existent) */ + int leds[3]; + int pcie_rst; + int mezz_pwren; + int mezz_irq; + int rs485en; + int gps_shdn; + int vidin_en; + int dioi2c_en; + int pcie_sson; + int usb_sel; + int wdis; +}; + +extern struct ventana gpio_cfg[GW_UNKNOWN]; + +/* configure i2c iomux */ +void setup_ventana_i2c(void); +/* configure uart iomux */ +void setup_iomux_uart(void); +/* conifgure PMIC */ +void setup_pmic(void); +/* configure gpio iomux/defaults */ +void setup_iomux_gpio(int board, struct ventana_board_info *); +/* late setup of GPIO (configuration per baseboard and env) */ +void setup_board_gpio(int board, struct ventana_board_info *); + +#endif /* #ifndef _GWVENTANA_COMMON_H_ */ diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c index 718e165..3febd12 100644 --- a/board/gateworks/gw_ventana/gsc.c +++ b/board/gateworks/gw_ventana/gsc.c @@ -132,6 +132,33 @@ int gsc_info(int verbose) return 0; } +/* + * The Gateworks System Controller implements a boot + * watchdog (always enabled) as a workaround for IMX6 boot related + * errata such as: + * ERR005768 - no fix scheduled + * ERR006282 - fixed in silicon r1.2 + * ERR007117 - fixed in silicon r1.3 + * ERR007220 - fixed in silicon r1.3 + * ERR007926 - no fix scheduled + * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf + * + * Disable the boot watchdog + */ +int gsc_boot_wd_disable(void) +{ + u8 reg; + + i2c_set_bus_num(CONFIG_I2C_GSC); + if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) { + reg |= (1 << GSC_SC_CTRL1_WDDIS); + if (!gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + return 0; + } + puts("Error: could not disable GSC Watchdog\n"); + return 1; +} + #ifdef CONFIG_CMD_GSC static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h index 2d4969e..e0c0ed0 100644 --- a/board/gateworks/gw_ventana/gsc.h +++ b/board/gateworks/gw_ventana/gsc.h @@ -66,5 +66,6 @@ enum { int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len); int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len); int gsc_info(int verbose); +int gsc_boot_wd_disable(void); #endif diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 1e54912..22f3b38 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -7,29 +7,26 @@ */ #include <common.h> -#include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> #include <asm/arch/iomux.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/mxc_hdmi.h> -#include <asm/arch/crm_regs.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/imx-common/iomux-v3.h> -#include <asm/imx-common/mxc_i2c.h> #include <asm/imx-common/boot_mode.h> #include <asm/imx-common/sata.h> #include <asm/imx-common/spi.h> #include <asm/imx-common/video.h> -#include <jffs2/load_kernel.h> -#include <hwconfig.h> +#include <asm/io.h> +#include <dm.h> +#include <dm/platform_data/serial_mxc.h> #include <i2c.h> -#include <linux/ctype.h> #include <fdt_support.h> #include <fsl_esdhc.h> +#include <jffs2/load_kernel.h> +#include <linux/ctype.h> #include <miiphy.h> -#include <mmc.h> #include <mtd_node.h> #include <netdev.h> #include <pci.h> @@ -41,47 +38,10 @@ #include <spi_flash.h> #include "gsc.h" -#include "ventana_eeprom.h" +#include "common.h" DECLARE_GLOBAL_DATA_PTR; -/* GPIO's common to all baseboards */ -#define GP_PHY_RST IMX_GPIO_NR(1, 30) -#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) -#define GP_SD3_CD IMX_GPIO_NR(7, 0) -#define GP_RS232_EN IMX_GPIO_NR(2, 11) -#define GP_MSATA_SEL IMX_GPIO_NR(2, 8) - -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | \ - PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) - -#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION) - /* * EEPROM board info struct populated by read_eeprom so that we only have to @@ -91,98 +51,6 @@ struct ventana_board_info ventana_info; static int board_type; -/* UART1: Function varies per baseboard */ -static iomux_v3_cfg_t const uart1_pads[] = { - IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - -/* UART2: Serial Console */ -static iomux_v3_cfg_t const uart2_pads[] = { - IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -/* I2C1: GSC */ -static struct i2c_pads_info mx6q_i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, - .gp = IMX_GPIO_NR(3, 28) - } -}; -static struct i2c_pads_info mx6dl_i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, - .gp = IMX_GPIO_NR(3, 28) - } -}; - -/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ -static struct i2c_pads_info mx6q_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; -static struct i2c_pads_info mx6dl_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -/* I2C3: Misc/Expansion */ -static struct i2c_pads_info mx6q_i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } -}; -static struct i2c_pads_info mx6dl_i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } -}; - /* MMC */ static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), @@ -268,20 +136,15 @@ static void setup_gpmi_nand(void) } #endif -static void setup_iomux_enet(void) +static void setup_iomux_enet(int gpio) { SETUP_IOMUX_PADS(enet_pads); /* toggle PHY_RST# */ - gpio_direction_output(GP_PHY_RST, 0); + gpio_request(gpio, "phy_rst#"); + gpio_direction_output(gpio, 0); mdelay(2); - gpio_set_value(GP_PHY_RST, 1); -} - -static void setup_iomux_uart(void) -{ - SETUP_IOMUX_PADS(uart1_pads); - SETUP_IOMUX_PADS(uart2_pads); + gpio_set_value(gpio, 1); } #ifdef CONFIG_USB_EHCI_MX6 @@ -295,6 +158,7 @@ static iomux_v3_cfg_t const usb_pads[] = { int board_ehci_hcd_init(int port) { struct ventana_board_info *info = &ventana_info; + int gpio; SETUP_IOMUX_PADS(usb_pads); @@ -303,18 +167,22 @@ int board_ehci_hcd_init(int port) case '3': /* GW53xx */ case '5': /* GW552x */ SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG); - gpio_direction_output(IMX_GPIO_NR(1, 9), 0); - mdelay(2); - gpio_set_value(IMX_GPIO_NR(1, 9), 1); + gpio = (IMX_GPIO_NR(1, 9)); break; case '4': /* GW54xx */ SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG); - gpio_direction_output(IMX_GPIO_NR(1, 16), 0); - mdelay(2); - gpio_set_value(IMX_GPIO_NR(1, 16), 1); + gpio = (IMX_GPIO_NR(1, 16)); break; + default: + return 0; } + /* request and toggle hub rst */ + gpio_request(gpio, "usb_hub_rst#"); + gpio_direction_output(gpio, 0); + mdelay(2); + gpio_set_value(gpio, 1); + return 0; } @@ -333,6 +201,7 @@ static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; int board_mmc_getcd(struct mmc *mmc) { /* Card Detect */ + gpio_request(GP_SD3_CD, "sd_cd"); gpio_direction_input(GP_SD3_CD); return !gpio_get_value(GP_SD3_CD); } @@ -364,6 +233,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) static void setup_spi(void) { + gpio_request(IMX_GPIO_NR(3, 19), "spi_cs"); gpio_direction_output(IMX_GPIO_NR(3, 19), 1); SETUP_IOMUX_PADS(ecspi1_pads); } @@ -399,7 +269,7 @@ int board_eth_init(bd_t *bis) { #ifdef CONFIG_FEC_MXC if (board_type != GW551x && board_type != GW552x) { - setup_iomux_enet(); + setup_iomux_enet(GP_PHY_RST); cpu_eth_init(bis); } #endif @@ -449,6 +319,7 @@ static void enable_lvds(struct display_info_t const *dev) writel(reg, &iomux->gpr[2]); /* Enable Backlight */ + gpio_request(IMX_GPIO_NR(1, 18), "bklt_en"); SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG); gpio_direction_output(IMX_GPIO_NR(1, 18), 1); } @@ -588,692 +459,25 @@ static void setup_display(void) writel(reg, &iomux->gpr[3]); /* Backlight CABEN on LVDS connector */ + gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio"); SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG); gpio_direction_output(IMX_GPIO_NR(1, 10), 0); } #endif /* CONFIG_VIDEO_IPUV3 */ -/* - * Baseboard specific GPIO - */ - -/* common to add baseboards */ -static iomux_v3_cfg_t const gw_gpio_pads[] = { - /* MSATA_EN */ - IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), - /* RS232_EN# */ - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), -}; - -/* prototype */ -static iomux_v3_cfg_t const gwproto_gpio_pads[] = { - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* RS485_EN */ - IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* DIOI2C_DIS# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* PCICK_SSON */ - IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - - /* GPS_SHDN */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* VID_PWR */ - IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* GPS_SHDN */ - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), - /* USBOTG_SEL */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* VID_PWR */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* PCI_RST# (GW522x) */ - IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - /* DIOI2C_DIS# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* GPS_SHDN */ - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), - /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* MIPI_DIO */ - IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), - /* RS485_EN */ - IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - /* DIOI2C_DIS# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw551x_gpio_pads[] = { - /* PANLED# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw552x_gpio_pads[] = { - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* MX6_DIO[4:9] */ - IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG), - /* PCIEGBE1_OFF# */ - IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), - /* PCIEGBE2_OFF# */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -/* - * each baseboard has 4 user configurable Digital IO lines which can - * be pinmuxed as a GPIO or in some cases a PWM - */ -struct dio_cfg { - iomux_v3_cfg_t gpio_padmux[2]; - unsigned gpio_param; - iomux_v3_cfg_t pwm_padmux[2]; - unsigned pwm_param; -}; - -struct ventana { - /* pinmux */ - iomux_v3_cfg_t const *gpio_pads; - int num_pads; - /* DIO pinmux/val */ - struct dio_cfg dio_cfg[4]; - int num_gpios; - /* various gpios (0 if non-existent) */ - int leds[3]; - int pcie_rst; - int mezz_pwren; - int mezz_irq; - int rs485en; - int gps_shdn; - int vidin_en; - int dioi2c_en; - int pcie_sson; - int usb_sel; - int wdis; -}; - -static struct ventana gpio_cfg[] = { - /* GW5400proto */ - { - .gpio_pads = gw54xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, - IMX_GPIO_NR(1, 9), - { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, - 1 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, - IMX_GPIO_NR(2, 9), - { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, - IMX_GPIO_NR(2, 10), - { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, - 4 - }, - }, - .num_gpios = 4, - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 10), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .mezz_pwren = IMX_GPIO_NR(4, 7), - .mezz_irq = IMX_GPIO_NR(4, 9), - .rs485en = IMX_GPIO_NR(3, 24), - .dioi2c_en = IMX_GPIO_NR(4, 5), - .pcie_sson = IMX_GPIO_NR(1, 20), - }, - - /* GW51xx */ - { - .gpio_pads = gw51xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, - IMX_GPIO_NR(1, 18), - { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, - 4 - }, - }, - .num_gpios = 4, - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 10), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .gps_shdn = IMX_GPIO_NR(1, 2), - .vidin_en = IMX_GPIO_NR(5, 20), - .wdis = IMX_GPIO_NR(7, 12), - }, - - /* GW52xx */ - { - .gpio_pads = gw52xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(1, 20), - { 0, 0 }, - 0 - }, - }, - .num_gpios = 4, - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .gps_shdn = IMX_GPIO_NR(1, 27), - .vidin_en = IMX_GPIO_NR(3, 31), - .usb_sel = IMX_GPIO_NR(1, 2), - .wdis = IMX_GPIO_NR(7, 12), - }, - - /* GW53xx */ - { - .gpio_pads = gw53xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(1, 20), - { 0, 0 }, - 0 - }, - }, - .num_gpios = 4, - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .gps_shdn = IMX_GPIO_NR(1, 27), - .vidin_en = IMX_GPIO_NR(3, 31), - .wdis = IMX_GPIO_NR(7, 12), - }, - - /* GW54xx */ - { - .gpio_pads = gw54xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, - IMX_GPIO_NR(1, 9), - { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, - 1 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, - IMX_GPIO_NR(2, 9), - { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, - IMX_GPIO_NR(2, 10), - { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, - 4 - }, - }, - .num_gpios = 4, - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .rs485en = IMX_GPIO_NR(7, 1), - .vidin_en = IMX_GPIO_NR(3, 31), - .dioi2c_en = IMX_GPIO_NR(4, 5), - .pcie_sson = IMX_GPIO_NR(1, 20), - .wdis = IMX_GPIO_NR(5, 17), - }, - - /* GW551x */ - { - .gpio_pads = gw551x_gpio_pads, - .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, - IMX_GPIO_NR(1, 18), - { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, - 4 - }, - }, - .num_gpios = 2, - .leds = { - IMX_GPIO_NR(4, 7), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), - .wdis = IMX_GPIO_NR(7, 12), - }, - - /* GW552x */ - { - .gpio_pads = gw552x_gpio_pads, - .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - }, - .num_gpios = 4, - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .wdis = IMX_GPIO_NR(7, 12), - }, -}; - /* setup board specific PMIC */ int power_init_board(void) { - struct pmic *p; - u32 reg; - - /* configure PFUZE100 PMIC */ - if (board_type == GW54xx || board_type == GW54proto) { - power_pfuze100_init(CONFIG_I2C_PMIC); - p = pmic_get("PFUZE100"); - if (p && !pmic_probe(p)) { - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - - /* Set VGEN1 to 1.5V and enable */ - pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); - reg &= ~(LDO_VOL_MASK); - reg |= (LDOA_1_50V | LDO_EN); - pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); - - /* Set SWBST to 5.0V and enable */ - pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); - reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); - reg |= (SWBST_5_00V | SWBST_MODE_AUTO); - pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); - } - } - - /* configure LTC3676 PMIC */ - else { - power_ltc3676_init(CONFIG_I2C_PMIC); - p = pmic_get("LTC3676_PMIC"); - if (p && !pmic_probe(p)) { - puts("PMIC: LTC3676\n"); - /* - * set board-specific scalar for max CPU frequency - * per CPU based on the LDO enabled Operating Ranges - * defined in the respective IMX6DQ and IMX6SDL - * datasheets. The voltage resulting from the R1/R2 - * feedback inputs on Ventana is 1308mV. Note that this - * is a bit shy of the Vmin of 1350mV in the datasheet - * for LDO enabled mode but is as high as we can go. - * - * We will rely on an OS kernel driver to properly - * regulate these per CPU operating point and use LDO - * bypass mode when using the higher frequency - * operating points to compensate as LDO bypass mode - * allows the rails be 125mV lower. - */ - /* mask PGOOD during SW1 transition */ - pmic_reg_write(p, LTC3676_DVB1B, - 0x1f | LTC3676_PGOOD_MASK); - /* set SW1 (VDD_SOC) */ - pmic_reg_write(p, LTC3676_DVB1A, 0x1f); - - /* mask PGOOD during SW3 transition */ - pmic_reg_write(p, LTC3676_DVB3B, - 0x1f | LTC3676_PGOOD_MASK); - /* set SW3 (VDD_ARM) */ - pmic_reg_write(p, LTC3676_DVB3A, 0x1f); - } - } - + setup_pmic(); return 0; } -/* setup GPIO pinmux and default configuration per baseboard */ -static void setup_board_gpio(int board) -{ - struct ventana_board_info *info = &ventana_info; - const char *s; - char arg[10]; - size_t len; - int i; - int quiet = simple_strtol(getenv("quiet"), NULL, 10); - - if (board >= GW_UNKNOWN) - return; - - /* RS232_EN# */ - gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1); - - /* MSATA Enable */ - if (is_cpu_type(MXC_CPU_MX6Q) && - test_bit(EECONFIG_SATA, info->config)) { - gpio_direction_output(GP_MSATA_SEL, - (hwconfig("msata")) ? 1 : 0); - } else { - gpio_direction_output(GP_MSATA_SEL, 0); - } - -#if !defined(CONFIG_CMD_PCI) - /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ - if (board_type == GW52xx && info->model[4] == '2') - gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23); - - /* assert PCI_RST# (released by OS when clock is valid) */ - gpio_direction_output(gpio_cfg[board].pcie_rst, 0); -#endif - - /* turn off (active-high) user LED's */ - for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { - if (gpio_cfg[board].leds[i]) - gpio_direction_output(gpio_cfg[board].leds[i], 1); - } - - /* Expansion Mezzanine IO */ - if (gpio_cfg[board].mezz_pwren) - gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); - if (gpio_cfg[board].mezz_irq) - gpio_direction_input(gpio_cfg[board].mezz_irq); - - /* RS485 Transmit Enable */ - if (gpio_cfg[board].rs485en) - gpio_direction_output(gpio_cfg[board].rs485en, 0); - - /* GPS_SHDN */ - if (gpio_cfg[board].gps_shdn) - gpio_direction_output(gpio_cfg[board].gps_shdn, 1); - - /* Analog video codec power enable */ - if (gpio_cfg[board].vidin_en) - gpio_direction_output(gpio_cfg[board].vidin_en, 1); - - /* DIOI2C_DIS# */ - if (gpio_cfg[board].dioi2c_en) - gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); - - /* PCICK_SSON: disable spread-spectrum clock */ - if (gpio_cfg[board].pcie_sson) - gpio_direction_output(gpio_cfg[board].pcie_sson, 0); - - /* USBOTG Select (PCISKT or FrontPanel) */ - if (gpio_cfg[board].usb_sel) - gpio_direction_output(gpio_cfg[board].usb_sel, - (hwconfig("usb_pcisel")) ? 1 : 0); - - - /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ - if (gpio_cfg[board].wdis) - gpio_direction_output(gpio_cfg[board].wdis, 1); - - /* - * Configure DIO pinmux/padctl registers - * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions - */ - for (i = 0; i < 4; i++) { - struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; - iomux_v3_cfg_t ctrl = DIO_PAD_CFG; - unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; - - if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1]) - continue; - sprintf(arg, "dio%d", i); - if (!hwconfig(arg)) - continue; - s = hwconfig_subarg(arg, "padctrl", &len); - if (s) { - ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16) - & 0x1ffff) | MUX_MODE_SION; - } - if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { - if (!quiet) { - printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, - (cfg->gpio_param/32)+1, - cfg->gpio_param%32, - cfg->gpio_param); - } - imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | - ctrl); - gpio_direction_input(cfg->gpio_param); - } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && - cfg->pwm_padmux) { - if (!quiet) - printf("DIO%d: pwm%d\n", i, cfg->pwm_param); - imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] | - MUX_PAD_CTRL(ctrl)); - } - } - - if (!quiet) { - if (is_cpu_type(MXC_CPU_MX6Q) && - (test_bit(EECONFIG_SATA, info->config))) { - printf("MSATA: %s\n", (hwconfig("msata") ? - "enabled" : "disabled")); - } - printf("RS232: %s\n", (hwconfig("rs232")) ? - "enabled" : "disabled"); - } -} - #if defined(CONFIG_CMD_PCI) int imx6_pcie_toggle_reset(void) { if (board_type < GW_UNKNOWN) { uint pin = gpio_cfg[board_type].pcie_rst; + gpio_request(pin, "pci_rst#"); gpio_direction_output(pin, 0); mdelay(50); gpio_direction_output(pin, 1); @@ -1339,11 +543,9 @@ void get_board_serial(struct tag_serialnr *serialnr) * Board Support */ -/* called from SPL board_init_f() */ int board_early_init_f(void) { setup_iomux_uart(); - gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */ #if defined(CONFIG_VIDEO_IPUV3) setup_display(); @@ -1374,15 +576,7 @@ int board_init(void) #ifdef CONFIG_MXC_SPI setup_spi(); #endif - if (is_cpu_type(MXC_CPU_MX6Q)) { - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); - } else { - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); - } + setup_ventana_i2c(); #ifdef CONFIG_CMD_SATA setup_sata(); @@ -1390,14 +584,7 @@ int board_init(void) /* read Gateworks EEPROM into global struct (used later) */ board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); - /* board-specifc GPIO iomux */ - SETUP_IOMUX_PADS(gw_gpio_pads); - if (board_type < GW_UNKNOWN) { - iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads; - int count = gpio_cfg[board_type].num_pads; - - imx_iomux_v3_setup_multiple_pads(p, count); - } + setup_iomux_gpio(board_type, &ventana_info); return 0; } @@ -1472,7 +659,6 @@ static const struct boot_mode board_boot_modes[] = { int misc_init_r(void) { struct ventana_board_info *info = &ventana_info; - unsigned char reg; /* set env vars based on EEPROM data */ if (ventana_info.model[0]) { @@ -1546,34 +732,15 @@ int misc_init_r(void) } - /* setup baseboard specific GPIO pinmux and config */ - setup_board_gpio(board_type); + /* setup baseboard specific GPIO based on board and env */ + setup_board_gpio(board_type, info); #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif - /* - * The Gateworks System Controller implements a boot - * watchdog (always enabled) as a workaround for IMX6 boot related - * errata such as: - * ERR005768 - no fix scheduled - * ERR006282 - fixed in silicon r1.2 - * ERR007117 - fixed in silicon r1.3 - * ERR007220 - fixed in silicon r1.3 - * ERR007926 - no fix scheduled - * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf - * - * Disable the boot watchdog and display/clear the timeout flag if set - */ - i2c_set_bus_num(CONFIG_I2C_GSC); - if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) { - reg |= (1 << GSC_SC_CTRL1_WDDIS); - if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) - puts("Error: could not disable GSC Watchdog\n"); - } else { - puts("Error: could not disable GSC Watchdog\n"); - } + /* disable boot watchdog */ + gsc_boot_wd_disable(); return 0; } @@ -1783,3 +950,11 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ +static struct mxc_serial_platdata ventana_mxc_serial_plat = { + .reg = (struct mxc_uart *)UART2_BASE, +}; + +U_BOOT_DEVICE(ventana_serial) = { + .name = "serial_mxc", + .platdata = &ventana_mxc_serial_plat, +}; diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 0c0fee3..79cb594 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -6,10 +6,8 @@ */ #include <common.h> -#include <i2c.h> #include <asm/io.h> #include <asm/arch/crm_regs.h> -#include <asm/arch/iomux.h> #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/sys_proto.h> @@ -18,54 +16,14 @@ #include <asm/imx-common/mxc_i2c.h> #include <spl.h> -#include "ventana_eeprom.h" +#include "gsc.h" +#include "common.h" DECLARE_GLOBAL_DATA_PTR; #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ -#define I2C_GSC 0 -#define GSC_EEPROM_ADDR 0x51 #define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */ #define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */ -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -#define CONFIG_SYS_I2C_SPEED 100000 - -/* I2C1: GSC */ -static struct i2c_pads_info mx6q_i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, - .gp = IMX_GPIO_NR(3, 28) - } -}; -static struct i2c_pads_info mx6dl_i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, - .gp = IMX_GPIO_NR(3, 28) - } -}; - -static void i2c_setup_iomux(void) -{ - if (is_cpu_type(MXC_CPU_MX6Q)) - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); - else - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); -} /* configure MX6Q/DUAL mmdc DDR io registers */ struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { @@ -530,15 +488,18 @@ void board_init_f(ulong dummy) struct ventana_board_info ventana_info; int board_model; + /* setup clock gating */ + ccgr_init(); + /* setup AIPS and disable watchdog */ arch_cpu_init(); - ccgr_init(); + /* setup AXI */ gpr_init(); /* iomux and setup of i2c */ - board_early_init_f(); - i2c_setup_iomux(); + setup_iomux_uart(); + setup_ventana_i2c(); /* setup GP timer */ timer_init(); @@ -547,7 +508,10 @@ void board_init_f(ulong dummy) preloader_console_init(); /* read/validate EEPROM info to determine board model and SDRAM cfg */ - board_model = read_eeprom(I2C_GSC, &ventana_info); + board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info); + + /* configure model-specific gpio */ + setup_iomux_gpio(board_model, &ventana_info); /* provide some some default: 32bit 128MB */ if (GW_UNKNOWN == board_model) { @@ -563,8 +527,30 @@ void board_init_f(ulong dummy) /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); - /* load/boot image from boot device */ - board_init_r(NULL, 0); + /* disable boot watchdog */ + gsc_boot_wd_disable(); +} + +/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */ +/* its our chance to print info about boot device */ +void spl_board_init(void) +{ + /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */ + u32 boot_device = spl_boot_device(); + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + puts("Booting from MMC\n"); + break; + case BOOT_DEVICE_NAND: + puts("Booting from NAND\n"); + break; + case BOOT_DEVICE_SATA: + puts("Booting from SATA\n"); + break; + default: + puts("Unknown boot device\n"); + } } void reset_cpu(ulong addr) diff --git a/board/google/Kconfig b/board/google/Kconfig index 302f68e..e9559c9 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -8,6 +8,7 @@ if VENDOR_GOOGLE choice prompt "Mainboard model" + optional config TARGET_CHROMEBOOK_LINK bool "Chromebook link" diff --git a/board/intel/Kconfig b/board/intel/Kconfig index 7fe21b9..3d9ecf0 100644 --- a/board/intel/Kconfig +++ b/board/intel/Kconfig @@ -8,6 +8,7 @@ if VENDOR_INTEL choice prompt "Mainboard model" + optional config TARGET_CROWNBAY bool "Crown Bay" diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig index 288a1ae..c518079 100644 --- a/board/micronas/vct/Kconfig +++ b/board/micronas/vct/Kconfig @@ -13,6 +13,7 @@ menu "vct board options" choice prompt "Board variant" + optional config VCT_PLATINUM bool "Enable VCT_PLATINUM" diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile deleted file mode 100644 index e3b2651..0000000 --- a/board/nvidia/common/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2011 The Chromium OS Authors. -# SPDX-License-Identifier: GPL-2.0+ - -include $(src)/common.mk diff --git a/board/nvidia/common/common.mk b/board/nvidia/common/common.mk deleted file mode 100644 index 9a9b529..0000000 --- a/board/nvidia/common/common.mk +++ /dev/null @@ -1,3 +0,0 @@ -# common options for all tegra boards -obj-y += ../../nvidia/common/board.o -obj-$(CONFIG_TEGRA_CLOCK_SCALING) += ../../nvidia/common/emc.o diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index d4d2496..ae8874b 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -6,8 +6,11 @@ */ #include <common.h> -#include <asm/arch/gpio.h> +#include <errno.h> +#include <asm/gpio.h> #include <asm/arch/pinmux.h> +#include <power/as3722.h> +#include <power/pmic.h> #include "pinmux-config-nyan-big.h" /* @@ -25,3 +28,32 @@ void pinmux_init(void) pinmux_config_drvgrp_table(nyan_big_drvgrps, ARRAY_SIZE(nyan_big_drvgrps)); } + +int tegra_board_id(void) +{ + static const int vector[] = {GPIO_PQ3, GPIO_PT1, GPIO_PX1, + GPIO_PX4, -1}; + + gpio_claim_vector(vector, "board_id%d"); + return gpio_get_values_as_int(vector); +} + +int tegra_lcd_pmic_init(int board_id) +{ + struct udevice *pmic; + int ret; + + ret = as3722_get(&pmic); + if (ret) + return -ENOENT; + + if (board_id == 0) + as3722_write(pmic, 0x00, 0x3c); + else + as3722_write(pmic, 0x00, 0x50); + as3722_write(pmic, 0x12, 0x10); + as3722_write(pmic, 0x0c, 0x07); + as3722_write(pmic, 0x20, 0x10); + + return 0; +} diff --git a/board/overo/Makefile b/board/overo/Makefile index 9109484..2189071 100644 --- a/board/overo/Makefile +++ b/board/overo/Makefile @@ -5,4 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := overo.o +ifdef CONFIG_SPL_BUILD +obj-y := spl.o common.o +else +obj-y := overo.o common.o +endif diff --git a/board/overo/common.c b/board/overo/common.c new file mode 100644 index 0000000..f6f6792 --- /dev/null +++ b/board/overo/common.c @@ -0,0 +1,341 @@ +/* + * Maintainer : Steve Sakoman <steve@sakoman.com> + * + * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * Sunil Kumar <sunilsaini05@gmail.com> + * Shashi Ranjan <shashiranjanmca05@gmail.com> + * + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <twl4030.h> +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define TWL4030_I2C_BUS 0 + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OVERO; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +#define MUX_OVERO() \ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\ + /* - MMC1_WP*/\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M0)) /*CAM_HS */\ + MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M0)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\ + /*Audio Interface */\ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ + /*Wireless LAN */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ + /*Bluetooth*/\ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\ + MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\ + MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\ + MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*McBSP1_CLKR*/\ + MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /*McBSP1_FSR*/\ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M0)) /*McBSP1_DX*/\ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*McBSP1_DR*/\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\ + /* BT_NRESET*/\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\ + /* - USBH_CPEN*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\ + /* - USBH_RESET*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA5*/\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA6*/\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA3*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\ + /* - W2W_NRESET*/\ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/\ + /* die to die */\ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ + +/* + * Routine: get_board_revision + * Description: Returns the board revision + */ +int get_board_revision(void) +{ + int revision; + + if (!gpio_request(112, "") && + !gpio_request(113, "") && + !gpio_request(115, "")) { + + gpio_direction_input(112); + gpio_direction_input(113); + gpio_direction_input(115); + + revision = gpio_get_value(115) << 2 | + gpio_get_value(113) << 1 | + gpio_get_value(112); + } else { + puts("Error: unable to acquire board revision GPIOs\n"); + revision = -1; + } + + return revision; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_OVERO(); +} diff --git a/board/overo/overo.c b/board/overo/overo.c index b7f85e7..34bf265 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -79,106 +79,6 @@ U_BOOT_DEVICE(overo_uart) = { }; /* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_OVERO; - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -/* - * Routine: get_board_revision - * Description: Returns the board revision - */ -int get_board_revision(void) -{ - int revision; - -#ifdef CONFIG_SYS_I2C_OMAP34XX - unsigned char data; - - /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */ - /* these boards should return a revision number of 0 */ - /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */ - i2c_set_bus_num(TWL4030_I2C_BUS); - data = 0x01; - i2c_write(0x4B, 0x29, 1, &data, 1); - data = 0x0c; - i2c_write(0x4B, 0x2b, 1, &data, 1); - i2c_read(0x4B, 0x2a, 1, &data, 1); -#endif - - if (!gpio_request(112, "") && - !gpio_request(113, "") && - !gpio_request(115, "")) { - - gpio_direction_input(112); - gpio_direction_input(113); - gpio_direction_input(115); - - revision = gpio_get_value(115) << 2 | - gpio_get_value(113) << 1 | - gpio_get_value(112); - } else { - puts("Error: unable to acquire board revision GPIOs\n"); - revision = -1; - } - - return revision; -} - -#ifdef CONFIG_SPL_BUILD -/* - * Routine: get_board_mem_timings - * Description: If we use SPL then there is no x-loader nor config header - * so we have to setup the DDR timings ourself on both banks. - */ -void get_board_mem_timings(struct board_sdrc_timings *timings) -{ - timings->mr = MICRON_V_MR_165; - switch (get_board_revision()) { - case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ - timings->mcfg = MICRON_V_MCFG_165(128 << 20); - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - break; - case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - case REVISION_4: - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - break; - case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - timings->mcfg = HYNIX_V_MCFG_200(256 << 20); - timings->ctrla = HYNIX_V_ACTIMA_200; - timings->ctrlb = HYNIX_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - break; - case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ - timings->mcfg = MCFG(512 << 20, 15); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - break; - default: - timings->mcfg = MICRON_V_MCFG_165(128 << 20); - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - } -} -#endif - -/* * Routine: get_sdio2_config * Description: Return information about the wifi module connection * Returns 0 if the module connects though a level translator @@ -287,6 +187,7 @@ int misc_init_r(void) expansion_config.revision, expansion_config.fab_revision); MUX_GUMSTIX(); + setenv("expansionname", "tobiduo"); break; case GUMSTIX_PALO35: printf("Recognized Palo35 expansion board (rev %d %s)\n", @@ -294,6 +195,7 @@ int misc_init_r(void) expansion_config.fab_revision); MUX_GUMSTIX(); setenv("defaultdisplay", "lcd35"); + setenv("expansionname", "palo35"); break; case GUMSTIX_PALO43: printf("Recognized Palo43 expansion board (rev %d %s)\n", @@ -359,6 +261,7 @@ int misc_init_r(void) MUX_GUMSTIX(); MUX_ARBOR43C(); setenv("defaultdisplay", "lcd43"); + setenv("expansionname", "arbor43c"); break; case ETTUS_USRP_E: printf("Recognized Ettus Research USRP-E (rev %d %s)\n", @@ -392,18 +295,7 @@ int misc_init_r(void) return 0; } -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_OVERO(); -} - -#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_NET) /* GPMC definitions for LAN9221 chips on Tobi expansion boards */ static const u32 gpmc_lan_config[] = { NET_LAN9221_GPMC_CONFIG1, @@ -486,7 +378,7 @@ int board_eth_init(bd_t *bis) } #endif -#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); @@ -500,7 +392,7 @@ void board_mmc_power_init(void) } #endif -#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_USB_EHCI) static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, diff --git a/board/overo/overo.h b/board/overo/overo.h index d0edf86..bbe16d5 100644 --- a/board/overo/overo.h +++ b/board/overo/overo.h @@ -17,6 +17,8 @@ const omap3_sysinfo sysinfo = { #endif }; +int get_board_revision(void); + /* overo revisions */ #define REVISION_0 0x0 #define REVISION_1 0x1 @@ -34,270 +36,6 @@ const omap3_sysinfo sysinfo = { * M0 - Mode 0 * The commented string gives the final mux configuration for that pin */ -#define MUX_OVERO() \ - /*SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - /*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\ - /* - MMC1_WP*/\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - /*CAMERA*/\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M0)) /*CAM_HS */\ - MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M0)) /*CAM_VS */\ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M0)) /*CAM_PCLK*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\ - /*Audio Interface */\ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ - /*Expansion card */\ - MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) /*MMC1_CLK*/\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ - /*Wireless LAN */\ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ - MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\ - MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ - /*Bluetooth*/\ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\ - MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\ - MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\ - MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\ - MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\ - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*McBSP1_CLKR*/\ - MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /*McBSP1_FSR*/\ - MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M0)) /*McBSP1_DX*/\ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*McBSP1_DR*/\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\ - /*Serial Interface*/\ - MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\ - /* BT_NRESET*/\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\ - /* - USBH_CPEN*/\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\ - /* - USBH_RESET*/\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA5*/\ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA6*/\ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA3*/\ - /*Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\ - /* - W2W_NRESET*/\ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/\ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/\ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/\ - /* die to die */\ - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ - #define MUX_GUMSTIX() \ /*GPMC*/\ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ diff --git a/board/overo/spl.c b/board/overo/spl.c new file mode 100644 index 0000000..5af780e --- /dev/null +++ b/board/overo/spl.c @@ -0,0 +1,60 @@ +/* + * Maintainer : Steve Sakoman <steve@sakoman.com> + * + * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * Sunil Kumar <sunilsaini05@gmail.com> + * Shashi Ranjan <shashiranjanmca05@gmail.com> + * + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include "overo.h" + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + timings->mr = MICRON_V_MR_165; + switch (get_board_revision()) { + case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ + timings->mcfg = MICRON_V_MCFG_165(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ + case REVISION_4: + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + break; + case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + break; + case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ + timings->mcfg = MCFG(512 << 20, 15); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + break; + default: + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } +} diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 9be2950..20dd75c 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -21,9 +21,9 @@ #include <asm/arch/pinmux.h> #include <asm/arch/power.h> #include <asm/arch/system.h> -#include <power/pmic.h> #include <asm/arch/sromc.h> #include <lcd.h> +#include <i2c.h> #include <samsung/misc.h> #include <usb.h> @@ -169,7 +169,7 @@ int board_early_init_f(void) } #endif -#if defined(CONFIG_POWER) +#if defined(CONFIG_POWER) || defined(CONFIG_DM_PMIC) int power_init_board(void) { set_ps_hold_ctrl(); diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 1a77c82..f0d69d4 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -16,6 +16,7 @@ #include <asm/arch/cpu.h> #include <asm/gpio.h> #include <linux/input.h> +#include <dm.h> #include <power/pmic.h> #include <mmc.h> diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index ae41c29..32155f1 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -12,7 +12,9 @@ #include <asm/arch/gpio.h> #include <asm/gpio.h> #include <asm/arch/cpu.h> +#include <dm.h> #include <power/pmic.h> +#include <power/regulator.h> #include <power/max77686_pmic.h> #include <errno.h> #include <mmc.h> @@ -31,6 +33,13 @@ enum { ODROID_TYPES, }; +static const char *mmc_regulators[] = { + "VDDQ_EMMC_1.8V", + "VDDQ_EMMC_2.8V", + "TFLASH_2.8V", + NULL, +}; + void set_board_type(void) { /* Set GPA1 pin 1 to HI - enable XCL205 output */ @@ -403,21 +412,6 @@ static void board_gpio_init(void) #endif } -static int pmic_init_max77686(void) -{ - struct pmic *p = pmic_get("MAX77686_PMIC"); - - if (pmic_probe(p)) - return -ENODEV; - - /* Set LDO Voltage */ - max77686_set_ldo_voltage(p, 20, 1800000); /* LDO20 eMMC */ - max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 SD */ - max77686_set_ldo_voltage(p, 22, 2800000); /* LDO22 eMMC */ - - return 0; -} - int exynos_early_init_f(void) { board_clock_init(); @@ -434,8 +428,8 @@ int exynos_init(void) int exynos_power_init(void) { - pmic_init(0); - pmic_init_max77686(); + if (regulator_list_autoset(mmc_regulators, NULL, true)) + error("Unable to init all mmc regulators"); return 0; } @@ -443,19 +437,20 @@ int exynos_power_init(void) #ifdef CONFIG_USB_GADGET static int s5pc210_phy_control(int on) { - struct pmic *p_pmic; + struct udevice *dev; + int ret; - p_pmic = pmic_get("MAX77686_PMIC"); - if (!p_pmic) - return -ENODEV; - - if (pmic_probe(p_pmic)) - return -1; + ret = regulator_get_by_platname("VDD_UOTG_3.0V", &dev); + if (ret) { + error("Regulator get error: %d", ret); + return ret; + } if (on) - return max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON); + return regulator_set_mode(dev, OPMODE_ON); else - return max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM); + return regulator_set_mode(dev, OPMODE_LPM); + } struct s3c_plat_otg_data s5pc210_otg_data = { @@ -472,7 +467,8 @@ struct s3c_plat_otg_data s5pc210_otg_data = { int board_usb_init(int index, enum usb_init_type init) { #ifdef CONFIG_CMD_USB - struct pmic *p_pmic; + struct udevice *dev; + int ret; /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/ /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */ @@ -490,14 +486,30 @@ int board_usb_init(int index, enum usb_init_type init) /* Power off and on BUCK8 for LAN9730 */ debug("LAN9730 - Turning power buck 8 OFF and ON.\n"); - p_pmic = pmic_get("MAX77686_PMIC"); - if (p_pmic && !pmic_probe(p_pmic)) { - max77686_set_buck_voltage(p_pmic, 8, 750000); - max77686_set_buck_voltage(p_pmic, 8, 3300000); + ret = regulator_get_by_platname("VCC_P3V3_2.85V", &dev); + if (ret) { + error("Regulator get error: %d", ret); + return ret; } -#endif + ret = regulator_set_enable(dev, true); + if (ret) { + error("Regulator %s enable setting error: %d", dev->name, ret); + return ret; + } + ret = regulator_set_value(dev, 750000); + if (ret) { + error("Regulator %s value setting error: %d", dev->name, ret); + return ret; + } + + ret = regulator_set_value(dev, 3300000); + if (ret) { + error("Regulator %s value setting error: %d", dev->name, ret); + return ret; + } +#endif debug("USB_udc_probe\n"); return s3c_udc_probe(&s5pc210_otg_data); } diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 2227f1c..80eaa63 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -7,6 +7,7 @@ #include <cros_ec.h> #include <dm.h> #include <os.h> +#include <asm/test.h> #include <asm/u-boot-sandbox.h> /* @@ -25,9 +26,17 @@ void flush_cache(unsigned long start, unsigned long size) { } +/* system timer offset in ms */ +static unsigned long sandbox_timer_offset; + +void sandbox_timer_add_offset(unsigned long offset) +{ + sandbox_timer_offset += offset; +} + unsigned long timer_read_counter(void) { - return os_get_nsec() / 1000; + return os_get_nsec() / 1000 + sandbox_timer_offset * 1000; } int dram_init(void) diff --git a/board/sc3/Kconfig b/board/sc3/Kconfig deleted file mode 100644 index 88a6d86..0000000 --- a/board/sc3/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_SC3 - -config SYS_BOARD - default "sc3" - -config SYS_CONFIG_NAME - default "sc3" - -endif diff --git a/board/sc3/MAINTAINERS b/board/sc3/MAINTAINERS deleted file mode 100644 index b86c6e6..0000000 --- a/board/sc3/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SC3 BOARD -M: Heiko Schocher <hs@denx.de> -S: Maintained -F: board/sc3/ -F: include/configs/sc3.h -F: configs/sc3_defconfig diff --git a/board/sc3/Makefile b/board/sc3/Makefile deleted file mode 100644 index c1d163e..0000000 --- a/board/sc3/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = sc3.o sc3nand.o -obj-y += init.o diff --git a/board/sc3/init.S b/board/sc3/init.S deleted file mode 100644 index 097aa4a..0000000 --- a/board/sc3/init.S +++ /dev/null @@ -1,360 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -#include <config.h> -#include <asm/ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -/** - * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals - * - * IMPORTANT: For pass1 this code must run from cache since you can not - * reliably change a peripheral banks timing register (pbxap) while running - * code from that bank. For ex., since we are running from ROM on bank 0, we - * can NOT execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * - * Bank 0 - Boot-Flash - * Bank 1 - NAND-Flash - * Bank 2 - ISA bus - * Bank 3 - Second Flash - * Bank 4 - USB controller - */ - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: -/* - * We need the current boot up configuration to set correct - * timings into internal flash and external flash - */ - mfdcr r24,CPC0_PSR /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx - 0 0 -> 8 bit external ROM - 0 1 -> 16 bit internal ROM */ - addi r4,0,2 - srw r24,r24,r4 /* shift right r24 two positions */ - andi. r24,r24,0x06000 -/* - * All calculations are based on 33MHz EBC clock. - * - * First, create a "very slow" timing (~250ns) with burst mode enabled - * This is need for the external flash access - */ - lis r25,0x0800 - /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */ - ori r25,r25,0x0280 -/* - * Second, create a fast timing: - * 90ns first cycle - 3 clock access - * and 90ns burst cycle, plus 1 clock after the last access - * This is used for the internal access - */ - lis r26,0x8900 - /* 1000 1001 0xxx 0000 0000 0010 100x xxxx */ - ori r26,r26,0x0280 -/* - * We can't change settings on CS# if we currently use them. - * -> load a few instructions into cache and run this code from cache - */ - mflr r4 /* save link register */ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 10; used to prefetch */ - mtctr r4 /* 10 cache lines to fit this function - in cache (gives us 8x10=80 instructions) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 10 cache lines */ -/* - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. 200usec should be enough. - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - */ - lis r3,0x0 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - -/*----------------------------------------------------------------------- - * Memory Bank 0 (BOOT-ROM) initialization - * 0xFFEF00000....0xFFFFFFF - * We only have to change the timing. Mapping is ok by boot-strapping - *----------------------------------------------------------------------- */ - - li r4,PB1AP /* PB0AP=Peripheral Bank 0 Access Parameters */ - mtdcr EBC0_CFGADDR,r4 - - mr r4,r26 /* assume internal fast flash is boot flash */ - cmpwi r24,0x2000 /* assumption true? ... */ - beq 1f /* ...yes! */ - mr r4,r25 /* ...no, use the slow variant */ - mr r25,r26 /* use this for the other flash */ -1: - mtdcr EBC0_CFGDATA,r4 /* change timing now */ - - li r4,PB0CR /* PB0CR=Peripheral Bank 0 Control Register */ - mtdcr EBC0_CFGADDR,r4 - mfdcr r4,EBC0_CFGDATA - lis r3,0x0001 - ori r3,r3,0x8000 /* allow reads and writes */ - or r4,r4,r3 - mtdcr EBC0_CFGDATA,r4 - -/*----------------------------------------------------------------------- - * Memory Bank 3 (Second-Flash) initialization - * 0xF0000000...0xF01FFFFF -> 2MB - *----------------------------------------------------------------------- */ - - li r4,PB3AP /* Peripheral Bank 1 Access Parameter */ - mtdcr EBC0_CFGADDR,r4 - mtdcr EBC0_CFGDATA,r2 /* change timing */ - - li r4,PB3CR /* Peripheral Bank 1 Configuration Registers */ - mtdcr EBC0_CFGADDR,r4 - - lis r4,0xF003 - ori r4,r4,0x8000 -/* - * Consider boot configuration - */ - xori r24,r24,0x2000 /* invert current bus width */ - or r4,r4,r24 - mtdcr EBC0_CFGDATA,r4 - -/*----------------------------------------------------------------------- - * Memory Bank 1 (NAND-Flash) initialization - * 0x77D00000...0x77DFFFFF -> 1MB - * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns - * - the setup time is 0ns - * - the hold time is 15ns - * -> - * - TWT = 0 - * - CSN = 0 - * - OEN = 0 - * - WBN = 0 - * - WBF = 0 - * - TH = 1 - * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold) - *----------------------------------------------------------------------- */ - - li r4,PB1AP /* Peripheral Bank 1 Access Parameter */ - mtdcr EBC0_CFGADDR,r4 - - lis r4,0x0000 - ori r4,r4,0x0200 - mtdcr EBC0_CFGDATA,r4 - - li r4,PB1CR /* Peripheral Bank 1 Configuration Registers */ - mtdcr EBC0_CFGADDR,r4 - - lis r4,0x77D1 - ori r4,r4,0x8000 - mtdcr EBC0_CFGDATA,r4 - - -/* USB init (without acceleration) */ -#ifndef CONFIG_ISP1161_PRESENT - li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */ - mtdcr EBC0_CFGADDR,r4 - lis r4,0x0180 - ori r4,r4,0x5940 - mtdcr EBC0_CFGDATA,r4 -#endif - -/*----------------------------------------------------------------------- - * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7) - * 0x78000000...0x7BFFFFFF -> 64 MB - * Wir arbeiten bei 33 MHz -> 30ns - *----------------------------------------------------------------------- - - A7 (ppc notation) or A24 (standard notation) decides about - the type of access: - A7/A24=0 -> memory cycle - A7/ /A24=1 -> I/O cycle -*/ - li r4,PB2AP /* PB2AP=Peripheral Bank 2 Access Parameters */ - mtdcr EBC0_CFGADDR,r4 -/* - We emulate an ISA access - - 1. Address active - 2. wait 0 EBC clocks -> CSN=0 - 3. set CS# - 4. wait 0 EBC clock -> OEN/WBN=0 - 5. set OE#/WE# - 6. wait 4 clocks (ca. 90ns) and for Ready signal - 7. hold for 4 clocks -> TH=4 -*/ - -#if 1 -/* faster access to isa-bus */ - lis r4,0x0180 - ori r4,r4,0x5940 -#else - lis r4,0x0100 - ori r4,r4,0x0340 -#endif - mtdcr EBC0_CFGDATA,r4 - -#ifdef IDE_USES_ISA_EMULATION - li r25,PB5AP /* PB5AP=Peripheral Bank 5 Access Parameters */ - mtdcr EBC0_CFGADDR,r25 - mtdcr EBC0_CFGDATA,r4 -#endif - - li r25,PB6AP /* PB6AP=Peripheral Bank 6 Access Parameters */ - mtdcr EBC0_CFGADDR,r25 - mtdcr EBC0_CFGDATA,r4 - li r25,PB7AP /* PB7AP=Peripheral Bank 7 Access Parameters */ - mtdcr EBC0_CFGADDR,r25 - mtdcr EBC0_CFGDATA,r4 - - li r25,PB2CR /* PB2CR=Peripheral Bank 2 Configuration Register */ - mtdcr EBC0_CFGADDR,r25 - - lis r4,0x780B - ori r4,r4,0xA000 - mtdcr EBC0_CFGDATA,r4 -/* - * the other areas are only 1MiB in size - */ - lis r4,0x7401 - ori r4,r4,0xA000 - - li r25,PB6CR /* PB6CR=Peripheral Bank 6 Configuration Register */ - mtdcr EBC0_CFGADDR,r25 - lis r4,0x7401 - ori r4,r4,0xA000 - mtdcr EBC0_CFGDATA,r4 - - li r25,PB7CR /* PB7CR=Peripheral Bank 7 Configuration Register */ - mtdcr EBC0_CFGADDR,r25 - lis r4,0x7411 - ori r4,r4,0xA000 - mtdcr EBC0_CFGDATA,r4 - -#ifndef CONFIG_ISP1161_PRESENT - li r25,PB4CR /* PB4CR=Peripheral Bank 4 Configuration Register */ - mtdcr EBC0_CFGADDR,r25 - lis r4,0x7421 - ori r4,r4,0xA000 - mtdcr EBC0_CFGDATA,r4 -#endif -#ifdef IDE_USES_ISA_EMULATION - li r25,PB5CR /* PB5CR=Peripheral Bank 5 Configuration Register */ - mtdcr EBC0_CFGADDR,r25 - lis r4,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 -#endif - -/*----------------------------------------------------------------------- - * Memory bank 4: USB controller Philips ISP6111 - * 0x77C00000 ... 0x77CFFFFF - * - * The chip is connected to: - * - CPU CS#4 - * - CPU IRQ#2 - * - CPU DMA 3 - * - * Timing: - * - command to first data: 300ns. Software must ensure this timing! - * - Write pulse: 26ns - * - Read pulse: 33ns - * - read cycle time: 150ns - * - write cycle time: 140ns - * - * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns - * - * |- 300ns --| - * |---- 420ns ---|---- 420ns ---| cycle - * CS ############:###____#######:###____####### - * OE ############:####___#######:####___####### - * WE ############:####__########:####__######## - * - * ----> 2 clocks RD/WR pulses: 60ns - * ----> CSN: 3 clock, 90ns - * ----> OEN: 1 clocks (read cycle) - * ----> WBN: 1 clocks (write cycle) - * ----> WBE: 2 clocks - * ----> TH: 7 clock, 210ns - * ----> TWT: 7 clocks - *----------------------------------------------------------------------- */ - -#ifdef CONFIG_ISP1161_PRESENT - - li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */ - mtdcr EBC0_CFGADDR,r4 - - lis r4,0x030D - ori r4,r4,0x5E80 - mtdcr EBC0_CFGDATA,r4 - - li r4,PB4CR /* PB2CR=Peripheral Bank 4 Configuration Register */ - mtdcr EBC0_CFGADDR,r4 - - lis r4,0x77C1 - ori r4,r4,0xA000 - mtdcr EBC0_CFGDATA,r4 - -#endif - -#ifndef IDE_USES_ISA_EMULATION - -/*----------------------------------------------------------------------- - * Memory Bank 5 used for IDE access - * - * Timings for IDE Interface - * - * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time - * 70 165 30 PIO-Mode 0, [ns] - * 3 6 1 [Cycles] ----> AP=0x040C0200 - * 50 125 20 PIO-Mode 1, [ns] - * 2 5 1 [Cycles] ----> AP=0x03080200 - * 30 100 15 PIO-Mode 2, [ns] - * 1 4 1 [Cycles] ----> AP=0x02040200 - * 30 80 10 PIO-Mode 3, [ns] - * 1 3 1 [Cycles] ----> AP=0x01840200 - * 25 70 10 PIO-Mode 4, [ns] - * 1 3 1 [Cycles] ----> AP=0x01840200 - * - *----------------------------------------------------------------------- */ - - li r4,PB5AP - mtdcr EBC0_CFGADDR,r4 - lis r4,0x040C - ori r4,r4,0x0200 - mtdcr EBC0_CFGDATA,r4 - - li r4,PB5CR /* PB2CR=Peripheral Bank 2 Configuration Register */ - mtdcr EBC0_CFGADDR,r4 - - lis r4,0x7A01 - ori r4,r4,0xA000 - mtdcr EBC0_CFGDATA,r4 -#endif -/* - * External Peripheral Control Register - */ - li r4,EBC0_CFG - mtdcr EBC0_CFGADDR,r4 - - lis r4,0xB84E - ori r4,r4,0xF000 - mtdcr EBC0_CFGDATA,r4 -/* - * drive POST code - */ - lis r4,0x7900 - ori r4,r4,0x0080 - li r3,0x0001 - stb r3,0(r4) /* 01 -> external bus controller is initialized */ - nop /* pass2 DCR errata #8 */ - blr diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c deleted file mode 100644 index 0216a37..0000000 --- a/board/sc3/sc3.c +++ /dev/null @@ -1,769 +0,0 @@ -/* - * (C) Copyright 2007 - * Heiko Schocher, DENX Software Engineering, <hs@denx.de>. - * - * (C) Copyright 2003 - * Juergen Beisert, EuroDesign embedded technologies, info@eurodsn.de - * Derived from walnut.c - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include "sc3.h" -#include <pci.h> -#include <i2c.h> -#include <malloc.h> -#include <netdev.h> - -#undef writel -#undef writeb -#define writeb(b,addr) ((*(volatile u8 *) (addr)) = (b)) -#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) - -/* write only register to configure things in our CPLD */ -#define CPLD_CONTROL_1 0x79000102 -#define CPLD_VERSION 0x79000103 - -#define IS_CAMERON ((*(unsigned char *)(CPLD_VERSION)== 0x32) ? 1 : 0) - -static struct pci_controller hose={0,}; - -/************************************************************ - * Standard definition - ************************************************************/ - -/* CPC0_CR0 Function ISA bus - - GPIO0 - - GPIO1 -> Output: NAND-Command Latch Enable - - GPIO2 -> Output: NAND Address Latch Enable - - GPIO3 -> IRQ input ISA-IRQ #5 (through CPLD) - - GPIO4 -> Output: NAND-Chip Enable - - GPIO5 -> IRQ input ISA-IRQ#7 (through CPLD) - - GPIO6 -> IRQ input ISA-IRQ#9 (through CPLD) - - GPIO7 -> IRQ input ISA-IRQ#10 (through CPLD) - - GPIO8 -> IRQ input ISA-IRQ#11 (through CPLD) - - GPIO9 -> IRQ input ISA-IRQ#12 (through CPLD) - - GPIO10/CS1# -> CS1# NAND ISA-CS#0 - - GPIO11/CS2# -> CS2# ISA emulation ISA-CS#1 - - GPIO12/CS3# -> CS3# 2nd Flash-Bank ISA-CS#2 or ISA-CS#7 - - GPIO13/CS4# -> CS4# USB HC or ISA emulation ISA-CS#3 - - GPIO14/CS5# -> CS5# Boosted IDE access ISA-CS#4 - - GPIO15/CS6# -> CS6# ISA emulation ISA-CS#5 - - GPIO16/CS7# -> CS7# ISA emulation ISA-CS#6 - - GPIO17/IRQ0 -> GPIO, in, NAND-Ready/Busy# line ISA-IRQ#3 - - GPIO18/IRQ1 -> IRQ input ISA-IRQ#14 - - GPIO19/IRQ2 -> IRQ input or USB ISA-IRQ#4 - - GPIO20/IRQ3 -> IRQ input PCI-IRQ#D - - GPIO21/IRQ4 -> IRQ input PCI-IRQ#C - - GPIO22/IRQ5 -> IRQ input PCI-IRQ#B - - GPIO23/IRQ6 -> IRQ input PCI-IRQ#A - - GPIO24 -> if GPIO output: 0=JTAG CPLD activ, 1=JTAG CPLD inactiv -*/ -/* -| CPLD register: io-space at offset 0x102 (write only) -| 0 -| 1 -| 2 0=CS#4 USB CS#, 1=ISA or GP bus -| 3 -| 4 -| 5 -| 6 1=enable faster IDE access -| 7 -*/ -#define USB_CHIP_ENABLE 0x04 -#define IDE_BOOSTING 0x40 - -/* --------------- USB stuff ------------------------------------- */ -#ifdef CONFIG_ISP1161_PRESENT -/** - * initUsbHost- Initialize the Philips isp1161 HC part if present - * @cpldConfig: Pointer to value in write only CPLD register - * - * Initialize the USB host controller if present and fills the - * scratch register to inform the driver about used resources - */ - -static void initUsbHost (unsigned char *cpldConfig) -{ - int i; - unsigned long usbBase; - /* - * Read back where init.S has located the USB chip - */ - mtdcr (0x012, 0x04); - usbBase = mfdcr (0x013); - if (!(usbBase & 0x18000)) /* enabled? */ - return; - usbBase &= 0xFFF00000; - - /* - * to test for the USB controller enable using of CS#4 and DMA 3 for USB access - */ - writeb (*cpldConfig | USB_CHIP_ENABLE,CPLD_CONTROL_1); - - /* - * first check: is the controller assembled? - */ - hcWriteWord (usbBase, 0x5555, HcScratch); - if (hcReadWord (usbBase, HcScratch) == 0x5555) { - hcWriteWord (usbBase, 0xAAAA, HcScratch); - if (hcReadWord (usbBase, HcScratch) == 0xAAAA) { - if ((hcReadWord (usbBase, HcChipID) & 0xFF00) != 0x6100) - return; /* this is not our controller */ - /* - * try a software reset. This needs up to 10 seconds (see datasheet) - */ - hcWriteDWord (usbBase, 0x00000001, HcCommandStatus); - for (i = 1000; i > 0; i--) { /* loop up to 10 seconds */ - udelay (10); - if (!(hcReadDWord (usbBase, HcCommandStatus) & 0x01)) - break; - } - - if (!i) - return; /* the controller doesn't responding. Broken? */ - /* - * OK. USB controller is ready. Initialize it in such way the later driver - * can us it (without any knowing about specific implementation) - */ - hcWriteDWord (usbBase, 0x00000000, HcControl); - /* - * disable all interrupt sources. Because we - * don't know where we come from (hard reset, cold start, soft reset...) - */ - hcWriteDWord (usbBase, 0x8000007D, HcInterruptDisable); - /* - * our current setup hardware configuration - * - every port power supply can switched indepently - * - every port can signal overcurrent - * - every port is "outside" and the devices are removeable - */ - hcWriteDWord (usbBase, 0x32000902, HcRhDescriptorA); - hcWriteDWord (usbBase, 0x00060000, HcRhDescriptorB); - /* - * don't forget to switch off power supply of each port - * The later running driver can reenable them to find and use - * the (maybe) connected devices. - * - */ - hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus1); - hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus2); - hcWriteWord (usbBase, 0x0428, HcHardwareConfiguration); - hcWriteWord (usbBase, 0x0040, HcDMAConfiguration); - hcWriteWord (usbBase, 0x0000, HcuPInterruptEnable); - hcWriteWord (usbBase, 0xA000 | (0x03 << 8) | 27, HcScratch); - /* - * controller is present and usable - */ - *cpldConfig |= USB_CHIP_ENABLE; - } - } -} -#endif - -#if defined(CONFIG_START_IDE) -int board_start_ide(void) -{ - if (IS_CAMERON) { - puts ("no IDE on cameron board.\n"); - return 0; - } - return 1; -} -#endif - -static int sc3_cameron_init (void) -{ - /* Set up the Memory Controller for the CAMERON version */ - mtebc (PB4AP, 0x01805940); - mtebc (PB4CR, 0x7401a000); - mtebc (PB5AP, 0x01805940); - mtebc (PB5CR, 0x7401a000); - mtebc (PB6AP, 0x0); - mtebc (PB6CR, 0x0); - mtebc (PB7AP, 0x0); - mtebc (PB7CR, 0x0); - return 0; -} - -void sc3_read_eeprom (void) -{ - uchar i2c_buffer[18]; - - i2c_read (0x50, 0x03, 1, i2c_buffer, 9); - i2c_buffer[9] = 0; - setenv ("serial#", (char *)i2c_buffer); - - /* read mac-address from eeprom */ - i2c_read (0x50, 0x11, 1, i2c_buffer, 15); - i2c_buffer[17] = 0; - i2c_buffer[16] = i2c_buffer[14]; - i2c_buffer[15] = i2c_buffer[13]; - i2c_buffer[14] = ':'; - i2c_buffer[13] = i2c_buffer[12]; - i2c_buffer[12] = i2c_buffer[11]; - i2c_buffer[11] = ':'; - i2c_buffer[8] = ':'; - i2c_buffer[5] = ':'; - i2c_buffer[2] = ':'; - setenv ("ethaddr", (char *)i2c_buffer); -} - -int board_early_init_f (void) -{ - /* write only register to configure things in our CPLD */ - unsigned char cpldConfig_1=0x00; - -/*-------------------------------------------------------------------------+ -| Interrupt controller setup for the SolidCard III CPU card (plus Evaluation board). -| -| Note: IRQ 0 UART 0, active high; level sensitive -| IRQ 1 UART 1, active high; level sensitive -| IRQ 2 IIC, active high; level sensitive -| IRQ 3 Ext. master, rising edge, edge sensitive -| IRQ 4 PCI, active high; level sensitive -| IRQ 5 DMA Channel 0, active high; level sensitive -| IRQ 6 DMA Channel 1, active high; level sensitive -| IRQ 7 DMA Channel 2, active high; level sensitive -| IRQ 8 DMA Channel 3, active high; level sensitive -| IRQ 9 Ethernet Wakeup, active high; level sensitive -| IRQ 10 MAL System Error (SERR), active high; level sensitive -| IRQ 11 MAL Tx End of Buffer, active high; level sensitive -| IRQ 12 MAL Rx End of Buffer, active high; level sensitive -| IRQ 13 MAL Tx Descriptor Error, active high; level sensitive -| IRQ 14 MAL Rx Descriptor Error, active high; level sensitive -| IRQ 15 Ethernet, active high; level sensitive -| IRQ 16 External PCI SERR, active high; level sensitive -| IRQ 17 ECC Correctable Error, active high; level sensitive -| IRQ 18 PCI Power Management, active high; level sensitive -| -| IRQ 19 (EXT IRQ7 405GPr only) -| IRQ 20 (EXT IRQ8 405GPr only) -| IRQ 21 (EXT IRQ9 405GPr only) -| IRQ 22 (EXT IRQ10 405GPr only) -| IRQ 23 (EXT IRQ11 405GPr only) -| IRQ 24 (EXT IRQ12 405GPr only) -| -| IRQ 25 (EXT IRQ 0) NAND-Flash R/B# (raising edge means flash is ready) -| IRQ 26 (EXT IRQ 1) IDE0 interrupt (x86 = IRQ14). Active high (edge sensitive) -| IRQ 27 (EXT IRQ 2) USB controller -| IRQ 28 (EXT IRQ 3) INT D, VGA; active low; level sensitive -| IRQ 29 (EXT IRQ 4) INT C, Ethernet; active low; level sensitive -| IRQ 30 (EXT IRQ 5) INT B, PC104+ SLOT; active low; level sensitive -| IRQ 31 (EXT IRQ 6) INT A, PC104+ SLOT; active low; level sensitive -| -| Direct Memory Access Controller Signal Polarities -| DRQ0 active high (like ISA) -| ACK0 active low (like ISA) -| EOT0 active high (like ISA) -| DRQ1 active high (like ISA) -| ACK1 active low (like ISA) -| EOT1 active high (like ISA) -| DRQ2 active high (like ISA) -| ACK2 active low (like ISA) -| EOT2 active high (like ISA) -| DRQ3 active high (like ISA) -| ACK3 active low (like ISA) -| EOT3 active high (like ISA) -| -+-------------------------------------------------------------------------*/ - - writeb (cpldConfig_1, CPLD_CONTROL_1); /* disable everything in CPLD */ - - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - - if (IS_CAMERON) { - sc3_cameron_init(); - mtdcr (0x0B6, 0x18000000); - mtdcr (UIC0PR, 0xFFFFFFF0); - mtdcr (UIC0TR, 0x10001030); - } else { - mtdcr (0x0B6, 0x0000000); - mtdcr (UIC0PR, 0xFFFFFFE0); - mtdcr (UIC0TR, 0x10000020); - } - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* setup other implementation specific details */ - mtdcr (CPC0_ECR, 0x60606000); - - mtdcr (CPC0_CR1, 0x000042C0); - - if (IS_CAMERON) { - mtdcr (CPC0_CR0, 0x01380000); - /* Setup the GPIOs */ - writel (0x08008000, 0xEF600700); /* Output states */ - writel (0x00000000, 0xEF600718); /* Open Drain control */ - writel (0x68098000, 0xEF600704); /* Output control */ - } else { - mtdcr (CPC0_CR0,0x00080000); - /* Setup the GPIOs */ - writel (0x08000000, 0xEF600700); /* Output states */ - writel (0x14000000, 0xEF600718); /* Open Drain control */ - writel (0x7C000000, 0xEF600704); /* Output control */ - } - - /* Code decompression disabled */ - mtdcr (DCP0_CFGADDR, KCONF); - mtdcr (DCP0_CFGDATA, 0x2B); - - /* CPC0_ER: enable sleep mode of (currently) unused components */ - /* CPC0_FR: force unused components into sleep mode */ - mtdcr (CPC0_ER, 0x3F800000); - mtdcr (CPC0_FR, 0x14000000); - - /* set PLB priority */ - mtdcr (PLB0_ACR, 0x08000000); - - /* --------------- DMA stuff ------------------------------------- */ - mtdcr (0x126, 0x49200000); - -#ifndef IDE_USES_ISA_EMULATION - cpldConfig_1 |= IDE_BOOSTING; /* enable faster IDE */ - /* cpldConfig |= 0x01; */ /* enable 8.33MHz output, if *not* present on your baseboard */ - writeb (cpldConfig_1, CPLD_CONTROL_1); -#endif - -#ifdef CONFIG_ISP1161_PRESENT - initUsbHost (&cpldConfig_1); - writeb (cpldConfig_1, CPLD_CONTROL_1); -#endif - /* FIXME: for what must we do this */ - *(unsigned long *)0x79000080 = 0x0001; - return(0); -} - -int misc_init_r (void) -{ - char *s1; - int i, xilinx_val; - volatile char *xilinx_adr; - xilinx_adr = (char *)0x79000102; - - *xilinx_adr = 0x00; - -/* customer settings ***************************************** */ -/* - s1 = getenv ("function"); - if (s1) { - if (!strcmp (s1, "Rosho")) { - printf ("function 'Rosho' activated\n"); - *xilinx_adr = 0x40; - } - else { - printf (">>>>>>>>>> function %s not recognized\n",s1); - } - } -*/ - -/* individual settings ***************************************** */ - if ((s1 = getenv ("xilinx"))) { - i=0; - xilinx_val = 0; - while (i < 3 && s1[i]) { - if (s1[i] >= '0' && s1[i] <= '9') - xilinx_val = (xilinx_val << 4) + s1[i] - '0'; - else - if (s1[i] >= 'A' && s1[i] <= 'F') - xilinx_val = (xilinx_val << 4) + s1[i] - 'A' + 10; - else - if (s1[i] >= 'a' && s1[i] <= 'f') - xilinx_val = (xilinx_val << 4) + s1[i] - 'a' + 10; - else { - xilinx_val = -1; - break; - } - i++; - } - if (xilinx_val >= 0 && xilinx_val <=255 && i < 3) { - printf ("Xilinx: set to %s\n", s1); - *xilinx_adr = (unsigned char) xilinx_val; - } else - printf ("Xilinx: rejected value %s\n", s1); - } - return 0; -} - -/* ------------------------------------------------------------------------- - * printCSConfig - * - * Print some informations about chips select configurations - * Only used while debugging. - * - * Params: - * - No. of CS pin - * - AP of this CS - * - CR of this CS - * - * Returns - * nothing - ------------------------------------------------------------------------- */ - -#ifdef SC3_DEBUGOUT -static void printCSConfig(int reg,unsigned long ap,unsigned long cr) -{ - const char *bsize[4] = {"8","16","32","?"}; - const unsigned char banks[8] = {1, 2, 4, 8, 16, 32, 64, 128}; - const char *bankaccess[4] = {"disabled", "RO", "WO", "RW"}; - -#define CYCLE 30 /* time of one clock (based on 33MHz) */ - - printf("\nCS#%d",reg); - if (!(cr & 0x00018000)) - puts(" unused"); - else { - if (((cr&0xFFF00000U) & ((banks[(cr & 0x000E0000) >> 17]-1) << 20))) - puts(" Address is not multiple of bank size!"); - - printf("\n -%s bit device", - bsize[(cr & 0x00006000) >> 13]); - printf(" at 0x%08lX", cr & 0xFFF00000U); - printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]); - printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]); - if (ap & 0x80000000) { - printf("\n -Burst device (%luns/%luns)", - (((ap & 0x7C000000) >> 26) + 1) * CYCLE, - (((ap & 0x03800000) >> 23) + 1) * CYCLE); - } else { - printf("\n -Non burst device, active cycle %luns", - (((ap & 0x7F800000) >> 23) + 1) * CYCLE); - printf("\n -Address setup %luns", - ((ap & 0xC0000) >> 18) * CYCLE); - printf("\n -CS active to RD %luns/WR %luns", - ((ap & 0x30000) >> 16) * CYCLE, - ((ap & 0xC000) >> 14) * CYCLE); - printf("\n -WR to CS inactive %luns", - ((ap & 0x3000) >> 12) * CYCLE); - printf("\n -Hold after access %luns", - ((ap & 0xE00) >> 9) * CYCLE); - printf("\n -Ready is %sabled", - ap & 0x100 ? "en" : "dis"); - } - } -} -#endif - -#ifdef SC3_DEBUGOUT - -static unsigned int ap[] = {PB0AP, PB1AP, PB2AP, PB3AP, PB4AP, - PB5AP, PB6AP, PB7AP}; -static unsigned int cr[] = {PB0CR, PB1CR, PB2CR, PB3CR, PB4CR, - PB5CR, PB6CR, PB7CR}; - -static int show_reg (int nr) -{ - unsigned long ul1, ul2; - - mtdcr (EBC0_CFGADDR, ap[nr]); - ul1 = mfdcr (EBC0_CFGDATA); - mtdcr (EBC0_CFGADDR, cr[nr]); - ul2 = mfdcr(EBC0_CFGDATA); - printCSConfig(nr, ul1, ul2); - return 0; -} -#endif - -int checkboard (void) -{ -#ifdef SC3_DEBUGOUT - unsigned long ul1; - int i; - - for (i = 0; i < 8; i++) { - show_reg (i); - } - - mtdcr (EBC0_CFGADDR, EBC0_CFG); - ul1 = mfdcr (EBC0_CFGDATA); - - puts ("\nGeneral configuration:\n"); - - if (ul1 & 0x80000000) - printf(" -External Bus is always driven\n"); - - if (ul1 & 0x400000) - printf(" -CS signals are always driven\n"); - - if (ul1 & 0x20000) - printf(" -PowerDown after %lu clocks\n", - (ul1 & 0x1F000) >> 7); - - switch (ul1 & 0xC0000) - { - case 0xC0000: - printf(" -No external master present\n"); - break; - case 0x00000: - printf(" -8 bit external master present\n"); - break; - case 0x40000: - printf(" -16 bit external master present\n"); - break; - case 0x80000: - printf(" -32 bit external master present\n"); - break; - } - - switch (ul1 & 0x300000) - { - case 0x300000: - printf(" -Prefetch: Illegal setting!\n"); - break; - case 0x000000: - printf(" -1 doubleword prefetch\n"); - break; - case 0x100000: - printf(" -2 doublewords prefetch\n"); - break; - case 0x200000: - printf(" -4 doublewords prefetch\n"); - break; - } - putc ('\n'); -#endif - printf("Board: SolidCard III %s %s version.\n", - (IS_CAMERON ? "Cameron" : "Eurodesign"), CONFIG_SC3_VERSION); - return 0; -} - -static int printSDRAMConfig(char reg, unsigned long cr) -{ - const int bisize[8]={4, 8, 16, 32, 64, 128, 256, 0}; -#ifdef SC3_DEBUGOUT - const char *basize[8]= - {"4", "8", "16", "32", "64", "128", "256", "Reserved"}; - - printf("SDRAM bank %d",reg); - - if (!(cr & 0x01)) - puts(" disabled\n"); - else { - printf(" at 0x%08lX, size %s MB",cr & 0xFFC00000,basize[(cr&0xE0000)>>17]); - printf(" mode %lu\n",((cr & 0xE000)>>13)+1); - } -#endif - - if (cr & 0x01) - return(bisize[(cr & 0xE0000) >> 17]); - - return 0; -} - -#ifdef SC3_DEBUGOUT -static unsigned int mbcf[] = {SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR}; -#endif - -phys_size_t initdram (int board_type) -{ - unsigned int mems=0; - unsigned long ul1; - -#ifdef SC3_DEBUGOUT - unsigned long ul2; - int i; - - puts("\nSDRAM configuration:\n"); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - ul1 = mfdcr(SDRAM0_CFGDATA); - - if (!(ul1 & 0x80000000)) { - puts(" Controller disabled\n"); - return 0; - } - for (i = 0; i < 4; i++) { - mtdcr (SDRAM0_CFGADDR, mbcf[i]); - ul1 = mfdcr (SDRAM0_CFGDATA); - mems += printSDRAMConfig (i, ul1); - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); - ul1 = mfdcr(SDRAM0_CFGDATA); - - printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1); - printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1); - printf (" -R/W to Precharge %lu (CTP)\n", ((ul1 & 0x30000) >> 16) + 1); - printf (" -Leadoff %lu\n", ((ul1 & 0xC000) >> 14) + 1); - printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4); - printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1)); - puts ("Misc:\n"); - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - ul1 = mfdcr(SDRAM0_CFGDATA); - printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7); - - mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); - ul2=mfdcr(SDRAM0_CFGDATA); - - mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); - ul1=mfdcr(SDRAM0_CFGDATA); - - if (ul1 & 0x20000000) - printf(" -Power Down after: %luns\n", - ((ul2 & 0xFFC00000) >> 22) * 7); - else - puts(" -Power Down disabled\n"); - - if (ul1 & 0x40000000) - printf(" -Self refresh feature active\n"); - else - puts(" -Self refresh disabled\n"); - - if (ul1 & 0x10000000) - puts(" -ECC enabled\n"); - else - puts(" -ECC disabled\n"); - - if (ul1 & 0x8000000) - puts(" -Using registered SDRAM\n"); - - if (!(ul1 & 0x6000000)) - puts(" -Using 32 bit data width\n"); - else - puts(" -Illegal data width!\n"); - - if (ul1 & 0x400000) - puts(" -ECC drivers inactive\n"); - else - puts(" -ECC drivers active\n"); - - if (ul1 & 0x200000) - puts(" -Memory lines always active outputs\n"); - else - puts(" -Memory lines only at write cycles active outputs\n"); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_STATUS); - ul1 = mfdcr (SDRAM0_CFGDATA); - if (ul1 & 0x80000000) - puts(" -SDRAM Controller ready\n"); - else - puts(" -SDRAM Controller not ready\n"); - - if (ul1 & 0x4000000) - puts(" -SDRAM in self refresh mode!\n"); - - return (mems * 1024 * 1024); -#else - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - ul1 = mfdcr (SDRAM0_CFGDATA); - mems = printSDRAMConfig (0, ul1); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); - ul1 = mfdcr (SDRAM0_CFGDATA); - mems += printSDRAMConfig (1, ul1); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); - ul1 = mfdcr(SDRAM0_CFGDATA); - mems += printSDRAMConfig (2, ul1); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); - ul1 = mfdcr(SDRAM0_CFGDATA); - mems += printSDRAMConfig (3, ul1); - - return (mems * 1024 * 1024); -#endif -} - -static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ -/*-------------------------------------------------------------------------+ - | ,-. ,-. ,-. ,-. ,-. - | INTD# ----|B|-----|P|-. ,-|P|-. ,-| |-. ,-|G| - | |R| |C| \ / |C| \ / |E| \ / |r| - | INTC# ----|I|-----|1|-. `/---|1|-. `/---|t|-. `/---|a| - | |D| |0| \/ |0| \/ |h| \/ |f| - | INTB# ----|G|-----|4|-./`----|4|-./`----|e|-./`----|i| - | |E| |+| /\ |+| /\ |r| /\ |k| - | INTA# ----| |-----| |- `----| |- `----| |- `----| | - | `-' `-' `-' `-' `-' - | Slot 0 10 11 12 13 - | REQ# 0 1 2 * - | GNT# 0 1 2 * - +-------------------------------------------------------------------------*/ - unsigned char int_line = 0xff; - - switch (PCI_DEV(dev)) { - case 10: - int_line = 31; /* INT A */ - POST_OUT(0x42); - break; - - case 11: - int_line = 30; /* INT B */ - POST_OUT(0x43); - break; - - case 12: - int_line = 29; /* INT C */ - POST_OUT(0x44); - break; - - case 13: - int_line = 28; /* INT D */ - POST_OUT(0x45); - break; - } - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); -} - -extern void pci_405gp_init(struct pci_controller *hose); -extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev); -extern void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,struct pci_config_table *entry); -/* - * The following table is used when there is a special need to setup a PCI device. - * For every PCI device found in this table is called the given init function with given - * parameters. So never let all IDs at PCI_ANY_ID. In this case any found device gets the same - * parameters! - * -*/ -static struct pci_config_table pci_solidcard3_config_table[] = -{ -/* Host to PCI Bridge device (405GP) */ - { - vendor: 0x1014, - device: 0x0156, - class: PCI_CLASS_BRIDGE_HOST, - bus: 0, - dev: 0, - func: 0, - config_device: pci_405gp_setup_bridge - }, - { } -}; - -/*-------------------------------------------------------------------------+ - | pci_init_board (Called from pci_init() in drivers/pci/pci.c) - | - | Init the PCI part of the SolidCard III - | - | Params: - * - Pointer to current PCI hose - * - Current Device - * - * Returns - * nothing - +-------------------------------------------------------------------------*/ - -void pci_init_board(void) -{ - POST_OUT(0x41); -/* - * we want the ptrs to RAM not flash (ie don't use init list) - */ - hose.fixup_irq = pci_solidcard3_fixup_irq; - hose.config_table = pci_solidcard3_config_table; - pci_405gp_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/sc3/sc3.h b/board/sc3/sc3.h deleted file mode 100644 index 7178cd0..0000000 --- a/board/sc3/sc3.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/** - * hcWriteWord - write a 16 bit value into the USB controller - * @base: base address to access the chip registers - * @value: 16 bit value to write into register @offset - * @offset: register to write the @value into - * - */ -static void inline hcWriteWord (unsigned long base, unsigned int value, - unsigned int offset) -{ - out_le16 ((volatile u16*)(base + 2), offset | 0x80); - out_le16 ((volatile u16*)base, value); -} - -/** - * hcWriteDWord - write a 32 bit value into the USB controller - * @base: base address to access the chip registers - * @value: 32 bit value to write into register @offset - * @offset: register to write the @value into - * - */ - -static void inline hcWriteDWord (unsigned long base, unsigned long value, - unsigned int offset) -{ - out_le16 ((volatile u16*)(base + 2), offset | 0x80); - out_le16 ((volatile u16*)base, value); - out_le16 ((volatile u16*)base, value >> 16); -} - -/** - * hcReadWord - read a 16 bit value from the USB controller - * @base: base address to access the chip registers - * @offset: register to read from - * - * Returns the readed register value - */ - -static unsigned int inline hcReadWord (unsigned long base, unsigned int offset) -{ - out_le16 ((volatile u16*)(base + 2), offset); - return (in_le16 ((volatile u16*)base)); -} - -/** - * hcReadDWord - read a 32 bit value from the USB controller - * @base: base address to access the chip registers - * @offset: register to read from - * - * Returns the readed register value - */ - -static unsigned long inline hcReadDWord (unsigned long base, unsigned int offset) -{ - unsigned long val, val16; - - out_le16 ((volatile u16*)(base + 2), offset); - val = in_le16((volatile u16*)base); - val16 = in_le16((volatile u16*)base); - return (val | (val16 << 16)); -} - -/* control and status registers isp1161 */ -#define HcRevision 0x00 -#define HcControl 0x01 -#define HcCommandStatus 0x02 -#define HcInterruptStatus 0x03 -#define HcInterruptEnable 0x04 -#define HcInterruptDisable 0x05 -#define HcFmInterval 0x0D -#define HcFmRemaining 0x0E -#define HcFmNumber 0x0F -#define HcLSThreshold 0x11 -#define HcRhDescriptorA 0x12 -#define HcRhDescriptorB 0x13 -#define HcRhStatus 0x14 -#define HcRhPortStatus1 0x15 -#define HcRhPortStatus2 0x16 - -#define HcHardwareConfiguration 0x20 -#define HcDMAConfiguration 0x21 -#define HcTransferCounter 0x22 -#define HcuPInterrupt 0x24 -#define HcuPInterruptEnable 0x25 -#define HcChipID 0x27 -#define HcScratch 0x28 -#define HcSoftwareReset 0x29 -#define HcITLBufferLength 0x2A -#define HcATLBufferLength 0x2B -#define HcBufferStatus 0x2C -#define HcReadBackITL0Length 0x2D -#define HcReadBackITL1Length 0x2E -#define HcITLBufferPort 0x40 -#define HcATLBufferPort 0x41 diff --git a/board/sc3/sc3nand.c b/board/sc3/sc3nand.c deleted file mode 100644 index a26cd79..0000000 --- a/board/sc3/sc3nand.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2007 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#if defined(CONFIG_CMD_NAND) - -#include <nand.h> -#include <asm/processor.h> - -#define readb(addr) *(volatile u_char *)(addr) -#define readl(addr) *(volatile u_long *)(addr) -#define writeb(d,addr) *(volatile u_char *)(addr) = (d) - -#define SC3_NAND_ALE 29 /* GPIO PIN 3 */ -#define SC3_NAND_CLE 30 /* GPIO PIN 2 */ -#define SC3_NAND_CE 27 /* GPIO PIN 5 */ - -static void *sc3_io_base; -static void *sc3_control_base = (void *)0xEF600700; - -static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - set_bit (SC3_NAND_CLE, sc3_control_base); - else - clear_bit (SC3_NAND_CLE, sc3_control_base); - if ( ctrl & NAND_ALE ) - set_bit (SC3_NAND_ALE, sc3_control_base); - else - clear_bit (SC3_NAND_ALE, sc3_control_base); - if ( ctrl & NAND_NCE ) - set_bit (SC3_NAND_CE, sc3_control_base); - else - clear_bit (SC3_NAND_CE, sc3_control_base); - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static int sc3_nand_dev_ready(struct mtd_info *mtd) -{ - if (!(readl(sc3_control_base + 0x1C) & 0x4000)) - return 0; - return 1; -} - -static void sc3_select_chip(struct mtd_info *mtd, int chip) -{ - clear_bit (SC3_NAND_CE, sc3_control_base); -} - -int board_nand_init(struct nand_chip *nand) -{ - nand->ecc.mode = NAND_ECC_SOFT; - - sc3_io_base = (void *) CONFIG_SYS_NAND_BASE; - /* Set address of NAND IO lines (Using Linear Data Access Region) */ - nand->IO_ADDR_R = (void __iomem *) sc3_io_base; - nand->IO_ADDR_W = (void __iomem *) sc3_io_base; - /* Reference hardware control function */ - nand->cmd_ctrl = sc3_nand_hwcontrol; - nand->dev_ready = sc3_nand_dev_ready; - nand->select_chip = sc3_select_chip; - return 0; -} -#endif diff --git a/board/seco/Kconfig b/board/seco/Kconfig index dcb1ac8..af16697 100644 --- a/board/seco/Kconfig +++ b/board/seco/Kconfig @@ -2,6 +2,7 @@ if TARGET_SECOMX6 choice prompt "SECO i.MX6 Board variant" + optional config SECOMX6_Q7 bool "Q7" @@ -16,6 +17,7 @@ endchoice choice prompt "SECO i.MX6 SoC variant" + optional config SECOMX6Q bool "i.MX6Q" diff --git a/board/solidrun/hummingboard/Kconfig b/board/solidrun/hummingboard/Kconfig deleted file mode 100644 index 36b7904..0000000 --- a/board/solidrun/hummingboard/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_HUMMINGBOARD - -config SYS_BOARD - default "hummingboard" - -config SYS_VENDOR - default "solidrun" - -config SYS_SOC - default "mx6" - -config SYS_CONFIG_NAME - default "hummingboard" - -endif diff --git a/board/solidrun/hummingboard/MAINTAINERS b/board/solidrun/hummingboard/MAINTAINERS deleted file mode 100644 index c0c062a..0000000 --- a/board/solidrun/hummingboard/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -HUMMINGBOARD BOARD -M: Jon Nettleton <jon.nettleton@gmail.com> -S: Maintained -F: board/solidrun/hummingboard/ -F: include/configs/hummingboard.h -F: configs/hummingboard_solo_defconfig diff --git a/board/solidrun/hummingboard/Makefile b/board/solidrun/hummingboard/Makefile deleted file mode 100644 index 042a2f0..0000000 --- a/board/solidrun/hummingboard/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2013 Freescale Semiconductor, Inc. -# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> -# Copyright (C) 2013, Jon Nettleton <jon.nettleton@gmail.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := hummingboard.o diff --git a/board/solidrun/hummingboard/README b/board/solidrun/hummingboard/README deleted file mode 100644 index cfd62d4..0000000 --- a/board/solidrun/hummingboard/README +++ /dev/null @@ -1,40 +0,0 @@ -U-Boot for SolidRun Hummingboard --------------------------------- - -This file contains information for the port of U-Boot to the Hummingboard. - -For more details about Hummingboard, please refer to: -http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware - -(Carrier-One was the previous name of Hummingboard). - -Building U-boot for Hummingboard --------------------------------- - -To build U-Boot for the Hummingboard Solo version: - -$ make hummingboard_solo_config -$ make - -Flashing U-boot into the SD card --------------------------------- - -- After the 'make' command completes, the generated 'u-boot.imx' binary must be -flashed into the SD card: - -$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=1k seek=1; sync - -(Note - the SD card node may vary, so adjust this as needed). - -Also, a more detailed explanation on how to format the SD card is available -at doc/README.imximage. - -- Insert the micro SD card into the slot located in the bottom of the board - -- Connect a 3.3V USB to serial converter cable to the host PC. The MX6 UART -signals are available in the 26 pin connector as shown at: -http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware -(Check for "26 pin header layout"). - -- Power up the board via USB cable (CON201) and U-boot messages will appear in -the serial console. diff --git a/board/solidrun/hummingboard/hummingboard.c b/board/solidrun/hummingboard/hummingboard.c deleted file mode 100644 index 52c384b..0000000 --- a/board/solidrun/hummingboard/hummingboard.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>. - * - * Authors: Fabio Estevam <fabio.estevam@freescale.com> - Jon Nettleton <jon.nettleton@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/arch/clock.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/sys_proto.h> -#include <asm/errno.h> -#include <asm/gpio.h> -#include <asm/imx-common/iomux-v3.h> -#include <asm/io.h> -#include <mmc.h> -#include <fsl_esdhc.h> -#include <miiphy.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ - PAD_CTL_HYS) - -#define USDHC_PAD_GPIO_CTRL (PAD_CTL_PUS_22K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define ETH_PHY_RESET IMX_GPIO_NR(4, 15) - -int dram_init(void) -{ - gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024); - - return 0; -} - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(USDHC_PAD_GPIO_CTRL), -}; - -#ifdef CONFIG_FSL_ESDHC -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - { USDHC2_BASE_ADDR }, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; /* SD card is the boot medium, so always present */ -} - -int board_mmc_init(bd_t *bis) -{ - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} -#endif - -#ifdef CONFIG_FEC_MXC -static iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - /* AR8035 reset */ - MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), - /* AR8035 interrupt */ - MX6_PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* GPIO16 -> AR8035 25MHz */ - MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), -}; - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); - - gpio_direction_output(ETH_PHY_RESET, 0); - mdelay(2); - gpio_set_value(ETH_PHY_RESET, 1); -} - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - - int ret = enable_fec_anatop_clock(ENET_25MHZ); - if (ret) - return ret; - - /* set gpr1[ENET_CLK_SEL] */ - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); - - setup_iomux_enet(); - - return cpu_eth_init(bis); -} -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int checkboard(void) -{ - puts("Board: Hummingboard\n"); - - return 0; -} diff --git a/board/solidrun/hummingboard/solo.cfg b/board/solidrun/hummingboard/solo.cfg deleted file mode 100644 index 28dd750..0000000 --- a/board/solidrun/hummingboard/solo.cfg +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -#include "../mx6-microsom/ddr-800mhz-32bit-setup.cfg" -#include "../mx6-microsom/800mhz_2x128mx16.cfg" -#include "../mx6-microsom/clocks.cfg" diff --git a/board/solidrun/mx6cuboxi/README b/board/solidrun/mx6cuboxi/README index 3050c48..b417ff0 100644 --- a/board/solidrun/mx6cuboxi/README +++ b/board/solidrun/mx6cuboxi/README @@ -1,7 +1,7 @@ -How to use U-boot on Solid-run mx6 hummingboard ------------------------------------------------ +How to use U-boot on Solid-run mx6 Hummingboard and Cubox-i +----------------------------------------------------------- -- Build U-boot for hummingboard: +- Build U-boot for Hummingboard/Cubox-i: $ make mrproper $ make mx6cuboxi_defconfig @@ -17,5 +17,5 @@ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync -- Insert the SD card in the hummingboard, power it up and U-boot messages -should come up. +- Insert the SD card in the board, power it up and U-boot messages should +come up. diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index d3a32c1..d15c726 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -18,17 +18,22 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> #include <asm/arch/mx6-pins.h> +#include <asm/arch/mxc_hdmi.h> #include <asm/errno.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/video.h> #include <mmc.h> #include <fsl_esdhc.h> +#include <malloc.h> #include <miiphy.h> #include <netdev.h> #include <asm/arch/crm_regs.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <spl.h> +#include <usb.h> +#include <usb/ehci-fsl.h> DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +55,7 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) #define ETH_PHY_RESET IMX_GPIO_NR(4, 15) +#define USB_H1_VBUS IMX_GPIO_NR(1, 0) int dram_init(void) { @@ -77,6 +83,10 @@ static iomux_v3_cfg_t const hb_cbi_sense[] = { IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)), }; +static iomux_v3_cfg_t const usb_pads[] = { + IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + static void setup_iomux_uart(void) { SETUP_IOMUX_PADS(uart1_pads); @@ -124,6 +134,8 @@ static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), + IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), + IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), }; static void setup_iomux_enet(void) @@ -143,9 +155,14 @@ int board_phy_config(struct phy_device *phydev) return 0; } +/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */ +#define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4)) + int board_eth_init(bd_t *bis) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct mii_dev *bus; + struct phy_device *phydev; int ret = enable_fec_anatop_clock(ENET_25MHZ); if (ret) @@ -156,13 +173,150 @@ int board_eth_init(bd_t *bis) setup_iomux_enet(); - return cpu_eth_init(bis); + bus = fec_get_miibus(IMX_FEC_BASE, -1); + if (!bus) + return -EINVAL; + + phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + ret = -EINVAL; + goto free_bus; + } + + debug("using phy at address %d\n", phydev->addr); + ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev); + if (ret) + goto free_phydev; + + return 0; + +free_phydev: + free(phydev); +free_bus: + free(bus); + return ret; } +#ifdef CONFIG_VIDEO_IPUV3 +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +struct display_info_t const displays[] = { + { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + /* 1024x768@60Hz (VESA)*/ + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15384, + .left_margin = 160, + .right_margin = 24, + .upper_margin = 29, + .lower_margin = 3, + .hsync_len = 136, + .vsync_len = 6, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + } + } +}; + +size_t display_count = ARRAY_SIZE(displays); + +static int setup_display(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + int timeout = 100000; + + enable_ipu_clock(); + imx_setup_hdmi(); + + /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */ + setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); + + reg = readl(&ccm->analog_pll_video); + reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37); + reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1); + writel(reg, &ccm->analog_pll_video); + + writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); + + reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; + writel(reg, &ccm->analog_pll_video); + + while (timeout--) + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) + break; + if (timeout < 0) { + printf("Warning: video pll lock timeout!\n"); + return -ETIMEDOUT; + } + + reg = readl(&ccm->analog_pll_video); + reg |= BM_ANADIG_PLL_VIDEO_ENABLE; + reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; + writel(reg, &ccm->analog_pll_video); + + /* gate ipu1_di0_clk */ + clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); + + /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */ + reg = readl(&ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | + MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK | + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) | + (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) | + (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &ccm->chsccdr); + + /* enable ipu1_di0_clk */ + setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); + + return 0; +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +#ifdef CONFIG_USB_EHCI_MX6 +static void setup_usb(void) +{ + SETUP_IOMUX_PADS(usb_pads); +} + +int board_ehci_hcd_init(int port) +{ + if (port == 1) + gpio_direction_output(USB_H1_VBUS, 1); + + return 0; +} +#endif + int board_early_init_f(void) { + int ret = 0; setup_iomux_uart(); - return 0; + +#ifdef CONFIG_VIDEO_IPUV3 + ret = setup_display(); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + return ret; } int board_init(void) diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 2c4830f..2dd5d93 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -33,21 +33,21 @@ const struct stm32_gpio_ctl gpio_ctl_usart = { .otype = STM32_GPIO_OTYPE_PP, .speed = STM32_GPIO_SPEED_50M, .pupd = STM32_GPIO_PUPD_UP, - .af = STM32_GPIO_AF7 + .af = STM32_GPIO_USART }; -static const struct stm32_gpio_dsc usart1_gpio[] = { - {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */ - {STM32_GPIO_PORT_A, STM32_GPIO_PIN_10}, /* RX */ +static const struct stm32_gpio_dsc usart_gpio[] = { + {STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */ + {STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */ }; -int uart1_setup_gpio(void) +int uart_setup_gpio(void) { int i; int rv = 0; - for (i = 0; i < ARRAY_SIZE(usart1_gpio); i++) { - rv = stm32_gpio_config(&usart1_gpio[i], &gpio_ctl_usart); + for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { + rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); if (rv) goto out; } @@ -272,7 +272,7 @@ int board_early_init_f(void) { int res; - res = uart1_setup_gpio(); + res = uart_setup_gpio(); if (res) return res; diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c index 38f6e1d..09f973f 100644 --- a/board/st/stv0991/stv0991.c +++ b/board/st/stv0991/stv0991.c @@ -21,6 +21,7 @@ DECLARE_GLOBAL_DATA_PTR; struct gpio_regs *const gpioa_regs = (struct gpio_regs *) GPIOA_BASE_ADDR; +#ifndef CONFIG_OF_CONTROL static const struct pl01x_serial_platdata serial_platdata = { .base = 0x80406000, .type = TYPE_PL011, @@ -31,6 +32,7 @@ U_BOOT_DEVICE(stv09911_serials) = { .name = "serial_pl01x", .platdata = &serial_platdata, }; +#endif #ifdef CONFIG_SHOW_BOOT_PROGRESS void show_boot_progress(int progress) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index a60d028..5b6cc5c 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -18,6 +18,7 @@ config SUNXI_GEN_SUN6I choice prompt "Sunxi SoC Variant" + optional config MACH_SUN4I bool "sun4i (Allwinner A10)" @@ -555,4 +556,7 @@ config DM_ETH config DM_SERIAL default y +config DM_USB + default y if !USB_MUSB_SUNXI + endif diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c index 42b166d..0b509b6 100644 --- a/board/tbs/tbs2910/tbs2910.c +++ b/board/tbs/tbs2910/tbs2910.c @@ -372,6 +372,12 @@ static const struct boot_mode board_boot_modes[] = { }; #endif +#ifdef CONFIG_USB_EHCI_MX6 +static iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + int board_init(void) { /* address of boot parameters */ @@ -391,6 +397,10 @@ int board_init(void) #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif +#ifdef CONFIG_USB_EHCI_MX6 + imx_iomux_v3_setup_multiple_pads( + usb_otg_pads, ARRAY_SIZE(usb_otg_pads)); +#endif return 0; } diff --git a/board/toradex/apalis_t30/Makefile b/board/toradex/apalis_t30/Makefile index a968e6b..0ea3d8f 100644 --- a/board/toradex/apalis_t30/Makefile +++ b/board/toradex/apalis_t30/Makefile @@ -1,6 +1,4 @@ # Copyright (c) 2014 Marcel Ziswiler # SPDX-License-Identifier: GPL-2.0+ -include $(srctree)/board/nvidia/common/common.mk - obj-y += apalis_t30.o diff --git a/board/toradex/colibri_t20/Makefile b/board/toradex/colibri_t20/Makefile index 86f78d9..e5e71ac 100644 --- a/board/toradex/colibri_t20/Makefile +++ b/board/toradex/colibri_t20/Makefile @@ -4,6 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -include $(srctree)/board/nvidia/common/common.mk - obj-y += colibri_t20.o diff --git a/board/toradex/colibri_t30/Makefile b/board/toradex/colibri_t30/Makefile index 3d58a4b..4242902 100644 --- a/board/toradex/colibri_t30/Makefile +++ b/board/toradex/colibri_t30/Makefile @@ -1,6 +1,4 @@ # Copyright (c) 2013-2014 Stefan Agner # SPDX-License-Identifier: GPL-2.0+ -include $(srctree)/board/nvidia/common/common.mk - obj-y += colibri_t30.o diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c index c9e163e..29db838 100644 --- a/board/tqc/tqma6/tqma6.c +++ b/board/tqc/tqma6/tqma6.c @@ -145,7 +145,7 @@ static unsigned const tqma6_ecspi1_cs[] = { TQMA6_SF_CS_GPIO, }; -static void tqma6_iomuxc_spi(void) +__weak void tqma6_iomuxc_spi(void) { unsigned i; diff --git a/board/warp/README b/board/warp/README index 0e1f076..db3100e 100644 --- a/board/warp/README +++ b/board/warp/README @@ -43,8 +43,8 @@ Transfer u-boot.imx that will be flashed into the eMMC: $ sudo dfu-util -D u-boot.imx -a boot -Then on the U-boot prompt the following message should be seen after a succesful -upgrade: +Then on the U-boot prompt the following message should be seen after a +successful upgrade: #DOWNLOAD ... OK Ctrl+C to exit ... diff --git a/common/Kconfig b/common/Kconfig index 15759f7..5b8b0c3 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -460,4 +460,40 @@ config BOOTSTAGE_STASH_SIZE endmenu +menu "Power commands" +config CMD_PMIC + bool "Enable Driver Model PMIC command" + depends on DM_PMIC + help + This is the pmic command, based on a driver model pmic's API. + Command features are unchanged: + - list - list pmic devices + - pmic dev <id> - show or [set] operating pmic device (NEW) + - pmic dump - dump registers + - pmic read address - read byte of register at address + - pmic write address - write byte to register at address + The only one change for this command is 'dev' subcommand. + +config CMD_REGULATOR + bool "Enable Driver Model REGULATOR command" + depends on DM_REGULATOR + help + This command is based on driver model regulator's API. + User interface features: + - list - list regulator devices + - regulator dev <id> - show or [set] operating regulator device + - regulator info - print constraints info + - regulator status - print operating status + - regulator value <val] <-f> - print/[set] voltage value [uV] + - regulator current <val> - print/[set] current value [uA] + - regulator mode <id> - print/[set] operating mode id + - regulator enable - enable the regulator output + - regulator disable - disable the regulator output + + The '-f' (force) option can be used for set the value which exceeds + the limits, which are found in device-tree and are kept in regulator's + uclass platdata structure. + +endmenu + endmenu diff --git a/common/Makefile b/common/Makefile index 9084c73..d6c1d48 100644 --- a/common/Makefile +++ b/common/Makefile @@ -211,6 +211,10 @@ obj-$(CONFIG_UPDATE_TFTP) += update.o obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o obj-$(CONFIG_CMD_DFU) += cmd_dfu.o obj-$(CONFIG_CMD_GPT) += cmd_gpt.o + +# Power +obj-$(CONFIG_CMD_PMIC) += cmd_pmic.o +obj-$(CONFIG_CMD_REGULATOR) += cmd_regulator.o endif ifdef CONFIG_SPL_BUILD diff --git a/common/board_r.c b/common/board_r.c index 1a46f62..bf6c725 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -480,17 +480,6 @@ static int initr_malloc_bootparams(void) } #endif -#ifdef CONFIG_SC3 -/* TODO: with new initcalls, move this into the driver */ -extern void sc3_read_eeprom(void); - -static int initr_sc3_read_eeprom(void) -{ - sc3_read_eeprom(); - return 0; -} -#endif - static int initr_jumptable(void) { jumptable_init(); @@ -804,9 +793,6 @@ init_fnc_t init_sequence_r[] = { #endif INIT_FUNC_WATCHDOG_RESET initr_secondary_cpu, -#ifdef CONFIG_SC3 - initr_sc3_read_eeprom, -#endif #if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET) mac_read_from_eeprom, #endif diff --git a/common/cmd_date.c b/common/cmd_date.c index 4a653e5..61727e3 100644 --- a/common/cmd_date.c +++ b/common/cmd_date.c @@ -10,6 +10,7 @@ */ #include <common.h> #include <command.h> +#include <dm.h> #include <rtc.h> #include <i2c.h> @@ -33,10 +34,18 @@ static int do_date(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { struct rtc_time tm; int rcode = 0; - int old_bus; + int old_bus __maybe_unused; /* switch to correct I2C bus */ -#ifdef CONFIG_SYS_I2C +#ifdef CONFIG_DM_I2C + struct udevice *dev; + + rcode = uclass_get_device(UCLASS_RTC, 0, &dev); + if (rcode) { + printf("Cannot find RTC: err=%d\n", rcode); + return CMD_RET_FAILURE; + } +#elif defined(CONFIG_SYS_I2C) old_bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM); #else @@ -48,32 +57,50 @@ static int do_date(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) case 2: /* set date & time */ if (strcmp(argv[1],"reset") == 0) { puts ("Reset RTC...\n"); - rtc_reset (); +#ifdef CONFIG_DM_I2C + rcode = dm_rtc_reset(dev); + if (!rcode) + rcode = dm_rtc_set(dev, &default_tm); +#else + rtc_reset(); rcode = rtc_set(&default_tm); +#endif if (rcode) puts("## Failed to set date after RTC reset\n"); } else { /* initialize tm with current time */ - rcode = rtc_get (&tm); - - if(!rcode) { +#ifdef CONFIG_DM_I2C + rcode = dm_rtc_get(dev, &tm); +#else + rcode = rtc_get(&tm); +#endif + if (!rcode) { /* insert new date & time */ - if (mk_date (argv[1], &tm) != 0) { + if (mk_date(argv[1], &tm) != 0) { puts ("## Bad date format\n"); break; } /* and write to RTC */ - rcode = rtc_set (&tm); - if(rcode) - puts("## Set date failed\n"); +#ifdef CONFIG_DM_I2C + rcode = dm_rtc_set(dev, &tm); +#else + rcode = rtc_set(&tm); +#endif + if (rcode) { + printf("## Set date failed: err=%d\n", + rcode); + } } else { puts("## Get date failed\n"); } } /* FALL TROUGH */ case 1: /* get date & time */ - rcode = rtc_get (&tm); - +#ifdef CONFIG_DM_I2C + rcode = dm_rtc_get(dev, &tm); +#else + rcode = rtc_get(&tm); +#endif if (rcode) { puts("## Get date failed\n"); break; @@ -93,11 +120,11 @@ static int do_date(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* switch back to original I2C bus */ #ifdef CONFIG_SYS_I2C i2c_set_bus_num(old_bus); -#else +#elif !defined(CONFIG_DM_I2C) I2C_SET_BUS(old_bus); #endif - return rcode; + return rcode ? CMD_RET_FAILURE : 0; } /* @@ -201,7 +228,7 @@ int mk_date (const char *datestr, struct rtc_time *tmp) tmp->tm_min = val; /* calculate day of week */ - GregorianDay (tmp); + rtc_calc_weekday(tmp); return (0); default: diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index ad38cbf..1bc0db8 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -1623,6 +1623,27 @@ int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) } #endif /* CONFIG_I2C_EDID */ +#ifdef CONFIG_DM_I2C +static void show_bus(struct udevice *bus) +{ + struct udevice *dev; + + printf("Bus %d:\t%s", bus->req_seq, bus->name); + if (device_active(bus)) + printf(" (active %d)", bus->seq); + printf("\n"); + for (device_find_first_child(bus, &dev); + dev; + device_find_next_child(&dev)) { + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + + printf(" %02x: %s, offset len %x, flags %x\n", + chip->chip_addr, dev->name, chip->offset_len, + chip->flags); + } +} +#endif + /** * do_i2c_show_bus() - Handle the "i2c bus" command-line command * @cmdtp: Command data struct pointer @@ -1632,20 +1653,30 @@ int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) * * Returns zero always. */ -#if defined(CONFIG_SYS_I2C) +#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C) static int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - int i; -#ifndef CONFIG_SYS_I2C_DIRECT_BUS - int j; -#endif - if (argc == 1) { /* show all busses */ +#ifdef CONFIG_DM_I2C + struct udevice *bus; + struct uclass *uc; + int ret; + + ret = uclass_get(UCLASS_I2C, &uc); + if (ret) + return CMD_RET_FAILURE; + uclass_foreach_dev(bus, uc) + show_bus(bus); +#else + int i; + for (i = 0; i < CONFIG_SYS_NUM_I2C_BUSES; i++) { printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name); #ifndef CONFIG_SYS_I2C_DIRECT_BUS + int j; + for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) { if (i2c_bus[i].next_hop[j].chip == 0) break; @@ -1657,15 +1688,30 @@ static int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc, #endif printf("\n"); } +#endif } else { + int i; + /* show specific bus */ i = simple_strtoul(argv[1], NULL, 10); +#ifdef CONFIG_DM_I2C + struct udevice *bus; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i, &bus); + if (ret) { + printf("Invalid bus %d: err=%d\n", i, ret); + return CMD_RET_FAILURE; + } + show_bus(bus); +#else if (i >= CONFIG_SYS_NUM_I2C_BUSES) { printf("Invalid bus %d\n", i); return -1; } printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name); #ifndef CONFIG_SYS_I2C_DIRECT_BUS + int j; for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) { if (i2c_bus[i].next_hop[j].chip == 0) break; @@ -1676,6 +1722,7 @@ static int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc, } #endif printf("\n"); +#endif } return 0; @@ -1835,7 +1882,7 @@ static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv } static cmd_tbl_t cmd_i2c_sub[] = { -#if defined(CONFIG_SYS_I2C) +#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C) U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""), #endif U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""), @@ -1902,7 +1949,7 @@ static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) /***************************************************/ #ifdef CONFIG_SYS_LONGHELP static char i2c_help_text[] = -#if defined(CONFIG_SYS_I2C) +#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C) "bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n" #endif "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n" diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 5d8c9e6..2e85d53 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -1227,7 +1227,7 @@ static int do_mem_crc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ac = argc - 1; #ifdef CONFIG_HASH_VERIFY if (strcmp(*av, "-v") == 0) { - flags |= HASH_FLAG_VERIFY; + flags |= HASH_FLAG_VERIFY | HASH_FLAG_ENV; av++; ac--; } @@ -1303,7 +1303,7 @@ U_BOOT_CMD( #ifdef CONFIG_CMD_CRC32 -#ifndef CONFIG_CRC32_VERIFY +#ifndef CONFIG_HASH_VERIFY U_BOOT_CMD( crc32, 4, 1, do_mem_crc, @@ -1311,7 +1311,7 @@ U_BOOT_CMD( "address count [addr]\n - compute CRC32 checksum [save at addr]" ); -#else /* CONFIG_CRC32_VERIFY */ +#else /* CONFIG_HASH_VERIFY */ U_BOOT_CMD( crc32, 5, 1, do_mem_crc, @@ -1320,7 +1320,7 @@ U_BOOT_CMD( "-v address count crc\n - verify crc of memory area" ); -#endif /* CONFIG_CRC32_VERIFY */ +#endif /* CONFIG_HASH_VERIFY */ #endif diff --git a/common/cmd_part.c b/common/cmd_part.c index d04588e..8483c12 100644 --- a/common/cmd_part.c +++ b/common/cmd_part.c @@ -128,7 +128,7 @@ static int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( part, CONFIG_SYS_MAXARGS, 1, do_part, "disk partition related commands", - "part uuid <interface> <dev>:<part>\n" + "uuid <interface> <dev>:<part>\n" " - print partition UUID\n" "part uuid <interface> <dev>:<part> <varname>\n" " - set environment variable to partition UUID\n" diff --git a/common/cmd_pmic.c b/common/cmd_pmic.c new file mode 100644 index 0000000..970767c --- /dev/null +++ b/common/cmd_pmic.c @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2014-2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <errno.h> +#include <dm.h> +#include <dm/uclass-internal.h> +#include <power/pmic.h> + +#define LIMIT_DEV 32 +#define LIMIT_PARENT 20 + +static struct udevice *currdev; + +static int failure(int ret) +{ + printf("Error: %d (%s)\n", ret, errno_str(ret)); + + return CMD_RET_FAILURE; +} + +static int do_dev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *name; + int ret = -ENODEV; + + switch (argc) { + case 2: + name = argv[1]; + ret = pmic_get(name, &currdev); + if (ret) { + printf("Can't get PMIC: %s!\n", name); + return failure(ret); + } + case 1: + if (!currdev) { + printf("PMIC device is not set!\n\n"); + return CMD_RET_USAGE; + } + + printf("dev: %d @ %s\n", currdev->seq, currdev->name); + } + + return CMD_RET_SUCCESS; +} + +static int do_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + int ret; + + printf("| %-*.*s| %-*.*s| %s @ %s\n", + LIMIT_DEV, LIMIT_DEV, "Name", + LIMIT_PARENT, LIMIT_PARENT, "Parent name", + "Parent uclass", "seq"); + + for (ret = uclass_first_device(UCLASS_PMIC, &dev); dev; + ret = uclass_next_device(&dev)) { + if (ret) + continue; + + printf("| %-*.*s| %-*.*s| %s @ %d\n", + LIMIT_DEV, LIMIT_DEV, dev->name, + LIMIT_PARENT, LIMIT_PARENT, dev->parent->name, + dev_get_uclass_name(dev->parent), dev->parent->seq); + } + + if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int do_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + uint8_t value; + uint reg; + int ret; + + if (!currdev) { + printf("First, set the PMIC device!\n"); + return CMD_RET_USAGE; + } + + dev = currdev; + + printf("Dump pmic: %s registers\n", dev->name); + + for (reg = 0; reg < pmic_reg_count(dev); reg++) { + ret = pmic_read(dev, reg, &value, 1); + if (ret) { + printf("Can't read register: %d\n", reg); + return failure(ret); + } + + if (!(reg % 16)) + printf("\n0x%02x: ", reg); + + printf("%2.2x ", value); + } + printf("\n"); + + return CMD_RET_SUCCESS; +} + +static int do_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + int regs, ret; + uint8_t value; + uint reg; + + if (!currdev) { + printf("First, set the PMIC device!\n"); + return CMD_RET_USAGE; + } + + dev = currdev; + + if (argc != 2) + return CMD_RET_USAGE; + + reg = simple_strtoul(argv[1], NULL, 0); + regs = pmic_reg_count(dev); + if (reg > regs) { + printf("PMIC max reg: %d\n", regs); + return failure(-EFAULT); + } + + ret = pmic_read(dev, reg, &value, 1); + if (ret) { + printf("Can't read PMIC register: %d!\n", reg); + return failure(ret); + } + + printf("0x%02x: 0x%2.2x\n", reg, value); + + return CMD_RET_SUCCESS; +} + +static int do_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + int regs, ret; + uint8_t value; + uint reg; + + if (!currdev) { + printf("First, set the PMIC device!\n"); + return CMD_RET_USAGE; + } + + dev = currdev; + + if (argc != 3) + return CMD_RET_USAGE; + + reg = simple_strtoul(argv[1], NULL, 0); + regs = pmic_reg_count(dev); + if (reg > regs) { + printf("PMIC max reg: %d\n", regs); + return failure(-EFAULT); + } + + value = simple_strtoul(argv[2], NULL, 0); + + ret = pmic_write(dev, reg, &value, 1); + if (ret) { + printf("Can't write PMIC register: %d!\n", reg); + return failure(ret); + } + + return CMD_RET_SUCCESS; +} + +static cmd_tbl_t subcmd[] = { + U_BOOT_CMD_MKENT(dev, 2, 1, do_dev, "", ""), + U_BOOT_CMD_MKENT(list, 1, 1, do_list, "", ""), + U_BOOT_CMD_MKENT(dump, 1, 1, do_dump, "", ""), + U_BOOT_CMD_MKENT(read, 2, 1, do_read, "", ""), + U_BOOT_CMD_MKENT(write, 3, 1, do_write, "", ""), +}; + +static int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + cmd_tbl_t *cmd; + + argc--; + argv++; + + cmd = find_cmd_tbl(argv[0], subcmd, ARRAY_SIZE(subcmd)); + if (cmd == NULL || argc > cmd->maxargs) + return CMD_RET_USAGE; + + return cmd->cmd(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD(pmic, CONFIG_SYS_MAXARGS, 1, do_pmic, + " operations", + "list - list pmic devices\n" + "pmic dev [name] - show or [set] operating PMIC device\n" + "pmic dump - dump registers\n" + "pmic read address - read byte of register at address\n" + "pmic write address - write byte to register at address\n" +); diff --git a/common/cmd_regulator.c b/common/cmd_regulator.c new file mode 100644 index 0000000..6149d1e --- /dev/null +++ b/common/cmd_regulator.c @@ -0,0 +1,408 @@ +/* + * Copyright (C) 2014-2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <errno.h> +#include <dm.h> +#include <dm/uclass-internal.h> +#include <power/regulator.h> + +#define LIMIT_DEVNAME 20 +#define LIMIT_OFNAME 32 +#define LIMIT_INFO 18 + +static struct udevice *currdev; + +static int failure(int ret) +{ + printf("Error: %d (%s)\n", ret, errno_str(ret)); + + return CMD_RET_FAILURE; +} + +static int do_dev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + const char *name; + int ret = -ENXIO; + + switch (argc) { + case 2: + name = argv[1]; + ret = regulator_get_by_platname(name, &currdev); + if (ret) { + printf("Can't get the regulator: %s!\n", name); + return failure(ret); + } + case 1: + if (!currdev) { + printf("Regulator device is not set!\n\n"); + return CMD_RET_USAGE; + } + + uc_pdata = dev_get_uclass_platdata(currdev); + if (!uc_pdata) { + printf("%s: no regulator platform data!\n", currdev->name); + return failure(ret); + } + + printf("dev: %s @ %s\n", uc_pdata->name, currdev->name); + } + + return CMD_RET_SUCCESS; +} + +static int curr_dev_and_platdata(struct udevice **devp, + struct dm_regulator_uclass_platdata **uc_pdata, + bool allow_type_fixed) +{ + *devp = NULL; + *uc_pdata = NULL; + + if (!currdev) { + printf("First, set the regulator device!\n"); + return CMD_RET_FAILURE; + } + + *devp = currdev; + + *uc_pdata = dev_get_uclass_platdata(*devp); + if (!*uc_pdata) { + error("Regulator: %s - missing platform data!", currdev->name); + return CMD_RET_FAILURE; + } + + if (!allow_type_fixed && (*uc_pdata)->type == REGULATOR_TYPE_FIXED) { + printf("Operation not allowed for fixed regulator!\n"); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +static int do_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + struct udevice *dev; + int ret; + + printf("| %-*.*s| %-*.*s| %s\n", + LIMIT_DEVNAME, LIMIT_DEVNAME, "Device", + LIMIT_OFNAME, LIMIT_OFNAME, "regulator-name", + "Parent"); + + for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; + ret = uclass_find_next_device(&dev)) { + if (ret) + continue; + + uc_pdata = dev_get_uclass_platdata(dev); + printf("| %-*.*s| %-*.*s| %s\n", + LIMIT_DEVNAME, LIMIT_DEVNAME, dev->name, + LIMIT_OFNAME, LIMIT_OFNAME, uc_pdata->name, + dev->parent->name); + } + + return ret; +} + +static int constraint(const char *name, int val, const char *val_name) +{ + printf("%-*s", LIMIT_INFO, name); + if (val < 0) { + printf(" %s (err: %d)\n", errno_str(val), val); + return val; + } + + if (val_name) + printf(" %d (%s)\n", val, val_name); + else + printf(" %d\n", val); + + return 0; +} + +static const char *get_mode_name(struct dm_regulator_mode *mode, + int mode_count, + int mode_id) +{ + while (mode_count--) { + if (mode->id == mode_id) + return mode->name; + mode++; + } + + return NULL; +} + +static int do_info(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + struct dm_regulator_uclass_platdata *uc_pdata; + struct dm_regulator_mode *modes; + const char *parent_uc; + int mode_count; + int ret; + int i; + + ret = curr_dev_and_platdata(&dev, &uc_pdata, true); + if (ret) + return ret; + + parent_uc = dev_get_uclass_name(dev->parent); + + printf("%s\n%-*s %s\n%-*s %s\n%-*s %s\n%-*s %s\n%-*s\n", + "Regulator info:", + LIMIT_INFO, "* regulator-name:", uc_pdata->name, + LIMIT_INFO, "* device name:", dev->name, + LIMIT_INFO, "* parent name:", dev->parent->name, + LIMIT_INFO, "* parent uclass:", parent_uc, + LIMIT_INFO, "* constraints:"); + + constraint(" - min uV:", uc_pdata->min_uV, NULL); + constraint(" - max uV:", uc_pdata->max_uV, NULL); + constraint(" - min uA:", uc_pdata->min_uA, NULL); + constraint(" - max uA:", uc_pdata->max_uA, NULL); + constraint(" - always on:", uc_pdata->always_on, + uc_pdata->always_on ? "true" : "false"); + constraint(" - boot on:", uc_pdata->boot_on, + uc_pdata->boot_on ? "true" : "false"); + + mode_count = regulator_mode(dev, &modes); + constraint("* op modes:", mode_count, NULL); + + for (i = 0; i < mode_count; i++, modes++) + constraint(" - mode id:", modes->id, modes->name); + + return CMD_RET_SUCCESS; +} + +static int do_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + int current, value, mode, ret; + const char *mode_name = NULL; + struct udevice *dev; + bool enabled; + + ret = curr_dev_and_platdata(&dev, &uc_pdata, true); + if (ret) + return ret; + + printf("Regulator %s status:\n", uc_pdata->name); + + enabled = regulator_get_enable(dev); + constraint(" * enable:", enabled, enabled ? "true" : "false"); + + value = regulator_get_value(dev); + constraint(" * value uV:", value, NULL); + + current = regulator_get_current(dev); + constraint(" * current uA:", current, NULL); + + mode = regulator_get_mode(dev); + mode_name = get_mode_name(uc_pdata->mode, uc_pdata->mode_count, mode); + constraint(" * mode id:", mode, mode_name); + + return CMD_RET_SUCCESS; +} + +static int do_value(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + struct dm_regulator_uclass_platdata *uc_pdata; + int value; + int force; + int ret; + + ret = curr_dev_and_platdata(&dev, &uc_pdata, argc == 1); + if (ret) + return ret; + + if (argc == 1) { + ret = regulator_get_value(dev); + if (ret < 0) { + printf("Regulator: %s - can't get the Voltage!\n", + uc_pdata->name); + return failure(ret); + } + + printf("%d uV\n", ret); + return CMD_RET_SUCCESS; + } + + if (argc == 3) + force = !strcmp("-f", argv[2]); + else + force = 0; + + value = simple_strtoul(argv[1], NULL, 0); + if ((value < uc_pdata->min_uV || value > uc_pdata->max_uV) && !force) { + printf("Value exceeds regulator constraint limits\n"); + return CMD_RET_FAILURE; + } + + ret = regulator_set_value(dev, value); + if (ret) { + printf("Regulator: %s - can't set the Voltage!\n", + uc_pdata->name); + return failure(ret); + } + + return CMD_RET_SUCCESS; +} + +static int do_current(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + struct dm_regulator_uclass_platdata *uc_pdata; + int current; + int ret; + + ret = curr_dev_and_platdata(&dev, &uc_pdata, argc == 1); + if (ret) + return ret; + + if (argc == 1) { + ret = regulator_get_current(dev); + if (ret < 0) { + printf("Regulator: %s - can't get the Current!\n", + uc_pdata->name); + return failure(ret); + } + + printf("%d uA\n", ret); + return CMD_RET_SUCCESS; + } + + current = simple_strtoul(argv[1], NULL, 0); + if (current < uc_pdata->min_uA || current > uc_pdata->max_uA) { + printf("Current exceeds regulator constraint limits\n"); + return CMD_RET_FAILURE; + } + + ret = regulator_set_current(dev, current); + if (ret) { + printf("Regulator: %s - can't set the Current!\n", + uc_pdata->name); + return failure(ret); + } + + return CMD_RET_SUCCESS; +} + +static int do_mode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + struct dm_regulator_uclass_platdata *uc_pdata; + int mode; + int ret; + + ret = curr_dev_and_platdata(&dev, &uc_pdata, false); + if (ret) + return ret; + + if (argc == 1) { + ret = regulator_get_mode(dev); + if (ret < 0) { + printf("Regulator: %s - can't get the operation mode!\n", + uc_pdata->name); + return failure(ret); + } + + printf("mode id: %d\n", ret); + return CMD_RET_SUCCESS; + } + + mode = simple_strtoul(argv[1], NULL, 0); + + ret = regulator_set_mode(dev, mode); + if (ret) { + printf("Regulator: %s - can't set the operation mode!\n", + uc_pdata->name); + return failure(ret); + } + + return CMD_RET_SUCCESS; +} + +static int do_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + struct dm_regulator_uclass_platdata *uc_pdata; + int ret; + + ret = curr_dev_and_platdata(&dev, &uc_pdata, true); + if (ret) + return ret; + + ret = regulator_set_enable(dev, true); + if (ret) { + printf("Regulator: %s - can't enable!\n", uc_pdata->name); + return failure(ret); + } + + return CMD_RET_SUCCESS; +} + +static int do_disable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + struct dm_regulator_uclass_platdata *uc_pdata; + int ret; + + ret = curr_dev_and_platdata(&dev, &uc_pdata, true); + if (ret) + return ret; + + ret = regulator_set_enable(dev, false); + if (ret) { + printf("Regulator: %s - can't disable!\n", uc_pdata->name); + return failure(ret); + } + + return CMD_RET_SUCCESS; +} + +static cmd_tbl_t subcmd[] = { + U_BOOT_CMD_MKENT(dev, 2, 1, do_dev, "", ""), + U_BOOT_CMD_MKENT(list, 1, 1, do_list, "", ""), + U_BOOT_CMD_MKENT(info, 2, 1, do_info, "", ""), + U_BOOT_CMD_MKENT(status, 2, 1, do_status, "", ""), + U_BOOT_CMD_MKENT(value, 3, 1, do_value, "", ""), + U_BOOT_CMD_MKENT(current, 3, 1, do_current, "", ""), + U_BOOT_CMD_MKENT(mode, 2, 1, do_mode, "", ""), + U_BOOT_CMD_MKENT(enable, 1, 1, do_enable, "", ""), + U_BOOT_CMD_MKENT(disable, 1, 1, do_disable, "", ""), +}; + +static int do_regulator(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + cmd_tbl_t *cmd; + + argc--; + argv++; + + cmd = find_cmd_tbl(argv[0], subcmd, ARRAY_SIZE(subcmd)); + if (cmd == NULL || argc > cmd->maxargs) + return CMD_RET_USAGE; + + return cmd->cmd(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD(regulator, CONFIG_SYS_MAXARGS, 1, do_regulator, + "uclass operations", + "list - list UCLASS regulator devices\n" + "regulator dev [regulator-name] - show/[set] operating regulator device\n" + "regulator info - print constraints info\n" + "regulator status - print operating status\n" + "regulator value [val] [-f] - print/[set] voltage value [uV] (force)\n" + "regulator current [val] - print/[set] current value [uA]\n" + "regulator mode [id] - print/[set] operating mode id\n" + "regulator enable - enable the regulator output\n" + "regulator disable - disable the regulator output\n" +); diff --git a/common/cmd_setexpr.c b/common/cmd_setexpr.c index 926339b..e7194fc 100644 --- a/common/cmd_setexpr.c +++ b/common/cmd_setexpr.c @@ -12,23 +12,37 @@ #include <common.h> #include <config.h> #include <command.h> +#include <mapmem.h> static ulong get_arg(char *s, int w) { - ulong *p; - /* - * if the parameter starts with a '*' then assume - * it is a pointer to the value we want + * If the parameter starts with a '*' then assume it is a pointer to + * the value we want. */ - if (s[0] == '*') { - p = (ulong *)simple_strtoul(&s[1], NULL, 16); + ulong *p; + ulong addr; + ulong val; + + addr = simple_strtoul(&s[1], NULL, 16); switch (w) { - case 1: return((ulong)(*(uchar *)p)); - case 2: return((ulong)(*(ushort *)p)); + case 1: + p = map_sysmem(addr, sizeof(uchar)); + val = (ulong)*(uchar *)p; + unmap_sysmem(p); + return val; + case 2: + p = map_sysmem(addr, sizeof(ushort)); + val = (ulong)*(ushort *)p; + unmap_sysmem(p); + return val; case 4: - default: return(*p); + default: + p = map_sysmem(addr, sizeof(ulong)); + val = *p; + unmap_sysmem(p); + return val; } } else { return simple_strtoul(s, NULL, 16); diff --git a/common/edid.c b/common/edid.c index df797fc..e08e420 100644 --- a/common/edid.c +++ b/common/edid.c @@ -13,6 +13,7 @@ #include <common.h> #include <edid.h> #include <errno.h> +#include <fdtdec.h> #include <linux/ctype.h> #include <linux/string.h> @@ -65,6 +66,110 @@ int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, return -1; } +/* Set all parts of a timing entry to the same value */ +static void set_entry(struct timing_entry *entry, u32 value) +{ + entry->min = value; + entry->typ = value; + entry->max = value; +} + +/** + * decode_timing() - Decoding an 18-byte detailed timing record + * + * @buf: Pointer to EDID detailed timing record + * @timing: Place to put timing + */ +static void decode_timing(u8 *buf, struct display_timing *timing) +{ + uint x_mm, y_mm; + unsigned int ha, hbl, hso, hspw, hborder; + unsigned int va, vbl, vso, vspw, vborder; + + /* Edid contains pixel clock in terms of 10KHz */ + set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); + x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); + y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); + ha = (buf[2] + ((buf[4] & 0xf0) << 4)); + hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); + hso = (buf[8] + ((buf[11] & 0xc0) << 2)); + hspw = (buf[9] + ((buf[11] & 0x30) << 4)); + hborder = buf[15]; + va = (buf[5] + ((buf[7] & 0xf0) << 4)); + vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); + vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); + vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); + vborder = buf[16]; + + set_entry(&timing->hactive, ha); + set_entry(&timing->hfront_porch, hso); + set_entry(&timing->hback_porch, hbl - hso - hspw); + set_entry(&timing->hsync_len, hspw); + + set_entry(&timing->vactive, va); + set_entry(&timing->vfront_porch, vso); + set_entry(&timing->vback_porch, vbl - vso - vspw); + set_entry(&timing->vsync_len, vspw); + + debug("Detailed mode clock %u Hz, %d mm x %d mm\n" + " %04x %04x %04x %04x hborder %x\n" + " %04x %04x %04x %04x vborder %x\n", + timing->pixelclock.typ, + x_mm, y_mm, + ha, ha + hso, ha + hso + hspw, + ha + hbl, hborder, + va, va + vso, va + vso + vspw, + va + vbl, vborder); +} + +int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, + int *panel_bits_per_colourp) +{ + struct edid1_info *edid = (struct edid1_info *)buf; + bool timing_done; + int i; + + if (buf_size < sizeof(*edid) || edid_check_info(edid)) { + debug("%s: Invalid buffer\n", __func__); + return -EINVAL; + } + + if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { + debug("%s: No preferred timing\n", __func__); + return -ENOENT; + } + + /* Look for detailed timing */ + timing_done = false; + for (i = 0; i < 4; i++) { + struct edid_monitor_descriptor *desc; + + desc = &edid->monitor_details.descriptor[i]; + if (desc->zero_flag_1 != 0) { + decode_timing((u8 *)desc, timing); + timing_done = true; + break; + } + } + if (!timing_done) + return -EINVAL; + + if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { + debug("%s: Not a digital display\n", __func__); + return -ENOSYS; + } + if (edid->version != 1 || edid->revision < 4) { + debug("%s: EDID version %d.%d does not have required info\n", + __func__, edid->version, edid->revision); + *panel_bits_per_colourp = -1; + } else { + *panel_bits_per_colourp = + ((edid->video_input_definition & 0x70) >> 3) + 4; + } + + return 0; +} + /** * Snip the tailing whitespace/return of a string. * diff --git a/common/fdt_support.c b/common/fdt_support.c index c5ed5ad..9e50148 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -1533,7 +1533,7 @@ int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width, if (ret < 0) return ret; - snprintf(name, sizeof(name), "framebuffer@%llx", base_address); + snprintf(name, sizeof(name), "framebuffer@%" PRIx64, base_address); ret = fdt_set_name(fdt, node, name); if (ret < 0) return ret; diff --git a/common/image-android.c b/common/image-android.c index 59079fc..d946c2f 100644 --- a/common/image-android.c +++ b/common/image-android.c @@ -10,8 +10,29 @@ #include <malloc.h> #include <errno.h> +#define ANDROID_IMAGE_DEFAULT_KERNEL_ADDR 0x10008000 + static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1]; +static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr) +{ + /* + * All the Android tools that generate a boot.img use this + * address as the default. + * + * Even though it doesn't really make a lot of sense, and it + * might be valid on some platforms, we treat that adress as + * the default value for this field, and try to execute the + * kernel in place in such a case. + * + * Otherwise, we will return the actual value set by the user. + */ + if (hdr->kernel_addr == ANDROID_IMAGE_DEFAULT_KERNEL_ADDR) + return (ulong)hdr + hdr->page_size; + + return hdr->kernel_addr; +} + /** * android_image_get_kernel() - processes kernel part of Android boot images * @hdr: Pointer to image header, which is at the start @@ -30,6 +51,8 @@ static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1]; int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, ulong *os_data, ulong *os_len) { + u32 kernel_addr = android_image_get_kernel_addr(hdr); + /* * Not all Android tools use the id field for signing the image with * sha1 (or anything) so we don't check it. It is not obvious that the @@ -41,7 +64,7 @@ int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, printf("Android's image name: %s\n", andr_tmp_str); printf("Kernel load addr 0x%08x size %u KiB\n", - hdr->kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024)); + kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024)); int len = 0; if (*hdr->cmdline) { @@ -101,7 +124,7 @@ ulong android_image_get_end(const struct andr_img_hdr *hdr) ulong android_image_get_kload(const struct andr_img_hdr *hdr) { - return hdr->kernel_addr; + return android_image_get_kernel_addr(hdr); } int android_image_get_ramdisk(const struct andr_img_hdr *hdr, diff --git a/common/image.c b/common/image.c index abc0d89..fdec496 100644 --- a/common/image.c +++ b/common/image.c @@ -533,7 +533,7 @@ void genimg_print_time(time_t timestamp) #ifndef USE_HOSTCC struct rtc_time tm; - to_tm(timestamp, &tm); + rtc_to_tm(timestamp, &tm); printf("%4d-%02d-%02d %2d:%02d:%02d UTC\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); diff --git a/common/spl/spl.c b/common/spl/spl.c index 690c9b0..aeb0645 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -328,7 +328,7 @@ ulong spl_relocate_stack_gd(void) ulong ptr; /* Get stack position: use 8-byte alignment for ABI compliance */ - ptr = CONFIG_SPL_STACK_R - sizeof(gd_t); + ptr = CONFIG_SPL_STACK_R_ADDR - sizeof(gd_t); ptr &= ~7; new_gd = (gd_t *)ptr; memcpy(new_gd, (void *)gd, sizeof(gd_t)); diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index e580f22..5d688d6 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -8,6 +8,7 @@ */ #include <common.h> #include <spl.h> +#include <linux/compiler.h> #include <asm/u-boot.h> #include <mmc.h> #include <image.h> @@ -21,7 +22,7 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector) struct image_header *header; header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - - sizeof(struct image_header)); + sizeof(struct image_header)); /* read image header to find the image size & load address */ err = mmc->block_dev.block_read(0, sector, 1, header); @@ -35,7 +36,7 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector) /* convert size to sectors - round up */ image_size_sectors = (spl_image.size + mmc->read_bl_len - 1) / - mmc->read_bl_len; + mmc->read_bl_len; /* Read the header too to avoid extra memcpy */ err = mmc->block_dev.block_read(0, sector, image_size_sectors, @@ -44,7 +45,7 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector) end: #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT if (err == 0) - printf("spl: mmc blk read err - %lu\n", err); + printf("spl: mmc block read error\n"); #endif return (err == 0); @@ -69,33 +70,38 @@ static int mmc_load_image_raw_partition(struct mmc *mmc, int partition) #ifdef CONFIG_SPL_OS_BOOT static int mmc_load_image_raw_os(struct mmc *mmc) { - if (!mmc->block_dev.block_read(0, - CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, - CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS, - (void *)CONFIG_SYS_SPL_ARGS_ADDR)) { + unsigned long err; + + err = mmc->block_dev.block_read(0, + CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, + CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS, + (void *)CONFIG_SYS_SPL_ARGS_ADDR); + if (err) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("mmc args blk read error\n"); + printf("spl: mmc block read error\n"); #endif return -1; } return mmc_load_image_raw_sector(mmc, - CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR); + CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR); } #endif void spl_mmc_load_image(void) { struct mmc *mmc; - int err; u32 boot_mode; + int err; + __maybe_unused int part; mmc_initialize(gd->bd); + /* We register only one device. So, the dev id is always 0 */ mmc = find_mmc_device(0); if (!mmc) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - puts("spl: mmc device not found!!\n"); + puts("spl: mmc device not found\n"); #endif hang(); } @@ -103,16 +109,22 @@ void spl_mmc_load_image(void) err = mmc_init(mmc); if (err) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: mmc init failed: err - %d\n", err); + printf("spl: mmc init failed with error: %d\n", err); #endif hang(); } boot_mode = spl_boot_mode(); - if (boot_mode == MMCSD_MODE_RAW) { - debug("boot mode - RAW\n"); + switch (boot_mode) { + case MMCSD_MODE_RAW: + debug("spl: mmc boot mode: raw\n"); + #ifdef CONFIG_SPL_OS_BOOT - if (spl_start_uboot() || mmc_load_image_raw_os(mmc)) + if (!spl_start_uboot()) { + err = mmc_load_image_raw_os(mmc); + if (!err) + return; + } #endif #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION err = mmc_load_image_raw_partition(mmc, @@ -121,76 +133,87 @@ void spl_mmc_load_image(void) err = mmc_load_image_raw_sector(mmc, CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); #endif + if (!err) + return; #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) - } - if (err || boot_mode == MMCSD_MODE_FS) { - debug("boot mode - FS\n"); + case MMCSD_MODE_FS: + debug("spl: mmc boot mode: fs\n"); + #ifdef CONFIG_SPL_FAT_SUPPORT #ifdef CONFIG_SPL_OS_BOOT - if (spl_start_uboot() || spl_load_image_fat_os(&mmc->block_dev, - CONFIG_SYS_MMCSD_FS_BOOT_PARTITION)) + if (!spl_start_uboot()) { + err = spl_load_image_fat_os(&mmc->block_dev, + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION); + if (!err) + return; + } #endif err = spl_load_image_fat(&mmc->block_dev, - CONFIG_SYS_MMCSD_FS_BOOT_PARTITION, - CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); - if(err) -#endif /* CONFIG_SPL_FAT_SUPPORT */ - { + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION, + CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); + if (!err) + return; +#endif #ifdef CONFIG_SPL_EXT_SUPPORT #ifdef CONFIG_SPL_OS_BOOT - if (spl_start_uboot() || spl_load_image_ext_os(&mmc->block_dev, - CONFIG_SYS_MMCSD_FS_BOOT_PARTITION)) + if (!spl_start_uboot()) { + err = spl_load_image_ext_os(&mmc->block_dev, + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION); + if (!err) + return; + } #endif err = spl_load_image_ext(&mmc->block_dev, - CONFIG_SYS_MMCSD_FS_BOOT_PARTITION, - CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); -#endif /* CONFIG_SPL_EXT_SUPPORT */ - } -#endif /* defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) */ + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION, + CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); + if (!err) + return; +#endif +#endif #ifdef CONFIG_SUPPORT_EMMC_BOOT - } else if (boot_mode == MMCSD_MODE_EMMCBOOT) { + case MMCSD_MODE_EMMCBOOT: /* * We need to check what the partition is configured to. * 1 and 2 match up to boot0 / boot1 and 7 is user data * which is the first physical partition (0). */ - int part = (mmc->part_config >> 3) & PART_ACCESS_MASK; + part = (mmc->part_config >> 3) & PART_ACCESS_MASK; if (part == 7) part = 0; if (mmc_switch_part(0, part)) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - puts("MMC partition switch failed\n"); + puts("spl: mmc partition switch failed\n"); #endif hang(); } + #ifdef CONFIG_SPL_OS_BOOT - if (spl_start_uboot() || mmc_load_image_raw_os(mmc)) + if (!spl_start_uboot()) { + err = mmc_load_image_raw_os(mmc); + if (!err) + return; + } #endif +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION + err = mmc_load_image_raw_partition(mmc, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION); +#else err = mmc_load_image_raw_sector(mmc, CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); #endif - } - - switch(boot_mode){ - case MMCSD_MODE_RAW: -#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) - case MMCSD_MODE_FS: -#endif -#ifdef CONFIG_SUPPORT_EMMC_BOOT - case MMCSD_MODE_EMMCBOOT: + if (!err) + return; #endif - /* Boot mode is ok. Nothing to do. */ - break; - case MMCSD_MODE_UNDEFINED: - default: + case MMCSD_MODE_UNDEFINED: + default: #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - puts("spl: wrong MMC boot mode\n"); + if (err) + puts("spl: mmc: no boot mode left to try\n"); + else + puts("spl: mmc: wrong boot mode\n"); #endif - hang(); - } - - if (err) hang(); + } } diff --git a/common/usb.c b/common/usb.c index a4820d3..6283f39 100644 --- a/common/usb.c +++ b/common/usb.c @@ -148,6 +148,32 @@ int usb_stop(void) return 0; } +/****************************************************************************** + * Detect if a USB device has been plugged or unplugged. + */ +int usb_detect_change(void) +{ + int i, j; + int change = 0; + + for (j = 0; j < USB_MAX_DEVICE; j++) { + for (i = 0; i < usb_dev[j].maxchild; i++) { + struct usb_port_status status; + + if (usb_get_port_status(&usb_dev[j], i + 1, + &status) < 0) + /* USB request failed */ + continue; + + if (le16_to_cpu(status.wPortChange) & + USB_PORT_STAT_C_CONNECTION) + change++; + } + } + + return change; +} + /* * disables the asynch behaviour of the control message. This is used for data * transfers that uses the exclusiv access to the control and bulk messages. @@ -192,6 +218,7 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, void *data, unsigned short size, int timeout) { ALLOC_CACHE_ALIGN_BUFFER(struct devrequest, setup_packet, 1); + int err; if ((timeout == 0) && (!asynch_allowed)) { /* request for a asynch control pipe is not allowed */ @@ -209,8 +236,9 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, request, requesttype, value, index, size); dev->status = USB_ST_NOT_PROC; /*not yet processed */ - if (submit_control_msg(dev, pipe, data, size, setup_packet) < 0) - return -EIO; + err = submit_control_msg(dev, pipe, data, size, setup_packet); + if (err < 0) + return err; if (timeout == 0) return (int)size; @@ -946,13 +974,18 @@ static int usb_setup_descriptor(struct usb_device *dev, bool do_read) * send 64-byte GET-DEVICE-DESCRIPTOR request. Since the descriptor is * only 18 bytes long, this will terminate with a short packet. But if * the maxpacket size is 8 or 16 the device may be waiting to transmit - * some more, or keeps on retransmitting the 8 byte header. */ + * some more, or keeps on retransmitting the 8 byte header. + */ - dev->descriptor.bMaxPacketSize0 = 64; /* Start off at 64 bytes */ - /* Default to 64 byte max packet size */ - dev->maxpacketsize = PACKET_SIZE_64; - dev->epmaxpacketin[0] = 64; - dev->epmaxpacketout[0] = 64; + if (dev->speed == USB_SPEED_LOW) { + dev->descriptor.bMaxPacketSize0 = 8; + dev->maxpacketsize = PACKET_SIZE_8; + } else { + dev->descriptor.bMaxPacketSize0 = 64; + dev->maxpacketsize = PACKET_SIZE_64; + } + dev->epmaxpacketin[0] = dev->descriptor.bMaxPacketSize0; + dev->epmaxpacketout[0] = dev->descriptor.bMaxPacketSize0; if (do_read) { int err; diff --git a/common/usb_hub.c b/common/usb_hub.c index c9be530..be01f4f 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -79,7 +79,7 @@ static int usb_get_hub_status(struct usb_device *dev, void *data) data, sizeof(struct usb_hub_status), USB_CNTL_TIMEOUT); } -static int usb_get_port_status(struct usb_device *dev, int port, void *data) +int usb_get_port_status(struct usb_device *dev, int port, void *data) { return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_PORT, 0, port, @@ -157,7 +157,7 @@ static inline char *portspeed(int portstatus) int legacy_hub_port_reset(struct usb_device *dev, int port, unsigned short *portstat) { - int tries; + int err, tries; ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1); unsigned short portstatus, portchange; @@ -168,8 +168,10 @@ int legacy_hub_port_reset(struct usb_device *dev, int port, debug("%s: resetting port %d...\n", __func__, port + 1); #endif for (tries = 0; tries < MAX_TRIES; tries++) { + err = usb_set_port_feature(dev, port + 1, USB_PORT_FEAT_RESET); + if (err < 0) + return err; - usb_set_port_feature(dev, port + 1, USB_PORT_FEAT_RESET); mdelay(200); if (usb_get_port_status(dev, port + 1, portsts) < 0) { @@ -269,7 +271,8 @@ int usb_hub_port_connect_change(struct usb_device *dev, int port) /* Reset the port */ ret = legacy_hub_port_reset(dev, port, &portstatus); if (ret < 0) { - printf("cannot reset port %i!?\n", port + 1); + if (ret != -ENXIO) + printf("cannot reset port %i!?\n", port + 1); return ret; } diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index 0713652..971e11a 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -1,10 +1,9 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=480 -CONFIG_DRAM_ZQ=123 CONFIG_DRAM_EMR1=4 CONFIG_SYS_CLK_FREQ=912000000 +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI" diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index e738923..d4953aa 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -1,13 +1,11 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro" -CONFIG_MMC_SUNXI_SLOT_EXTRA=1 -CONFIG_USB1_VBUS_PIN="PB10" -CONFIG_MMC0_CD_PIN="PG1" -CONFIG_MMC1_CD_PIN="PG13" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=4 +CONFIG_MMC0_CD_PIN="PG1" +CONFIG_MMC1_CD_PIN="PG13" +CONFIG_MMC_SUNXI_SLOT_EXTRA=1 +CONFIG_USB1_VBUS_PIN="PB10" +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI" diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index f558a6c..4bee362 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -1,18 +1,15 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro" +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PG11" -CONFIG_VIDEO_HDMI=n +# CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y -# For use with the Olimex 7" LCD module, adjust timings for other displays -# Set video-mode=sunxi:800x600-24@60,monitor=lcd in the env. to enable CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="PB10" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN5I=y -CONFIG_DRAM_CLK=408 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=0 +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI" diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 7b7b116..43d5fa1 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -1,19 +1,16 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino" +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PG11" -CONFIG_VIDEO_HDMI=n +CONFIG_AXP_GPIO=y +# CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y -# For use with the Olimex 7" LCD module, adjust timings for other displays -# Set video-mode=sunxi:800x600-24@60,monitor=lcd in the env. to enable CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_AXP_GPIO=y -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN5I=y -CONFIG_DRAM_CLK=408 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=0 +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI" diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index 59e7473..78eee6a 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -1,13 +1,11 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2" -CONFIG_MMC0_CD_PIN="PH1" -CONFIG_USB0_VBUS_PIN="PC17" -CONFIG_USB0_VBUS_DET="PH5" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=480 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_MMC0_CD_PIN="PH1" +CONFIG_USB0_VBUS_PIN="PC17" +CONFIG_USB0_VBUS_DET="PH5" +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index 2ba70f7..0b64d94 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -1,10 +1,8 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=480 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index 7d2e810..e61067d 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -1,14 +1,12 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro" -CONFIG_MMC_SUNXI_SLOT_EXTRA=3 -CONFIG_VIDEO_VGA=y -CONFIG_MMC0_CD_PIN="PH1" -CONFIG_MMC3_CD_PIN="PH11" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_MMC0_CD_PIN="PH1" +CONFIG_MMC3_CD_PIN="PH11" +CONFIG_MMC_SUNXI_SLOT_EXTRA=3 +CONFIG_VIDEO_VGA=y +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index ff41444..94c5443 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -1,13 +1,9 @@ -# The Ainol AW1 is an A20 based tablet with a 800x480 lcd screen, sdio wifi, -# volume up/down and home buttons, micro-sd slot, micro usb (otg), headphones -# connector and a SPCI modem connector. -# -# Also see: http://linux-sunxi.org/Ainol_AW1 -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1" +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN7I=y +CONFIG_DRAM_CLK=432 +CONFIG_DRAM_ZQ=123 CONFIG_MMC0_CD_PIN="PH1" -CONFIG_USB_MUSB_SUNXI=y CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y @@ -15,9 +11,7 @@ CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:40000,le:87,ri:112,up:38,lo CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=4 +CONFIG_USB_MUSB_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index 375cc68..63307b8 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -1,18 +1,16 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76" +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_CLK=432 CONFIG_MMC0_CD_PIN="PG0" -CONFIG_USB_MUSB_SUNXI=y CONFIG_USB0_VBUS_PIN="PG12" CONFIG_USB0_VBUS_DET="PG1" +CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_AXP_GPIO=y -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN5I=y -CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=4 +CONFIG_USB_MUSB_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" diff --git a/configs/Astar_MID756_defconfig b/configs/Astar_MID756_defconfig index 0072ab8..b779f88 100644 --- a/configs/Astar_MID756_defconfig +++ b/configs/Astar_MID756_defconfig @@ -1,11 +1,8 @@ -# The Astar MID756 is a 7" tablet using the A33 SoC with a 800x480 LCD screen, -# 512M RAM, 8G ROM and integrated sdio wifi. -# -# Also see: http://linux-sunxi.org/Softwinner_astar-rda -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" -CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-astar-mid756" -CONFIG_USB_MUSB_SUNXI=y +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A33=y +CONFIG_DRAM_CLK=480 +CONFIG_DRAM_ZQ=15291 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y @@ -14,13 +11,9 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN8I_A33=y -CONFIG_DRAM_CLK=480 -# zq = 0x3bbb -CONFIG_DRAM_ZQ=15291 -# Wifi power +CONFIG_USB_MUSB_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-astar-mid756" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" CONFIG_AXP221_DLDO1_VOLT=3300 -# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP CONFIG_AXP221_ALDO1_VOLT=3000 diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index f3f42e4..6e320bd 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -1,10 +1,8 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004" -CONFIG_USB1_VBUS_PIN="PG13" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=4 +CONFIG_USB1_VBUS_PIN="PG13" +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI" diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig index b9467bb..a043659 100644 --- a/configs/B4420QDS_NAND_defconfig +++ b/configs/B4420QDS_NAND_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND" diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig index d62a068..29afd8a 100644 --- a/configs/B4420QDS_SPIFLASH_defconfig +++ b/configs/B4420QDS_SPIFLASH_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig index dc77f70..dc563a7 100644 --- a/configs/B4420QDS_defconfig +++ b/configs/B4420QDS_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420" diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig index c5e4d37..9e7462d 100644 --- a/configs/B4860QDS_NAND_defconfig +++ b/configs/B4860QDS_NAND_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND" diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig index f73a2ae..c2e9acc 100644 --- a/configs/B4860QDS_SECURE_BOOT_defconfig +++ b/configs/B4860QDS_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT" diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig index 235d3ea..275e494 100644 --- a/configs/B4860QDS_SPIFLASH_defconfig +++ b/configs/B4860QDS_SPIFLASH_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig index dda1944..928fc67 100644 --- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig index 15b3dfb..e0eafaf 100644 --- a/configs/B4860QDS_defconfig +++ b/configs/B4860QDS_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860" diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig index bb63eea..88127b7 100644 --- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig +++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9131RDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100" diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig index 3f536e6..f80d9c6 100644 --- a/configs/BSC9131RDB_NAND_defconfig +++ b/configs/BSC9131RDB_NAND_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9131RDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND" diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig index 895ae12..fbe1ccd 100644 --- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig +++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9131RDB=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100" diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig index 8961976..baaf91c 100644 --- a/configs/BSC9131RDB_SPIFLASH_defconfig +++ b/configs/BSC9131RDB_SPIFLASH_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9131RDB=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH" diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig index 8aef0d6..4904a1d 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT" diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig index 14daffa..71f8faa 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100" diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig index ac31fad..721b7f5 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT" diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig index 2474172..37e413d 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133" diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig index b26f6e0..1ecca15 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT" diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig index 7eaa32d..5e13188 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100" diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig index 13d7794..536ae0d 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT" diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig index 7e205c5..aeaf1e8 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133" diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig index 8e5585a..6ee5d30 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT" diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig index 6a7920f..85731bc 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100" diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig index 920cf6c..bbd515b 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT" diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig index 95a35f2..5bcaae5 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133" diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig index c55b5a7..610b747 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT" diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig index 85e4701..177dec4 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100" diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig index 7eb3727..d7e6281 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT" diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig index b8e4e7d..7eed6cc 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y +CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133" diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 8dcf4a7..904d27d 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -1,11 +1,9 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi" -CONFIG_GMAC_TX_DELAY=3 CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_GMAC_TX_DELAY=3 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index d3e015c..7b7556b 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -1,13 +1,11 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro" -CONFIG_USB1_VBUS_PIN="PH0" -CONFIG_USB2_VBUS_PIN="PH1" -CONFIG_GMAC_TX_DELAY=3 CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_USB1_VBUS_PIN="PH0" +CONFIG_USB2_VBUS_PIN="PH1" +CONFIG_GMAC_TX_DELAY=3 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig index f4de2b3..b86dea8 100644 --- a/configs/C29XPCIE_NAND_defconfig +++ b/configs/C29XPCIE_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND" diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig index 86751cf..afbc3b3 100644 --- a/configs/C29XPCIE_NOR_SECBOOT_defconfig +++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y +CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT" diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig index d1a42b2..9d3e0b3 100644 --- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig +++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y +CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT" diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig index 2185d9d..ab196e7 100644 --- a/configs/C29XPCIE_SPIFLASH_defconfig +++ b/configs/C29XPCIE_SPIFLASH_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y +CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH" diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig index 2ee3305..b968504 100644 --- a/configs/C29XPCIE_defconfig +++ b/configs/C29XPCIE_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y +CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT" diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index 817cd6d..850d70d 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -1,16 +1,12 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC" -CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=123 -# Ethernet phy power -CONFIG_AXP221_DLDO1_VOLT=3300 -# Wifi power -CONFIG_AXP221_ALDO1_VOLT=3300 -# No Vbus gpio for either usb CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" +CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC" CONFIG_ETH_DESIGNWARE=y +CONFIG_AXP221_DLDO1_VOLT=3300 +CONFIG_AXP221_ALDO1_VOLT=3300 diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index 9053075..819b353 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -1,20 +1,19 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825" -CONFIG_USB_MUSB_SUNXI=y +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN4I=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_EMR1=4 CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:51000,le:19,ri:300,up:6,lo:31,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" +CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y +CONFIG_USB_MUSB_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" CONFIG_VIDEO_LCD_SPI_CS="PA0" CONFIG_VIDEO_LCD_SPI_SCLK="PA1" CONFIG_VIDEO_LCD_SPI_MOSI="PA2" -CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y -CONFIG_DRAM_CLK=408 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=4 diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index c7efabc..e6bed2d 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -1,13 +1,11 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC" -CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=240 CONFIG_DRAM_ZQ=251 -# Wifi power -CONFIG_AXP221_ALDO1_VOLT=3300 -# No Vbus gpio for usb1 CONFIG_USB1_VBUS_PIN="" +CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC" CONFIG_ETH_DESIGNWARE=y +CONFIG_AXP221_ALDO1_VOLT=3300 diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index 092d6b0..e88cce4 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -1,11 +1,9 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2" -CONFIG_MMC0_CD_PIN="PH1" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=480 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_MMC0_CD_PIN="PH1" +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index 09b67ff..ce9591d 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -1,9 +1,7 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=480 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=0 +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI" diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index 50d6d66..c34ab50 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -1,12 +1,10 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck" -CONFIG_GMAC_TX_DELAY=1 -CONFIG_VIDEO_VGA=y CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_VIDEO_VGA=y +CONFIG_GMAC_TX_DELAY=1 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig index 9e049b2..015140f 100644 --- a/configs/Hummingbird_A31_defconfig +++ b/configs/Hummingbird_A31_defconfig @@ -1,17 +1,13 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)" -CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird" -CONFIG_VIDEO_VGA_VIA_LCD=y -CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN6I=y -CONFIG_DRAM_CLK=312 CONFIG_DRAM_ZQ=251 -# Wifi power -CONFIG_AXP221_ALDO1_VOLT=3300 -# Vbus gpio for usb1 CONFIG_USB1_VBUS_PIN="PH24" -# No Vbus gpio for usb2 CONFIG_USB2_VBUS_PIN="" +CONFIG_VIDEO_VGA_VIA_LCD=y +CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25" +CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)" CONFIG_ETH_DESIGNWARE=y +CONFIG_AXP221_ALDO1_VOLT=3300 diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index 3b71719..e26f4f0 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -1,24 +1,18 @@ -# The Hyundai A7HD is a 7" 16:9 A10 powered tablet featuring 1G RAM, 8G -# nand, 1024x600 IPS screen, a mini hdmi port, mini usb receptacle and a -# headphones port for details see: http://linux-sunxi.org/Hyundai_A7HD -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd" -CONFIG_USB_MUSB_SUNXI=y +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN4I=y +CONFIG_DRAM_EMR1=4 CONFIG_USB0_VBUS_PIN="PB09" CONFIG_USB0_VBUS_DET="PH5" CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="PH6" CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:45,ri:274,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" -CONFIG_VIDEO_LCD_DCLK_PHASE=1 CONFIG_VIDEO_LCD_POWER="PH2" CONFIG_VIDEO_LCD_BL_EN="PH9" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW=n +# CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y -CONFIG_DRAM_CLK=360 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=4 +CONFIG_USB_MUSB_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" diff --git a/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig b/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig index f54e2ee..5b1080f 100644 --- a/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig +++ b/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig @@ -1,9 +1,8 @@ -# This is a defconfig for generic 7" tablets using the Ippo q8h v1.2 pcb, -# with an A33 SoC (the pcb can take an A23 or an A33), and a 1024x600 LCD -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" -CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ippo-q8h-v1.2-lcd1024x600" -CONFIG_USB_MUSB_SUNXI=y +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A33=y +CONFIG_DRAM_CLK=480 +CONFIG_DRAM_ZQ=15291 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y @@ -12,13 +11,9 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN8I_A33=y -CONFIG_DRAM_CLK=480 -# zq = 0x3bbb -CONFIG_DRAM_ZQ=15291 -# Wifi power +CONFIG_USB_MUSB_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ippo-q8h-v1.2-lcd1024x600" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" CONFIG_AXP221_DLDO1_VOLT=3300 -# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP CONFIG_AXP221_ALDO1_VOLT=3000 diff --git a/configs/Ippo_q8h_v1_2_defconfig b/configs/Ippo_q8h_v1_2_defconfig index a6d58e7..8d03300 100644 --- a/configs/Ippo_q8h_v1_2_defconfig +++ b/configs/Ippo_q8h_v1_2_defconfig @@ -1,7 +1,8 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" -CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v1.2" -CONFIG_USB_MUSB_SUNXI=y +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A23=y +CONFIG_DRAM_CLK=432 +CONFIG_DRAM_ZQ=63306 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y @@ -10,13 +11,9 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN8I_A23=y -CONFIG_DRAM_CLK=432 -# zq = 0xf74a -CONFIG_DRAM_ZQ=63306 -# Wifi power +CONFIG_USB_MUSB_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v1.2" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" CONFIG_AXP221_DLDO1_VOLT=3300 -# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP CONFIG_AXP221_ALDO1_VOLT=3000 diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig index 7f6e4ce..1a07064 100644 --- a/configs/Ippo_q8h_v5_defconfig +++ b/configs/Ippo_q8h_v5_defconfig @@ -1,7 +1,8 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" -CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5" -CONFIG_USB_MUSB_SUNXI=y +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A23=y +CONFIG_DRAM_CLK=480 +CONFIG_DRAM_ZQ=63351 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y @@ -10,13 +11,9 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN8I_A23=y -CONFIG_DRAM_CLK=480 -# zq = 0xf777 -CONFIG_DRAM_ZQ=63351 -# Wifi power +CONFIG_USB_MUSB_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" CONFIG_AXP221_DLDO1_VOLT=3300 -# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP CONFIG_AXP221_ALDO1_VOLT=3000 diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig index 60d2357..be381ef 100644 --- a/configs/Linksprite_pcDuino3_Nano_defconfig +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -1,12 +1,11 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano" -CONFIG_GMAC_TX_DELAY=3 -CONFIG_USB1_VBUS_PIN="PH11" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_ZQ=122 -CONFIG_DRAM_EMR1=4 +CONFIG_USB1_VBUS_PIN="PH11" +CONFIG_GMAC_TX_DELAY=3 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index 83e539d..2c846f9 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -1,10 +1,9 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=480 CONFIG_DRAM_ZQ=122 -CONFIG_DRAM_EMR1=4 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index 93366d3..aed5b59 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -1,9 +1,7 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=0 +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI" diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig index bcf2359..a13cc8b 100644 --- a/configs/M52277EVB_defconfig +++ b/configs/M52277EVB_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000" CONFIG_M68K=y CONFIG_TARGET_M52277EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000" diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig index 0e49bc3..65de4d5 100644 --- a/configs/M52277EVB_stmicro_defconfig +++ b/configs/M52277EVB_stmicro_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000" CONFIG_M68K=y CONFIG_TARGET_M52277EVB=y +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000" diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index e6facec..e19b730 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000" CONFIG_M68K=y CONFIG_TARGET_M5235EVB=y +CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000" diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index 04b11ec..afb14b0 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFE00000" CONFIG_M68K=y CONFIG_TARGET_M5235EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFE00000" diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index 048d3a9..c52bfa3 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0" CONFIG_M68K=y CONFIG_TARGET_M5329EVB=y +CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0" diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index 01e3d6a..4154742 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" CONFIG_M68K=y CONFIG_TARGET_M5329EVB=y +CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index 51a7b81..f71c0bf 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" CONFIG_M68K=y CONFIG_TARGET_M5373EVB=y +CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig index 8f18bbe..dceaab3 100644 --- a/configs/M54418TWR_defconfig +++ b/configs/M54418TWR_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig index 4b1c6c9..722cdf0 100644 --- a/configs/M54418TWR_nand_mii_defconfig +++ b/configs/M54418TWR_nand_mii_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000" CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000" diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig index 72cc83c..a411f98 100644 --- a/configs/M54418TWR_nand_rmii_defconfig +++ b/configs/M54418TWR_nand_rmii_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig index 0bc929f..7fb9a1d 100644 --- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig +++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig index 93fe401..83bbb98 100644 --- a/configs/M54418TWR_serial_mii_defconfig +++ b/configs/M54418TWR_serial_mii_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000" CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000" diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig index 8f18bbe..dceaab3 100644 --- a/configs/M54418TWR_serial_rmii_defconfig +++ b/configs/M54418TWR_serial_rmii_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000" diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig index af02731..804e888 100644 --- a/configs/M54451EVB_defconfig +++ b/configs/M54451EVB_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000" CONFIG_M68K=y CONFIG_TARGET_M54451EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000" diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig index 4a3c87f..93412d0 100644 --- a/configs/M54451EVB_stmicro_defconfig +++ b/configs/M54451EVB_stmicro_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000" CONFIG_M68K=y CONFIG_TARGET_M54451EVB=y +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000" diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig index b05a12e..e137545 100644 --- a/configs/M54455EVB_a66_defconfig +++ b/configs/M54455EVB_a66_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666" CONFIG_M68K=y CONFIG_TARGET_M54455EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666" diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig index ffd3407..2eddfd6 100644 --- a/configs/M54455EVB_defconfig +++ b/configs/M54455EVB_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333" CONFIG_M68K=y CONFIG_TARGET_M54455EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333" diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig index 90cf787..583d847 100644 --- a/configs/M54455EVB_i66_defconfig +++ b/configs/M54455EVB_i66_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666" CONFIG_M68K=y CONFIG_TARGET_M54455EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666" diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig index a3d69db..2ec20f4 100644 --- a/configs/M54455EVB_intel_defconfig +++ b/configs/M54455EVB_intel_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333" CONFIG_M68K=y CONFIG_TARGET_M54455EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333" diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig index cf33d0f..e50c124 100644 --- a/configs/M54455EVB_stm33_defconfig +++ b/configs/M54455EVB_stm33_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333" CONFIG_M68K=y CONFIG_TARGET_M54455EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333" diff --git a/configs/M5475AFE_defconfig b/configs/M5475AFE_defconfig index 28fd0ec..7eb5ec8 100644 --- a/configs/M5475AFE_defconfig +++ b/configs/M5475AFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64" CONFIG_M68K=y CONFIG_TARGET_M5475EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64" diff --git a/configs/M5475BFE_defconfig b/configs/M5475BFE_defconfig index 329f3e3..bcf67ca 100644 --- a/configs/M5475BFE_defconfig +++ b/configs/M5475BFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16" CONFIG_M68K=y CONFIG_TARGET_M5475EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16" diff --git a/configs/M5475CFE_defconfig b/configs/M5475CFE_defconfig index 8dd75db..d51fa15 100644 --- a/configs/M5475CFE_defconfig +++ b/configs/M5475CFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL" CONFIG_M68K=y CONFIG_TARGET_M5475EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL" diff --git a/configs/M5475DFE_defconfig b/configs/M5475DFE_defconfig index a6288da..25bee35 100644 --- a/configs/M5475DFE_defconfig +++ b/configs/M5475DFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL" CONFIG_M68K=y CONFIG_TARGET_M5475EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL" diff --git a/configs/M5475EFE_defconfig b/configs/M5475EFE_defconfig index 19640a2..e5d7fa8 100644 --- a/configs/M5475EFE_defconfig +++ b/configs/M5475EFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL" CONFIG_M68K=y CONFIG_TARGET_M5475EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL" diff --git a/configs/M5475FFE_defconfig b/configs/M5475FFE_defconfig index 0201d38..dd26c62 100644 --- a/configs/M5475FFE_defconfig +++ b/configs/M5475FFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64" CONFIG_M68K=y CONFIG_TARGET_M5475EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64" diff --git a/configs/M5475GFE_defconfig b/configs/M5475GFE_defconfig index b876868..d1560bb 100644 --- a/configs/M5475GFE_defconfig +++ b/configs/M5475GFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64" CONFIG_M68K=y CONFIG_TARGET_M5475EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64" diff --git a/configs/M5485AFE_defconfig b/configs/M5485AFE_defconfig index 612218d..7f5ae64 100644 --- a/configs/M5485AFE_defconfig +++ b/configs/M5485AFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64" CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64" diff --git a/configs/M5485BFE_defconfig b/configs/M5485BFE_defconfig index 697feb0..7fa7fb1 100644 --- a/configs/M5485BFE_defconfig +++ b/configs/M5485BFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16" CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16" diff --git a/configs/M5485CFE_defconfig b/configs/M5485CFE_defconfig index 46c0d08..a8b9ea7 100644 --- a/configs/M5485CFE_defconfig +++ b/configs/M5485CFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL" CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL" diff --git a/configs/M5485DFE_defconfig b/configs/M5485DFE_defconfig index ad6248d..f6174ec 100644 --- a/configs/M5485DFE_defconfig +++ b/configs/M5485DFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL" CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL" diff --git a/configs/M5485EFE_defconfig b/configs/M5485EFE_defconfig index 5f27496..868c7f2 100644 --- a/configs/M5485EFE_defconfig +++ b/configs/M5485EFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL" CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL" diff --git a/configs/M5485FFE_defconfig b/configs/M5485FFE_defconfig index b1da743..773c4f4 100644 --- a/configs/M5485FFE_defconfig +++ b/configs/M5485FFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64" CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64" diff --git a/configs/M5485GFE_defconfig b/configs/M5485GFE_defconfig index 578d24a..ff1e8f4 100644 --- a/configs/M5485GFE_defconfig +++ b/configs/M5485GFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64" CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64" diff --git a/configs/M5485HFE_defconfig b/configs/M5485HFE_defconfig index c632055..ba87cb7 100644 --- a/configs/M5485HFE_defconfig +++ b/configs/M5485HFE_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO" CONFIG_M68K=y CONFIG_TARGET_M5485EVB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO" diff --git a/configs/MIP405T_defconfig b/configs/MIP405T_defconfig index 304d890..f8ccc81 100644 --- a/configs/MIP405T_defconfig +++ b/configs/MIP405T_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="MIP405T" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_MIP405=y +CONFIG_SYS_EXTRA_OPTIONS="MIP405T" diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig index fcacfc6..88df54c 100644 --- a/configs/MK808C_defconfig +++ b/configs/MK808C_defconfig @@ -1,13 +1,7 @@ -# The MK808C is an Allwinner based Android TV dongle. -# -# It features a A20 SOC, 1G RAM, 8GB NAND, HDMI out, A/V out, -# 1 USB A, 1 USB mini OTG, Bluetooth and Wireless LAN. -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI" diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index ca6c304..b272d9b 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index 974bdf9..3df3653 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index ba81885..5b798e4 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND" diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index afe8740..0feef7b 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND" diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index e1ba08d..6c96e3a 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 55df0f6..81d3059 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 1ceee68..93b6860 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index ef67be5..304e035 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE" diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index f853309..53ed247 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y +CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 5321801..baae2c0 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y +CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index 83f25ae..747f79e 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y +CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX" diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index d3be43a..8bc56ef 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XEMDS=y +CONFIG_SYS_EXTRA_OPTIONS="PCI" diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig index 45dc91a..f39153b 100644 --- a/configs/MPC8536DS_36BIT_defconfig +++ b/configs/MPC8536DS_36BIT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8536DS=y +CONFIG_SYS_EXTRA_OPTIONS="36BIT" diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig index 4a9f0cd..0ea8835 100644 --- a/configs/MPC8536DS_SDCARD_defconfig +++ b/configs/MPC8536DS_SDCARD_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8536DS=y +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig index 2d357e8..02410ee 100644 --- a/configs/MPC8536DS_SPIFLASH_defconfig +++ b/configs/MPC8536DS_SPIFLASH_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8536DS=y +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig index 502fbfc..55478ab 100644 --- a/configs/MPC8541CDS_legacy_defconfig +++ b/configs/MPC8541CDS_legacy_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="LEGACY" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8541CDS=y +CONFIG_SYS_EXTRA_OPTIONS="LEGACY" diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 438ea85..dfe1fca 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8548CDS=y +CONFIG_SYS_EXTRA_OPTIONS="36BIT" diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index e027b2f..69c44af 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="LEGACY" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8548CDS=y +CONFIG_SYS_EXTRA_OPTIONS="LEGACY" diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig index 3040905..8e53ee0 100644 --- a/configs/MPC8555CDS_legacy_defconfig +++ b/configs/MPC8555CDS_legacy_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="LEGACY" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8555CDS=y +CONFIG_SYS_EXTRA_OPTIONS="LEGACY" diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig index 5730180..326983d 100644 --- a/configs/MPC8569MDS_ATM_defconfig +++ b/configs/MPC8569MDS_ATM_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="ATM" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8569MDS=y +CONFIG_SYS_EXTRA_OPTIONS="ATM" diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig index 9a26a59..0ce85e4 100644 --- a/configs/MPC8572DS_36BIT_defconfig +++ b/configs/MPC8572DS_36BIT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8572DS=y +CONFIG_SYS_EXTRA_OPTIONS="36BIT" diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig index 525fa06..6005c59 100644 --- a/configs/MPC8641HPCN_36BIT_defconfig +++ b/configs/MPC8641HPCN_36BIT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PHYS_64BIT" CONFIG_PPC=y CONFIG_MPC86xx=y CONFIG_TARGET_MPC8641HPCN=y +CONFIG_SYS_EXTRA_OPTIONS="PHYS_64BIT" diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig index c767b3d..00f0796 100644 --- a/configs/MSI_Primo73_defconfig +++ b/configs/MSI_Primo73_defconfig @@ -1,23 +1,13 @@ -# The MSI Primo73 is an A20 based tablet, with 1G RAM, 16G NAND, -# 1024x600 TN LCD display, mono speaker, 0.3 MP front camera, 2.0 MP -# rear camera, 3000 mAh battery, gt911 touchscreen, mma8452 accelerometer -# and rtl8188etv usb wifi. Has "power", "volume+" and "volume-" buttons -# (both volume buttons are also connected to the UBOOT_SEL pin). The -# external connectors are represented by MicroSD slot, MiniHDMI, MicroUSB -# OTG and 3.5mm headphone jack. More details are available at -# http://linux-sunxi.org/MSI_Primo73 -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73" +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN7I=y +CONFIG_DRAM_CLK=384 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:60000,le:60,ri:160,up:13,lo:12,hs:100,vs:10,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_USB_KEYBOARD=n -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=384 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +# CONFIG_USB_KEYBOARD is not set +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig index 7e41e4b..83a95cb 100644 --- a/configs/MSI_Primo81_defconfig +++ b/configs/MSI_Primo81_defconfig @@ -1,30 +1,19 @@ -# The MSI Primo81 is an A31s based tablet, with 1G RAM, 16G NAND, -# 1024x768 IPS LCD display, mono speaker, 0.3 MP front camera, 2.0 MP -# rear camera, 3500 mAh battery, gt911 touchscreen, mma8452 accelerometer -# and rtl8188etv usb wifi. Has "power", "volume+" and "volume-" buttons -# (both volume buttons are also connected to the UBOOT_SEL pin). The -# external connectors are represented by MicroSD slot, MiniHDMI, MicroUSB -# OTG and 3.5mm headphone jack. More details are available at -# http://linux-sunxi.org/MSI_Primo81 - -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="" -CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81" +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN6I=y +CONFIG_DRAM_CLK=360 +CONFIG_DRAM_ZQ=122 CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo:36,hs:64,vs:50,sync:3,vmode:0" +CONFIG_VIDEO_LCD_BL_EN="PA25" +CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y +# CONFIG_USB_KEYBOARD is not set +CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81" +CONFIG_SPL=y +CONFIG_AXP221_DLDO1_VOLT=3300 CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27 CONFIG_VIDEO_LCD_SSD2828_RESET="PA26" CONFIG_VIDEO_LCD_SPI_CS="PH9" CONFIG_VIDEO_LCD_SPI_SCLK="PH10" CONFIG_VIDEO_LCD_SPI_MOSI="PH11" CONFIG_VIDEO_LCD_SPI_MISO="PH12" -CONFIG_VIDEO_LCD_BL_EN="PA25" -CONFIG_VIDEO_LCD_BL_PWM="PH13" -CONFIG_USB_KEYBOARD=n -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN6I=y -CONFIG_DRAM_CLK=360 -CONFIG_DRAM_ZQ=122 -# Wifi power -CONFIG_AXP221_DLDO1_VOLT=3300 diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index e47709f..5a9703d 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -1,9 +1,6 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y -CONFIG_DRAM_CLK=360 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=0 +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,USB_EHCI" diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index 32b20a7..6678e4c 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -1,10 +1,7 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000" -CONFIG_VIDEO_VGA=y CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y -CONFIG_DRAM_CLK=360 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=0 +CONFIG_VIDEO_VGA=y +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI" diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig index adcf3b2..bf67433 100644 --- a/configs/Mele_I7_defconfig +++ b/configs/Mele_I7_defconfig @@ -1,27 +1,14 @@ -# The Mele I7 is a Allwinner based Android TV box. -# -# It features a A31 SOC, 1G RAM, 8GB NAND, HDMI out, A/V out, -# SPDIF, IrDA, 3 USB A, 1 USB micro OTG and Wireless LAN. -# -# For more details see: http://linux-sunxi.org/Mele_I7 -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC" -CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN6I=y -CONFIG_DRAM_CLK=312 CONFIG_DRAM_ZQ=120 -# The Mele I7 uses 3.3V for general IO +CONFIG_USB1_VBUS_PIN="PC27" +CONFIG_USB2_VBUS_PIN="" +CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC" +CONFIG_ETH_DESIGNWARE=y CONFIG_AXP221_DCDC1_VOLT=3300 -# Ethernet phy power CONFIG_AXP221_DLDO1_VOLT=3300 -# USB hub power CONFIG_AXP221_DLDO4_VOLT=3300 -# Wifi power CONFIG_AXP221_ALDO1_VOLT=3300 -# Vbus gpio for usb1 -CONFIG_USB1_VBUS_PIN="PC27" -# No Vbus gpio for usb2 -CONFIG_USB2_VBUS_PIN="" -CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig index e2f8d65..9c2eb86 100644 --- a/configs/Mele_M3_defconfig +++ b/configs/Mele_M3_defconfig @@ -1,13 +1,11 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3" -CONFIG_VIDEO_VGA=y -CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_MMC0_CD_PIN="PH1" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_MMC0_CD_PIN="PH1" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_VIDEO_VGA=y +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,USB_EHCI" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig index 78fba71..5ee648b 100644 --- a/configs/Mele_M5_defconfig +++ b/configs/Mele_M5_defconfig @@ -1,14 +1,10 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,USB_EHCI,STATUSLED=234" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5" -CONFIG_VIDEO_HDMI=y -CONFIG_MMC0_CD_PIN="PH1" -CONFIG_USB1_VBUS_PIN="PH6" -CONFIG_USB2_VBUS_PIN="PH3" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_ZQ=122 -CONFIG_DRAM_EMR1=4 +CONFIG_MMC0_CD_PIN="PH1" +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,USB_EHCI,STATUSLED=234" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index ea35024..4708133 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -1,21 +1,14 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC" -CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN6I=y -CONFIG_DRAM_CLK=312 CONFIG_DRAM_ZQ=120 -# The Mele M9 uses 3.3V for general IO +CONFIG_USB1_VBUS_PIN="PC27" +CONFIG_USB2_VBUS_PIN="" +CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC" +CONFIG_ETH_DESIGNWARE=y CONFIG_AXP221_DCDC1_VOLT=3300 -# Ethernet phy power CONFIG_AXP221_DLDO1_VOLT=3300 -# USB hub power CONFIG_AXP221_DLDO4_VOLT=3300 -# Wifi power CONFIG_AXP221_ALDO1_VOLT=3300 -# Vbus gpio for usb1 -CONFIG_USB1_VBUS_PIN="PC27" -# No Vbus gpio for usb2 -CONFIG_USB2_VBUS_PIN="" -CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index 434c561..918b639 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -1,9 +1,6 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y -CONFIG_DRAM_CLK=360 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=0 +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI" diff --git a/configs/MiniFAP_defconfig b/configs/MiniFAP_defconfig index 8eccf26..6b4f2b2 100644 --- a/configs/MiniFAP_defconfig +++ b/configs/MiniFAP_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="MINIFAP" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y +CONFIG_SYS_EXTRA_OPTIONS="MINIFAP" diff --git a/configs/O2DNT2_RAMBOOT_defconfig b/configs/O2DNT2_RAMBOOT_defconfig index 49e60ab..8549b8e 100644 --- a/configs/O2DNT2_RAMBOOT_defconfig +++ b/configs/O2DNT2_RAMBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_O2DNT2=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000" diff --git a/configs/O2MNT_O2M110_defconfig b/configs/O2MNT_O2M110_defconfig index 12428de..320b898 100644 --- a/configs/O2MNT_O2M110_defconfig +++ b/configs/O2MNT_O2M110_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M110\"" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_O2MNT=y +CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M110\"" diff --git a/configs/O2MNT_O2M112_defconfig b/configs/O2MNT_O2M112_defconfig index a56329a..b17330a 100644 --- a/configs/O2MNT_O2M112_defconfig +++ b/configs/O2MNT_O2M112_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M112\"" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_O2MNT=y +CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M112\"" diff --git a/configs/O2MNT_O2M113_defconfig b/configs/O2MNT_O2M113_defconfig index 03f54ca..86ec47a 100644 --- a/configs/O2MNT_O2M113_defconfig +++ b/configs/O2MNT_O2M113_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M113\"" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_O2MNT=y +CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M113\"" diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index cd25521..9d5e5dc 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -1,21 +1,12 @@ -# The Orangepi is a development board using the Allwinner A20 SoC, with 1G -# RAM, microsd slot, HDMI, 1Gbit ethernet, USB wifi, Micro USB (otg), sata, -# 4 USB A ports, ir receiver and a headphones jack. -# -# Also see: -# http://linux-sunxi.org/Xunlong_Orange_Pi -# http://www.orangepi.org/ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi" -CONFIG_GMAC_TX_DELAY=3 -CONFIG_USB1_VBUS_PIN="PH26" -CONFIG_USB2_VBUS_PIN="PH22" -CONFIG_VIDEO_VGA=y CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_USB1_VBUS_PIN="PH26" +CONFIG_USB2_VBUS_PIN="PH22" +CONFIG_VIDEO_VGA=y +CONFIG_GMAC_TX_DELAY=3 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index 0bef159..99cc600 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -1,24 +1,14 @@ -# The Orangepi mini is a development board using the Allwinner A20 SoC, -# with 1G RAM, 2 microsd slots (use the top side one for booting), HDMI, -# 1Gbit ethernet, USB wifi, Micro USB (otg), sata, 2 USB A ports, -# ir receiver and a headphones jack. -# -# Also see: -# http://linux-sunxi.org/Xunlong_Orange_Pi_Mini -# http://www.orangepi.org/ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini" -CONFIG_MMC_SUNXI_SLOT_EXTRA=3 -CONFIG_MMC0_CD_PIN="PH10" -CONFIG_MMC3_CD_PIN="PH11" -CONFIG_GMAC_TX_DELAY=3 -CONFIG_USB1_VBUS_PIN="PH26" -CONFIG_USB2_VBUS_PIN="PH22" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_MMC0_CD_PIN="PH10" +CONFIG_MMC3_CD_PIN="PH11" +CONFIG_MMC_SUNXI_SLOT_EXTRA=3 +CONFIG_USB1_VBUS_PIN="PH26" +CONFIG_USB2_VBUS_PIN="PH22" +CONFIG_GMAC_TX_DELAY=3 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig index c441d9f..6245bd8 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT" diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 6449b2d..35c47de 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND" diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig index 197141a..6bffe04 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT" diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 8739428..d3b99d1 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT" diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 9a36f5c..50598f0 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD" diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig index 2dae76c..3680b58 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT" diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index b985fa5..54f0664 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH" diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig index c3c30fa..cec155d 100644 --- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT" diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index f19d5d2..d2a4268 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND" diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig index 9769a2f..d143079 100644 --- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT" diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 8935503..223f783 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA" diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index a7888ca..6229dad 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD" diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig index 76499d9..a8019bb 100644 --- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT" diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index 2731a01..de54e1d 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH" diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig index be6fe06..61e559d 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT" diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index a81424c..54bd88d 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND" diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig index 90e278d3..a4656ea 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT" diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index ac23218..ac78763 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT" diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index eaa7da7..50e8005 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD" diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig index e2a379d..6ebe23c 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT" diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 39e3545..7461016 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH" diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig index de34914..c43ea2b 100644 --- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT" diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 1e11593..c6bec43 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND" diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig index 78221af..9c65183 100644 --- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT" diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index a2386c7..4bf4ac9 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB" diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 1d6a421..af9a4dd 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD" diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig index 1cba920..65a2a42 100644 --- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT" diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 106b2bc..83f434d 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH" diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig index 1036dc2..59aa9be 100644 --- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT" diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig index 503ee0c..b8d9c53 100644 --- a/configs/P1020MBG-PC_36BIT_defconfig +++ b/configs/P1020MBG-PC_36BIT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT" diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig index 1aac35b..0e64e82 100644 --- a/configs/P1020MBG-PC_SDCARD_defconfig +++ b/configs/P1020MBG-PC_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD" diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig index cee84ef..905b94c 100644 --- a/configs/P1020MBG-PC_defconfig +++ b/configs/P1020MBG-PC_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1020MBG" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P1020MBG" diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 86c05e9..d61c848 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND" diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 7d483d3..1e59860 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD" diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 44b38cb..073b77c 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH" diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 2120a09..b95841c 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT" diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 69a05a8..f8106a0 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND" diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 5a72da1..f781a7b 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD" diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 335e703..32d91e4 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH" diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index a19a59f..e3f11d5 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC" diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 2ff990b..a869d68 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND" diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index fc7b89d..10827e5 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD" diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index fb4269f..02cbb69 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH" diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 61f7a02..74f6c6d 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD" diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig index 6a84344..f94345c 100644 --- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD" diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig index 6892cc2..ac4bbd3 100644 --- a/configs/P1020UTM-PC_36BIT_defconfig +++ b/configs/P1020UTM-PC_36BIT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT" diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig index c91a50c..c4cd42e7 100644 --- a/configs/P1020UTM-PC_SDCARD_defconfig +++ b/configs/P1020UTM-PC_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD" diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig index 4c28014..aae966b 100644 --- a/configs/P1020UTM-PC_defconfig +++ b/configs/P1020UTM-PC_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1020UTM" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P1020UTM" diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig index ae764b6..2ef7735 100644 --- a/configs/P1021RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND" diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig index 36216e9..ae9280a 100644 --- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD" diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig index bd600f0..260d1eb 100644 --- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH" diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig index eae7d2d..8349514 100644 --- a/configs/P1021RDB-PC_36BIT_defconfig +++ b/configs/P1021RDB-PC_36BIT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT" diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig index e4523de..fda74df 100644 --- a/configs/P1021RDB-PC_NAND_defconfig +++ b/configs/P1021RDB-PC_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND" diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig index 8a40f29..9da9221 100644 --- a/configs/P1021RDB-PC_SDCARD_defconfig +++ b/configs/P1021RDB-PC_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD" diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig index 1b1b3fc..e126d65 100644 --- a/configs/P1021RDB-PC_SPIFLASH_defconfig +++ b/configs/P1021RDB-PC_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH" diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig index 7557da2..761edd6 100644 --- a/configs/P1021RDB-PC_defconfig +++ b/configs/P1021RDB-PC_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P1021RDB" diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig index 0c326cd..9590558 100644 --- a/configs/P1022DS_36BIT_NAND_defconfig +++ b/configs/P1022DS_36BIT_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1022DS=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND" diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig index 4990fc4..cb297b3 100644 --- a/configs/P1022DS_36BIT_SDCARD_defconfig +++ b/configs/P1022DS_36BIT_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1022DS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD" diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig index 4d7d7ac..df57db6 100644 --- a/configs/P1022DS_36BIT_SPIFLASH_defconfig +++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1022DS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH" diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig index f2ff2d0..d62f9f7 100644 --- a/configs/P1022DS_36BIT_defconfig +++ b/configs/P1022DS_36BIT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1022DS=y +CONFIG_SYS_EXTRA_OPTIONS="36BIT" diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig index 03b6e27..cf73c18 100644 --- a/configs/P1022DS_NAND_defconfig +++ b/configs/P1022DS_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1022DS=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="NAND" diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig index 0b693b3..b69467e 100644 --- a/configs/P1022DS_SDCARD_defconfig +++ b/configs/P1022DS_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1022DS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig index 2fc5981..808b366 100644 --- a/configs/P1022DS_SPIFLASH_defconfig +++ b/configs/P1022DS_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1022DS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig index 687277f..b1cd35c 100644 --- a/configs/P1024RDB_36BIT_defconfig +++ b/configs/P1024RDB_36BIT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT" diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig index f0ba0dc..7afa100 100644 --- a/configs/P1024RDB_NAND_defconfig +++ b/configs/P1024RDB_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND" diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig index 1c4968d..4a2e3ed 100644 --- a/configs/P1024RDB_SDCARD_defconfig +++ b/configs/P1024RDB_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD" diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig index 744ddbe..883d95e 100644 --- a/configs/P1024RDB_SPIFLASH_defconfig +++ b/configs/P1024RDB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH" diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig index 89e88f2..5a9edb7 100644 --- a/configs/P1024RDB_defconfig +++ b/configs/P1024RDB_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1024RDB" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P1024RDB" diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig index 6903fec..832eeb3 100644 --- a/configs/P1025RDB_36BIT_defconfig +++ b/configs/P1025RDB_36BIT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT" diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig index 266ca17..baf055e 100644 --- a/configs/P1025RDB_NAND_defconfig +++ b/configs/P1025RDB_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND" diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig index 0563bbd..95f841e 100644 --- a/configs/P1025RDB_SDCARD_defconfig +++ b/configs/P1025RDB_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD" diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig index 765db63..3affb9e 100644 --- a/configs/P1025RDB_SPIFLASH_defconfig +++ b/configs/P1025RDB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH" diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig index 589e174..43b38a1 100644 --- a/configs/P1025RDB_defconfig +++ b/configs/P1025RDB_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P1025RDB" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P1025RDB" diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 8a8f60c..aaf9450 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND" diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 6237621..054bebf 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD" diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 8b1ffa1..dd20fe0 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH" diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 8f0c994..bcae073 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT" diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index b97bde0..f58795e 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_TPL=y +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND" diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 00ce2fc..e72a17b 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD" diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 936fac2..f56dac4 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH" diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 3e46572..a9c3d76 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB" diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 4a4e076..6a6a98f 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index af06581..48df22c 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig index c49dcbf..50f02af 100644 --- a/configs/P2041RDB_SECURE_BOOT_defconfig +++ b/configs/P2041RDB_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index ecba89a..6939ed9 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig index 53bd271..f5dd3af 100644 --- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y +CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index 5934048..20d2449 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index dacadaa..870d783 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig index 9850956..9e0155a 100644 --- a/configs/P3041DS_SECURE_BOOT_defconfig +++ b/configs/P3041DS_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 0a71926..17e6413 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig index 5c14324..4d06bed 100644 --- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y +CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 99fbbf2..ba3ea16 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig index bae1da2..e2c6bcc 100644 --- a/configs/P4080DS_SECURE_BOOT_defconfig +++ b/configs/P4080DS_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index 855319d..8c74031 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig index 6240d73..e1c1e43 100644 --- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y +CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig index 6fe8446..1693cae 100644 --- a/configs/P5020DS_NAND_defconfig +++ b/configs/P5020DS_NAND_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig index e19aa6e..b1bd63c 100644 --- a/configs/P5020DS_SDCARD_defconfig +++ b/configs/P5020DS_SDCARD_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig index 30871d9..8ab306e 100644 --- a/configs/P5020DS_SECURE_BOOT_defconfig +++ b/configs/P5020DS_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig index dbcc056..4a4b112 100644 --- a/configs/P5020DS_SPIFLASH_defconfig +++ b/configs/P5020DS_SPIFLASH_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig index dc191f7..7ebaebd 100644 --- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y +CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index de3cd06..f738dd4 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index f0ef285..da37167 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig index 8e21ca5..e4fbcc9 100644 --- a/configs/P5040DS_SECURE_BOOT_defconfig +++ b/configs/P5040DS_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index a2922f5..a8fb94a 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig index c3ba6a1..54cee92 100644 --- a/configs/T1023RDB_NAND_defconfig +++ b/configs/T1023RDB_NAND_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig index a2632aa..f39b94a 100644 --- a/configs/T1023RDB_SDCARD_defconfig +++ b/configs/T1023RDB_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig index c2e2d7e..0da1db2 100644 --- a/configs/T1023RDB_SECURE_BOOT_defconfig +++ b/configs/T1023RDB_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT" diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig index 202103c..a8e8e7c 100644 --- a/configs/T1023RDB_SPIFLASH_defconfig +++ b/configs/T1023RDB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig index a839925..eea0b9b 100644 --- a/configs/T1023RDB_defconfig +++ b/configs/T1023RDB_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB" diff --git a/configs/T1024QDS_D4_SECURE_BOOT_defconfig b/configs/T1024QDS_D4_SECURE_BOOT_defconfig index d86ae05..1570ee0 100644 --- a/configs/T1024QDS_D4_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_D4_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XQDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT" diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig index e42913d..3563b14 100644 --- a/configs/T1024QDS_NAND_defconfig +++ b/configs/T1024QDS_NAND_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND" diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig index 52e98c0..f4cf6be 100644 --- a/configs/T1024QDS_SDCARD_defconfig +++ b/configs/T1024QDS_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig index b932619..dedc60d 100644 --- a/configs/T1024QDS_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XQDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT" diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig index 1656883..91f0ab8 100644 --- a/configs/T1024QDS_SPIFLASH_defconfig +++ b/configs/T1024QDS_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig index 94a76ba..ed5a667 100644 --- a/configs/T1024QDS_defconfig +++ b/configs/T1024QDS_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XQDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024" diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 7214194..5c90d3a 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 9c33505..5d295ac 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig index be01417..08da947 100644 --- a/configs/T1024RDB_SECURE_BOOT_defconfig +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT" diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 5a59000..474da0b 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index c22b3ed..9e96797 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB" diff --git a/configs/T1040QDS_D4_defconfig b/configs/T1040QDS_D4_defconfig index 0684cb0..ce70c37 100644 --- a/configs/T1040QDS_D4_defconfig +++ b/configs/T1040QDS_D4_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T1040QDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4" diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig index f3f61eb..005e762 100644 --- a/configs/T1040QDS_SECURE_BOOT_defconfig +++ b/configs/T1040QDS_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T1040QDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT" diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig index b8e1a3d..6de2bd6 100644 --- a/configs/T1040QDS_defconfig +++ b/configs/T1040QDS_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T1040QDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040" diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig index fb87031..fdd25c3 100644 --- a/configs/T1040RDB_NAND_defconfig +++ b/configs/T1040RDB_NAND_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig index feb659c..af20611 100644 --- a/configs/T1040RDB_SDCARD_defconfig +++ b/configs/T1040RDB_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig index 0b5ddaf..2e00ccb 100644 --- a/configs/T1040RDB_SECURE_BOOT_defconfig +++ b/configs/T1040RDB_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB" diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig index 699b57e..598dedf 100644 --- a/configs/T1040RDB_SPIFLASH_defconfig +++ b/configs/T1040RDB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig index 072eab0..71ecc81 100644 --- a/configs/T1040RDB_defconfig +++ b/configs/T1040RDB_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB" diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig index 2dd6fda..164def3 100644 --- a/configs/T1042RDB_PI_NAND_defconfig +++ b/configs/T1042RDB_PI_NAND_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND" diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig index 0e33e35..581a8f6 100644 --- a/configs/T1042RDB_PI_SDCARD_defconfig +++ b/configs/T1042RDB_PI_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig index 776fc9a..4bd853c 100644 --- a/configs/T1042RDB_PI_SPIFLASH_defconfig +++ b/configs/T1042RDB_PI_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig index f8f6334..078a105 100644 --- a/configs/T1042RDB_PI_defconfig +++ b/configs/T1042RDB_PI_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI" diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig index c8dd5c2..8aee85f 100644 --- a/configs/T1042RDB_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB" diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig index 85eceb9..7c6de00 100644 --- a/configs/T1042RDB_defconfig +++ b/configs/T1042RDB_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB" diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 0129238..83697da 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND" diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 035a60d..830ced3 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 4f7d709..eb3f086 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT" diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index a831b16..805a730 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 1055486..c086c2b 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 180d155..d657dbd 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080" diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index b778f61..ed38d0c 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND" diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 44fee22..7cb4a72 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig index cee5370..4af6d0c 100644 --- a/configs/T2080RDB_SECURE_BOOT_defconfig +++ b/configs/T2080RDB_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT" diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 05cdc7c..0dce597 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig index 9bdf533..824f021 100644 --- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index f6ade16..9da8e89 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080" diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig index a3d4c53..ca0259c 100644 --- a/configs/T2081QDS_NAND_defconfig +++ b/configs/T2081QDS_NAND_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND" diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig index ebf3c00..a76cf42 100644 --- a/configs/T2081QDS_SDCARD_defconfig +++ b/configs/T2081QDS_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig index ff358e3..32376b6 100644 --- a/configs/T2081QDS_SPIFLASH_defconfig +++ b/configs/T2081QDS_SPIFLASH_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig index 407af92..4d4e44f 100644 --- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig index 93480a6..b24ee59 100644 --- a/configs/T2081QDS_defconfig +++ b/configs/T2081QDS_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081" diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig index 8d1659e..191005a 100644 --- a/configs/T4160QDS_NAND_defconfig +++ b/configs/T4160QDS_NAND_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND" diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig index bf66469..4f1148a 100644 --- a/configs/T4160QDS_SDCARD_defconfig +++ b/configs/T4160QDS_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig index 9fc209f..b55cab9 100644 --- a/configs/T4160QDS_SECURE_BOOT_defconfig +++ b/configs/T4160QDS_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT" diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig index 749f445..b2f81b4 100644 --- a/configs/T4160QDS_defconfig +++ b/configs/T4160QDS_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160" diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig index 34bd914..fc73a47 100644 --- a/configs/T4160RDB_defconfig +++ b/configs/T4160RDB_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240RDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160" diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig index 3070082..9922f13 100644 --- a/configs/T4240QDS_NAND_defconfig +++ b/configs/T4240QDS_NAND_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND" diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig index 3ecd4a0..d31e836 100644 --- a/configs/T4240QDS_SDCARD_defconfig +++ b/configs/T4240QDS_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig index 9cc7775..1488967 100644 --- a/configs/T4240QDS_SECURE_BOOT_defconfig +++ b/configs/T4240QDS_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT" diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig index 7c10655..5ded552 100644 --- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig index 80889e0..0fb7e0e 100644 --- a/configs/T4240QDS_defconfig +++ b/configs/T4240QDS_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index c17ce43..eac2bc4 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240RDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 37b1b55..35e4aa4 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240RDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" diff --git a/configs/TQM5200S_HIGHBOOT_defconfig b/configs/TQM5200S_HIGHBOOT_defconfig index f54377e..3e2c400 100644 --- a/configs/TQM5200S_HIGHBOOT_defconfig +++ b/configs/TQM5200S_HIGHBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y +CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000" diff --git a/configs/TQM5200S_defconfig b/configs/TQM5200S_defconfig index 5d976ce..050410a 100644 --- a/configs/TQM5200S_defconfig +++ b/configs/TQM5200S_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y +CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S" diff --git a/configs/TQM5200_B_HIGHBOOT_defconfig b/configs/TQM5200_B_HIGHBOOT_defconfig index 61c120a..68b0843 100644 --- a/configs/TQM5200_B_HIGHBOOT_defconfig +++ b/configs/TQM5200_B_HIGHBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,SYS_TEXT_BASE=0xFFF00000" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y +CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,SYS_TEXT_BASE=0xFFF00000" diff --git a/configs/TQM5200_B_defconfig b/configs/TQM5200_B_defconfig index ddc5d2c..0ddfe9b 100644 --- a/configs/TQM5200_B_defconfig +++ b/configs/TQM5200_B_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y +CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B" diff --git a/configs/TQM5200_STK100_defconfig b/configs/TQM5200_STK100_defconfig index 9c198c6..24be3d9 100644 --- a/configs/TQM5200_STK100_defconfig +++ b/configs/TQM5200_STK100_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="STK52XX_REV100" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y +CONFIG_SYS_EXTRA_OPTIONS="STK52XX_REV100" diff --git a/configs/TQM823L_LCD_defconfig b/configs/TQM823L_LCD_defconfig index cacd3e2..2ccd1bc 100644 --- a/configs/TQM823L_LCD_defconfig +++ b/configs/TQM823L_LCD_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="LCD,NEC_NL6448BC20" CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM823L=y +CONFIG_SYS_EXTRA_OPTIONS="LCD,NEC_NL6448BC20" diff --git a/configs/TTTech_defconfig b/configs/TTTech_defconfig index be99da3..5270094 100644 --- a/configs/TTTech_defconfig +++ b/configs/TTTech_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01" CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM823L=y +CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01" diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig index 95d758e..c86900a 100644 --- a/configs/TWR-P1025_defconfig +++ b/configs/TWR-P1025_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_TWR=y +CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025" diff --git a/configs/TZX-Q8-713B7_defconfig b/configs/TZX-Q8-713B7_defconfig index 3484a2f..c33317e 100644 --- a/configs/TZX-Q8-713B7_defconfig +++ b/configs/TZX-Q8-713B7_defconfig @@ -1,18 +1,16 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-tzx-q8-713b7" +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_CLK=408 CONFIG_MMC0_CD_PIN="PG0" -CONFIG_USB_MUSB_SUNXI=y CONFIG_USB0_VBUS_PIN="PG12" CONFIG_USB0_VBUS_DET="PG1" +CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_AXP_GPIO=y -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN5I=y -CONFIG_DRAM_CLK=408 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=4 +CONFIG_USB_MUSB_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-tzx-q8-713b7" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" diff --git a/configs/UCP1020_SPIFLASH_defconfig b/configs/UCP1020_SPIFLASH_defconfig index 2ffb8da..c512439 100644 --- a/configs/UCP1020_SPIFLASH_defconfig +++ b/configs/UCP1020_SPIFLASH_defconfig @@ -2,5 +2,3 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_UCP1020=y CONFIG_TARGET_UCP1020_SPIFLASH=y -CONFIG_SPI_FLASH=y -CONFIG_UCP1020=y diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig index 61de360..1c272d6 100644 --- a/configs/UCP1020_defconfig +++ b/configs/UCP1020_defconfig @@ -1,5 +1,3 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_UCP1020=y -CONFIG_SPI_FLASH=y -CONFIG_UCP1020=y diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index ee44b51..9ab2fa5 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -1,9 +1,13 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66" -CONFIG_USB_MUSB_SUNXI=y +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_CLK=432 +CONFIG_DRAM_EMR1=0 +CONFIG_MMC0_CD_PIN="PG0" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_VBUS_PIN="PB04" CONFIG_USB0_VBUS_DET="PG01" +CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:480,y:800,depth:18,pclk_khz:25000,le:2,ri:93,up:2,lo:93,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PG4" @@ -11,13 +15,8 @@ CONFIG_VIDEO_LCD_RESET="PG11" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_TL059WV5C0=y -CONFIG_AXP_GPIO=y -CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_MMC0_CD_PIN="PG0" -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN5I=y -CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=0 -CONFIG_DM_SERIAL=n +CONFIG_USB_MUSB_SUNXI=y +# CONFIG_DM_SERIAL is not set +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig index 9c6dfd6..011e921 100644 --- a/configs/Wexler_TAB7200_defconfig +++ b/configs/Wexler_TAB7200_defconfig @@ -1,13 +1,11 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200" -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" -CONFIG_VIDEO_LCD_POWER="PH8" -CONFIG_VIDEO_LCD_BL_EN="PH7" -CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_POWER="PH8" +CONFIG_VIDEO_LCD_BL_EN="PH7" +CONFIG_VIDEO_LCD_BL_PWM="PB2" +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI" diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig index 19b8f39..8bdca23 100644 --- a/configs/Wits_Pro_A20_DKT_defconfig +++ b/configs/Wits_Pro_A20_DKT_defconfig @@ -1,16 +1,14 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt" +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN7I=y +CONFIG_DRAM_CLK=384 +CONFIG_VIDEO_VGA=y CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:65000,le:159,ri:160,up:22,lo:15,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y -CONFIG_VIDEO_VGA=y -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=384 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,USB_EHCI" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index b675726..346e689 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -1,30 +1,22 @@ -# The Yones Toptech BD1078 is an A20 based 10" tablet with a 1024x600 lcd -# screen, volume up/down and back buttons, headphones jack, mini hdmi, micro -# usb (otg), micro usb (host), external micro-sd slot and a separate internal -# micro-sd slot. -# -# Also see: http://linux-sunxi.org/Yones_Toptech_BD1078 -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078" -CONFIG_MMC_SUNXI_SLOT_EXTRA=1 +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN7I=y +CONFIG_DRAM_CLK=408 CONFIG_MMC0_CD_PIN="PH1" CONFIG_MMC1_CD_PIN="PH2" CONFIG_MMC1_PINS="PH" -CONFIG_USB_MUSB_SUNXI=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=1 CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:63000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 -CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW=n -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=408 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +# CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set +CONFIG_VIDEO_LCD_PANEL_LVDS=y +CONFIG_USB_MUSB_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" diff --git a/configs/a3m071_defconfig b/configs/a3m071_defconfig index 7971c06..eeaff87 100644 --- a/configs/a3m071_defconfig +++ b/configs/a3m071_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_A3M071=y +CONFIG_SPL=y diff --git a/configs/a4m2k_defconfig b/configs/a4m2k_defconfig index 0410814..15c6411 100644 --- a/configs/a4m2k_defconfig +++ b/configs/a4m2k_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="A4M2K" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_A3M071=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="A4M2K" diff --git a/configs/acadia_defconfig b/configs/acadia_defconfig index 26221ce..4e0d81c 100644 --- a/configs/acadia_defconfig +++ b/configs/acadia_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_ACADIA=y +CONFIG_REGEX=y diff --git a/configs/afeb9260_defconfig b/configs/afeb9260_defconfig deleted file mode 100644 index 694d24d..0000000 --- a/configs/afeb9260_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_AFEB9260=y diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig index e0b058b..624717c 100644 --- a/configs/am335x_boneblack_defconfig +++ b/configs/am335x_boneblack_defconfig @@ -1,6 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM335X_EVM=y CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT" -CONFIG_ARM=y -CONFIG_TARGET_AM335X_EVM=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index e4ffe5f..e805c9d 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -1,11 +1,11 @@ -CONFIG_SPL=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT" CONFIG_ARM=y CONFIG_TARGET_AM335X_EVM=y -CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack" +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT" +CONFIG_OF_CONTROL=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 968d041..f23c0e3 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -1,7 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM335X_EVM=y CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_EXTRA_OPTIONS="NAND" -CONFIG_CONS_INDEX=1 -CONFIG_ARM=y -CONFIG_TARGET_AM335X_EVM=y diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig index 4826057..0f62bbc 100644 --- a/configs/am335x_evm_nor_defconfig +++ b/configs/am335x_evm_nor_defconfig @@ -1,8 +1,7 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM335X_EVM=y +CONFIG_NOR=y CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_EXTRA_OPTIONS="NAND" -CONFIG_CONS_INDEX=1 -CONFIG_ARM=y -CONFIG_TARGET_AM335X_EVM=y -CONFIG_NOR=y diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig index 47ff6cd..1e25d89 100644 --- a/configs/am335x_evm_norboot_defconfig +++ b/configs/am335x_evm_norboot_defconfig @@ -1,4 +1,3 @@ -CONFIG_CONS_INDEX=1 CONFIG_ARM=y CONFIG_TARGET_AM335X_EVM=y CONFIG_NOR=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index 7a8415a..5c992e1 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -1,7 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM335X_EVM=y CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT" -CONFIG_CONS_INDEX=1 -CONFIG_ARM=y -CONFIG_TARGET_AM335X_EVM=y diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig index 4c8418a..0cc86e3 100644 --- a/configs/am335x_evm_usbspl_defconfig +++ b/configs/am335x_evm_usbspl_defconfig @@ -1,7 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM335X_EVM=y CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT" -CONFIG_CONS_INDEX=1 -CONFIG_ARM=y -CONFIG_TARGET_AM335X_EVM=y diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig index 7ff0a13..8b212c6 100644 --- a/configs/am335x_igep0033_defconfig +++ b/configs/am335x_igep0033_defconfig @@ -1,5 +1,5 @@ +CONFIG_ARM=y +CONFIG_TARGET_AM335X_IGEP0033=y CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_ARM=y -CONFIG_TARGET_AM335X_IGEP0033=y diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig index cd16724..abdd345 100644 --- a/configs/am3517_crane_defconfig +++ b/configs/am3517_crane_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_AM3517_CRANE=y +CONFIG_SPL=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index daf1ae4..d084f77 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_AM3517_EVM=y +CONFIG_SPL=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 14bda69..46d2fd2 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" CONFIG_ARM=y CONFIG_TARGET_AM43XX_EVM=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index 281a215..a0a18f2 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT" CONFIG_ARM=y CONFIG_TARGET_AM43XX_EVM=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT" diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig index b81fbff..87f6986 100644 --- a/configs/apf27_defconfig +++ b/configs/apf27_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_APF27=y +CONFIG_SPL=y diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig index 3bb8c48..2d78654 100644 --- a/configs/apx4devkit_defconfig +++ b/configs/apx4devkit_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_APX4DEVKIT=y +CONFIG_SPL=y diff --git a/configs/arcangel4-be_defconfig b/configs/arcangel4-be_defconfig index 36ea6be..f7ecfdd 100644 --- a/configs/arcangel4-be_defconfig +++ b/configs/arcangel4-be_defconfig @@ -1,10 +1,10 @@ CONFIG_ARC=y CONFIG_CPU_BIG_ENDIAN=y CONFIG_TARGET_ARCANGEL4=y -CONFIG_DM=y +CONFIG_SYS_CLK_FREQ=70000000 CONFIG_DM_SERIAL=y -CONFIG_DEFAULT_DEVICE_TREE="arcangel4" CONFIG_SYS_TEXT_BASE=0x81000000 -CONFIG_SYS_CLK_FREQ=70000000 +CONFIG_DEFAULT_DEVICE_TREE="arcangel4" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y +CONFIG_DM=y diff --git a/configs/arcangel4_defconfig b/configs/arcangel4_defconfig index 75a91c8..12dc3f2 100644 --- a/configs/arcangel4_defconfig +++ b/configs/arcangel4_defconfig @@ -1,9 +1,9 @@ CONFIG_ARC=y CONFIG_TARGET_ARCANGEL4=y -CONFIG_DM=y +CONFIG_SYS_CLK_FREQ=70000000 CONFIG_DM_SERIAL=y -CONFIG_DEFAULT_DEVICE_TREE="arcangel4" CONFIG_SYS_TEXT_BASE=0x81000000 -CONFIG_SYS_CLK_FREQ=70000000 +CONFIG_DEFAULT_DEVICE_TREE="arcangel4" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y +CONFIG_DM=y diff --git a/configs/arches_defconfig b/configs/arches_defconfig index 30c6932..9084a3a 100644 --- a/configs/arches_defconfig +++ b/configs/arches_defconfig @@ -4,4 +4,3 @@ CONFIG_TARGET_CANYONLANDS=y CONFIG_ARCHES=y CONFIG_DEFAULT_DEVICE_TREE="arches" CONFIG_OF_CONTROL=y -CONFIG_OF_SEPARATE=y diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig index 6541865..162e739 100644 --- a/configs/aristainetos_defconfig +++ b/configs/aristainetos_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL" CONFIG_ARM=y CONFIG_TARGET_ARISTAINETOS=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL" diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig index 21d5f4a..e48003a 100644 --- a/configs/arndale_defconfig +++ b/configs/arndale_defconfig @@ -1,10 +1,10 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_ARNDALE=y CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale" -CONFIG_SOUND=y +CONFIG_SPL=y CONFIG_CMD_SOUND=y +CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y CONFIG_SOUND_MAX98095=y diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig index 64f5e54..3573d39 100644 --- a/configs/at91rm9200ek_ram_defconfig +++ b/configs/at91rm9200ek_ram_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91RM9200EK=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig index 46ce31b..052f8af 100644 --- a/configs/at91sam9260ek_dataflash_cs0_defconfig +++ b/configs/at91sam9260ek_dataflash_cs0_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0" diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig index 9fd40df..f654294 100644 --- a/configs/at91sam9260ek_dataflash_cs1_defconfig +++ b/configs/at91sam9260ek_dataflash_cs1_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1" diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig index 98adab2..1b2d232 100644 --- a/configs/at91sam9260ek_nandflash_defconfig +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH" diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig index 9c311a3..d8299da 100644 --- a/configs/at91sam9261ek_dataflash_cs0_defconfig +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0" diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig index 3711fe4..1eb0e78 100644 --- a/configs/at91sam9261ek_dataflash_cs3_defconfig +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3" diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index 503f760..d14e5a9 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH" diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index 15925b6..b272745 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index 15925b6..b272745 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index 457fb1a..05e6e8c 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index e49b177..3318ad7 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH" diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index fcd1764..04efa1b 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH" diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig index 8334122..bdd4e1f 100644 --- a/configs/at91sam9g10ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0" diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig index 25626ce..809d803 100644 --- a/configs/at91sam9g10ek_dataflash_cs3_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3" diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig index 7ae0794..9c0b4f5 100644 --- a/configs/at91sam9g10ek_nandflash_defconfig +++ b/configs/at91sam9g10ek_nandflash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH" diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig index e277557..4441e09 100644 --- a/configs/at91sam9g20ek_2mmc_defconfig +++ b/configs/at91sam9g20ek_2mmc_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC" diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig index 29219fb..49be950 100644 --- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH" diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig index 4587f49..0b259ed 100644 --- a/configs/at91sam9g20ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0" diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig index c9fcc6e..974138c 100644 --- a/configs/at91sam9g20ek_dataflash_cs1_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1" diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig index 1d60e0a..9cac5f4 100644 --- a/configs/at91sam9g20ek_nandflash_defconfig +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH" diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index f3e1ebe..201d0c4 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9M10G45EK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC" diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index 5e0b16e..844acd4 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9M10G45EK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH" diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index 4fc417a..d9cf7d1 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9N12EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC" diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index 11b42d4..9f0ceb9 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9N12EK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH" diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index 5426bcd..81650c5 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9N12EK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH" diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig index 174bcc4..967d28a 100644 --- a/configs/at91sam9rlek_dataflash_defconfig +++ b/configs/at91sam9rlek_dataflash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH" CONFIG_HUSH_PARSER=y diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig index 41a2821..95a71df 100644 --- a/configs/at91sam9rlek_mmc_defconfig +++ b/configs/at91sam9rlek_mmc_defconfig @@ -1,5 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC" CONFIG_HUSH_PARSER=y diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig index fdb2d6b..885214d 100644 --- a/configs/at91sam9rlek_nandflash_defconfig +++ b/configs/at91sam9rlek_nandflash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH" CONFIG_HUSH_PARSER=y diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index 15b5fa9..91bfd99 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH" diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index c8096c2..d915382 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC" diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index 6eea1af..5d0c13f 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH" diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 7ef1534..c2d7fd4 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH" diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig index 1449791..e7ee6c6 100644 --- a/configs/at91sam9xeek_dataflash_cs0_defconfig +++ b/configs/at91sam9xeek_dataflash_cs0_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0" diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig index b465064..0512f06 100644 --- a/configs/at91sam9xeek_dataflash_cs1_defconfig +++ b/configs/at91sam9xeek_dataflash_cs1_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1" diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig index 7e73d48..2e3c132 100644 --- a/configs/at91sam9xeek_nandflash_defconfig +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH" diff --git a/configs/axm_defconfig b/configs/axm_defconfig index f78434e..a1d9f1d 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_TAURUS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM" diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index c97628d..d33cc00 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -2,8 +2,8 @@ CONFIG_ARC=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARC_CACHE_LINE_SHIFT=5 CONFIG_TARGET_AXS101=y -CONFIG_SYS_TEXT_BASE=0x81000000 CONFIG_SYS_CLK_FREQ=750000000 -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index e92fd7c..d30088e 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -1,8 +1,8 @@ CONFIG_ARC=y CONFIG_ISA_ARCV2=y CONFIG_TARGET_AXS101=y -CONFIG_SYS_TEXT_BASE=0x81000000 CONFIG_SYS_CLK_FREQ=50000000 -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index 9909a94..f2ab415 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -1,10 +1,9 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox" -CONFIG_USB2_VBUS_PIN="PH12" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=384 -CONFIG_DRAM_ZQ=123 CONFIG_DRAM_EMR1=4 +CONFIG_USB2_VBUS_PIN="PH12" +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI" diff --git a/configs/bamboo_defconfig b/configs/bamboo_defconfig index 1d66807..df4adb6 100644 --- a/configs/bamboo_defconfig +++ b/configs/bamboo_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_BAMBOO=y +CONFIG_REGEX=y diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig index f8c9f03..ff2144f 100644 --- a/configs/bcm11130_defconfig +++ b/configs/bcm11130_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0" CONFIG_ARM=y CONFIG_TARGET_BCM28155_AP=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0" diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig index 39cb709..a21e623 100644 --- a/configs/bcm11130_nand_defconfig +++ b/configs/bcm11130_nand_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_ARM=y CONFIG_TARGET_BCM28155_AP=y +CONFIG_SYS_EXTRA_OPTIONS="NAND" diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig index 94b791c..3ab05f6 100644 --- a/configs/bcm28155_w1d_defconfig +++ b/configs/bcm28155_w1d_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC" CONFIG_ARM=y CONFIG_TARGET_BCM28155_AP=y +CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC" diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig index 6f5c154..a650507 100644 --- a/configs/bcm911360_entphn-ns_defconfig +++ b/configs/bcm911360_entphn-ns_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC" CONFIG_ARM=y CONFIG_TARGET_BCMCYGNUS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC" diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig index 37b5846..0f9397f 100644 --- a/configs/bcm911360_entphn_defconfig +++ b/configs/bcm911360_entphn_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000" CONFIG_ARM=y CONFIG_TARGET_BCMCYGNUS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000" diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig index 527e407..0eedc35 100644 --- a/configs/bcm911360k_defconfig +++ b/configs/bcm911360k_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" CONFIG_ARM=y CONFIG_TARGET_BCMCYGNUS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig index 0e3aaa7..5d3aee1 100644 --- a/configs/bcm958300k-ns_defconfig +++ b/configs/bcm958300k-ns_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC" CONFIG_ARM=y CONFIG_TARGET_BCMCYGNUS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC" diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig index 527e407..0eedc35 100644 --- a/configs/bcm958300k_defconfig +++ b/configs/bcm958300k_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" CONFIG_ARM=y CONFIG_TARGET_BCMCYGNUS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig index 527e407..0eedc35 100644 --- a/configs/bcm958305k_defconfig +++ b/configs/bcm958305k_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" CONFIG_ARM=y CONFIG_TARGET_BCMCYGNUS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig index 7c86300..bb3236d 100644 --- a/configs/bcm958622hr_defconfig +++ b/configs/bcm958622hr_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000" CONFIG_ARM=y CONFIG_TARGET_BCMNSP=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000" diff --git a/configs/beagle_x15_defconfig b/configs/beagle_x15_defconfig index 5bb8433..7199468 100644 --- a/configs/beagle_x15_defconfig +++ b/configs/beagle_x15_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" CONFIG_ARM=y CONFIG_OMAP54XX=y CONFIG_TARGET_BEAGLE_X15=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig index e250e10..3dd8013 100644 --- a/configs/bf527-ezkit-v2_defconfig +++ b/configs/bf527-ezkit-v2_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1" CONFIG_BLACKFIN=y CONFIG_TARGET_BF527_EZKIT=y +CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1" CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf609-ezkit_defconfig b/configs/bf609-ezkit_defconfig index 96f746e..d947a09 100644 --- a/configs/bf609-ezkit_defconfig +++ b/configs/bf609-ezkit_defconfig @@ -1,5 +1,5 @@ CONFIG_BLACKFIN=y +CONFIG_NET=y +CONFIG_NETDEVICES=y CONFIG_TARGET_BF609_EZKIT=y CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y -CONFIG_NET=y diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig index bc873bed..27c6e11 100644 --- a/configs/bg0900_defconfig +++ b/configs/bg0900_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_BG0900=y +CONFIG_SPL=y diff --git a/configs/bubinga_defconfig b/configs/bubinga_defconfig index 65ea4d1..532448d 100644 --- a/configs/bubinga_defconfig +++ b/configs/bubinga_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_BUBINGA=y +CONFIG_REGEX=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 6e4a389..bdce6aa 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="CADDY2" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_VME8349=y +CONFIG_SYS_EXTRA_OPTIONS="CADDY2" diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig index 753d2a5..c9d2917 100644 --- a/configs/cairo_defconfig +++ b/configs/cairo_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_CAIRO=y +CONFIG_SPL=y diff --git a/configs/cam5200_defconfig b/configs/cam5200_defconfig index d3de17b..33db80b 100644 --- a/configs/cam5200_defconfig +++ b/configs/cam5200_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y +CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B" diff --git a/configs/cam5200_niosflash_defconfig b/configs/cam5200_niosflash_defconfig index a375e13..c13b9bf 100644 --- a/configs/cam5200_niosflash_defconfig +++ b/configs/cam5200_niosflash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y +CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH" diff --git a/configs/cam_enc_4xx_defconfig b/configs/cam_enc_4xx_defconfig index bf6b7f1..89bffa0 100644 --- a/configs/cam_enc_4xx_defconfig +++ b/configs/cam_enc_4xx_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_CAM_ENC_4XX=y +CONFIG_SPL=y diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig index 44d4fbd..e936d7b 100644 --- a/configs/canyonlands_defconfig +++ b/configs/canyonlands_defconfig @@ -5,3 +5,4 @@ CONFIG_CANYONLANDS=y CONFIG_DEFAULT_DEVICE_TREE="canyonlands" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y +CONFIG_REGEX=y diff --git a/configs/cgtqmx6qeval_defconfig b/configs/cgtqmx6qeval_defconfig index 4eba4be..5a20f22 100644 --- a/configs/cgtqmx6qeval_defconfig +++ b/configs/cgtqmx6qeval_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_CGTQMX6EVAL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q" diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 81222d2..3d2bdf6 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -1,13 +1,10 @@ CONFIG_X86=y CONFIG_VENDOR_GOOGLE=y -CONFIG_TARGET_CHROMEBOOK_LINK=y -CONFIG_OF_CONTROL=y -CONFIG_OF_SEPARATE=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" +CONFIG_TARGET_CHROMEBOOK_LINK=y CONFIG_HAVE_MRC=y -CONFIG_SMM_TSEG_SIZE=0x800000 -CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_OF_CONTROL=y CONFIG_DM_PCI=y -CONFIG_CROS_EC_LPC=y +CONFIG_VIDEO_VESA=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index 91189c9..4bbce09 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -1,12 +1,10 @@ CONFIG_X86=y CONFIG_VENDOR_GOOGLE=y -CONFIG_TARGET_CHROMEBOX_PANTHER=y -CONFIG_OF_CONTROL=y -CONFIG_OF_SEPARATE=y CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther" +CONFIG_TARGET_CHROMEBOX_PANTHER=y CONFIG_HAVE_MRC=y -CONFIG_SMM_TSEG_SIZE=0x800000 -CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_OF_CONTROL=y CONFIG_DM_PCI=y +CONFIG_VIDEO_VESA=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index c83a0e8..18a7157 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL" CONFIG_ARM=y CONFIG_TARGET_CM_FX6=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL" diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig index d189799..a694bb5 100644 --- a/configs/cm_t335_defconfig +++ b/configs/cm_t335_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_CM_T335=y +CONFIG_SPL=y diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig index 2d05ffb..da18e5f 100644 --- a/configs/cm_t3517_defconfig +++ b/configs/cm_t3517_defconfig @@ -1,4 +1,3 @@ -CONFIG_SPL=n CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_CM_T3517=y diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig index 63a85b4..a4e0daa 100644 --- a/configs/cm_t35_defconfig +++ b/configs/cm_t35_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_CM_T35=y +CONFIG_SPL=y diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig index dda8abd..aa7eedb 100644 --- a/configs/cm_t54_defconfig +++ b/configs/cm_t54_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP54XX=y CONFIG_TARGET_CM_T54=y +CONFIG_SPL=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index cef5a9e..0df337c 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" CONFIG_ARM=y CONFIG_TARGET_COLIBRI_VF=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig index 661e85c..2943298 100644 --- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig +++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD,DEVELOP" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_CONTROLCENTERD=y +CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD,DEVELOP" diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig index 76ab9d3..1c18315 100644 --- a/configs/controlcenterd_36BIT_SDCARD_defconfig +++ b/configs/controlcenterd_36BIT_SDCARD_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_CONTROLCENTERD=y +CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD" diff --git a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig index c8695ab..bfd6449 100644 --- a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig +++ b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig @@ -1,5 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_CONTROLCENTERD=y +CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP" # CONFIG_CMD_BOOTM is not set diff --git a/configs/controlcenterd_TRAILBLAZER_defconfig b/configs/controlcenterd_TRAILBLAZER_defconfig index 730b96e..17ee3a8 100644 --- a/configs/controlcenterd_TRAILBLAZER_defconfig +++ b/configs/controlcenterd_TRAILBLAZER_defconfig @@ -1,5 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_CONTROLCENTERD=y +CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH" # CONFIG_CMD_BOOTM is not set diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig index 799853f..66f94d0 100644 --- a/configs/coreboot-x86_defconfig +++ b/configs/coreboot-x86_defconfig @@ -1,5 +1,4 @@ CONFIG_X86=y -CONFIG_VENDOR_COREBOOT=y CONFIG_TARGET_COREBOOT=y CONFIG_OF_CONTROL=y CONFIG_DM_PCI=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index 0427e9e..06e5a28 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_CORVUS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH" diff --git a/configs/cpu9260_128M_defconfig b/configs/cpu9260_128M_defconfig index 6fe59dd..e59356c 100644 --- a/configs/cpu9260_128M_defconfig +++ b/configs/cpu9260_128M_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_CPU9260=y +CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M" diff --git a/configs/cpu9260_defconfig b/configs/cpu9260_defconfig index 63e7c73..8b6c543 100644 --- a/configs/cpu9260_defconfig +++ b/configs/cpu9260_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="CPU9260" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_CPU9260=y +CONFIG_SYS_EXTRA_OPTIONS="CPU9260" diff --git a/configs/cpu9260_nand_128M_defconfig b/configs/cpu9260_nand_128M_defconfig index 11c5bce..47f885b 100644 --- a/configs/cpu9260_nand_128M_defconfig +++ b/configs/cpu9260_nand_128M_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M,NANDBOOT" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_CPU9260=y +CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M,NANDBOOT" diff --git a/configs/cpu9260_nand_defconfig b/configs/cpu9260_nand_defconfig index d4d6ec9..c6ff773 100644 --- a/configs/cpu9260_nand_defconfig +++ b/configs/cpu9260_nand_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="CPU9260,NANDBOOT" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_CPU9260=y +CONFIG_SYS_EXTRA_OPTIONS="CPU9260,NANDBOOT" diff --git a/configs/cpu9G20_128M_defconfig b/configs/cpu9G20_128M_defconfig index 8d33f08..aa6a335 100644 --- a/configs/cpu9G20_128M_defconfig +++ b/configs/cpu9G20_128M_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_CPU9260=y +CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M" diff --git a/configs/cpu9G20_defconfig b/configs/cpu9G20_defconfig index fcfebb8..b63841f 100644 --- a/configs/cpu9G20_defconfig +++ b/configs/cpu9G20_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="CPU9G20" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_CPU9260=y +CONFIG_SYS_EXTRA_OPTIONS="CPU9G20" diff --git a/configs/cpu9G20_nand_128M_defconfig b/configs/cpu9G20_nand_128M_defconfig index 315042d..2871f31 100644 --- a/configs/cpu9G20_nand_128M_defconfig +++ b/configs/cpu9G20_nand_128M_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M,NANDBOOT" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_CPU9260=y +CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M,NANDBOOT" diff --git a/configs/cpu9G20_nand_defconfig b/configs/cpu9G20_nand_defconfig index c405c50..b0ef7d4 100644 --- a/configs/cpu9G20_nand_defconfig +++ b/configs/cpu9G20_nand_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,NANDBOOT" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_CPU9260=y +CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,NANDBOOT" diff --git a/configs/cpuat91_ram_defconfig b/configs/cpuat91_ram_defconfig index 2759192..408ef62 100644 --- a/configs/cpuat91_ram_defconfig +++ b/configs/cpuat91_ram_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_CPUAT91=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 61d1fcc..9804ea7 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -1,7 +1,6 @@ CONFIG_X86=y CONFIG_VENDOR_INTEL=y -CONFIG_TARGET_CROWNBAY=y -CONFIG_OF_CONTROL=y -CONFIG_OF_SEPARATE=y CONFIG_DEFAULT_DEVICE_TREE="crownbay" +CONFIG_TARGET_CROWNBAY=y CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_OF_CONTROL=y diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index c459f4d..e54dcf4 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NET2BIG_V2=y +CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2" diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig index 57c1494..092696e 100644 --- a/configs/da850_am18xxevm_defconfig +++ b/configs/da850_am18xxevm_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50" CONFIG_ARM=y CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_DA850EVM=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50" diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 5891d15..f3e3e9a 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH" CONFIG_ARM=y CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_DA850EVM=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH" diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 25c303c..24148da 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT" CONFIG_ARM=y CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_DA850EVM=y +CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT" diff --git a/configs/davinci_dm6467Tevm_defconfig b/configs/davinci_dm6467Tevm_defconfig index 4523d4a..5671c38 100644 --- a/configs/davinci_dm6467Tevm_defconfig +++ b/configs/davinci_dm6467Tevm_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000" CONFIG_ARM=y CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_DAVINCI_DM6467EVM=y +CONFIG_SYS_EXTRA_OPTIONS="DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000" diff --git a/configs/davinci_dm6467evm_defconfig b/configs/davinci_dm6467evm_defconfig index 5208257..f9741a1 100644 --- a/configs/davinci_dm6467evm_defconfig +++ b/configs/davinci_dm6467evm_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="REFCLK_FREQ=27000000" CONFIG_ARM=y CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_DAVINCI_DM6467EVM=y +CONFIG_SYS_EXTRA_OPTIONS="REFCLK_FREQ=27000000" diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 8bdad0f..07b9183 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_DB_MV784MP_GP=y +CONFIG_SPL=y diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig index aa4d338..8692c0d 100644 --- a/configs/dbau1000_defconfig +++ b/configs/dbau1000_defconfig @@ -1,4 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="DBAU1000" CONFIG_MIPS=y CONFIG_TARGET_DBAU1X00=y -CONFIG_SYS_BIG_ENDIAN=y +CONFIG_SYS_EXTRA_OPTIONS="DBAU1000" diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig index aac9f03..9c16424 100644 --- a/configs/dbau1100_defconfig +++ b/configs/dbau1100_defconfig @@ -1,4 +1,3 @@ CONFIG_MIPS=y CONFIG_TARGET_DBAU1X00=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_DBAU1100=y diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig index d96de13..d665d8e 100644 --- a/configs/dbau1500_defconfig +++ b/configs/dbau1500_defconfig @@ -1,4 +1,3 @@ CONFIG_MIPS=y CONFIG_TARGET_DBAU1X00=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_DBAU1500=y diff --git a/configs/dbau1550_defconfig b/configs/dbau1550_defconfig index a2dfe18..f27fb23 100644 --- a/configs/dbau1550_defconfig +++ b/configs/dbau1550_defconfig @@ -1,4 +1,3 @@ CONFIG_MIPS=y CONFIG_TARGET_DBAU1X00=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_DBAU1550=y diff --git a/configs/dbau1550_el_defconfig b/configs/dbau1550_el_defconfig index 767326f..3b1d74d 100644 --- a/configs/dbau1550_el_defconfig +++ b/configs/dbau1550_el_defconfig @@ -1,4 +1,4 @@ CONFIG_MIPS=y CONFIG_TARGET_DBAU1X00=y -CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DBAU1550=y +CONFIG_SYS_LITTLE_ENDIAN=y diff --git a/configs/devconcenter_defconfig b/configs/devconcenter_defconfig index 7f82d7d..ecf766e 100644 --- a/configs/devconcenter_defconfig +++ b/configs/devconcenter_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_INTIP=y +CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER" diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index 84a1a25..9f3bc18 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_DEVKIT8000=y +CONFIG_SPL=y diff --git a/configs/digsy_mtc_RAMBOOT_defconfig b/configs/digsy_mtc_RAMBOOT_defconfig index a1e765b..fa7fd06 100644 --- a/configs/digsy_mtc_RAMBOOT_defconfig +++ b/configs/digsy_mtc_RAMBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_DIGSY_MTC=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000" diff --git a/configs/digsy_mtc_rev5_RAMBOOT_defconfig b/configs/digsy_mtc_rev5_RAMBOOT_defconfig index d356174..be297fe 100644 --- a/configs/digsy_mtc_rev5_RAMBOOT_defconfig +++ b/configs/digsy_mtc_rev5_RAMBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000,DIGSY_REV5" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_DIGSY_MTC=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000,DIGSY_REV5" diff --git a/configs/digsy_mtc_rev5_defconfig b/configs/digsy_mtc_rev5_defconfig index f66f86f..12f82da 100644 --- a/configs/digsy_mtc_rev5_defconfig +++ b/configs/digsy_mtc_rev5_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="DIGSY_REV5" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_DIGSY_MTC=y +CONFIG_SYS_EXTRA_OPTIONS="DIGSY_REV5" diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig index 1d2a571..2f508c3 100644 --- a/configs/dlvision-10g_defconfig +++ b/configs/dlvision-10g_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_DLVISION_10G=y +CONFIG_REGEX=y diff --git a/configs/dlvision_defconfig b/configs/dlvision_defconfig index c0317dc..3149cb1 100644 --- a/configs/dlvision_defconfig +++ b/configs/dlvision_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_DLVISION=y +CONFIG_REGEX=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 20a1fad..520f35f 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1" CONFIG_ARM=y CONFIG_OMAP54XX=y CONFIG_TARGET_DRA7XX_EVM=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1" diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig index 7d1ea9e..04e0532 100644 --- a/configs/dra7xx_evm_qspiboot_defconfig +++ b/configs/dra7xx_evm_qspiboot_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,QSPI_BOOT" CONFIG_ARM=y CONFIG_OMAP54XX=y CONFIG_TARGET_DRA7XX_EVM=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,QSPI_BOOT" diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig index 2d2dcba..32830fb 100644 --- a/configs/dra7xx_evm_uart3_defconfig +++ b/configs/dra7xx_evm_uart3_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3,SPL_YMODEM_SUPPORT" CONFIG_ARM=y CONFIG_OMAP54XX=y CONFIG_TARGET_DRA7XX_EVM=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3,SPL_YMODEM_SUPPORT" diff --git a/configs/draco_defconfig b/configs/draco_defconfig index fba7bf1..ebd6b08 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_DRACO=y +CONFIG_SPL=y diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig index c0bf27d..de89ec9 100644 --- a/configs/duovero_defconfig +++ b/configs/duovero_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP44XX=y CONFIG_TARGET_DUOVERO=y +CONFIG_SPL=y diff --git a/configs/dxr2_defconfig b/configs/dxr2_defconfig index e0f577f..c6530ed 100644 --- a/configs/dxr2_defconfig +++ b/configs/dxr2_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_DXR2=y +CONFIG_SPL=y diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index f69aa53..7c7f188 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400" CONFIG_M68K=y CONFIG_TARGET_EB_CPU5282=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400" diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index b590f25..095d554 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418" CONFIG_M68K=y CONFIG_TARGET_EB_CPU5282=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418" diff --git a/configs/eb_cpux9k2_ram_defconfig b/configs/eb_cpux9k2_ram_defconfig index 4393ccc..93acc13 100644 --- a/configs/eb_cpux9k2_ram_defconfig +++ b/configs/eb_cpux9k2_ram_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_EB_CPUX9K2=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" diff --git a/configs/ebony_defconfig b/configs/ebony_defconfig index db93555..bf2dab6 100644 --- a/configs/ebony_defconfig +++ b/configs/ebony_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_EBONY=y +CONFIG_REGEX=y diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig index 8587c51..230bd87 100644 --- a/configs/eco5pk_defconfig +++ b/configs/eco5pk_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_ECO5PK=y +CONFIG_SPL=y diff --git a/configs/edb9315a_defconfig b/configs/edb9315a_defconfig index e92daf6..0d4bb2d 100644 --- a/configs/edb9315a_defconfig +++ b/configs/edb9315a_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a" CONFIG_ARM=y CONFIG_TARGET_EDB93XX=y +CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a" diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig index 2a74f76..1476d4d 100644 --- a/configs/edminiv2_defconfig +++ b/configs/edminiv2_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ORION5X=y CONFIG_TARGET_EDMINIV2=y +CONFIG_SPL=y diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig index 9a3d40a..5fc79ca 100644 --- a/configs/ethernut5_defconfig +++ b/configs/ethernut5_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_ETHERNUT5=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE" diff --git a/configs/fo300_defconfig b/configs/fo300_defconfig index 6492b4b..05068d4 100644 --- a/configs/fo300_defconfig +++ b/configs/fo300_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="FO300" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_TQM5200=y +CONFIG_SYS_EXTRA_OPTIONS="FO300" diff --git a/configs/forfun_q88db_defconfig b/configs/forfun_q88db_defconfig index 7722915..fc7ce6a 100644 --- a/configs/forfun_q88db_defconfig +++ b/configs/forfun_q88db_defconfig @@ -1,18 +1,15 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-forfun-q88db" -CONFIG_USB_MUSB_SUNXI=y +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_CLK=384 CONFIG_USB0_VBUS_PIN="PG12" CONFIG_USB0_VBUS_DET="PG1" +CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_AXP_GPIO=y -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN5I=y -CONFIG_DRAM_CLK=384 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=4 - +CONFIG_USB_MUSB_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-forfun-q88db" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" diff --git a/configs/fx12mm_defconfig b/configs/fx12mm_defconfig index 9900a54..a84dc65 100644 --- a/configs/fx12mm_defconfig +++ b/configs/fx12mm_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_FX12MM=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o" diff --git a/configs/fx12mm_flash_defconfig b/configs/fx12mm_flash_defconfig index 5a0587f..cd28f33 100644 --- a/configs/fx12mm_flash_defconfig +++ b/configs/fx12mm_flash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_FX12MM=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o" diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 1a54ba5..7de7749 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -1,9 +1,8 @@ CONFIG_X86=y +CONFIG_NET=y +CONFIG_NETDEVICES=y CONFIG_VENDOR_INTEL=y +CONFIG_DEFAULT_DEVICE_TREE="galileo" CONFIG_TARGET_GALILEO=y CONFIG_OF_CONTROL=y -CONFIG_OF_SEPARATE=y -CONFIG_DEFAULT_DEVICE_TREE="galileo" CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y -CONFIG_NET=y diff --git a/configs/gdppc440etx_defconfig b/configs/gdppc440etx_defconfig index 1097b9c..5aa579a 100644 --- a/configs/gdppc440etx_defconfig +++ b/configs/gdppc440etx_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_GDPPC440ETX=y +CONFIG_REGEX=y diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig index f8363b2..98bcaf4 100644 --- a/configs/glacier_ramboot_defconfig +++ b/configs/glacier_ramboot_defconfig @@ -1,8 +1,8 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_CANYONLANDS=y CONFIG_GLACIER=y CONFIG_DEFAULT_DEVICE_TREE="glacier" +CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/gr_cpci_ax2000_defconfig b/configs/gr_cpci_ax2000_defconfig index b59d077..73ac213 100644 --- a/configs/gr_cpci_ax2000_defconfig +++ b/configs/gr_cpci_ax2000_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SPARC=y CONFIG_TARGET_GR_CPCI_AX2000=y +CONFIG_SYS_TEXT_BASE=0x00000000 diff --git a/configs/gr_ep2s60_defconfig b/configs/gr_ep2s60_defconfig index 2c69efa..a59f0ad 100644 --- a/configs/gr_ep2s60_defconfig +++ b/configs/gr_ep2s60_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SPARC=y CONFIG_TARGET_GR_EP2S60=y +CONFIG_SYS_TEXT_BASE=0x00000000 diff --git a/configs/gr_xc3s_1500_defconfig b/configs/gr_xc3s_1500_defconfig index fecdd25..257759f 100644 --- a/configs/gr_xc3s_1500_defconfig +++ b/configs/gr_xc3s_1500_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SPARC=y CONFIG_TARGET_GR_XC3S_1500=y +CONFIG_SYS_TEXT_BASE=0x00000000 diff --git a/configs/grsim_defconfig b/configs/grsim_defconfig index e3ffd69..43d232c 100644 --- a/configs/grsim_defconfig +++ b/configs/grsim_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SPARC=y CONFIG_TARGET_GRSIM=y +CONFIG_SYS_TEXT_BASE=0x00000000 diff --git a/configs/grsim_leon2_defconfig b/configs/grsim_leon2_defconfig index 6090e34..f28ad4a 100644 --- a/configs/grsim_leon2_defconfig +++ b/configs/grsim_leon2_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SPARC=y CONFIG_TARGET_GRSIM_LEON2=y +CONFIG_SYS_TEXT_BASE=0x00000000 diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig index d6bbdc1..2d6552f 100644 --- a/configs/gwventana_defconfig +++ b/configs/gwventana_defconfig @@ -1,5 +1,7 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" CONFIG_ARM=y CONFIG_TARGET_GW_VENTANA=y CONFIG_SYS_MALLOC_F=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x18000000 diff --git a/configs/haleakala_defconfig b/configs/haleakala_defconfig index 7e63116..81e3398 100644 --- a/configs/haleakala_defconfig +++ b/configs/haleakala_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_KILAUEA=y +CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA" diff --git a/configs/hummingboard_solo_defconfig b/configs/hummingboard_solo_defconfig deleted file mode 100644 index 600fa00..0000000 --- a/configs/hummingboard_solo_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512" -CONFIG_ARM=y -CONFIG_TARGET_HUMMINGBOARD=y diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig index e579fde..c8ccf45 100644 --- a/configs/i12-tvbox_defconfig +++ b/configs/i12-tvbox_defconfig @@ -1,10 +1,8 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI" CONFIG_ETH_DESIGNWARE=y diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index 0ae11a7..e807aeb 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -1,20 +1,17 @@ -# The iNet 3F is an A10 tablet with 1GiB RAM and a 1024x768 screen. -# Also see: http://linux-sunxi.org/INet_3F -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f" +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN4I=y +CONFIG_DRAM_CLK=432 +CONFIG_DRAM_EMR1=4 CONFIG_MMC0_CD_PIN="PH1" -CONFIG_USB_MUSB_SUNXI=y CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0" -CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y -CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=4 +CONFIG_VIDEO_LCD_PANEL_LVDS=y +CONFIG_USB_MUSB_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index 204f887..eaf7c5a 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -1,19 +1,17 @@ -# The iNet 3W is an A10 tablet with 1GiB RAM and a 1024x768 screen. -# Also see: http://linux-sunxi.org/INet_3W -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w" +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN4I=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_ZQ=127 +CONFIG_DRAM_EMR1=4 CONFIG_MMC0_CD_PIN="PH20" -CONFIG_USB_MUSB_SUNXI=y CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:65000,le:159,ri:160,up:22,lo:15,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN4I=y -CONFIG_DRAM_CLK=408 -CONFIG_DRAM_ZQ=127 -CONFIG_DRAM_EMR1=4 +CONFIG_USB_MUSB_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index 0646f9f..017a87a 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -1,17 +1,15 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs" -CONFIG_USB_MUSB_SUNXI=y +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_CLK=408 CONFIG_USB0_VBUS_PIN="PG12" CONFIG_USB0_VBUS_DET="PG1" +CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_AXP_GPIO=y -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN5I=y -CONFIG_DRAM_CLK=408 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=4 +CONFIG_USB_MUSB_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" diff --git a/configs/icon_defconfig b/configs/icon_defconfig index 771a093..caf7c23 100644 --- a/configs/icon_defconfig +++ b/configs/icon_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_ICON=y +CONFIG_REGEX=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 8479cd4..36db73a 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000" CONFIG_PPC=y CONFIG_MPC83xx=y +CONFIG_TARGET_IDS8313=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y -CONFIG_TARGET_IDS8313=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000" diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig index 2bf24a8..950bac5 100644 --- a/configs/igep0020_defconfig +++ b/configs/igep0020_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND" CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_IGEP00X0=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND" diff --git a/configs/igep0020_nand_defconfig b/configs/igep0020_nand_defconfig index c199e58..4686a88 100644 --- a/configs/igep0020_nand_defconfig +++ b/configs/igep0020_nand_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND" CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_IGEP00X0=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND" diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig index 096b662..5e1d43d 100644 --- a/configs/igep0030_defconfig +++ b/configs/igep0030_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND" CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_IGEP00X0=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND" diff --git a/configs/igep0030_nand_defconfig b/configs/igep0030_nand_defconfig index 40c0a55..d92dd44 100644 --- a/configs/igep0030_nand_defconfig +++ b/configs/igep0030_nand_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND" CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_IGEP00X0=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND" diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig index 2f250d2..cf120cd 100644 --- a/configs/igep0032_defconfig +++ b/configs/igep0032_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND" CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_IGEP00X0=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND" diff --git a/configs/ima3-mx53_defconfig b/configs/ima3-mx53_defconfig index c7a9f68..0ada8a1 100644 --- a/configs/ima3-mx53_defconfig +++ b/configs/ima3-mx53_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg" CONFIG_ARM=y CONFIG_TARGET_IMA3_MX53=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg" diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig index 9531952..eca9cdb 100644 --- a/configs/imx31_phycore_eet_defconfig +++ b/configs/imx31_phycore_eet_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX31_PHYCORE_EET" CONFIG_ARM=y CONFIG_TARGET_IMX31_PHYCORE=y +CONFIG_SYS_EXTRA_OPTIONS="IMX31_PHYCORE_EET" diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 1123b52..a8c254d 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NETSPACE_V2=y +CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2" diff --git a/configs/intip_defconfig b/configs/intip_defconfig index d6af774..3aa372f 100644 --- a/configs/intip_defconfig +++ b/configs/intip_defconfig @@ -1,4 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="INTIB" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_INTIP=y +CONFIG_SYS_EXTRA_OPTIONS="INTIB" +CONFIG_REGEX=y diff --git a/configs/io64_defconfig b/configs/io64_defconfig index 1111e54..9c0566e 100644 --- a/configs/io64_defconfig +++ b/configs/io64_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_IO64=y +CONFIG_REGEX=y diff --git a/configs/io_defconfig b/configs/io_defconfig index 959af75..5037ff3 100644 --- a/configs/io_defconfig +++ b/configs/io_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_IO=y +CONFIG_REGEX=y diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig index 6dc8887..72956d4 100644 --- a/configs/iocon_defconfig +++ b/configs/iocon_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_IOCON=y +CONFIG_REGEX=y diff --git a/configs/ipam390_defconfig b/configs/ipam390_defconfig index b42524e..ca17d1b 100644 --- a/configs/ipam390_defconfig +++ b/configs/ipam390_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_IPAM390=y +CONFIG_SPL=y diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index c0d87cc..da41bff 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -1,20 +1,7 @@ -# The Jesurun Q5 has a black plastic casing with the approximate dimensions of -# 100mm x 100mm x 24mm with rounded edges. In terms of hardware it features an -# Allwinner A10 SoC with 1GB RAM and 8GB of NAND flash. The storage capacity -# can be extended up to 32GB with a MicroSD card. The external connectors are: -# 2x USB-A female supporting USB2.0, 3.5mm female jack for audio, HDMI female, -# SPDIF, RJ45 LAN and Power. In addition the device has 1x red LED (hard wired -# to power) and an programmable green led. On the board there is also an -# unpopulated IR receiver and the UART. The device is equipped with an -# AXP209 PMU. -# -# For more details see: http://linux-sunxi.org/Jesurun_Q5 -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI,MACPWR=SUNXI_GPH(19)" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=312 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=0 +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI,MACPWR=SUNXI_GPH(19)" diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 8379b7b..f9edee5 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_KEYSTONE=y CONFIG_TARGET_K2E_EVM=y +CONFIG_SPL=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 764ed5b..fd959f4 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_KEYSTONE=y CONFIG_TARGET_K2HK_EVM=y +CONFIG_SPL=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index efb2c7e..7ab19d5 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_KEYSTONE=y CONFIG_TARGET_K2L_EVM=y +CONFIG_SPL=y diff --git a/configs/katmai_defconfig b/configs/katmai_defconfig index 8492314..02cff2f 100644 --- a/configs/katmai_defconfig +++ b/configs/katmai_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_KATMAI=y +CONFIG_REGEX=y diff --git a/configs/kilauea_defconfig b/configs/kilauea_defconfig index 28021d9..99c78a9 100644 --- a/configs/kilauea_defconfig +++ b/configs/kilauea_defconfig @@ -1,4 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="KILAUEA" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_KILAUEA=y +CONFIG_SYS_EXTRA_OPTIONS="KILAUEA" +CONFIG_REGEX=y diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig index 6a263a6..6b69c6d 100644 --- a/configs/km_kirkwood_128m16_defconfig +++ b/configs/km_kirkwood_128m16_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_KM_KIRKWOOD=y +CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16" diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig index aff76e5..b7ac8ae 100644 --- a/configs/km_kirkwood_defconfig +++ b/configs/km_kirkwood_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_KM_KIRKWOOD=y +CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD" diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig index 13c70a7..825ad69 100644 --- a/configs/km_kirkwood_pci_defconfig +++ b/configs/km_kirkwood_pci_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_KM_KIRKWOOD=y +CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI" diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig index 22a005c..4947d1a 100644 --- a/configs/kmcoge4_defconfig +++ b/configs/kmcoge4_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KMCOGE4" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_KMP204X=y +CONFIG_SYS_EXTRA_OPTIONS="KMCOGE4" diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 80c1f75..a8b5275 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_KM8360=y +CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE" diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig index 78057e4..3d734d8 100644 --- a/configs/kmcoge5un_defconfig +++ b/configs/kmcoge5un_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_KM_KIRKWOOD=y +CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN" diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index f87e347..3374ab0 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KMETER1" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_KM8360=y +CONFIG_SYS_EXTRA_OPTIONS="KMETER1" diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig index 82c1924..fb2c639 100644 --- a/configs/kmlion1_defconfig +++ b/configs/kmlion1_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KMLION1" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_KMP204X=y +CONFIG_SYS_EXTRA_OPTIONS="KMLION1" diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig index d125c52..97e5f32 100644 --- a/configs/kmnusa_defconfig +++ b/configs/kmnusa_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_KM_KIRKWOOD=y +CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA" diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 8195184..11c53b5 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y +CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2" diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig index d40dfd9..181eff1 100644 --- a/configs/kmsugp1_defconfig +++ b/configs/kmsugp1_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_KM_KIRKWOOD=y +CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1" diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 99a9a9b..fd4bb9a 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y +CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5" diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig index 40d0993..bb1bee3 100644 --- a/configs/kmsuv31_defconfig +++ b/configs/kmsuv31_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_KM_KIRKWOOD=y +CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31" diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index dd9c2f2..512d12c 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_SUVD3=y +CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" diff --git a/configs/kwb_defconfig b/configs/kwb_defconfig index b857a4b..cd2e5e6 100644 --- a/configs/kwb_defconfig +++ b/configs/kwb_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" CONFIG_ARM=y CONFIG_TARGET_KWB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" # CONFIG_CMD_CRC32 is not set diff --git a/configs/lcd4_lwmon5_defconfig b/configs/lcd4_lwmon5_defconfig index f11a376..241457a 100644 --- a/configs/lcd4_lwmon5_defconfig +++ b/configs/lcd4_lwmon5_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="LCD4_LWMON5" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_LWMON5=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="LCD4_LWMON5" diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 3c57481..caf1ae2 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index 4d2714b..ac9a4d5 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART" CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART" diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 3cd33fa..6f7227d 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 2b47995..6c4ec8f 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index a59f59e..db81c4c 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_SYS_EXTRA_OPTIONS="LPUART" diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 91c1125..ee3f5ca 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" diff --git a/configs/ls1021aqds_sdcard_defconfig b/configs/ls1021aqds_sdcard_defconfig index 910aa67..61cbc12 100644 --- a/configs/ls1021aqds_sdcard_defconfig +++ b/configs/ls1021aqds_sdcard_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index eeeb0d5..cd6bc80 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 7c80041..1351949 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="LPUART" CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_SYS_EXTRA_OPTIONS="LPUART" diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index c9715a4..57e180d 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" diff --git a/configs/ls1021atwr_sdcard_defconfig b/configs/ls1021atwr_sdcard_defconfig index 3390eac..b9217dd 100644 --- a/configs/ls1021atwr_sdcard_defconfig +++ b/configs/ls1021atwr_sdcard_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" diff --git a/configs/ls2085a_emu_D4_defconfig b/configs/ls2085a_emu_D4_defconfig index 0bc36ed..f6d57b4 100644 --- a/configs/ls2085a_emu_D4_defconfig +++ b/configs/ls2085a_emu_D4_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4" CONFIG_ARM=y CONFIG_TARGET_LS2085A_EMU=y +CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4" diff --git a/configs/ls2085a_emu_defconfig b/configs/ls2085a_emu_defconfig index a2efec3..2858138 100644 --- a/configs/ls2085a_emu_defconfig +++ b/configs/ls2085a_emu_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="EMU" CONFIG_ARM=y CONFIG_TARGET_LS2085A_EMU=y +CONFIG_SYS_EXTRA_OPTIONS="EMU" diff --git a/configs/ls2085a_simu_defconfig b/configs/ls2085a_simu_defconfig index 7563a75..5443bf8 100644 --- a/configs/ls2085a_simu_defconfig +++ b/configs/ls2085a_simu_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SIMU" CONFIG_ARM=y CONFIG_TARGET_LS2085A_SIMU=y +CONFIG_SYS_EXTRA_OPTIONS="SIMU" diff --git a/configs/ls2085aqds_defconfig b/configs/ls2085aqds_defconfig index e3a17a3..d58b783 100644 --- a/configs/ls2085aqds_defconfig +++ b/configs/ls2085aqds_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_ARM=y CONFIG_TARGET_LS2085AQDS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" diff --git a/configs/ls2085aqds_nand_defconfig b/configs/ls2085aqds_nand_defconfig index f84a426..c4ee1ea 100644 --- a/configs/ls2085aqds_nand_defconfig +++ b/configs/ls2085aqds_nand_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_LS2085AQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" diff --git a/configs/ls2085ardb_defconfig b/configs/ls2085ardb_defconfig index 6b64f71..edf89bf 100644 --- a/configs/ls2085ardb_defconfig +++ b/configs/ls2085ardb_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_ARM=y CONFIG_TARGET_LS2085ARDB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" diff --git a/configs/ls2085ardb_nand_defconfig b/configs/ls2085ardb_nand_defconfig index 74812f7..c4f2147 100644 --- a/configs/ls2085ardb_nand_defconfig +++ b/configs/ls2085ardb_nand_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_LS2085ARDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index 8c02fb3..efd8fca 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_LSXL=y +CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2" diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index 86845d1..bb3a80e 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="LSXHL" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_LSXL=y +CONFIG_SYS_EXTRA_OPTIONS="LSXHL" diff --git a/configs/luan_defconfig b/configs/luan_defconfig index d42b4a9..3ca5ad1 100644 --- a/configs/luan_defconfig +++ b/configs/luan_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_LUAN=y +CONFIG_REGEX=y diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig index d902434..9b5e593 100644 --- a/configs/m28evk_defconfig +++ b/configs/m28evk_defconfig @@ -1,3 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_M28EVK=y +CONFIG_SPL=y +CONFIG_REGEX=y diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig index 1d7933b..c918532 100644 --- a/configs/m53evk_defconfig +++ b/configs/m53evk_defconfig @@ -1,4 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg" CONFIG_ARM=y CONFIG_TARGET_M53EVK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg" +CONFIG_REGEX=y diff --git a/configs/makalu_defconfig b/configs/makalu_defconfig index ed9b82d..18c7a20 100644 --- a/configs/makalu_defconfig +++ b/configs/makalu_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_MAKALU=y +CONFIG_REGEX=y diff --git a/configs/malta_defconfig b/configs/malta_defconfig index 5a178a7..1035bd6 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -1,3 +1,2 @@ CONFIG_MIPS=y CONFIG_TARGET_MALTA=y -CONFIG_SYS_BIG_ENDIAN=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index d5c9f08..f54fdd0 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH" CONFIG_ARM=y CONFIG_TARGET_EMBESTMX6BOARDS=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH" diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index 17f1abb..96ff2b9 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_MAXBCM=y +CONFIG_SPL=y diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig index 4abf34d..be3d50b 100644 --- a/configs/mcx_defconfig +++ b/configs/mcx_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_MCX=y +CONFIG_SPL=y diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig index 0430d58..de1d055 100644 --- a/configs/meesc_dataflash_defconfig +++ b/configs/meesc_dataflash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_MEESC=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig index b8a48f8..e725837 100644 --- a/configs/meesc_defconfig +++ b/configs/meesc_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_MEESC=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" diff --git a/configs/mgcoge3ne_defconfig b/configs/mgcoge3ne_defconfig index e2eb06f..7b795f5 100644 --- a/configs/mgcoge3ne_defconfig +++ b/configs/mgcoge3ne_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="MGCOGE3NE" CONFIG_PPC=y CONFIG_MPC8260=y CONFIG_TARGET_KM82XX=y +CONFIG_SYS_EXTRA_OPTIONS="MGCOGE3NE" diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig index da991aa..1f2e436 100644 --- a/configs/mgcoge3un_defconfig +++ b/configs/mgcoge3un_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_KM_KIRKWOOD=y +CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN" diff --git a/configs/mgcoge_defconfig b/configs/mgcoge_defconfig index d2d4673..1fb8dfd 100644 --- a/configs/mgcoge_defconfig +++ b/configs/mgcoge_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="MGCOGE" CONFIG_PPC=y CONFIG_MPC8260=y CONFIG_TARGET_KM82XX=y +CONFIG_SYS_EXTRA_OPTIONS="MGCOGE" diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 4211d71..77e07da 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y CONFIG_MICROBLAZE=y CONFIG_TARGET_MICROBLAZE_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" +CONFIG_SPL=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y -CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 426fb52..ad794aa 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -1,14 +1,12 @@ CONFIG_X86=y CONFIG_VENDOR_INTEL=y -CONFIG_TARGET_MINNOWMAX=y -CONFIG_OF_CONTROL=y -CONFIG_OF_SEPARATE=y CONFIG_DEFAULT_DEVICE_TREE="minnowmax" +CONFIG_TARGET_MINNOWMAX=y +CONFIG_HAVE_INTEL_ME=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y -CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 -CONFIG_HAVE_INTEL_ME=y +CONFIG_SMP=y CONFIG_GENERATE_SFI_TABLE=y -CONFIG_CPU=y CONFIG_CMD_CPU=y -CONFIG_SMP=y +CONFIG_OF_CONTROL=y +CONFIG_CPU=y diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig index 4162627..5c60634 100644 --- a/configs/mixtile_loftq_defconfig +++ b/configs/mixtile_loftq_defconfig @@ -1,23 +1,12 @@ -# The Mixtile LOFT-Q is an A31 based board with 2G RAM, 8G EMMC, sdio wifi, -# 1Gbit ethernet, HDMI display, toslink audio plug, 4 USB2.0 port, external -# USB2SATA connector, sd card plug, 3x60 external fpic expansion connector, -# NXP JN5168 zigbee gw, remote support. -# -# Also see http://focalcrest.com/en/pc.html#pro02 -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)" -CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN6I=y -CONFIG_DRAM_CLK=312 CONFIG_DRAM_ZQ=251 -CONFIG_MMC_SUNXI_SLOT=0 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -# Wifi power -CONFIG_AXP221_ALDO1_VOLT=3300 -# Vbus gpio for usb1 CONFIG_USB1_VBUS_PIN="PH24" -# No Vbus gpio for usb2 CONFIG_USB2_VBUS_PIN="" +CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)" CONFIG_ETH_DESIGNWARE=y +CONFIG_AXP221_ALDO1_VOLT=3300 diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig index 8e070b9..4994936 100644 --- a/configs/mk802_a10s_defconfig +++ b/configs/mk802_a10s_defconfig @@ -1,10 +1,9 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802" -CONFIG_USB1_VBUS_PIN="PB10" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=123 CONFIG_DRAM_EMR1=0 +CONFIG_USB1_VBUS_PIN="PB10" +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI" diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index 92b9ae4..1a9a361 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -1,10 +1,7 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802" -CONFIG_USB2_VBUS_PIN="PH12" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y -CONFIG_DRAM_CLK=360 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=0 +CONFIG_USB2_VBUS_PIN="PH12" +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI" diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig index 447d128..3850fba 100644 --- a/configs/mk802ii_defconfig +++ b/configs/mk802ii_defconfig @@ -1,9 +1,6 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y -CONFIG_DRAM_CLK=360 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=0 +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI" diff --git a/configs/ml507_defconfig b/configs/ml507_defconfig index 009972a..cbd37b3 100644 --- a/configs/ml507_defconfig +++ b/configs/ml507_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_ML507=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o" diff --git a/configs/ml507_flash_defconfig b/configs/ml507_flash_defconfig index a9658b6..fba47ef 100644 --- a/configs/ml507_flash_defconfig +++ b/configs/ml507_flash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_ML507=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o" diff --git a/configs/mpc5121ads_rev2_defconfig b/configs/mpc5121ads_rev2_defconfig index 9a89611..bda0863 100644 --- a/configs/mpc5121ads_rev2_defconfig +++ b/configs/mpc5121ads_rev2_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC5121ADS_REV2" CONFIG_PPC=y CONFIG_MPC512X=y CONFIG_TARGET_MPC5121ADS=y +CONFIG_SYS_EXTRA_OPTIONS="MPC5121ADS_REV2" diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig index fd4f649..7092f76 100644 --- a/configs/mt_ventoux_defconfig +++ b/configs/mt_ventoux_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_MT_VENTOUX=y +CONFIG_SPL=y diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index 5bb4eb6..491e5ad 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_MX23_OLINUXINO=y +CONFIG_SPL=y diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig index a2d2891..c386bba 100644 --- a/configs/mx23evk_defconfig +++ b/configs/mx23evk_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_MX23EVK=y +CONFIG_SPL=y diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig index f676da6..99af9df 100644 --- a/configs/mx25pdk_defconfig +++ b/configs/mx25pdk_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg" CONFIG_ARM=y CONFIG_TARGET_MX25PDK=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg" diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig index 296a3ae..353f827 100644 --- a/configs/mx28evk_auart_console_defconfig +++ b/configs/mx28evk_auart_console_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC" CONFIG_ARM=y CONFIG_TARGET_MX28EVK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC" diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index 3714ff0..8399cbd 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC" CONFIG_ARM=y CONFIG_TARGET_MX28EVK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC" diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig index 0339b86..20e2bd4 100644 --- a/configs/mx28evk_nand_defconfig +++ b/configs/mx28evk_nand_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND" CONFIG_ARM=y CONFIG_TARGET_MX28EVK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND" diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig index 140fb08..5411e47 100644 --- a/configs/mx28evk_spi_defconfig +++ b/configs/mx28evk_spi_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH" CONFIG_ARM=y CONFIG_TARGET_MX28EVK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH" diff --git a/configs/mx31pdk_defconfig b/configs/mx31pdk_defconfig index 2d39920..3c961b4 100644 --- a/configs/mx31pdk_defconfig +++ b/configs/mx31pdk_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_MX31PDK=y +CONFIG_SPL=y diff --git a/configs/mx51_efikamx_defconfig b/configs/mx51_efikamx_defconfig index a804b5a..89b2527 100644 --- a/configs/mx51_efikamx_defconfig +++ b/configs/mx51_efikamx_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg" CONFIG_ARM=y CONFIG_TARGET_MX51_EFIKAMX=y +CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg" diff --git a/configs/mx51_efikasb_defconfig b/configs/mx51_efikasb_defconfig index b07762f..b7faacf 100644 --- a/configs/mx51_efikasb_defconfig +++ b/configs/mx51_efikasb_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg" CONFIG_ARM=y CONFIG_TARGET_MX51_EFIKAMX=y +CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg" diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index 890aa76..b3ac9f6 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg" CONFIG_ARM=y CONFIG_TARGET_MX51EVK=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg" diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig index e5cb895..988a7fd 100644 --- a/configs/mx53ard_defconfig +++ b/configs/mx53ard_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg" CONFIG_ARM=y CONFIG_TARGET_MX53ARD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg" diff --git a/configs/mx53evk_defconfig b/configs/mx53evk_defconfig index 570241f..73e6095 100644 --- a/configs/mx53evk_defconfig +++ b/configs/mx53evk_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg" CONFIG_ARM=y CONFIG_TARGET_MX53EVK=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg" diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index 92a67fb..8bb225b 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg" CONFIG_ARM=y CONFIG_TARGET_MX53LOCO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg" diff --git a/configs/mx53smd_defconfig b/configs/mx53smd_defconfig index 97cb931..bb8b8eb 100644 --- a/configs/mx53smd_defconfig +++ b/configs/mx53smd_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg" CONFIG_ARM=y CONFIG_TARGET_MX53SMD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg" diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 4c2f0e0..68eec29 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" CONFIG_ARM=y CONFIG_TARGET_MX6CUBOXI=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" CONFIG_DM=y CONFIG_DM_THERMAL=y diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig index de0193f..e2711ec 100644 --- a/configs/mx6dlarm2_defconfig +++ b/configs/mx6dlarm2_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048" CONFIG_ARM=y CONFIG_TARGET_MX6QARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048" diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig index cc432cf..f8af528 100644 --- a/configs/mx6dlarm2_lpddr2_defconfig +++ b/configs/mx6dlarm2_lpddr2_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512" CONFIG_ARM=y CONFIG_TARGET_MX6QARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512" diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig index b649935..1f19dc3 100644 --- a/configs/mx6dlsabreauto_defconfig +++ b/configs/mx6dlsabreauto_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL" CONFIG_ARM=y CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL" diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig index b333e59..5ca0e26 100644 --- a/configs/mx6dlsabresd_defconfig +++ b/configs/mx6dlsabresd_defconfig @@ -1,5 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL" CONFIG_ARM=y CONFIG_TARGET_MX6SABRESD=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL" diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig index 3fe3559..f229702 100644 --- a/configs/mx6qarm2_defconfig +++ b/configs/mx6qarm2_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048" CONFIG_ARM=y CONFIG_TARGET_MX6QARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048" diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig index 491e22a..477a692 100644 --- a/configs/mx6qarm2_lpddr2_defconfig +++ b/configs/mx6qarm2_lpddr2_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512" CONFIG_ARM=y CONFIG_TARGET_MX6QARM2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512" diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig index 7d86700..595177c 100644 --- a/configs/mx6qsabreauto_defconfig +++ b/configs/mx6qsabreauto_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q" diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 50b75ae..012ab6b2 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -1,5 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE" CONFIG_ARM=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE" CONFIG_DM=y CONFIG_DM_THERMAL=y diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig index 67c1b77..821c251 100644 --- a/configs/mx6qsabresd_defconfig +++ b/configs/mx6qsabresd_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_MX6SABRESD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q" diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig index 7f563cd..0589c48 100644 --- a/configs/mx6sabresd_spl_defconfig +++ b/configs/mx6sabresd_spl_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q" CONFIG_ARM=y CONFIG_TARGET_MX6SABRESD=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q" diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index c6b3108..ed9f836 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -1,7 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL" CONFIG_ARM=y CONFIG_TARGET_MX6SLEVK=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL" CONFIG_DM=y CONFIG_DM_THERMAL=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 454cb40..d0c993a 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -1,7 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR" CONFIG_ARM=y CONFIG_TARGET_MX6SLEVK=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR" CONFIG_DM=y CONFIG_DM_THERMAL=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index f23d48f..65590bb 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX" CONFIG_ARM=y CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX" diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig index b5e0635..3bafa12 100644 --- a/configs/mx6sxsabresd_spl_defconfig +++ b/configs/mx6sxsabresd_spl_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX" CONFIG_ARM=y CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX" diff --git a/configs/neo_defconfig b/configs/neo_defconfig index 2a19247..bc28353 100644 --- a/configs/neo_defconfig +++ b/configs/neo_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_NEO=y +CONFIG_REGEX=y diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index 7422fbe..d27182b 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NET2BIG_V2=y +CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2" diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 6a3a32f..02c82c5 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NETSPACE_V2=y +CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2" diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index 903d6c9..bdabbf5 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NETSPACE_V2=y +CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2" diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index 774faa7..a372ddc 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NETSPACE_V2=y +CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2" diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 776fc04..c83d398 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NETSPACE_V2=y +CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2" diff --git a/configs/nhk8815_onenand_defconfig b/configs/nhk8815_onenand_defconfig index dd8048d..c334e61 100644 --- a/configs/nhk8815_onenand_defconfig +++ b/configs/nhk8815_onenand_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BOOT_ONENAND" CONFIG_ARM=y CONFIG_ARCH_NOMADIK=y CONFIG_NOMADIK_NHK8815=y +CONFIG_SYS_EXTRA_OPTIONS="BOOT_ONENAND" diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index ce9343a..04439cd 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048" CONFIG_ARM=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048" diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 15dd549..d0f3d08 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024" CONFIG_ARM=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024" diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 12d9516..b8bf23f 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048" CONFIG_ARM=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048" diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index b282dc3..525794c 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024" CONFIG_ARM=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024" diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index d1a4f15..4d59075 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024" CONFIG_ARM=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024" diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index 73a206f..efeab49 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512" CONFIG_ARM=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512" diff --git a/configs/novena_defconfig b/configs/novena_defconfig index ba12075..0baa16d 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -1,4 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_KOSAGI_NOVENA=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" +CONFIG_REGEX=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 0d2ed51..d447ddc 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -3,3 +3,5 @@ CONFIG_TEGRA=y CONFIG_TEGRA124=y CONFIG_TARGET_NYAN_BIG=y CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big" +CONFIG_DISPLAY_PORT=y +CONFIG_VIDEO_TEGRA124=y diff --git a/configs/ocotea_defconfig b/configs/ocotea_defconfig index 34518cd..c0fa6ce 100644 --- a/configs/ocotea_defconfig +++ b/configs/ocotea_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_OCOTEA=y +CONFIG_REGEX=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 0fb4623..3f4c2cb 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -3,4 +3,3 @@ CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_ODROID_XU3=y CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set - diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index d32b5b5..a659bfc 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -1,8 +1,15 @@ CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_ODROID=y -CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_CONTROL=y CONFIG_DM_I2C=y CONFIG_DM_I2C_COMPAT=y -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_ERRNO_STR=y +CONFIG_DM_PMIC=y +CONFIG_CMD_PMIC=y +CONFIG_DM_PMIC_MAX77686=y +CONFIG_DM_REGULATOR=y +CONFIG_CMD_REGULATOR=y +CONFIG_DM_REGULATOR_MAX77686=y diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index 2a3cc66..07cb186 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_BEAGLE=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="NAND" diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index 91c290b..b3b1d0e 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_EVM=y +CONFIG_SPL=y diff --git a/configs/omap3_evm_quick_mmc_defconfig b/configs/omap3_evm_quick_mmc_defconfig index 12005bf..a41166f 100644 --- a/configs/omap3_evm_quick_mmc_defconfig +++ b/configs/omap3_evm_quick_mmc_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y +CONFIG_SPL=y diff --git a/configs/omap3_evm_quick_nand_defconfig b/configs/omap3_evm_quick_nand_defconfig index 5cc9512..3ae768b 100644 --- a/configs/omap3_evm_quick_nand_defconfig +++ b/configs/omap3_evm_quick_nand_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y +CONFIG_SPL=y diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig index 250890b..a48a1e0 100644 --- a/configs/omap3_ha_defconfig +++ b/configs/omap3_ha_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA" CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_TAO3530=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA" diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig index ff49de9..eb431ec 100644 --- a/configs/omap3_overo_defconfig +++ b/configs/omap3_overo_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_OVERO=y +CONFIG_SPL=y diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig index acc82d8..c8e278b 100644 --- a/configs/omap4_panda_defconfig +++ b/configs/omap4_panda_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP44XX=y CONFIG_TARGET_OMAP4_PANDA=y +CONFIG_SPL=y diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig index bfa928f..0598136 100644 --- a/configs/omap4_sdp4430_defconfig +++ b/configs/omap4_sdp4430_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP44XX=y CONFIG_TARGET_OMAP4_SDP4430=y +CONFIG_SPL=y diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index 5ab4682..88411ce 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP54XX=y CONFIG_TARGET_OMAP5_UEVM=y +CONFIG_SPL=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 8f19721..148e06a 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -1,3 +1,4 @@ CONFIG_ARM=y CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_OMAPL138_LCDK=y +CONFIG_SPL=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 7b3ea99..d7c2aee 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_OPENRD=y +CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index d34793d..2c03cf2 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_OPENRD=y +CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index 4e10d4d..4f37a94 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_OPENRD=y +CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" diff --git a/configs/origen_defconfig b/configs/origen_defconfig index aaef37f..53257d6 100644 --- a/configs/origen_defconfig +++ b/configs/origen_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_ORIGEN=y -CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen" +CONFIG_SPL=y +CONFIG_OF_CONTROL=y diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig index c516038..fae11ea 100644 --- a/configs/ot1200_defconfig +++ b/configs/ot1200_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_OT1200=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q" diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig index d99b037..2d23923 100644 --- a/configs/ot1200_spl_defconfig +++ b/configs/ot1200_spl_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_OT1200=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" diff --git a/configs/otc570_dataflash_defconfig b/configs/otc570_dataflash_defconfig index 7aac6d8..1c04762 100644 --- a/configs/otc570_dataflash_defconfig +++ b/configs/otc570_dataflash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_OTC570=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" diff --git a/configs/otc570_defconfig b/configs/otc570_defconfig index 5204245..f0358bb 100644 --- a/configs/otc570_defconfig +++ b/configs/otc570_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_OTC570=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" diff --git a/configs/palmtreo680_defconfig b/configs/palmtreo680_defconfig index 998f89b..f30d2b7 100644 --- a/configs/palmtreo680_defconfig +++ b/configs/palmtreo680_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_PALMTREO680=y +CONFIG_SPL=y diff --git a/configs/pb1000_defconfig b/configs/pb1000_defconfig index 72c22a0..bbffef6 100644 --- a/configs/pb1000_defconfig +++ b/configs/pb1000_defconfig @@ -1,4 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="PB1000" CONFIG_MIPS=y CONFIG_TARGET_PB1X00=y -CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_SYS_EXTRA_OPTIONS="PB1000" diff --git a/configs/pcm030_LOWBOOT_defconfig b/configs/pcm030_LOWBOOT_defconfig index 72ecf8f..601de5f 100644 --- a/configs/pcm030_LOWBOOT_defconfig +++ b/configs/pcm030_LOWBOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000" CONFIG_PPC=y CONFIG_MPC5xxx=y CONFIG_TARGET_PCM030=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000" diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig index 08075e7..af02b2f 100644 --- a/configs/pcm051_rev1_defconfig +++ b/configs/pcm051_rev1_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="REV1" CONFIG_ARM=y CONFIG_TARGET_PCM051=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="REV1" diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index 56deb48..2a907d7 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="REV3" CONFIG_ARM=y CONFIG_TARGET_PCM051=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="REV3" diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index 1869a41..865f52c 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -1,9 +1,9 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_PEACH_PI=y CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi" +CONFIG_SPL=y +CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_CROS_EC_KEYB=y -CONFIG_CMD_CROS_EC=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index bf6c9bd..b850092 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -1,9 +1,9 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_PEACH_PIT=y CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit" +CONFIG_SPL=y +CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_CROS_EC_KEYB=y -CONFIG_CMD_CROS_EC=y diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig index 6346b57..502c4f0 100644 --- a/configs/pengwyn_defconfig +++ b/configs/pengwyn_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_PENGWYN=y +CONFIG_SPL=y diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig index 3b042ec..9c7bf58 100644 --- a/configs/pepper_defconfig +++ b/configs/pepper_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_PEPPER=y +CONFIG_SPL=y diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig index c102626..c80c3cb 100644 --- a/configs/platinum_picon_defconfig +++ b/configs/platinum_picon_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL" CONFIG_ARM=y CONFIG_TARGET_PLATINUM_PICON=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL" diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig index 77049e5..303de5c 100644 --- a/configs/platinum_titanium_defconfig +++ b/configs/platinum_titanium_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_PLATINUM_TITANIUM=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig index 0c7efc7..c557e97 100644 --- a/configs/pm9261_defconfig +++ b/configs/pm9261_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_PM9261=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261" diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig index 6e88046..f14f0a7 100644 --- a/configs/pm9263_defconfig +++ b/configs/pm9263_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_PM9263=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263" diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig index 112ad5f..f188cd5 100644 --- a/configs/pm9g45_defconfig +++ b/configs/pm9g45_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_PM9G45=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45" diff --git a/configs/polaris_defconfig b/configs/polaris_defconfig index f510a53..284a63e 100644 --- a/configs/polaris_defconfig +++ b/configs/polaris_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="POLARIS" CONFIG_ARM=y CONFIG_TARGET_TRIZEPSIV=y +CONFIG_SYS_EXTRA_OPTIONS="POLARIS" diff --git a/configs/portl2_defconfig b/configs/portl2_defconfig index 1895c80..52867ff 100644 --- a/configs/portl2_defconfig +++ b/configs/portl2_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="KM_PORTL2" CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_KM_KIRKWOOD=y +CONFIG_SYS_EXTRA_OPTIONS="KM_PORTL2" diff --git a/configs/portuxg20_defconfig b/configs/portuxg20_defconfig index 9f3a8e1..29184e6 100644 --- a/configs/portuxg20_defconfig +++ b/configs/portuxg20_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,PORTUXG20" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_STAMP9G20=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,PORTUXG20" diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index f9e594f..db2b03a 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_PXM2=y +CONFIG_SPL=y diff --git a/configs/qemu_mips64_defconfig b/configs/qemu_mips64_defconfig index 3608bbe..691c505 100644 --- a/configs/qemu_mips64_defconfig +++ b/configs/qemu_mips64_defconfig @@ -1,4 +1,3 @@ CONFIG_MIPS=y CONFIG_TARGET_QEMU_MIPS=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_CPU_MIPS64_R1=y diff --git a/configs/qemu_mips_defconfig b/configs/qemu_mips_defconfig index f58dd22..2f767d6 100644 --- a/configs/qemu_mips_defconfig +++ b/configs/qemu_mips_defconfig @@ -1,4 +1,2 @@ CONFIG_MIPS=y CONFIG_TARGET_QEMU_MIPS=y -CONFIG_SYS_BIG_ENDIAN=y -CONFIG_CPU_MIPS32_R2=y diff --git a/configs/qemu_mipsel_defconfig b/configs/qemu_mipsel_defconfig index 84a4511..d0acb28 100644 --- a/configs/qemu_mipsel_defconfig +++ b/configs/qemu_mipsel_defconfig @@ -1,4 +1,3 @@ CONFIG_MIPS=y CONFIG_TARGET_QEMU_MIPS=y CONFIG_SYS_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32_R2=y diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index d7ed165..bc1657d 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -1,10 +1,8 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle" -CONFIG_USB1_VBUS_PIN="PG13" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=384 -CONFIG_DRAM_ZQ=123 -CONFIG_DRAM_EMR1=4 +CONFIG_USB1_VBUS_PIN="PG13" +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI" diff --git a/configs/rainier_defconfig b/configs/rainier_defconfig index 666cb18..1713592 100644 --- a/configs/rainier_defconfig +++ b/configs/rainier_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAINIER" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_SEQUOIA=y +CONFIG_SYS_EXTRA_OPTIONS="RAINIER" diff --git a/configs/rainier_ramboot_defconfig b/configs/rainier_ramboot_defconfig index 2ecb1cf..ba22d9d 100644 --- a/configs/rainier_ramboot_defconfig +++ b/configs/rainier_ramboot_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_SEQUOIA=y +CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds" diff --git a/configs/redwood_defconfig b/configs/redwood_defconfig index ad87d0e..36840dd 100644 --- a/configs/redwood_defconfig +++ b/configs/redwood_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_REDWOOD=y +CONFIG_REGEX=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 5296bde..c0b689b 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC" CONFIG_ARM=y CONFIG_TARGET_EMBESTMX6BOARDS=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC" diff --git a/configs/rut_defconfig b/configs/rut_defconfig index b7161ba..fd90d2d 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_RUT=y +CONFIG_SPL=y diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig index cdce39f..03a28ba 100644 --- a/configs/s5pc210_universal_defconfig +++ b/configs/s5pc210_universal_defconfig @@ -1,5 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_S5PC210_UNIVERSAL=y -CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210" +CONFIG_OF_CONTROL=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 3b1621a..9bcac2c 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D3_XPLAINED=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index 3a366e2..39cc95d 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D3_XPLAINED=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 940c337..1aad37e 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index 7ecd07f..ada612c 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 30e96f9..675189d 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH" diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 539b1d1..1ea23f7 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D4_XPLAINED=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 4021cb2..a358eb0 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D4_XPLAINED=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index 2b4d8fc..06457e7 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D4_XPLAINED=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index 2c77fb8..e5dbe92 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D4EK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index 4a10fa1..fa6f58b 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D4EK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index 72fb5e4..8b03ea8 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D4EK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 5de7fbe..f8dac33 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -1,28 +1,37 @@ -CONFIG_OF_CONTROL=y -CONFIG_OF_HOSTFILE=y +CONFIG_DM_USB=y +CONFIG_PCI=y +CONFIG_SYS_VSNPRINTF=y +CONFIG_DEFAULT_DEVICE_TREE="sandbox" +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y -CONFIG_DEFAULT_DEVICE_TREE="sandbox" +CONFIG_CMD_SOUND=y +CONFIG_OF_CONTROL=y +CONFIG_OF_HOSTFILE=y +CONFIG_DM_PCI=y +CONFIG_PCI_SANDBOX=y +CONFIG_SPI_FLASH_SANDBOX=y +CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_KEYB=y -CONFIG_CMD_CROS_EC=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_PCI_SANDBOX=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_EMUL=y -CONFIG_USB_STORAGE=y -CONFIG_BOOTSTAGE=y -CONFIG_BOOTSTAGE_REPORT=y -CONFIG_SANDBOX_GPIO=y -CONFIG_SYS_VSNPRINTF=y +CONFIG_TPM_TIS_SANDBOX=y CONFIG_SYS_I2C_SANDBOX=y CONFIG_SANDBOX_SPI=y -CONFIG_SPI_FLASH_SANDBOX=y -CONFIG_TPM_TIS_SANDBOX=y +CONFIG_SANDBOX_GPIO=y CONFIG_SOUND=y -CONFIG_CMD_SOUND=y CONFIG_SOUND_SANDBOX=y +CONFIG_USB=y +CONFIG_USB_EMUL=y +CONFIG_USB_STORAGE=y +CONFIG_DM_RTC=y +CONFIG_CMD_UT_TIME=y +CONFIG_ERRNO_STR=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_SANDBOX=y +CONFIG_CMD_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_SANDBOX=y +CONFIG_CMD_REGULATOR=y diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig index 14e0f6a..3032d26 100644 --- a/configs/sansa_fuze_plus_defconfig +++ b/configs/sansa_fuze_plus_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_SANSA_FUZE_PLUS=y +CONFIG_SPL=y diff --git a/configs/sbc35_a9g20_eeprom_defconfig b/configs/sbc35_a9g20_eeprom_defconfig deleted file mode 100644 index cd0909c..0000000 --- a/configs/sbc35_a9g20_eeprom_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_EEPROM" -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_SBC35_A9G20=y diff --git a/configs/sbc35_a9g20_nandflash_defconfig b/configs/sbc35_a9g20_nandflash_defconfig deleted file mode 100644 index 017346f..0000000 --- a/configs/sbc35_a9g20_nandflash_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH" -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_SBC35_A9G20=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index f7aaa7d..84ae579 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M" diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 2e1171f..f8bdfb6 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M" diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig index ae4f63f..fa4f0c1 100644 --- a/configs/sbc8548_PCI_33_PCIE_defconfig +++ b/configs/sbc8548_PCI_33_PCIE_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_SBC8548=y +CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE" diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig index b79b993..23da2b6 100644 --- a/configs/sbc8548_PCI_33_defconfig +++ b/configs/sbc8548_PCI_33_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI,33" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_SBC8548=y +CONFIG_SYS_EXTRA_OPTIONS="PCI,33" diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig index 661fd0f..a9d8fb5 100644 --- a/configs/sbc8548_PCI_66_PCIE_defconfig +++ b/configs/sbc8548_PCI_66_PCIE_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_SBC8548=y +CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE" diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig index 8cc95e5..8f2cc37 100644 --- a/configs/sbc8548_PCI_66_defconfig +++ b/configs/sbc8548_PCI_66_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PCI,66" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_SBC8548=y +CONFIG_SYS_EXTRA_OPTIONS="PCI,66" diff --git a/configs/sc3_defconfig b/configs/sc3_defconfig deleted file mode 100644 index e77b04c..0000000 --- a/configs/sc3_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_SC3=y diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig index c640125..7148bb7 100644 --- a/configs/sc_sps_1_defconfig +++ b/configs/sc_sps_1_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_SC_SPS_1=y +CONFIG_SPL=y diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig index dcd681d..aa5b3bb 100644 --- a/configs/secomx6quq7_defconfig +++ b/configs/secomx6quq7_defconfig @@ -1,7 +1,7 @@ -CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC" CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_SECOMX6=y CONFIG_SECOMX6_UQ7=y CONFIG_SECOMX6Q=y CONFIG_SECOMX6_2GB=y +CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC" diff --git a/configs/sequoia_defconfig b/configs/sequoia_defconfig index 678c2bb..3164728 100644 --- a/configs/sequoia_defconfig +++ b/configs/sequoia_defconfig @@ -1,4 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_SEQUOIA=y +CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA" +CONFIG_REGEX=y diff --git a/configs/sequoia_ramboot_defconfig b/configs/sequoia_ramboot_defconfig index 0d0c6c1..5b2c6f4 100644 --- a/configs/sequoia_ramboot_defconfig +++ b/configs/sequoia_ramboot_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_SEQUOIA=y +CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds" diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig index 35809e9..9ff4121 100644 --- a/configs/sh7753evb_defconfig +++ b/configs/sh7753evb_defconfig @@ -1,3 +1,2 @@ CONFIG_SH=y -CONFIG_SH_32BIT=y CONFIG_TARGET_SH7753EVB=y diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig index 0e7b868..fb872de 100644 --- a/configs/smdk5250_defconfig +++ b/configs/smdk5250_defconfig @@ -1,10 +1,10 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_SMDK5250=y CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250" -CONFIG_SOUND=y +CONFIG_SPL=y CONFIG_CMD_SOUND=y +CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y CONFIG_SOUND_MAX98095=y diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig index 3d3db8e..b9949d3 100644 --- a/configs/smdk5420_defconfig +++ b/configs/smdk5420_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_SMDK5420=y CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420" +CONFIG_SPL=y diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig index 041030f..ac9bd25 100644 --- a/configs/smdkc100_defconfig +++ b/configs/smdkc100_defconfig @@ -1,4 +1,4 @@ CONFIG_ARM=y -CONFIG_TARGET_SMDKC100=y CONFIG_ARCH_S5PC1XX=y +CONFIG_TARGET_SMDKC100=y CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100" diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig index 101d957..833906e 100644 --- a/configs/smdkv310_defconfig +++ b/configs/smdkv310_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_SMDKV310=y CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310" +CONFIG_SPL=y diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig index 5c8850a..5d239c9 100644 --- a/configs/snapper9260_defconfig +++ b/configs/snapper9260_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SNAPPER9260=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260" diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig index 9270b8d..382b2ab 100644 --- a/configs/snapper9g20_defconfig +++ b/configs/snapper9g20_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SNAPPER9260=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" diff --git a/configs/snow_defconfig b/configs/snow_defconfig index 6c76f4d..0ae2b9b 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -1,14 +1,14 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_SNOW=y CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow" +CONFIG_SPL=y +CONFIG_CMD_SOUND=y +CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_KEYB=y -CONFIG_CMD_CROS_EC=y CONFIG_SOUND=y -CONFIG_CMD_SOUND=y CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y CONFIG_SOUND_MAX98095=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 52032e5..f682492 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -1,5 +1,7 @@ -CONFIG_SPL=y CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y CONFIG_TARGET_SOCFPGA_ARRIA5=y -CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk" +CONFIG_SPL=y +CONFIG_OF_CONTROL=y +CONFIG_REGEX=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 6c982ab..256952e 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -1,8 +1,10 @@ -CONFIG_SPL=y CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y CONFIG_TARGET_SOCFPGA_CYCLONE5=y -CONFIG_OF_CONTROL=y +CONFIG_NET=y +CONFIG_NETDEVICES=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" +CONFIG_SPL=y +CONFIG_OF_CONTROL=y CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y -CONFIG_NET=y +CONFIG_REGEX=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index c81ab0f..8b3cccc 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -1,8 +1,9 @@ -CONFIG_SPL=y CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y CONFIG_TARGET_SOCFPGA_CYCLONE5=y -CONFIG_OF_CONTROL=y +CONFIG_NET=y +CONFIG_NETDEVICES=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" +CONFIG_SPL=y +CONFIG_OF_CONTROL=y CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y -CONFIG_NET=y diff --git a/configs/spear300_defconfig b/configs/spear300_defconfig index df0b190..52dd4da 100644 --- a/configs/spear300_defconfig +++ b/configs/spear300_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear300" CONFIG_ARM=y CONFIG_TARGET_SPEAR300=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear300" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear300_nand_defconfig b/configs/spear300_nand_defconfig index a49492c..2910c07 100644 --- a/configs/spear300_nand_defconfig +++ b/configs/spear300_nand_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear300,nand" CONFIG_ARM=y CONFIG_TARGET_SPEAR300=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear300,nand" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear300_usbtty_defconfig b/configs/spear300_usbtty_defconfig index 3d60d7f..12d197e 100644 --- a/configs/spear300_usbtty_defconfig +++ b/configs/spear300_usbtty_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty" CONFIG_ARM=y CONFIG_TARGET_SPEAR300=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear300_usbtty_nand_defconfig b/configs/spear300_usbtty_nand_defconfig index ffe4f59..e303cad 100644 --- a/configs/spear300_usbtty_nand_defconfig +++ b/configs/spear300_usbtty_nand_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty,nand" CONFIG_ARM=y CONFIG_TARGET_SPEAR300=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty,nand" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear310_defconfig b/configs/spear310_defconfig index 16a6bc3..5e0beb6 100644 --- a/configs/spear310_defconfig +++ b/configs/spear310_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear310" CONFIG_ARM=y CONFIG_TARGET_SPEAR310=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear310" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear310_nand_defconfig b/configs/spear310_nand_defconfig index 05e3c96..3772d40 100644 --- a/configs/spear310_nand_defconfig +++ b/configs/spear310_nand_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear310,nand" CONFIG_ARM=y CONFIG_TARGET_SPEAR310=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear310,nand" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear310_pnor_defconfig b/configs/spear310_pnor_defconfig index 384cb54..137161e 100644 --- a/configs/spear310_pnor_defconfig +++ b/configs/spear310_pnor_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear310,FLASH_PNOR" CONFIG_ARM=y CONFIG_TARGET_SPEAR310=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear310,FLASH_PNOR" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear310_usbtty_defconfig b/configs/spear310_usbtty_defconfig index 0115f2c..df8bb52 100644 --- a/configs/spear310_usbtty_defconfig +++ b/configs/spear310_usbtty_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty" CONFIG_ARM=y CONFIG_TARGET_SPEAR310=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear310_usbtty_nand_defconfig b/configs/spear310_usbtty_nand_defconfig index 2d82b66..71cabff 100644 --- a/configs/spear310_usbtty_nand_defconfig +++ b/configs/spear310_usbtty_nand_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,nand" CONFIG_ARM=y CONFIG_TARGET_SPEAR310=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,nand" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear310_usbtty_pnor_defconfig b/configs/spear310_usbtty_pnor_defconfig index 579df36..b5418e5 100644 --- a/configs/spear310_usbtty_pnor_defconfig +++ b/configs/spear310_usbtty_pnor_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,FLASH_PNOR" CONFIG_ARM=y CONFIG_TARGET_SPEAR310=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,FLASH_PNOR" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear320_defconfig b/configs/spear320_defconfig index 7bd51a8..0172c15 100644 --- a/configs/spear320_defconfig +++ b/configs/spear320_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear320" CONFIG_ARM=y CONFIG_TARGET_SPEAR320=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear320" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear320_nand_defconfig b/configs/spear320_nand_defconfig index d7c995c..347b3de 100644 --- a/configs/spear320_nand_defconfig +++ b/configs/spear320_nand_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear320,nand" CONFIG_ARM=y CONFIG_TARGET_SPEAR320=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear320,nand" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear320_pnor_defconfig b/configs/spear320_pnor_defconfig index a56a4e0..7b1b8e1 100644 --- a/configs/spear320_pnor_defconfig +++ b/configs/spear320_pnor_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear320,FLASH_PNOR" CONFIG_ARM=y CONFIG_TARGET_SPEAR320=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear320,FLASH_PNOR" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear320_usbtty_defconfig b/configs/spear320_usbtty_defconfig index c2fb481..907ba89 100644 --- a/configs/spear320_usbtty_defconfig +++ b/configs/spear320_usbtty_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty" CONFIG_ARM=y CONFIG_TARGET_SPEAR320=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear320_usbtty_nand_defconfig b/configs/spear320_usbtty_nand_defconfig index 98368ed..1350134 100644 --- a/configs/spear320_usbtty_nand_defconfig +++ b/configs/spear320_usbtty_nand_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,nand" CONFIG_ARM=y CONFIG_TARGET_SPEAR320=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,nand" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear320_usbtty_pnor_defconfig b/configs/spear320_usbtty_pnor_defconfig index e428d25..0b31b9a 100644 --- a/configs/spear320_usbtty_pnor_defconfig +++ b/configs/spear320_usbtty_pnor_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,FLASH_PNOR" CONFIG_ARM=y CONFIG_TARGET_SPEAR320=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,FLASH_PNOR" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig index dae0d59..e573ecc 100644 --- a/configs/spear600_defconfig +++ b/configs/spear600_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear600" CONFIG_ARM=y CONFIG_TARGET_SPEAR600=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear600" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear600_nand_defconfig b/configs/spear600_nand_defconfig index cdd98fc..a1e9c02 100644 --- a/configs/spear600_nand_defconfig +++ b/configs/spear600_nand_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear600,nand" CONFIG_ARM=y CONFIG_TARGET_SPEAR600=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear600,nand" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig index 1e28edf..7673960 100644 --- a/configs/spear600_usbtty_defconfig +++ b/configs/spear600_usbtty_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty" CONFIG_ARM=y CONFIG_TARGET_SPEAR600=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig index 2f8fd5e..1cdb780 100644 --- a/configs/spear600_usbtty_nand_defconfig +++ b/configs/spear600_usbtty_nand_defconfig @@ -1,6 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty,nand" CONFIG_ARM=y CONFIG_TARGET_SPEAR600=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty,nand" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/stamp9g20_defconfig b/configs/stamp9g20_defconfig index 03bf492..e765329 100644 --- a/configs/stamp9g20_defconfig +++ b/configs/stamp9g20_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_STAMP9G20=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 76ba41b..2be3f82 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -1,7 +1,8 @@ -CONFIG_SYS_EXTRA_OPTIONS="stv0991" CONFIG_ARM=y CONFIG_TARGET_STV0991=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_DEFAULT_DEVICE_TREE="stv0991" +CONFIG_SYS_EXTRA_OPTIONS="stv0991" +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/stxssa_4M_defconfig b/configs/stxssa_4M_defconfig index 1ffe9f9..e6df158 100644 --- a/configs/stxssa_4M_defconfig +++ b/configs/stxssa_4M_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="STXSSA_4M" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_STXSSA=y +CONFIG_SYS_EXTRA_OPTIONS="STXSSA_4M" diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index c46b725..35aa847 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -1,20 +1,13 @@ -# Gemei G9 is an A10 based tablet, with 1G RAM, 16G NAND, -# 1024x768 IPS LCD display, stereo speakers, 1.3MP front camera and 5 MP -# rear camera, 8000mAh battery, GT901 2+1 touchscreen, Bosch BMA250 -# accelerometer and RTL8188CUS USB wifi. It also has MicroSD slot, MiniHDMI, -# 1 x MicroUSB OTG port and 1 x MicroUSB host port and 3.5mm headphone jack. -# More details are available at: http://linux-sunxi.org/Gemei_G9 -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI" -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9" -CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0" -CONFIG_VIDEO_LCD_PANEL_LVDS=y -CONFIG_VIDEO_LCD_POWER="PH8" -CONFIG_VIDEO_LCD_BL_EN="PH7" -CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 -CONFIG_DRAM_ZQ=123 CONFIG_DRAM_EMR1=4 +CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_POWER="PH8" +CONFIG_VIDEO_LCD_BL_EN="PH7" +CONFIG_VIDEO_LCD_BL_PWM="PB2" +CONFIG_VIDEO_LCD_PANEL_LVDS=y +CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI" diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 0407c87..e477b0e 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SUVD3" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_SUVD3=y +CONFIG_SYS_EXTRA_OPTIONS="SUVD3" diff --git a/configs/t3corp_defconfig b/configs/t3corp_defconfig index c61508a..beac623 100644 --- a/configs/t3corp_defconfig +++ b/configs/t3corp_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_T3CORP=y +CONFIG_REGEX=y diff --git a/configs/taihu_defconfig b/configs/taihu_defconfig index ac83725..42126f5 100644 --- a/configs/taihu_defconfig +++ b/configs/taihu_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_TAIHU=y +CONFIG_REGEX=y diff --git a/configs/taishan_defconfig b/configs/taishan_defconfig index e956c6f..81fe19d 100644 --- a/configs/taishan_defconfig +++ b/configs/taishan_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_TAISHAN=y +CONFIG_REGEX=y diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig index 86ba4cd..ad4517d 100644 --- a/configs/tao3530_defconfig +++ b/configs/tao3530_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_TAO3530=y +CONFIG_SPL=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 90c22d2..336ca41 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_TAURUS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS" diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig index aed9210..c8a71bf 100644 --- a/configs/tb100_defconfig +++ b/configs/tb100_defconfig @@ -1,13 +1,13 @@ CONFIG_ARC=y CONFIG_ARC_CACHE_LINE_SHIFT=5 CONFIG_TARGET_TB100=y -CONFIG_DM=y +CONFIG_SYS_CLK_FREQ=500000000 +CONFIG_NET=y +CONFIG_NETDEVICES=y CONFIG_DM_SERIAL=y -CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100" CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_SYS_CLK_FREQ=500000000 +CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y +CONFIG_DM=y CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y -CONFIG_NET=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 602d691..cace345 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_TBS2910=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q" diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig index 6f1325b..f48f921 100644 --- a/configs/ti814x_evm_defconfig +++ b/configs/ti814x_evm_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_TI814X_EVM=y +CONFIG_SPL=y diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig index 4661f3c..c08e422 100644 --- a/configs/ti816x_evm_defconfig +++ b/configs/ti816x_evm_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_TI816X_EVM=y +CONFIG_SPL=y diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig index 96f7f79..62af244 100644 --- a/configs/titanium_defconfig +++ b/configs/titanium_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/barco/titanium/imximage.cfg" CONFIG_ARM=y CONFIG_TARGET_TITANIUM=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/barco/titanium/imximage.cfg" diff --git a/configs/tny_a9260_eeprom_defconfig b/configs/tny_a9260_eeprom_defconfig deleted file mode 100644 index 28a1d5e..0000000 --- a/configs/tny_a9260_eeprom_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_EEPROM" -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_TNY_A9260=y diff --git a/configs/tny_a9260_nandflash_defconfig b/configs/tny_a9260_nandflash_defconfig deleted file mode 100644 index 14710c0..0000000 --- a/configs/tny_a9260_nandflash_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH" -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_TNY_A9260=y diff --git a/configs/tny_a9g20_eeprom_defconfig b/configs/tny_a9g20_eeprom_defconfig deleted file mode 100644 index f4023cc..0000000 --- a/configs/tny_a9g20_eeprom_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_EEPROM" -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_TNY_A9260=y diff --git a/configs/tny_a9g20_nandflash_defconfig b/configs/tny_a9g20_nandflash_defconfig deleted file mode 100644 index 2452e1e..0000000 --- a/configs/tny_a9g20_nandflash_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH" -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_TARGET_TNY_A9260=y diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig index 4ee9238..627883a 100644 --- a/configs/tqma6q_mba6_mmc_defconfig +++ b/configs/tqma6q_mba6_mmc_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_MMC_BOOT" CONFIG_ARM=y CONFIG_TARGET_TQMA6=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_MMC_BOOT" diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig index 86d4ca3..a56a802 100644 --- a/configs/tqma6q_mba6_spi_defconfig +++ b/configs/tqma6q_mba6_spi_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_SPI_BOOT" CONFIG_ARM=y CONFIG_TARGET_TQMA6=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_SPI_BOOT" diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig index 5efce6a..51958e2 100644 --- a/configs/tqma6s_mba6_mmc_defconfig +++ b/configs/tqma6s_mba6_mmc_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_MMC_BOOT" CONFIG_ARM=y CONFIG_TARGET_TQMA6=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_MMC_BOOT" diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig index e8b3afd..f94f704 100644 --- a/configs/tqma6s_mba6_spi_defconfig +++ b/configs/tqma6s_mba6_spi_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_SPI_BOOT" CONFIG_ARM=y CONFIG_TARGET_TQMA6=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_SPI_BOOT" diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig index 9359706..8326d69 100644 --- a/configs/trats2_defconfig +++ b/configs/trats2_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_TRATS2=y -CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_CONTROL=y diff --git a/configs/trats_defconfig b/configs/trats_defconfig index 901a014..b6f4ebe 100644 --- a/configs/trats_defconfig +++ b/configs/trats_defconfig @@ -1,5 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_TRATS=y -CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats" +CONFIG_OF_CONTROL=y diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig index e307c65..a710804 100644 --- a/configs/tricorder_defconfig +++ b/configs/tricorder_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_TRICORDER=y +CONFIG_SPL=y diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig index de6c16e..c00bffe 100644 --- a/configs/tricorder_flash_defconfig +++ b/configs/tricorder_flash_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD" CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_TRICORDER=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD" diff --git a/configs/tseries_mmc_defconfig b/configs/tseries_mmc_defconfig index 0b92e14..cdcdb99 100644 --- a/configs/tseries_mmc_defconfig +++ b/configs/tseries_mmc_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT" CONFIG_ARM=y CONFIG_TARGET_TSERIES=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT" # CONFIG_CMD_CRC32 is not set diff --git a/configs/tseries_nand_defconfig b/configs/tseries_nand_defconfig index 658e188..2139f4d 100644 --- a/configs/tseries_nand_defconfig +++ b/configs/tseries_nand_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND" CONFIG_ARM=y CONFIG_TARGET_TSERIES=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND" # CONFIG_CMD_CRC32 is not set diff --git a/configs/tseries_spi_defconfig b/configs/tseries_spi_defconfig index a274db0..5e01789 100644 --- a/configs/tseries_spi_defconfig +++ b/configs/tseries_spi_defconfig @@ -1,5 +1,5 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT" CONFIG_ARM=y CONFIG_TARGET_TSERIES=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT" # CONFIG_CMD_CRC32 is not set diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index c1c9c43..d4a422c 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="TUGE1" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y +CONFIG_SYS_EXTRA_OPTIONS="TUGE1" diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index ecea63f..c8db21a 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="TUXX1" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y +CONFIG_SYS_EXTRA_OPTIONS="TUXX1" diff --git a/configs/twister_defconfig b/configs/twister_defconfig index 344369d..710ab43 100644 --- a/configs/twister_defconfig +++ b/configs/twister_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_TWISTER=y +CONFIG_SPL=y diff --git a/configs/tx25_defconfig b/configs/tx25_defconfig index dfa5c30..8f7e303 100644 --- a/configs/tx25_defconfig +++ b/configs/tx25_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_TX25=y +CONFIG_SPL=y diff --git a/configs/udoo_quad_defconfig b/configs/udoo_quad_defconfig index 860a310..9687475 100644 --- a/configs/udoo_quad_defconfig +++ b/configs/udoo_quad_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024" CONFIG_ARM=y CONFIG_TARGET_UDOO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024" diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig index ae2b9a1..7ce920a 100644 --- a/configs/usb_a9263_dataflash_defconfig +++ b/configs/usb_a9263_dataflash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_USB_A9263=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" diff --git a/configs/v5fx30teval_defconfig b/configs/v5fx30teval_defconfig index bb58153..42e0438 100644 --- a/configs/v5fx30teval_defconfig +++ b/configs/v5fx30teval_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_V5FX30TEVAL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o" diff --git a/configs/v5fx30teval_flash_defconfig b/configs/v5fx30teval_flash_defconfig index 1c6ec89..495f3b9 100644 --- a/configs/v5fx30teval_flash_defconfig +++ b/configs/v5fx30teval_flash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_V5FX30TEVAL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o" diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig index 32e9e8c..7514857 100644 --- a/configs/vct_platinum_defconfig +++ b/configs/vct_platinum_defconfig @@ -1,4 +1,3 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_VCT_PLATINUM=y diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig index 4346518..7fb75f0 100644 --- a/configs/vct_platinum_onenand_defconfig +++ b/configs/vct_platinum_onenand_defconfig @@ -1,5 +1,4 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_VCT_PLATINUM=y CONFIG_VCT_ONENAND=y diff --git a/configs/vct_platinum_onenand_small_defconfig b/configs/vct_platinum_onenand_small_defconfig index fd52282..4d82da9 100644 --- a/configs/vct_platinum_onenand_small_defconfig +++ b/configs/vct_platinum_onenand_small_defconfig @@ -1,6 +1,5 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_VCT_PLATINUM=y CONFIG_VCT_ONENAND=y CONFIG_VCT_SMALL_IMAGE=y diff --git a/configs/vct_platinum_small_defconfig b/configs/vct_platinum_small_defconfig index 58f956d..5e1f4ab 100644 --- a/configs/vct_platinum_small_defconfig +++ b/configs/vct_platinum_small_defconfig @@ -1,6 +1,5 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_VCT_PLATINUM=y CONFIG_VCT_SMALL_IMAGE=y # CONFIG_CMD_CRC32 is not set diff --git a/configs/vct_platinumavc_defconfig b/configs/vct_platinumavc_defconfig index 732565c..0a5748a 100644 --- a/configs/vct_platinumavc_defconfig +++ b/configs/vct_platinumavc_defconfig @@ -1,4 +1,3 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_VCT_PLATINUMAVC=y diff --git a/configs/vct_platinumavc_onenand_defconfig b/configs/vct_platinumavc_onenand_defconfig index 670e7f9..289f864 100644 --- a/configs/vct_platinumavc_onenand_defconfig +++ b/configs/vct_platinumavc_onenand_defconfig @@ -1,5 +1,4 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_VCT_PLATINUMAVC=y CONFIG_VCT_ONENAND=y diff --git a/configs/vct_platinumavc_onenand_small_defconfig b/configs/vct_platinumavc_onenand_small_defconfig index 31a4948..1b28535 100644 --- a/configs/vct_platinumavc_onenand_small_defconfig +++ b/configs/vct_platinumavc_onenand_small_defconfig @@ -1,6 +1,5 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_VCT_PLATINUMAVC=y CONFIG_VCT_ONENAND=y CONFIG_VCT_SMALL_IMAGE=y diff --git a/configs/vct_platinumavc_small_defconfig b/configs/vct_platinumavc_small_defconfig index ce00a6c..54813ca 100644 --- a/configs/vct_platinumavc_small_defconfig +++ b/configs/vct_platinumavc_small_defconfig @@ -1,6 +1,5 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_VCT_PLATINUMAVC=y CONFIG_VCT_SMALL_IMAGE=y # CONFIG_CMD_CRC32 is not set diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig index a19e65d..80c468b 100644 --- a/configs/vct_premium_defconfig +++ b/configs/vct_premium_defconfig @@ -1,4 +1,3 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_VCT_PREMIUM=y diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig index 092d0f7..eb61ef6 100644 --- a/configs/vct_premium_onenand_defconfig +++ b/configs/vct_premium_onenand_defconfig @@ -1,5 +1,4 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_VCT_PREMIUM=y CONFIG_VCT_ONENAND=y diff --git a/configs/vct_premium_onenand_small_defconfig b/configs/vct_premium_onenand_small_defconfig index eabfb88..f592a62 100644 --- a/configs/vct_premium_onenand_small_defconfig +++ b/configs/vct_premium_onenand_small_defconfig @@ -1,6 +1,5 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_VCT_PREMIUM=y CONFIG_VCT_ONENAND=y CONFIG_VCT_SMALL_IMAGE=y diff --git a/configs/vct_premium_small_defconfig b/configs/vct_premium_small_defconfig index 1ce0efd..3fb5e69 100644 --- a/configs/vct_premium_small_defconfig +++ b/configs/vct_premium_small_defconfig @@ -1,6 +1,5 @@ CONFIG_MIPS=y CONFIG_TARGET_VCT=y -CONFIG_SYS_BIG_ENDIAN=y CONFIG_VCT_PREMIUM=y CONFIG_VCT_SMALL_IMAGE=y # CONFIG_CMD_CRC32 is not set diff --git a/configs/versatileab_defconfig b/configs/versatileab_defconfig index 94680fe..058f8cd 100644 --- a/configs/versatileab_defconfig +++ b/configs/versatileab_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_AB" CONFIG_ARM=y CONFIG_ARCH_VERSATILE=y +CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_AB" diff --git a/configs/versatilepb_defconfig b/configs/versatilepb_defconfig index 2c59e5c..ae8224f 100644 --- a/configs/versatilepb_defconfig +++ b/configs/versatilepb_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_PB" CONFIG_ARM=y CONFIG_ARCH_VERSATILE=y +CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_PB" diff --git a/configs/versatileqemu_defconfig b/configs/versatileqemu_defconfig index fb0485d..dd71501 100644 --- a/configs/versatileqemu_defconfig +++ b/configs/versatileqemu_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB" CONFIG_ARM=y CONFIG_ARCH_VERSATILE=y +CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB" diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index d28a428..49052f1 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -1,5 +1,3 @@ -# ARM Ltd. Juno Board Reference Design CONFIG_ARM=y CONFIG_TARGET_VEXPRESS64_JUNO=y CONFIG_DEFAULT_DEVICE_TREE="vexpress64" -CONFIG_SHOW_BOOT_PROGRESS=y diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index 26cf7db4..d05c848 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -1,4 +1,3 @@ -# Semihosted FVP fast model CONFIG_ARM=y CONFIG_TARGET_VEXPRESS64_BASE_FVP=y CONFIG_DEFAULT_DEVICE_TREE="vexpress64" diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig index 7de374a..3a71740 100644 --- a/configs/vf610twr_defconfig +++ b/configs/vf610twr_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC" CONFIG_ARM=y CONFIG_TARGET_VF610TWR=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC" diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig index e78db26..e22704a 100644 --- a/configs/vf610twr_nand_defconfig +++ b/configs/vf610twr_nand_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND" CONFIG_ARM=y CONFIG_TARGET_VF610TWR=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND" diff --git a/configs/vision2_defconfig b/configs/vision2_defconfig index 430dbc0..ae2b487 100644 --- a/configs/vision2_defconfig +++ b/configs/vision2_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg" CONFIG_ARM=y CONFIG_TARGET_VISION2=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg" diff --git a/configs/vl_ma2sc_ram_defconfig b/configs/vl_ma2sc_ram_defconfig index fdb262d..c1f4947 100644 --- a/configs/vl_ma2sc_ram_defconfig +++ b/configs/vl_ma2sc_ram_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMLOAD" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_VL_MA2SC=y +CONFIG_SYS_EXTRA_OPTIONS="RAMLOAD" diff --git a/configs/vpac270_nor_128_defconfig b/configs/vpac270_nor_128_defconfig index 74609ab..0f2ff7c 100644 --- a/configs/vpac270_nor_128_defconfig +++ b/configs/vpac270_nor_128_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_128M" CONFIG_ARM=y CONFIG_TARGET_VPAC270=y +CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_128M" diff --git a/configs/vpac270_nor_256_defconfig b/configs/vpac270_nor_256_defconfig index d6163ef..dfff8b4 100644 --- a/configs/vpac270_nor_256_defconfig +++ b/configs/vpac270_nor_256_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_256M" CONFIG_ARM=y CONFIG_TARGET_VPAC270=y +CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_256M" diff --git a/configs/vpac270_ond_256_defconfig b/configs/vpac270_ond_256_defconfig index 75a471e..ea61a76 100644 --- a/configs/vpac270_ond_256_defconfig +++ b/configs/vpac270_ond_256_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="ONENAND,RAM_256M" CONFIG_ARM=y CONFIG_TARGET_VPAC270=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="ONENAND,RAM_256M" diff --git a/configs/walnut_defconfig b/configs/walnut_defconfig index 844e67f..c5b302e 100644 --- a/configs/walnut_defconfig +++ b/configs/walnut_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_WALNUT=y +CONFIG_REGEX=y diff --git a/configs/wandboard_dl_defconfig b/configs/wandboard_dl_defconfig index 5a1f7f5..0136cdf 100644 --- a/configs/wandboard_dl_defconfig +++ b/configs/wandboard_dl_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024" CONFIG_ARM=y CONFIG_TARGET_WANDBOARD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024" diff --git a/configs/wandboard_quad_defconfig b/configs/wandboard_quad_defconfig index d940848..0f9bdf9 100644 --- a/configs/wandboard_quad_defconfig +++ b/configs/wandboard_quad_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048" CONFIG_ARM=y CONFIG_TARGET_WANDBOARD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048" diff --git a/configs/wandboard_solo_defconfig b/configs/wandboard_solo_defconfig index 66aa5d3..57a227c 100644 --- a/configs/wandboard_solo_defconfig +++ b/configs/wandboard_solo_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512" CONFIG_ARM=y CONFIG_TARGET_WANDBOARD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512" diff --git a/configs/warp_defconfig b/configs/warp_defconfig index 624a8af..24e1b9f 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL" CONFIG_ARM=y CONFIG_TARGET_WARP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL" diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig index 275a33f..29e87f5 100644 --- a/configs/woodburn_sd_defconfig +++ b/configs/woodburn_sd_defconfig @@ -1,4 +1,4 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg" CONFIG_ARM=y CONFIG_TARGET_WOODBURN_SD=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg" diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 142a505..09cd3ba 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_TARGET_WORK_92105=y +CONFIG_SPL=y CONFIG_DM=y CONFIG_DM_GPIO=y -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="" diff --git a/configs/wtk_defconfig b/configs/wtk_defconfig index 2ccddc1..838190b 100644 --- a/configs/wtk_defconfig +++ b/configs/wtk_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ065T9DR51U" CONFIG_PPC=y CONFIG_8xx=y CONFIG_TARGET_TQM823L=y +CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ065T9DR51U" diff --git a/configs/x600_defconfig b/configs/x600_defconfig index 7cd239b..ad990df 100644 --- a/configs/x600_defconfig +++ b/configs/x600_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_X600=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_NETDEVICES=y CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SPL=y +CONFIG_ETH_DESIGNWARE=y diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig index 7537567..7cd97e6 100644 --- a/configs/xfi3_defconfig +++ b/configs/xfi3_defconfig @@ -1,3 +1,3 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_XFI3=y +CONFIG_SPL=y diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig index 691412c..f4ed6d1 100644 --- a/configs/xilinx-ppc405-generic_defconfig +++ b/configs/xilinx-ppc405-generic_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_XILINX_PPC405_GENERIC=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000" diff --git a/configs/xilinx-ppc405-generic_flash_defconfig b/configs/xilinx-ppc405-generic_flash_defconfig index 317b63d..1b0311c 100644 --- a/configs/xilinx-ppc405-generic_flash_defconfig +++ b/configs/xilinx-ppc405-generic_flash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_XILINX_PPC405_GENERIC=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC" diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig index 31ce75b..cac8785 100644 --- a/configs/xilinx-ppc440-generic_defconfig +++ b/configs/xilinx-ppc440-generic_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_XILINX_PPC440_GENERIC=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1" diff --git a/configs/xilinx-ppc440-generic_flash_defconfig b/configs/xilinx-ppc440-generic_flash_defconfig index 635926f..b271554 100644 --- a/configs/xilinx-ppc440-generic_flash_defconfig +++ b/configs/xilinx-ppc440-generic_flash_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_XILINX_PPC440_GENERIC=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC" diff --git a/configs/xilinx_zynqmp_defconfig b/configs/xilinx_zynqmp_defconfig index 8b6aa70..c512e9c 100644 --- a/configs/xilinx_zynqmp_defconfig +++ b/configs/xilinx_zynqmp_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_XILINX_ZYNQMP=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp" CONFIG_CMD_BDI=y CONFIG_CMD_BOOTD=y CONFIG_CMD_RUN=y @@ -11,4 +12,3 @@ CONFIG_CMD_SOURCE=y CONFIG_CMD_TIME=y CONFIG_CMD_MISC=y CONFIG_CMD_TIMER=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp" diff --git a/configs/yellowstone_defconfig b/configs/yellowstone_defconfig index 843095b..7b1a630 100644 --- a/configs/yellowstone_defconfig +++ b/configs/yellowstone_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_YOSEMITE=y +CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE" diff --git a/configs/yosemite_defconfig b/configs/yosemite_defconfig index d5eea68..430f25e 100644 --- a/configs/yosemite_defconfig +++ b/configs/yosemite_defconfig @@ -1,4 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_YOSEMITE=y +CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE" +CONFIG_REGEX=y diff --git a/configs/yucca_defconfig b/configs/yucca_defconfig index 6c8e20a..ed42523 100644 --- a/configs/yucca_defconfig +++ b/configs/yucca_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_YUCCA=y +CONFIG_REGEX=y diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 40d675f..9a7d26c 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -1,10 +1,10 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_MICROZED=y -CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y -CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed" +CONFIG_OF_CONTROL=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index 61852cb..f86ef5d 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -1,6 +1,5 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_PICOZED=y -CONFIG_OF_CONTROL=n CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed" +CONFIG_SPL=y diff --git a/configs/zynq_zc70x_defconfig b/configs/zynq_zc70x_defconfig index 7c3cb2d..01b9fab 100644 --- a/configs/zynq_zc70x_defconfig +++ b/configs/zynq_zc70x_defconfig @@ -1,10 +1,10 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_ZC70X=y -CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_OF_CONTROL=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 36b95fa..6565276 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -1,11 +1,11 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_ZC770=y -CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" +CONFIG_OF_CONTROL=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 6c5eecc..adc0d7f 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -1,11 +1,11 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_ZC770=y -CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" +CONFIG_OF_CONTROL=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index eabc106..0066ca0 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -1,11 +1,11 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_ZC770=y -CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" +CONFIG_OF_CONTROL=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index b2b4b99..4900b7c 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -1,10 +1,10 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_ZED=y -CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zed" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_OF_CONTROL=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index da55320..37bfa64 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -1,10 +1,10 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_ZYBO=y -CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo" # CONFIG_SYS_MALLOC_F is not set +CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_OF_CONTROL=y diff --git a/doc/README.mxc_hab b/doc/README.mxc_hab index a1b1d34..b688580 100644 --- a/doc/README.mxc_hab +++ b/doc/README.mxc_hab @@ -1,7 +1,13 @@ High Assurance Boot (HAB) for i.MX6 CPUs -To authenticate U-Boot only by the CPU there is no code required in -U-Boot itself. However, the U-Boot image to be programmed into the +To enable the authenticated or encrypted boot mode of U-Boot, it is +required to set the proper configuration for the target board. This +is done by adding the following configuration in in the proper config +file (e.g. include/configs/mx6qarm2.h) + +#define CONFIG_SECURE_BOOT + +In addition, the U-Boot image to be programmed into the boot media needs to be properly constructed, i.e. it must contain a proper Command Sequence File (CSF). @@ -69,7 +75,7 @@ CONFIG_SECURE_BOOT CONFIG_SYS_FSL_SEC_COMPAT 4 /* HAB version */ CONFIG_FSL_CAAM CONFIG_CMD_DEKBLOB -CONFIG_SYS_FSL_LE +CONFIG_SYS_FSL_SEC_LE Note: The encrypted boot feature is only supported by HABv4 or greater. diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 59d2142..aa2b07b 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,14 +12,17 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -korat powerpc ppc4xx - - Larry Johnson <lrj@acm.org> -galaxy5200 powerpc mpc5xxx - - Eric Millbrandt <emillbrandt@dekaresearch.com> -W7OLMC powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com> -W7OLMG powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com> -aev powerpc mpc5xxx - - -TB5200 powerpc mpc5xxx - - -JSE powerpc ppc4xx - - Stephen Williams <steve@icarus.com> -BC3450 powerpc mpc5xxx - - +afeb9260 arm arm926ejs - - Sergey Lapin <slapin@ossfans.org> +tny_a9260 arm arm926ejs - - Albin Tonnerre <albin.tonnerre@free-electrons.com> +sbc35_a9g20 arm arm926ejs - - Albin Tonnerre <albin.tonnerre@free-electrons.com> +korat powerpc ppc4xx 5043045d 2015-03-17 Larry Johnson <lrj@acm.org> +galaxy5200 powerpc mpc5xxx 41eb4e5c 2015-03-17 Eric Millbrandt <emillbrandt@dekaresearch.com> +W7OLMC powerpc ppc4xx 6beecd5d 2015-03-17 Erik Theisen <etheisen@mindspring.com> +W7OLMG powerpc ppc4xx 6beecd5d 2015-03-17 Erik Theisen <etheisen@mindspring.com> +aev powerpc mpc5xxx 470ee8b1 2015-03-17 +TB5200 powerpc mpc5xxx 470ee8b1 2015-03-17 +JSE powerpc ppc4xx 2da8137b 2015-03-17 Stephen Williams <steve@icarus.com> +BC3450 powerpc mpc5xxx f8296d69 2015-03-17 hawkboard arm arm926ejs cb957cda 2015-02-24 Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com> tnetv107x arm arm1176 50b82c4b 2015-02-24 Chan-Taek Park <c-park@ti.com> a320evb arm arm920t 29fc6f24 2015-02-24 Po-Yu Chuang <ratbert@faraday-tech.com> diff --git a/doc/device-tree-bindings/gpu/nvidia,tegra20-host1x.txt b/doc/device-tree-bindings/gpu/nvidia,tegra20-host1x.txt new file mode 100644 index 0000000..b48f4ef --- /dev/null +++ b/doc/device-tree-bindings/gpu/nvidia,tegra20-host1x.txt @@ -0,0 +1,372 @@ +NVIDIA Tegra host1x + +Required properties: +- compatible: "nvidia,tegra<chip>-host1x" +- reg: Physical base address and length of the controller's registers. +- interrupts: The interrupt outputs from the controller. +- #address-cells: The number of cells used to represent physical base addresses + in the host1x address space. Should be 1. +- #size-cells: The number of cells used to represent the size of an address + range in the host1x address space. Should be 1. +- ranges: The mapping of the host1x address space to the CPU address space. +- clocks: Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the following entries: + - host1x + +The host1x top-level node defines a number of children, each representing one +of the following host1x client modules: + +- mpe: video encoder + + Required properties: + - compatible: "nvidia,tegra<chip>-mpe" + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - clocks: Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - mpe + +- vi: video input + + Required properties: + - compatible: "nvidia,tegra<chip>-vi" + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - clocks: Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - vi + +- epp: encoder pre-processor + + Required properties: + - compatible: "nvidia,tegra<chip>-epp" + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - clocks: Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - epp + +- isp: image signal processor + + Required properties: + - compatible: "nvidia,tegra<chip>-isp" + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - clocks: Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - isp + +- gr2d: 2D graphics engine + + Required properties: + - compatible: "nvidia,tegra<chip>-gr2d" + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - clocks: Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - 2d + +- gr3d: 3D graphics engine + + Required properties: + - compatible: "nvidia,tegra<chip>-gr3d" + - reg: Physical base address and length of the controller's registers. + - clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must include the following entries: + (This property may be omitted if the only clock in the list is "3d") + - 3d + This MUST be the first entry. + - 3d2 (Only required on SoCs with two 3D clocks) + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - 3d + - 3d2 (Only required on SoCs with two 3D clocks) + +- dc: display controller + + Required properties: + - compatible: "nvidia,tegra<chip>-dc" + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must include the following entries: + - dc + This MUST be the first entry. + - parent + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - dc + - nvidia,head: The number of the display controller head. This is used to + setup the various types of output to receive video data from the given + head. + + Each display controller node has a child node, named "rgb", that represents + the RGB output associated with the controller. It can take the following + optional properties: + - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing + - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection + - nvidia,edid: supplies a binary EDID blob + - nvidia,panel: phandle of a display panel + +- hdmi: High Definition Multimedia Interface + + Required properties: + - compatible: "nvidia,tegra<chip>-hdmi" + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - hdmi-supply: supply for the +5V HDMI connector pin + - vdd-supply: regulator for supply voltage + - pll-supply: regulator for PLL + - clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must include the following entries: + - hdmi + This MUST be the first entry. + - parent + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - hdmi + + Optional properties: + - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing + - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection + - nvidia,edid: supplies a binary EDID blob + - nvidia,panel: phandle of a display panel + +- tvo: TV encoder output + + Required properties: + - compatible: "nvidia,tegra<chip>-tvo" + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - clocks: Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + +- dsi: display serial interface + + Required properties: + - compatible: "nvidia,tegra<chip>-dsi" + - reg: Physical base address and length of the controller's registers. + - clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must include the following entries: + - dsi + This MUST be the first entry. + - lp + - parent + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - dsi + - avdd-dsi-supply: phandle of a supply that powers the DSI controller + - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying + which pads are used by this DSI output and need to be calibrated. See also + ../mipi/nvidia,tegra114-mipi.txt. + + Optional properties: + - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing + - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection + - nvidia,edid: supplies a binary EDID blob + - nvidia,panel: phandle of a display panel + +- sor: serial output resource + + Required properties: + - compatible: "nvidia,tegra124-sor" + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must include the following entries: + - sor: clock input for the SOR hardware + - parent: input for the pixel clock + - dp: reference clock for the SOR clock + - safe: safe reference for the SOR clock during power up + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - sor + + Optional properties: + - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing + - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection + - nvidia,edid: supplies a binary EDID blob + - nvidia,panel: phandle of a display panel + + Optional properties when driving an eDP output: + - nvidia,dpaux: phandle to a DispayPort AUX interface + +- dpaux: DisplayPort AUX interface + - compatible: "nvidia,tegra124-dpaux" + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must include the following entries: + - dpaux: clock input for the DPAUX hardware + - parent: reference clock + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - dpaux + - vdd-supply: phandle of a supply that powers the DisplayPort link + +Example: + +/ { + ... + + host1x { + compatible = "nvidia,tegra20-host1x", "simple-bus"; + reg = <0x50000000 0x00024000>; + interrupts = <0 65 0x04 /* mpcore syncpt */ + 0 67 0x04>; /* mpcore general */ + clocks = <&tegra_car TEGRA20_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x04000000>; + + mpe { + compatible = "nvidia,tegra20-mpe"; + reg = <0x54040000 0x00040000>; + interrupts = <0 68 0x04>; + clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&tegra_car 60>; + reset-names = "mpe"; + }; + + vi { + compatible = "nvidia,tegra20-vi"; + reg = <0x54080000 0x00040000>; + interrupts = <0 69 0x04>; + clocks = <&tegra_car TEGRA20_CLK_VI>; + resets = <&tegra_car 100>; + reset-names = "vi"; + }; + + epp { + compatible = "nvidia,tegra20-epp"; + reg = <0x540c0000 0x00040000>; + interrupts = <0 70 0x04>; + clocks = <&tegra_car TEGRA20_CLK_EPP>; + resets = <&tegra_car 19>; + reset-names = "epp"; + }; + + isp { + compatible = "nvidia,tegra20-isp"; + reg = <0x54100000 0x00040000>; + interrupts = <0 71 0x04>; + clocks = <&tegra_car TEGRA20_CLK_ISP>; + resets = <&tegra_car 23>; + reset-names = "isp"; + }; + + gr2d { + compatible = "nvidia,tegra20-gr2d"; + reg = <0x54140000 0x00040000>; + interrupts = <0 72 0x04>; + clocks = <&tegra_car TEGRA20_CLK_GR2D>; + resets = <&tegra_car 21>; + reset-names = "2d"; + }; + + gr3d { + compatible = "nvidia,tegra20-gr3d"; + reg = <0x54180000 0x00040000>; + clocks = <&tegra_car TEGRA20_CLK_GR3D>; + resets = <&tegra_car 24>; + reset-names = "3d"; + }; + + dc@54200000 { + compatible = "nvidia,tegra20-dc"; + reg = <0x54200000 0x00040000>; + interrupts = <0 73 0x04>; + clocks = <&tegra_car TEGRA20_CLK_DISP1>, + <&tegra_car TEGRA20_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; + + rgb { + status = "disabled"; + }; + }; + + dc@54240000 { + compatible = "nvidia,tegra20-dc"; + reg = <0x54240000 0x00040000>; + interrupts = <0 74 0x04>; + clocks = <&tegra_car TEGRA20_CLK_DISP2>, + <&tegra_car TEGRA20_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; + + rgb { + status = "disabled"; + }; + }; + + hdmi { + compatible = "nvidia,tegra20-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = <0 75 0x04>; + clocks = <&tegra_car TEGRA20_CLK_HDMI>, + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; + status = "disabled"; + }; + + tvo { + compatible = "nvidia,tegra20-tvo"; + reg = <0x542c0000 0x00040000>; + interrupts = <0 76 0x04>; + clocks = <&tegra_car TEGRA20_CLK_TVO>; + status = "disabled"; + }; + + dsi { + compatible = "nvidia,tegra20-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA20_CLK_DSI>, + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + status = "disabled"; + }; + }; + + ... +}; diff --git a/doc/device-tree-bindings/pmic/max77686.txt b/doc/device-tree-bindings/pmic/max77686.txt new file mode 100644 index 0000000..09aee64 --- /dev/null +++ b/doc/device-tree-bindings/pmic/max77686.txt @@ -0,0 +1,35 @@ +MAXIM, MAX77686 pmic + +This device uses two drivers: +- drivers/power/pmic/max77686.c (for parent device) +- drivers/power/regulator/max77686.c (for child regulators) + +This file describes the binding info for the PMIC driver. + +To bind the regulators, please read the additional binding info: +- doc/device-tree-bindings/regulator/max77686.txt + +Required properties: +- compatible: "maxim,max77686" +- reg = 0x9 + +With those two properties, the pmic device can be used for read/write only. +To bind each regulator, the optional regulators subnode should exists. + +Optional subnode: +- voltage-regulators: subnode list of each device's regulator + (see max77686.txt - regulator binding info) + +Example: + +max77686@09 { + compatible = "maxim,max77686"; + reg = <0x09>; + + voltage-regulators { + ldo1 { + ... + }; + ... + }; +}; diff --git a/doc/device-tree-bindings/pmic/sandbox.txt b/doc/device-tree-bindings/pmic/sandbox.txt new file mode 100644 index 0000000..d84c977 --- /dev/null +++ b/doc/device-tree-bindings/pmic/sandbox.txt @@ -0,0 +1,35 @@ +Sandbox pmic + +This device uses two drivers: +- drivers/power/pmic/sandbox.c (for parent device) +- drivers/power/regulator/sandbox.c (for child regulators) + +This file describes the binding info for the PMIC driver. + +To bind the regulators, please read the regulator binding info: +- doc/device-tree-bindings/regulator/sandbox.txt + +Required PMIC node properties: +- compatible: "sandbox,pmic" +- reg = 0x40 + +Required PMIC's "emul" subnode, with property: +- compatible: "sandbox,i2c-pmic" + +With the above properties, the pmic device can be used for read/write only. +To bind each regulator, the optional regulator subnodes should exists. + +Optional subnodes: +- ldo/buck subnodes of each device's regulator (see regulator binding info) + +Example: + +sandbox_pmic { + compatible = "sandbox,pmic"; + reg = <0x40>; + + /* Mandatory for I/O */ + emul { + compatible = "sandbox,i2c-pmic"; + }; +}; diff --git a/doc/device-tree-bindings/regulator/fixed.txt b/doc/device-tree-bindings/regulator/fixed.txt new file mode 100644 index 0000000..4ff39b8 --- /dev/null +++ b/doc/device-tree-bindings/regulator/fixed.txt @@ -0,0 +1,38 @@ +Fixed Voltage regulator + +Binding: +The binding is done by the property "compatible" - this is different, than for +binding by the node prefix (doc/device-tree-bindings/regulator/regulator.txt). + +Required properties: +- compatible: "regulator-fixed" +- regulator-name: this is required by the regulator uclass + +Optional properties: +- gpio: GPIO to use for enable control +- regulator constraints (binding info: regulator.txt) + +Other kernel-style properties, are currently not used. + +Note: +For the regulator constraints, driver expects that: +- regulator-min-microvolt is equal to regulator-max-microvolt +- regulator-min-microamp is equal to regulator-max-microamp + +Example: +fixed_regulator@0 { + /* Mandatory */ + compatible = "regulator-fixed"; + regulator-name = "LED_3.3V"; + + /* Optional: */ + gpio = <&gpc1 0 GPIO_ACTIVE_LOW>; + + /* Optional for regulator uclass */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-min-microamp = <15000>; + regulator-max-microamp = <15000>; + regulator-always-on; + regulator-boot-on; +}; diff --git a/doc/device-tree-bindings/regulator/max77686.txt b/doc/device-tree-bindings/regulator/max77686.txt new file mode 100644 index 0000000..ae9b1b6 --- /dev/null +++ b/doc/device-tree-bindings/regulator/max77686.txt @@ -0,0 +1,70 @@ +MAXIM, MAX77686 regulators + +This device uses two drivers: +- drivers/power/pmic/max77686.c (as parent I/O device) +- drivers/power/regulator/max77686.c (for child regulators) + +This file describes the binding info for the REGULATOR driver. + +First, please read the binding info for the pmic: +- doc/device-tree-bindings/pmic/max77686.txt + +Required subnode: +- voltage-regulators: required for the PMIC driver + +Required properties: +- regulator-name: used for regulator uclass platform data '.name' + +Optional: +- regulator-min-microvolt: minimum allowed Voltage to set +- regulator-max-microvolt: minimum allowed Voltage to set +- regulator-always-on: regulator should be never disabled +- regulator-boot-on: regulator should be enabled by the bootloader + +Example: +(subnode of max77686 pmic node) +voltage-regulators { + ldo1 { + regulator-name = "VDD_ALIVE_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2 { + regulator-name = "VDDQ_VM1M2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + . + . + . + ldo26 { + regulator-name = "nc"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + buck1 { + regulator-compatible = "BUCK1"; + regulator-name = "VDD_MIF_1.0V"; + regulator-min-microvolt = <8500000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + . + . + . + buck9 { + regulator-compatible = "BUCK9"; + regulator-name = "nc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; +}; diff --git a/doc/device-tree-bindings/regulator/regulator.txt b/doc/device-tree-bindings/regulator/regulator.txt new file mode 100644 index 0000000..68b02a8 --- /dev/null +++ b/doc/device-tree-bindings/regulator/regulator.txt @@ -0,0 +1,54 @@ +Voltage/Current regulator + +Binding: +The regulator devices don't use the "compatible" property. The binding is done +by the prefix of regulator node's name. Usually the pmic I/O driver will provide +the array of 'struct pmic_child_info' with the prefixes and compatible drivers. +The bind is done by calling function: pmic_bind_childs(). +Example drivers: +pmic: drivers/power/pmic/max77686.c +regulator: drivers/power/regulator/max77686.c + +For the node name e.g.: "prefix[:alpha:]num { ... }": +- the driver prefix should be: "prefix" or "PREFIX" - case insensitive +- the node name's "num" is set as "dev->driver_data" on bind + +Example the prefix "ldo" will pass for: "ldo1", "ldo@1", "LDO1", "LDOREG@1"... + +Required properties: +- regulator-name: a string, required by the regulator uclass + +Note +The "regulator-name" constraint is used for setting the device's uclass +platform data '.name' field. And the regulator device name is set from +it's node name. + +Optional properties: +- regulator-min-microvolt: a minimum allowed Voltage value +- regulator-max-microvolt: a maximum allowed Voltage value +- regulator-min-microamp: a minimum allowed Current value +- regulator-max-microamp: a maximum allowed Current value +- regulator-always-on: regulator should never be disabled +- regulator-boot-on: enabled by bootloader/firmware + +Other kernel-style properties, are currently not used. + +Note: +For the regulator autoset from constraints, the framework expects that: +- regulator-min-microvolt is equal to regulator-max-microvolt +- regulator-min-microamp is equal to regulator-max-microamp +- regulator-always-on or regulator-boot-on is set + +Example: +ldo0 { + /* Mandatory */ + regulator-name = "VDDQ_EMMC_1.8V"; + + /* Optional */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-min-microamp = <100000>; + regulator-max-microamp = <100000>; + regulator-always-on; + regulator-boot-on; +}; diff --git a/doc/device-tree-bindings/regulator/sandbox.txt b/doc/device-tree-bindings/regulator/sandbox.txt new file mode 100644 index 0000000..d70494c --- /dev/null +++ b/doc/device-tree-bindings/regulator/sandbox.txt @@ -0,0 +1,45 @@ +Sandbox, PMIC regulators + +This device uses two drivers: +- drivers/power/pmic/sandbox.c (as parent I/O device) +- drivers/power/regulator/sandbox.c (for child regulators) + +This file describes the binding info for the REGULATOR driver. + +First, please read the binding info for the PMIC: +- doc/device-tree-bindings/pmic/sandbox.txt + +Required subnodes: +- ldoN { }; +- buckN { }; + +The sandbox PMIC can support: ldo1, ldo2, buck1, buck2. + +For each PMIC's regulator subnode, there is one required property: +- regulator-name: used for regulator uclass platform data '.name' + +Optional: +- regulator-min-microvolt: minimum allowed Voltage to set +- regulator-max-microvolt: minimum allowed Voltage to set +- regulator-min-microamps: minimum allowed Current limit to set (LDO1/BUCK1) +- regulator-max-microamps: minimum allowed Current limit to set (LDO1/BUCK1) +- regulator-always-on: regulator should be never disabled +- regulator-boot-on: regulator should be enabled by the bootloader + +Example PMIC's regulator subnodes: + +ldo1 { + regulator-name = "VDD_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamps = <100000>; + regulator-max-microamps = <400000>; + regulator-always-on; +}; + +buck2 { + regulator-name = "VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; +}; diff --git a/doc/device-tree-bindings/serial/pl01x.txt b/doc/device-tree-bindings/serial/pl01x.txt new file mode 100644 index 0000000..61c27d1 --- /dev/null +++ b/doc/device-tree-bindings/serial/pl01x.txt @@ -0,0 +1,7 @@ +* ARM AMBA Primecell PL011 & PL010 serial UART + +Required properties: +- compatible: must be "arm,primecell", "arm,pl011" or "arm,pl010" +- reg: exactly one register range with length 0x1000 +- clock: input clock frequency for the UART (used to calculate the baud + rate divisor) diff --git a/doc/device-tree-bindings/video/display-timing.txt b/doc/device-tree-bindings/video/display-timing.txt new file mode 100644 index 0000000..e1d4a0b --- /dev/null +++ b/doc/device-tree-bindings/video/display-timing.txt @@ -0,0 +1,110 @@ +display-timing bindings +======================= + +display-timings node +-------------------- + +required properties: + - none + +optional properties: + - native-mode: The native mode for the display, in case multiple modes are + provided. When omitted, assume the first node is the native. + +timing subnode +-------------- + +required properties: + - hactive, vactive: display resolution + - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters + in pixels + vfront-porch, vback-porch, vsync-len: vertical display timing parameters in + lines + - clock-frequency: display clock in Hz + +optional properties: + - hsync-active: hsync pulse is active low/high/ignored + - vsync-active: vsync pulse is active low/high/ignored + - de-active: data-enable pulse is active low/high/ignored + - pixelclk-active: with + - active high = drive pixel data on rising edge/ + sample data on falling edge + - active low = drive pixel data on falling edge/ + sample data on rising edge + - ignored = ignored + - interlaced (bool): boolean to enable interlaced mode + - doublescan (bool): boolean to enable doublescan mode + - doubleclk (bool): boolean to enable doubleclock mode + +All the optional properties that are not bool follow the following logic: + <1>: high active + <0>: low active + omitted: not used on hardware + +There are different ways of describing the capabilities of a display. The +devicetree representation corresponds to the one commonly found in datasheets +for displays. If a display supports multiple signal timings, the native-mode +can be specified. + +The parameters are defined as: + + +----------+-------------------------------------+----------+-------+ + | | ↑ | | | + | | |vback_porch | | | + | | ↓ | | | + +----------#######################################----------+-------+ + | # ↑ # | | + | # | # | | + | hback # | # hfront | hsync | + | porch # | hactive # porch | len | + |<-------->#<-------+--------------------------->#<-------->|<----->| + | # | # | | + | # |vactive # | | + | # | # | | + | # ↓ # | | + +----------#######################################----------+-------+ + | | ↑ | | | + | | |vfront_porch | | | + | | ↓ | | | + +----------+-------------------------------------+----------+-------+ + | | ↑ | | | + | | |vsync_len | | | + | | ↓ | | | + +----------+-------------------------------------+----------+-------+ + +Example: + + display-timings { + native-mode = <&timing0>; + timing0: 1080p24 { + /* 1920x1080p24 */ + clock-frequency = <52000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <25>; + hback-porch = <25>; + hsync-len = <25>; + vback-porch = <2>; + vfront-porch = <2>; + vsync-len = <2>; + hsync-active = <1>; + }; + }; + +Every required property also supports the use of ranges, so the commonly used +datasheet description with minimum, typical and maximum values can be used. + +Example: + + timing1: timing { + /* 1920x1080p24 */ + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hsync-len = <0 44 60>; + hfront-porch = <80 88 95>; + hback-porch = <100 148 160>; + vfront-porch = <0 4 6>; + vback-porch = <0 36 50>; + vsync-len = <0 5 6>; + }; diff --git a/doc/driver-model/pmic-framework.txt b/doc/driver-model/pmic-framework.txt new file mode 100644 index 0000000..95b1a66 --- /dev/null +++ b/doc/driver-model/pmic-framework.txt @@ -0,0 +1,140 @@ +# +# (C) Copyright 2014-2015 Samsung Electronics +# Przemyslaw Marczak <p.marczak@samsung.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +PMIC framework based on Driver Model +==================================== +TOC: +1. Introduction +2. How does it work +3. Pmic uclass +4. Regulator uclass + +1. Introduction +=============== +This is an introduction to driver-model multi uclass PMIC IC's support. +At present it's based on two uclass types: +- UCLASS_PMIC - basic uclass type for PMIC I/O, which provides common + read/write interface. +- UCLASS_REGULATOR - additional uclass type for specific PMIC features, + which are Voltage/Current regulators. + +New files: +UCLASS_PMIC: +- drivers/power/pmic/pmic-uclass.c +- include/power/pmic.h +UCLASS_REGULATOR: +- drivers/power/regulator/regulator-uclass.c +- include/power/regulator.h + +Commands: +- common/cmd_pmic.c +- common/cmd_regulator.c + +2. How doees it work +==================== +The Power Management Integrated Circuits (PMIC) are used in embedded systems +to provide stable, precise and specific voltage power source with over-voltage +and thermal protection circuits. + +The single PMIC can provide various functions by single or multiple interfaces, +like in the example below. + +-- SoC + | + | ______________________________________ + | BUS 0 | Multi interface PMIC IC |--> LDO out 1 + | e.g.I2C0 | |--> LDO out N + |-----------|---- PMIC device 0 (READ/WRITE ops) | + | or SPI0 | |_ REGULATOR device (ldo/... ops) |--> BUCK out 1 + | | |_ CHARGER device (charger ops) |--> BUCK out M + | | |_ MUIC device (microUSB con ops) | + | BUS 1 | |_ ... |---> BATTERY + | e.g.I2C1 | | + |-----------|---- PMIC device 1 (READ/WRITE ops) |---> USB in 1 + . or SPI1 | |_ RTC device (rtc ops) |---> USB in 2 + . |______________________________________|---> USB out + . + +Since U-Boot provides driver model features for I2C and SPI bus drivers, +the PMIC devices should also support this. By the pmic and regulator API's, +PMIC drivers can simply provide a common functions, for multi-interface and +and multi-instance device support. + +Basic design assumptions: + +- Common I/O API - UCLASS_PMIC +For the multi-function PMIC devices, this can be used as parent I/O device +for each IC's interface. Then, each children uses the same dev for read/write. + +- Common regulator API - UCLASS_REGULATOR +For driving the regulator attributes, auto setting function or command line +interface, based on kernel-style regulator device tree constraints. + +For simple implementations, regulator drivers are not required, so the code can +use pmic read/write directly. + +3. Pmic uclass +============== +The basic information: +* Uclass: 'UCLASS_PMIC' +* Header: 'include/power/pmic.h' +* Core: 'drivers/power/pmic/pmic-uclass.c' + config: 'CONFIG_DM_PMIC' +* Command: 'common/cmd_pmic.c' + config: 'CONFIG_CMD_PMIC' +* Example: 'drivers/power/pmic/max77686.c' + +For detailed API description, please refer to the header file. + +As an example of the pmic driver, please refer to the MAX77686 driver. + +Please pay attention for the driver's bind() method. Exactly the function call: +'pmic_bind_children()', which is used to bind the regulators by using the array +of regulator's node, compatible prefixes. + +The 'pmic; command also supports the new API. So the pmic command can be enabled +by adding CONFIG_CMD_PMIC. +The new pmic command allows to: +- list pmic devices +- choose the current device (like the mmc command) +- read or write the pmic register +- dump all pmic registers + +This command can use only UCLASS_PMIC devices, since this uclass is designed +for pmic I/O operations only. + +For more information, please refer to the core file. + +4. Regulator uclass +=================== +The basic information: +* Uclass: 'UCLASS_REGULATOR' +* Header: 'include/power/regulator.h' +* Core: 'drivers/power/regulator/regulator-uclass.c' + config: 'CONFIG_DM_REGULATOR' + binding: 'doc/device-tree-bindings/regulator/regulator.txt' +* Command: 'common/cmd_regulator.c' + config: 'CONFIG_CMD_REGULATOR' +* Example: 'drivers/power/regulator/max77686.c' + 'drivers/power/pmic/max77686.c' (required I/O driver for the above) +* Example: 'drivers/power/regulator/fixed.c' + config" 'CONFIG_DM_REGULATOR_FIXED' + +For detailed API description, please refer to the header file. + +For the example regulator driver, please refer to the MAX77686 regulator driver, +but this driver can't operate without pmic's example driver, which provides an +I/O interface for MAX77686 regulator. + +The second example is a fixed Voltage/Current regulator for a common use. + +The 'regulator' command also supports the new API. The command allow: +- list regulator devices +- choose the current device (like the mmc command) +- do all regulator-specific operations + +For more information, please refer to the command file. diff --git a/doc/git-mailrc b/doc/git-mailrc index 174109f..598bb3e 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -22,7 +22,7 @@ alias gruss Graeme Russ <graeme.russ@gmail.com> alias hs Heiko Schocher <hs@denx.de> alias ijc Ian Campbell <ijc+uboot@hellion.org.uk> alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -alias jagan Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> +alias jagan Jagan Teki <jteki@openedev.com> alias jasonjin Jason Jin <jason.jin@freescale.com> alias jhersh Joe Hershberger <joe.hershberger@ni.com> alias jwrdegoede Hans de Goede <hdegoede@redhat.com> @@ -64,6 +64,7 @@ alias rmobile uboot, iwamatsu alias s3c samsung alias s5pc samsung alias samsung uboot, prom +alias socfpga uboot, marex, Dinh Nguyen <dinguyen@opensource.altera.com> alias sunxi uboot, ijc, jwrdegoede alias tegra uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com> alias tegra2 tegra diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 381868b..530bb3e 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -495,22 +495,54 @@ int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize) return 0; } +int gpio_claim_vector(const int *gpio_num_array, const char *fmt) +{ + int i, ret; + int gpio; + + for (i = 0; i < 32; i++) { + gpio = gpio_num_array[i]; + if (gpio == -1) + break; + ret = gpio_requestf(gpio, fmt, i); + if (ret) + goto err; + ret = gpio_direction_input(gpio); + if (ret) { + gpio_free(gpio); + goto err; + } + } + + return 0; +err: + for (i--; i >= 0; i--) + gpio_free(gpio_num_array[i]); + + return ret; +} + /* * get a number comprised of multiple GPIO values. gpio_num_array points to * the array of gpio pin numbers to scan, terminated by -1. */ -unsigned gpio_get_values_as_int(const int *gpio_num_array) +int gpio_get_values_as_int(const int *gpio_list) { int gpio; unsigned bitmask = 1; unsigned vector = 0; + int ret; while (bitmask && - ((gpio = *gpio_num_array++) != -1)) { - if (gpio_get_value(gpio)) + ((gpio = *gpio_list++) != -1)) { + ret = gpio_get_value(gpio); + if (ret < 0) + return ret; + else if (ret) vector |= bitmask; bitmask <<= 1; } + return vector; } diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c index d3497e9..6d6fdb0 100644 --- a/drivers/gpio/stm32_gpio.c +++ b/drivers/gpio/stm32_gpio.c @@ -69,22 +69,14 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc, setbits_le32(&STM32_RCC->ahb1enr, 1 << dsc->port); i = (dsc->pin & 0x07) * 4; - clrbits_le32(&gpio_regs->afr[dsc->pin >> 3], (0xF << i)); - setbits_le32(&gpio_regs->afr[dsc->pin >> 3], ctl->af << i); + clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i); i = dsc->pin * 2; - clrbits_le32(&gpio_regs->moder, (0x3 << i)); - setbits_le32(&gpio_regs->moder, ctl->mode << i); - - clrbits_le32(&gpio_regs->otyper, (0x3 << i)); - setbits_le32(&gpio_regs->otyper, ctl->otype << i); - - clrbits_le32(&gpio_regs->ospeedr, (0x3 << i)); - setbits_le32(&gpio_regs->ospeedr, ctl->speed << i); - - clrbits_le32(&gpio_regs->pupdr, (0x3 << i)); - setbits_le32(&gpio_regs->pupdr, ctl->pupd << i); + clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i); + clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i); + clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i); + clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i); rv = 0; out: diff --git a/drivers/i2c/i2c-gpio.c b/drivers/i2c/i2c-gpio.c index ed899d4..a8b83c5 100644 --- a/drivers/i2c/i2c-gpio.c +++ b/drivers/i2c/i2c-gpio.c @@ -41,18 +41,19 @@ static int i2c_gpio_sda_get(struct gpio_desc *sda) static void i2c_gpio_sda_set(struct gpio_desc *sda, int bit) { - if (bit) { + if (bit) dm_gpio_set_dir_flags(sda, GPIOD_IS_IN); - } else { + else dm_gpio_set_dir_flags(sda, GPIOD_IS_OUT); - dm_gpio_set_value(sda, 0); - } } static void i2c_gpio_scl_set(struct gpio_desc *scl, int bit) { - dm_gpio_set_dir_flags(scl, GPIOD_IS_OUT); - dm_gpio_set_value(scl, bit); + ulong flags = GPIOD_IS_OUT; + + if (bit) + flags |= GPIOD_IS_OUT_ACTIVE; + dm_gpio_set_dir_flags(scl, flags); } static void i2c_gpio_write_bit(struct gpio_desc *scl, struct gpio_desc *sda, diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index f2e95c0..eaba965 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -186,6 +186,25 @@ int dm_i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer, } } +int dm_i2c_reg_read(struct udevice *dev, uint offset) +{ + uint8_t val; + int ret; + + ret = dm_i2c_read(dev, offset, &val, 1); + if (ret < 0) + return ret; + + return val; +} + +int dm_i2c_reg_write(struct udevice *dev, uint offset, uint value) +{ + uint8_t val = value; + + return dm_i2c_write(dev, offset, &val, 1); +} + /** * i2c_probe_chip() - probe for a chip on a bus * @@ -396,6 +415,13 @@ int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len) return 0; } +int i2c_get_chip_offset_len(struct udevice *dev) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + + return chip->offset_len; +} + int i2c_deblock(struct udevice *bus) { struct dm_i2c_ops *ops = i2c_get_ops(bus); diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 42782cb..81adf6f 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -18,29 +18,25 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/errno.h> +#include <asm/imx-common/mxc_i2c.h> #include <asm/io.h> #include <i2c.h> #include <watchdog.h> +#include <dm.h> +#include <fdtdec.h> DECLARE_GLOBAL_DATA_PTR; -#ifdef I2C_QUIRK_REG -struct mxc_i2c_regs { - uint8_t iadr; - uint8_t ifdr; - uint8_t i2cr; - uint8_t i2sr; - uint8_t i2dr; -}; -#else -struct mxc_i2c_regs { - uint32_t iadr; - uint32_t ifdr; - uint32_t i2cr; - uint32_t i2sr; - uint32_t i2dr; -}; -#endif +#define I2C_QUIRK_FLAG (1 << 0) + +#define IMX_I2C_REGSHIFT 2 +#define VF610_I2C_REGSHIFT 0 +/* Register index */ +#define IADR 0 +#define IFDR 1 +#define I2CR 2 +#define I2SR 3 +#define I2DR 4 #define I2CR_IIEN (1 << 6) #define I2CR_MSTA (1 << 5) @@ -104,7 +100,6 @@ static u16 i2c_clk_div[50][2] = { }; #endif - #ifndef CONFIG_SYS_MXC_I2C1_SPEED #define CONFIG_SYS_MXC_I2C1_SPEED 100000 #endif @@ -131,11 +126,10 @@ static u16 i2c_clk_div[50][2] = { #define CONFIG_SYS_MXC_I2C4_SLAVE 0 #endif - /* * Calculate and set proper clock divider */ -static uint8_t i2c_imx_get_clk(unsigned int rate) +static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate) { unsigned int i2c_clk_rate; unsigned int div; @@ -168,18 +162,20 @@ static uint8_t i2c_imx_get_clk(unsigned int rate) /* * Set I2C Bus speed */ -static int bus_i2c_set_bus_speed(void *base, int speed) +static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed) { - struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; - u8 clk_idx = i2c_imx_get_clk(speed); + ulong base = i2c_bus->base; + bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; + u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed); u8 idx = i2c_clk_div[clk_idx][1]; + int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; /* Store divider value */ - writeb(idx, &i2c_regs->ifdr); + writeb(idx, base + (IFDR << reg_shift)); /* Reset module */ - writeb(I2CR_IDIS, &i2c_regs->i2cr); - writeb(0, &i2c_regs->i2sr); + writeb(I2CR_IDIS, base + (I2CR << reg_shift)); + writeb(0, base + (I2SR << reg_shift)); return 0; } @@ -187,21 +183,26 @@ static int bus_i2c_set_bus_speed(void *base, int speed) #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8)) #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8)) -static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state) +static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state) { unsigned sr; ulong elapsed; + bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; + int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + ulong base = i2c_bus->base; ulong start_time = get_timer(0); for (;;) { - sr = readb(&i2c_regs->i2sr); + sr = readb(base + (I2SR << reg_shift)); if (sr & I2SR_IAL) { -#ifdef I2C_QUIRK_REG - writeb(sr | I2SR_IAL, &i2c_regs->i2sr); -#else - writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr); -#endif + if (quirk) + writeb(sr | I2SR_IAL, base + + (I2SR << reg_shift)); + else + writeb(sr & ~I2SR_IAL, base + + (I2SR << reg_shift)); printf("%s: Arbitration lost sr=%x cr=%x state=%x\n", - __func__, sr, readb(&i2c_regs->i2cr), state); + __func__, sr, readb(base + (I2CR << reg_shift)), + state); return -ERESTART; } if ((sr & (state >> 8)) == (unsigned char)state) @@ -212,17 +213,21 @@ static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state) break; } printf("%s: failed sr=%x cr=%x state=%x\n", __func__, - sr, readb(&i2c_regs->i2cr), state); + sr, readb(base + (I2CR << reg_shift)), state); return -ETIMEDOUT; } -static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) +static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte) { int ret; + int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? + VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + ulong base = i2c_bus->base; - writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); - writeb(byte, &i2c_regs->i2dr); - ret = wait_for_sr_state(i2c_regs, ST_IIF); + writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); + writeb(byte, base + (I2DR << reg_shift)); + + ret = wait_for_sr_state(i2c_bus, ST_IIF); if (ret < 0) return ret; if (ret & I2SR_RX_NO_AK) @@ -231,16 +236,28 @@ static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) } /* + * Stub implementations for outer i2c slave operations. + */ +void __i2c_force_reset_slave(void) +{ +} +void i2c_force_reset_slave(void) + __attribute__((weak, alias("__i2c_force_reset_slave"))); + +/* * Stop I2C transaction */ -static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs) +static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus) { int ret; - unsigned int temp = readb(&i2c_regs->i2cr); + int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? + VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + ulong base = i2c_bus->base; + unsigned int temp = readb(base + (I2CR << reg_shift)); temp &= ~(I2CR_MSTA | I2CR_MTX); - writeb(temp, &i2c_regs->i2cr); - ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); + writeb(temp, base + (I2CR << reg_shift)); + ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE); if (ret < 0) printf("%s:trigger stop failed\n", __func__); } @@ -249,66 +266,96 @@ static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs) * Send start signal, chip address and * write register address */ -static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs, - uchar chip, uint addr, int alen) +static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip, + u32 addr, int alen) { unsigned int temp; int ret; + bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; + ulong base = i2c_bus->base; + int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + + /* Reset i2c slave */ + i2c_force_reset_slave(); /* Enable I2C controller */ -#ifdef I2C_QUIRK_REG - if (readb(&i2c_regs->i2cr) & I2CR_IDIS) { -#else - if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) { -#endif - writeb(I2CR_IEN, &i2c_regs->i2cr); + if (quirk) + ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS; + else + ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN); + + if (ret) { + writeb(I2CR_IEN, base + (I2CR << reg_shift)); /* Wait for controller to be stable */ udelay(50); } - if (readb(&i2c_regs->iadr) == (chip << 1)) - writeb((chip << 1) ^ 2, &i2c_regs->iadr); - writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); - ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); + + if (readb(base + (IADR << reg_shift)) == (chip << 1)) + writeb((chip << 1) ^ 2, base + (IADR << reg_shift)); + writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); + ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE); if (ret < 0) return ret; /* Start I2C transaction */ - temp = readb(&i2c_regs->i2cr); + temp = readb(base + (I2CR << reg_shift)); temp |= I2CR_MSTA; - writeb(temp, &i2c_regs->i2cr); + writeb(temp, base + (I2CR << reg_shift)); - ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY); + ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY); if (ret < 0) return ret; temp |= I2CR_MTX | I2CR_TX_NO_AK; - writeb(temp, &i2c_regs->i2cr); + writeb(temp, base + (I2CR << reg_shift)); /* write slave address */ - ret = tx_byte(i2c_regs, chip << 1); + ret = tx_byte(i2c_bus, chip << 1); if (ret < 0) return ret; while (alen--) { - ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff); + ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff); if (ret < 0) return ret; } return 0; } -static int i2c_idle_bus(void *base); +#ifndef CONFIG_DM_I2C +int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) +{ + if (i2c_bus && i2c_bus->idle_bus_fn) + return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data); + return 0; +} +#else +/* + * Since pinmux is not supported, implement a weak function here. + * You can implement your i2c_bus_idle in board file. When pinctrl + * is supported, this can be removed. + */ +int __i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) +{ + return 0; +} -static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs, - uchar chip, uint addr, int alen) +int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) + __attribute__((weak, alias("__i2c_idle_bus"))); +#endif + +static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip, + u32 addr, int alen) { int retry; int ret; + int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? + VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; for (retry = 0; retry < 3; retry++) { - ret = i2c_init_transfer_(i2c_regs, chip, addr, alen); + ret = i2c_init_transfer_(i2c_bus, chip, addr, alen); if (ret >= 0) return 0; - i2c_imx_stop(i2c_regs); + i2c_imx_stop(i2c_bus); if (ret == -ENODEV) return ret; @@ -316,54 +363,67 @@ static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs, retry); if (ret != -ERESTART) /* Disable controller */ - writeb(I2CR_IDIS, &i2c_regs->i2cr); + writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift)); udelay(100); - if (i2c_idle_bus(i2c_regs) < 0) + if (i2c_idle_bus(i2c_bus) < 0) break; } - printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs); + printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base); return ret; } -/* - * Read data from I2C device - */ -int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, - int len) + +static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf, + int len) +{ + int i, ret = 0; + + debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); + debug("write_data: "); + /* use rc for counter */ + for (i = 0; i < len; ++i) + debug(" 0x%02x", buf[i]); + debug("\n"); + + for (i = 0; i < len; i++) { + ret = tx_byte(i2c_bus, buf[i]); + if (ret < 0) { + debug("i2c_write_data(): rc=%d\n", ret); + break; + } + } + + return ret; +} + +static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf, + int len) { int ret; unsigned int temp; int i; - struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; - - ret = i2c_init_transfer(i2c_regs, chip, addr, alen); - if (ret < 0) - return ret; + int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? + VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + ulong base = i2c_bus->base; - temp = readb(&i2c_regs->i2cr); - temp |= I2CR_RSTA; - writeb(temp, &i2c_regs->i2cr); - - ret = tx_byte(i2c_regs, (chip << 1) | 1); - if (ret < 0) { - i2c_imx_stop(i2c_regs); - return ret; - } + debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len); /* setup bus to read data */ - temp = readb(&i2c_regs->i2cr); + temp = readb(base + (I2CR << reg_shift)); temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); if (len == 1) temp |= I2CR_TX_NO_AK; - writeb(temp, &i2c_regs->i2cr); - writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); - readb(&i2c_regs->i2dr); /* dummy read to clear ICF */ + writeb(temp, base + (I2CR << reg_shift)); + writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); + /* dummy read to clear ICF */ + readb(base + (I2DR << reg_shift)); /* read data */ for (i = 0; i < len; i++) { - ret = wait_for_sr_state(i2c_regs, ST_IIF); + ret = wait_for_sr_state(i2c_bus, ST_IIF); if (ret < 0) { - i2c_imx_stop(i2c_regs); + debug("i2c_read_data(): ret=%d\n", ret); + i2c_imx_stop(i2c_bus); return ret; } @@ -372,105 +432,111 @@ int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, * controller from generating another clock cycle */ if (i == (len - 1)) { - i2c_imx_stop(i2c_regs); + i2c_imx_stop(i2c_bus); } else if (i == (len - 2)) { - temp = readb(&i2c_regs->i2cr); + temp = readb(base + (I2CR << reg_shift)); temp |= I2CR_TX_NO_AK; - writeb(temp, &i2c_regs->i2cr); + writeb(temp, base + (I2CR << reg_shift)); } - writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); - buf[i] = readb(&i2c_regs->i2dr); + writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); + buf[i] = readb(base + (I2DR << reg_shift)); } - i2c_imx_stop(i2c_regs); + + /* reuse ret for counter*/ + for (ret = 0; ret < len; ++ret) + debug(" 0x%02x", buf[ret]); + debug("\n"); + + i2c_imx_stop(i2c_bus); return 0; } +#ifndef CONFIG_DM_I2C /* - * Write data to I2C device + * Read data from I2C device */ -int bus_i2c_write(void *base, uchar chip, uint addr, int alen, - const uchar *buf, int len) +static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, + int alen, u8 *buf, int len) { - int ret; - int i; - struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; + int ret = 0; + u32 temp; + int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? + VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + ulong base = i2c_bus->base; - ret = i2c_init_transfer(i2c_regs, chip, addr, alen); + ret = i2c_init_transfer(i2c_bus, chip, addr, alen); if (ret < 0) return ret; - for (i = 0; i < len; i++) { - ret = tx_byte(i2c_regs, buf[i]); - if (ret < 0) - break; + temp = readb(base + (I2CR << reg_shift)); + temp |= I2CR_RSTA; + writeb(temp, base + (I2CR << reg_shift)); + + ret = tx_byte(i2c_bus, (chip << 1) | 1); + if (ret < 0) { + i2c_imx_stop(i2c_bus); + return ret; } - i2c_imx_stop(i2c_regs); + + ret = i2c_read_data(i2c_bus, chip, buf, len); + + i2c_imx_stop(i2c_bus); + return ret; +} + +/* + * Write data to I2C device + */ +static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, + int alen, const u8 *buf, int len) +{ + int ret = 0; + + ret = i2c_init_transfer(i2c_bus, chip, addr, alen); + if (ret < 0) + return ret; + + ret = i2c_write_data(i2c_bus, chip, buf, len); + + i2c_imx_stop(i2c_bus); + return ret; } -static void * const i2c_bases[] = { +static struct mxc_i2c_bus mxc_i2c_buses[] = { #if defined(CONFIG_MX25) - (void *)IMX_I2C_BASE, - (void *)IMX_I2C2_BASE, - (void *)IMX_I2C3_BASE + { 0, IMX_I2C_BASE }, + { 1, IMX_I2C2_BASE }, + { 2, IMX_I2C3_BASE }, #elif defined(CONFIG_MX27) - (void *)IMX_I2C1_BASE, - (void *)IMX_I2C2_BASE + { 0, IMX_I2C1_BASE }, + { 1, IMX_I2C2_BASE }, #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \ defined(CONFIG_MX51) || defined(CONFIG_MX53) || \ - defined(CONFIG_MX6) || defined(CONFIG_LS102XA) - (void *)I2C1_BASE_ADDR, - (void *)I2C2_BASE_ADDR, - (void *)I2C3_BASE_ADDR + defined(CONFIG_MX6) + { 0, I2C1_BASE_ADDR }, + { 1, I2C2_BASE_ADDR }, + { 2, I2C3_BASE_ADDR }, +#elif defined(CONFIG_LS102XA) + { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG }, + { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG }, + { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG }, #elif defined(CONFIG_VF610) - (void *)I2C0_BASE_ADDR + { 0, I2C0_BASE_ADDR, I2C_QUIRK_FLAG }, #elif defined(CONFIG_FSL_LSCH3) - (void *)I2C1_BASE_ADDR, - (void *)I2C2_BASE_ADDR, - (void *)I2C3_BASE_ADDR, - (void *)I2C4_BASE_ADDR + { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG }, + { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG }, + { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG }, + { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG }, #else #error "architecture not supported" #endif + { } }; -struct i2c_parms { - void *base; - void *idle_bus_data; - int (*idle_bus_fn)(void *p); -}; - -struct sram_data { - unsigned curr_i2c_bus; - struct i2c_parms i2c_data[ARRAY_SIZE(i2c_bases)]; -}; - -void *i2c_get_base(struct i2c_adapter *adap) -{ - return i2c_bases[adap->hwadapnr]; -} - -static struct i2c_parms *i2c_get_parms(void *base) -{ - struct sram_data *srdata = (void *)gd->srdata; - int i = 0; - struct i2c_parms *p = srdata->i2c_data; - while (i < ARRAY_SIZE(srdata->i2c_data)) { - if (p->base == base) - return p; - p++; - i++; - } - printf("Invalid I2C base: %p\n", base); - return NULL; -} - -static int i2c_idle_bus(void *base) +struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap) { - struct i2c_parms *p = i2c_get_parms(base); - if (p && p->idle_bus_fn) - return p->idle_bus_fn(p->idle_bus_data); - return 0; + return &mxc_i2c_buses[adap->hwadapnr]; } static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip, @@ -495,29 +561,33 @@ static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0); } -void bus_i2c_init(void *base, int speed, int unused, - int (*idle_bus_fn)(void *p), void *idle_bus_data) +int __enable_i2c_clk(unsigned char enable, unsigned i2c_num) +{ + return 1; +} +int enable_i2c_clk(unsigned char enable, unsigned i2c_num) + __attribute__((weak, alias("__enable_i2c_clk"))); + +void bus_i2c_init(int index, int speed, int unused, + int (*idle_bus_fn)(void *p), void *idle_bus_data) { - struct sram_data *srdata = (void *)gd->srdata; - int i = 0; - struct i2c_parms *p = srdata->i2c_data; - if (!base) + int ret; + + if (index >= ARRAY_SIZE(mxc_i2c_buses)) { + debug("Error i2c index\n"); return; - for (;;) { - if (!p->base || (p->base == base)) { - p->base = base; - if (idle_bus_fn) { - p->idle_bus_fn = idle_bus_fn; - p->idle_bus_data = idle_bus_data; - } - break; - } - p++; - i++; - if (i >= ARRAY_SIZE(srdata->i2c_data)) - return; } - bus_i2c_set_bus_speed(base, speed); + + mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn; + mxc_i2c_buses[index].idle_bus_data = idle_bus_data; + + ret = enable_i2c_clk(1, index); + if (ret < 0) { + debug("I2C-%d clk fail to enable.\n", index); + return; + } + + bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed); } /* @@ -525,13 +595,13 @@ void bus_i2c_init(void *base, int speed, int unused, */ static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) { - bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL); + bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL); } /* * Set I2C Speed */ -static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) +static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) { return bus_i2c_set_bus_speed(i2c_get_base(adap), speed); } @@ -556,6 +626,7 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, CONFIG_SYS_MXC_I2C3_SPEED, CONFIG_SYS_MXC_I2C3_SLAVE, 2) #endif + #ifdef CONFIG_SYS_I2C_MXC_I2C4 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe, mxc_i2c_read, mxc_i2c_write, @@ -563,3 +634,143 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe, CONFIG_SYS_MXC_I2C4_SPEED, CONFIG_SYS_MXC_I2C4_SLAVE, 3) #endif + +#else + +static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); + + return bus_i2c_set_bus_speed(i2c_bus, speed); +} + +static int mxc_i2c_probe(struct udevice *bus) +{ + struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); + fdt_addr_t addr; + int ret; + + i2c_bus->driver_data = dev_get_driver_data(bus); + + addr = dev_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -ENODEV; + + i2c_bus->base = addr; + i2c_bus->index = bus->seq; + + /* Enable clk */ + ret = enable_i2c_clk(1, bus->seq); + if (ret < 0) + return ret; + + ret = i2c_idle_bus(i2c_bus); + if (ret < 0) { + /* Disable clk */ + enable_i2c_clk(0, bus->seq); + return ret; + } + + /* + * Pinmux settings are in board file now, until pinmux is supported, + * we can set pinmux here in probe function. + */ + + debug("i2c : controller bus %d at %lu , speed %d: ", + bus->seq, i2c_bus->base, + i2c_bus->speed); + + return 0; +} + +static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr, + u32 chip_flags) +{ + int ret; + struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); + + ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0); + if (ret < 0) { + debug("%s failed, ret = %d\n", __func__, ret); + return ret; + } + + i2c_imx_stop(i2c_bus); + + return 0; +} + +static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); + int ret = 0; + ulong base = i2c_bus->base; + int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? + VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + + /* + * Here the 3rd parameter addr and the 4th one alen are set to 0, + * because here we only want to send out chip address. The register + * address is wrapped in msg. + */ + ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0); + if (ret < 0) { + debug("i2c_init_transfer error: %d\n", ret); + return ret; + } + + for (; nmsgs > 0; nmsgs--, msg++) { + bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); + debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); + if (msg->flags & I2C_M_RD) + ret = i2c_read_data(i2c_bus, msg->addr, msg->buf, + msg->len); + else { + ret = i2c_write_data(i2c_bus, msg->addr, msg->buf, + msg->len); + if (ret) + break; + if (next_is_read) { + /* Reuse ret */ + ret = readb(base + (I2CR << reg_shift)); + ret |= I2CR_RSTA; + writeb(ret, base + (I2CR << reg_shift)); + + ret = tx_byte(i2c_bus, (msg->addr << 1) | 1); + if (ret < 0) { + i2c_imx_stop(i2c_bus); + break; + } + } + } + } + + if (ret) + debug("i2c_write: error sending\n"); + + i2c_imx_stop(i2c_bus); + + return ret; +} + +static const struct dm_i2c_ops mxc_i2c_ops = { + .xfer = mxc_i2c_xfer, + .probe_chip = mxc_i2c_probe_chip, + .set_bus_speed = mxc_i2c_set_bus_speed, +}; + +static const struct udevice_id mxc_i2c_ids[] = { + { .compatible = "fsl,imx21-i2c", }, + { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, }, + {} +}; + +U_BOOT_DRIVER(i2c_mxc) = { + .name = "i2c_mxc", + .id = UCLASS_I2C, + .of_match = mxc_i2c_ids, + .probe = mxc_i2c_probe, + .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus), + .ops = &mxc_i2c_ops, +}; +#endif diff --git a/drivers/i2c/sandbox_i2c.c b/drivers/i2c/sandbox_i2c.c index d6adc0f..2c84c41 100644 --- a/drivers/i2c/sandbox_i2c.c +++ b/drivers/i2c/sandbox_i2c.c @@ -18,14 +18,15 @@ DECLARE_GLOBAL_DATA_PTR; -struct dm_sandbox_i2c_emul_priv { - struct udevice *emul; +struct sandbox_i2c_priv { + bool test_mode; }; static int get_emul(struct udevice *dev, struct udevice **devp, struct dm_i2c_ops **opsp) { struct dm_i2c_chip *plat; + struct udevice *child; int ret; *devp = NULL; @@ -37,9 +38,22 @@ static int get_emul(struct udevice *dev, struct udevice **devp, if (ret) return ret; - ret = device_get_child(dev, 0, &plat->emul); - if (ret) - return ret; + for (device_find_first_child(dev, &child); child; + device_find_next_child(&child)) { + if (device_get_uclass_id(child) != UCLASS_I2C_EMUL) + continue; + + ret = device_probe(child); + if (ret) + return ret; + + break; + } + + if (child) + plat->emul = child; + else + return -ENODEV; } *devp = plat->emul; *opsp = i2c_get_ops(plat->emul); @@ -47,17 +61,25 @@ static int get_emul(struct udevice *dev, struct udevice **devp, return 0; } +void sandbox_i2c_set_test_mode(struct udevice *bus, bool test_mode) +{ + struct sandbox_i2c_priv *priv = dev_get_priv(bus); + + priv->test_mode = test_mode; +} + static int sandbox_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) { struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus); + struct sandbox_i2c_priv *priv = dev_get_priv(bus); struct dm_i2c_ops *ops; struct udevice *emul, *dev; bool is_read; int ret; /* Special test code to return success but with no emulation */ - if (msg->addr == SANDBOX_I2C_TEST_ADDR) + if (priv->test_mode && msg->addr == SANDBOX_I2C_TEST_ADDR) return 0; ret = i2c_get_chip(bus, msg->addr, 1, &dev); @@ -68,13 +90,18 @@ static int sandbox_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, if (ret) return ret; - /* - * For testing, don't allow writing above 100KHz for writes and - * 400KHz for reads - */ - is_read = nmsgs > 1; - if (i2c->speed_hz > (is_read ? 400000 : 100000)) - return -EINVAL; + if (priv->test_mode) { + /* + * For testing, don't allow writing above 100KHz for writes and + * 400KHz for reads. + */ + is_read = nmsgs > 1; + if (i2c->speed_hz > (is_read ? 400000 : 100000)) { + debug("%s: Max speed exceeded\n", __func__); + return -EINVAL; + } + } + return ops->xfer(emul, msg, nmsgs); } @@ -92,4 +119,5 @@ U_BOOT_DRIVER(i2c_sandbox) = { .id = UCLASS_I2C, .of_match = sandbox_i2c_ids, .ops = &sandbox_i2c_ops, + .priv_auto_alloc_size = sizeof(struct sandbox_i2c_priv), }; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 0e571d9..64b07a3 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -60,3 +60,16 @@ config CONFIG_FSL_SEC_MON system states. Security Monitor can be transitioned on any security failures, like software violations or hardware security violations. + +config PCA9551_LED + bool "Enable PCA9551 LED driver" + help + Enable driver for PCA9551 LED controller. This controller + is connected via I2C. So I2C needs to be enabled. + +config PCA9551_I2C_ADDR + hex "I2C address of PCA9551 LED controller" + depends on PCA9551_LED + default 0x60 + help + The I2C address of the PCA9551 LED controller. diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 25630c3..120babc 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_SANDBOX) += swap_case.o obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o +obj-$(CONFIG_PCA9551_LED) += pca9551_led.o diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index 982bac7..4b6ac6a 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -986,7 +986,8 @@ int cros_ec_register(struct udevice *dev) } /* Remember this device for use by the cros_ec command */ - debug("Google Chrome EC CROS-EC driver ready, id '%s'\n", id); + debug("Google Chrome EC v%d CROS-EC driver ready, id '%s'\n", + cdev->protocol_version, id); return 0; } diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index df41e82..7509612 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -459,6 +459,8 @@ static int process_cmd(struct ec_state *ec, case EC_CMD_MKBP_STATE: len = cros_ec_keyscan(ec, resp_data); break; + case EC_CMD_ENTERING_MODE: + break; default: printf(" ** Unknown EC command %#02x\n", req_hdr->command); return -1; diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c index ac2ee86..0686925 100644 --- a/drivers/misc/cros_ec_spi.c +++ b/drivers/misc/cros_ec_spi.c @@ -25,6 +25,8 @@ int cros_ec_spi_packet(struct udevice *udev, int out_bytes, int in_bytes) { struct cros_ec_dev *dev = dev_get_uclass_priv(udev); struct spi_slave *slave = dev_get_parentdata(dev->dev); + ulong start; + uint8_t byte; int rv; /* Do the transfer */ @@ -33,10 +35,25 @@ int cros_ec_spi_packet(struct udevice *udev, int out_bytes, int in_bytes) return -1; } - rv = spi_xfer(slave, max(out_bytes, in_bytes) * 8, - dev->dout, dev->din, - SPI_XFER_BEGIN | SPI_XFER_END); + rv = spi_xfer(slave, out_bytes * 8, dev->dout, NULL, SPI_XFER_BEGIN); + if (rv) + goto done; + start = get_timer(0); + while (1) { + rv = spi_xfer(slave, 8, NULL, &byte, 0); + if (byte == SPI_PREAMBLE_END_BYTE) + break; + if (rv) + goto done; + if (get_timer(start) > 100) { + rv = -ETIMEDOUT; + goto done; + } + } + rv = spi_xfer(slave, in_bytes * 8, NULL, dev->din, 0); +done: + spi_xfer(slave, 0, NULL, NULL, SPI_XFER_END); spi_release_bus(slave); if (rv) { diff --git a/drivers/misc/i2c_eeprom_emul.c b/drivers/misc/i2c_eeprom_emul.c index 7343445..4410d03 100644 --- a/drivers/misc/i2c_eeprom_emul.c +++ b/drivers/misc/i2c_eeprom_emul.c @@ -8,6 +8,7 @@ #include <common.h> #include <dm.h> +#include <errno.h> #include <fdtdec.h> #include <i2c.h> #include <malloc.h> diff --git a/drivers/misc/pca9551_led.c b/drivers/misc/pca9551_led.c new file mode 100644 index 0000000..79b1e20 --- /dev/null +++ b/drivers/misc/pca9551_led.c @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <i2c.h> + +#ifndef CONFIG_PCA9551_I2C_ADDR +#error "CONFIG_PCA9551_I2C_ADDR not defined!" +#endif + +#define PCA9551_REG_INPUT 0x00 /* Input register (read only) */ +#define PCA9551_REG_PSC0 0x01 /* Frequency prescaler 0 */ +#define PCA9551_REG_PWM0 0x02 /* PWM0 */ +#define PCA9551_REG_PSC1 0x03 /* Frequency prescaler 1 */ +#define PCA9551_REG_PWM1 0x04 /* PWM1 */ +#define PCA9551_REG_LS0 0x05 /* LED0 to LED3 selector */ +#define PCA9551_REG_LS1 0x06 /* LED4 to LED7 selector */ + +#define PCA9551_CTRL_AI (1 << 4) /* Auto-increment flag */ + +#define PCA9551_LED_STATE_ON 0x00 +#define PCA9551_LED_STATE_OFF 0x01 +#define PCA9551_LED_STATE_BLINK0 0x02 +#define PCA9551_LED_STATE_BLINK1 0x03 + +struct pca9551_blink_rate { + u8 psc; /* Frequency preescaler, see PCA9551_7.pdf p. 6 */ + u8 pwm; /* Pulse width modulation, see PCA9551_7.pdf p. 6 */ +}; + +static int freq0, freq1; + +static int pca9551_led_get_state(int led, int *state) +{ + unsigned int reg; + u8 shift, buf; + int ret; + + if (led < 0 || led > 7) { + return -EINVAL; + } else if (led < 4) { + reg = PCA9551_REG_LS0; + shift = led << 1; + } else { + reg = PCA9551_REG_LS1; + shift = (led - 4) << 1; + } + + ret = i2c_read(CONFIG_PCA9551_I2C_ADDR, reg, 1, &buf, 1); + if (ret) + return ret; + + *state = (buf >> shift) & 0x03; + return 0; +} + +static int pca9551_led_set_state(int led, int state) +{ + unsigned int reg; + u8 shift, buf, mask; + int ret; + + if (led < 0 || led > 7) { + return -EINVAL; + } else if (led < 4) { + reg = PCA9551_REG_LS0; + shift = led << 1; + } else { + reg = PCA9551_REG_LS1; + shift = (led - 4) << 1; + } + mask = 0x03 << shift; + + ret = i2c_read(CONFIG_PCA9551_I2C_ADDR, reg, 1, &buf, 1); + if (ret) + return ret; + + buf = (buf & ~mask) | ((state & 0x03) << shift); + + ret = i2c_write(CONFIG_PCA9551_I2C_ADDR, reg, 1, &buf, 1); + if (ret) + return ret; + + return 0; +} + +static int pca9551_led_set_blink_rate(int idx, struct pca9551_blink_rate rate) +{ + unsigned int reg; + int ret; + + switch (idx) { + case 0: + reg = PCA9551_REG_PSC0; + break; + case 1: + reg = PCA9551_REG_PSC1; + break; + default: + return -EINVAL; + } + reg |= PCA9551_CTRL_AI; + + ret = i2c_write(CONFIG_PCA9551_I2C_ADDR, reg, 1, (u8 *)&rate, 2); + if (ret) + return ret; + + return 0; +} + +/* + * Functions referenced by cmd_led.c + */ +void __led_set(led_id_t mask, int state) +{ + if (state == STATUS_LED_OFF) + pca9551_led_set_state(mask, PCA9551_LED_STATE_OFF); + else + pca9551_led_set_state(mask, PCA9551_LED_STATE_ON); +} + +void __led_toggle(led_id_t mask) +{ + int state = 0; + + pca9551_led_get_state(mask, &state); + pca9551_led_set_state(mask, !state); +} + +void __led_blink(led_id_t mask, int freq) +{ + struct pca9551_blink_rate rate; + int mode; + int blink; + + if ((freq0 == 0) || (freq == freq0)) { + blink = 0; + mode = PCA9551_LED_STATE_BLINK0; + freq0 = freq; + } else { + blink = 1; + mode = PCA9551_LED_STATE_BLINK1; + freq1 = freq; + } + + rate.psc = ((freq * 38) / 1000) - 1; + rate.pwm = 128; /* 50% duty cycle */ + + pca9551_led_set_blink_rate(blink, rate); + pca9551_led_set_state(mask, mode); +} diff --git a/drivers/misc/swap_case.c b/drivers/misc/swap_case.c index f6028ba..3b8aa48 100644 --- a/drivers/misc/swap_case.c +++ b/drivers/misc/swap_case.c @@ -9,6 +9,7 @@ #include <common.h> #include <dm.h> +#include <errno.h> #include <pci.h> #include <asm/test.h> #include <linux/ctype.h> diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c index d576d31..895604d 100644 --- a/drivers/mtd/spi/sandbox.c +++ b/drivers/mtd/spi/sandbox.c @@ -129,7 +129,7 @@ static int sandbox_sf_probe(struct udevice *dev) } } if (cs == -1) { - printf("Error: Unknown chip select for device '%s'", + printf("Error: Unknown chip select for device '%s'\n", dev->name); return -EINVAL; } diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c index 4b25902..350e21a 100644 --- a/drivers/mtd/spi/sf-uclass.c +++ b/drivers/mtd/spi/sf-uclass.c @@ -53,10 +53,10 @@ int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, { struct spi_slave *slave; struct udevice *bus; - char name[20], *str; + char name[30], *str; int ret; - snprintf(name, sizeof(name), "%d:%d", busnum, cs); + snprintf(name, sizeof(name), "spi_flash@%d:%d", busnum, cs); str = strdup(name); ret = spi_get_bus_and_cs(busnum, cs, max_hz, spi_mode, "spi_flash_std", str, &bus, &slave); diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c index e239ff4..4e083d3 100644 --- a/drivers/net/sandbox.c +++ b/drivers/net/sandbox.c @@ -11,6 +11,7 @@ #include <dm.h> #include <malloc.h> #include <net.h> +#include <asm/test.h> DECLARE_GLOBAL_DATA_PTR; @@ -30,6 +31,7 @@ struct eth_sandbox_priv { }; static bool disabled[8] = {false}; +static bool skip_timeout; /* * sandbox_eth_disable_response() @@ -42,6 +44,16 @@ void sandbox_eth_disable_response(int index, bool disable) disabled[index] = disable; } +/* + * sandbox_eth_skip_timeout() + * + * When the first packet read is attempted, fast-forward time + */ +void sandbox_eth_skip_timeout(void) +{ + skip_timeout = true; +} + static int sb_eth_start(struct udevice *dev) { struct eth_sandbox_priv *priv = dev_get_priv(dev); @@ -144,6 +156,11 @@ static int sb_eth_recv(struct udevice *dev, uchar **packetp) { struct eth_sandbox_priv *priv = dev_get_priv(dev); + if (skip_timeout) { + sandbox_timer_add_offset(10000UL); + skip_timeout = false; + } + if (priv->recv_packet_length) { int lcl_recv_packet_length = priv->recv_packet_length; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index f8f0239..23cdd71 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -1,3 +1,9 @@ +menu "Power" + +source "drivers/power/pmic/Kconfig" + +source "drivers/power/regulator/Kconfig" + config AXP221_POWER boolean "axp221 / axp223 pmic support" depends on MACH_SUN6I || MACH_SUN8I @@ -73,3 +79,5 @@ config AXP221_ELDO3_VOLT disable eldo3. On some A31(s) tablets it might be used to supply 1.2V for the SSD2828 chip (converter of parallel LCD interface into MIPI DSI). + +endmenu diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 2145652..a2d3c04 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o obj-$(CONFIG_TWL4030_POWER) += twl4030.o obj-$(CONFIG_TWL6030_POWER) += twl6030.o obj-$(CONFIG_PALMAS_POWER) += palmas.o - obj-$(CONFIG_POWER) += power_core.o obj-$(CONFIG_DIALOG_POWER) += power_dialog.o obj-$(CONFIG_POWER_FSL) += power_fsl.o diff --git a/drivers/power/as3722.c b/drivers/power/as3722.c index a60bb5f..c09e1de 100644 --- a/drivers/power/as3722.c +++ b/drivers/power/as3722.c @@ -27,7 +27,7 @@ #define AS3722_DEVICE_ID 0x0c #define AS3722_ASIC_ID2 0x91 -static int as3722_read(struct udevice *pmic, u8 reg, u8 *value) +int as3722_read(struct udevice *pmic, u8 reg, u8 *value) { int err; @@ -38,7 +38,7 @@ static int as3722_read(struct udevice *pmic, u8 reg, u8 *value) return 0; } -static int as3722_write(struct udevice *pmic, u8 reg, u8 value) +int as3722_write(struct udevice *pmic, u8 reg, u8 value) { int err; @@ -234,6 +234,15 @@ int as3722_gpio_direction_output(struct udevice *pmic, unsigned int gpio, return 0; } +/* Temporary function until we get the pmic framework */ +int as3722_get(struct udevice **devp) +{ + int bus = 0; + int address = 0x40; + + return i2c_get_chip_for_busnum(bus, address, 1, devp); +} + int as3722_init(struct udevice **devp) { struct udevice *pmic; @@ -258,7 +267,8 @@ int as3722_init(struct udevice **devp) debug("AS3722 revision %#x found on I2C bus %u, address %#x\n", revision, bus, address); - *devp = pmic; + if (devp) + *devp = pmic; return 0; } diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig new file mode 100644 index 0000000..164f421 --- /dev/null +++ b/drivers/power/pmic/Kconfig @@ -0,0 +1,43 @@ +config DM_PMIC + bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC)" + depends on DM + ---help--- + This config enables the driver-model PMIC support. + UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. + For the multi-function PMIC devices, this can be used as parent I/O + device for each IC's interface. Then, each children uses its parent + for read/write. For detailed description, please refer to the files: + - 'drivers/power/pmic/pmic-uclass.c' + - 'include/power/pmic.h' + +config DM_PMIC_MAX77686 + bool "Enable Driver Model for PMIC MAX77686" + depends on DM_PMIC + ---help--- + This config enables implementation of driver-model pmic uclass features + for PMIC MAX77686. The driver implements read/write operations. + +config DM_PMIC_SANDBOX + bool "Enable Driver Model for emulated Sandbox PMIC " + depends on DM_PMIC + ---help--- + Enable the driver for Sandbox PMIC emulation. The emulated PMIC device + depends on two drivers: + - sandbox PMIC I/O driver - implements dm pmic operations + - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission + + A detailed information can be found in header: '<power/sandbox_pmic.h>' + + The Sandbox PMIC info: + * I/O interface: + - I2C chip address: 0x40 + - first register address: 0x0 + - register count: 0x10 + * Adjustable outputs: + - 2x LDO + - 2x BUCK + - Each, with a different operating conditions (header). + * Reset values: + - set by i2c emul driver's probe() (defaults in header) + + Driver binding info: doc/device-tree-bindings/pmic/sandbox.txt diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 985cfdb..ae86f04 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -5,6 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_DM_PMIC) += pmic-uclass.o +obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o +obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o diff --git a/drivers/power/pmic/i2c_pmic_emul.c b/drivers/power/pmic/i2c_pmic_emul.c new file mode 100644 index 0000000..aeab5c9 --- /dev/null +++ b/drivers/power/pmic/i2c_pmic_emul.c @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <errno.h> +#include <dm.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/sandbox_pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * struct sandbox_i2c_pmic_plat_data - platform data for the PMIC + * + * @rw_reg: PMICs register of the chip I/O transaction + * @reg: PMICs registers array + */ +struct sandbox_i2c_pmic_plat_data { + u8 rw_reg; + u8 reg[SANDBOX_PMIC_REG_COUNT]; +}; + +static int sandbox_i2c_pmic_read_data(struct udevice *emul, uchar chip, + uchar *buffer, int len) +{ + struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul); + + if (plat->rw_reg + len > SANDBOX_PMIC_REG_COUNT) { + error("Request exceeds PMIC register range! Max register: %#x", + SANDBOX_PMIC_REG_COUNT); + return -EFAULT; + } + + debug("Read PMIC: %#x at register: %#x count: %d\n", + (unsigned)chip & 0xff, plat->rw_reg, len); + + memcpy(buffer, &plat->reg[plat->rw_reg], len); + + return 0; +} + +static int sandbox_i2c_pmic_write_data(struct udevice *emul, uchar chip, + uchar *buffer, int len, + bool next_is_read) +{ + struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul); + + /* Probe only */ + if (!len) + return 0; + + /* Set PMIC register for I/O */ + plat->rw_reg = *buffer; + + debug("Write PMIC: %#x at register: %#x count: %d\n", + (unsigned)chip & 0xff, plat->rw_reg, len); + + /* For read operation, set (write) only chip reg */ + if (next_is_read) + return 0; + + buffer++; + len--; + + if (plat->rw_reg + len > SANDBOX_PMIC_REG_COUNT) { + error("Request exceeds PMIC register range! Max register: %#x", + SANDBOX_PMIC_REG_COUNT); + } + + memcpy(&plat->reg[plat->rw_reg], buffer, len); + + return 0; +} + +static int sandbox_i2c_pmic_xfer(struct udevice *emul, struct i2c_msg *msg, + int nmsgs) +{ + int ret = 0; + + for (; nmsgs > 0; nmsgs--, msg++) { + bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); + if (msg->flags & I2C_M_RD) { + ret = sandbox_i2c_pmic_read_data(emul, msg->addr, + msg->buf, msg->len); + } else { + ret = sandbox_i2c_pmic_write_data(emul, msg->addr, + msg->buf, msg->len, + next_is_read); + } + + if (ret) + break; + } + + return ret; +} + +static int sandbox_i2c_pmic_ofdata_to_platdata(struct udevice *emul) +{ + struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul); + const u8 *reg_defaults; + + debug("%s:%d Setting PMIC default registers\n", __func__, __LINE__); + + reg_defaults = fdtdec_locate_byte_array(gd->fdt_blob, emul->of_offset, + "reg-defaults", + SANDBOX_PMIC_REG_COUNT); + + if (!reg_defaults) { + error("Property \"reg-defaults\" not found for device: %s!", + emul->name); + return -EINVAL; + } + + memcpy(&plat->reg, reg_defaults, SANDBOX_PMIC_REG_COUNT); + + return 0; +} + +struct dm_i2c_ops sandbox_i2c_pmic_emul_ops = { + .xfer = sandbox_i2c_pmic_xfer, +}; + +static const struct udevice_id sandbox_i2c_pmic_ids[] = { + { .compatible = "sandbox,i2c-pmic" }, + { } +}; + +U_BOOT_DRIVER(sandbox_i2c_pmic_emul) = { + .name = "sandbox_i2c_pmic_emul", + .id = UCLASS_I2C_EMUL, + .of_match = sandbox_i2c_pmic_ids, + .ofdata_to_platdata = sandbox_i2c_pmic_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct sandbox_i2c_pmic_plat_data), + .ops = &sandbox_i2c_pmic_emul_ops, +}; diff --git a/drivers/power/pmic/max77686.c b/drivers/power/pmic/max77686.c new file mode 100644 index 0000000..3523b4a --- /dev/null +++ b/drivers/power/pmic/max77686.c @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2014-2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <errno.h> +#include <dm.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/max77686_pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct pmic_child_info pmic_children_info[] = { + { .prefix = "ldo", .driver = MAX77686_LDO_DRIVER }, + { .prefix = "buck", .driver = MAX77686_BUCK_DRIVER }, + { }, +}; + +static int max77686_reg_count(struct udevice *dev) +{ + return MAX77686_NUM_OF_REGS; +} + +static int max77686_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + if (dm_i2c_write(dev, reg, buff, len)) { + error("write error to device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +static int max77686_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + if (dm_i2c_read(dev, reg, buff, len)) { + error("read error from device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +static int max77686_bind(struct udevice *dev) +{ + int regulators_node; + const void *blob = gd->fdt_blob; + int children; + + regulators_node = fdt_subnode_offset(blob, dev->of_offset, + "voltage-regulators"); + if (regulators_node <= 0) { + debug("%s: %s regulators subnode not found!", __func__, + dev->name); + return -ENXIO; + } + + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); + + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + debug("%s: %s - no child found\n", __func__, dev->name); + + /* Always return success for this device */ + return 0; +} + +static struct dm_pmic_ops max77686_ops = { + .reg_count = max77686_reg_count, + .read = max77686_read, + .write = max77686_write, +}; + +static const struct udevice_id max77686_ids[] = { + { .compatible = "maxim,max77686" }, + { } +}; + +U_BOOT_DRIVER(pmic_max77686) = { + .name = "max77686 pmic", + .id = UCLASS_PMIC, + .of_match = max77686_ids, + .bind = max77686_bind, + .ops = &max77686_ops, +}; diff --git a/drivers/power/pmic/pmic-uclass.c b/drivers/power/pmic/pmic-uclass.c new file mode 100644 index 0000000..812ac13 --- /dev/null +++ b/drivers/power/pmic/pmic-uclass.c @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2014-2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <errno.h> +#include <dm.h> +#include <dm/lists.h> +#include <dm/device-internal.h> +#include <dm/uclass-internal.h> +#include <power/pmic.h> +#include <linux/ctype.h> + +DECLARE_GLOBAL_DATA_PTR; + +static ulong str_get_num(const char *ptr, const char *maxptr) +{ + if (!ptr || !maxptr) + return 0; + + while (!isdigit(*ptr) && ptr++ < maxptr); + + return simple_strtoul(ptr, NULL, 0); +} + +int pmic_bind_children(struct udevice *pmic, int offset, + const struct pmic_child_info *child_info) +{ + const struct pmic_child_info *info; + const void *blob = gd->fdt_blob; + struct driver *drv; + struct udevice *child; + const char *node_name; + int node_name_len; + int bind_count = 0; + int node; + int prefix_len; + int ret; + + debug("%s for '%s' at node offset: %d\n", __func__, pmic->name, + pmic->of_offset); + + for (node = fdt_first_subnode(blob, offset); + node > 0; + node = fdt_next_subnode(blob, node)) { + node_name = fdt_get_name(blob, node, &node_name_len); + + debug("* Found child node: '%s' at offset:%d\n", node_name, + node); + + child = NULL; + for (info = child_info; info->prefix && info->driver; info++) { + prefix_len = strlen(info->prefix); + if (strncasecmp(info->prefix, node_name, prefix_len)) + continue; + + debug(" - compatible prefix: '%s'\n", info->prefix); + + drv = lists_driver_lookup_name(info->driver); + if (!drv) { + debug(" - driver: '%s' not found!\n", + info->driver); + continue; + } + + debug(" - found child driver: '%s'\n", drv->name); + + ret = device_bind(pmic, drv, node_name, NULL, + node, &child); + if (ret) { + debug(" - child binding error: %d\n", ret); + continue; + } + + debug(" - bound child device: '%s'\n", child->name); + + child->driver_data = str_get_num(node_name + + prefix_len, + node_name + + node_name_len); + + debug(" - set 'child->driver_data': %lu\n", + child->driver_data); + break; + } + + if (child) + bind_count++; + else + debug(" - compatible prefix not found\n"); + } + + debug("Bound: %d childs for PMIC: '%s'\n", bind_count, pmic->name); + return bind_count; +} + +int pmic_get(const char *name, struct udevice **devp) +{ + return uclass_get_device_by_name(UCLASS_PMIC, name, devp); +} + +int pmic_reg_count(struct udevice *dev) +{ + const struct dm_pmic_ops *ops = dev_get_driver_ops(dev); + + if (!ops || !ops->reg_count) + return -ENOSYS; + + return ops->reg_count(dev); +} + +int pmic_read(struct udevice *dev, uint reg, uint8_t *buffer, int len) +{ + const struct dm_pmic_ops *ops = dev_get_driver_ops(dev); + + if (!buffer) + return -EFAULT; + + if (!ops || !ops->read) + return -ENOSYS; + + return ops->read(dev, reg, buffer, len); +} + +int pmic_write(struct udevice *dev, uint reg, const uint8_t *buffer, int len) +{ + const struct dm_pmic_ops *ops = dev_get_driver_ops(dev); + + if (!buffer) + return -EFAULT; + + if (!ops || !ops->write) + return -ENOSYS; + + return ops->write(dev, reg, buffer, len); +} + +UCLASS_DRIVER(pmic) = { + .id = UCLASS_PMIC, + .name = "pmic", +}; diff --git a/drivers/power/pmic/pmic_max77686.c b/drivers/power/pmic/pmic_max77686.c index 95b1a57..1ad810a 100644 --- a/drivers/power/pmic/pmic_max77686.c +++ b/drivers/power/pmic/pmic_max77686.c @@ -295,7 +295,7 @@ int pmic_init(unsigned char bus) p->name = name; p->interface = PMIC_I2C; - p->number_of_regs = PMIC_NUM_OF_REGS; + p->number_of_regs = MAX77686_NUM_OF_REGS; p->hw.i2c.tx_num = 1; puts("Board PMIC init\n"); diff --git a/drivers/power/pmic/sandbox.c b/drivers/power/pmic/sandbox.c new file mode 100644 index 0000000..3e56acd --- /dev/null +++ b/drivers/power/pmic/sandbox.c @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <errno.h> +#include <dm.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/sandbox_pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct pmic_child_info pmic_children_info[] = { + { .prefix = SANDBOX_OF_LDO_PREFIX, .driver = SANDBOX_LDO_DRIVER }, + { .prefix = SANDBOX_OF_BUCK_PREFIX, .driver = SANDBOX_BUCK_DRIVER }, + { }, +}; + +static int sandbox_pmic_reg_count(struct udevice *dev) +{ + return SANDBOX_PMIC_REG_COUNT; +} + +static int sandbox_pmic_write(struct udevice *dev, uint reg, + const uint8_t *buff, int len) +{ + if (dm_i2c_write(dev, reg, buff, len)) { + error("write error to device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +static int sandbox_pmic_read(struct udevice *dev, uint reg, + uint8_t *buff, int len) +{ + if (dm_i2c_read(dev, reg, buff, len)) { + error("read error from device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +static int sandbox_pmic_bind(struct udevice *dev) +{ + if (!pmic_bind_children(dev, dev->of_offset, pmic_children_info)) + error("%s:%d PMIC: %s - no child found!", __func__, __LINE__, + dev->name); + + /* Always return success for this device - allows for PMIC I/O */ + return 0; +} + +static struct dm_pmic_ops sandbox_pmic_ops = { + .reg_count = sandbox_pmic_reg_count, + .read = sandbox_pmic_read, + .write = sandbox_pmic_write, +}; + +static const struct udevice_id sandbox_pmic_ids[] = { + { .compatible = "sandbox,pmic" }, + { } +}; + +U_BOOT_DRIVER(sandbox_pmic) = { + .name = "sandbox_pmic", + .id = UCLASS_PMIC, + .of_match = sandbox_pmic_ids, + .bind = sandbox_pmic_bind, + .ops = &sandbox_pmic_ops, +}; diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig new file mode 100644 index 0000000..6289b83 --- /dev/null +++ b/drivers/power/regulator/Kconfig @@ -0,0 +1,63 @@ +config DM_REGULATOR + bool "Enable Driver Model for REGULATOR drivers (UCLASS_REGULATOR)" + depends on DM + ---help--- + This config enables the driver model regulator support. + UCLASS_REGULATOR - designed to provide a common API for basic regulator's + functions, like get/set Voltage or Current value, enable state, etc... + Note: + When enabling this, please read the description, found in the files: + - 'include/power/pmic.h' + - 'include/power/regulator.h' + - 'drivers/power/pmic/pmic-uclass.c' + - 'drivers/power/pmic/regulator-uclass.c' + It's important to call the device_bind() with the proper node offset, + when binding the regulator devices. The pmic_bind_childs() can be used + for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_node() + otherwise. Detailed information can be found in the header file. + +config DM_REGULATOR_MAX77686 + bool "Enable Driver Model for REGULATOR MAX77686" + depends on DM_REGULATOR && DM_PMIC_MAX77686 + ---help--- + This config enables implementation of driver-model regulator uclass + features for REGULATOR MAX77686. The driver implements get/set api for: + value, enable and mode. + +config DM_REGULATOR_FIXED + bool "Enable Driver Model for REGULATOR Fixed value" + depends on DM_REGULATOR + ---help--- + This config enables implementation of driver-model regulator uclass + features for fixed value regulators. The driver implements get/set api + for enable and get only for voltage value. + +config DM_REGULATOR_SANDBOX + bool "Enable Driver Model for Sandbox PMIC regulator" + depends on DM_REGULATOR && DM_PMIC_SANDBOX + ---help--- + Enable the regulator driver for emulated Sandbox PMIC. + The emulated PMIC device depends on two drivers: + - sandbox PMIC I/O driver - implements dm pmic operations + - sandbox PMIC regulator driver - implements dm regulator operations + - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission + + The regulator driver provides uclass operations for sandbox PMIC's + regulators. The driver implements get/set api for: voltage, current, + operation mode and enable state. + The driver supports LDO and BUCK regulators. + + The Sandbox PMIC info: + * I/O interface: + - I2C chip address: 0x40 + - first register address: 0x0 + - register count: 0x10 + * Adjustable outputs: + - 2x LDO + - 2x BUCK + - Each, with a different operating conditions (header). + * Reset values: + - set by i2c emul driver's probe() (defaults in header) + + A detailed information can be found in header: '<power/sandbox_pmic.h>' + Binding info: 'doc/device-tree-bindings/pmic/max77686.txt' diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile new file mode 100644 index 0000000..96aa624 --- /dev/null +++ b/drivers/power/regulator/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2015 Samsung Electronics +# Przemyslaw Marczak <p.marczak@samsung.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DM_REGULATOR) += regulator-uclass.o +obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o +obj-$(CONFIG_DM_REGULATOR_FIXED) += fixed.o +obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c new file mode 100644 index 0000000..d053817 --- /dev/null +++ b/drivers/power/regulator/fixed.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <errno.h> +#include <dm.h> +#include <i2c.h> +#include <asm/gpio.h> +#include <power/pmic.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct fixed_regulator_platdata { + struct gpio_desc gpio; /* GPIO for regulator enable control */ +}; + +static int fixed_regulator_ofdata_to_platdata(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + struct fixed_regulator_platdata *dev_pdata; + struct gpio_desc *gpio; + int ret; + + dev_pdata = dev_get_platdata(dev); + uc_pdata = dev_get_uclass_platdata(dev); + if (!uc_pdata) + return -ENXIO; + + /* Set type to fixed */ + uc_pdata->type = REGULATOR_TYPE_FIXED; + + /* Get fixed regulator gpio desc */ + gpio = &dev_pdata->gpio; + ret = gpio_request_by_name(dev, "gpio", 0, gpio, GPIOD_IS_OUT); + if (ret) + debug("Fixed regulator gpio - not found! Error: %d", ret); + + return 0; +} + +static int fixed_regulator_get_value(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + if (!uc_pdata) + return -ENXIO; + + if (uc_pdata->min_uV != uc_pdata->max_uV) { + debug("Invalid constraints for: %s\n", uc_pdata->name); + return -EINVAL; + } + + return uc_pdata->min_uV; +} + +static int fixed_regulator_get_current(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + if (!uc_pdata) + return -ENXIO; + + if (uc_pdata->min_uA != uc_pdata->max_uA) { + debug("Invalid constraints for: %s\n", uc_pdata->name); + return -EINVAL; + } + + return uc_pdata->min_uA; +} + +static bool fixed_regulator_get_enable(struct udevice *dev) +{ + struct fixed_regulator_platdata *dev_pdata = dev_get_platdata(dev); + + if (!dev_pdata->gpio.dev) + return false; + + return dm_gpio_get_value(&dev_pdata->gpio); +} + +static int fixed_regulator_set_enable(struct udevice *dev, bool enable) +{ + struct fixed_regulator_platdata *dev_pdata = dev_get_platdata(dev); + int ret; + + if (!dev_pdata->gpio.dev) + return -ENOSYS; + + ret = dm_gpio_set_value(&dev_pdata->gpio, enable); + if (ret) { + error("Can't set regulator : %s gpio to: %d\n", dev->name, + enable); + return ret; + } + return 0; +} + +static const struct dm_regulator_ops fixed_regulator_ops = { + .get_value = fixed_regulator_get_value, + .get_current = fixed_regulator_get_current, + .get_enable = fixed_regulator_get_enable, + .set_enable = fixed_regulator_set_enable, +}; + +static const struct udevice_id fixed_regulator_ids[] = { + { .compatible = "regulator-fixed" }, + { }, +}; + +U_BOOT_DRIVER(fixed_regulator) = { + .name = "fixed regulator", + .id = UCLASS_REGULATOR, + .ops = &fixed_regulator_ops, + .of_match = fixed_regulator_ids, + .ofdata_to_platdata = fixed_regulator_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct fixed_regulator_platdata), +}; diff --git a/drivers/power/regulator/max77686.c b/drivers/power/regulator/max77686.c new file mode 100644 index 0000000..37ebe94 --- /dev/null +++ b/drivers/power/regulator/max77686.c @@ -0,0 +1,825 @@ +/* + * Copyright (C) 2012-2015 Samsung Electronics + * + * Rajeshwari Shinde <rajeshwari.s@samsung.com> + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <errno.h> +#include <dm.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/max77686_pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MODE(_id, _val, _name) { \ + .id = _id, \ + .register_value = _val, \ + .name = _name, \ +} + +/* LDO: 1,3,4,5,9,17,18,19,20,21,22,23,24,26,26,27 */ +static struct dm_regulator_mode max77686_ldo_mode_standby1[] = { + MODE(OPMODE_OFF, MAX77686_LDO_MODE_OFF, "OFF"), + MODE(OPMODE_LPM, MAX77686_LDO_MODE_LPM, "LPM"), + MODE(OPMODE_STANDBY_LPM, MAX77686_LDO_MODE_STANDBY_LPM, "ON/LPM"), + MODE(OPMODE_ON, MAX77686_LDO_MODE_ON, "ON"), +}; + +/* LDO: 2,6,7,8,10,11,12,14,15,16 */ +static struct dm_regulator_mode max77686_ldo_mode_standby2[] = { + MODE(OPMODE_OFF, MAX77686_LDO_MODE_OFF, "OFF"), + MODE(OPMODE_STANDBY, MAX77686_LDO_MODE_STANDBY, "ON/OFF"), + MODE(OPMODE_STANDBY_LPM, MAX77686_LDO_MODE_STANDBY_LPM, "ON/LPM"), + MODE(OPMODE_ON, MAX77686_LDO_MODE_ON, "ON"), +}; + +/* Buck: 1 */ +static struct dm_regulator_mode max77686_buck_mode_standby[] = { + MODE(OPMODE_OFF, MAX77686_BUCK_MODE_OFF, "OFF"), + MODE(OPMODE_STANDBY, MAX77686_BUCK_MODE_STANDBY, "ON/OFF"), + MODE(OPMODE_ON, MAX77686_BUCK_MODE_ON, "ON"), +}; + +/* Buck: 2,3,4 */ +static struct dm_regulator_mode max77686_buck_mode_lpm[] = { + MODE(OPMODE_OFF, MAX77686_BUCK_MODE_OFF, "OFF"), + MODE(OPMODE_STANDBY, MAX77686_BUCK_MODE_STANDBY, "ON/OFF"), + MODE(OPMODE_LPM, MAX77686_BUCK_MODE_LPM, "LPM"), + MODE(OPMODE_ON, MAX77686_BUCK_MODE_ON, "ON"), +}; + +/* Buck: 5,6,7,8,9 */ +static struct dm_regulator_mode max77686_buck_mode_onoff[] = { + MODE(OPMODE_OFF, MAX77686_BUCK_MODE_OFF, "OFF"), + MODE(OPMODE_ON, MAX77686_BUCK_MODE_ON, "ON"), +}; + +static const char max77686_buck_addr[] = { + 0xff, 0x10, 0x12, 0x1c, 0x26, 0x30, 0x32, 0x34, 0x36, 0x38 +}; + +static int max77686_buck_volt2hex(int buck, int uV) +{ + unsigned int hex = 0; + unsigned int hex_max = 0; + + switch (buck) { + case 2: + case 3: + case 4: + /* hex = (uV - 600000) / 12500; */ + hex = (uV - MAX77686_BUCK_UV_LMIN) / MAX77686_BUCK_UV_LSTEP; + hex_max = MAX77686_BUCK234_VOLT_MAX_HEX; + /** + * Those use voltage scaller - temporary not implemented + * so return just 0 + */ + return -ENOSYS; + default: + /* hex = (uV - 750000) / 50000; */ + hex = (uV - MAX77686_BUCK_UV_HMIN) / MAX77686_BUCK_UV_HSTEP; + hex_max = MAX77686_BUCK_VOLT_MAX_HEX; + break; + } + + if (hex >= 0 && hex <= hex_max) + return hex; + + error("Value: %d uV is wrong for BUCK%d", uV, buck); + return -EINVAL; +} + +static int max77686_buck_hex2volt(int buck, int hex) +{ + unsigned uV = 0; + unsigned int hex_max = 0; + + if (hex < 0) + goto bad_hex; + + switch (buck) { + case 2: + case 3: + case 4: + hex_max = MAX77686_BUCK234_VOLT_MAX_HEX; + if (hex > hex_max) + goto bad_hex; + + /* uV = hex * 12500 + 600000; */ + uV = hex * MAX77686_BUCK_UV_LSTEP + MAX77686_BUCK_UV_LMIN; + break; + default: + hex_max = MAX77686_BUCK_VOLT_MAX_HEX; + if (hex > hex_max) + goto bad_hex; + + /* uV = hex * 50000 + 750000; */ + uV = hex * MAX77686_BUCK_UV_HSTEP + MAX77686_BUCK_UV_HMIN; + break; + } + + return uV; + +bad_hex: + error("Value: %#x is wrong for BUCK%d", hex, buck); + return -EINVAL; +} + +static int max77686_ldo_volt2hex(int ldo, int uV) +{ + unsigned int hex = 0; + + switch (ldo) { + case 1: + case 2: + case 6: + case 7: + case 8: + case 15: + hex = (uV - MAX77686_LDO_UV_MIN) / MAX77686_LDO_UV_LSTEP; + /* hex = (uV - 800000) / 25000; */ + break; + default: + hex = (uV - MAX77686_LDO_UV_MIN) / MAX77686_LDO_UV_HSTEP; + /* hex = (uV - 800000) / 50000; */ + } + + if (hex >= 0 && hex <= MAX77686_LDO_VOLT_MAX_HEX) + return hex; + + error("Value: %d uV is wrong for LDO%d", uV, ldo); + return -EINVAL; +} + +static int max77686_ldo_hex2volt(int ldo, int hex) +{ + unsigned int uV = 0; + + if (hex > MAX77686_LDO_VOLT_MAX_HEX) + goto bad_hex; + + switch (ldo) { + case 1: + case 2: + case 6: + case 7: + case 8: + case 15: + /* uV = hex * 25000 + 800000; */ + uV = hex * MAX77686_LDO_UV_LSTEP + MAX77686_LDO_UV_MIN; + break; + default: + /* uV = hex * 50000 + 800000; */ + uV = hex * MAX77686_LDO_UV_HSTEP + MAX77686_LDO_UV_MIN; + } + + return uV; + +bad_hex: + error("Value: %#x is wrong for ldo%d", hex, ldo); + return -EINVAL; +} + +static int max77686_ldo_hex2mode(int ldo, int hex) +{ + if (hex > MAX77686_LDO_MODE_MASK) + return -EINVAL; + + switch (hex) { + case MAX77686_LDO_MODE_OFF: + return OPMODE_OFF; + case MAX77686_LDO_MODE_LPM: /* == MAX77686_LDO_MODE_STANDBY: */ + /* The same mode values but different meaning for each ldo */ + switch (ldo) { + case 2: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 14: + case 15: + case 16: + return OPMODE_STANDBY; + default: + return OPMODE_LPM; + } + case MAX77686_LDO_MODE_STANDBY_LPM: + return OPMODE_STANDBY_LPM; + case MAX77686_LDO_MODE_ON: + return OPMODE_ON; + default: + return -EINVAL; + } +} + +static int max77686_buck_hex2mode(int buck, int hex) +{ + if (hex > MAX77686_BUCK_MODE_MASK) + return -EINVAL; + + switch (hex) { + case MAX77686_BUCK_MODE_OFF: + return OPMODE_OFF; + case MAX77686_BUCK_MODE_ON: + return OPMODE_ON; + case MAX77686_BUCK_MODE_STANDBY: + switch (buck) { + case 1: + case 2: + case 3: + case 4: + return OPMODE_STANDBY; + default: + return -EINVAL; + } + case MAX77686_BUCK_MODE_LPM: + switch (buck) { + case 2: + case 3: + case 4: + return OPMODE_LPM; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static int max77686_buck_modes(int buck, struct dm_regulator_mode **modesp) +{ + int ret = -EINVAL; + + if (buck < 1 || buck > MAX77686_BUCK_NUM) + return ret; + + switch (buck) { + case 1: + *modesp = max77686_buck_mode_standby; + ret = ARRAY_SIZE(max77686_buck_mode_standby); + break; + case 2: + case 3: + case 4: + *modesp = max77686_buck_mode_lpm; + ret = ARRAY_SIZE(max77686_buck_mode_lpm); + break; + default: + *modesp = max77686_buck_mode_onoff; + ret = ARRAY_SIZE(max77686_buck_mode_onoff); + } + + return ret; +} + +static int max77686_ldo_modes(int ldo, struct dm_regulator_mode **modesp, + struct udevice *dev) +{ + int ret = -EINVAL; + + if (ldo < 1 || ldo > MAX77686_LDO_NUM) + return ret; + + switch (ldo) { + case 2: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 14: + case 15: + case 16: + *modesp = max77686_ldo_mode_standby2; + ret = ARRAY_SIZE(max77686_ldo_mode_standby2); + break; + default: + *modesp = max77686_ldo_mode_standby1; + ret = ARRAY_SIZE(max77686_ldo_mode_standby1); + } + + return ret; +} + +static int max77686_ldo_val(struct udevice *dev, int op, int *uV) +{ + unsigned int ret, hex, adr; + unsigned char val; + int ldo; + + if (op == PMIC_OP_GET) + *uV = 0; + + ldo = dev->driver_data; + if (ldo < 1 || ldo > MAX77686_LDO_NUM) { + error("Wrong ldo number: %d", ldo); + return -EINVAL; + } + + adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1; + + ret = pmic_read(dev->parent, adr, &val, 1); + if (ret) + return ret; + + if (op == PMIC_OP_GET) { + val &= MAX77686_LDO_VOLT_MASK; + ret = max77686_ldo_hex2volt(ldo, val); + if (ret < 0) + return ret; + *uV = ret; + return 0; + } + + hex = max77686_ldo_volt2hex(ldo, *uV); + if (hex < 0) + return hex; + + val &= ~MAX77686_LDO_VOLT_MASK; + val |= hex; + ret = pmic_write(dev->parent, adr, &val, 1); + + return ret; +} + +static int max77686_buck_val(struct udevice *dev, int op, int *uV) +{ + unsigned int hex, ret, mask, adr; + unsigned char val; + int buck; + + buck = dev->driver_data; + if (buck < 1 || buck > MAX77686_BUCK_NUM) { + error("Wrong buck number: %d", buck); + return -EINVAL; + } + + if (op == PMIC_OP_GET) + *uV = 0; + + /* &buck_out = ctrl + 1 */ + adr = max77686_buck_addr[buck] + 1; + + /* mask */ + switch (buck) { + case 2: + case 3: + case 4: + /* Those use voltage scallers - will support in the future */ + mask = MAX77686_BUCK234_VOLT_MASK; + return -ENOSYS; + default: + mask = MAX77686_BUCK_VOLT_MASK; + } + + ret = pmic_read(dev->parent, adr, &val, 1); + if (ret) + return ret; + + if (op == PMIC_OP_GET) { + val &= mask; + ret = max77686_buck_hex2volt(buck, val); + if (ret < 0) + return ret; + *uV = ret; + return 0; + } + + hex = max77686_buck_volt2hex(buck, *uV); + if (hex < 0) + return hex; + + val &= ~mask; + val |= hex; + ret = pmic_write(dev->parent, adr, &val, 1); + + return ret; +} + +static int max77686_ldo_mode(struct udevice *dev, int op, int *opmode) +{ + unsigned int ret, adr, mode; + unsigned char val; + int ldo; + + if (op == PMIC_OP_GET) + *opmode = -EINVAL; + + ldo = dev->driver_data; + if (ldo < 1 || ldo > MAX77686_LDO_NUM) { + error("Wrong ldo number: %d", ldo); + return -EINVAL; + } + + adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1; + + ret = pmic_read(dev->parent, adr, &val, 1); + if (ret) + return ret; + + if (op == PMIC_OP_GET) { + val &= MAX77686_LDO_MODE_MASK; + ret = max77686_ldo_hex2mode(ldo, val); + if (ret < 0) + return ret; + *opmode = ret; + return 0; + } + + /* mode */ + switch (*opmode) { + case OPMODE_OFF: + mode = MAX77686_LDO_MODE_OFF; + break; + case OPMODE_LPM: + switch (ldo) { + case 2: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 14: + case 15: + case 16: + return -EINVAL; + default: + mode = MAX77686_LDO_MODE_LPM; + } + break; + case OPMODE_STANDBY: + switch (ldo) { + case 2: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 14: + case 15: + case 16: + mode = MAX77686_LDO_MODE_STANDBY; + break; + default: + return -EINVAL; + } + break; + case OPMODE_STANDBY_LPM: + mode = MAX77686_LDO_MODE_STANDBY_LPM; + break; + case OPMODE_ON: + mode = MAX77686_LDO_MODE_ON; + break; + default: + mode = 0xff; + } + + if (mode == 0xff) { + error("Wrong mode: %d for ldo%d", *opmode, ldo); + return -EINVAL; + } + + val &= ~MAX77686_LDO_MODE_MASK; + val |= mode; + ret = pmic_write(dev->parent, adr, &val, 1); + + return ret; +} + +static int max77686_ldo_enable(struct udevice *dev, int op, bool *enable) +{ + int ret, on_off; + + if (op == PMIC_OP_GET) { + ret = max77686_ldo_mode(dev, op, &on_off); + if (ret) + return ret; + + switch (on_off) { + case OPMODE_OFF: + *enable = 0; + break; + case OPMODE_ON: + *enable = 1; + break; + default: + return -EINVAL; + } + } else if (op == PMIC_OP_SET) { + switch (*enable) { + case 0: + on_off = OPMODE_OFF; + break; + case 1: + on_off = OPMODE_ON; + break; + default: + return -EINVAL; + } + + ret = max77686_ldo_mode(dev, op, &on_off); + if (ret) + return ret; + } + + return 0; +} + +static int max77686_buck_mode(struct udevice *dev, int op, int *opmode) +{ + unsigned int ret, mask, adr, mode, mode_shift; + unsigned char val; + int buck; + + buck = dev->driver_data; + if (buck < 1 || buck > MAX77686_BUCK_NUM) { + error("Wrong buck number: %d", buck); + return -EINVAL; + } + + adr = max77686_buck_addr[buck]; + + /* mask */ + switch (buck) { + case 2: + case 3: + case 4: + mode_shift = MAX77686_BUCK_MODE_SHIFT_2; + break; + default: + mode_shift = MAX77686_BUCK_MODE_SHIFT_1; + } + + mask = MAX77686_BUCK_MODE_MASK << mode_shift; + + ret = pmic_read(dev->parent, adr, &val, 1); + if (ret) + return ret; + + if (op == PMIC_OP_GET) { + val &= mask; + val >>= mode_shift; + ret = max77686_buck_hex2mode(buck, val); + if (ret < 0) + return ret; + *opmode = ret; + return 0; + } + + /* mode */ + switch (*opmode) { + case OPMODE_OFF: + mode = MAX77686_BUCK_MODE_OFF; + break; + case OPMODE_STANDBY: + switch (buck) { + case 1: + case 2: + case 3: + case 4: + mode = MAX77686_BUCK_MODE_STANDBY << mode_shift; + break; + default: + mode = 0xff; + } + break; + case OPMODE_LPM: + switch (buck) { + case 2: + case 3: + case 4: + mode = MAX77686_BUCK_MODE_LPM << mode_shift; + break; + default: + mode = 0xff; + } + break; + case OPMODE_ON: + mode = MAX77686_BUCK_MODE_ON << mode_shift; + break; + default: + mode = 0xff; + } + + if (mode == 0xff) { + error("Wrong mode: %d for buck: %d\n", *opmode, buck); + return -EINVAL; + } + + val &= ~mask; + val |= mode; + ret = pmic_write(dev->parent, adr, &val, 1); + + return ret; +} + +static int max77686_buck_enable(struct udevice *dev, int op, bool *enable) +{ + int ret, on_off; + + if (op == PMIC_OP_GET) { + ret = max77686_buck_mode(dev, op, &on_off); + if (ret) + return ret; + + switch (on_off) { + case OPMODE_OFF: + *enable = false; + break; + case OPMODE_ON: + *enable = true; + break; + default: + return -EINVAL; + } + } else if (op == PMIC_OP_SET) { + switch (*enable) { + case 0: + on_off = OPMODE_OFF; + break; + case 1: + on_off = OPMODE_ON; + break; + default: + return -EINVAL; + } + + ret = max77686_buck_mode(dev, op, &on_off); + if (ret) + return ret; + } + + return 0; +} + +static int max77686_ldo_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + + uc_pdata->type = REGULATOR_TYPE_LDO; + uc_pdata->mode_count = max77686_ldo_modes(dev->driver_data, + &uc_pdata->mode, dev); + + return 0; +} + +static int ldo_get_value(struct udevice *dev) +{ + int uV; + int ret; + + ret = max77686_ldo_val(dev, PMIC_OP_GET, &uV); + if (ret) + return ret; + + return uV; +} + +static int ldo_set_value(struct udevice *dev, int uV) +{ + return max77686_ldo_val(dev, PMIC_OP_SET, &uV); +} + +static bool ldo_get_enable(struct udevice *dev) +{ + bool enable = false; + int ret; + + ret = max77686_ldo_enable(dev, PMIC_OP_GET, &enable); + if (ret) + return ret; + + return enable; +} + +static int ldo_set_enable(struct udevice *dev, bool enable) +{ + return max77686_ldo_enable(dev, PMIC_OP_SET, &enable); +} + +static int ldo_get_mode(struct udevice *dev) +{ + int mode; + int ret; + + ret = max77686_ldo_mode(dev, PMIC_OP_GET, &mode); + if (ret) + return ret; + + return mode; +} + +static int ldo_set_mode(struct udevice *dev, int mode) +{ + return max77686_ldo_mode(dev, PMIC_OP_SET, &mode); +} + +static int max77686_buck_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + + uc_pdata->type = REGULATOR_TYPE_BUCK; + uc_pdata->mode_count = max77686_buck_modes(dev->driver_data, + &uc_pdata->mode); + + return 0; +} + +static int buck_get_value(struct udevice *dev) +{ + int uV; + int ret; + + ret = max77686_buck_val(dev, PMIC_OP_GET, &uV); + if (ret) + return ret; + + return uV; +} + +static int buck_set_value(struct udevice *dev, int uV) +{ + return max77686_buck_val(dev, PMIC_OP_SET, &uV); +} + +static bool buck_get_enable(struct udevice *dev) +{ + bool enable = false; + int ret; + + ret = max77686_buck_enable(dev, PMIC_OP_GET, &enable); + if (ret) + return ret; + + return enable; +} + +static int buck_set_enable(struct udevice *dev, bool enable) +{ + return max77686_buck_enable(dev, PMIC_OP_SET, &enable); +} + +static int buck_get_mode(struct udevice *dev) +{ + int mode; + int ret; + + ret = max77686_buck_mode(dev, PMIC_OP_GET, &mode); + if (ret) + return ret; + + return mode; +} + +static int buck_set_mode(struct udevice *dev, int mode) +{ + return max77686_buck_mode(dev, PMIC_OP_SET, &mode); +} + +static const struct dm_regulator_ops max77686_ldo_ops = { + .get_value = ldo_get_value, + .set_value = ldo_set_value, + .get_enable = ldo_get_enable, + .set_enable = ldo_set_enable, + .get_mode = ldo_get_mode, + .set_mode = ldo_set_mode, +}; + +U_BOOT_DRIVER(max77686_ldo) = { + .name = MAX77686_LDO_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &max77686_ldo_ops, + .probe = max77686_ldo_probe, +}; + +static const struct dm_regulator_ops max77686_buck_ops = { + .get_value = buck_get_value, + .set_value = buck_set_value, + .get_enable = buck_get_enable, + .set_enable = buck_set_enable, + .get_mode = buck_get_mode, + .set_mode = buck_set_mode, +}; + +U_BOOT_DRIVER(max77686_buck) = { + .name = MAX77686_BUCK_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &max77686_buck_ops, + .probe = max77686_buck_probe, +}; diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c new file mode 100644 index 0000000..31ffd44 --- /dev/null +++ b/drivers/power/regulator/regulator-uclass.c @@ -0,0 +1,332 @@ +/* + * Copyright (C) 2014-2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <fdtdec.h> +#include <errno.h> +#include <dm.h> +#include <dm/uclass-internal.h> +#include <power/pmic.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +int regulator_mode(struct udevice *dev, struct dm_regulator_mode **modep) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + + *modep = NULL; + + uc_pdata = dev_get_uclass_platdata(dev); + if (!uc_pdata) + return -ENXIO; + + *modep = uc_pdata->mode; + return uc_pdata->mode_count; +} + +int regulator_get_value(struct udevice *dev) +{ + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + + if (!ops || !ops->get_value) + return -ENOSYS; + + return ops->get_value(dev); +} + +int regulator_set_value(struct udevice *dev, int uV) +{ + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + + if (!ops || !ops->set_value) + return -ENOSYS; + + return ops->set_value(dev, uV); +} + +int regulator_get_current(struct udevice *dev) +{ + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + + if (!ops || !ops->get_current) + return -ENOSYS; + + return ops->get_current(dev); +} + +int regulator_set_current(struct udevice *dev, int uA) +{ + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + + if (!ops || !ops->set_current) + return -ENOSYS; + + return ops->set_current(dev, uA); +} + +bool regulator_get_enable(struct udevice *dev) +{ + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + + if (!ops || !ops->get_enable) + return -ENOSYS; + + return ops->get_enable(dev); +} + +int regulator_set_enable(struct udevice *dev, bool enable) +{ + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + + if (!ops || !ops->set_enable) + return -ENOSYS; + + return ops->set_enable(dev, enable); +} + +int regulator_get_mode(struct udevice *dev) +{ + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + + if (!ops || !ops->get_mode) + return -ENOSYS; + + return ops->get_mode(dev); +} + +int regulator_set_mode(struct udevice *dev, int mode) +{ + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + + if (!ops || !ops->set_mode) + return -ENOSYS; + + return ops->set_mode(dev, mode); +} + +int regulator_get_by_platname(const char *plat_name, struct udevice **devp) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + struct udevice *dev; + int ret; + + *devp = NULL; + + for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; + ret = uclass_find_next_device(&dev)) { + if (ret) + continue; + + uc_pdata = dev_get_uclass_platdata(dev); + if (!uc_pdata || strcmp(plat_name, uc_pdata->name)) + continue; + + return uclass_get_device_tail(dev, 0, devp); + } + + debug("%s: can't find: %s\n", __func__, plat_name); + + return -ENODEV; +} + +int regulator_get_by_devname(const char *devname, struct udevice **devp) +{ + return uclass_get_device_by_name(UCLASS_REGULATOR, devname, devp); +} + +static int failed(int ret, bool verbose, const char *fmt, ...) +{ + va_list args; + char buf[64]; + + if (verbose == false) + return ret; + + va_start(args, fmt); + vscnprintf(buf, sizeof(buf), fmt, args); + va_end(args); + + printf(buf); + + if (!ret) + return 0; + + printf(" (ret: %d)", ret); + + return ret; +} + +int regulator_autoset(const char *platname, + struct udevice **devp, + bool verbose) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + struct udevice *dev; + int ret; + + if (devp) + *devp = NULL; + + ret = regulator_get_by_platname(platname, &dev); + if (ret) { + error("Can get the regulator: %s!", platname); + return ret; + } + + uc_pdata = dev_get_uclass_platdata(dev); + if (!uc_pdata) { + error("Can get the regulator %s uclass platdata!", platname); + return -ENXIO; + } + + if (!uc_pdata->always_on && !uc_pdata->boot_on) + goto retdev; + + if (verbose) + printf("%s@%s: ", dev->name, uc_pdata->name); + + /* Those values are optional (-ENODATA if unset) */ + if ((uc_pdata->min_uV != -ENODATA) && + (uc_pdata->max_uV != -ENODATA) && + (uc_pdata->min_uV == uc_pdata->max_uV)) { + ret = regulator_set_value(dev, uc_pdata->min_uV); + if (failed(ret, verbose, "set %d uV", uc_pdata->min_uV)) + goto exit; + } + + /* Those values are optional (-ENODATA if unset) */ + if ((uc_pdata->min_uA != -ENODATA) && + (uc_pdata->max_uA != -ENODATA) && + (uc_pdata->min_uA == uc_pdata->max_uA)) { + ret = regulator_set_current(dev, uc_pdata->min_uA); + if (failed(ret, verbose, "; set %d uA", uc_pdata->min_uA)) + goto exit; + } + + ret = regulator_set_enable(dev, true); + if (failed(ret, verbose, "; enabling", uc_pdata->min_uA)) + goto exit; + +retdev: + if (devp) + *devp = dev; +exit: + if (verbose) + printf("\n"); + + return ret; +} + +int regulator_list_autoset(const char *list_platname[], + struct udevice *list_devp[], + bool verbose) +{ + struct udevice *dev; + int error = 0, i = 0, ret; + + while (list_platname[i]) { + ret = regulator_autoset(list_platname[i], &dev, verbose); + if (ret & !error) + error = ret; + + if (list_devp) + list_devp[i] = dev; + + i++; + } + + return error; +} + +static bool regulator_name_is_unique(struct udevice *check_dev, + const char *check_name) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + struct udevice *dev; + int check_len = strlen(check_name); + int ret; + int len; + + for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; + ret = uclass_find_next_device(&dev)) { + if (ret || dev == check_dev) + continue; + + uc_pdata = dev_get_uclass_platdata(dev); + len = strlen(uc_pdata->name); + if (len != check_len) + continue; + + if (!strcmp(uc_pdata->name, check_name)) + return false; + } + + return true; +} + +static int regulator_post_bind(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + int offset = dev->of_offset; + const void *blob = gd->fdt_blob; + const char *property = "regulator-name"; + + uc_pdata = dev_get_uclass_platdata(dev); + if (!uc_pdata) + return -ENXIO; + + /* Regulator's mandatory constraint */ + uc_pdata->name = fdt_getprop(blob, offset, property, NULL); + if (!uc_pdata->name) { + debug("%s: dev: %s has no property 'regulator-name'\n", + __func__, dev->name); + return -EINVAL; + } + + if (regulator_name_is_unique(dev, uc_pdata->name)) + return 0; + + error("\"%s\" of dev: \"%s\", has nonunique value: \"%s\"", + property, dev->name, uc_pdata->name); + + return -EINVAL; +} + +static int regulator_pre_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + int offset = dev->of_offset; + + uc_pdata = dev_get_uclass_platdata(dev); + if (!uc_pdata) + return -ENXIO; + + /* Regulator's optional constraints */ + uc_pdata->min_uV = fdtdec_get_int(gd->fdt_blob, offset, + "regulator-min-microvolt", -ENODATA); + uc_pdata->max_uV = fdtdec_get_int(gd->fdt_blob, offset, + "regulator-max-microvolt", -ENODATA); + uc_pdata->min_uA = fdtdec_get_int(gd->fdt_blob, offset, + "regulator-min-microamp", -ENODATA); + uc_pdata->max_uA = fdtdec_get_int(gd->fdt_blob, offset, + "regulator-max-microamp", -ENODATA); + uc_pdata->always_on = fdtdec_get_bool(gd->fdt_blob, offset, + "regulator-always-on"); + uc_pdata->boot_on = fdtdec_get_bool(gd->fdt_blob, offset, + "regulator-boot-on"); + + return 0; +} + +UCLASS_DRIVER(regulator) = { + .id = UCLASS_REGULATOR, + .name = "regulator", + .post_bind = regulator_post_bind, + .pre_probe = regulator_pre_probe, + .per_device_platdata_auto_alloc_size = + sizeof(struct dm_regulator_uclass_platdata), +}; diff --git a/drivers/power/regulator/sandbox.c b/drivers/power/regulator/sandbox.c new file mode 100644 index 0000000..2cca579 --- /dev/null +++ b/drivers/power/regulator/sandbox.c @@ -0,0 +1,355 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <errno.h> +#include <dm.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/sandbox_pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MODE(_id, _val, _name) [_id] = { \ + .id = _id, \ + .register_value = _val, \ + .name = _name, \ +} + +#define RANGE(_min, _max, _step) { \ + .min = _min, \ + .max = _max, \ + .step = _step, \ +} + +/* + * struct output_range - helper structure type to define the range of output + * operating values (current/voltage), limited by the PMIC IC design. + * + * @min - minimum value + * @max - maximum value + * @step - step value +*/ +struct output_range { + int min; + int max; + int step; +}; + +/* BUCK: 1,2 - voltage range */ +static struct output_range buck_voltage_range[] = { + RANGE(OUT_BUCK1_UV_MIN, OUT_BUCK1_UV_MAX, OUT_BUCK1_UV_STEP), + RANGE(OUT_BUCK2_UV_MIN, OUT_BUCK2_UV_MAX, OUT_BUCK2_UV_STEP), +}; + +/* BUCK: 1 - current range */ +static struct output_range buck_current_range[] = { + RANGE(OUT_BUCK1_UA_MIN, OUT_BUCK1_UA_MAX, OUT_BUCK1_UA_STEP), +}; + +/* BUCK operating modes */ +static struct dm_regulator_mode sandbox_buck_modes[] = { + MODE(BUCK_OM_OFF, OM2REG(BUCK_OM_OFF), "OFF"), + MODE(BUCK_OM_ON, OM2REG(BUCK_OM_ON), "ON"), + MODE(BUCK_OM_PWM, OM2REG(BUCK_OM_PWM), "PWM"), +}; + +/* LDO: 1,2 - voltage range */ +static struct output_range ldo_voltage_range[] = { + RANGE(OUT_LDO1_UV_MIN, OUT_LDO1_UV_MAX, OUT_LDO1_UV_STEP), + RANGE(OUT_LDO2_UV_MIN, OUT_LDO2_UV_MAX, OUT_LDO2_UV_STEP), +}; + +/* LDO: 1 - current range */ +static struct output_range ldo_current_range[] = { + RANGE(OUT_LDO1_UA_MIN, OUT_LDO1_UA_MAX, OUT_LDO1_UA_STEP), +}; + +/* LDO operating modes */ +static struct dm_regulator_mode sandbox_ldo_modes[] = { + MODE(LDO_OM_OFF, OM2REG(LDO_OM_OFF), "OFF"), + MODE(LDO_OM_ON, OM2REG(LDO_OM_ON), "ON"), + MODE(LDO_OM_SLEEP, OM2REG(LDO_OM_SLEEP), "SLEEP"), + MODE(LDO_OM_STANDBY, OM2REG(LDO_OM_STANDBY), "STANDBY"), +}; + +int out_get_value(struct udevice *dev, int output_count, int reg_type, + struct output_range *range) +{ + uint8_t reg_val; + uint reg; + int ret; + + if (dev->driver_data > output_count) { + error("Unknown regulator number: %lu for PMIC %s!", + dev->driver_data, dev->name); + return -EINVAL; + } + + reg = (dev->driver_data - 1) * OUT_REG_COUNT + reg_type; + ret = pmic_read(dev->parent, reg, ®_val, 1); + if (ret) { + error("PMIC read failed: %d\n", ret); + return ret; + } + + ret = REG2VAL(range[dev->driver_data - 1].min, + range[dev->driver_data - 1].step, + reg_val); + + return ret; +} + +static int out_set_value(struct udevice *dev, int output_count, int reg_type, + struct output_range *range, int value) +{ + uint8_t reg_val; + uint reg; + int ret; + int max_value; + + if (dev->driver_data > output_count) { + error("Unknown regulator number: %lu for PMIC %s!", + dev->driver_data, dev->name); + return -EINVAL; + } + + max_value = range[dev->driver_data - 1].max; + if (value > max_value) { + error("Wrong value for %s: %lu. Max is: %d.", + dev->name, dev->driver_data, max_value); + return -EINVAL; + } + + reg_val = VAL2REG(range[dev->driver_data - 1].min, + range[dev->driver_data - 1].step, + value); + + reg = (dev->driver_data - 1) * OUT_REG_COUNT + reg_type; + ret = pmic_write(dev->parent, reg, ®_val, 1); + if (ret) { + error("PMIC write failed: %d\n", ret); + return ret; + } + + return 0; +} + +static int out_get_mode(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + uint8_t reg_val; + uint reg; + int ret; + int i; + + uc_pdata = dev_get_uclass_platdata(dev); + + reg = (dev->driver_data - 1) * OUT_REG_COUNT + OUT_REG_OM; + ret = pmic_read(dev->parent, reg, ®_val, 1); + if (ret) { + error("PMIC read failed: %d\n", ret); + return ret; + } + + for (i = 0; i < uc_pdata->mode_count; i++) { + if (reg_val == uc_pdata->mode[i].register_value) + return uc_pdata->mode[i].id; + } + + error("Unknown operation mode for %s!", dev->name); + return -EINVAL; +} + +static int out_set_mode(struct udevice *dev, int mode) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + int reg_val = -1; + uint reg; + int ret; + int i; + + uc_pdata = dev_get_uclass_platdata(dev); + + if (mode >= uc_pdata->mode_count) + return -EINVAL; + + for (i = 0; i < uc_pdata->mode_count; i++) { + if (mode == uc_pdata->mode[i].id) { + reg_val = uc_pdata->mode[i].register_value; + break; + } + } + + if (reg_val == -1) { + error("Unknown operation mode for %s!", dev->name); + return -EINVAL; + } + + reg = (dev->driver_data - 1) * OUT_REG_COUNT + OUT_REG_OM; + ret = pmic_write(dev->parent, reg, (uint8_t *)®_val, 1); + if (ret) { + error("PMIC write failed: %d\n", ret); + return ret; + } + + return 0; +} + +static int buck_get_voltage(struct udevice *dev) +{ + return out_get_value(dev, SANDBOX_BUCK_COUNT, OUT_REG_UV, + buck_voltage_range); +} + +static int buck_set_voltage(struct udevice *dev, int uV) +{ + return out_set_value(dev, SANDBOX_BUCK_COUNT, OUT_REG_UV, + buck_voltage_range, uV); +} + +static int buck_get_current(struct udevice *dev) +{ + /* BUCK2 - unsupported */ + if (dev->driver_data == 2) + return -ENOSYS; + + return out_get_value(dev, SANDBOX_BUCK_COUNT, OUT_REG_UA, + buck_current_range); +} + +static int buck_set_current(struct udevice *dev, int uA) +{ + /* BUCK2 - unsupported */ + if (dev->driver_data == 2) + return -ENOSYS; + + return out_set_value(dev, SANDBOX_BUCK_COUNT, OUT_REG_UA, + buck_current_range, uA); +} + +static bool buck_get_enable(struct udevice *dev) +{ + if (out_get_mode(dev) == BUCK_OM_OFF) + return false; + + return true; +} + +static int buck_set_enable(struct udevice *dev, bool enable) +{ + return out_set_mode(dev, enable ? BUCK_OM_ON : BUCK_OM_OFF); +} + +static int sandbox_buck_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + + uc_pdata->type = REGULATOR_TYPE_BUCK; + uc_pdata->mode = sandbox_buck_modes; + uc_pdata->mode_count = ARRAY_SIZE(sandbox_buck_modes); + + return 0; +} + +static const struct dm_regulator_ops sandbox_buck_ops = { + .get_value = buck_get_voltage, + .set_value = buck_set_voltage, + .get_current = buck_get_current, + .set_current = buck_set_current, + .get_enable = buck_get_enable, + .set_enable = buck_set_enable, + .get_mode = out_get_mode, + .set_mode = out_set_mode, +}; + +U_BOOT_DRIVER(sandbox_buck) = { + .name = SANDBOX_BUCK_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &sandbox_buck_ops, + .probe = sandbox_buck_probe, +}; + +static int ldo_get_voltage(struct udevice *dev) +{ + return out_get_value(dev, SANDBOX_LDO_COUNT, OUT_REG_UV, + ldo_voltage_range); +} + +static int ldo_set_voltage(struct udevice *dev, int uV) +{ + return out_set_value(dev, SANDBOX_LDO_COUNT, OUT_REG_UV, + ldo_voltage_range, uV); +} + +static int ldo_get_current(struct udevice *dev) +{ + /* LDO2 - unsupported */ + if (dev->driver_data == 2) + return -ENOSYS; + + return out_get_value(dev, SANDBOX_LDO_COUNT, OUT_REG_UA, + ldo_current_range); +} + +static int ldo_set_current(struct udevice *dev, int uA) +{ + /* LDO2 - unsupported */ + if (dev->driver_data == 2) + return -ENOSYS; + + return out_set_value(dev, SANDBOX_LDO_COUNT, OUT_REG_UA, + ldo_current_range, uA); +} + +static bool ldo_get_enable(struct udevice *dev) +{ + if (out_get_mode(dev) == LDO_OM_OFF) + return false; + + return true; +} + +static int ldo_set_enable(struct udevice *dev, bool enable) +{ + return out_set_mode(dev, enable ? LDO_OM_ON : LDO_OM_OFF); +} + +static int sandbox_ldo_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + + uc_pdata->type = REGULATOR_TYPE_LDO; + uc_pdata->mode = sandbox_ldo_modes; + uc_pdata->mode_count = ARRAY_SIZE(sandbox_ldo_modes); + + return 0; +} + +static const struct dm_regulator_ops sandbox_ldo_ops = { + .get_value = ldo_get_voltage, + .set_value = ldo_set_voltage, + .get_current = ldo_get_current, + .set_current = ldo_set_current, + .get_enable = ldo_get_enable, + .set_enable = ldo_set_enable, + .get_mode = out_get_mode, + .set_mode = out_set_mode, +}; + +U_BOOT_DRIVER(sandbox_ldo) = { + .name = SANDBOX_LDO_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &sandbox_ldo_ops, + .probe = sandbox_ldo_probe, +}; diff --git a/drivers/pwm/pwm-imx-util.c b/drivers/pwm/pwm-imx-util.c index f1d0b35..79d86028 100644 --- a/drivers/pwm/pwm-imx-util.c +++ b/drivers/pwm/pwm-imx-util.c @@ -56,7 +56,7 @@ int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c, *prescale = *period_c / 0x10000 + 1; *period_c /= *prescale; - c = (unsigned long long)(*period_c * duty_ns); + c = *period_c * (unsigned long long)duty_ns; do_div(c, period_ns); *duty_c = c; diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index e69de29..bd63621 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -0,0 +1,8 @@ +config DM_RTC + bool "Enable Driver Model for RTC drivers" + depends on DM + help + Enable drver model for real-time-clock drivers. The RTC uclass + then provides the rtc_get()/rtc_set() interface, delegating to + drivers to perform the actual functions. See rtc.h for a + description of the API. diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index fdcbc00..3092de1 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -7,6 +7,8 @@ #ccflags-y += -DDEBUG +obj-$(CONFIG_DM_RTC) += rtc-uclass.o + obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o obj-$(CONFIG_RTC_BFIN) += bfin_rtc.o obj-y += date.o @@ -24,6 +26,7 @@ obj-$(CONFIG_RTC_DS164x) += ds164x.o obj-$(CONFIG_RTC_DS174x) += ds174x.o obj-$(CONFIG_RTC_DS3231) += ds3231.o obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o +obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o obj-$(CONFIG_RTC_IMXDI) += imxdi.o obj-$(CONFIG_RTC_ISL1208) += isl1208.o obj-$(CONFIG_RTC_M41T11) += m41t11.o @@ -49,4 +52,5 @@ obj-$(CONFIG_RTC_RTC4543) += rtc4543.o obj-$(CONFIG_RTC_RV3029) += rv3029.o obj-$(CONFIG_RTC_RX8025) += rx8025.o obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o +obj-$(CONFIG_SANDBOX) += sandbox_rtc.o obj-$(CONFIG_RTC_X1205) += x1205.o diff --git a/drivers/rtc/at91sam9_rtt.c b/drivers/rtc/at91sam9_rtt.c index 714dd2a..a684ad6 100644 --- a/drivers/rtc/at91sam9_rtt.c +++ b/drivers/rtc/at91sam9_rtt.c @@ -44,7 +44,7 @@ int rtc_get (struct rtc_time *tmp) } while (tim!=tim2); off = readl(&gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); /* off==0 means time is invalid, but we ignore that */ - to_tm (tim+off, tmp); + rtc_to_tm(tim+off, tmp); return 0; } @@ -54,8 +54,7 @@ int rtc_set (struct rtc_time *tmp) at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; ulong tim; - tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + tim = rtc_mktime(tmp); /* clear alarm, set prescaler to 32768, clear counter */ writel(32768+AT91_RTT_RTTRST, &rtt->mr); diff --git a/drivers/rtc/bfin_rtc.c b/drivers/rtc/bfin_rtc.c index 4cf2d83..a079a1d 100644 --- a/drivers/rtc/bfin_rtc.c +++ b/drivers/rtc/bfin_rtc.c @@ -67,8 +67,7 @@ int rtc_set(struct rtc_time *tmp) wait_for_complete(); /* Calculate number of seconds this incoming time represents */ - remain = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + remain = rtc_mktime(tmp); /* Figure out how many days since epoch */ days = remain / NUM_SECS_IN_DAY; @@ -114,7 +113,7 @@ int rtc_get(struct rtc_time *tmp) /* Calculate the total number of seconds since epoch */ time_in_sec = (tm_sec) + MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hr) + DAYS_TO_SECS(tm_day); - to_tm(time_in_sec, tmp); + rtc_to_tm(time_in_sec, tmp); return 0; } diff --git a/drivers/rtc/date.c b/drivers/rtc/date.c index 15e6db0..8c643a0 100644 --- a/drivers/rtc/date.c +++ b/drivers/rtc/date.c @@ -11,6 +11,7 @@ #include <common.h> #include <command.h> +#include <errno.h> #include <rtc.h> #if defined(CONFIG_CMD_DATE) || defined(CONFIG_TIMESTAMP) @@ -30,13 +31,15 @@ static int month_days[12] = { /* * This only works for the Gregorian calendar - i.e. after 1752 (in the UK) */ -void GregorianDay(struct rtc_time * tm) +int rtc_calc_weekday(struct rtc_time *tm) { int leapsToDate; int lastYear; int day; int MonthOffset[] = { 0,31,59,90,120,151,181,212,243,273,304,334 }; + if (tm->tm_year < 1753) + return -EINVAL; lastYear=tm->tm_year-1; /* @@ -64,9 +67,11 @@ void GregorianDay(struct rtc_time * tm) day += lastYear*365 + leapsToDate + MonthOffset[tm->tm_mon-1] + tm->tm_mday; tm->tm_wday=day%7; + + return 0; } -void to_tm(int tim, struct rtc_time * tm) +int rtc_to_tm(int tim, struct rtc_time *tm) { register int i; register long hms, day; @@ -98,10 +103,14 @@ void to_tm(int tim, struct rtc_time * tm) /* Days are what is left over (+1) from all that. */ tm->tm_mday = day + 1; + /* Zero unused fields */ + tm->tm_yday = 0; + tm->tm_isdst = 0; + /* * Determine the day of week */ - GregorianDay(tm); + return rtc_calc_weekday(tm); } /* Converts Gregorian date to seconds since 1970-01-01 00:00:00. @@ -119,22 +128,23 @@ void to_tm(int tim, struct rtc_time * tm) * machines were long is 32-bit! (However, as time_t is signed, we * will already get problems at other places on 2038-01-19 03:14:08) */ -unsigned long -mktime (unsigned int year, unsigned int mon, - unsigned int day, unsigned int hour, - unsigned int min, unsigned int sec) +unsigned long rtc_mktime(const struct rtc_time *tm) { - if (0 >= (int) (mon -= 2)) { /* 1..12 -> 11,12,1..10 */ + int mon = tm->tm_mon; + int year = tm->tm_year; + int days, hours; + + mon -= 2; + if (0 >= (int)mon) { /* 1..12 -> 11,12,1..10 */ mon += 12; /* Puts Feb last since it has leap day */ year -= 1; } - return ((( - (unsigned long) (year/4 - year/100 + year/400 + 367*mon/12 + day) + - year*365 - 719499 - )*24 + hour /* now have hours */ - )*60 + min /* now have minutes */ - )*60 + sec; /* finally seconds */ + days = (unsigned long)(year / 4 - year / 100 + year / 400 + + 367 * mon / 12 + tm->tm_mday) + + year * 365 - 719499; + hours = days * 24 + tm->tm_hour; + return (hours * 60 + tm->tm_min) * 60 + tm->tm_sec; } #endif diff --git a/drivers/rtc/ds1306.c b/drivers/rtc/ds1306.c index 1ec1837..7dd3e19 100644 --- a/drivers/rtc/ds1306.c +++ b/drivers/rtc/ds1306.c @@ -110,7 +110,7 @@ int rtc_get (struct rtc_time *tmp) immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ udelay (10); - GregorianDay (tmp); /* Determine the day of week */ + rtc_calc_weekday(tmp); /* Determine the day of week */ debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, @@ -180,8 +180,7 @@ int rtc_set (struct rtc_time *tmp) { ulong tim; - tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + tim = rtc_mktime(tmp); immap->im_sitk.sitk_rtck = KAPWR_KEY; immap->im_sit.sit_rtc = tim; diff --git a/drivers/rtc/ds1374.c b/drivers/rtc/ds1374.c index 427b1eb..7847357 100644 --- a/drivers/rtc/ds1374.c +++ b/drivers/rtc/ds1374.c @@ -118,7 +118,7 @@ int rtc_get (struct rtc_time *tm){ DEBUGR ("Get RTC s since 1.1.1970: %ld\n", time1); - to_tm(time1, tm); /* To Gregorian Date */ + rtc_to_tm(time1, tm); /* To Gregorian Date */ if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF) { printf ("### Warning: RTC oscillator has stopped\n"); @@ -147,9 +147,7 @@ int rtc_set (struct rtc_time *tmp){ if (tmp->tm_year < 1970 || tmp->tm_year > 2069) printf("WARNING: year should be between 1970 and 2069!\n"); - time = mktime(tmp->tm_year, tmp->tm_mon, - tmp->tm_mday, tmp->tm_hour, - tmp->tm_min, tmp->tm_sec); + time = rtc_mktime(tmp); DEBUGR ("Set RTC s since 1.1.1970: %ld (0x%02lx)\n", time, time); diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c index 713dad2..7d0cfb3 100644 --- a/drivers/rtc/ftrtc010.c +++ b/drivers/rtc/ftrtc010.c @@ -86,7 +86,7 @@ int rtc_get(struct rtc_time *tmp) now = ftrtc010_time() + readl(&rtc->record); #endif - to_tm(now, tmp); + rtc_to_tm(now, tmp); return 0; } @@ -104,8 +104,7 @@ int rtc_set(struct rtc_time *tmp) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - new = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour, - tmp->tm_min, tmp->tm_sec); + new = rtc_mktime(tmp); now = ftrtc010_time(); diff --git a/drivers/rtc/i2c_rtc_emul.c b/drivers/rtc/i2c_rtc_emul.c new file mode 100644 index 0000000..20827fd --- /dev/null +++ b/drivers/rtc/i2c_rtc_emul.c @@ -0,0 +1,236 @@ +/* + * Simulate an I2C real time clock + * + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This is a test driver. It starts off with the current time of the machine, + * but also supports setting the time, using an offset from the current + * clock. This driver is only intended for testing, not accurate + * time-keeping. It does not change the system time. + */ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <i2c.h> +#include <os.h> +#include <rtc.h> +#include <asm/rtc.h> +#include <asm/test.h> + +#ifdef DEBUG +#define debug_buffer print_buffer +#else +#define debug_buffer(x, ...) +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/** + * struct sandbox_i2c_rtc_plat_data - platform data for the RTC + * + * @base_time: Base system time when RTC device was bound + * @offset: RTC offset from current system time + * @use_system_time: true to use system time, false to use @base_time + * @reg: Register values + */ +struct sandbox_i2c_rtc_plat_data { + long base_time; + long offset; + bool use_system_time; + u8 reg[REG_COUNT]; +}; + +struct sandbox_i2c_rtc { + unsigned int offset_secs; +}; + +long sandbox_i2c_rtc_set_offset(struct udevice *dev, bool use_system_time, + int offset) +{ + struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev); + long old_offset; + + old_offset = plat->offset; + plat->use_system_time = use_system_time; + if (offset != -1) + plat->offset = offset; + + return old_offset; +} + +long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time) +{ + struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev); + long old_base_time; + + old_base_time = plat->base_time; + if (base_time != -1) + plat->base_time = base_time; + + return old_base_time; +} + +static void reset_time(struct udevice *dev) +{ + struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev); + struct rtc_time now; + + os_localtime(&now); + plat->base_time = rtc_mktime(&now); + plat->offset = 0; + plat->use_system_time = true; +} + +static int sandbox_i2c_rtc_get(struct udevice *dev, struct rtc_time *time) +{ + struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev); + struct rtc_time tm_now; + long now; + + if (plat->use_system_time) { + os_localtime(&tm_now); + now = rtc_mktime(&tm_now); + } else { + now = plat->base_time; + } + + return rtc_to_tm(now + plat->offset, time); +} + +static int sandbox_i2c_rtc_set(struct udevice *dev, const struct rtc_time *time) +{ + struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev); + struct rtc_time tm_now; + long now; + + if (plat->use_system_time) { + os_localtime(&tm_now); + now = rtc_mktime(&tm_now); + } else { + now = plat->base_time; + } + plat->offset = rtc_mktime(time) - now; + + return 0; +} + +/* Update the current time in the registers */ +static int sandbox_i2c_rtc_prepare_read(struct udevice *emul) +{ + struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(emul); + struct rtc_time time; + int ret; + + ret = sandbox_i2c_rtc_get(emul, &time); + if (ret) + return ret; + + plat->reg[REG_SEC] = time.tm_sec; + plat->reg[REG_MIN] = time.tm_min; + plat->reg[REG_HOUR] = time.tm_hour; + plat->reg[REG_MDAY] = time.tm_mday; + plat->reg[REG_MON] = time.tm_mon; + plat->reg[REG_YEAR] = time.tm_year - 1900; + plat->reg[REG_WDAY] = time.tm_wday; + + return 0; +} + +static int sandbox_i2c_rtc_complete_write(struct udevice *emul) +{ + struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(emul); + struct rtc_time time; + int ret; + + time.tm_sec = plat->reg[REG_SEC]; + time.tm_min = plat->reg[REG_MIN]; + time.tm_hour = plat->reg[REG_HOUR]; + time.tm_mday = plat->reg[REG_MDAY]; + time.tm_mon = plat->reg[REG_MON]; + time.tm_year = plat->reg[REG_YEAR] + 1900; + time.tm_wday = plat->reg[REG_WDAY]; + + ret = sandbox_i2c_rtc_set(emul, &time); + if (ret) + return ret; + + return 0; +} + +static int sandbox_i2c_rtc_xfer(struct udevice *emul, struct i2c_msg *msg, + int nmsgs) +{ + struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(emul); + uint offset = 0; + int ret; + + debug("\n%s\n", __func__); + ret = sandbox_i2c_rtc_prepare_read(emul); + if (ret) + return ret; + for (; nmsgs > 0; nmsgs--, msg++) { + int len; + u8 *ptr; + + len = msg->len; + debug(" %s: msg->len=%d", + msg->flags & I2C_M_RD ? "read" : "write", + msg->len); + if (msg->flags & I2C_M_RD) { + debug(", offset %x, len %x: ", offset, len); + + /* Read the register */ + memcpy(msg->buf, plat->reg + offset, len); + memset(msg->buf + len, '\xff', msg->len - len); + debug_buffer(0, msg->buf, 1, msg->len, 0); + } else if (len >= 1) { + ptr = msg->buf; + offset = *ptr++ & (REG_COUNT - 1); + len--; + debug(", set offset %x: ", offset); + debug_buffer(0, msg->buf, 1, msg->len, 0); + + /* Write the register */ + memcpy(plat->reg + offset, ptr, len); + if (offset == REG_RESET) + reset_time(emul); + } + } + ret = sandbox_i2c_rtc_complete_write(emul); + if (ret) + return ret; + + return 0; +} + +struct dm_i2c_ops sandbox_i2c_rtc_emul_ops = { + .xfer = sandbox_i2c_rtc_xfer, +}; + +static int sandbox_i2c_rtc_bind(struct udevice *dev) +{ + reset_time(dev); + + return 0; +} + +static const struct udevice_id sandbox_i2c_rtc_ids[] = { + { .compatible = "sandbox,i2c-rtc" }, + { } +}; + +U_BOOT_DRIVER(sandbox_i2c_rtc_emul) = { + .name = "sandbox_i2c_rtc_emul", + .id = UCLASS_I2C_EMUL, + .of_match = sandbox_i2c_rtc_ids, + .bind = sandbox_i2c_rtc_bind, + .priv_auto_alloc_size = sizeof(struct sandbox_i2c_rtc), + .platdata_auto_alloc_size = sizeof(struct sandbox_i2c_rtc_plat_data), + .ops = &sandbox_i2c_rtc_emul_ops, +}; diff --git a/drivers/rtc/imxdi.c b/drivers/rtc/imxdi.c index 0d7d736..17519ce 100644 --- a/drivers/rtc/imxdi.c +++ b/drivers/rtc/imxdi.c @@ -192,7 +192,7 @@ int rtc_get(struct rtc_time *tmp) } now = __raw_readl(&data.regs->dtcmr); - to_tm(now, tmp); + rtc_to_tm(now, tmp); err: return rc; @@ -209,8 +209,7 @@ int rtc_set(struct rtc_time *tmp) goto err; } - now = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + now = rtc_mktime(tmp); /* zero the fractional part first */ rc = DI_WRITE_WAIT(0, dtclr); if (rc == 0) diff --git a/drivers/rtc/mc13xxx-rtc.c b/drivers/rtc/mc13xxx-rtc.c index 528247a..3e46336 100644 --- a/drivers/rtc/mc13xxx-rtc.c +++ b/drivers/rtc/mc13xxx-rtc.c @@ -36,7 +36,7 @@ int rtc_get(struct rtc_time *rtc) tim = day1 * 86400 + time; - to_tm(tim, rtc); + rtc_to_tm(tim, rtc); rtc->tm_yday = 0; rtc->tm_isdst = 0; @@ -51,8 +51,7 @@ int rtc_set(struct rtc_time *rtc) if (!p) return -1; - time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday, - rtc->tm_hour, rtc->tm_min, rtc->tm_sec); + time = rtc_mktime(rtc); day = time / 86400; time %= 86400; diff --git a/drivers/rtc/mcfrtc.c b/drivers/rtc/mcfrtc.c index 8961ca4..e02e297 100644 --- a/drivers/rtc/mcfrtc.c +++ b/drivers/rtc/mcfrtc.c @@ -38,7 +38,7 @@ int rtc_get(struct rtc_time *tmp) tim = (tim * 60) + rtc_mins; tim = (tim * 60) + rtc->seconds; - to_tm(tim, tmp); + rtc_to_tm(tim, tmp); tmp->tm_yday = 0; tmp->tm_isdst = 0; diff --git a/drivers/rtc/mpc8xx.c b/drivers/rtc/mpc8xx.c index d239dae..147a225 100644 --- a/drivers/rtc/mpc8xx.c +++ b/drivers/rtc/mpc8xx.c @@ -26,7 +26,7 @@ int rtc_get (struct rtc_time *tmp) tim = immr->im_sit.sit_rtc; - to_tm (tim, tmp); + rtc_to_tm(tim, tmp); debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, @@ -44,8 +44,7 @@ int rtc_set (struct rtc_time *tmp) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + tim = rtc_mktime(tmp); immr->im_sitk.sitk_rtck = KAPWR_KEY; immr->im_sit.sit_rtc = tim; diff --git a/drivers/rtc/mx27rtc.c b/drivers/rtc/mx27rtc.c index ae6595b..29ccdf1 100644 --- a/drivers/rtc/mx27rtc.c +++ b/drivers/rtc/mx27rtc.c @@ -30,7 +30,7 @@ int rtc_get(struct rtc_time *time) sec += min * 60 + hour * 3600 + day * 24 * 3600; - to_tm(sec, time); + rtc_to_tm(sec, time); return 0; } @@ -40,8 +40,7 @@ int rtc_set(struct rtc_time *time) struct rtc_regs *rtc_regs = (struct rtc_regs *)IMX_RTC_BASE; uint32_t day, hour, min, sec; - sec = mktime(time->tm_year, time->tm_mon, time->tm_mday, - time->tm_hour, time->tm_min, time->tm_sec); + sec = rtc_mktime(time); day = sec / (24 * 3600); sec = sec % (24 * 3600); diff --git a/drivers/rtc/mxsrtc.c b/drivers/rtc/mxsrtc.c index 32ba8a3..6e32154 100644 --- a/drivers/rtc/mxsrtc.c +++ b/drivers/rtc/mxsrtc.c @@ -43,7 +43,7 @@ int rtc_get(struct rtc_time *time) uint32_t secs; secs = readl(&rtc_regs->hw_rtc_seconds); - to_tm(secs, time); + rtc_to_tm(secs, time); return 0; } @@ -52,8 +52,7 @@ int rtc_set(struct rtc_time *time) { uint32_t secs; - secs = mktime(time->tm_year, time->tm_mon, time->tm_mday, - time->tm_hour, time->tm_min, time->tm_sec); + secs = rtc_mktime(time); return mxs_rtc_set_time(secs); } diff --git a/drivers/rtc/pl031.c b/drivers/rtc/pl031.c index c4d1259..fc83049 100644 --- a/drivers/rtc/pl031.c +++ b/drivers/rtc/pl031.c @@ -72,8 +72,7 @@ int rtc_set(struct rtc_time *tmp) } /* Calculate number of seconds this incoming time represents */ - tim = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + tim = rtc_mktime(tmp); RTC_WRITE_REG(RTC_LR, tim); @@ -97,7 +96,7 @@ int rtc_get(struct rtc_time *tmp) tim = RTC_READ_REG(RTC_DR); - to_tm (tim, tmp); + rtc_to_tm(tim, tmp); debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c new file mode 100644 index 0000000..fe74c69 --- /dev/null +++ b/drivers/rtc/rtc-uclass.c @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <rtc.h> + +int dm_rtc_get(struct udevice *dev, struct rtc_time *time) +{ + struct rtc_ops *ops = rtc_get_ops(dev); + + assert(ops); + if (!ops->get) + return -ENOSYS; + return ops->get(dev, time); +} + +int dm_rtc_set(struct udevice *dev, struct rtc_time *time) +{ + struct rtc_ops *ops = rtc_get_ops(dev); + + assert(ops); + if (!ops->set) + return -ENOSYS; + return ops->set(dev, time); +} + +int dm_rtc_reset(struct udevice *dev) +{ + struct rtc_ops *ops = rtc_get_ops(dev); + + assert(ops); + if (!ops->reset) + return -ENOSYS; + return ops->reset(dev); +} + +int rtc_read8(struct udevice *dev, unsigned int reg) +{ + struct rtc_ops *ops = rtc_get_ops(dev); + + assert(ops); + if (!ops->read8) + return -ENOSYS; + return ops->read8(dev, reg); +} + +int rtc_write8(struct udevice *dev, unsigned int reg, int val) +{ + struct rtc_ops *ops = rtc_get_ops(dev); + + assert(ops); + if (!ops->write8) + return -ENOSYS; + return ops->write8(dev, reg, val); +} + +int rtc_read32(struct udevice *dev, unsigned int reg, u32 *valuep) +{ + u32 value = 0; + int ret; + int i; + + for (i = 0; i < sizeof(value); i++) { + ret = rtc_read8(dev, reg + i); + if (ret) + return ret; + value |= ret << (i << 3); + } + + *valuep = value; + return 0; +} + +int rtc_write32(struct udevice *dev, unsigned int reg, u32 value) +{ + int i, ret; + + for (i = 0; i < sizeof(value); i++) { + ret = rtc_write8(dev, reg + i, (value >> (i << 3)) & 0xff); + if (ret) + return ret; + } + + return 0; +} + +UCLASS_DRIVER(rtc) = { + .name = "rtc", + .id = UCLASS_RTC, +}; diff --git a/drivers/rtc/sandbox_rtc.c b/drivers/rtc/sandbox_rtc.c new file mode 100644 index 0000000..f292fbe --- /dev/null +++ b/drivers/rtc/sandbox_rtc.c @@ -0,0 +1,106 @@ +/* + * (C) Copyright 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <i2c.h> +#include <rtc.h> +#include <asm/rtc.h> + +#define REG_COUNT 0x80 + +static int sandbox_rtc_get(struct udevice *dev, struct rtc_time *time) +{ + time->tm_sec = dm_i2c_reg_read(dev, REG_SEC); + if (time->tm_sec < 0) + return time->tm_sec; + time->tm_min = dm_i2c_reg_read(dev, REG_MIN); + if (time->tm_min < 0) + return time->tm_min; + time->tm_hour = dm_i2c_reg_read(dev, REG_HOUR); + if (time->tm_hour < 0) + return time->tm_hour; + time->tm_mday = dm_i2c_reg_read(dev, REG_MDAY); + if (time->tm_mday < 0) + return time->tm_mday; + time->tm_mon = dm_i2c_reg_read(dev, REG_MON); + if (time->tm_mon < 0) + return time->tm_mon; + time->tm_year = dm_i2c_reg_read(dev, REG_YEAR); + if (time->tm_year < 0) + return time->tm_year; + time->tm_year += 1900; + time->tm_wday = dm_i2c_reg_read(dev, REG_WDAY); + if (time->tm_wday < 0) + return time->tm_wday; + + return 0; +} + +static int sandbox_rtc_set(struct udevice *dev, const struct rtc_time *time) +{ + int ret; + + ret = dm_i2c_reg_write(dev, REG_SEC, time->tm_sec); + if (ret < 0) + return ret; + ret = dm_i2c_reg_write(dev, REG_MIN, time->tm_min); + if (ret < 0) + return ret; + ret = dm_i2c_reg_write(dev, REG_HOUR, time->tm_hour); + if (ret < 0) + return ret; + ret = dm_i2c_reg_write(dev, REG_MDAY, time->tm_mday); + if (ret < 0) + return ret; + ret = dm_i2c_reg_write(dev, REG_MON, time->tm_mon); + if (ret < 0) + return ret; + ret = dm_i2c_reg_write(dev, REG_YEAR, time->tm_year - 1900); + if (ret < 0) + return ret; + ret = dm_i2c_reg_write(dev, REG_WDAY, time->tm_wday); + if (ret < 0) + return ret; + + return 0; +} + +static int sandbox_rtc_reset(struct udevice *dev) +{ + return dm_i2c_reg_write(dev, REG_RESET, 0); +} + +static int sandbox_rtc_read8(struct udevice *dev, unsigned int reg) +{ + return dm_i2c_reg_read(dev, reg); +} + +static int sandbox_rtc_write8(struct udevice *dev, unsigned int reg, int val) +{ + return dm_i2c_reg_write(dev, reg, val); +} + +static const struct rtc_ops sandbox_rtc_ops = { + .get = sandbox_rtc_get, + .set = sandbox_rtc_set, + .reset = sandbox_rtc_reset, + .read8 = sandbox_rtc_read8, + .write8 = sandbox_rtc_write8, +}; + +static const struct udevice_id sandbox_rtc_ids[] = { + { .compatible = "sandbox-rtc" }, + { } +}; + +U_BOOT_DRIVER(rtc_sandbox) = { + .name = "rtc-sandbox", + .id = UCLASS_RTC, + .of_match = sandbox_rtc_ids, + .ops = &sandbox_rtc_ops, +}; diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 2124161..ad503af 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -20,6 +20,9 @@ #include <dm/platform_data/serial_pl01x.h> #include <linux/compiler.h> #include "serial_pl01x_internal.h" +#include <fdtdec.h> + +DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_DM_SERIAL @@ -28,7 +31,6 @@ static enum pl01x_type pl01x_type __attribute__ ((section(".data"))); static struct pl01x_regs *base_regs __attribute__ ((section(".data"))); #define NUM_PORTS (sizeof(port)/sizeof(port[0])) -DECLARE_GLOBAL_DATA_PTR; #endif static int pl01x_putc(struct pl01x_regs *regs, char c) @@ -351,9 +353,35 @@ static const struct dm_serial_ops pl01x_serial_ops = { .setbrg = pl01x_serial_setbrg, }; +#ifdef CONFIG_OF_CONTROL +static const struct udevice_id pl01x_serial_id[] ={ + {.compatible = "arm,pl011", .data = TYPE_PL011}, + {.compatible = "arm,pl010", .data = TYPE_PL010}, + {} +}; + +static int pl01x_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct pl01x_serial_platdata *plat = dev_get_platdata(dev); + fdt_addr_t addr; + + addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->base = addr; + plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1); + plat->type = dev_get_driver_data(dev); + return 0; +} +#endif + U_BOOT_DRIVER(serial_pl01x) = { .name = "serial_pl01x", .id = UCLASS_SERIAL, + .of_match = of_match_ptr(pl01x_serial_id), + .ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata), + .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata), .probe = pl01x_serial_probe, .ops = &pl01x_serial_ops, .flags = DM_FLAG_PRE_RELOC, diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 3c80096..1b22c69 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -10,11 +10,34 @@ #include <serial.h> #include <asm/arch/stm32.h> +/* + * Set up the usart port + */ +#if (CONFIG_STM32_USART >= 1) && (CONFIG_STM32_USART <= 6) +#define USART_PORT (CONFIG_STM32_USART - 1) +#else +#define USART_PORT 0 +#endif +/* + * Set up the usart base address + * + * --STM32_USARTD_BASE means default setting + */ #define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000) -#define RCC_APB2ENR_USART1EN (1 << 4) - -#define USART_BASE STM32_USART1_BASE -#define RCC_USART_ENABLE RCC_APB2ENR_USART1EN +#define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400) +#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800) +#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400) +#define STM32_USARTD_BASE STM32_USART1_BASE +/* + * RCC USART specific definitions + * + * --RCC_ENR_USARTDEN means default setting + */ +#define RCC_ENR_USART1EN (1 << 4) +#define RCC_ENR_USART2EN (1 << 17) +#define RCC_ENR_USART3EN (1 << 18) +#define RCC_ENR_USART6EN (1 << 5) +#define RCC_ENR_USARTDEN RCC_ENR_USART1EN struct stm32_serial { u32 sr; @@ -39,6 +62,24 @@ struct stm32_serial { DECLARE_GLOBAL_DATA_PTR; +static const unsigned long usart_base[] = { + STM32_USART1_BASE, + STM32_USART2_BASE, + STM32_USART3_BASE, + STM32_USARTD_BASE, + STM32_USARTD_BASE, + STM32_USART6_BASE +}; + +static const unsigned long rcc_enr_en[] = { + RCC_ENR_USART1EN, + RCC_ENR_USART2EN, + RCC_ENR_USART3EN, + RCC_ENR_USARTDEN, + RCC_ENR_USARTDEN, + RCC_ENR_USART6EN +}; + static void stm32_serial_setbrg(void) { serial_init(); @@ -46,14 +87,17 @@ static void stm32_serial_setbrg(void) static int stm32_serial_init(void) { - struct stm32_serial *usart = (struct stm32_serial *)USART_BASE; + struct stm32_serial *usart = + (struct stm32_serial *)usart_base[USART_PORT]; u32 clock, int_div, frac_div, tmp; - if ((USART_BASE & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE) { - setbits_le32(&STM32_RCC->apb1enr, RCC_USART_ENABLE); + if ((usart_base[USART_PORT] & STM32_BUS_MASK) == + STM32_APB1PERIPH_BASE) { + setbits_le32(&STM32_RCC->apb1enr, rcc_enr_en[USART_PORT]); clock = clock_get(CLOCK_APB1); - } else if ((USART_BASE & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE) { - setbits_le32(&STM32_RCC->apb2enr, RCC_USART_ENABLE); + } else if ((usart_base[USART_PORT] & STM32_BUS_MASK) == + STM32_APB2PERIPH_BASE) { + setbits_le32(&STM32_RCC->apb2enr, rcc_enr_en[USART_PORT]); clock = clock_get(CLOCK_APB2); } else { return -1; @@ -72,7 +116,8 @@ static int stm32_serial_init(void) static int stm32_serial_getc(void) { - struct stm32_serial *usart = (struct stm32_serial *)USART_BASE; + struct stm32_serial *usart = + (struct stm32_serial *)usart_base[USART_PORT]; while ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0) ; return readl(&usart->dr); @@ -80,7 +125,9 @@ static int stm32_serial_getc(void) static void stm32_serial_putc(const char c) { - struct stm32_serial *usart = (struct stm32_serial *)USART_BASE; + struct stm32_serial *usart = + (struct stm32_serial *)usart_base[USART_PORT]; + while ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0) ; writel(c, &usart->dr); @@ -88,7 +135,8 @@ static void stm32_serial_putc(const char c) static int stm32_serial_tstc(void) { - struct stm32_serial *usart = (struct stm32_serial *)USART_BASE; + struct stm32_serial *usart = + (struct stm32_serial *)usart_base[USART_PORT]; u8 ret; ret = readl(&usart->sr) & USART_SR_FLAG_RXNE; diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 83fe8e0..737ae64 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -63,9 +63,12 @@ int spi_claim_bus(struct spi_slave *slave) } if (!speed) speed = 100000; - ret = spi_set_speed_mode(bus, speed, slave->mode); - if (ret) - return ret; + if (speed != slave->speed) { + ret = spi_set_speed_mode(bus, speed, slave->mode); + if (ret) + return ret; + slave->speed = speed; + } return ops->claim_bus ? ops->claim_bus(dev) : 0; } diff --git a/drivers/tpm/tpm.c b/drivers/tpm/tpm.c index 31761ec..a650892 100644 --- a/drivers/tpm/tpm.c +++ b/drivers/tpm/tpm.c @@ -34,6 +34,7 @@ #include <config.h> #include <common.h> +#include <dm.h> #include <linux/compiler.h> #include <fdtdec.h> #include <i2c.h> @@ -48,10 +49,14 @@ DECLARE_GLOBAL_DATA_PTR; /* TPM configuration */ struct tpm { +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#else int i2c_bus; int slave_addr; - char inited; int old_bus; +#endif + char inited; } tpm; /* Global structure for tpm chip data */ @@ -372,7 +377,7 @@ static unsigned long tpm_calc_ordinal_duration(struct tpm_chip *chip, static ssize_t tpm_transmit(const unsigned char *buf, size_t bufsiz) { - ssize_t rc; + int rc; u32 count, ordinal; unsigned long start, stop; @@ -391,9 +396,11 @@ static ssize_t tpm_transmit(const unsigned char *buf, size_t bufsiz) return -E2BIG; } + debug("Calling send\n"); rc = chip->vendor.send(chip, (u8 *)buf, count); + debug(" ... done calling send\n"); if (rc < 0) { - error("tpm_transmit: tpm_send: error %zd\n", rc); + error("tpm_transmit: tpm_send: error %d\n", rc); goto out; } @@ -403,7 +410,7 @@ static ssize_t tpm_transmit(const unsigned char *buf, size_t bufsiz) start = get_timer(0); stop = tpm_calc_ordinal_duration(chip, ordinal); do { - debug("waiting for status...\n"); + debug("waiting for status... %ld %ld\n", start, stop); u8 status = chip->vendor.status(chip); if ((status & chip->vendor.req_complete_mask) == chip->vendor.req_complete_val) { @@ -428,15 +435,30 @@ out_recv: debug("out_recv: reading response...\n"); rc = chip->vendor.recv(chip, (u8 *)buf, TPM_BUFSIZE); if (rc < 0) - error("tpm_transmit: tpm_recv: error %zd\n", rc); + error("tpm_transmit: tpm_recv: error %d\n", rc); out: return rc; } +#ifdef CONFIG_DM_I2C +static int tpm_open_dev(struct udevice *dev) +{ + int rc; + + debug("%s: start\n", __func__); + if (g_chip.is_open) + return -EBUSY; + rc = tpm_vendor_init_dev(dev); + if (rc < 0) + g_chip.is_open = 0; + return rc; +} +#else static int tpm_open(uint32_t dev_addr) { int rc; + if (g_chip.is_open) return -EBUSY; rc = tpm_vendor_init(dev_addr); @@ -444,7 +466,7 @@ static int tpm_open(uint32_t dev_addr) g_chip.is_open = 0; return rc; } - +#endif static void tpm_close(void) { if (g_chip.is_open) { @@ -455,6 +477,7 @@ static void tpm_close(void) static int tpm_select(void) { +#ifndef CONFIG_DM_I2C int ret; tpm.old_bus = i2c_get_bus_num(); @@ -466,11 +489,13 @@ static int tpm_select(void) return -1; } } +#endif return 0; } static int tpm_deselect(void) { +#ifndef CONFIG_DM_I2C int ret; if (tpm.old_bus != i2c_get_bus_num()) { @@ -482,6 +507,7 @@ static int tpm_deselect(void) } } tpm.old_bus = -1; +#endif return 0; } @@ -493,10 +519,9 @@ static int tpm_deselect(void) */ static int tpm_decode_config(struct tpm *dev) { -#ifdef CONFIG_OF_CONTROL const void *blob = gd->fdt_blob; - int node, parent; - int i2c_bus; + int parent; + int node; node = fdtdec_next_compatible(blob, 0, COMPAT_INFINEON_SLB9635_TPM); if (node < 0) { @@ -512,15 +537,48 @@ static int tpm_decode_config(struct tpm *dev) debug("%s: Cannot find node parent\n", __func__); return -1; } +#ifdef CONFIG_DM_I2C + struct udevice *bus; + int chip_addr; + int ret; + + /* + * TODO(sjg@chromium.org): Remove this when driver model supports + * TPMs + */ + ret = uclass_get_device_by_of_offset(UCLASS_I2C, parent, &bus); + if (ret) { + debug("Cannot find bus for node '%s: ret=%d'\n", + fdt_get_name(blob, parent, NULL), ret); + return ret; + } + + chip_addr = fdtdec_get_int(blob, node, "reg", -1); + if (chip_addr == -1) { + debug("Cannot find reg property for node '%s: ret=%d'\n", + fdt_get_name(blob, node, NULL), ret); + return ret; + } + /* + * TODO(sjg@chromium.org): Older TPMs will need to use the older method + * in iic_tpm_read() so the offset length needs to be 0 here. + */ + ret = i2c_get_chip(bus, chip_addr, 1, &dev->dev); + if (ret) { + debug("Cannot find device for node '%s: ret=%d'\n", + fdt_get_name(blob, node, NULL), ret); + return ret; + } +#else + int i2c_bus; + i2c_bus = i2c_get_bus_num_fdt(parent); if (i2c_bus < 0) return -1; dev->i2c_bus = i2c_bus; dev->slave_addr = fdtdec_get_addr(blob, node, "reg"); -#else - dev->i2c_bus = CONFIG_TPM_TIS_I2C_BUS_NUMBER; - dev->slave_addr = CONFIG_TPM_TIS_I2C_SLAVE_ADDRESS; #endif + return 0; } @@ -547,6 +605,7 @@ int tis_init(void) if (tpm_select()) return -1; +#ifndef CONFIG_DM_I2C /* * Probe TPM twice; the first probing might fail because TPM is asleep, * and the probing can wake up TPM. @@ -556,8 +615,10 @@ int tis_init(void) tpm.slave_addr); return -1; } +#endif tpm_deselect(); + debug("%s: done\n", __func__); tpm.inited = 1; @@ -574,7 +635,11 @@ int tis_open(void) if (tpm_select()) return -1; +#ifdef CONFIG_DM_I2C + rc = tpm_open_dev(tpm.dev); +#else rc = tpm_open(tpm.slave_addr); +#endif tpm_deselect(); diff --git a/drivers/tpm/tpm_private.h b/drivers/tpm/tpm_private.h index 888a074..8894c98 100644 --- a/drivers/tpm/tpm_private.h +++ b/drivers/tpm/tpm_private.h @@ -131,6 +131,9 @@ struct tpm_chip *tpm_register_hardware(const struct tpm_vendor_specific *); int tpm_vendor_init(uint32_t dev_addr); +struct udevice; +int tpm_vendor_init_dev(struct udevice *dev); + void tpm_vendor_cleanup(struct tpm_chip *chip); diff --git a/drivers/tpm/tpm_tis_i2c.c b/drivers/tpm/tpm_tis_i2c.c index c1bbed4..ee4dfea 100644 --- a/drivers/tpm/tpm_tis_i2c.c +++ b/drivers/tpm/tpm_tis_i2c.c @@ -37,6 +37,7 @@ */ #include <common.h> +#include <dm.h> #include <fdtdec.h> #include <linux/compiler.h> #include <i2c.h> @@ -122,13 +123,19 @@ static const char * const chip_name[] = { /* Structure to store I2C TPM specific stuff */ struct tpm_dev { +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#else uint addr; +#endif u8 buf[TPM_DEV_BUFSIZE + sizeof(u8)]; /* Max buffer size + addr */ enum i2c_chip_type chip_type; }; static struct tpm_dev tpm_dev = { +#ifndef CONFIG_DM_I2C .addr = TPM_I2C_ADDR +#endif }; static struct tpm_dev tpm_dev; @@ -156,8 +163,12 @@ static int iic_tpm_read(u8 addr, u8 *buffer, size_t len) if ((tpm_dev.chip_type == SLB9635) || (tpm_dev.chip_type == UNKNOWN)) { /* slb9635 protocol should work in both cases */ for (count = 0; count < MAX_COUNT; count++) { +#ifdef CONFIG_DM_I2C + rc = dm_i2c_write(tpm_dev.dev, 0, (uchar *)&addrbuf, 1); +#else rc = i2c_write(tpm_dev.addr, 0, 0, (uchar *)&addrbuf, 1); +#endif if (rc == 0) break; /* Success, break to skip sleep */ udelay(SLEEP_DURATION); @@ -171,7 +182,11 @@ static int iic_tpm_read(u8 addr, u8 *buffer, size_t len) */ for (count = 0; count < MAX_COUNT; count++) { udelay(SLEEP_DURATION); +#ifdef CONFIG_DM_I2C + rc = dm_i2c_read(tpm_dev.dev, 0, buffer, len); +#else rc = i2c_read(tpm_dev.addr, 0, 0, buffer, len); +#endif if (rc == 0) break; /* success, break to skip sleep */ } @@ -184,7 +199,11 @@ static int iic_tpm_read(u8 addr, u8 *buffer, size_t len) * be safe on the safe side. */ for (count = 0; count < MAX_COUNT; count++) { +#ifdef CONFIG_DM_I2C + rc = dm_i2c_read(tpm_dev.dev, addr, buffer, len); +#else rc = i2c_read(tpm_dev.addr, addr, 1, buffer, len); +#endif if (rc == 0) break; /* break here to skip sleep */ udelay(SLEEP_DURATION); @@ -206,18 +225,26 @@ static int iic_tpm_write_generic(u8 addr, u8 *buffer, size_t len, int count; /* Prepare send buffer */ +#ifndef CONFIG_DM_I2C tpm_dev.buf[0] = addr; memcpy(&(tpm_dev.buf[1]), buffer, len); + buffer = tpm_dev.buf; + len++; +#endif for (count = 0; count < max_count; count++) { - rc = i2c_write(tpm_dev.addr, 0, 0, tpm_dev.buf, len + 1); +#ifdef CONFIG_DM_I2C + rc = dm_i2c_write(tpm_dev.dev, addr, buffer, len); +#else + rc = i2c_write(tpm_dev.addr, 0, 0, buffer, len); +#endif if (rc == 0) break; /* Success, break to skip sleep */ udelay(sleep_time); } /* take care of 'guard time' */ - udelay(SLEEP_DURATION); + udelay(sleep_time); if (rc) return -rc; @@ -292,11 +319,14 @@ static int request_locality(struct tpm_chip *chip, int loc) { unsigned long start, stop; u8 buf = TPM_ACCESS_REQUEST_USE; + int rc; if (check_locality(chip, loc) >= 0) return loc; /* We already have the locality */ - iic_tpm_write(TPM_ACCESS(loc), &buf, 1); + rc = iic_tpm_write(TPM_ACCESS(loc), &buf, 1); + if (rc) + return rc; /* Wait for burstcount */ start = get_timer(0); @@ -323,10 +353,15 @@ static u8 tpm_tis_i2c_status(struct tpm_chip *chip) static void tpm_tis_i2c_ready(struct tpm_chip *chip) { + int rc; + /* This causes the current command to be aborted */ u8 buf = TPM_STS_COMMAND_READY; - iic_tpm_write_long(TPM_STS(chip->vendor.locality), &buf, 1); + debug("%s\n", __func__); + rc = iic_tpm_write_long(TPM_STS(chip->vendor.locality), &buf, 1); + if (rc) + debug("%s: rc=%d\n", __func__, rc); } static ssize_t get_burstcount(struct tpm_chip *chip) @@ -422,6 +457,8 @@ static int tpm_tis_i2c_recv(struct tpm_chip *chip, u8 *buf, size_t count) expected = get_unaligned_be32(buf + TPM_RSP_SIZE_BYTE); if ((size_t)expected > count) { + error("Error size=%x, expected=%x, count=%x\n", size, expected, + count); size = -EIO; goto out; } @@ -456,11 +493,12 @@ out: static int tpm_tis_i2c_send(struct tpm_chip *chip, u8 *buf, size_t len) { int rc, status; - ssize_t burstcnt; + size_t burstcnt; size_t count = 0; int retry = 0; u8 sts = TPM_STS_GO; + debug("%s: len=%d\n", __func__, len); if (len > TPM_DEV_BUFSIZE) return -E2BIG; /* Command is too long for our tpm, sorry */ @@ -483,9 +521,10 @@ static int tpm_tis_i2c_send(struct tpm_chip *chip, u8 *buf, size_t len) if (burstcnt < 0) return burstcnt; - while (count < len - 1) { - if (burstcnt > len - 1 - count) - burstcnt = len - 1 - count; + while (count < len) { + udelay(300); + if (burstcnt > len - count) + burstcnt = len - count; #ifdef CONFIG_TPM_TIS_I2C_BURST_LIMITATION if (retry && burstcnt > CONFIG_TPM_TIS_I2C_BURST_LIMITATION) @@ -497,9 +536,15 @@ static int tpm_tis_i2c_send(struct tpm_chip *chip, u8 *buf, size_t len) if (rc == 0) count += burstcnt; else { - retry++; - wait_for_stat(chip, TPM_STS_VALID, - chip->vendor.timeout_c, &status); + debug("%s: error\n", __func__); + if (retry++ > 10) { + rc = -EIO; + goto out_err; + } + rc = wait_for_stat(chip, TPM_STS_VALID, + chip->vendor.timeout_c, &status); + if (rc) + goto out_err; if ((status & TPM_STS_DATA_EXPECT) == 0) { rc = -EIO; @@ -508,20 +553,14 @@ static int tpm_tis_i2c_send(struct tpm_chip *chip, u8 *buf, size_t len) } } - /* Write last byte */ - iic_tpm_write(TPM_DATA_FIFO(chip->vendor.locality), &(buf[count]), 1); - wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, &status); - if ((status & TPM_STS_DATA_EXPECT) != 0) { - rc = -EIO; - goto out_err; - } - /* Go and do it */ iic_tpm_write(TPM_STS(chip->vendor.locality), &sts, 1); + debug("done\n"); return len; out_err: + debug("%s: out_err\n", __func__); tpm_tis_i2c_ready(chip); /* * The TPM needs some time to clean up here, @@ -558,26 +597,17 @@ static enum i2c_chip_type tpm_vendor_chip_type(void) return UNKNOWN; } -/* Initialisation of i2c tpm */ -int tpm_vendor_init(uint32_t dev_addr) +static int tpm_vendor_init_common(void) { + struct tpm_chip *chip; u32 vendor; u32 expected_did_vid; - uint old_addr; - int rc = 0; - struct tpm_chip *chip; - - old_addr = tpm_dev.addr; - if (dev_addr != 0) - tpm_dev.addr = dev_addr; tpm_dev.chip_type = tpm_vendor_chip_type(); chip = tpm_register_hardware(&tpm_tis_i2c); - if (chip < 0) { - rc = -ENODEV; - goto out_err; - } + if (chip < 0) + return -ENODEV; /* Disable interrupts (not supported) */ chip->vendor.irq = 0; @@ -588,15 +618,13 @@ int tpm_vendor_init(uint32_t dev_addr) chip->vendor.timeout_c = TIS_SHORT_TIMEOUT; chip->vendor.timeout_d = TIS_SHORT_TIMEOUT; - if (request_locality(chip, 0) < 0) { - rc = -ENODEV; - goto out_err; - } + if (request_locality(chip, 0) < 0) + return -ENODEV; /* Read four bytes from DID_VID register */ if (iic_tpm_read(TPM_DID_VID(0), (uchar *)&vendor, 4) < 0) { - rc = -EIO; - goto out_release; + release_locality(chip, 0, 1); + return -EIO; } if (tpm_dev.chip_type == SLB9635) { @@ -609,8 +637,7 @@ int tpm_vendor_init(uint32_t dev_addr) if (tpm_dev.chip_type != UNKNOWN && vendor != expected_did_vid) { error("Vendor id did not match! ID was %08x\n", vendor); - rc = -ENODEV; - goto out_release; + return -ENODEV; } debug("1.2 TPM (chip type %s device-id 0x%X)\n", @@ -622,14 +649,33 @@ int tpm_vendor_init(uint32_t dev_addr) */ return 0; +} + +#ifdef CONFIG_DM_I2C +/* Initialisation of i2c tpm */ +int tpm_vendor_init_dev(struct udevice *dev) +{ + tpm_dev.dev = dev; + return tpm_vendor_init_common(); +} +#else +/* Initialisation of i2c tpm */ +int tpm_vendor_init(uint32_t dev_addr) +{ + uint old_addr; + int rc = 0; -out_release: - release_locality(chip, 0, 1); + old_addr = tpm_dev.addr; + if (dev_addr != 0) + tpm_dev.addr = dev_addr; + + rc = tpm_vendor_init_common(); + if (rc) + tpm_dev.addr = old_addr; -out_err: - tpm_dev.addr = old_addr; return rc; } +#endif void tpm_vendor_cleanup(struct tpm_chip *chip) { diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 3b57e56..4d35d3e 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o obj-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o +obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o # echi obj-$(CONFIG_USB_EHCI) += ehci-hcd.o diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index 86cf631..18e9251 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -25,14 +25,12 @@ /* Declare global data pointer */ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_DM_USB struct exynos_ehci_platdata { struct usb_platdata usb_plat; fdt_addr_t hcd_base; fdt_addr_t phy_base; struct gpio_desc vbus_gpio; }; -#endif /** * Contains pointers to register base addresses @@ -42,16 +40,8 @@ struct exynos_ehci { struct ehci_ctrl ctrl; struct exynos_usb_phy *usb; struct ehci_hccr *hcd; -#ifndef CONFIG_DM_USB - struct gpio_desc vbus_gpio; -#endif }; -#ifndef CONFIG_DM_USB -static struct exynos_ehci exynos; -#endif - -#ifdef CONFIG_DM_USB static int ehci_usb_ofdata_to_platdata(struct udevice *dev) { struct exynos_ehci_platdata *plat = dev_get_platdata(dev); @@ -91,55 +81,6 @@ static int ehci_usb_ofdata_to_platdata(struct udevice *dev) return 0; } -#else -static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos) -{ - fdt_addr_t addr; - unsigned int node; - int depth; - - node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_EHCI); - if (node <= 0) { - debug("EHCI: Can't get device node for ehci\n"); - return -ENODEV; - } - - /* - * Get the base address for EHCI controller from the device node - */ - addr = fdtdec_get_addr(blob, node, "reg"); - if (addr == FDT_ADDR_T_NONE) { - debug("Can't get the EHCI register address\n"); - return -ENXIO; - } - - exynos->hcd = (struct ehci_hccr *)addr; - - /* Vbus gpio */ - gpio_request_by_name_nodev(blob, node, "samsung,vbus-gpio", 0, - &exynos->vbus_gpio, GPIOD_IS_OUT); - - depth = 0; - node = fdtdec_next_compatible_subnode(blob, node, - COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth); - if (node <= 0) { - debug("EHCI: Can't get device node for usb-phy controller\n"); - return -ENODEV; - } - - /* - * Get the base address for usbphy from the device node - */ - exynos->usb = (struct exynos_usb_phy *)fdtdec_get_addr(blob, node, - "reg"); - if (exynos->usb == NULL) { - debug("Can't get the usbphy register address\n"); - return -ENXIO; - } - - return 0; -} -#endif static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb) { @@ -270,63 +211,6 @@ static void reset_usb_phy(struct exynos_usb_phy *usb) set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE); } -#ifndef CONFIG_DM_USB -/* - * EHCI-initialization - * Create the appropriate control structures to manage - * a new EHCI host controller. - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - struct exynos_ehci *ctx = &exynos; - -#ifdef CONFIG_OF_CONTROL - if (exynos_usb_parse_dt(gd->fdt_blob, ctx)) { - debug("Unable to parse device tree for ehci-exynos\n"); - return -ENODEV; - } -#else - ctx->usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy(); - ctx->hcd = (struct ehci_hccr *)samsung_get_base_usb_ehci(); -#endif - -#ifdef CONFIG_OF_CONTROL - /* setup the Vbus gpio here */ - if (dm_gpio_is_valid(&ctx->vbus_gpio)) - dm_gpio_set_value(&ctx->vbus_gpio, 1); -#endif - - setup_usb_phy(ctx->usb); - - board_usb_init(index, init); - - *hccr = ctx->hcd; - *hcor = (struct ehci_hcor *)((uint32_t) *hccr - + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - - debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n", - (uint32_t)*hccr, (uint32_t)*hcor, - (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - - return 0; -} - -/* - * Destroy the appropriate control structures corresponding - * the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - struct exynos_ehci *ctx = &exynos; - - reset_usb_phy(ctx->usb); - - return 0; -} -#endif - -#ifdef CONFIG_DM_USB static int ehci_usb_probe(struct udevice *dev) { struct exynos_ehci_platdata *plat = dev_get_platdata(dev); @@ -377,4 +261,3 @@ U_BOOT_DRIVER(usb_ehci) = { .platdata_auto_alloc_size = sizeof(struct exynos_ehci_platdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index bd9861d..1e5a6e2 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -125,14 +125,7 @@ static struct descriptor { static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev) { #ifdef CONFIG_DM_USB - struct udevice *dev; - - /* Find the USB controller */ - for (dev = udev->dev; - device_get_uclass_id(dev) != UCLASS_USB; - dev = dev->parent) - ; - return dev_get_priv(dev); + return dev_get_priv(usb_get_bus(udev->dev)); #else return udev->controller; #endif @@ -310,23 +303,33 @@ static void ehci_update_endpt2_dev_n_port(struct usb_device *udev, * in the tree before that one! */ #ifdef CONFIG_DM_USB + /* + * When called from usb-uclass.c: usb_scan_device() udev->dev points + * to the parent udevice, not the actual udevice belonging to the + * udev as the device is not instantiated yet. So when searching + * for the first usb-2 parent start with udev->dev not + * udev->dev->parent . + */ struct udevice *parent; + struct usb_device *uparent; + + ttdev = udev; + parent = udev->dev; + uparent = dev_get_parentdata(parent); - for (ttdev = udev; ; ) { - struct udevice *dev = ttdev->dev; + while (uparent->speed != USB_SPEED_HIGH) { + struct udevice *dev = parent; - if (dev->parent && - device_get_uclass_id(dev->parent) == UCLASS_USB_HUB) - parent = dev->parent; - else - parent = NULL; - if (!parent) + if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) { + printf("ehci: Error cannot find high speed parent of usb-1 device\n"); return; - ttdev = dev_get_parentdata(parent); - if (!ttdev->speed != USB_SPEED_HIGH) - break; + } + + ttdev = dev_get_parentdata(dev); + parent = dev->parent; + uparent = dev_get_parentdata(parent); } - parent_devnum = ttdev->devnum; + parent_devnum = uparent->devnum; #else ttdev = udev; while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH) @@ -872,7 +875,7 @@ static int ehci_submit_root(struct usb_device *dev, unsigned long pipe, port - 1); reg |= EHCI_PS_PO; ehci_writel(status_reg, reg); - break; + return -ENXIO; } else { int ret; @@ -894,11 +897,22 @@ static int ehci_submit_root(struct usb_device *dev, unsigned long pipe, */ ret = handshake(status_reg, EHCI_PS_PR, 0, 2 * 1000); - if (!ret) - ctrl->portreset |= 1 << port; - else + if (!ret) { + reg = ehci_readl(status_reg); + if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) + == EHCI_PS_CS && !ehci_is_TDI()) { + debug("port %d full speed --> companion\n", port - 1); + reg &= ~EHCI_PS_CLEAR; + reg |= EHCI_PS_PO; + ehci_writel(status_reg, reg); + return -ENXIO; + } else { + ctrl->portreset |= 1 << port; + } + } else { printf("port(%d) reset error\n", port - 1); + } } break; case USB_PORT_FEAT_TEST: @@ -1249,9 +1263,9 @@ disable_periodic(struct ehci_ctrl *ctrl) return 0; } -struct int_queue * -create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, - int elementsize, void *buffer, int interval) +static struct int_queue *_ehci_create_int_queue(struct usb_device *dev, + unsigned long pipe, int queuesize, int elementsize, + void *buffer, int interval) { struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); struct int_queue *result = NULL; @@ -1407,7 +1421,8 @@ fail1: return NULL; } -void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) +static void *_ehci_poll_int_queue(struct usb_device *dev, + struct int_queue *queue) { struct QH *cur = queue->current; struct qTD *cur_td; @@ -1442,8 +1457,8 @@ void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) } /* Do not free buffers associated with QHs, they're owned by someone else */ -int -destroy_int_queue(struct usb_device *dev, struct int_queue *queue) +static int _ehci_destroy_int_queue(struct usb_device *dev, + struct int_queue *queue) { struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); int result = -1; @@ -1500,12 +1515,12 @@ static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe, debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", dev, pipe, buffer, length, interval); - queue = create_int_queue(dev, pipe, 1, length, buffer, interval); + queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval); if (!queue) return -1; timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); - while ((backbuffer = poll_int_queue(dev, queue)) == NULL) + while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL) if (get_timer(0) > timeout) { printf("Timeout poll on interrupt endpoint\n"); result = -ETIMEDOUT; @@ -1518,7 +1533,7 @@ static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe, return -EINVAL; } - ret = destroy_int_queue(dev, queue); + ret = _ehci_destroy_int_queue(dev, queue); if (ret < 0) return ret; @@ -1544,6 +1559,24 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, { return _ehci_submit_int_msg(dev, pipe, buffer, length, interval); } + +struct int_queue *create_int_queue(struct usb_device *dev, + unsigned long pipe, int queuesize, int elementsize, + void *buffer, int interval) +{ + return _ehci_create_int_queue(dev, pipe, queuesize, elementsize, + buffer, interval); +} + +void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) +{ + return _ehci_poll_int_queue(dev, queue); +} + +int destroy_int_queue(struct usb_device *dev, struct int_queue *queue) +{ + return _ehci_destroy_int_queue(dev, queue); +} #endif #ifdef CONFIG_DM_USB @@ -1572,16 +1605,42 @@ static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev, return _ehci_submit_int_msg(udev, pipe, buffer, length, interval); } +static struct int_queue *ehci_create_int_queue(struct udevice *dev, + struct usb_device *udev, unsigned long pipe, int queuesize, + int elementsize, void *buffer, int interval) +{ + debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); + return _ehci_create_int_queue(udev, pipe, queuesize, elementsize, + buffer, interval); +} + +static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev, + struct int_queue *queue) +{ + debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); + return _ehci_poll_int_queue(udev, queue); +} + +static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev, + struct int_queue *queue) +{ + debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); + return _ehci_destroy_int_queue(udev, queue); +} + int ehci_register(struct udevice *dev, struct ehci_hccr *hccr, struct ehci_hcor *hcor, const struct ehci_ops *ops, uint tweaks, enum usb_init_type init) { + struct usb_bus_priv *priv = dev_get_uclass_priv(dev); struct ehci_ctrl *ctrl = dev_get_priv(dev); int ret; debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__, dev->name, ctrl, hccr, hcor, init); + priv->desc_before_addr = true; + ehci_setup_ops(ctrl, ops); ctrl->hccr = hccr; ctrl->hcor = hcor; @@ -1617,6 +1676,9 @@ struct dm_usb_ops ehci_usb_ops = { .control = ehci_submit_control_msg, .bulk = ehci_submit_bulk_msg, .interrupt = ehci_submit_int_msg, + .create_int_queue = ehci_create_int_queue, + .poll_int_queue = ehci_poll_int_queue, + .destroy_int_queue = ehci_destroy_int_queue, }; #endif diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index 0edb643..34130f8 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -14,53 +14,88 @@ #include <asm/arch/clock.h> #include <asm/arch/usb_phy.h> #include <asm/io.h> +#include <dm.h> #include "ehci.h" -int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, - struct ehci_hcor **hcor) +struct ehci_sunxi_priv { + struct ehci_ctrl ehci; + int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */ + int phy_index; /* Index of the usb-phy attached to this hcd */ +}; + +static int ehci_usb_probe(struct udevice *dev) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - int ahb_gate_offset; + struct usb_platdata *plat = dev_get_platdata(dev); + struct ehci_sunxi_priv *priv = dev_get_priv(dev); + struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev); + struct ehci_hcor *hcor; + + /* + * This should go away once we've moved to the driver model for + * clocks resp. phys. + */ + if (hccr == (void *)SUNXI_USB1_BASE) { + priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; + priv->phy_index = 1; + } else { + priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1; + priv->phy_index = 2; + } - ahb_gate_offset = index ? AHB_GATE_OFFSET_USB_EHCI1 : - AHB_GATE_OFFSET_USB_EHCI0; - setbits_le32(&ccm->ahb_gate0, 1 << ahb_gate_offset); + setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask); #ifdef CONFIG_SUNXI_GEN_SUN6I - setbits_le32(&ccm->ahb_reset0_cfg, 1 << ahb_gate_offset); + setbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask); #endif - sunxi_usb_phy_init(index + 1); - sunxi_usb_phy_power_on(index + 1); - - if (index == 0) - *hccr = (void *)SUNXI_USB1_BASE; - else - *hccr = (void *)SUNXI_USB2_BASE; - - *hcor = (struct ehci_hcor *)((uint32_t) *hccr - + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + sunxi_usb_phy_init(priv->phy_index); + sunxi_usb_phy_power_on(priv->phy_index); - debug("sunxi-ehci: init hccr %x and hcor %x hc_length %d\n", - (uint32_t)*hccr, (uint32_t)*hcor, - (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + hcor = (struct ehci_hcor *)((uint32_t)hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); - return 0; + return ehci_register(dev, hccr, hcor, NULL, 0, plat->init_type); } -int ehci_hcd_stop(int index) +static int ehci_usb_remove(struct udevice *dev) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - int ahb_gate_offset; + struct ehci_sunxi_priv *priv = dev_get_priv(dev); + int ret; + + ret = ehci_deregister(dev); + if (ret) + return ret; - sunxi_usb_phy_power_off(index + 1); - sunxi_usb_phy_exit(index + 1); + sunxi_usb_phy_power_off(priv->phy_index); + sunxi_usb_phy_exit(priv->phy_index); - ahb_gate_offset = index ? AHB_GATE_OFFSET_USB_EHCI1 : - AHB_GATE_OFFSET_USB_EHCI0; #ifdef CONFIG_SUNXI_GEN_SUN6I - clrbits_le32(&ccm->ahb_reset0_cfg, 1 << ahb_gate_offset); + clrbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask); #endif - clrbits_le32(&ccm->ahb_gate0, 1 << ahb_gate_offset); + clrbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask); return 0; } + +static const struct udevice_id ehci_usb_ids[] = { + { .compatible = "allwinner,sun4i-a10-ehci", }, + { .compatible = "allwinner,sun5i-a13-ehci", }, + { .compatible = "allwinner,sun6i-a31-ehci", }, + { .compatible = "allwinner,sun7i-a20-ehci", }, + { .compatible = "allwinner,sun8i-a23-ehci", }, + { .compatible = "allwinner,sun9i-a80-ehci", }, + { } +}; + +U_BOOT_DRIVER(usb_ehci) = { + .name = "ehci_sunxi", + .id = UCLASS_USB, + .of_match = ehci_usb_ids, + .probe = ehci_usb_probe, + .remove = ehci_usb_remove, + .ops = &ehci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct ehci_sunxi_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 97a7ede..691ed1c 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -30,6 +30,8 @@ #include <common.h> #include <asm/byteorder.h> +#include <dm.h> +#include <errno.h> #if defined(CONFIG_PCI_OHCI) # include <pci.h> @@ -103,16 +105,104 @@ static struct pci_device_id ehci_pci_ids[] = { # define m32_swap(x) cpu_to_le32(x) #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */ +#ifdef CONFIG_DM_USB +/* + * We really should do proper cache flushing everywhere, but for now we only + * do it for new (driver-model) usb code to avoid regressions. + */ +#define flush_dcache_buffer(addr, size) \ + flush_dcache_range((unsigned long)(addr), \ + ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN)) +#define invalidate_dcache_buffer(addr, size) \ + invalidate_dcache_range((unsigned long)(addr), \ + ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN)) +#else +#define flush_dcache_buffer(addr, size) +#define invalidate_dcache_buffer(addr, size) +#endif + +/* Do not use sizeof(ed / td) as our ed / td structs contain extra members */ +#define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16) +#define flush_dcache_td(addr) flush_dcache_buffer(addr, 16) +#define flush_dcache_iso_td(addr) flush_dcache_buffer(addr, 32) +#define flush_dcache_hcca(addr) flush_dcache_buffer(addr, 256) +#define invalidate_dcache_ed(addr) invalidate_dcache_buffer(addr, 16) +#define invalidate_dcache_td(addr) invalidate_dcache_buffer(addr, 16) +#define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32) +#define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256) + +#ifdef CONFIG_DM_USB +/* + * The various ohci_mdelay(1) calls in the code seem unnecessary. We keep + * them around when building for older boards not yet converted to the dm + * just in case (to avoid regressions), for dm this turns them into nops. + */ +#define ohci_mdelay(x) +#else +#define ohci_mdelay(x) mdelay(x) +#endif + +#ifndef CONFIG_DM_USB /* global ohci_t */ static ohci_t gohci; /* this must be aligned to a 256 byte boundary */ struct ohci_hcca ghcca[1]; -/* a pointer to the aligned storage */ -struct ohci_hcca *phcca; -/* this allocates EDs for all possible endpoints */ -struct ohci_device ohci_dev; -/* device which was disconnected */ -struct usb_device *devgone; +#endif + +/* mapping of the OHCI CC status to error codes */ +static int cc_to_error[16] = { + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 +}; + +static const char *cc_to_string[16] = { + "No Error", + "CRC: Last data packet from endpoint contained a CRC error.", + "BITSTUFFING: Last data packet from endpoint contained a bit " \ + "stuffing violation", + "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \ + "that did not match the expected value.", + "STALL: TD was moved to the Done Queue because the endpoint returned" \ + " a STALL PID", + "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \ + "not provide a handshake (OUT)", + "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\ + "(IN) or handshake (OUT)", + "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \ + "value is not defined.", + "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \ + "either the size of the maximum data packet allowed\n" \ + "from the endpoint (found in MaximumPacketSize field\n" \ + "of ED) or the remaining buffer size.", + "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \ + "and that amount was not sufficient to fill the\n" \ + "specified buffer", + "reserved1", + "reserved2", + "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \ + "than it could be written to system memory", + "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \ + "system memory fast enough to keep up with data USB " \ + "data rate.", + "NOT ACCESSED: This code is set by software before the TD is placed" \ + "on a list to be processed by the HC.(1)", + "NOT ACCESSED: This code is set by software before the TD is placed" \ + "on a list to be processed by the HC.(2)", +}; static inline u32 roothub_a(struct ohci *hc) { return ohci_readl(&hc->regs->roothub.a); } @@ -124,11 +214,42 @@ static inline u32 roothub_portstatus(struct ohci *hc, int i) { return ohci_readl(&hc->regs->roothub.portstatus[i]); } /* forward declaration */ -static int hc_interrupt(void); -static void td_submit_job(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, +static int hc_interrupt(ohci_t *ohci); +static void td_submit_job(ohci_t *ohci, struct usb_device *dev, + unsigned long pipe, void *buffer, int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval); +static int ep_link(ohci_t * ohci, ed_t * ed); +static int ep_unlink(ohci_t * ohci, ed_t * ed); +static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, + unsigned long pipe, int interval, int load); + +/*-------------------------------------------------------------------------*/ + +/* TDs ... */ +static struct td *td_alloc(ohci_dev_t *ohci_dev, struct usb_device *usb_dev) +{ + int i; + struct td *td; + + td = NULL; + for (i = 0; i < NUM_TD; i++) + { + if (ohci_dev->tds[i].usb_dev == NULL) + { + td = &ohci_dev->tds[i]; + td->usb_dev = usb_dev; + break; + } + } + + return td; +} + +static inline void ed_free(struct ed *ed) +{ + ed->usb_dev = NULL; +} /*-------------------------------------------------------------------------* * URB support functions @@ -158,18 +279,18 @@ static void urb_free_priv(urb_priv_t *urb) /*-------------------------------------------------------------------------*/ #ifdef DEBUG -static int sohci_get_current_frame_number(struct usb_device *dev); +static int sohci_get_current_frame_number(ohci_t *ohci); /* debug| print the main components of an URB * small: 0) header + data packets 1) just header */ -static void pkt_print(urb_priv_t *purb, struct usb_device *dev, +static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, struct devrequest *setup, char *str, int small) { dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx", str, - sohci_get_current_frame_number(dev), + sohci_get_current_frame_number(ohci), usb_pipedevice(pipe), usb_pipeendpoint(pipe), usb_pipeout(pipe)? 'O': 'I', @@ -213,9 +334,11 @@ void ep_print_int_eds(ohci_t *ohci, char *str) ed_p = &(ohci->hcca->int_table [i]); if (*ed_p == 0) continue; + invalidate_dcache_ed(ed_p); printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); while (*ed_p != 0 && j--) { ed_t *ed = (ed_t *)m32_swap(ed_p); + invalidate_dcache_ed(ed); printf(" ed: %4x;", ed->hwINFO); ed_p = &ed->hwNextED; } @@ -246,6 +369,7 @@ static void maybe_print_eds(char *label, __u32 value) if (value) { dbg("%s %08x", label, value); + invalidate_dcache_ed(edp); dbg("%08x", edp->hwINFO); dbg("%08x", edp->hwTailP); dbg("%08x", edp->hwHeadP); @@ -380,6 +504,7 @@ static void ohci_dump(ohci_t *controller, int verbose) ohci_dump_status(controller); if (verbose) ep_print_int_eds(controller, "hcca"); + invalidate_dcache_hcca(controller->hcca); dbg("hcca frame #%04x", controller->hcca->frame_no); ohci_dump_roothub(controller, 1); } @@ -391,9 +516,9 @@ static void ohci_dump(ohci_t *controller, int verbose) /* get a transfer request */ -int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup) +int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb, + struct devrequest *setup) { - ohci_t *ohci; ed_t *ed; urb_priv_t *purb_priv = urb; int i, size = 0; @@ -403,8 +528,6 @@ int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup) int transfer_len = urb->transfer_buffer_length; int interval = urb->interval; - ohci = &gohci; - /* when controller's hung, permit only roothub cleanup attempts * such as powering down ports */ if (ohci->disabled) { @@ -417,7 +540,7 @@ int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup) urb->finished = 0; /* every endpoint has a ed, locate and fill it */ - ed = ep_add_ed(dev, pipe, interval, 1); + ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1); if (!ed) { err("sohci_submit_job: ENOMEM"); return -1; @@ -453,7 +576,7 @@ int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup) /* allocate the TDs */ /* note that td[0] was allocated in ep_add_ed */ for (i = 0; i < size; i++) { - purb_priv->td[i] = td_alloc(dev); + purb_priv->td[i] = td_alloc(ohci_dev, dev); if (!purb_priv->td[i]) { purb_priv->length = i; urb_free_priv(purb_priv); @@ -473,55 +596,19 @@ int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup) ep_link(ohci, ed); /* fill the TDs and link it to the ed */ - td_submit_job(dev, pipe, buffer, transfer_len, + td_submit_job(ohci, dev, pipe, buffer, transfer_len, setup, purb_priv, interval); return 0; } -static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb) -{ - struct ohci_regs *regs = hc->regs; - - switch (usb_pipetype(urb->pipe)) { - case PIPE_INTERRUPT: - /* implicitly requeued */ - if (urb->dev->irq_handle && - (urb->dev->irq_act_len = urb->actual_length)) { - ohci_writel(OHCI_INTR_WDH, ®s->intrenable); - ohci_readl(®s->intrenable); /* PCI posting flush */ - urb->dev->irq_handle(urb->dev); - ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); - ohci_readl(®s->intrdisable); /* PCI posting flush */ - } - urb->actual_length = 0; - td_submit_job( - urb->dev, - urb->pipe, - urb->transfer_buffer, - urb->transfer_buffer_length, - NULL, - urb, - urb->interval); - break; - case PIPE_CONTROL: - case PIPE_BULK: - break; - default: - return 0; - } - return 1; -} - /*-------------------------------------------------------------------------*/ #ifdef DEBUG /* tell us the current USB frame number */ - -static int sohci_get_current_frame_number(struct usb_device *usb_dev) +static int sohci_get_current_frame_number(ohci_t *ohci) { - ohci_t *ohci = &gohci; - + invalidate_dcache_hcca(ohci->hcca); return m16_swap(ohci->hcca->frame_no); } #endif @@ -600,6 +687,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi) switch (ed->type) { case PIPE_CONTROL: ed->hwNextED = 0; + flush_dcache_ed(ed); if (ohci->ed_controltail == NULL) ohci_writel(ed, &ohci->regs->ed_controlhead); else @@ -617,6 +705,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi) case PIPE_BULK: ed->hwNextED = 0; + flush_dcache_ed(ed); if (ohci->ed_bulktail == NULL) ohci_writel(ed, &ohci->regs->ed_bulkhead); else @@ -649,7 +738,9 @@ static int ep_link(ohci_t *ohci, ed_t *edi) inter = ep_rev(6, ((ed_t *)ed_p)->int_interval); ed->hwNextED = *ed_p; + flush_dcache_ed(ed); *ed_p = m32_swap((unsigned long)ed); + flush_dcache_hcca(ohci->hcca); } break; } @@ -662,6 +753,8 @@ static int ep_link(ohci_t *ohci, ed_t *edi) static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, unsigned index, unsigned period) { + __maybe_unused unsigned long aligned_ed_p; + for (; index < NUM_INTS; index += period) { __u32 *ed_p = &ohci->hcca->int_table [index]; @@ -670,6 +763,12 @@ static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, if (((struct ed *) m32_swap((unsigned long)ed_p)) == ed) { *ed_p = ed->hwNextED; +#ifdef CONFIG_DM_USB + aligned_ed_p = (unsigned long)ed_p; + aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1); + flush_dcache_range(aligned_ed_p, + aligned_ed_p + ARCH_DMA_MINALIGN); +#endif break; } ed_p = &(((struct ed *) @@ -689,6 +788,7 @@ static int ep_unlink(ohci_t *ohci, ed_t *edi) int i; ed->hwINFO |= m32_swap(OHCI_ED_SKIP); + flush_dcache_ed(ed); switch (ed->type) { case PIPE_CONTROL: @@ -702,6 +802,7 @@ static int ep_unlink(ohci_t *ohci, ed_t *edi) &ohci->regs->ed_controlhead); } else { ed->ed_prev->hwNextED = ed->hwNextED; + flush_dcache_ed(ed->ed_prev); } if (ohci->ed_controltail == ed) { ohci->ed_controltail = ed->ed_prev; @@ -722,6 +823,7 @@ static int ep_unlink(ohci_t *ohci, ed_t *edi) &ohci->regs->ed_bulkhead); } else { ed->ed_prev->hwNextED = ed->hwNextED; + flush_dcache_ed(ed->ed_prev); } if (ohci->ed_bulktail == ed) { ohci->ed_bulktail = ed->ed_prev; @@ -751,14 +853,14 @@ static int ep_unlink(ohci_t *ohci, ed_t *edi) * info fields are setted anyway even though most of them should not * change */ -static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe, - int interval, int load) +static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, + unsigned long pipe, int interval, int load) { td_t *td; ed_t *ed_ret; volatile ed_t *ed; - ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) | + ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) | (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { @@ -769,12 +871,12 @@ static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe, if (ed->state == ED_NEW) { /* dummy td; end of td list for ed */ - td = td_alloc(usb_dev); + td = td_alloc(ohci_dev, usb_dev); ed->hwTailP = m32_swap((unsigned long)td); ed->hwHeadP = ed->hwTailP; ed->state = ED_UNLINK; ed->type = usb_pipetype(pipe); - ohci_dev.ed_cnt++; + ohci_dev->ed_cnt++; } ed->hwINFO = m32_swap(usb_pipedevice(pipe) @@ -790,6 +892,8 @@ static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe, ed->int_load = load; } + flush_dcache_ed(ed); + return ed_ret; } @@ -815,6 +919,7 @@ static void td_fill(ohci_t *ohci, unsigned int info, /* use this td as the next dummy */ td_pt = urb_priv->td [index]; td_pt->hwNextTD = 0; + flush_dcache_td(td_pt); /* fill the old dummy TD */ td = urb_priv->td [index] = @@ -842,27 +947,30 @@ static void td_fill(ohci_t *ohci, unsigned int info, td->hwBE = 0; td->hwNextTD = m32_swap((unsigned long)td_pt); + flush_dcache_td(td); /* append to queue */ td->ed->hwTailP = td->hwNextTD; + flush_dcache_ed(td->ed); } /*-------------------------------------------------------------------------*/ /* prepare all TDs of a transfer */ -static void td_submit_job(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, +static void td_submit_job(ohci_t *ohci, struct usb_device *dev, + unsigned long pipe, void *buffer, int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) { - ohci_t *ohci = &gohci; int data_len = transfer_len; void *data; int cnt = 0; __u32 info = 0; unsigned int toggle = 0; + flush_dcache_buffer(buffer, data_len); + /* OHCI handles the DATA-toggles itself, we just use the USB-toggle * bits for reseting */ if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { @@ -902,6 +1010,7 @@ static void td_submit_job(struct usb_device *dev, unsigned long pipe, case PIPE_CONTROL: /* Setup phase */ info = TD_CC | TD_DP_SETUP | TD_T_DATA0; + flush_dcache_buffer(setup, 8); td_fill(ohci, info, setup, 8, dev, cnt++, urb); /* Optional Data phase */ @@ -914,7 +1023,7 @@ static void td_submit_job(struct usb_device *dev, unsigned long pipe, } /* Status phase */ - info = usb_pipeout(pipe)? + info = (usb_pipeout(pipe) || data_len == 0) ? TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; td_fill(ohci, info, data, 0, dev, cnt++, urb); @@ -973,6 +1082,7 @@ static void check_status(td_t *td_list) if (cc) { err(" USB-error: %s (%x)", cc_to_string[cc], cc); + invalidate_dcache_ed(td_list->ed); if (*phwHeadP & m32_swap(0x1)) { if (lurb_priv && ((td_list->index + 1) < urb_len)) { @@ -985,9 +1095,11 @@ static void check_status(td_t *td_list) td_list->index - 1; } else *phwHeadP &= m32_swap(0xfffffff2); + flush_dcache_ed(td_list->ed); } #ifdef CONFIG_MPC5200 td_list->hwNextTD = 0; + flush_dcache_td(td_list); #endif } } @@ -1000,11 +1112,14 @@ static td_t *dl_reverse_done_list(ohci_t *ohci) td_t *td_rev = NULL; td_t *td_list = NULL; + invalidate_dcache_hcca(ohci->hcca); td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; ohci->hcca->done_head = 0; + flush_dcache_hcca(ohci->hcca); while (td_list_hc) { td_list = (td_t *)td_list_hc; + invalidate_dcache_td(td_list); check_status(td_list); td_list->next_dl_td = td_rev; td_rev = td_list; @@ -1019,7 +1134,7 @@ static td_t *dl_reverse_done_list(ohci_t *ohci) static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status) { if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) - urb->finished = sohci_return_job(ohci, urb); + urb->finished = 1; else dbg("finish_urb: strange.., ED state %x, \n", status); } @@ -1039,6 +1154,7 @@ static int takeback_td(ohci_t *ohci, td_t *td_list) urb_priv_t *lurb_priv; __u32 tdINFO, edHeadP, edTailP; + invalidate_dcache_td(td_list); tdINFO = m32_swap(td_list->hwINFO); ed = td_list->ed; @@ -1064,6 +1180,7 @@ static int takeback_td(ohci_t *ohci, td_t *td_list) lurb_priv->td_cnt, lurb_priv->length); if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) { + invalidate_dcache_ed(ed); edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; edTailP = m32_swap(ed->hwTailP); @@ -1100,16 +1217,16 @@ static int dl_done_list(ohci_t *ohci) #define OK(x) len = (x); break #ifdef DEBUG #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \ - &gohci.regs->roothub.status); } + &ohci->regs->roothub.status); } #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \ - (x)); ohci_writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); } + (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); } #else -#define WR_RH_STAT(x) ohci_writel((x), &gohci.regs->roothub.status) +#define WR_RH_STAT(x) ohci_writel((x), &ohci->regs->roothub.status) #define WR_RH_PORTSTAT(x) ohci_writel((x), \ - &gohci.regs->roothub.portstatus[wIndex-1]) + &ohci->regs->roothub.portstatus[wIndex-1]) #endif -#define RD_RH_STAT roothub_status(&gohci) -#define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1) +#define RD_RH_STAT roothub_status(ohci) +#define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1) /* request to virtual root hub */ @@ -1137,8 +1254,9 @@ int rh_check_port_status(ohci_t *controller) return res; } -static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, struct devrequest *cmd) +static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev, + unsigned long pipe, void *buffer, int transfer_len, + struct devrequest *cmd) { void *data = buffer; int leni = transfer_len; @@ -1151,10 +1269,10 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32)); #ifdef DEBUG -pkt_print(NULL, dev, pipe, buffer, transfer_len, +pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); #else - mdelay(1); + ohci_mdelay(1); #endif if (usb_pipeint(pipe)) { info("Root-Hub submit IRQ: NOT implemented"); @@ -1235,7 +1353,6 @@ pkt_print(NULL, dev, pipe, buffer, transfer_len, OK(0); case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_PPS); - mdelay(100); OK(0); case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ if (RD_RH_PORTSTAT & RH_PS_CCS) @@ -1245,7 +1362,7 @@ pkt_print(NULL, dev, pipe, buffer, transfer_len, break; case RH_SET_ADDRESS: - gohci.rh.devnum = wValue; + ohci->rh.devnum = wValue; OK(0); case RH_GET_DESCRIPTOR: @@ -1290,7 +1407,7 @@ pkt_print(NULL, dev, pipe, buffer, transfer_len, case RH_GET_DESCRIPTOR | RH_CLASS: { - __u32 temp = roothub_a(&gohci); + __u32 temp = roothub_a(ohci); databuf[0] = 9; /* min length; */ databuf[1] = 0x29; @@ -1309,7 +1426,7 @@ pkt_print(NULL, dev, pipe, buffer, transfer_len, databuf[4] = 0; databuf[5] = (temp & RH_A_POTPGT) >> 24; databuf[6] = 0; - temp = roothub_b(&gohci); + temp = roothub_b(ohci); databuf[7] = temp & RH_B_DR; if (databuf[2] < 7) { databuf[8] = 0xff; @@ -1338,9 +1455,9 @@ pkt_print(NULL, dev, pipe, buffer, transfer_len, } #ifdef DEBUG - ohci_dump_roothub(&gohci, 1); + ohci_dump_roothub(ohci, 1); #else - mdelay(1); + ohci_mdelay(1); #endif len = min_t(int, len, leni); @@ -1350,10 +1467,10 @@ pkt_print(NULL, dev, pipe, buffer, transfer_len, dev->status = stat; #ifdef DEBUG - pkt_print(NULL, dev, pipe, buffer, + pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); #else - mdelay(1); + ohci_mdelay(1); #endif return stat; @@ -1361,18 +1478,43 @@ pkt_print(NULL, dev, pipe, buffer, transfer_len, /*-------------------------------------------------------------------------*/ +static ohci_dev_t *ohci_get_ohci_dev(ohci_t *ohci, int devnum, int intr) +{ + int i; + + if (!intr) + return &ohci->ohci_dev; + + /* First see if we already have an ohci_dev for this dev. */ + for (i = 0; i < NUM_INT_DEVS; i++) { + if (ohci->int_dev[i].devnum == devnum) + return &ohci->int_dev[i]; + } + + /* If not then find a free one. */ + for (i = 0; i < NUM_INT_DEVS; i++) { + if (ohci->int_dev[i].devnum == -1) { + ohci->int_dev[i].devnum = devnum; + return &ohci->int_dev[i]; + } + } + + printf("ohci: Error out of ohci_devs for interrupt endpoints\n"); + return NULL; +} + /* common code for handling submit messages - used for all but root hub */ /* accesses. */ -int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) +static urb_priv_t *ohci_alloc_urb(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, int interval) { - int stat = 0; - int maxsize = usb_maxpacket(dev, pipe); - int timeout; urb_priv_t *urb; - urb = malloc(sizeof(urb_priv_t)); - memset(urb, 0, sizeof(urb_priv_t)); + urb = calloc(1, sizeof(urb_priv_t)); + if (!urb) { + printf("ohci: Error out of memory allocating urb\n"); + return NULL; + } urb->dev = dev; urb->pipe = pipe; @@ -1380,18 +1522,29 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, urb->transfer_buffer_length = transfer_len; urb->interval = interval; - /* device pulled? Shortcut the action. */ - if (devgone == dev) { - dev->status = USB_ST_CRC_ERR; - return 0; - } + return urb; +} + +static int submit_common_msg(ohci_t *ohci, struct usb_device *dev, + unsigned long pipe, void *buffer, int transfer_len, + struct devrequest *setup, int interval) +{ + int stat = 0; + int maxsize = usb_maxpacket(dev, pipe); + int timeout; + urb_priv_t *urb; + ohci_dev_t *ohci_dev; + + urb = ohci_alloc_urb(dev, pipe, buffer, transfer_len, interval); + if (!urb) + return -ENOMEM; #ifdef DEBUG urb->actual_length = 0; - pkt_print(urb, dev, pipe, buffer, transfer_len, + pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); #else - mdelay(1); + ohci_mdelay(1); #endif if (!maxsize) { err("submit_common_message: pipesize for pipe %lx is zero", @@ -1399,14 +1552,18 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, return -1; } - if (sohci_submit_job(urb, setup) < 0) { + ohci_dev = ohci_get_ohci_dev(ohci, dev->devnum, usb_pipeint(pipe)); + if (!ohci_dev) + return -ENOMEM; + + if (sohci_submit_job(ohci, ohci_dev, urb, setup) < 0) { err("sohci_submit_job failed"); return -1; } #if 0 mdelay(10); - /* ohci_dump_status(&gohci); */ + /* ohci_dump_status(ohci); */ #endif timeout = USB_TIMEOUT_MS(pipe); @@ -1414,7 +1571,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, /* wait for it to complete */ for (;;) { /* check whether the controller is done */ - stat = hc_interrupt(); + stat = hc_interrupt(ohci); if (stat < 0) { stat = USB_ST_CRC_ERR; break; @@ -1440,7 +1597,8 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, dbg("*"); } else { - err("CTL:TIMEOUT "); + if (!usb_pipeint(pipe)) + err("CTL:TIMEOUT "); dbg("submit_common_msg: TO status %x\n", stat); urb->finished = 1; stat = USB_ST_CRC_ERR; @@ -1451,60 +1609,168 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, dev->status = stat; dev->act_len = urb->actual_length; + if (usb_pipein(pipe) && dev->status == 0 && dev->act_len) + invalidate_dcache_buffer(buffer, dev->act_len); + #ifdef DEBUG - pkt_print(urb, dev, pipe, buffer, transfer_len, + pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); #else - mdelay(1); + ohci_mdelay(1); #endif + urb_free_priv(urb); + return 0; +} + +#define MAX_INT_QUEUESIZE 8 + +struct int_queue { + int queuesize; + int curr_urb; + urb_priv_t *urb[MAX_INT_QUEUESIZE]; +}; + +static struct int_queue *_ohci_create_int_queue(ohci_t *ohci, + struct usb_device *udev, unsigned long pipe, int queuesize, + int elementsize, void *buffer, int interval) +{ + struct int_queue *queue; + ohci_dev_t *ohci_dev; + int i; + + if (queuesize > MAX_INT_QUEUESIZE) + return NULL; + + ohci_dev = ohci_get_ohci_dev(ohci, udev->devnum, 1); + if (!ohci_dev) + return NULL; + + queue = malloc(sizeof(*queue)); + if (!queue) { + printf("ohci: Error out of memory allocating int queue\n"); + return NULL; + } + + for (i = 0; i < queuesize; i++) { + queue->urb[i] = ohci_alloc_urb(udev, pipe, + buffer + i * elementsize, + elementsize, interval); + if (!queue->urb[i]) + break; + + if (sohci_submit_job(ohci, ohci_dev, queue->urb[i], NULL)) { + printf("ohci: Error submitting int queue job\n"); + urb_free_priv(queue->urb[i]); + break; + } + } + if (i == 0) { + /* We did not succeed in submitting even 1 urb */ + free(queue); + return NULL; + } + + queue->queuesize = i; + queue->curr_urb = 0; + + return queue; +} + +static void *_ohci_poll_int_queue(ohci_t *ohci, struct usb_device *udev, + struct int_queue *queue) +{ + if (queue->curr_urb == queue->queuesize) + return NULL; /* Queue depleted */ + + if (hc_interrupt(ohci) < 0) + return NULL; + + if (queue->urb[queue->curr_urb]->finished) { + void *ret = queue->urb[queue->curr_urb]->transfer_buffer; + queue->curr_urb++; + return ret; + } + + return NULL; +} + +static int _ohci_destroy_int_queue(ohci_t *ohci, struct usb_device *dev, + struct int_queue *queue) +{ + int i; + + for (i = 0; i < queue->queuesize; i++) + urb_free_priv(queue->urb[i]); + + free(queue); - /* free TDs in urb_priv */ - if (!usb_pipeint(pipe)) - urb_free_priv(urb); return 0; } +#ifndef CONFIG_DM_USB /* submit routines called from usb.c */ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len) { info("submit_bulk_msg"); - return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); + return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, + NULL, 0); +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval) +{ + info("submit_int_msg"); + return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL, + interval); +} + +struct int_queue *create_int_queue(struct usb_device *dev, + unsigned long pipe, int queuesize, int elementsize, + void *buffer, int interval) +{ + return _ohci_create_int_queue(&gohci, dev, pipe, queuesize, + elementsize, buffer, interval); } -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup) +void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) +{ + return _ohci_poll_int_queue(&gohci, dev, queue); +} + +int destroy_int_queue(struct usb_device *dev, struct int_queue *queue) +{ + return _ohci_destroy_int_queue(&gohci, dev, queue); +} +#endif + +static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev, + unsigned long pipe, void *buffer, int transfer_len, + struct devrequest *setup) { int maxsize = usb_maxpacket(dev, pipe); info("submit_control_msg"); #ifdef DEBUG - pkt_print(NULL, dev, pipe, buffer, transfer_len, + pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); #else - mdelay(1); + ohci_mdelay(1); #endif if (!maxsize) { err("submit_control_message: pipesize for pipe %lx is zero", pipe); return -1; } - if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { - gohci.rh.dev = dev; + if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) { + ohci->rh.dev = dev; /* root hub - redirect */ - return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, - setup); + return ohci_submit_rh_msg(ohci, dev, pipe, buffer, + transfer_len, setup); } - return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, int interval) -{ - info("submit_int_msg"); - return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, - interval); + return submit_common_msg(ohci, dev, pipe, buffer, transfer_len, + setup, 0); } /*-------------------------------------------------------------------------* @@ -1593,8 +1859,11 @@ static int hc_start(ohci_t *ohci) { __u32 mask; unsigned int fminterval; + int i; ohci->disabled = 1; + for (i = 0; i < NUM_INT_DEVS; i++) + ohci->int_dev[i].devnum = -1; /* Tell the controller where the control and bulk lists are * The lists are empty now. */ @@ -1635,9 +1904,6 @@ static int hc_start(ohci_t *ohci) ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status); #endif /* OHCI_USE_NPS */ - /* POTPGT delay is bits 24-31, in 2 ms units. */ - mdelay((roothub_a(ohci) >> 23) & 0x1fe); - /* connect the virtual root hub */ ohci->rh.devnum = 0; @@ -1648,13 +1914,14 @@ static int hc_start(ohci_t *ohci) /* an interrupt happens */ -static int hc_interrupt(void) +static int hc_interrupt(ohci_t *ohci) { - ohci_t *ohci = &gohci; struct ohci_regs *regs = ohci->regs; int ints; int stat = -1; + invalidate_dcache_hcca(ohci->hcca); + if ((ohci->hcca->done_head != 0) && !(m32_swap(ohci->hcca->done_head) & 0x01)) { ints = OHCI_INTR_WDH; @@ -1688,7 +1955,7 @@ static int hc_interrupt(void) #ifdef DEBUG ohci_dump(ohci, 1); #else - mdelay(1); + ohci_mdelay(1); #endif /* FIXME: be optimistic, hope that bug won't repeat often. */ /* Make some non-interrupt context restart the controller. */ @@ -1699,10 +1966,10 @@ static int hc_interrupt(void) } if (ints & OHCI_INTR_WDH) { - mdelay(1); + ohci_mdelay(1); ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); (void)ohci_readl(®s->intrdisable); /* flush */ - stat = dl_done_list(&gohci); + stat = dl_done_list(ohci); ohci_writel(OHCI_INTR_WDH, ®s->intrenable); (void)ohci_readl(®s->intrdisable); /* flush */ } @@ -1729,6 +1996,8 @@ static int hc_interrupt(void) /*-------------------------------------------------------------------------*/ +#ifndef CONFIG_DM_USB + /*-------------------------------------------------------------------------*/ /* De-allocate all resources.. */ @@ -1772,21 +2041,9 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) err("HCCA not aligned!!"); return -1; } - phcca = &ghcca[0]; - info("aligned ghcca %p", phcca); - memset(&ohci_dev, 0, sizeof(struct ohci_device)); - if ((__u32)&ohci_dev.ed[0] & 0x7) { - err("EDs not aligned!!"); - return -1; - } - memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); - if ((__u32)gtd & 0x7) { - err("TDs not aligned!!"); - return -1; - } - ptd = gtd; - gohci.hcca = phcca; - memset(phcca, 0, sizeof(struct ohci_hcca)); + gohci.hcca = &ghcca[0]; + info("aligned ghcca %p", gohci.hcca); + memset(gohci.hcca, 0, sizeof(struct ohci_hcca)); gohci.disabled = 1; gohci.sleeping = 0; @@ -1848,7 +2105,7 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) #ifdef DEBUG ohci_dump(&gohci, 1); #else - mdelay(1); + ohci_mdelay(1); #endif ohci_inited = 1; return 0; @@ -1880,3 +2137,115 @@ int usb_lowlevel_stop(int index) ohci_inited = 0; return 0; } + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, struct devrequest *setup) +{ + return _ohci_submit_control_msg(&gohci, dev, pipe, buffer, + transfer_len, setup); +} +#endif + +#ifdef CONFIG_DM_USB +static int ohci_submit_control_msg(struct udevice *dev, struct usb_device *udev, + unsigned long pipe, void *buffer, int length, + struct devrequest *setup) +{ + ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); + + return _ohci_submit_control_msg(ohci, udev, pipe, buffer, + length, setup); +} + +static int ohci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, + unsigned long pipe, void *buffer, int length) +{ + ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); + + return submit_common_msg(ohci, udev, pipe, buffer, length, NULL, 0); +} + +static int ohci_submit_int_msg(struct udevice *dev, struct usb_device *udev, + unsigned long pipe, void *buffer, int length, + int interval) +{ + ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); + + return submit_common_msg(ohci, udev, pipe, buffer, length, + NULL, interval); +} + +static struct int_queue *ohci_create_int_queue(struct udevice *dev, + struct usb_device *udev, unsigned long pipe, int queuesize, + int elementsize, void *buffer, int interval) +{ + ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); + + return _ohci_create_int_queue(ohci, udev, pipe, queuesize, elementsize, + buffer, interval); +} + +static void *ohci_poll_int_queue(struct udevice *dev, struct usb_device *udev, + struct int_queue *queue) +{ + ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); + + return _ohci_poll_int_queue(ohci, udev, queue); +} + +static int ohci_destroy_int_queue(struct udevice *dev, struct usb_device *udev, + struct int_queue *queue) +{ + ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); + + return _ohci_destroy_int_queue(ohci, udev, queue); +} + +int ohci_register(struct udevice *dev, struct ohci_regs *regs) +{ + struct usb_bus_priv *priv = dev_get_uclass_priv(dev); + ohci_t *ohci = dev_get_priv(dev); + u32 reg; + + priv->desc_before_addr = true; + + ohci->regs = regs; + ohci->hcca = memalign(256, sizeof(struct ohci_hcca)); + if (!ohci->hcca) + return -ENOMEM; + memset(ohci->hcca, 0, sizeof(struct ohci_hcca)); + + if (hc_reset(ohci) < 0) + return -EIO; + + if (hc_start(ohci) < 0) + return -EIO; + + reg = ohci_readl(®s->revision); + printf("USB OHCI %x.%x\n", (reg >> 4) & 0xf, reg & 0xf); + + return 0; +} + +int ohci_deregister(struct udevice *dev) +{ + ohci_t *ohci = dev_get_priv(dev); + + if (hc_reset(ohci) < 0) + return -EIO; + + free(ohci->hcca); + + return 0; +} + +struct dm_usb_ops ohci_usb_ops = { + .control = ohci_submit_control_msg, + .bulk = ohci_submit_bulk_msg, + .interrupt = ohci_submit_int_msg, + .create_int_queue = ohci_create_int_queue, + .poll_int_queue = ohci_poll_int_queue, + .destroy_int_queue = ohci_destroy_int_queue, +}; + +#endif diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c new file mode 100644 index 0000000..e33a8f7 --- /dev/null +++ b/drivers/usb/host/ohci-sunxi.c @@ -0,0 +1,104 @@ +/* + * Sunxi ohci glue + * + * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> + * + * Based on code from + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/usb_phy.h> +#include <asm/io.h> +#include <dm.h> +#include <usb.h> +#include "ohci.h" + +struct ohci_sunxi_priv { + ohci_t ohci; + int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */ + int usb_gate_mask; /* Mask of usb_clk_cfg clk gate bits for this hcd */ + int phy_index; /* Index of the usb-phy attached to this hcd */ +}; + +static int ohci_usb_probe(struct udevice *dev) +{ + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev); + struct ohci_sunxi_priv *priv = dev_get_priv(dev); + struct ohci_regs *regs = (struct ohci_regs *)dev_get_addr(dev); + + bus_priv->companion = true; + + /* + * This should go away once we've moved to the driver model for + * clocks resp. phys. + */ + if (regs == (void *)(SUNXI_USB1_BASE + 0x400)) { + priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; + priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; + priv->phy_index = 1; + } else { + priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI1; + priv->usb_gate_mask = CCM_USB_CTRL_OHCI1_CLK; + priv->phy_index = 2; + } + + setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask); + setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask); +#ifdef CONFIG_SUNXI_GEN_SUN6I + setbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask); +#endif + + sunxi_usb_phy_init(priv->phy_index); + sunxi_usb_phy_power_on(priv->phy_index); + + return ohci_register(dev, regs); +} + +static int ohci_usb_remove(struct udevice *dev) +{ + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct ohci_sunxi_priv *priv = dev_get_priv(dev); + int ret; + + ret = ohci_deregister(dev); + if (ret) + return ret; + + sunxi_usb_phy_power_off(priv->phy_index); + sunxi_usb_phy_exit(priv->phy_index); + +#ifdef CONFIG_SUNXI_GEN_SUN6I + clrbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask); +#endif + clrbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask); + clrbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask); + + return 0; +} + +static const struct udevice_id ohci_usb_ids[] = { + { .compatible = "allwinner,sun4i-a10-ohci", }, + { .compatible = "allwinner,sun5i-a13-ohci", }, + { .compatible = "allwinner,sun6i-a31-ohci", }, + { .compatible = "allwinner,sun7i-a20-ohci", }, + { .compatible = "allwinner,sun8i-a23-ohci", }, + { .compatible = "allwinner,sun9i-a80-ohci", }, + { } +}; + +U_BOOT_DRIVER(usb_ohci) = { + .name = "ohci_sunxi", + .id = UCLASS_USB, + .of_match = ohci_usb_ids, + .probe = ohci_usb_probe, + .remove = ohci_usb_remove, + .ops = &ohci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct ohci_sunxi_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h index 9a4a2c2..f1526d4 100644 --- a/drivers/usb/host/ohci.h +++ b/drivers/usb/host/ohci.h @@ -18,6 +18,18 @@ # define ohci_writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) #endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */ +#if defined CONFIG_DM_USB && ARCH_DMA_MINALIGN > 16 +#define ED_ALIGNMENT ARCH_DMA_MINALIGN +#else +#define ED_ALIGNMENT 16 +#endif + +#if defined CONFIG_DM_USB && ARCH_DMA_MINALIGN > 32 +#define TD_ALIGNMENT ARCH_DMA_MINALIGN +#else +#define TD_ALIGNMENT 32 +#endif + /* functions for doing board or CPU specific setup/cleanup */ int usb_board_stop(void); @@ -25,64 +37,7 @@ int usb_cpu_init(void); int usb_cpu_stop(void); int usb_cpu_init_fail(void); -static int cc_to_error[16] = { - -/* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 -}; - -static const char *cc_to_string[16] = { - "No Error", - "CRC: Last data packet from endpoint contained a CRC error.", - "BITSTUFFING: Last data packet from endpoint contained a bit " \ - "stuffing violation", - "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \ - "that did not match the expected value.", - "STALL: TD was moved to the Done Queue because the endpoint returned" \ - " a STALL PID", - "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \ - "not provide a handshake (OUT)", - "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\ - "(IN) or handshake (OUT)", - "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \ - "value is not defined.", - "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \ - "either the size of the maximum data packet allowed\n" \ - "from the endpoint (found in MaximumPacketSize field\n" \ - "of ED) or the remaining buffer size.", - "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \ - "and that amount was not sufficient to fill the\n" \ - "specified buffer", - "reserved1", - "reserved2", - "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \ - "than it could be written to system memory", - "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \ - "system memory fast enough to keep up with data USB " \ - "data rate.", - "NOT ACCESSED: This code is set by software before the TD is placed" \ - "on a list to be processed by the HC.(1)", - "NOT ACCESSED: This code is set by software before the TD is placed" \ - "on a list to be processed by the HC.(2)", -}; - /* ED States */ - #define ED_NEW 0x00 #define ED_UNLINK 0x01 #define ED_OPER 0x02 @@ -109,7 +64,7 @@ struct ed { struct usb_device *usb_dev; void *purb; __u32 unused[2]; -} __attribute__((aligned(16))); +} __attribute__((aligned(ED_ALIGNMENT))); typedef struct ed ed_t; @@ -169,7 +124,7 @@ struct td { __u32 data; __u32 unused2[2]; -} __attribute__((aligned(32))); +} __attribute__((aligned(TD_ALIGNMENT))); typedef struct td td_t; #define OHCI_ED_SKIP (1 << 14) @@ -408,6 +363,19 @@ typedef struct } urb_priv_t; #define URB_DEL 1 +#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ + +#define NUM_TD 64 /* we need more TDs than EDs */ + +#define NUM_INT_DEVS 8 /* num of ohci_dev structs for int endpoints */ + +typedef struct ohci_device { + ed_t ed[NUM_EDS] __aligned(ED_ALIGNMENT); + td_t tds[NUM_TD] __aligned(TD_ALIGNMENT); + int ed_cnt; + int devnum; +} ohci_dev_t; + /* * This is the full ohci controller description * @@ -417,6 +385,9 @@ typedef struct typedef struct ohci { + /* this allocates EDs for all possible endpoints */ + struct ohci_device ohci_dev __aligned(TD_ALIGNMENT); + struct ohci_device int_dev[NUM_INT_DEVS] __aligned(TD_ALIGNMENT); struct ohci_hcca *hcca; /* hcca */ /*dma_addr_t hcca_dma;*/ @@ -439,53 +410,9 @@ typedef struct ohci { const char *slot_name; } ohci_t; -#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ - -struct ohci_device { - ed_t ed[NUM_EDS]; - int ed_cnt; -}; - -/* hcd */ -/* endpoint */ -static int ep_link(ohci_t * ohci, ed_t * ed); -static int ep_unlink(ohci_t * ohci, ed_t * ed); -static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe, - int interval, int load); - -/*-------------------------------------------------------------------------*/ - -/* we need more TDs than EDs */ -#define NUM_TD 64 - -/* +1 so we can align the storage */ -td_t gtd[NUM_TD+1]; -/* pointers to aligned storage */ -td_t *ptd; +#ifdef CONFIG_DM_USB +extern struct dm_usb_ops ohci_usb_ops; -/* TDs ... */ -static inline struct td * -td_alloc (struct usb_device *usb_dev) -{ - int i; - struct td *td; - - td = NULL; - for (i = 0; i < NUM_TD; i++) - { - if (ptd[i].usb_dev == NULL) - { - td = &ptd[i]; - td->usb_dev = usb_dev; - break; - } - } - - return td; -} - -static inline void -ed_free (struct ed *ed) -{ - ed->usb_dev = NULL; -} +int ohci_register(struct udevice *dev, struct ohci_regs *regs); +int ohci_deregister(struct udevice *dev); +#endif diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index 714bc0e..963464c 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -21,6 +21,10 @@ DECLARE_GLOBAL_DATA_PTR; extern bool usb_started; /* flag for the started/stopped USB status */ static bool asynch_allowed; +struct usb_uclass_priv { + int companion_device_count; +}; + int usb_disable_asynch(int disable) { int old_value = asynch_allowed; @@ -46,11 +50,22 @@ int submit_control_msg(struct usb_device *udev, unsigned long pipe, { struct udevice *bus = udev->controller_dev; struct dm_usb_ops *ops = usb_get_ops(bus); + struct usb_uclass_priv *uc_priv = bus->uclass->priv; + int err; if (!ops->control) return -ENOSYS; - return ops->control(bus, udev, pipe, buffer, length, setup); + err = ops->control(bus, udev, pipe, buffer, length, setup); + if (setup->request == USB_REQ_SET_FEATURE && + setup->requesttype == USB_RT_PORT && + setup->value == cpu_to_le16(USB_PORT_FEAT_RESET) && + err == -ENXIO) { + /* Device handed over to companion after port reset */ + uc_priv->companion_device_count++; + } + + return err; } int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer, @@ -65,6 +80,42 @@ int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer, return ops->bulk(bus, udev, pipe, buffer, length); } +struct int_queue *create_int_queue(struct usb_device *udev, + unsigned long pipe, int queuesize, int elementsize, + void *buffer, int interval) +{ + struct udevice *bus = udev->controller_dev; + struct dm_usb_ops *ops = usb_get_ops(bus); + + if (!ops->create_int_queue) + return NULL; + + return ops->create_int_queue(bus, udev, pipe, queuesize, elementsize, + buffer, interval); +} + +void *poll_int_queue(struct usb_device *udev, struct int_queue *queue) +{ + struct udevice *bus = udev->controller_dev; + struct dm_usb_ops *ops = usb_get_ops(bus); + + if (!ops->poll_int_queue) + return NULL; + + return ops->poll_int_queue(bus, udev, queue); +} + +int destroy_int_queue(struct usb_device *udev, struct int_queue *queue) +{ + struct udevice *bus = udev->controller_dev; + struct dm_usb_ops *ops = usb_get_ops(bus); + + if (!ops->destroy_int_queue) + return -ENOSYS; + + return ops->destroy_int_queue(bus, udev, queue); +} + int usb_alloc_device(struct usb_device *udev) { struct udevice *bus = udev->controller_dev; @@ -81,12 +132,16 @@ int usb_stop(void) { struct udevice *bus; struct uclass *uc; + struct usb_uclass_priv *uc_priv; int err = 0, ret; /* De-activate any devices that have been activated */ ret = uclass_get(UCLASS_USB, &uc); if (ret) return ret; + + uc_priv = uc->priv; + uclass_foreach_dev(bus, uc) { ret = device_remove(bus); if (ret && !err) @@ -106,12 +161,13 @@ int usb_stop(void) #endif usb_stor_reset(); usb_hub_reset(); + uc_priv->companion_device_count = 0; usb_started = 0; return err; } -static int usb_scan_bus(struct udevice *bus, bool recurse) +static void usb_scan_bus(struct udevice *bus, bool recurse) { struct usb_bus_priv *priv; struct udevice *dev; @@ -121,16 +177,22 @@ static int usb_scan_bus(struct udevice *bus, bool recurse) assert(recurse); /* TODO: Support non-recusive */ + printf("scanning bus %d for devices... ", bus->seq); + debug("\n"); ret = usb_scan_device(bus, 0, USB_SPEED_FULL, &dev); if (ret) - return ret; - - return priv->next_addr; + printf("failed, error %d\n", ret); + else if (priv->next_addr == 0) + printf("No USB Device found\n"); + else + printf("%d USB Device(s) found\n", priv->next_addr); } int usb_init(void) { int controllers_initialized = 0; + struct usb_uclass_priv *uc_priv; + struct usb_bus_priv *priv; struct udevice *bus; struct uclass *uc; int count = 0; @@ -143,11 +205,12 @@ int usb_init(void) if (ret) return ret; + uc_priv = uc->priv; + uclass_foreach_dev(bus, uc) { /* init low_level USB */ + printf("USB%d: ", count); count++; - printf("USB"); - printf("%d: ", bus->seq); ret = device_probe(bus); if (ret == -ENODEV) { /* No such device. */ puts("Port not available.\n"); @@ -159,23 +222,39 @@ int usb_init(void) printf("probe failed, error %d\n", ret); continue; } - /* - * lowlevel init is OK, now scan the bus for devices - * i.e. search HUBs and configure them - */ controllers_initialized++; - printf("scanning bus %d for devices... ", bus->seq); - debug("\n"); - ret = usb_scan_bus(bus, true); - if (ret < 0) - printf("failed, error %d\n", ret); - else if (!ret) - printf("No USB Device found\n"); - else - printf("%d USB Device(s) found\n", ret); usb_started = true; } + /* + * lowlevel init done, now scan the bus for devices i.e. search HUBs + * and configure them, first scan primary controllers. + */ + uclass_foreach_dev(bus, uc) { + if (!device_active(bus)) + continue; + + priv = dev_get_uclass_priv(bus); + if (!priv->companion) + usb_scan_bus(bus, true); + } + + /* + * Now that the primary controllers have been scanned and have handed + * over any devices they do not understand to their companions, scan + * the companions if necessary. + */ + if (uc_priv->companion_device_count) { + uclass_foreach_dev(bus, uc) { + if (!device_active(bus)) + continue; + + priv = dev_get_uclass_priv(bus); + if (priv->companion) + usb_scan_bus(bus, true); + } + } + debug("scan end\n"); /* if we were not able to find at least one working bus, bail out */ if (!count) @@ -477,9 +556,7 @@ int usb_scan_device(struct udevice *parent, int port, *devp = NULL; memset(udev, '\0', sizeof(*udev)); - ret = usb_get_bus(parent, &udev->controller_dev); - if (ret) - return ret; + udev->controller_dev = usb_get_bus(parent); priv = dev_get_uclass_priv(udev->controller_dev); /* @@ -536,11 +613,7 @@ int usb_scan_device(struct udevice *parent, int port, plat = dev_get_parent_platdata(dev); debug("%s: Probing '%s', plat=%p\n", __func__, dev->name, plat); plat->devnum = udev->devnum; - plat->speed = udev->speed; - plat->slot_id = udev->slot_id; - plat->portnr = port; - debug("** device '%s': stashing slot_id=%d\n", dev->name, - plat->slot_id); + plat->udev = udev; priv->next_addr++; ret = device_probe(dev); if (ret) { @@ -579,45 +652,55 @@ int usb_child_post_bind(struct udevice *dev) return 0; } -int usb_get_bus(struct udevice *dev, struct udevice **busp) +struct udevice *usb_get_bus(struct udevice *dev) { struct udevice *bus; - *busp = NULL; for (bus = dev; bus && device_get_uclass_id(bus) != UCLASS_USB; ) bus = bus->parent; if (!bus) { /* By design this cannot happen */ assert(bus); debug("USB HUB '%s' does not have a controller\n", dev->name); - return -EXDEV; } - *busp = bus; - return 0; + return bus; } int usb_child_pre_probe(struct udevice *dev) { - struct udevice *bus; struct usb_device *udev = dev_get_parentdata(dev); struct usb_dev_platdata *plat = dev_get_parent_platdata(dev); int ret; - ret = usb_get_bus(dev, &bus); - if (ret) - return ret; - udev->controller_dev = bus; - udev->dev = dev; - udev->devnum = plat->devnum; - udev->slot_id = plat->slot_id; - udev->portnr = plat->portnr; - udev->speed = plat->speed; - debug("** device '%s': getting slot_id=%d\n", dev->name, plat->slot_id); - - ret = usb_select_config(udev); - if (ret) - return ret; + if (plat->udev) { + /* + * Copy over all the values set in the on stack struct + * usb_device in usb_scan_device() to our final struct + * usb_device for this dev. + */ + *udev = *(plat->udev); + /* And clear plat->udev as it will not be valid for long */ + plat->udev = NULL; + udev->dev = dev; + } else { + /* + * This happens with devices which are explicitly bound + * instead of being discovered through usb_scan_device() + * such as sandbox emul devices. + */ + udev->dev = dev; + udev->controller_dev = usb_get_bus(dev); + udev->devnum = plat->devnum; + + /* + * udev did not go through usb_scan_device(), so we need to + * select the config and read the config descriptors. + */ + ret = usb_select_config(udev); + if (ret) + return ret; + } return 0; } @@ -627,6 +710,7 @@ UCLASS_DRIVER(usb) = { .name = "usb", .flags = DM_UC_FLAG_SEQ_ALIAS, .post_bind = usb_post_bind, + .priv_auto_alloc_size = sizeof(struct usb_uclass_priv), .per_child_auto_alloc_size = sizeof(struct usb_device), .per_device_auto_alloc_size = sizeof(struct usb_bus_priv), .child_post_bind = usb_child_post_bind, diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c index 23c7ecc..a27a796 100644 --- a/drivers/usb/host/xhci-exynos5.c +++ b/drivers/usb/host/xhci-exynos5.c @@ -33,36 +33,24 @@ /* Declare global data pointer */ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_DM_USB struct exynos_xhci_platdata { fdt_addr_t hcd_base; fdt_addr_t phy_base; struct gpio_desc vbus_gpio; }; -#endif /** * Contains pointers to register base addresses * for the usb controller. */ struct exynos_xhci { -#ifdef CONFIG_DM_USB struct usb_platdata usb_plat; -#endif struct xhci_ctrl ctrl; struct exynos_usb3_phy *usb3_phy; struct xhci_hccr *hcd; struct dwc3 *dwc3_reg; -#ifndef CONFIG_DM_USB - struct gpio_desc vbus_gpio; -#endif }; -#ifndef CONFIG_DM_USB -static struct exynos_xhci exynos; -#endif - -#ifdef CONFIG_DM_USB static int xhci_usb_ofdata_to_platdata(struct udevice *dev) { struct exynos_xhci_platdata *plat = dev_get_platdata(dev); @@ -102,54 +90,6 @@ static int xhci_usb_ofdata_to_platdata(struct udevice *dev) return 0; } -#else -static int exynos_usb3_parse_dt(const void *blob, struct exynos_xhci *exynos) -{ - fdt_addr_t addr; - unsigned int node; - int depth; - - node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_XHCI); - if (node <= 0) { - debug("XHCI: Can't get device node for xhci\n"); - return -ENODEV; - } - - /* - * Get the base address for XHCI controller from the device node - */ - addr = fdtdec_get_addr(blob, node, "reg"); - if (addr == FDT_ADDR_T_NONE) { - debug("Can't get the XHCI register base address\n"); - return -ENXIO; - } - exynos->hcd = (struct xhci_hccr *)addr; - - /* Vbus gpio */ - gpio_request_by_name_nodev(blob, node, "samsung,vbus-gpio", 0, - &exynos->vbus_gpio, GPIOD_IS_OUT); - - depth = 0; - node = fdtdec_next_compatible_subnode(blob, node, - COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth); - if (node <= 0) { - debug("XHCI: Can't get device node for usb3-phy controller\n"); - return -ENODEV; - } - - /* - * Get the base address for usbphy from the device node - */ - exynos->usb3_phy = (struct exynos_usb3_phy *)fdtdec_get_addr(blob, node, - "reg"); - if (exynos->usb3_phy == NULL) { - debug("Can't get the usbphy register address\n"); - return -ENXIO; - } - - return 0; -} -#endif static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy) { @@ -340,53 +280,6 @@ static void exynos_xhci_core_exit(struct exynos_xhci *exynos) exynos5_usb3_phy_exit(exynos->usb3_phy); } -#ifndef CONFIG_DM_USB -int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) -{ - struct exynos_xhci *ctx = &exynos; - int ret; - -#ifdef CONFIG_OF_CONTROL - exynos_usb3_parse_dt(gd->fdt_blob, ctx); -#else - ctx->usb3_phy = (struct exynos_usb3_phy *)samsung_get_base_usb3_phy(); - ctx->hcd = (struct xhci_hccr *)samsung_get_base_usb_xhci(); -#endif - - ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); - -#ifdef CONFIG_OF_CONTROL - /* setup the Vbus gpio here */ - if (dm_gpio_is_valid(&ctx->vbus_gpio)) - dm_gpio_set_value(&ctx->vbus_gpio, 1); -#endif - - ret = exynos_xhci_core_init(ctx); - if (ret) { - puts("XHCI: failed to initialize controller\n"); - return -EINVAL; - } - - *hccr = (ctx->hcd); - *hcor = (struct xhci_hcor *)((uint32_t) *hccr - + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); - - debug("Exynos5-xhci: init hccr %x and hcor %x hc_length %d\n", - (uint32_t)*hccr, (uint32_t)*hcor, - (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); - - return 0; -} - -void xhci_hcd_stop(int index) -{ - struct exynos_xhci *ctx = &exynos; - - exynos_xhci_core_exit(ctx); -} -#endif - -#ifdef CONFIG_DM_USB static int xhci_usb_probe(struct udevice *dev) { struct exynos_xhci_platdata *plat = dev_get_platdata(dev); @@ -443,4 +336,3 @@ U_BOOT_DRIVER(usb_xhci) = { .priv_auto_alloc_size = sizeof(struct exynos_xhci), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 51728b3..2544301 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -88,3 +88,18 @@ config VIDEO_LCD_SPI_MISO hardware and LCD panel id retrieval (if the panel can report it). The option takes a string in the format understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. + +config DISPLAY_PORT + bool "Enable DisplayPort support" + help + eDP (Embedded DisplayPort) is a standard widely used in laptops + to drive LCD panels. This framework provides support for enabling + these displays where supported by the video hardware. + +config VIDEO_TEGRA124 + bool "Enable video support on Tegra124" + help + Tegra124 supports many video output options including eDP and + HDMI. At present only eDP is supported by U-Boot. This option + enables this support which can be used on devices which + have an eDP display connected. diff --git a/drivers/video/Makefile b/drivers/video/Makefile index f64918e..2ead7f1 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -5,6 +5,10 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_DM +obj-$(CONFIG_DISPLAY_PORT) += dp-uclass.o +endif + obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o @@ -48,3 +52,5 @@ obj-$(CONFIG_FORMIKE) += formike.o obj-$(CONFIG_LG4573) += lg4573.o obj-$(CONFIG_AM335X_LCD) += am335x-fb.o obj-$(CONFIG_VIDEO_PARADE) += parade.o + +obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ diff --git a/drivers/video/dp-uclass.c b/drivers/video/dp-uclass.c new file mode 100644 index 0000000..17f5de9 --- /dev/null +++ b/drivers/video/dp-uclass.c @@ -0,0 +1,34 @@ +/* + * Copyright 2014 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <displayport.h> +#include <errno.h> + +int display_port_read_edid(struct udevice *dev, u8 *buf, int buf_size) +{ + struct dm_display_port_ops *ops = display_port_get_ops(dev); + + if (!ops || !ops->read_edid) + return -ENOSYS; + return ops->read_edid(dev, buf, buf_size); +} + +int display_port_enable(struct udevice *dev, int panel_bpp, + const struct display_timing *timing) +{ + struct dm_display_port_ops *ops = display_port_get_ops(dev); + + if (!ops || !ops->enable) + return -ENOSYS; + return ops->enable(dev, panel_bpp, timing); +} + +UCLASS_DRIVER(display_port) = { + .id = UCLASS_DISPLAY_PORT, + .name = "display_port", +}; diff --git a/drivers/video/tegra124/Makefile b/drivers/video/tegra124/Makefile new file mode 100644 index 0000000..52eedb0 --- /dev/null +++ b/drivers/video/tegra124/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (c) 2014 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += display.o +obj-y += dp.o +obj-y += sor.o +obj-y += tegra124-lcd.o diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra124/display.c new file mode 100644 index 0000000..7179dbf --- /dev/null +++ b/drivers/video/tegra124/display.c @@ -0,0 +1,472 @@ +/* + * Copyright 2014 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Extracted from Chromium coreboot commit 3f59b13d + */ + +#include <common.h> +#include <dm.h> +#include <edid.h> +#include <errno.h> +#include <displayport.h> +#include <edid.h> +#include <fdtdec.h> +#include <lcd.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/pwm.h> +#include <asm/arch-tegra/dc.h> +#include "displayport.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* return in 1000ths of a Hertz */ +static int tegra_dc_calc_refresh(const struct display_timing *timing) +{ + int h_total, v_total, refresh; + int pclk = timing->pixelclock.typ; + + h_total = timing->hactive.typ + timing->hfront_porch.typ + + timing->hback_porch.typ + timing->hsync_len.typ; + v_total = timing->vactive.typ + timing->vfront_porch.typ + + timing->vback_porch.typ + timing->vsync_len.typ; + if (!pclk || !h_total || !v_total) + return 0; + refresh = pclk / h_total; + refresh *= 1000; + refresh /= v_total; + + return refresh; +} + +static void print_mode(const struct display_timing *timing) +{ + int refresh = tegra_dc_calc_refresh(timing); + + debug("MODE:%dx%d@%d.%03uHz pclk=%d\n", + timing->hactive.typ, timing->vactive.typ, refresh / 1000, + refresh % 1000, timing->pixelclock.typ); +} + +static int update_display_mode(struct dc_ctlr *disp_ctrl, + const struct display_timing *timing, + int href_to_sync, int vref_to_sync) +{ + print_mode(timing); + + writel(0x1, &disp_ctrl->disp.disp_timing_opt); + + writel(vref_to_sync << 16 | href_to_sync, + &disp_ctrl->disp.ref_to_sync); + + writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ, + &disp_ctrl->disp.sync_width); + + writel(((timing->vback_porch.typ - vref_to_sync) << 16) | + timing->hback_porch.typ, &disp_ctrl->disp.back_porch); + + writel(((timing->vfront_porch.typ + vref_to_sync) << 16) | + timing->hfront_porch.typ, &disp_ctrl->disp.front_porch); + + writel(timing->hactive.typ | (timing->vactive.typ << 16), + &disp_ctrl->disp.disp_active); + + /** + * We want to use PLLD_out0, which is PLLD / 2: + * PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv. + * + * Currently most panels work inside clock range 50MHz~100MHz, and PLLD + * has some requirements to have VCO in range 500MHz~1000MHz (see + * clock.c for more detail). To simplify calculation, we set + * PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values + * may be calculated by clock_display, to allow wider frequency range. + * + * Note ShiftClockDiv is a 7.1 format value. + */ + const u32 shift_clock_div = 1; + writel((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) | + ((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT, + &disp_ctrl->disp.disp_clk_ctrl); + debug("%s: PixelClock=%u, ShiftClockDiv=%u\n", __func__, + timing->pixelclock.typ, shift_clock_div); + return 0; +} + +static u32 tegra_dc_poll_register(void *reg, + u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us) +{ + u32 temp = timeout_us; + u32 reg_val = 0; + + do { + udelay(poll_interval_us); + reg_val = readl(reg); + if (timeout_us > poll_interval_us) + timeout_us -= poll_interval_us; + else + break; + } while ((reg_val & mask) != exp_val); + + if ((reg_val & mask) == exp_val) + return 0; /* success */ + + return temp; +} + +int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl) +{ + writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); + + if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl, + GENERAL_ACT_REQ, 0, 100, + DC_POLL_TIMEOUT_MS * 1000)) { + debug("dc timeout waiting for DC to stop\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static struct display_timing min_mode = { + .hsync_len = { .typ = 1 }, + .vsync_len = { .typ = 1 }, + .hback_porch = { .typ = 20 }, + .vback_porch = { .typ = 0 }, + .hactive = { .typ = 16 }, + .vactive = { .typ = 16 }, + .hfront_porch = { .typ = 1 }, + .vfront_porch = { .typ = 2 }, +}; + +/* Disable windows and set minimum raster timings */ +void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl, + int *dc_reg_ctx) +{ + const int href_to_sync = 0, vref_to_sync = 1; + int selected_windows, i; + + selected_windows = readl(&disp_ctrl->cmd.disp_win_header); + + /* Store and clear window options */ + for (i = 0; i < DC_N_WINDOWS; ++i) { + writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header); + dc_reg_ctx[i] = readl(&disp_ctrl->win.win_opt); + writel(0, &disp_ctrl->win.win_opt); + writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl); + } + + writel(selected_windows, &disp_ctrl->cmd.disp_win_header); + + /* Store current raster timings and set minimum timings */ + dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync); + writel(href_to_sync | (vref_to_sync << 16), + &disp_ctrl->disp.ref_to_sync); + + dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width); + writel(min_mode.hsync_len.typ | (min_mode.vsync_len.typ << 16), + &disp_ctrl->disp.sync_width); + + dc_reg_ctx[i++] = readl(&disp_ctrl->disp.back_porch); + writel(min_mode.hback_porch.typ | (min_mode.vback_porch.typ << 16), + &disp_ctrl->disp.back_porch); + + dc_reg_ctx[i++] = readl(&disp_ctrl->disp.front_porch); + writel(min_mode.hfront_porch.typ | (min_mode.vfront_porch.typ << 16), + &disp_ctrl->disp.front_porch); + + dc_reg_ctx[i++] = readl(&disp_ctrl->disp.disp_active); + writel(min_mode.hactive.typ | (min_mode.vactive.typ << 16), + &disp_ctrl->disp.disp_active); + + writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); +} + +/* Restore previous windows status and raster timings */ +void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl, + int *dc_reg_ctx) +{ + int selected_windows, i; + + selected_windows = readl(&disp_ctrl->cmd.disp_win_header); + + for (i = 0; i < DC_N_WINDOWS; ++i) { + writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header); + writel(dc_reg_ctx[i], &disp_ctrl->win.win_opt); + writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl); + } + + writel(selected_windows, &disp_ctrl->cmd.disp_win_header); + + writel(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync); + writel(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width); + writel(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch); + writel(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch); + writel(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active); + + writel(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl); +} + +static int tegra_depth_for_bpp(int bpp) +{ + switch (bpp) { + case 32: + return COLOR_DEPTH_R8G8B8A8; + case 16: + return COLOR_DEPTH_B5G6R5; + default: + debug("Unsupported LCD bit depth"); + return -1; + } +} + +static int update_window(struct dc_ctlr *disp_ctrl, + u32 frame_buffer, int fb_bits_per_pixel, + const struct display_timing *timing) +{ + const u32 colour_white = 0xffffff; + int colour_depth; + u32 val; + + writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); + + writel(((timing->vactive.typ << 16) | timing->hactive.typ), + &disp_ctrl->win.size); + writel(((timing->vactive.typ << 16) | + (timing->hactive.typ * fb_bits_per_pixel / 8)), + &disp_ctrl->win.prescaled_size); + writel(((timing->hactive.typ * fb_bits_per_pixel / 8 + 31) / + 32 * 32), &disp_ctrl->win.line_stride); + + colour_depth = tegra_depth_for_bpp(fb_bits_per_pixel); + if (colour_depth == -1) + return -EINVAL; + + writel(colour_depth, &disp_ctrl->win.color_depth); + + writel(frame_buffer, &disp_ctrl->winbuf.start_addr); + writel(0x1000 << V_DDA_INC_SHIFT | 0x1000 << H_DDA_INC_SHIFT, + &disp_ctrl->win.dda_increment); + + writel(colour_white, &disp_ctrl->disp.blend_background_color); + writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT, + &disp_ctrl->cmd.disp_cmd); + + writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); + + val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; + val |= GENERAL_UPDATE | WIN_A_UPDATE; + writel(val, &disp_ctrl->cmd.state_ctrl); + + /* Enable win_a */ + val = readl(&disp_ctrl->win.win_opt); + writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt); + + return 0; +} + +static int tegra_dc_init(struct dc_ctlr *disp_ctrl) +{ + /* do not accept interrupts during initialization */ + writel(0x00000000, &disp_ctrl->cmd.int_mask); + writel(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, + &disp_ctrl->cmd.state_access); + writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); + writel(0x00000000, &disp_ctrl->win.win_opt); + writel(0x00000000, &disp_ctrl->win.byte_swap); + writel(0x00000000, &disp_ctrl->win.buffer_ctrl); + + writel(0x00000000, &disp_ctrl->win.pos); + writel(0x00000000, &disp_ctrl->win.h_initial_dda); + writel(0x00000000, &disp_ctrl->win.v_initial_dda); + writel(0x00000000, &disp_ctrl->win.dda_increment); + writel(0x00000000, &disp_ctrl->win.dv_ctrl); + + writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl); + writel(0x00000000, &disp_ctrl->win.blend_match_select); + writel(0x00000000, &disp_ctrl->win.blend_nomatch_select); + writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit); + + writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi); + writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset); + writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset); + + writel(0x00000000, &disp_ctrl->com.crc_checksum); + writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]); + writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]); + writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]); + writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]); + writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0); + + return 0; +} + +static void dump_config(int panel_bpp, struct display_timing *timing) +{ + printf("timing->hactive.typ = %d\n", timing->hactive.typ); + printf("timing->vactive.typ = %d\n", timing->vactive.typ); + printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ); + + printf("timing->hfront_porch.typ = %d\n", timing->hfront_porch.typ); + printf("timing->hsync_len.typ = %d\n", timing->hsync_len.typ); + printf("timing->hback_porch.typ = %d\n", timing->hback_porch.typ); + + printf("timing->vfront_porch.typ %d\n", timing->vfront_porch.typ); + printf("timing->vsync_len.typ = %d\n", timing->vsync_len.typ); + printf("timing->vback_porch.typ = %d\n", timing->vback_porch.typ); + + printf("panel_bits_per_pixel = %d\n", panel_bpp); +} + +static int display_update_config_from_edid(struct udevice *dp_dev, + int *panel_bppp, + struct display_timing *timing) +{ + u8 buf[EDID_SIZE]; + int bpc, ret; + + ret = display_port_read_edid(dp_dev, buf, sizeof(buf)); + if (ret < 0) + return ret; + ret = edid_get_timing(buf, ret, timing, &bpc); + if (ret) + return ret; + + /* Use this information if valid */ + if (bpc != -1) + *panel_bppp = bpc * 3; + + return 0; +} + +/* Somewhat torturous method */ +static int get_backlight_info(const void *blob, struct gpio_desc *vdd, + struct gpio_desc *enable, int *pwmp) +{ + int sor, panel, backlight, power; + const u32 *prop; + int len; + int ret; + + *pwmp = 0; + sor = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR); + if (sor < 0) + return -ENOENT; + panel = fdtdec_lookup_phandle(blob, sor, "nvidia,panel"); + if (panel < 0) + return -ENOENT; + backlight = fdtdec_lookup_phandle(blob, panel, "backlight"); + if (backlight < 0) + return -ENOENT; + ret = gpio_request_by_name_nodev(blob, backlight, "enable-gpios", 0, + enable, GPIOD_IS_OUT); + if (ret) + return ret; + prop = fdt_getprop(blob, backlight, "pwms", &len); + if (!prop || len != 3 * sizeof(u32)) + return -EINVAL; + *pwmp = fdt32_to_cpu(prop[1]); + + power = fdtdec_lookup_phandle(blob, backlight, "power-supply"); + if (power < 0) + return -ENOENT; + ret = gpio_request_by_name_nodev(blob, power, "gpio", 0, vdd, + GPIOD_IS_OUT); + if (ret) + goto err; + + return 0; + +err: + dm_gpio_free(NULL, enable); + return ret; +} + +int display_init(void *lcdbase, int fb_bits_per_pixel, + struct display_timing *timing) +{ + struct dc_ctlr *dc_ctlr; + const void *blob = gd->fdt_blob; + struct udevice *dp_dev; + const int href_to_sync = 1, vref_to_sync = 1; + int panel_bpp = 18; /* default 18 bits per pixel */ + u32 plld_rate; + struct gpio_desc vdd_gpio, enable_gpio; + int pwm; + int node; + int ret; + + ret = uclass_get_device(UCLASS_DISPLAY_PORT, 0, &dp_dev); + if (ret) + return ret; + + node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC); + if (node < 0) + return -ENOENT; + dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg"); + if (fdtdec_decode_display_timing(blob, node, 0, timing)) + return -EINVAL; + + ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing); + if (ret) { + debug("%s: Failed to decode EDID, using defaults\n", __func__); + dump_config(panel_bpp, timing); + } + + if (!get_backlight_info(blob, &vdd_gpio, &enable_gpio, &pwm)) { + dm_gpio_set_value(&vdd_gpio, 1); + debug("%s: backlight vdd setting gpio %08x to %d\n", + __func__, gpio_get_number(&vdd_gpio), 1); + } + + /* + * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER + * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the + * update_display_mode() for detail. + */ + plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2); + if (plld_rate == 0) { + printf("dc: clock init failed\n"); + return -EIO; + } else if (plld_rate != timing->pixelclock.typ * 2) { + debug("dc: plld rounded to %u\n", plld_rate); + timing->pixelclock.typ = plld_rate / 2; + } + + /* Init dc */ + ret = tegra_dc_init(dc_ctlr); + if (ret) { + debug("dc: init failed\n"); + return ret; + } + + /* Configure dc mode */ + ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync); + if (ret) { + debug("dc: failed to configure display mode\n"); + return ret; + } + + /* Enable dp */ + ret = display_port_enable(dp_dev, panel_bpp, timing); + if (ret) + return ret; + + ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing); + if (ret) + return ret; + + /* Set up Tegra PWM to drive the panel backlight */ + pwm_enable(pwm, 0, 220, 0x2e); + udelay(10 * 1000); + + if (dm_gpio_is_valid(&enable_gpio)) { + dm_gpio_set_value(&enable_gpio, 1); + debug("%s: backlight enable setting gpio %08x to %d\n", + __func__, gpio_get_number(&enable_gpio), 1); + } + + return 0; +} diff --git a/drivers/video/tegra124/displayport.h b/drivers/video/tegra124/displayport.h new file mode 100644 index 0000000..ace6ab0 --- /dev/null +++ b/drivers/video/tegra124/displayport.h @@ -0,0 +1,412 @@ +/* + * Copyright (c) 2014, NVIDIA Corporation. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _TEGRA_DISPLAYPORT_H +#define _TEGRA_DISPLAYPORT_H + +#include <linux/drm_dp_helper.h> + +struct dpaux_ctlr { + u32 reserved0; + u32 intr_en_aux; + u32 reserved2_4; + u32 intr_aux; +}; + +#define DPAUX_INTR_EN_AUX 0x1 +#define DPAUX_INTR_AUX 0x5 +#define DPAUX_DP_AUXDATA_WRITE_W(i) (0x9 + 4 * (i)) +#define DPAUX_DP_AUXDATA_READ_W(i) (0x19 + 4 * (i)) +#define DPAUX_DP_AUXADDR 0x29 +#define DPAUX_DP_AUXCTL 0x2d +#define DPAUX_DP_AUXCTL_CMDLEN_SHIFT 0 +#define DPAUX_DP_AUXCTL_CMDLEN_FIELD 0xff +#define DPAUX_DP_AUXCTL_CMD_SHIFT 12 +#define DPAUX_DP_AUXCTL_CMD_MASK (0xf << 12) +#define DPAUX_DP_AUXCTL_CMD_I2CWR (0 << 12) +#define DPAUX_DP_AUXCTL_CMD_I2CRD (1 << 12) +#define DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT (2 << 12) +#define DPAUX_DP_AUXCTL_CMD_MOTWR (4 << 12) +#define DPAUX_DP_AUXCTL_CMD_MOTRD (5 << 12) +#define DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT (6 << 12) +#define DPAUX_DP_AUXCTL_CMD_AUXWR (8 << 12) +#define DPAUX_DP_AUXCTL_CMD_AUXRD (9 << 12) +#define DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT 16 +#define DPAUX_DP_AUXCTL_TRANSACTREQ_MASK (0x1 << 16) +#define DPAUX_DP_AUXCTL_TRANSACTREQ_DONE (0 << 16) +#define DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING (1 << 16) +#define DPAUX_DP_AUXCTL_RST_SHIFT 31 +#define DPAUX_DP_AUXCTL_RST_DEASSERT (0 << 31) +#define DPAUX_DP_AUXCTL_RST_ASSERT (1 << 31) +#define DPAUX_DP_AUXSTAT 0x31 +#define DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT 28 +#define DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG (0 << 28) +#define DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED (1 << 28) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT 20 +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK (0xf << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE (0 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC (1 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1 (2 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND (3 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS (4 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH (5 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1 (6 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1 (7 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M (8 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1 (9 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2 (10 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY (11 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP (12 << 20) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT 16 +#define DPAUX_DP_AUXSTAT_REPLYTYPE_MASK (0xf << 16) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_ACK (0 << 16) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_NACK (1 << 16) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER (2 << 16) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK (4 << 16) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER (8 << 16) +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT 11 +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING (0 << 11) +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING (1 << 11) +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT 10 +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING (0 << 10) +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING (1 << 10) +#define DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT 9 +#define DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING (0 << 9) +#define DPAUX_DP_AUXSTAT_RX_ERROR_PENDING (1 << 9) +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT 8 +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING (0 << 8) +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING (1 << 8) +#define DPAUX_DP_AUXSTAT_REPLY_M_SHIFT 0 +#define DPAUX_DP_AUXSTAT_REPLY_M_MASK (0xff << 0) +#define DPAUX_HPD_CONFIG (0x3d) +#define DPAUX_HPD_IRQ_CONFIG 0x41 +#define DPAUX_DP_AUX_CONFIG 0x45 +#define DPAUX_HYBRID_PADCTL 0x49 +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT 15 +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE (0 << 15) +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE (1 << 15) +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT 14 +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE (0 << 14) +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE (1 << 14) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT 12 +#define DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK (0x3 << 12) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60 (0 << 12) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64 (1 << 12) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 (2 << 12) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56 (3 << 12) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT 8 +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK (0x7 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78 (0 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60 (1 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54 (2 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45 (3 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 (4 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42 (5 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39 (6 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34 (7 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT 2 +#define DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK (0x3f << 2) +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT 1 +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE (0 << 1) +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE (1 << 1) +#define DPAUX_HYBRID_PADCTL_MODE_SHIFT 0 +#define DPAUX_HYBRID_PADCTL_MODE_AUX 0 +#define DPAUX_HYBRID_PADCTL_MODE_I2C 1 +#define DPAUX_HYBRID_SPARE 0x4d +#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP 0 +#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN 1 + +#define DP_AUX_DEFER_MAX_TRIES 7 +#define DP_AUX_TIMEOUT_MAX_TRIES 2 +#define DP_POWER_ON_MAX_TRIES 3 + +#define DP_AUX_MAX_BYTES 16 + +#define DP_AUX_TIMEOUT_MS 40 +#define DP_DPCP_RETRY_SLEEP_NS 400 + +static const u32 tegra_dp_vs_regs[][4][4] = { + /* postcursor2 L0 */ + { + /* pre-emphasis: L0, L1, L2, L3 */ + {0x13, 0x19, 0x1e, 0x28}, /* voltage swing: L0 */ + {0x1e, 0x25, 0x2d}, /* L1 */ + {0x28, 0x32}, /* L2 */ + {0x3c}, /* L3 */ + }, + + /* postcursor2 L1 */ + { + {0x12, 0x17, 0x1b, 0x25}, + {0x1c, 0x23, 0x2a}, + {0x25, 0x2f}, + {0x39}, + }, + + /* postcursor2 L2 */ + { + {0x12, 0x16, 0x1a, 0x22}, + {0x1b, 0x20, 0x27}, + {0x24, 0x2d}, + {0x36}, + }, + + /* postcursor2 L3 */ + { + {0x11, 0x14, 0x17, 0x1f}, + {0x19, 0x1e, 0x24}, + {0x22, 0x2a}, + {0x32}, + }, +}; + +static const u32 tegra_dp_pe_regs[][4][4] = { + /* postcursor2 L0 */ + { + /* pre-emphasis: L0, L1, L2, L3 */ + {0x00, 0x09, 0x13, 0x25}, /* voltage swing: L0 */ + {0x00, 0x0f, 0x1e}, /* L1 */ + {0x00, 0x14}, /* L2 */ + {0x00}, /* L3 */ + }, + + /* postcursor2 L1 */ + { + {0x00, 0x0a, 0x14, 0x28}, + {0x00, 0x0f, 0x1e}, + {0x00, 0x14}, + {0x00}, + }, + + /* postcursor2 L2 */ + { + {0x00, 0x0a, 0x14, 0x28}, + {0x00, 0x0f, 0x1e}, + {0x00, 0x14}, + {0x00}, + }, + + /* postcursor2 L3 */ + { + {0x00, 0x0a, 0x14, 0x28}, + {0x00, 0x0f, 0x1e}, + {0x00, 0x14}, + {0x00}, + }, +}; + +static const u32 tegra_dp_pc_regs[][4][4] = { + /* postcursor2 L0 */ + { + /* pre-emphasis: L0, L1, L2, L3 */ + {0x00, 0x00, 0x00, 0x00}, /* voltage swing: L0 */ + {0x00, 0x00, 0x00}, /* L1 */ + {0x00, 0x00}, /* L2 */ + {0x00}, /* L3 */ + }, + + /* postcursor2 L1 */ + { + {0x02, 0x02, 0x04, 0x05}, + {0x02, 0x04, 0x05}, + {0x04, 0x05}, + {0x05}, + }, + + /* postcursor2 L2 */ + { + {0x04, 0x05, 0x08, 0x0b}, + {0x05, 0x09, 0x0b}, + {0x08, 0x0a}, + {0x0b}, + }, + + /* postcursor2 L3 */ + { + {0x05, 0x09, 0x0b, 0x12}, + {0x09, 0x0d, 0x12}, + {0x0b, 0x0f}, + {0x12}, + }, +}; + +static const u32 tegra_dp_tx_pu[][4][4] = { + /* postcursor2 L0 */ + { + /* pre-emphasis: L0, L1, L2, L3 */ + {0x20, 0x30, 0x40, 0x60}, /* voltage swing: L0 */ + {0x30, 0x40, 0x60}, /* L1 */ + {0x40, 0x60}, /* L2 */ + {0x60}, /* L3 */ + }, + + /* postcursor2 L1 */ + { + {0x20, 0x20, 0x30, 0x50}, + {0x30, 0x40, 0x50}, + {0x40, 0x50}, + {0x60}, + }, + + /* postcursor2 L2 */ + { + {0x20, 0x20, 0x30, 0x40}, + {0x30, 0x30, 0x40}, + {0x40, 0x50}, + {0x60}, + }, + + /* postcursor2 L3 */ + { + {0x20, 0x20, 0x20, 0x40}, + {0x30, 0x30, 0x40}, + {0x40, 0x40}, + {0x60}, + }, +}; + +enum { + DRIVECURRENT_LEVEL0 = 0, + DRIVECURRENT_LEVEL1 = 1, + DRIVECURRENT_LEVEL2 = 2, + DRIVECURRENT_LEVEL3 = 3, +}; + +enum { + PREEMPHASIS_DISABLED = 0, + PREEMPHASIS_LEVEL1 = 1, + PREEMPHASIS_LEVEL2 = 2, + PREEMPHASIS_LEVEL3 = 3, +}; + +enum { + POSTCURSOR2_LEVEL0 = 0, + POSTCURSOR2_LEVEL1 = 1, + POSTCURSOR2_LEVEL2 = 2, + POSTCURSOR2_LEVEL3 = 3, + POSTCURSOR2_SUPPORTED +}; + +static inline int tegra_dp_is_max_vs(u32 pe, u32 vs) +{ + return (vs < (DRIVECURRENT_LEVEL3 - pe)) ? 0 : 1; +} + +static inline int tegra_dp_is_max_pe(u32 pe, u32 vs) +{ + return (pe < (PREEMPHASIS_LEVEL3 - vs)) ? 0 : 1; +} + +static inline int tegra_dp_is_max_pc(u32 pc) +{ + return (pc < POSTCURSOR2_LEVEL3) ? 0 : 1; +} + +/* DPCD definitions which are not defined in drm_dp_helper.h */ +#define DP_DPCD_REV_MAJOR_SHIFT 4 +#define DP_DPCD_REV_MAJOR_MASK (0xf << 4) +#define DP_DPCD_REV_MINOR_SHIFT 0 +#define DP_DPCD_REV_MINOR_MASK 0xf + +#define DP_MAX_LINK_RATE_VAL_1_62_GPBS 0x6 +#define DP_MAX_LINK_RATE_VAL_2_70_GPBS 0xa +#define DP_MAX_LINK_RATE_VAL_5_40_GPBS 0x4 + +#define DP_MAX_LANE_COUNT_LANE_1 0x1 +#define DP_MAX_LANE_COUNT_LANE_2 0x2 +#define DP_MAX_LANE_COUNT_LANE_4 0x4 +#define DP_MAX_LANE_COUNT_TPS3_SUPPORTED_YES (1 << 6) +#define DP_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (1 << 7) + +#define NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT 0 +#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T (0x00000001 << 2) +#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2) +#define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 +#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T (0x00000001 << 5) +#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F (0x00000000 << 5) + +#define DP_MAX_DOWNSPREAD_VAL_NONE 0 +#define DP_MAX_DOWNSPREAD_VAL_0_5_PCT 1 +#define DP_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T (1 << 6) + +#define DP_EDP_CONFIGURATION_CAP_ASC_RESET_YES 1 +#define DP_EDP_CONFIGURATION_CAP_FRAMING_CHANGE_YES (1 << 1) + +#define DP_LANE_COUNT_SET_ENHANCEDFRAMING_T (1 << 7) + +#define DP_TRAINING_PATTERN_SET_SC_DISABLED_T (1 << 5) +#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F (0x00000000 << 5) +#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T (0x00000001 << 5) + +#define DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_DISABLE 0 +#define DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_ENABLE 1 + +#define NV_DPCD_TRAINING_LANE0_1_SET2 0x10f +#define NV_DPCD_TRAINING_LANE2_3_SET2 0x110 +#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T (1 << 2) +#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F (0 << 2) +#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T (1 << 6) +#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F (0 << 6) +#define NV_DPCD_LANEX_SET2_PC2_SHIFT 0 +#define NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT 4 + +#define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0 +#define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000) +#define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001) +#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1 +#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1) +#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1) +#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2 +#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2) +#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2) +#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4 +#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4) +#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4) +#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5 +#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5) +#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5) +#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6 +#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6) +#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6) + +#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED (0x00000204) +#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO (0x00000000) +#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES (0x00000001) + +#define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0 +#define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000) +#define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001) +#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1 +#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1) +#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1) +#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2 +#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2) +#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2) +#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4 +#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4) +#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4) +#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5 +#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5) +#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5) +#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6 +#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6) +#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6) + +#define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT 0 +#define NV_DPCD_ADJUST_REQ_LANEX_DC_MASK 0x3 +#define NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT 2 +#define NV_DPCD_ADJUST_REQ_LANEX_PE_MASK (0x3 << 2) +#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT 4 +#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK (0x3 << 4) +#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT 6 +#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK (0x3 << 6) +#define NV_DPCD_ADJUST_REQ_POST_CURSOR2 (0x0000020C) +#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK 0x3 +#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(i) (i*2) + +#define NV_DPCD_TRAINING_AUX_RD_INTERVAL (0x0000000E) +#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2) +#endif diff --git a/drivers/video/tegra124/dp.c b/drivers/video/tegra124/dp.c new file mode 100644 index 0000000..3c0b721 --- /dev/null +++ b/drivers/video/tegra124/dp.c @@ -0,0 +1,1607 @@ +/* + * Copyright (c) 2011-2013, NVIDIA Corporation. + * Copyright 2014 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <displayport.h> +#include <dm.h> +#include <div64.h> +#include <errno.h> +#include <fdtdec.h> +#include <asm/io.h> +#include <asm/arch-tegra/dc.h> +#include "displayport.h" +#include "edid.h" +#include "sor.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define DO_FAST_LINK_TRAINING 1 + +struct tegra_dp_plat { + ulong base; +}; + +struct tegra_dp_priv { + struct dpaux_ctlr *regs; + struct tegra_dc_sor_data *sor; + u8 revision; + int enabled; +}; + +struct tegra_dp_priv dp_data; + +static inline u32 tegra_dpaux_readl(struct tegra_dp_priv *dp, u32 reg) +{ + return readl((u32 *)dp->regs + reg); +} + +static inline void tegra_dpaux_writel(struct tegra_dp_priv *dp, u32 reg, + u32 val) +{ + writel(val, (u32 *)dp->regs + reg); +} + +static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dp_priv *dp, + u32 reg, u32 mask, u32 exp_val, + u32 poll_interval_us, + u32 timeout_us) +{ + u32 reg_val = 0; + u32 temp = timeout_us; + + do { + udelay(poll_interval_us); + reg_val = tegra_dpaux_readl(dp, reg); + if (timeout_us > poll_interval_us) + timeout_us -= poll_interval_us; + else + break; + } while ((reg_val & mask) != exp_val); + + if ((reg_val & mask) == exp_val) + return 0; /* success */ + debug("dpaux_poll_register 0x%x: timeout: (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n", + reg, reg_val, mask, exp_val); + return temp; +} + +static inline int tegra_dpaux_wait_transaction(struct tegra_dp_priv *dp) +{ + /* According to DP spec, each aux transaction needs to finish + within 40ms. */ + if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL, + DPAUX_DP_AUXCTL_TRANSACTREQ_MASK, + DPAUX_DP_AUXCTL_TRANSACTREQ_DONE, + 100, DP_AUX_TIMEOUT_MS * 1000) != 0) { + debug("dp: DPAUX transaction timeout\n"); + return -1; + } + return 0; +} + +static int tegra_dc_dpaux_write_chunk(struct tegra_dp_priv *dp, u32 cmd, + u32 addr, u8 *data, u32 *size, + u32 *aux_stat) +{ + int i; + u32 reg_val; + u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES; + u32 defer_retries = DP_AUX_DEFER_MAX_TRIES; + u32 temp_data; + + if (*size > DP_AUX_MAX_BYTES) + return -1; /* only write one chunk of data */ + + /* Make sure the command is write command */ + switch (cmd) { + case DPAUX_DP_AUXCTL_CMD_I2CWR: + case DPAUX_DP_AUXCTL_CMD_MOTWR: + case DPAUX_DP_AUXCTL_CMD_AUXWR: + break; + default: + debug("dp: aux write cmd 0x%x is invalid\n", cmd); + return -EINVAL; + } + + tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); + for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) { + memcpy(&temp_data, data, 4); + tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i), temp_data); + data += 4; + } + + reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); + reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK; + reg_val |= cmd; + reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD; + reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT); + + while ((timeout_retries > 0) && (defer_retries > 0)) { + if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) || + (defer_retries != DP_AUX_DEFER_MAX_TRIES)) + udelay(1); + + reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING; + tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); + + if (tegra_dpaux_wait_transaction(dp)) + debug("dp: aux write transaction timeout\n"); + + *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); + + if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) || + (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) || + (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || + (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) { + if (timeout_retries-- > 0) { + debug("dp: aux write retry (0x%x) -- %d\n", + *aux_stat, timeout_retries); + /* clear the error bits */ + tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, + *aux_stat); + continue; + } else { + debug("dp: aux write got error (0x%x)\n", + *aux_stat); + return -ETIMEDOUT; + } + } + + if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) || + (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) { + if (defer_retries-- > 0) { + debug("dp: aux write defer (0x%x) -- %d\n", + *aux_stat, defer_retries); + /* clear the error bits */ + tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, + *aux_stat); + continue; + } else { + debug("dp: aux write defer exceeds max retries (0x%x)\n", + *aux_stat); + return -ETIMEDOUT; + } + } + + if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) == + DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) { + *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK); + return 0; + } else { + debug("dp: aux write failed (0x%x)\n", *aux_stat); + return -EIO; + } + } + /* Should never come to here */ + return -EIO; +} + +static int tegra_dc_dpaux_read_chunk(struct tegra_dp_priv *dp, u32 cmd, + u32 addr, u8 *data, u32 *size, + u32 *aux_stat) +{ + u32 reg_val; + u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES; + u32 defer_retries = DP_AUX_DEFER_MAX_TRIES; + + if (*size > DP_AUX_MAX_BYTES) { + debug("only read one chunk\n"); + return -EIO; /* only read one chunk */ + } + + /* Check to make sure the command is read command */ + switch (cmd) { + case DPAUX_DP_AUXCTL_CMD_I2CRD: + case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT: + case DPAUX_DP_AUXCTL_CMD_MOTRD: + case DPAUX_DP_AUXCTL_CMD_AUXRD: + break; + default: + debug("dp: aux read cmd 0x%x is invalid\n", cmd); + return -EIO; + } + + *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); + if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) { + debug("dp: HPD is not detected\n"); + return -EIO; + } + + tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); + + reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); + reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK; + reg_val |= cmd; + reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD; + reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT); + while ((timeout_retries > 0) && (defer_retries > 0)) { + if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) || + (defer_retries != DP_AUX_DEFER_MAX_TRIES)) + udelay(DP_DPCP_RETRY_SLEEP_NS * 2); + + reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING; + tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); + + if (tegra_dpaux_wait_transaction(dp)) + debug("dp: aux read transaction timeout\n"); + + *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); + + if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) || + (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) || + (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || + (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) { + if (timeout_retries-- > 0) { + debug("dp: aux read retry (0x%x) -- %d\n", + *aux_stat, timeout_retries); + /* clear the error bits */ + tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, + *aux_stat); + continue; /* retry */ + } else { + debug("dp: aux read got error (0x%x)\n", + *aux_stat); + return -ETIMEDOUT; + } + } + + if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) || + (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) { + if (defer_retries-- > 0) { + debug("dp: aux read defer (0x%x) -- %d\n", + *aux_stat, defer_retries); + /* clear the error bits */ + tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, + *aux_stat); + continue; + } else { + debug("dp: aux read defer exceeds max retries (0x%x)\n", + *aux_stat); + return -ETIMEDOUT; + } + } + + if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) == + DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) { + int i; + u32 temp_data[4]; + + for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) + temp_data[i] = tegra_dpaux_readl(dp, + DPAUX_DP_AUXDATA_READ_W(i)); + + *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK); + memcpy(data, temp_data, *size); + + return 0; + } else { + debug("dp: aux read failed (0x%x\n", *aux_stat); + return -EIO; + } + } + /* Should never come to here */ + debug("%s: can't\n", __func__); + + return -EIO; +} + +static int tegra_dc_dpaux_read(struct tegra_dp_priv *dp, u32 cmd, u32 addr, + u8 *data, u32 *size, u32 *aux_stat) +{ + u32 finished = 0; + u32 cur_size; + int ret = 0; + + do { + cur_size = *size - finished; + if (cur_size > DP_AUX_MAX_BYTES) + cur_size = DP_AUX_MAX_BYTES; + + ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr, + data, &cur_size, aux_stat); + if (ret) + break; + + /* cur_size should be the real size returned */ + addr += cur_size; + data += cur_size; + finished += cur_size; + + } while (*size > finished); + *size = finished; + + return ret; +} + +static int tegra_dc_dp_dpcd_read(struct tegra_dp_priv *dp, u32 cmd, + u8 *data_ptr) +{ + u32 size = 1; + u32 status = 0; + int ret; + + ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, + cmd, data_ptr, &size, &status); + if (ret) { + debug("dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n", + cmd, status); + } + + return ret; +} + +static int tegra_dc_dp_dpcd_write(struct tegra_dp_priv *dp, u32 cmd, + u8 data) +{ + u32 size = 1; + u32 status = 0; + int ret; + + ret = tegra_dc_dpaux_write_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXWR, + cmd, &data, &size, &status); + if (ret) { + debug("dp: Failed to write DPCD data. CMD 0x%x, Status 0x%x\n", + cmd, status); + } + + return ret; +} + +static int tegra_dc_i2c_aux_read(struct tegra_dp_priv *dp, u32 i2c_addr, + u8 addr, u8 *data, u32 size, u32 *aux_stat) +{ + u32 finished = 0; + int ret = 0; + + do { + u32 cur_size = min((u32)DP_AUX_MAX_BYTES, size - finished); + + u32 len = 1; + ret = tegra_dc_dpaux_write_chunk( + dp, DPAUX_DP_AUXCTL_CMD_MOTWR, i2c_addr, + &addr, &len, aux_stat); + if (ret) { + debug("%s: error sending address to read.\n", + __func__); + return ret; + } + + ret = tegra_dc_dpaux_read_chunk( + dp, DPAUX_DP_AUXCTL_CMD_I2CRD, i2c_addr, + data, &cur_size, aux_stat); + if (ret) { + debug("%s: error reading data.\n", __func__); + return ret; + } + + /* cur_size should be the real size returned */ + addr += cur_size; + data += cur_size; + finished += cur_size; + } while (size > finished); + + return finished; +} + +static void tegra_dc_dpaux_enable(struct tegra_dp_priv *dp) +{ + /* clear interrupt */ + tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff); + /* do not enable interrupt for now. Enable them when Isr in place */ + tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0); + + tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL, + DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 | + DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 | + 0x18 << DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT | + DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE); + + tegra_dpaux_writel(dp, DPAUX_HYBRID_SPARE, + DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP); +} + +#ifdef DEBUG +static void tegra_dc_dp_dump_link_cfg(struct tegra_dp_priv *dp, + const struct tegra_dp_link_config *link_cfg) +{ + debug("DP config: cfg_name cfg_value\n"); + debug(" Lane Count %d\n", + link_cfg->max_lane_count); + debug(" SupportEnhancedFraming %s\n", + link_cfg->support_enhanced_framing ? "Y" : "N"); + debug(" Bandwidth %d\n", + link_cfg->max_link_bw); + debug(" bpp %d\n", + link_cfg->bits_per_pixel); + debug(" EnhancedFraming %s\n", + link_cfg->enhanced_framing ? "Y" : "N"); + debug(" Scramble_enabled %s\n", + link_cfg->scramble_ena ? "Y" : "N"); + debug(" LinkBW %d\n", + link_cfg->link_bw); + debug(" lane_count %d\n", + link_cfg->lane_count); + debug(" activespolarity %d\n", + link_cfg->activepolarity); + debug(" active_count %d\n", + link_cfg->active_count); + debug(" tu_size %d\n", + link_cfg->tu_size); + debug(" active_frac %d\n", + link_cfg->active_frac); + debug(" watermark %d\n", + link_cfg->watermark); + debug(" hblank_sym %d\n", + link_cfg->hblank_sym); + debug(" vblank_sym %d\n", + link_cfg->vblank_sym); +} +#endif + +static int _tegra_dp_lower_link_config(struct tegra_dp_priv *dp, + struct tegra_dp_link_config *cfg) +{ + switch (cfg->link_bw) { + case SOR_LINK_SPEED_G1_62: + if (cfg->max_link_bw > SOR_LINK_SPEED_G1_62) + cfg->link_bw = SOR_LINK_SPEED_G2_7; + cfg->lane_count /= 2; + break; + case SOR_LINK_SPEED_G2_7: + cfg->link_bw = SOR_LINK_SPEED_G1_62; + break; + case SOR_LINK_SPEED_G5_4: + if (cfg->lane_count == 1) { + cfg->link_bw = SOR_LINK_SPEED_G2_7; + cfg->lane_count = cfg->max_lane_count; + } else { + cfg->lane_count /= 2; + } + break; + default: + debug("dp: Error link rate %d\n", cfg->link_bw); + return -ENOLINK; + } + + return (cfg->lane_count > 0) ? 0 : -ENOLINK; +} + +/* + * Calcuate if given cfg can meet the mode request. + * Return 0 if mode is possible, -1 otherwise + */ +static int tegra_dc_dp_calc_config(struct tegra_dp_priv *dp, + const struct display_timing *timing, + struct tegra_dp_link_config *link_cfg) +{ + const u32 link_rate = 27 * link_cfg->link_bw * 1000 * 1000; + const u64 f = 100000; /* precision factor */ + u32 num_linkclk_line; /* Number of link clocks per line */ + u64 ratio_f; /* Ratio of incoming to outgoing data rate */ + u64 frac_f; + u64 activesym_f; /* Activesym per TU */ + u64 activecount_f; + u32 activecount; + u32 activepolarity; + u64 approx_value_f; + u32 activefrac = 0; + u64 accumulated_error_f = 0; + u32 lowest_neg_activecount = 0; + u32 lowest_neg_activepolarity = 0; + u32 lowest_neg_tusize = 64; + u32 num_symbols_per_line; + u64 lowest_neg_activefrac = 0; + u64 lowest_neg_error_f = 64 * f; + u64 watermark_f; + int i; + int neg; + + if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ || + !link_cfg->bits_per_pixel) + return -1; + + if ((u64)timing->pixelclock.typ * link_cfg->bits_per_pixel >= + (u64)link_rate * 8 * link_cfg->lane_count) + return -1; + + num_linkclk_line = (u32)(lldiv(link_rate * timing->hactive.typ, + timing->pixelclock.typ)); + + ratio_f = (u64)timing->pixelclock.typ * link_cfg->bits_per_pixel * f; + ratio_f /= 8; + do_div(ratio_f, link_rate * link_cfg->lane_count); + + for (i = 64; i >= 32; --i) { + activesym_f = ratio_f * i; + activecount_f = lldiv(activesym_f, (u32)f) * f; + frac_f = activesym_f - activecount_f; + activecount = (u32)(lldiv(activecount_f, (u32)f)); + + if (frac_f < (lldiv(f, 2))) /* fraction < 0.5 */ + activepolarity = 0; + else { + activepolarity = 1; + frac_f = f - frac_f; + } + + if (frac_f != 0) { + /* warning: frac_f should be 64-bit */ + frac_f = lldiv(f * f, frac_f); /* 1 / fraction */ + if (frac_f > (15 * f)) + activefrac = activepolarity ? 1 : 15; + else + activefrac = activepolarity ? + (u32)lldiv(frac_f, (u32)f) + 1 : + (u32)lldiv(frac_f, (u32)f); + } + + if (activefrac == 1) + activepolarity = 0; + + if (activepolarity == 1) + approx_value_f = activefrac ? lldiv( + (activecount_f + (activefrac * f - f) * f), + (activefrac * f)) : + activecount_f + f; + else + approx_value_f = activefrac ? + activecount_f + lldiv(f, activefrac) : + activecount_f; + + if (activesym_f < approx_value_f) { + accumulated_error_f = num_linkclk_line * + lldiv(approx_value_f - activesym_f, i); + neg = 1; + } else { + accumulated_error_f = num_linkclk_line * + lldiv(activesym_f - approx_value_f, i); + neg = 0; + } + + if ((neg && (lowest_neg_error_f > accumulated_error_f)) || + (accumulated_error_f == 0)) { + lowest_neg_error_f = accumulated_error_f; + lowest_neg_tusize = i; + lowest_neg_activecount = activecount; + lowest_neg_activepolarity = activepolarity; + lowest_neg_activefrac = activefrac; + + if (accumulated_error_f == 0) + break; + } + } + + if (lowest_neg_activefrac == 0) { + link_cfg->activepolarity = 0; + link_cfg->active_count = lowest_neg_activepolarity ? + lowest_neg_activecount : lowest_neg_activecount - 1; + link_cfg->tu_size = lowest_neg_tusize; + link_cfg->active_frac = 1; + } else { + link_cfg->activepolarity = lowest_neg_activepolarity; + link_cfg->active_count = (u32)lowest_neg_activecount; + link_cfg->tu_size = lowest_neg_tusize; + link_cfg->active_frac = (u32)lowest_neg_activefrac; + } + + watermark_f = lldiv(ratio_f * link_cfg->tu_size * (f - ratio_f), f); + link_cfg->watermark = (u32)(lldiv(watermark_f + lowest_neg_error_f, + f)) + link_cfg->bits_per_pixel / 4 - 1; + num_symbols_per_line = (timing->hactive.typ * + link_cfg->bits_per_pixel) / + (8 * link_cfg->lane_count); + + if (link_cfg->watermark > 30) { + debug("dp: sor setting: unable to get a good tusize, force watermark to 30\n"); + link_cfg->watermark = 30; + return -1; + } else if (link_cfg->watermark > num_symbols_per_line) { + debug("dp: sor setting: force watermark to the number of symbols in the line\n"); + link_cfg->watermark = num_symbols_per_line; + return -1; + } + + /* + * Refer to dev_disp.ref for more information. + * # symbols/hblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - + * SetRasterBlankStart.X - 7) * link_clk / pclk) + * - 3 * enhanced_framing - Y + * where Y = (# lanes == 4) 3 : (# lanes == 2) ? 6 : 12 + */ + link_cfg->hblank_sym = (int)lldiv(((uint64_t)timing->hback_porch.typ + + timing->hfront_porch.typ + timing->hsync_len.typ - 7) * + link_rate, timing->pixelclock.typ) - + 3 * link_cfg->enhanced_framing - + (12 / link_cfg->lane_count); + + if (link_cfg->hblank_sym < 0) + link_cfg->hblank_sym = 0; + + + /* + * Refer to dev_disp.ref for more information. + * # symbols/vblank = ((SetRasterBlankStart.X - + * SetRasterBlankEen.X - 25) * link_clk / pclk) + * - Y - 1; + * where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39 + */ + link_cfg->vblank_sym = (int)lldiv(((uint64_t)timing->hactive.typ - 25) + * link_rate, timing->pixelclock.typ) - (36 / + link_cfg->lane_count) - 4; + + if (link_cfg->vblank_sym < 0) + link_cfg->vblank_sym = 0; + + link_cfg->is_valid = 1; +#ifdef DEBUG + tegra_dc_dp_dump_link_cfg(dp, link_cfg); +#endif + + return 0; +} + +static int tegra_dc_dp_init_max_link_cfg( + const struct display_timing *timing, + struct tegra_dp_priv *dp, + struct tegra_dp_link_config *link_cfg) +{ + const int drive_current = 0x40404040; + const int preemphasis = 0x0f0f0f0f; + const int postcursor = 0; + u8 dpcd_data; + int ret; + + ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LANE_COUNT, &dpcd_data); + if (ret) + return ret; + link_cfg->max_lane_count = dpcd_data & DP_MAX_LANE_COUNT_MASK; + link_cfg->tps3_supported = (dpcd_data & + DP_MAX_LANE_COUNT_TPS3_SUPPORTED_YES) ? 1 : 0; + + link_cfg->support_enhanced_framing = + (dpcd_data & DP_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ? + 1 : 0; + + ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_DOWNSPREAD, &dpcd_data); + if (ret) + return ret; + link_cfg->downspread = (dpcd_data & DP_MAX_DOWNSPREAD_VAL_0_5_PCT) ? + 1 : 0; + + ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_AUX_RD_INTERVAL, + &link_cfg->aux_rd_interval); + if (ret) + return ret; + ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LINK_RATE, + &link_cfg->max_link_bw); + if (ret) + return ret; + + /* + * Set to a high value for link training and attach. + * Will be re-programmed when dp is enabled. + */ + link_cfg->drive_current = drive_current; + link_cfg->preemphasis = preemphasis; + link_cfg->postcursor = postcursor; + + ret = tegra_dc_dp_dpcd_read(dp, DP_EDP_CONFIGURATION_CAP, &dpcd_data); + if (ret) + return ret; + + link_cfg->alt_scramber_reset_cap = + (dpcd_data & DP_EDP_CONFIGURATION_CAP_ASC_RESET_YES) ? + 1 : 0; + link_cfg->only_enhanced_framing = + (dpcd_data & DP_EDP_CONFIGURATION_CAP_FRAMING_CHANGE_YES) ? + 1 : 0; + + link_cfg->lane_count = link_cfg->max_lane_count; + link_cfg->link_bw = link_cfg->max_link_bw; + link_cfg->enhanced_framing = link_cfg->support_enhanced_framing; + link_cfg->frame_in_ms = (1000 / 60) + 1; + + tegra_dc_dp_calc_config(dp, timing, link_cfg); + return 0; +} + +static int tegra_dc_dp_set_assr(struct tegra_dp_priv *dp, + struct tegra_dc_sor_data *sor, int ena) +{ + int ret; + + u8 dpcd_data = ena ? + DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_ENABLE : + DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_DISABLE; + + ret = tegra_dc_dp_dpcd_write(dp, DP_EDP_CONFIGURATION_SET, + dpcd_data); + if (ret) + return ret; + + /* Also reset the scrambler to 0xfffe */ + tegra_dc_sor_set_internal_panel(sor, ena); + return 0; +} + +static int tegra_dp_set_link_bandwidth(struct tegra_dp_priv *dp, + struct tegra_dc_sor_data *sor, + u8 link_bw) +{ + tegra_dc_sor_set_link_bandwidth(sor, link_bw); + + /* Sink side */ + return tegra_dc_dp_dpcd_write(dp, DP_LINK_BW_SET, link_bw); +} + +static int tegra_dp_set_lane_count(struct tegra_dp_priv *dp, + const struct tegra_dp_link_config *link_cfg, + struct tegra_dc_sor_data *sor) +{ + u8 dpcd_data; + int ret; + + /* check if panel support enhanched_framing */ + dpcd_data = link_cfg->lane_count; + if (link_cfg->enhanced_framing) + dpcd_data |= DP_LANE_COUNT_SET_ENHANCEDFRAMING_T; + ret = tegra_dc_dp_dpcd_write(dp, DP_LANE_COUNT_SET, dpcd_data); + if (ret) + return ret; + + tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count); + + /* Also power down lanes that will not be used */ + return 0; +} + +static int tegra_dc_dp_link_trained(struct tegra_dp_priv *dp, + const struct tegra_dp_link_config *cfg) +{ + u32 lane; + u8 mask; + u8 data; + int ret; + + for (lane = 0; lane < cfg->lane_count; ++lane) { + ret = tegra_dc_dp_dpcd_read(dp, (lane / 2) ? + DP_LANE2_3_STATUS : DP_LANE0_1_STATUS, + &data); + if (ret) + return ret; + mask = (lane & 1) ? + NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES | + NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES | + NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES : + DP_LANE_CR_DONE | + DP_LANE_CHANNEL_EQ_DONE | + DP_LANE_SYMBOL_LOCKED; + if ((data & mask) != mask) + return -1; + } + return 0; +} + +static int tegra_dp_channel_eq_status(struct tegra_dp_priv *dp, + const struct tegra_dp_link_config *cfg) +{ + u32 cnt; + u32 n_lanes = cfg->lane_count; + u8 data; + u8 ce_done = 1; + int ret; + + for (cnt = 0; cnt < n_lanes / 2; cnt++) { + ret = tegra_dc_dp_dpcd_read(dp, DP_LANE0_1_STATUS + cnt, &data); + if (ret) + return ret; + + if (n_lanes == 1) { + ce_done = (data & (0x1 << + NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) && + (data & (0x1 << + NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT)); + break; + } else if (!(data & (0x1 << + NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) || + !(data & (0x1 << + NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT)) || + !(data & (0x1 << + NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT)) || + !(data & (0x1 << + NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT))) + return -EIO; + } + + if (ce_done) { + ret = tegra_dc_dp_dpcd_read(dp, + DP_LANE_ALIGN_STATUS_UPDATED, + &data); + if (ret) + return ret; + if (!(data & NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES)) + ce_done = 0; + } + + return ce_done ? 0 : -EIO; +} + +static int tegra_dp_clock_recovery_status(struct tegra_dp_priv *dp, + const struct tegra_dp_link_config *cfg) +{ + u32 cnt; + u32 n_lanes = cfg->lane_count; + u8 data_ptr; + int ret; + + for (cnt = 0; cnt < n_lanes / 2; cnt++) { + ret = tegra_dc_dp_dpcd_read(dp, (DP_LANE0_1_STATUS + cnt), + &data_ptr); + if (ret) + return ret; + + if (n_lanes == 1) + return (data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) ? + 1 : 0; + else if (!(data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) || + !(data_ptr & (NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES))) + return 0; + } + + return 1; +} + +static int tegra_dp_lt_adjust(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], + u32 pc[4], u8 pc_supported, + const struct tegra_dp_link_config *cfg) +{ + size_t cnt; + u8 data_ptr; + u32 n_lanes = cfg->lane_count; + int ret; + + for (cnt = 0; cnt < n_lanes / 2; cnt++) { + ret = tegra_dc_dp_dpcd_read(dp, DP_ADJUST_REQUEST_LANE0_1 + cnt, + &data_ptr); + if (ret) + return ret; + pe[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_PE_MASK) >> + NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT; + vs[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_DC_MASK) >> + NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT; + pe[1 + 2 * cnt] = + (data_ptr & NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK) >> + NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT; + vs[1 + 2 * cnt] = + (data_ptr & NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK) >> + NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT; + } + if (pc_supported) { + ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_ADJUST_REQ_POST_CURSOR2, + &data_ptr); + if (ret) + return ret; + for (cnt = 0; cnt < n_lanes; cnt++) { + pc[cnt] = (data_ptr >> + NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(cnt)) & + NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK; + } + } + + return 0; +} + +static void tegra_dp_wait_aux_training(struct tegra_dp_priv *dp, + bool is_clk_recovery, + const struct tegra_dp_link_config *cfg) +{ + if (!cfg->aux_rd_interval) + udelay(is_clk_recovery ? 200 : 500); + else + mdelay(cfg->aux_rd_interval * 4); +} + +static void tegra_dp_tpg(struct tegra_dp_priv *dp, u32 tp, u32 n_lanes, + const struct tegra_dp_link_config *cfg) +{ + u8 data = (tp == training_pattern_disabled) + ? (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F) + : (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T); + + tegra_dc_sor_set_dp_linkctl(dp->sor, 1, tp, cfg); + tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, data); +} + +static int tegra_dp_link_config(struct tegra_dp_priv *dp, + const struct tegra_dp_link_config *link_cfg) +{ + u8 dpcd_data; + u32 retry; + int ret; + + if (link_cfg->lane_count == 0) { + debug("dp: error: lane count is 0. Can not set link config.\n"); + return -ENOLINK; + } + + /* Set power state if it is not in normal level */ + ret = tegra_dc_dp_dpcd_read(dp, DP_SET_POWER, &dpcd_data); + if (ret) + return ret; + + if (dpcd_data == DP_SET_POWER_D3) { + dpcd_data = DP_SET_POWER_D0; + + /* DP spec requires 3 retries */ + for (retry = 3; retry > 0; --retry) { + ret = tegra_dc_dp_dpcd_write(dp, DP_SET_POWER, + dpcd_data); + if (!ret) + break; + if (retry == 1) { + debug("dp: Failed to set DP panel power\n"); + return ret; + } + } + } + + /* Enable ASSR if possible */ + if (link_cfg->alt_scramber_reset_cap) { + ret = tegra_dc_dp_set_assr(dp, dp->sor, 1); + if (ret) + return ret; + } + + ret = tegra_dp_set_link_bandwidth(dp, dp->sor, link_cfg->link_bw); + if (ret) { + debug("dp: Failed to set link bandwidth\n"); + return ret; + } + ret = tegra_dp_set_lane_count(dp, link_cfg, dp->sor); + if (ret) { + debug("dp: Failed to set lane count\n"); + return ret; + } + tegra_dc_sor_set_dp_linkctl(dp->sor, 1, training_pattern_none, + link_cfg); + + return 0; +} + +static int tegra_dp_lower_link_config(struct tegra_dp_priv *dp, + const struct display_timing *timing, + struct tegra_dp_link_config *cfg) +{ + struct tegra_dp_link_config tmp_cfg; + int ret; + + tmp_cfg = *cfg; + cfg->is_valid = 0; + + ret = _tegra_dp_lower_link_config(dp, cfg); + if (!ret) + ret = tegra_dc_dp_calc_config(dp, timing, cfg); + if (!ret) + ret = tegra_dp_link_config(dp, cfg); + if (ret) + goto fail; + + return 0; + +fail: + *cfg = tmp_cfg; + tegra_dp_link_config(dp, &tmp_cfg); + return ret; +} + +static int tegra_dp_lt_config(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], + u32 pc[4], const struct tegra_dp_link_config *cfg) +{ + struct tegra_dc_sor_data *sor = dp->sor; + u32 n_lanes = cfg->lane_count; + u8 pc_supported = cfg->tps3_supported; + u32 cnt; + u32 val; + + for (cnt = 0; cnt < n_lanes; cnt++) { + u32 mask = 0; + u32 pe_reg, vs_reg, pc_reg; + u32 shift = 0; + + switch (cnt) { + case 0: + mask = PR_LANE2_DP_LANE0_MASK; + shift = PR_LANE2_DP_LANE0_SHIFT; + break; + case 1: + mask = PR_LANE1_DP_LANE1_MASK; + shift = PR_LANE1_DP_LANE1_SHIFT; + break; + case 2: + mask = PR_LANE0_DP_LANE2_MASK; + shift = PR_LANE0_DP_LANE2_SHIFT; + break; + case 3: + mask = PR_LANE3_DP_LANE3_MASK; + shift = PR_LANE3_DP_LANE3_SHIFT; + break; + default: + debug("dp: incorrect lane cnt\n"); + return -EINVAL; + } + + pe_reg = tegra_dp_pe_regs[pc[cnt]][vs[cnt]][pe[cnt]]; + vs_reg = tegra_dp_vs_regs[pc[cnt]][vs[cnt]][pe[cnt]]; + pc_reg = tegra_dp_pc_regs[pc[cnt]][vs[cnt]][pe[cnt]]; + + tegra_dp_set_pe_vs_pc(sor, mask, pe_reg << shift, + vs_reg << shift, pc_reg << shift, + pc_supported); + } + + tegra_dp_disable_tx_pu(dp->sor); + udelay(20); + + for (cnt = 0; cnt < n_lanes; cnt++) { + u32 max_vs_flag = tegra_dp_is_max_vs(pe[cnt], vs[cnt]); + u32 max_pe_flag = tegra_dp_is_max_pe(pe[cnt], vs[cnt]); + + val = (vs[cnt] << NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT) | + (max_vs_flag ? + NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T : + NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F) | + (pe[cnt] << NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT) | + (max_pe_flag ? + NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T : + NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F); + tegra_dc_dp_dpcd_write(dp, (DP_TRAINING_LANE0_SET + cnt), val); + } + + if (pc_supported) { + for (cnt = 0; cnt < n_lanes / 2; cnt++) { + u32 max_pc_flag0 = tegra_dp_is_max_pc(pc[cnt]); + u32 max_pc_flag1 = tegra_dp_is_max_pc(pc[cnt + 1]); + val = (pc[cnt] << NV_DPCD_LANEX_SET2_PC2_SHIFT) | + (max_pc_flag0 ? + NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T : + NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F) | + (pc[cnt + 1] << + NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT) | + (max_pc_flag1 ? + NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T : + NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F); + tegra_dc_dp_dpcd_write(dp, + NV_DPCD_TRAINING_LANE0_1_SET2 + + cnt, val); + } + } + + return 0; +} + +static int _tegra_dp_channel_eq(struct tegra_dp_priv *dp, u32 pe[4], + u32 vs[4], u32 pc[4], u8 pc_supported, + u32 n_lanes, + const struct tegra_dp_link_config *cfg) +{ + u32 retry_cnt; + + for (retry_cnt = 0; retry_cnt < 4; retry_cnt++) { + int ret; + + if (retry_cnt) { + ret = tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported, + cfg); + if (ret) + return ret; + tegra_dp_lt_config(dp, pe, vs, pc, cfg); + } + + tegra_dp_wait_aux_training(dp, false, cfg); + + if (!tegra_dp_clock_recovery_status(dp, cfg)) { + debug("dp: CR failed in channel EQ sequence!\n"); + break; + } + + if (!tegra_dp_channel_eq_status(dp, cfg)) + return 0; + } + + return -EIO; +} + +static int tegra_dp_channel_eq(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], + u32 pc[4], + const struct tegra_dp_link_config *cfg) +{ + u32 n_lanes = cfg->lane_count; + u8 pc_supported = cfg->tps3_supported; + int ret; + u32 tp_src = training_pattern_2; + + if (pc_supported) + tp_src = training_pattern_3; + + tegra_dp_tpg(dp, tp_src, n_lanes, cfg); + + ret = _tegra_dp_channel_eq(dp, pe, vs, pc, pc_supported, n_lanes, cfg); + + tegra_dp_tpg(dp, training_pattern_disabled, n_lanes, cfg); + + return ret; +} + +static int _tegra_dp_clk_recovery(struct tegra_dp_priv *dp, u32 pe[4], + u32 vs[4], u32 pc[4], u8 pc_supported, + u32 n_lanes, + const struct tegra_dp_link_config *cfg) +{ + u32 vs_temp[4]; + u32 retry_cnt = 0; + + do { + tegra_dp_lt_config(dp, pe, vs, pc, cfg); + tegra_dp_wait_aux_training(dp, true, cfg); + + if (tegra_dp_clock_recovery_status(dp, cfg)) + return 0; + + memcpy(vs_temp, vs, sizeof(vs_temp)); + tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported, cfg); + + if (memcmp(vs_temp, vs, sizeof(vs_temp))) + retry_cnt = 0; + else + ++retry_cnt; + } while (retry_cnt < 5); + + return -EIO; +} + +static int tegra_dp_clk_recovery(struct tegra_dp_priv *dp, u32 pe[4], + u32 vs[4], u32 pc[4], + const struct tegra_dp_link_config *cfg) +{ + u32 n_lanes = cfg->lane_count; + u8 pc_supported = cfg->tps3_supported; + int err; + + tegra_dp_tpg(dp, training_pattern_1, n_lanes, cfg); + + err = _tegra_dp_clk_recovery(dp, pe, vs, pc, pc_supported, n_lanes, + cfg); + if (err < 0) + tegra_dp_tpg(dp, training_pattern_disabled, n_lanes, cfg); + + return err; +} + +static int tegra_dc_dp_full_link_training(struct tegra_dp_priv *dp, + const struct display_timing *timing, + struct tegra_dp_link_config *cfg) +{ + struct tegra_dc_sor_data *sor = dp->sor; + int err; + u32 pe[4], vs[4], pc[4]; + + tegra_sor_precharge_lanes(sor, cfg); + +retry_cr: + memset(pe, PREEMPHASIS_DISABLED, sizeof(pe)); + memset(vs, DRIVECURRENT_LEVEL0, sizeof(vs)); + memset(pc, POSTCURSOR2_LEVEL0, sizeof(pc)); + + err = tegra_dp_clk_recovery(dp, pe, vs, pc, cfg); + if (err) { + if (!tegra_dp_lower_link_config(dp, timing, cfg)) + goto retry_cr; + + debug("dp: clk recovery failed\n"); + goto fail; + } + + err = tegra_dp_channel_eq(dp, pe, vs, pc, cfg); + if (err) { + if (!tegra_dp_lower_link_config(dp, timing, cfg)) + goto retry_cr; + + debug("dp: channel equalization failed\n"); + goto fail; + } +#ifdef DEBUG + tegra_dc_dp_dump_link_cfg(dp, cfg); +#endif + return 0; + +fail: + return err; +} + +/* + * All link training functions are ported from kernel dc driver. + * See more details at drivers/video/tegra/dc/dp.c + */ +static int tegra_dc_dp_fast_link_training(struct tegra_dp_priv *dp, + const struct tegra_dp_link_config *link_cfg, + struct tegra_dc_sor_data *sor) +{ + u8 link_bw; + u8 lane_count; + u16 data16; + u32 data32; + u32 size; + u32 status; + int j; + u32 mask = 0xffff >> ((4 - link_cfg->lane_count) * 4); + + tegra_dc_sor_set_lane_parm(sor, link_cfg); + tegra_dc_dp_dpcd_write(dp, DP_MAIN_LINK_CHANNEL_CODING_SET, + DP_SET_ANSI_8B10B); + + /* Send TP1 */ + tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_1, link_cfg); + tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, + DP_TRAINING_PATTERN_1); + + for (j = 0; j < link_cfg->lane_count; ++j) + tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24); + udelay(520); + + size = sizeof(data16); + tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, + DP_LANE0_1_STATUS, (u8 *)&data16, &size, &status); + status = mask & 0x1111; + if ((data16 & status) != status) { + debug("dp: Link training error for TP1 (%#x, status %#x)\n", + data16, status); + return -EFAULT; + } + + /* enable ASSR */ + tegra_dc_dp_set_assr(dp, sor, link_cfg->scramble_ena); + tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_3, link_cfg); + + tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, + link_cfg->link_bw == 20 ? 0x23 : 0x22); + for (j = 0; j < link_cfg->lane_count; ++j) + tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24); + udelay(520); + + size = sizeof(data32); + tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, DP_LANE0_1_STATUS, + (u8 *)&data32, &size, &status); + if ((data32 & mask) != (0x7777 & mask)) { + debug("dp: Link training error for TP2/3 (0x%x)\n", data32); + return -EFAULT; + } + + tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_disabled, + link_cfg); + tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, 0); + + if (tegra_dc_dp_link_trained(dp, link_cfg)) { + tegra_dc_sor_read_link_config(sor, &link_bw, &lane_count); + debug("Fast link training failed, link bw %d, lane # %d\n", + link_bw, lane_count); + return -EFAULT; + } + + debug("Fast link training succeeded, link bw %d, lane %d\n", + link_cfg->link_bw, link_cfg->lane_count); + + return 0; +} + +static int tegra_dp_do_link_training(struct tegra_dp_priv *dp, + struct tegra_dp_link_config *link_cfg, + const struct display_timing *timing, + struct tegra_dc_sor_data *sor) +{ + u8 link_bw; + u8 lane_count; + int ret; + + if (DO_FAST_LINK_TRAINING) { + ret = tegra_dc_dp_fast_link_training(dp, link_cfg, sor); + if (ret) { + debug("dp: fast link training failed\n"); + } else { + /* + * set to a known-good drive setting if fast link + * succeeded. Ignore any error. + */ + ret = tegra_dc_sor_set_voltage_swing(dp->sor, link_cfg); + if (ret) + debug("Failed to set voltage swing\n"); + } + } else { + ret = -ENOSYS; + } + if (ret) { + /* Try full link training then */ + ret = tegra_dc_dp_full_link_training(dp, timing, link_cfg); + if (ret) { + debug("dp: full link training failed\n"); + return ret; + } + } + + /* Everything is good; double check the link config */ + tegra_dc_sor_read_link_config(sor, &link_bw, &lane_count); + + if ((link_cfg->link_bw == link_bw) && + (link_cfg->lane_count == lane_count)) + return 0; + else + return -EFAULT; +} + +static int tegra_dc_dp_explore_link_cfg(struct tegra_dp_priv *dp, + struct tegra_dp_link_config *link_cfg, + struct tegra_dc_sor_data *sor, + const struct display_timing *timing) +{ + struct tegra_dp_link_config temp_cfg; + + if (!timing->pixelclock.typ || !timing->hactive.typ || + !timing->vactive.typ) { + debug("dp: error mode configuration"); + return -EINVAL; + } + if (!link_cfg->max_link_bw || !link_cfg->max_lane_count) { + debug("dp: error link configuration"); + return -EINVAL; + } + + link_cfg->is_valid = 0; + + memcpy(&temp_cfg, link_cfg, sizeof(temp_cfg)); + + temp_cfg.link_bw = temp_cfg.max_link_bw; + temp_cfg.lane_count = temp_cfg.max_lane_count; + + /* + * set to max link config + */ + if ((!tegra_dc_dp_calc_config(dp, timing, &temp_cfg)) && + (!tegra_dp_link_config(dp, &temp_cfg)) && + (!tegra_dp_do_link_training(dp, &temp_cfg, timing, sor))) + /* the max link cfg is doable */ + memcpy(link_cfg, &temp_cfg, sizeof(temp_cfg)); + + return link_cfg->is_valid ? 0 : -EFAULT; +} + +static int tegra_dp_hpd_plug(struct tegra_dp_priv *dp) +{ + const int vdd_to_hpd_delay_ms = 200; + u32 val; + ulong start; + + start = get_timer(0); + do { + val = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); + if (val & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED) + return 0; + udelay(100); + } while (get_timer(start) < vdd_to_hpd_delay_ms); + + return -EIO; +} + +static int tegra_dc_dp_sink_out_of_sync(struct tegra_dp_priv *dp, u32 delay_ms) +{ + u8 dpcd_data; + int out_of_sync; + int ret; + + debug("%s: delay=%d\n", __func__, delay_ms); + mdelay(delay_ms); + ret = tegra_dc_dp_dpcd_read(dp, DP_SINK_STATUS, &dpcd_data); + if (ret) + return ret; + + out_of_sync = !(dpcd_data & DP_SINK_STATUS_PORT0_IN_SYNC); + if (out_of_sync) + debug("SINK receive port 0 out of sync, data=%x\n", dpcd_data); + else + debug("SINK is in synchronization\n"); + + return out_of_sync; +} + +static int tegra_dc_dp_check_sink(struct tegra_dp_priv *dp, + struct tegra_dp_link_config *link_cfg, + const struct display_timing *timing) +{ + const int max_retry = 5; + int delay_frame; + int retries; + + /* + * DP TCON may skip some main stream frames, thus we need to wait + * some delay before reading the DPCD SINK STATUS register, starting + * from 5 + */ + delay_frame = 5; + + retries = max_retry; + do { + int ret; + + if (!tegra_dc_dp_sink_out_of_sync(dp, link_cfg->frame_in_ms * + delay_frame)) + return 0; + + debug("%s: retries left %d\n", __func__, retries); + if (!retries--) { + printf("DP: Out of sync after %d retries\n", max_retry); + return -EIO; + } + ret = tegra_dc_sor_detach(dp->sor); + if (ret) + return ret; + if (tegra_dc_dp_explore_link_cfg(dp, link_cfg, dp->sor, + timing)) { + debug("dp: %s: error to configure link\n", __func__); + continue; + } + + tegra_dc_sor_set_power_state(dp->sor, 1); + tegra_dc_sor_attach(dp->sor, link_cfg, timing); + + /* Increase delay_frame for next try in case the sink is + skipping more frames */ + delay_frame += 10; + } while (1); +} + +int tegra_dp_enable(struct udevice *dev, int panel_bpp, + const struct display_timing *timing) +{ + struct tegra_dp_priv *priv = dev_get_priv(dev); + struct tegra_dp_link_config slink_cfg, *link_cfg = &slink_cfg; + struct tegra_dc_sor_data *sor; + int data; + int retry; + int ret; + + memset(link_cfg, '\0', sizeof(*link_cfg)); + link_cfg->is_valid = 0; + link_cfg->scramble_ena = 1; + + tegra_dc_dpaux_enable(priv); + + if (tegra_dp_hpd_plug(priv) < 0) { + debug("dp: hpd plug failed\n"); + return -EIO; + } + + link_cfg->bits_per_pixel = panel_bpp; + if (tegra_dc_dp_init_max_link_cfg(timing, priv, link_cfg)) { + debug("dp: failed to init link configuration\n"); + return -ENOLINK; + } + + ret = tegra_dc_sor_init(&sor); + if (ret) + return ret; + priv->sor = sor; + ret = tegra_dc_sor_enable_dp(sor, link_cfg); + if (ret) + return ret; + + tegra_dc_sor_set_panel_power(sor, 1); + + /* Write power on to DPCD */ + data = DP_SET_POWER_D0; + retry = 0; + do { + ret = tegra_dc_dp_dpcd_write(priv, DP_SET_POWER, data); + } while ((retry++ < DP_POWER_ON_MAX_TRIES) && ret); + + if (ret || retry >= DP_POWER_ON_MAX_TRIES) { + debug("dp: failed to power on panel (0x%x)\n", ret); + return -ENETUNREACH; + goto error_enable; + } + + /* Confirm DP plugging status */ + if (!(tegra_dpaux_readl(priv, DPAUX_DP_AUXSTAT) & + DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) { + debug("dp: could not detect HPD\n"); + return -ENXIO; + } + + /* Check DP version */ + if (tegra_dc_dp_dpcd_read(priv, DP_DPCD_REV, &priv->revision)) { + debug("dp: failed to read the revision number from sink\n"); + return -EIO; + } + + if (tegra_dc_dp_explore_link_cfg(priv, link_cfg, sor, timing)) { + debug("dp: error configuring link\n"); + return -ENOMEDIUM; + } + + tegra_dc_sor_set_power_state(sor, 1); + ret = tegra_dc_sor_attach(sor, link_cfg, timing); + if (ret && ret != -EEXIST) + return ret; + + /* + * This takes a long time, but can apparently resolve a failure to + * bring up the display correctly. + */ + if (0) { + ret = tegra_dc_dp_check_sink(priv, link_cfg, timing); + if (ret) + return ret; + } + + /* Power down the unused lanes to save power - a few hundred mW */ + tegra_dc_sor_power_down_unused_lanes(sor, link_cfg); + + priv->enabled = true; +error_enable: + return 0; +} + +static int tegra_dp_ofdata_to_platdata(struct udevice *dev) +{ + struct tegra_dp_plat *plat = dev_get_platdata(dev); + const void *blob = gd->fdt_blob; + + plat->base = fdtdec_get_addr(blob, dev->of_offset, "reg"); + + return 0; +} + +static int tegra_dp_read_edid(struct udevice *dev, u8 *buf, int buf_size) +{ + struct tegra_dp_priv *priv = dev_get_priv(dev); + const int tegra_edid_i2c_address = 0x50; + u32 aux_stat = 0; + + tegra_dc_dpaux_enable(priv); + + return tegra_dc_i2c_aux_read(priv, tegra_edid_i2c_address, 0, buf, + buf_size, &aux_stat); +} + +static const struct dm_display_port_ops dp_tegra_ops = { + .read_edid = tegra_dp_read_edid, + .enable = tegra_dp_enable, +}; + +static int dp_tegra_probe(struct udevice *dev) +{ + struct tegra_dp_plat *plat = dev_get_platdata(dev); + struct tegra_dp_priv *priv = dev_get_priv(dev); + + priv->regs = (struct dpaux_ctlr *)plat->base; + priv->enabled = false; + + return 0; +} + +static const struct udevice_id tegra_dp_ids[] = { + { .compatible = "nvidia,tegra124-dpaux" }, + { } +}; + +U_BOOT_DRIVER(dp_tegra) = { + .name = "dpaux_tegra", + .id = UCLASS_DISPLAY_PORT, + .of_match = tegra_dp_ids, + .ofdata_to_platdata = tegra_dp_ofdata_to_platdata, + .probe = dp_tegra_probe, + .ops = &dp_tegra_ops, + .priv_auto_alloc_size = sizeof(struct tegra_dp_priv), + .platdata_auto_alloc_size = sizeof(struct tegra_dp_plat), +}; diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c new file mode 100644 index 0000000..aa3d80c --- /dev/null +++ b/drivers/video/tegra124/sor.c @@ -0,0 +1,1024 @@ +/* + * Copyright (c) 2011-2013, NVIDIA Corporation. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch-tegra/dc.h> +#include "displayport.h" +#include "sor.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define DEBUG_SOR 0 + +#define APBDEV_PMC_DPD_SAMPLE 0x20 +#define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE 0 +#define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE 1 +#define APBDEV_PMC_SEL_DPD_TIM 0x1c8 +#define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT 0x7f +#define APBDEV_PMC_IO_DPD2_REQ 0x1c0 +#define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT 25 +#define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF (0 << 25) +#define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON (1 << 25) +#define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT 30 +#define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK (0x3 << 30) +#define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE (0 << 30) +#define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF (1 << 30) +#define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON (2 << 30) +#define APBDEV_PMC_IO_DPD2_STATUS 0x1c4 +#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT 25 +#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF (0 << 25) +#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON (1 << 25) + +static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) +{ + return readl((u32 *)sor->base + reg); +} + +static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg, + u32 val) +{ + writel(val, (u32 *)sor->base + reg); +} + +static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor, + u32 reg, u32 mask, u32 val) +{ + u32 reg_val = tegra_sor_readl(sor, reg); + reg_val &= ~mask; + reg_val |= val; + tegra_sor_writel(sor, reg, reg_val); +} + +void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor) +{ + tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), + DP_PADCTL_TX_PU_MASK, DP_PADCTL_TX_PU_DISABLE); +} + +void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, u32 pe_reg, + u32 vs_reg, u32 pc_reg, u8 pc_supported) +{ + tegra_sor_write_field(sor, PR(sor->portnum), mask, pe_reg); + tegra_sor_write_field(sor, DC(sor->portnum), mask, vs_reg); + if (pc_supported) { + tegra_sor_write_field(sor, POSTCURSOR(sor->portnum), mask, + pc_reg); + } +} + +static int tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg, + u32 mask, u32 exp_val, + int poll_interval_us, int timeout_ms) +{ + u32 reg_val = 0; + ulong start; + + start = get_timer(0); + do { + reg_val = tegra_sor_readl(sor, reg); + if (((reg_val & mask) == exp_val)) + return 0; + udelay(poll_interval_us); + } while (get_timer(start) < timeout_ms); + + debug("sor_poll_register 0x%x: timeout, (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n", + reg, reg_val, mask, exp_val); + + return -ETIMEDOUT; +} + +int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd) +{ + u32 reg_val; + u32 orig_val; + + orig_val = tegra_sor_readl(sor, PWR); + + reg_val = pu_pd ? PWR_NORMAL_STATE_PU : + PWR_NORMAL_STATE_PD; /* normal state only */ + + if (reg_val == orig_val) + return 0; /* No update needed */ + + reg_val |= PWR_SETTING_NEW_TRIGGER; + tegra_sor_writel(sor, PWR, reg_val); + + /* Poll to confirm it is done */ + if (tegra_dc_sor_poll_register(sor, PWR, + PWR_SETTING_NEW_DEFAULT_MASK, + PWR_SETTING_NEW_DONE, + 100, TEGRA_SOR_TIMEOUT_MS)) { + debug("dc timeout waiting for SOR_PWR = NEW_DONE\n"); + return -EFAULT; + } + + return 0; +} + +void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena, + u8 training_pattern, + const struct tegra_dp_link_config *link_cfg) +{ + u32 reg_val; + + reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); + + if (ena) + reg_val |= DP_LINKCTL_ENABLE_YES; + else + reg_val &= DP_LINKCTL_ENABLE_NO; + + reg_val &= ~DP_LINKCTL_TUSIZE_MASK; + reg_val |= (link_cfg->tu_size << DP_LINKCTL_TUSIZE_SHIFT); + + if (link_cfg->enhanced_framing) + reg_val |= DP_LINKCTL_ENHANCEDFRAME_ENABLE; + + tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val); + + switch (training_pattern) { + case training_pattern_1: + tegra_sor_writel(sor, DP_TPG, 0x41414141); + break; + case training_pattern_2: + case training_pattern_3: + reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ? + 0x43434343 : 0x42424242; + tegra_sor_writel(sor, DP_TPG, reg_val); + break; + default: + tegra_sor_writel(sor, DP_TPG, 0x50505050); + break; + } +} + +static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor, + int pu, int is_lvds) +{ + u32 reg_val; + + /* SOR lane sequencer */ + if (pu) { + reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER | + LANE_SEQ_CTL_SEQUENCE_DOWN | + LANE_SEQ_CTL_NEW_POWER_STATE_PU; + } else { + reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER | + LANE_SEQ_CTL_SEQUENCE_UP | + LANE_SEQ_CTL_NEW_POWER_STATE_PD; + } + + if (is_lvds) + reg_val |= 15 << LANE_SEQ_CTL_DELAY_SHIFT; + else + reg_val |= 1 << LANE_SEQ_CTL_DELAY_SHIFT; + + tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val); + + if (tegra_dc_sor_poll_register(sor, LANE_SEQ_CTL, + LANE_SEQ_CTL_SETTING_MASK, + LANE_SEQ_CTL_SETTING_NEW_DONE, + 100, TEGRA_SOR_TIMEOUT_MS)) { + debug("dp: timeout while waiting for SOR lane sequencer to power down lanes\n"); + return -1; + } + + return 0; +} + +static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor, + u32 lane_count, int pu) +{ + u32 reg_val; + + reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); + + if (pu) { + switch (lane_count) { + case 4: + reg_val |= (DP_PADCTL_PD_TXD_3_NO | + DP_PADCTL_PD_TXD_2_NO); + /* fall through */ + case 2: + reg_val |= DP_PADCTL_PD_TXD_1_NO; + case 1: + reg_val |= DP_PADCTL_PD_TXD_0_NO; + break; + default: + debug("dp: invalid lane number %d\n", lane_count); + return -1; + } + + tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); + tegra_dc_sor_set_lane_count(sor, lane_count); + } + + return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0); +} + +void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor, + int power_up) +{ + u32 reg_val; + + reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); + + if (power_up) + reg_val |= DP_PADCTL_PAD_CAL_PD_POWERUP; + else + reg_val &= ~DP_PADCTL_PAD_CAL_PD_POWERUP; + + tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); +} + +static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div, + u32 pwm_dutycycle) +{ + tegra_sor_writel(sor, PWM_DIV, pwm_div); + tegra_sor_writel(sor, PWM_CTL, + (pwm_dutycycle & PWM_CTL_DUTY_CYCLE_MASK) | + PWM_CTL_SETTING_NEW_TRIGGER); + + if (tegra_dc_sor_poll_register(sor, PWM_CTL, + PWM_CTL_SETTING_NEW_SHIFT, + PWM_CTL_SETTING_NEW_DONE, + 100, TEGRA_SOR_TIMEOUT_MS)) { + debug("dp: timeout while waiting for SOR PWM setting\n"); + } +} + +static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *link_cfg) +{ + u32 reg_val; + + tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw); + + tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg); + reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum)); + reg_val &= ~DP_CONFIG_WATERMARK_MASK; + reg_val |= link_cfg->watermark; + reg_val &= ~DP_CONFIG_ACTIVESYM_COUNT_MASK; + reg_val |= (link_cfg->active_count << + DP_CONFIG_ACTIVESYM_COUNT_SHIFT); + reg_val &= ~DP_CONFIG_ACTIVESYM_FRAC_MASK; + reg_val |= (link_cfg->active_frac << + DP_CONFIG_ACTIVESYM_FRAC_SHIFT); + if (link_cfg->activepolarity) + reg_val |= DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE; + else + reg_val &= ~DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE; + reg_val |= (DP_CONFIG_ACTIVESYM_CNTL_ENABLE | + DP_CONFIG_RD_RESET_VAL_NEGATIVE); + + tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val); + + /* program h/vblank sym */ + tegra_sor_write_field(sor, DP_AUDIO_HBLANK_SYMBOLS, + DP_AUDIO_HBLANK_SYMBOLS_MASK, + link_cfg->hblank_sym); + + tegra_sor_write_field(sor, DP_AUDIO_VBLANK_SYMBOLS, + DP_AUDIO_VBLANK_SYMBOLS_MASK, + link_cfg->vblank_sym); +} + +static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor) +{ + tegra_sor_writel(sor, SUPER_STATE0, 0); + tegra_sor_writel(sor, SUPER_STATE0, 1); + tegra_sor_writel(sor, SUPER_STATE0, 0); +} + +static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor) +{ + tegra_sor_writel(sor, STATE0, 0); + tegra_sor_writel(sor, STATE0, 1); + tegra_sor_writel(sor, STATE0, 0); +} + +static int tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up) +{ + u32 reg_val; + void *pmc_base = sor->pmc_base; + + if (up) { + writel(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE, + pmc_base + APBDEV_PMC_DPD_SAMPLE); + writel(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM); + } + + reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_REQ); + reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON || + APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK); + + reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON | + APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF : + APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF | + APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON; + + writel(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ); + + /* Polling */ + u32 temp = 10 * 1000; + do { + udelay(20); + reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_STATUS); + if (temp > 20) + temp -= 20; + else + break; + } while ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0); + + if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0) { + debug("PMC_IO_DPD2 polling failed (0x%x)\n", reg_val); + return -EIO; + } + + if (up) { + writel(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE, + pmc_base + APBDEV_PMC_DPD_SAMPLE); + } + + return 0; +} + +void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int) +{ + u32 reg_val; + + reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum)); + if (is_int) + reg_val |= DP_SPARE_PANEL_INTERNAL; + else + reg_val &= ~DP_SPARE_PANEL_INTERNAL; + + reg_val |= DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK | + DP_SPARE_SEQ_ENABLE_YES; + tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val); +} + +void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw, + u8 *lane_count) +{ + u32 reg_val; + + reg_val = tegra_sor_readl(sor, CLK_CNTRL); + *link_bw = (reg_val & CLK_CNTRL_DP_LINK_SPEED_MASK) + >> CLK_CNTRL_DP_LINK_SPEED_SHIFT; + reg_val = tegra_sor_readl(sor, + DP_LINKCTL(sor->portnum)); + + switch (reg_val & DP_LINKCTL_LANECOUNT_MASK) { + case DP_LINKCTL_LANECOUNT_ZERO: + *lane_count = 0; + break; + case DP_LINKCTL_LANECOUNT_ONE: + *lane_count = 1; + break; + case DP_LINKCTL_LANECOUNT_TWO: + *lane_count = 2; + break; + case DP_LINKCTL_LANECOUNT_FOUR: + *lane_count = 4; + break; + default: + printf("Unknown lane count\n"); + } +} + +void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw) +{ + tegra_sor_write_field(sor, CLK_CNTRL, + CLK_CNTRL_DP_LINK_SPEED_MASK, + link_bw << CLK_CNTRL_DP_LINK_SPEED_SHIFT); +} + +void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count) +{ + u32 reg_val; + + reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); + reg_val &= ~DP_LINKCTL_LANECOUNT_MASK; + switch (lane_count) { + case 0: + break; + case 1: + reg_val |= DP_LINKCTL_LANECOUNT_ONE; + break; + case 2: + reg_val |= DP_LINKCTL_LANECOUNT_TWO; + break; + case 4: + reg_val |= DP_LINKCTL_LANECOUNT_FOUR; + break; + default: + /* 0 should be handled earlier. */ + printf("dp: Invalid lane count %d\n", lane_count); + return; + } + tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val); +} + +/* + * The SOR power sequencer does not work for t124 so SW has to + * go through the power sequence manually + * Power up steps from spec: + * STEP PDPORT PDPLL PDBG PLLVCOD PLLCAPD E_DPD PDCAL + * 1 1 1 1 1 1 1 1 + * 2 1 1 1 1 1 0 1 + * 3 1 1 0 1 1 0 1 + * 4 1 0 0 0 0 0 1 + * 5 0 0 0 0 0 0 1 + */ +static int tegra_dc_sor_power_up(struct tegra_dc_sor_data *sor, int is_lvds) +{ + int ret; + + if (sor->power_is_up) + return 0; + + /* Set link bw */ + tegra_dc_sor_set_link_bandwidth(sor, is_lvds ? + CLK_CNTRL_DP_LINK_SPEED_LVDS : + CLK_CNTRL_DP_LINK_SPEED_G1_62); + + /* step 1 */ + tegra_sor_write_field(sor, PLL2, + PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */ + PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */ + PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */ + PLL2_AUX7_PORT_POWERDOWN_ENABLE | + PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE | + PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE); + tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */ + PLL0_VCOPD_MASK, /* PLLVCOPD */ + PLL0_PWR_OFF | PLL0_VCOPD_ASSERT); + tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), + DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */ + DP_PADCTL_PAD_CAL_PD_POWERDOWN); + + /* step 2 */ + ret = tegra_dc_sor_io_set_dpd(sor, 1); + if (ret) + return ret; + udelay(15); + + /* step 3 */ + tegra_sor_write_field(sor, PLL2, + PLL2_AUX6_BANDGAP_POWERDOWN_MASK, + PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE); + udelay(25); + + /* step 4 */ + tegra_sor_write_field(sor, PLL0, + PLL0_PWR_MASK | /* PDPLL */ + PLL0_VCOPD_MASK, /* PLLVCOPD */ + PLL0_PWR_ON | PLL0_VCOPD_RESCIND); + /* PLLCAPD */ + tegra_sor_write_field(sor, PLL2, + PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, + PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE); + udelay(225); + + /* step 5 PDPORT */ + tegra_sor_write_field(sor, PLL2, + PLL2_AUX7_PORT_POWERDOWN_MASK, + PLL2_AUX7_PORT_POWERDOWN_DISABLE); + + sor->power_is_up = 1; + + return 0; +} + +#if DEBUG_SOR +static void dump_sor_reg(struct tegra_dc_sor_data *sor) +{ +#define DUMP_REG(a) printk(BIOS_INFO, "%-32s %03x %08x\n", \ + #a, a, tegra_sor_readl(sor, a)); + + DUMP_REG(SUPER_STATE0); + DUMP_REG(SUPER_STATE1); + DUMP_REG(STATE0); + DUMP_REG(STATE1); + DUMP_REG(NV_HEAD_STATE0(0)); + DUMP_REG(NV_HEAD_STATE0(1)); + DUMP_REG(NV_HEAD_STATE1(0)); + DUMP_REG(NV_HEAD_STATE1(1)); + DUMP_REG(NV_HEAD_STATE2(0)); + DUMP_REG(NV_HEAD_STATE2(1)); + DUMP_REG(NV_HEAD_STATE3(0)); + DUMP_REG(NV_HEAD_STATE3(1)); + DUMP_REG(NV_HEAD_STATE4(0)); + DUMP_REG(NV_HEAD_STATE4(1)); + DUMP_REG(NV_HEAD_STATE5(0)); + DUMP_REG(NV_HEAD_STATE5(1)); + DUMP_REG(CRC_CNTRL); + DUMP_REG(CLK_CNTRL); + DUMP_REG(CAP); + DUMP_REG(PWR); + DUMP_REG(TEST); + DUMP_REG(PLL0); + DUMP_REG(PLL1); + DUMP_REG(PLL2); + DUMP_REG(PLL3); + DUMP_REG(CSTM); + DUMP_REG(LVDS); + DUMP_REG(CRCA); + DUMP_REG(CRCB); + DUMP_REG(SEQ_CTL); + DUMP_REG(LANE_SEQ_CTL); + DUMP_REG(SEQ_INST(0)); + DUMP_REG(SEQ_INST(1)); + DUMP_REG(SEQ_INST(2)); + DUMP_REG(SEQ_INST(3)); + DUMP_REG(SEQ_INST(4)); + DUMP_REG(SEQ_INST(5)); + DUMP_REG(SEQ_INST(6)); + DUMP_REG(SEQ_INST(7)); + DUMP_REG(SEQ_INST(8)); + DUMP_REG(PWM_DIV); + DUMP_REG(PWM_CTL); + DUMP_REG(MSCHECK); + DUMP_REG(XBAR_CTRL); + DUMP_REG(DP_LINKCTL(0)); + DUMP_REG(DP_LINKCTL(1)); + DUMP_REG(DC(0)); + DUMP_REG(DC(1)); + DUMP_REG(LANE_DRIVE_CURRENT(0)); + DUMP_REG(PR(0)); + DUMP_REG(LANE4_PREEMPHASIS(0)); + DUMP_REG(POSTCURSOR(0)); + DUMP_REG(DP_CONFIG(0)); + DUMP_REG(DP_CONFIG(1)); + DUMP_REG(DP_MN(0)); + DUMP_REG(DP_MN(1)); + DUMP_REG(DP_PADCTL(0)); + DUMP_REG(DP_PADCTL(1)); + DUMP_REG(DP_DEBUG(0)); + DUMP_REG(DP_DEBUG(1)); + DUMP_REG(DP_SPARE(0)); + DUMP_REG(DP_SPARE(1)); + DUMP_REG(DP_TPG); + + return; +} +#endif + +static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor, + int is_lvds, + const struct tegra_dp_link_config *link_cfg, + const struct display_timing *timing) +{ + const int head_num = 0; + u32 reg_val = STATE1_ASY_OWNER_HEAD0 << head_num; + u32 vtotal, htotal; + u32 vsync_end, hsync_end; + u32 vblank_end, hblank_end; + u32 vblank_start, hblank_start; + + reg_val |= is_lvds ? STATE1_ASY_PROTOCOL_LVDS_CUSTOM : + STATE1_ASY_PROTOCOL_DP_A; + reg_val |= STATE1_ASY_SUBOWNER_NONE | + STATE1_ASY_CRCMODE_COMPLETE_RASTER; + + reg_val |= STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE; + reg_val |= STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE; + reg_val |= (link_cfg->bits_per_pixel > 18) ? + STATE1_ASY_PIXELDEPTH_BPP_24_444 : + STATE1_ASY_PIXELDEPTH_BPP_18_444; + + tegra_sor_writel(sor, STATE1, reg_val); + + /* + * Skipping programming NV_HEAD_STATE0, assuming: + * interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB + */ + vtotal = timing->vsync_len.typ + timing->vback_porch.typ + + timing->vactive.typ + timing->vfront_porch.typ; + htotal = timing->hsync_len.typ + timing->hback_porch.typ + + timing->hactive.typ + timing->hfront_porch.typ; + + tegra_sor_writel(sor, NV_HEAD_STATE1(head_num), + vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT | + htotal << NV_HEAD_STATE1_HTOTAL_SHIFT); + + vsync_end = timing->vsync_len.typ - 1; + hsync_end = timing->hsync_len.typ - 1; + tegra_sor_writel(sor, NV_HEAD_STATE2(head_num), + vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT | + hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT); + + vblank_end = vsync_end + timing->vback_porch.typ; + hblank_end = hsync_end + timing->hback_porch.typ; + tegra_sor_writel(sor, NV_HEAD_STATE3(head_num), + vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT | + hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT); + + vblank_start = vblank_end + timing->vactive.typ; + hblank_start = hblank_end + timing->hactive.typ; + tegra_sor_writel(sor, NV_HEAD_STATE4(head_num), + vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT | + hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT); + + /* TODO: adding interlace mode support */ + tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1); + + tegra_sor_write_field(sor, CSTM, + CSTM_ROTCLK_DEFAULT_MASK | + CSTM_LVDS_EN_ENABLE, + 2 << CSTM_ROTCLK_SHIFT | + is_lvds ? CSTM_LVDS_EN_ENABLE : + CSTM_LVDS_EN_DISABLE); + + tegra_dc_sor_config_pwm(sor, 1024, 1024); +} + +static void tegra_dc_sor_enable_dc(struct dc_ctlr *disp_ctrl) +{ + u32 reg_val = readl(&disp_ctrl->cmd.state_access); + + writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); + writel(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt); + + /* Enable DC now - otherwise pure text console may not show. */ + writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT, + &disp_ctrl->cmd.disp_cmd); + writel(reg_val, &disp_ctrl->cmd.state_access); +} + +int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *link_cfg) +{ + int ret; + + tegra_sor_write_field(sor, CLK_CNTRL, + CLK_CNTRL_DP_CLK_SEL_MASK, + CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK); + + tegra_sor_write_field(sor, PLL2, + PLL2_AUX6_BANDGAP_POWERDOWN_MASK, + PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE); + udelay(25); + + tegra_sor_write_field(sor, PLL3, + PLL3_PLLVDD_MODE_MASK, + PLL3_PLLVDD_MODE_V3_3); + tegra_sor_writel(sor, PLL0, + 0xf << PLL0_ICHPMP_SHFIT | + 0x3 << PLL0_VCOCAP_SHIFT | + PLL0_PLLREG_LEVEL_V45 | + PLL0_RESISTORSEL_EXT | + PLL0_PWR_ON | PLL0_VCOPD_RESCIND); + tegra_sor_write_field(sor, PLL2, + PLL2_AUX1_SEQ_MASK | + PLL2_AUX9_LVDSEN_OVERRIDE | + PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, + PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE | + PLL2_AUX9_LVDSEN_OVERRIDE | + PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE); + tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH | + PLL1_TMDS_TERM_ENABLE); + + if (tegra_dc_sor_poll_register(sor, PLL2, + PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, + PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE, + 100, TEGRA_SOR_TIMEOUT_MS)) { + printf("DP failed to lock PLL\n"); + return -EIO; + } + + tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK | + PLL2_AUX7_PORT_POWERDOWN_MASK, + PLL2_AUX2_OVERRIDE_POWERDOWN | + PLL2_AUX7_PORT_POWERDOWN_DISABLE); + + ret = tegra_dc_sor_power_up(sor, 0); + if (ret) { + debug("DP failed to power up\n"); + return ret; + } + + /* re-enable SOR clock */ + clock_sor_enable_edp_clock(); + + /* Power up lanes */ + tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1); + + tegra_dc_sor_set_dp_mode(sor, link_cfg); + debug("%s ret\n", __func__); + + return 0; +} + +int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *link_cfg, + const struct display_timing *timing) +{ + const void *blob = gd->fdt_blob; + struct dc_ctlr *disp_ctrl; + u32 reg_val; + int node; + + /* Use the first display controller */ + debug("%s\n", __func__); + node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC); + if (node < 0) + return -ENOENT; + disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg"); + + tegra_dc_sor_enable_dc(disp_ctrl); + tegra_dc_sor_config_panel(sor, 0, link_cfg, timing); + + writel(0x9f00, &disp_ctrl->cmd.state_ctrl); + writel(0x9f, &disp_ctrl->cmd.state_ctrl); + + writel(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | + PW4_ENABLE | PM0_ENABLE | PM1_ENABLE, + &disp_ctrl->cmd.disp_pow_ctrl); + + reg_val = tegra_sor_readl(sor, TEST); + if (reg_val & TEST_ATTACHED_TRUE) + return -EEXIST; + + tegra_sor_writel(sor, SUPER_STATE1, + SUPER_STATE1_ATTACHED_NO); + + /* + * Enable display2sor clock at least 2 cycles before DC start, + * to clear sor internal valid signal. + */ + writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); + writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); + writel(0, &disp_ctrl->disp.disp_win_opt); + writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); + + /* Attach head */ + tegra_dc_sor_update(sor); + tegra_sor_writel(sor, SUPER_STATE1, + SUPER_STATE1_ATTACHED_YES); + tegra_sor_writel(sor, SUPER_STATE1, + SUPER_STATE1_ATTACHED_YES | + SUPER_STATE1_ASY_HEAD_OP_AWAKE | + SUPER_STATE1_ASY_ORMODE_NORMAL); + tegra_dc_sor_super_update(sor); + + /* Enable dc */ + reg_val = readl(&disp_ctrl->cmd.state_access); + writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); + writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT, + &disp_ctrl->cmd.disp_cmd); + writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); + writel(reg_val, &disp_ctrl->cmd.state_access); + + if (tegra_dc_sor_poll_register(sor, TEST, + TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, + TEST_ACT_HEAD_OPMODE_AWAKE, + 100, + TEGRA_SOR_ATTACH_TIMEOUT_MS)) { + printf("dc timeout waiting for OPMOD = AWAKE\n"); + return -ETIMEDOUT; + } else { + debug("%s: sor is attached\n", __func__); + } + +#if DEBUG_SOR + dump_sor_reg(sor); +#endif + debug("%s: ret=%d\n", __func__, 0); + + return 0; +} + +void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *link_cfg) +{ + tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), + link_cfg->drive_current); + tegra_sor_writel(sor, PR(sor->portnum), + link_cfg->preemphasis); + tegra_sor_writel(sor, POSTCURSOR(sor->portnum), + link_cfg->postcursor); + tegra_sor_writel(sor, LVDS, 0); + + tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw); + tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count); + + tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), + DP_PADCTL_TX_PU_ENABLE | + DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK, + DP_PADCTL_TX_PU_ENABLE | + 2 << DP_PADCTL_TX_PU_VALUE_SHIFT); + + /* Precharge */ + tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0); + udelay(20); + + tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0); +} + +int tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *link_cfg) +{ + u32 drive_current = 0; + u32 pre_emphasis = 0; + + /* Set to a known-good pre-calibrated setting */ + switch (link_cfg->link_bw) { + case SOR_LINK_SPEED_G1_62: + case SOR_LINK_SPEED_G2_7: + drive_current = 0x13131313; + pre_emphasis = 0; + break; + case SOR_LINK_SPEED_G5_4: + debug("T124 does not support 5.4G link clock.\n"); + default: + debug("Invalid sor link bandwidth: %d\n", link_cfg->link_bw); + return -ENOLINK; + } + + tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), drive_current); + tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis); + + return 0; +} + +void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *link_cfg) +{ + u32 pad_ctrl = 0; + int err = 0; + + switch (link_cfg->lane_count) { + case 4: + pad_ctrl = DP_PADCTL_PD_TXD_0_NO | + DP_PADCTL_PD_TXD_1_NO | + DP_PADCTL_PD_TXD_2_NO | + DP_PADCTL_PD_TXD_3_NO; + break; + case 2: + pad_ctrl = DP_PADCTL_PD_TXD_0_NO | + DP_PADCTL_PD_TXD_1_NO | + DP_PADCTL_PD_TXD_2_YES | + DP_PADCTL_PD_TXD_3_YES; + break; + case 1: + pad_ctrl = DP_PADCTL_PD_TXD_0_NO | + DP_PADCTL_PD_TXD_1_YES | + DP_PADCTL_PD_TXD_2_YES | + DP_PADCTL_PD_TXD_3_YES; + break; + default: + printf("Invalid sor lane count: %u\n", link_cfg->lane_count); + return; + } + + pad_ctrl |= DP_PADCTL_PAD_CAL_PD_POWERDOWN; + tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl); + + err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0); + if (err) { + debug("Wait for lane power down failed: %d\n", err); + return; + } +} + +int tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *cfg) +{ + u32 val = 0; + + switch (cfg->lane_count) { + case 4: + val |= (DP_PADCTL_PD_TXD_3_NO | + DP_PADCTL_PD_TXD_2_NO); + /* fall through */ + case 2: + val |= DP_PADCTL_PD_TXD_1_NO; + /* fall through */ + case 1: + val |= DP_PADCTL_PD_TXD_0_NO; + break; + default: + debug("dp: invalid lane number %d\n", cfg->lane_count); + return -EINVAL; + } + + tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), + (0xf << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT), + (val << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT)); + udelay(100); + tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), + (0xf << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT), + 0); + + return 0; +} + +static void tegra_dc_sor_enable_sor(struct dc_ctlr *disp_ctrl, bool enable) +{ + u32 reg_val = readl(&disp_ctrl->disp.disp_win_opt); + + reg_val = enable ? reg_val | SOR_ENABLE : reg_val & ~SOR_ENABLE; + writel(reg_val, &disp_ctrl->disp.disp_win_opt); +} + +int tegra_dc_sor_detach(struct tegra_dc_sor_data *sor) +{ + int dc_reg_ctx[DC_REG_SAVE_SPACE]; + const void *blob = gd->fdt_blob; + struct dc_ctlr *disp_ctrl; + unsigned long dc_int_mask; + int node; + int ret; + + debug("%s\n", __func__); + /* Use the first display controller */ + node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC); + if (node < 0) { + ret = -ENOENT; + goto err; + } + disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg"); + + /* Sleep mode */ + tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP | + SUPER_STATE1_ASY_ORMODE_SAFE | + SUPER_STATE1_ATTACHED_YES); + tegra_dc_sor_super_update(sor); + + tegra_dc_sor_disable_win_short_raster(disp_ctrl, dc_reg_ctx); + + if (tegra_dc_sor_poll_register(sor, TEST, + TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, + TEST_ACT_HEAD_OPMODE_SLEEP, 100, + TEGRA_SOR_ATTACH_TIMEOUT_MS)) { + debug("dc timeout waiting for OPMOD = SLEEP\n"); + ret = -ETIMEDOUT; + goto err; + } + + tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP | + SUPER_STATE1_ASY_ORMODE_SAFE | + SUPER_STATE1_ATTACHED_NO); + + /* Mask DC interrupts during the 2 dummy frames required for detach */ + dc_int_mask = readl(&disp_ctrl->cmd.int_mask); + writel(0, &disp_ctrl->cmd.int_mask); + + /* Stop DC->SOR path */ + tegra_dc_sor_enable_sor(disp_ctrl, false); + ret = tegra_dc_sor_general_act(disp_ctrl); + if (ret) + goto err; + + /* Stop DC */ + writel(CTRL_MODE_STOP << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd); + ret = tegra_dc_sor_general_act(disp_ctrl); + if (ret) + goto err; + + tegra_dc_sor_restore_win_and_raster(disp_ctrl, dc_reg_ctx); + + writel(dc_int_mask, &disp_ctrl->cmd.int_mask); + + return 0; +err: + debug("%s: ret=%d\n", __func__, ret); + + return ret; +} + +int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp) +{ + const void *blob = gd->fdt_blob; + struct tegra_dc_sor_data *sor; + int node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR); + if (node < 0) + return -ENOENT; + sor = calloc(1, sizeof(*sor)); + if (!sor) + return -ENOMEM; + sor->base = (void *)fdtdec_get_addr(blob, node, "reg"); + + node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC); + if (node < 0) + return -ENOENT; + sor->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg"); + + sor->power_is_up = 0; + sor->portnum = 0; + *sorp = sor; + + return 0; +} diff --git a/drivers/video/tegra124/sor.h b/drivers/video/tegra124/sor.h new file mode 100644 index 0000000..dc8fd03 --- /dev/null +++ b/drivers/video/tegra124/sor.h @@ -0,0 +1,922 @@ +/* + * Copyright (c) 2011-2013, NVIDIA Corporation. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _VIDEO_TEGRA124_SOR_H +#define _VIDEO_TEGRA124_SOR_H + +#define SUPER_STATE0 0x1 +#define SUPER_STATE0_UPDATE_SHIFT 0 +#define SUPER_STATE0_UPDATE_DEFAULT_MASK 0x1 +#define SUPER_STATE1 0x2 +#define SUPER_STATE1_ATTACHED_SHIFT 3 +#define SUPER_STATE1_ATTACHED_NO (0 << 3) +#define SUPER_STATE1_ATTACHED_YES (1 << 3) +#define SUPER_STATE1_ASY_ORMODE_SHIFT 2 +#define SUPER_STATE1_ASY_ORMODE_SAFE (0 << 2) +#define SUPER_STATE1_ASY_ORMODE_NORMAL (1 << 2) +#define SUPER_STATE1_ASY_HEAD_OP_SHIFT 0 +#define SUPER_STATE1_ASY_HEAD_OP_DEFAULT_MASK 0x3 +#define SUPER_STATE1_ASY_HEAD_OP_SLEEP 0 +#define SUPER_STATE1_ASY_HEAD_OP_SNOOZE 1 +#define SUPER_STATE1_ASY_HEAD_OP_AWAKE 2 +#define STATE0 0x3 +#define STATE0_UPDATE_SHIFT 0 +#define STATE0_UPDATE_DEFAULT_MASK 0x1 +#define STATE1 0x4 +#define STATE1_ASY_PIXELDEPTH_SHIFT 17 +#define STATE1_ASY_PIXELDEPTH_DEFAULT_MASK (0xf << 17) +#define STATE1_ASY_PIXELDEPTH_BPP_16_422 (1 << 17) +#define STATE1_ASY_PIXELDEPTH_BPP_18_444 (2 << 17) +#define STATE1_ASY_PIXELDEPTH_BPP_20_422 (3 << 17) +#define STATE1_ASY_PIXELDEPTH_BPP_24_422 (4 << 17) +#define STATE1_ASY_PIXELDEPTH_BPP_24_444 (5 << 17) +#define STATE1_ASY_PIXELDEPTH_BPP_30_444 (6 << 17) +#define STATE1_ASY_PIXELDEPTH_BPP_32_422 (7 << 17) +#define STATE1_ASY_PIXELDEPTH_BPP_36_444 (8 << 17) +#define STATE1_ASY_PIXELDEPTH_BPP_48_444 (9 << 17) +#define STATE1_ASY_REPLICATE_SHIFT 15 +#define STATE1_ASY_REPLICATE_DEFAULT_MASK (3 << 15) +#define STATE1_ASY_REPLICATE_OFF (0 << 15) +#define STATE1_ASY_REPLICATE_X2 (1 << 15) +#define STATE1_ASY_REPLICATE_X4 (2 << 15) +#define STATE1_ASY_DEPOL_SHIFT 14 +#define STATE1_ASY_DEPOL_DEFAULT_MASK (1 << 14) +#define STATE1_ASY_DEPOL_POSITIVE_TRUE (0 << 14) +#define STATE1_ASY_DEPOL_NEGATIVE_TRUE (1 << 14) +#define STATE1_ASY_VSYNCPOL_SHIFT 13 +#define STATE1_ASY_VSYNCPOL_DEFAULT_MASK (1 << 13) +#define STATE1_ASY_VSYNCPOL_POSITIVE_TRUE (0 << 13) +#define STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE (1 << 13) +#define STATE1_ASY_HSYNCPOL_SHIFT 12 +#define STATE1_ASY_HSYNCPOL_DEFAULT_MASK (1 << 12) +#define STATE1_ASY_HSYNCPOL_POSITIVE_TRUE (0 << 12) +#define STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE (1 << 12) +#define STATE1_ASY_PROTOCOL_SHIFT 8 +#define STATE1_ASY_PROTOCOL_DEFAULT_MASK (0xf << 8) +#define STATE1_ASY_PROTOCOL_LVDS_CUSTOM (0 << 8) +#define STATE1_ASY_PROTOCOL_DP_A (8 << 8) +#define STATE1_ASY_PROTOCOL_DP_B (9 << 8) +#define STATE1_ASY_PROTOCOL_CUSTOM (15 << 8) +#define STATE1_ASY_CRCMODE_SHIFT 6 +#define STATE1_ASY_CRCMODE_DEFAULT_MASK (3 << 6) +#define STATE1_ASY_CRCMODE_ACTIVE_RASTER (0 << 6) +#define STATE1_ASY_CRCMODE_COMPLETE_RASTER (1 << 6) +#define STATE1_ASY_CRCMODE_NON_ACTIVE_RASTER (2 << 6) +#define STATE1_ASY_SUBOWNER_SHIFT 4 +#define STATE1_ASY_SUBOWNER_DEFAULT_MASK (3 << 4) +#define STATE1_ASY_SUBOWNER_NONE (0 << 4) +#define STATE1_ASY_SUBOWNER_SUBHEAD0 (1 << 4) +#define STATE1_ASY_SUBOWNER_SUBHEAD1 (2 << 4) +#define STATE1_ASY_SUBOWNER_BOTH (3 << 4) +#define STATE1_ASY_OWNER_SHIFT 0 +#define STATE1_ASY_OWNER_DEFAULT_MASK 0xf +#define STATE1_ASY_OWNER_NONE 0 +#define STATE1_ASY_OWNER_HEAD0 1 +#define STATE1_ASY_OWNER_HEAD1 2 +#define NV_HEAD_STATE0(i) 0x5 +#define NV_HEAD_STATE0_INTERLACED_SHIFT 4 +#define NV_HEAD_STATE0_INTERLACED_DEFAULT_MASK (3 << 4) +#define NV_HEAD_STATE0_INTERLACED_PROGRESSIVE (0 << 4) +#define NV_HEAD_STATE0_INTERLACED_INTERLACED (1 << 4) +#define NV_HEAD_STATE0_RANGECOMPRESS_SHIFT 3 +#define NV_HEAD_STATE0_RANGECOMPRESS_DEFAULT_MASK (1 << 3) +#define NV_HEAD_STATE0_RANGECOMPRESS_DISABLE (0 << 3) +#define NV_HEAD_STATE0_RANGECOMPRESS_ENABLE (1 << 3) +#define NV_HEAD_STATE0_DYNRANGE_SHIFT 2 +#define NV_HEAD_STATE0_DYNRANGE_DEFAULT_MASK (1 << 2) +#define NV_HEAD_STATE0_DYNRANGE_VESA (0 << 2) +#define NV_HEAD_STATE0_DYNRANGE_CEA (1 << 2) +#define NV_HEAD_STATE0_COLORSPACE_SHIFT 0 +#define NV_HEAD_STATE0_COLORSPACE_DEFAULT_MASK 0x3 +#define NV_HEAD_STATE0_COLORSPACE_RGB 0 +#define NV_HEAD_STATE0_COLORSPACE_YUV_601 1 +#define NV_HEAD_STATE0_COLORSPACE_YUV_709 2 +#define NV_HEAD_STATE1(i) (7 + i) +#define NV_HEAD_STATE1_VTOTAL_SHIFT 16 +#define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK (0x7fff << 16) +#define NV_HEAD_STATE1_HTOTAL_SHIFT 0 +#define NV_HEAD_STATE1_HTOTAL_DEFAULT_MASK 0x7fff +#define NV_HEAD_STATE2(i) (9 + i) +#define NV_HEAD_STATE2_VSYNC_END_SHIFT 16 +#define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK (0x7fff << 16) +#define NV_HEAD_STATE2_HSYNC_END_SHIFT 0 +#define NV_HEAD_STATE2_HSYNC_END_DEFAULT_MASK 0x7fff +#define NV_HEAD_STATE3(i) (0xb + i) +#define NV_HEAD_STATE3_VBLANK_END_SHIFT 16 +#define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK (0x7fff << 16) +#define NV_HEAD_STATE3_HBLANK_END_SHIFT 0 +#define NV_HEAD_STATE3_HBLANK_END_DEFAULT_MASK 0x7fff +#define NV_HEAD_STATE4(i) (0xd + i) +#define NV_HEAD_STATE4_VBLANK_START_SHIFT 16 +#define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK (0x7fff << 16) +#define NV_HEAD_STATE4_HBLANK_START_SHIFT 0 +#define NV_HEAD_STATE4_HBLANK_START_DEFAULT_MASK 0x7fff +#define NV_HEAD_STATE5(i) (0xf + i) +#define CRC_CNTRL 0x11 +#define CRC_CNTRL_ARM_CRC_ENABLE_SHIFT 0 +#define CRC_CNTRL_ARM_CRC_ENABLE_NO 0 +#define CRC_CNTRL_ARM_CRC_ENABLE_YES 1 +#define CRC_CNTRL_ARM_CRC_ENABLE_DIS 0 +#define CRC_CNTRL_ARM_CRC_ENABLE_EN 1 +#define CLK_CNTRL 0x13 +#define CLK_CNTRL_DP_CLK_SEL_SHIFT 0 +#define CLK_CNTRL_DP_CLK_SEL_MASK 0x3 +#define CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK 0 +#define CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK 1 +#define CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK 2 +#define CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK 3 +#define CLK_CNTRL_DP_LINK_SPEED_SHIFT 2 +#define CLK_CNTRL_DP_LINK_SPEED_MASK (0x1f << 2) +#define CLK_CNTRL_DP_LINK_SPEED_G1_62 (6 << 2) +#define CLK_CNTRL_DP_LINK_SPEED_G2_7 (10 << 2) +#define CLK_CNTRL_DP_LINK_SPEED_LVDS (7 << 2) +#define CAP 0x14 +#define CAP_DP_A_SHIFT 24 +#define CAP_DP_A_DEFAULT_MASK (1 << 24) +#define CAP_DP_A_FALSE (0 << 24) +#define CAP_DP_A_TRUE (1 << 24) +#define CAP_DP_B_SHIFT 25 +#define CAP_DP_B_DEFAULT_MASK (1 << 24) +#define CAP_DP_B_FALSE (0 << 24) +#define CAP_DP_B_TRUE (1 << 24) +#define PWR 0x15 +#define PWR_SETTING_NEW_SHIFT 31 +#define PWR_SETTING_NEW_DEFAULT_MASK (1 << 31) +#define PWR_SETTING_NEW_DONE (0 << 31) +#define PWR_SETTING_NEW_PENDING (1 << 31) +#define PWR_SETTING_NEW_TRIGGER (1 << 31) +#define PWR_MODE_SHIFT 28 +#define PWR_MODE_DEFAULT_MASK (1 << 28) +#define PWR_MODE_NORMAL (0 << 28) +#define PWR_MODE_SAFE (1 << 28) +#define PWR_HALT_DELAY_SHIFT 24 +#define PWR_HALT_DELAY_DEFAULT_MASK (1 << 24) +#define PWR_HALT_DELAY_DONE (0 << 24) +#define PWR_HALT_DELAY_ACTIVE (1 << 24) +#define PWR_SAFE_START_SHIFT 17 +#define PWR_SAFE_START_DEFAULT_MASK (1 << 17) +#define PWR_SAFE_START_NORMAL (0 << 17) +#define PWR_SAFE_START_ALT (1 << 17) +#define PWR_SAFE_STATE_SHIFT 16 +#define PWR_SAFE_STATE_DEFAULT_MASK (1 << 16) +#define PWR_SAFE_STATE_PD (0 << 16) +#define PWR_SAFE_STATE_PU (1 << 16) +#define PWR_NORMAL_START_SHIFT 1 +#define PWR_NORMAL_START_DEFAULT_MASK (1 << 1) +#define PWR_NORMAL_START_NORMAL (0 << 16) +#define PWR_NORMAL_START_ALT (1 << 16) +#define PWR_NORMAL_STATE_SHIFT 0 +#define PWR_NORMAL_STATE_DEFAULT_MASK 0x1 +#define PWR_NORMAL_STATE_PD 0 +#define PWR_NORMAL_STATE_PU 1 +#define TEST 0x16 +#define TEST_TESTMUX_SHIFT 24 +#define TEST_TESTMUX_DEFAULT_MASK (0xff << 24) +#define TEST_TESTMUX_AVSS (0 << 24) +#define TEST_TESTMUX_CLOCKIN (2 << 24) +#define TEST_TESTMUX_PLL_VOL (4 << 24) +#define TEST_TESTMUX_SLOWCLKINT (8 << 24) +#define TEST_TESTMUX_AVDD (16 << 24) +#define TEST_TESTMUX_VDDREG (32 << 24) +#define TEST_TESTMUX_REGREF_VDDREG (64 << 24) +#define TEST_TESTMUX_REGREF_AVDD (128 << 24) +#define TEST_CRC_SHIFT 23 +#define TEST_CRC_PRE_SERIALIZE (0 << 23) +#define TEST_CRC_POST_DESERIALIZE (1 << 23) +#define TEST_TPAT_SHIFT 20 +#define TEST_TPAT_DEFAULT_MASK (7 << 20) +#define TEST_TPAT_LO (0 << 20) +#define TEST_TPAT_TDAT (1 << 20) +#define TEST_TPAT_RAMP (2 << 20) +#define TEST_TPAT_WALK (3 << 20) +#define TEST_TPAT_MAXSTEP (4 << 20) +#define TEST_TPAT_MINSTEP (5 << 20) +#define TEST_DSRC_SHIFT 16 +#define TEST_DSRC_DEFAULT_MASK (3 << 16) +#define TEST_DSRC_NORMAL (0 << 16) +#define TEST_DSRC_DEBUG (1 << 16) +#define TEST_DSRC_TGEN (2 << 16) +#define TEST_HEAD_NUMBER_SHIFT 12 +#define TEST_HEAD_NUMBER_DEFAULT_MASK (3 << 12) +#define TEST_HEAD_NUMBER_NONE (0 << 12) +#define TEST_HEAD_NUMBER_HEAD0 (1 << 12) +#define TEST_HEAD_NUMBER_HEAD1 (2 << 12) +#define TEST_ATTACHED_SHIFT 10 +#define TEST_ATTACHED_DEFAULT_MASK (1 << 10) +#define TEST_ATTACHED_FALSE (0 << 10) +#define TEST_ATTACHED_TRUE (1 << 10) +#define TEST_ACT_HEAD_OPMODE_SHIFT 8 +#define TEST_ACT_HEAD_OPMODE_DEFAULT_MASK (3 << 8) +#define TEST_ACT_HEAD_OPMODE_SLEEP (0 << 8) +#define TEST_ACT_HEAD_OPMODE_SNOOZE (1 << 8) +#define TEST_ACT_HEAD_OPMODE_AWAKE (2 << 8) +#define TEST_INVD_SHIFT 6 +#define TEST_INVD_DISABLE (0 << 6) +#define TEST_INVD_ENABLE (1 << 6) +#define TEST_TEST_ENABLE_SHIFT 1 +#define TEST_TEST_ENABLE_DISABLE (0 << 1) +#define TEST_TEST_ENABLE_ENABLE (1 << 1) +#define PLL0 0x17 +#define PLL0_ICHPMP_SHFIT 24 +#define PLL0_ICHPMP_DEFAULT_MASK (0xf << 24) +#define PLL0_VCOCAP_SHIFT 8 +#define PLL0_VCOCAP_DEFAULT_MASK (0xf << 8) +#define PLL0_PLLREG_LEVEL_SHIFT 6 +#define PLL0_PLLREG_LEVEL_DEFAULT_MASK (3 << 6) +#define PLL0_PLLREG_LEVEL_V25 (0 << 6) +#define PLL0_PLLREG_LEVEL_V15 (1 << 6) +#define PLL0_PLLREG_LEVEL_V35 (2 << 6) +#define PLL0_PLLREG_LEVEL_V45 (3 << 6) +#define PLL0_PULLDOWN_SHIFT 5 +#define PLL0_PULLDOWN_DEFAULT_MASK (1 << 5) +#define PLL0_PULLDOWN_DISABLE (0 << 5) +#define PLL0_PULLDOWN_ENABLE (1 << 5) +#define PLL0_RESISTORSEL_SHIFT 4 +#define PLL0_RESISTORSEL_DEFAULT_MASK (1 << 4) +#define PLL0_RESISTORSEL_INT (0 << 4) +#define PLL0_RESISTORSEL_EXT (1 << 4) +#define PLL0_VCOPD_SHIFT 2 +#define PLL0_VCOPD_MASK (1 << 2) +#define PLL0_VCOPD_RESCIND (0 << 2) +#define PLL0_VCOPD_ASSERT (1 << 2) +#define PLL0_PWR_SHIFT 0 +#define PLL0_PWR_MASK 1 +#define PLL0_PWR_ON 0 +#define PLL0_PWR_OFF 1 +#define PLL1_TMDS_TERM_SHIFT 8 +#define PLL1_TMDS_TERM_DISABLE (0 << 8) +#define PLL1_TMDS_TERM_ENABLE (1 << 8) +#define PLL1 0x18 +#define PLL1_TERM_COMPOUT_SHIFT 15 +#define PLL1_TERM_COMPOUT_LOW (0 << 15) +#define PLL1_TERM_COMPOUT_HIGH (1 << 15) +#define PLL2 0x19 +#define PLL2_DCIR_PLL_RESET_SHIFT 0 +#define PLL2_DCIR_PLL_RESET_OVERRIDE (0 << 0) +#define PLL2_DCIR_PLL_RESET_ALLOW (1 << 0) +#define PLL2_AUX1_SHIFT 17 +#define PLL2_AUX1_SEQ_MASK (1 << 17) +#define PLL2_AUX1_SEQ_PLLCAPPD_ALLOW (0 << 17) +#define PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE (1 << 17) +#define PLL2_AUX2_SHIFT 18 +#define PLL2_AUX2_MASK (1 << 18) +#define PLL2_AUX2_OVERRIDE_POWERDOWN (0 << 18) +#define PLL2_AUX2_ALLOW_POWERDOWN (1 << 18) +#define PLL2_AUX6_SHIFT 22 +#define PLL2_AUX6_BANDGAP_POWERDOWN_MASK (1 << 22) +#define PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE (0 << 22) +#define PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE (1 << 22) +#define PLL2_AUX7_SHIFT 23 +#define PLL2_AUX7_PORT_POWERDOWN_MASK (1 << 23) +#define PLL2_AUX7_PORT_POWERDOWN_DISABLE (0 << 23) +#define PLL2_AUX7_PORT_POWERDOWN_ENABLE (1 << 23) +#define PLL2_AUX8_SHIFT 24 +#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK (1 << 24) +#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE (0 << 24) +#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE (1 << 24) +#define PLL2_AUX9_SHIFT 25 +#define PLL2_AUX9_LVDSEN_ALLOW (0 << 25) +#define PLL2_AUX9_LVDSEN_OVERRIDE (1 << 25) +#define PLL3 0x1a +#define PLL3_PLLVDD_MODE_SHIFT 13 +#define PLL3_PLLVDD_MODE_MASK (1 << 13) +#define PLL3_PLLVDD_MODE_V1_8 (0 << 13) +#define PLL3_PLLVDD_MODE_V3_3 (1 << 13) +#define CSTM 0x1b +#define CSTM_ROTDAT_SHIFT 28 +#define CSTM_ROTDAT_DEFAULT_MASK (7 << 28) +#define CSTM_ROTCLK_SHIFT 24 +#define CSTM_ROTCLK_DEFAULT_MASK (0xf << 24) +#define CSTM_LVDS_EN_SHIFT 16 +#define CSTM_LVDS_EN_DISABLE (0 << 16) +#define CSTM_LVDS_EN_ENABLE (1 << 16) +#define CSTM_LINKACTB_SHIFT 15 +#define CSTM_LINKACTB_DISABLE (0 << 15) +#define CSTM_LINKACTB_ENABLE (1 << 15) +#define CSTM_LINKACTA_SHIFT 14 +#define CSTM_LINKACTA_DISABLE (0 << 14) +#define CSTM_LINKACTA_ENABLE (1 << 14) +#define LVDS 0x1c +#define LVDS_ROTDAT_SHIFT 28 +#define LVDS_ROTDAT_DEFAULT_MASK (7 << 28) +#define LVDS_ROTDAT_RST (0 << 28) +#define LVDS_ROTCLK_SHIFT 24 +#define LVDS_ROTCLK_DEFAULT_MASK (0xf << 24) +#define LVDS_ROTCLK_RST (0 << 24) +#define LVDS_PLLDIV_SHIFT 21 +#define LVDS_PLLDIV_DEFAULT_MASK (1 << 21) +#define LVDS_PLLDIV_BY_7 (0 << 21) +#define LVDS_BALANCED_SHIFT 19 +#define LVDS_BALANCED_DEFAULT_MASK (1 << 19) +#define LVDS_BALANCED_DISABLE (0 << 19) +#define LVDS_BALANCED_ENABLE (1 << 19) +#define LVDS_NEW_MODE_SHIFT 18 +#define LVDS_NEW_MODE_DEFAULT_MASK (1 << 18) +#define LVDS_NEW_MODE_DISABLE (0 << 18) +#define LVDS_NEW_MODE_ENABLE (1 << 18) +#define LVDS_DUP_SYNC_SHIFT 17 +#define LVDS_DUP_SYNC_DEFAULT_MASK (1 << 17) +#define LVDS_DUP_SYNC_DISABLE (0 << 17) +#define LVDS_DUP_SYNC_ENABLE (1 << 17) +#define LVDS_LVDS_EN_SHIFT 16 +#define LVDS_LVDS_EN_DEFAULT_MASK (1 << 16) +#define LVDS_LVDS_EN_ENABLE (1 << 16) +#define LVDS_LINKACTB_SHIFT 15 +#define LVDS_LINKACTB_DEFAULT_MASK (1 << 15) +#define LVDS_LINKACTB_DISABLE (0 << 15) +#define LVDS_LINKACTB_ENABLE (1 << 15) +#define LVDS_LINKACTA_SHIFT 14 +#define LVDS_LINKACTA_DEFAULT_MASK (1 << 14) +#define LVDS_LINKACTA_ENABLE (1 << 14) +#define LVDS_MODE_SHIFT 12 +#define LVDS_MODE_DEFAULT_MASK (3 << 12) +#define LVDS_MODE_LVDS (0 << 12) +#define LVDS_UPPER_SHIFT 11 +#define LVDS_UPPER_DEFAULT_MASK (1 << 11) +#define LVDS_UPPER_FALSE (0 << 11) +#define LVDS_UPPER_TRUE (1 << 11) +#define LVDS_PD_TXCB_SHIFT 9 +#define LVDS_PD_TXCB_DEFAULT_MASK (1 << 9) +#define LVDS_PD_TXCB_ENABLE (0 << 9) +#define LVDS_PD_TXCB_DISABLE (1 << 9) +#define LVDS_PD_TXCA_SHIFT 8 +#define LVDS_PD_TXCA_DEFAULT_MASK (1 << 8) +#define LVDS_PD_TXCA_ENABLE (0 << 8) +#define LVDS_PD_TXDB_3_SHIFT 7 +#define LVDS_PD_TXDB_3_DEFAULT_MASK (1 << 7) +#define LVDS_PD_TXDB_3_ENABLE (0 << 7) +#define LVDS_PD_TXDB_3_DISABLE (1 << 7) +#define LVDS_PD_TXDB_2_SHIFT 6 +#define LVDS_PD_TXDB_2_DEFAULT_MASK (1 << 6) +#define LVDS_PD_TXDB_2_ENABLE (0 << 6) +#define LVDS_PD_TXDB_2_DISABLE (1 << 6) +#define LVDS_PD_TXDB_1_SHIFT 5 +#define LVDS_PD_TXDB_1_DEFAULT_MASK (1 << 5) +#define LVDS_PD_TXDB_1_ENABLE (0 << 5) +#define LVDS_PD_TXDB_1_DISABLE (1 << 5) +#define LVDS_PD_TXDB_0_SHIFT 4 +#define LVDS_PD_TXDB_0_DEFAULT_MASK (1 << 4) +#define LVDS_PD_TXDB_0_ENABLE (0 << 4) +#define LVDS_PD_TXDB_0_DISABLE (1 << 4) +#define LVDS_PD_TXDA_3_SHIFT 3 +#define LVDS_PD_TXDA_3_DEFAULT_MASK (1 << 3) +#define LVDS_PD_TXDA_3_ENABLE (0 << 3) +#define LVDS_PD_TXDA_3_DISABLE (1 << 3) +#define LVDS_PD_TXDA_2_SHIFT 2 +#define LVDS_PD_TXDA_2_DEFAULT_MASK (1 << 2) +#define LVDS_PD_TXDA_2_ENABLE (0 << 2) +#define LVDS_PD_TXDA_1_SHIFT 1 +#define LVDS_PD_TXDA_1_DEFAULT_MASK (1 << 1) +#define LVDS_PD_TXDA_1_ENABLE (0 << 1) +#define LVDS_PD_TXDA_0_SHIFT 0 +#define LVDS_PD_TXDA_0_DEFAULT_MASK 0x1 +#define LVDS_PD_TXDA_0_ENABLE 0 +#define CRCA 0x1d +#define CRCA_VALID_FALSE 0 +#define CRCA_VALID_TRUE 1 +#define CRCA_VALID_RST 1 +#define CRCB 0x1e +#define CRCB_CRC_DEFAULT_MASK 0xffffffff +#define SEQ_CTL 0x20 +#define SEQ_CTL_SWITCH_SHIFT 30 +#define SEQ_CTL_SWITCH_MASK (1 << 30) +#define SEQ_CTL_SWITCH_WAIT (0 << 30) +#define SEQ_CTL_SWITCH_FORCE (1 << 30) +#define SEQ_CTL_STATUS_SHIFT 28 +#define SEQ_CTL_STATUS_MASK (1 << 28) +#define SEQ_CTL_STATUS_STOPPED (0 << 28) +#define SEQ_CTL_STATUS_RUNNING (1 << 28) +#define SEQ_CTL_PC_SHIFT 16 +#define SEQ_CTL_PC_MASK (0xf << 16) +#define SEQ_CTL_PD_PC_ALT_SHIFT 12 +#define SEQ_CTL_PD_PC_ALT_MASK (0xf << 12) +#define SEQ_CTL_PD_PC_SHIFT 8 +#define SEQ_CTL_PD_PC_MASK (0xf << 8) +#define SEQ_CTL_PU_PC_ALT_SHIFT 4 +#define SEQ_CTL_PU_PC_ALT_MASK (0xf << 4) +#define SEQ_CTL_PU_PC_SHIFT 0 +#define SEQ_CTL_PU_PC_MASK 0xf +#define LANE_SEQ_CTL 0x21 +#define LANE_SEQ_CTL_SETTING_NEW_SHIFT 31 +#define LANE_SEQ_CTL_SETTING_MASK (1 << 31) +#define LANE_SEQ_CTL_SETTING_NEW_DONE (0 << 31) +#define LANE_SEQ_CTL_SETTING_NEW_PENDING (1 << 31) +#define LANE_SEQ_CTL_SETTING_NEW_TRIGGER (1 << 31) +#define LANE_SEQ_CTL_SEQ_STATE_SHIFT 28 +#define LANE_SEQ_CTL_SEQ_STATE_IDLE (0 << 28) +#define LANE_SEQ_CTL_SEQ_STATE_BUSY (1 << 28) +#define LANE_SEQ_CTL_SEQUENCE_SHIFT 20 +#define LANE_SEQ_CTL_SEQUENCE_UP (0 << 20) +#define LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20) +#define LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT 16 +#define LANE_SEQ_CTL_NEW_POWER_STATE_PU (0 << 16) +#define LANE_SEQ_CTL_NEW_POWER_STATE_PD (1 << 16) +#define LANE_SEQ_CTL_DELAY_SHIFT 12 +#define LANE_SEQ_CTL_DELAY_DEFAULT_MASK (0xf << 12) +#define LANE_SEQ_CTL_LANE9_STATE_SHIFT 9 +#define LANE_SEQ_CTL_LANE9_STATE_POWERUP (0 << 9) +#define LANE_SEQ_CTL_LANE9_STATE_POWERDOWN (1 << 9) +#define LANE_SEQ_CTL_LANE8_STATE_SHIFT 8 +#define LANE_SEQ_CTL_LANE8_STATE_POWERUP (0 << 8) +#define LANE_SEQ_CTL_LANE8_STATE_POWERDOWN (1 << 8) +#define LANE_SEQ_CTL_LANE7_STATE_SHIFT 7 +#define LANE_SEQ_CTL_LANE7_STATE_POWERUP (0 << 7) +#define LANE_SEQ_CTL_LANE7_STATE_POWERDOWN (1 << 7) +#define LANE_SEQ_CTL_LANE6_STATE_SHIFT 6 +#define LANE_SEQ_CTL_LANE6_STATE_POWERUP (0 << 6) +#define LANE_SEQ_CTL_LANE6_STATE_POWERDOWN (1 << 6) +#define LANE_SEQ_CTL_LANE5_STATE_SHIFT 5 +#define LANE_SEQ_CTL_LANE5_STATE_POWERUP (0 << 5) +#define LANE_SEQ_CTL_LANE5_STATE_POWERDOWN (1 << 5) +#define LANE_SEQ_CTL_LANE4_STATE_SHIFT 4 +#define LANE_SEQ_CTL_LANE4_STATE_POWERUP (0 << 4) +#define LANE_SEQ_CTL_LANE4_STATE_POWERDOWN (1 << 4) +#define LANE_SEQ_CTL_LANE3_STATE_SHIFT 3 +#define LANE_SEQ_CTL_LANE3_STATE_POWERUP (0 << 3) +#define LANE_SEQ_CTL_LANE3_STATE_POWERDOWN (1 << 3) +#define LANE_SEQ_CTL_LANE2_STATE_SHIFT 2 +#define LANE_SEQ_CTL_LANE2_STATE_POWERUP (0 << 2) +#define LANE_SEQ_CTL_LANE2_STATE_POWERDOWN (1 << 2) +#define LANE_SEQ_CTL_LANE1_STATE_SHIFT 1 +#define LANE_SEQ_CTL_LANE1_STATE_POWERUP (0 << 1) +#define LANE_SEQ_CTL_LANE1_STATE_POWERDOWN (1 << 1) +#define LANE_SEQ_CTL_LANE0_STATE_SHIFT 0 +#define LANE_SEQ_CTL_LANE0_STATE_POWERUP 0 +#define LANE_SEQ_CTL_LANE0_STATE_POWERDOWN 1 +#define SEQ_INST(i) (0x22 + i) +#define SEQ_INST_PLL_PULLDOWN_SHIFT 31 +#define SEQ_INST_PLL_PULLDOWN_DISABLE (0 << 31) +#define SEQ_INST_PLL_PULLDOWN_ENABLE (1 << 31) +#define SEQ_INST_POWERDOWN_MACRO_SHIFT 30 +#define SEQ_INST_POWERDOWN_MACRO_NORMAL (0 << 30) +#define SEQ_INST_POWERDOWN_MACRO_POWERDOWN (1 << 30) +#define SEQ_INST_ASSERT_PLL_RESET_SHIFT 29 +#define SEQ_INST_ASSERT_PLL_RESET_NORMAL (0 << 29) +#define SEQ_INST_ASSERT_PLL_RESET_RST (1 << 29) +#define SEQ_INST_BLANK_V_SHIFT 28 +#define SEQ_INST_BLANK_V_NORMAL (0 << 28) +#define SEQ_INST_BLANK_V_INACTIVE (1 << 28) +#define SEQ_INST_BLANK_H_SHIFT 27 +#define SEQ_INST_BLANK_H_NORMAL (0 << 27) +#define SEQ_INST_BLANK_H_INACTIVE (1 << 27) +#define SEQ_INST_BLANK_DE_SHIFT 26 +#define SEQ_INST_BLANK_DE_NORMAL (0 << 26) +#define SEQ_INST_BLANK_DE_INACTIVE (1 << 26) +#define SEQ_INST_BLACK_DATA_SHIFT 25 +#define SEQ_INST_BLACK_DATA_NORMAL (0 << 25) +#define SEQ_INST_BLACK_DATA_BLACK (1 << 25) +#define SEQ_INST_TRISTATE_IOS_SHIFT 24 +#define SEQ_INST_TRISTATE_IOS_ENABLE_PINS (0 << 24) +#define SEQ_INST_TRISTATE_IOS_TRISTATE (1 << 24) +#define SEQ_INST_DRIVE_PWM_OUT_LO_SHIFT 23 +#define SEQ_INST_DRIVE_PWM_OUT_LO_FALSE (0 << 23) +#define SEQ_INST_DRIVE_PWM_OUT_LO_TRUE (1 << 23) +#define SEQ_INST_PIN_B_SHIFT 22 +#define SEQ_INST_PIN_B_LOW (0 << 22) +#define SEQ_INST_PIN_B_HIGH (1 << 22) +#define SEQ_INST_PIN_A_SHIFT 21 +#define SEQ_INST_PIN_A_LOW (0 << 21) +#define SEQ_INST_PIN_A_HIGH (1 << 21) +#define SEQ_INST_SEQUENCE_SHIFT 19 +#define SEQ_INST_SEQUENCE_UP (0 << 19) +#define SEQ_INST_SEQUENCE_DOWN (1 << 19) +#define SEQ_INST_LANE_SEQ_SHIFT 18 +#define SEQ_INST_LANE_SEQ_STOP (0 << 18) +#define SEQ_INST_LANE_SEQ_RUN (1 << 18) +#define SEQ_INST_PDPORT_SHIFT 17 +#define SEQ_INST_PDPORT_NO (0 << 17) +#define SEQ_INST_PDPORT_YES (1 << 17) +#define SEQ_INST_PDPLL_SHIFT 16 +#define SEQ_INST_PDPLL_NO (0 << 16) +#define SEQ_INST_PDPLL_YES (1 << 16) +#define SEQ_INST_HALT_SHIFT 15 +#define SEQ_INST_HALT_FALSE (0 << 15) +#define SEQ_INST_HALT_TRUE (1 << 15) +#define SEQ_INST_WAIT_UNITS_SHIFT 12 +#define SEQ_INST_WAIT_UNITS_DEFAULT_MASK (3 << 12) +#define SEQ_INST_WAIT_UNITS_US (0 << 12) +#define SEQ_INST_WAIT_UNITS_MS (1 << 12) +#define SEQ_INST_WAIT_UNITS_VSYNC (2 << 12) +#define SEQ_INST_WAIT_TIME_SHIFT 0 +#define SEQ_INST_WAIT_TIME_DEFAULT_MASK 0x3ff +#define PWM_DIV 0x32 +#define PWM_DIV_DIVIDE_DEFAULT_MASK 0xffffff +#define PWM_CTL 0x33 +#define PWM_CTL_SETTING_NEW_SHIFT 31 +#define PWM_CTL_SETTING_NEW_DONE (0 << 31) +#define PWM_CTL_SETTING_NEW_PENDING (1 << 31) +#define PWM_CTL_SETTING_NEW_TRIGGER (1 << 31) +#define PWM_CTL_CLKSEL_SHIFT 30 +#define PWM_CTL_CLKSEL_PCLK (0 << 30) +#define PWM_CTL_CLKSEL_XTAL (1 << 30) +#define PWM_CTL_DUTY_CYCLE_SHIFT 0 +#define PWM_CTL_DUTY_CYCLE_MASK 0xffffff +#define MSCHECK 0x49 +#define MSCHECK_CTL_SHIFT 31 +#define MSCHECK_CTL_CLEAR (0 << 31) +#define MSCHECK_CTL_RUN (1 << 31) +#define XBAR_CTRL 0x4a +#define DP_LINKCTL(i) (0x4c + (i)) +#define DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT 31 +#define DP_LINKCTL_FORCE_IDLEPTTRN_NO (0 << 31) +#define DP_LINKCTL_FORCE_IDLEPTTRN_YES (1 << 31) +#define DP_LINKCTL_COMPLIANCEPTTRN_SHIFT 28 +#define DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN (0 << 28) +#define DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE (1 << 28) +#define DP_LINKCTL_LANECOUNT_SHIFT 16 +#define DP_LINKCTL_LANECOUNT_MASK (0x1f << 16) +#define DP_LINKCTL_LANECOUNT_ZERO (0 << 16) +#define DP_LINKCTL_LANECOUNT_ONE (1 << 16) +#define DP_LINKCTL_LANECOUNT_TWO (3 << 16) +#define DP_LINKCTL_LANECOUNT_FOUR (15 << 16) +#define DP_LINKCTL_ENHANCEDFRAME_SHIFT 14 +#define DP_LINKCTL_ENHANCEDFRAME_DISABLE (0 << 14) +#define DP_LINKCTL_ENHANCEDFRAME_ENABLE (1 << 14) +#define DP_LINKCTL_SYNCMODE_SHIFT 10 +#define DP_LINKCTL_SYNCMODE_DISABLE (0 << 10) +#define DP_LINKCTL_SYNCMODE_ENABLE (1 << 10) +#define DP_LINKCTL_TUSIZE_SHIFT 2 +#define DP_LINKCTL_TUSIZE_MASK (0x7f << 2) +#define DP_LINKCTL_ENABLE_SHIFT 0 +#define DP_LINKCTL_ENABLE_NO 0 +#define DP_LINKCTL_ENABLE_YES 1 +#define DC(i) (0x4e + (i)) +#define DC_LANE3_DP_LANE3_SHIFT 24 +#define DC_LANE3_DP_LANE3_MASK (0xff << 24) +#define DC_LANE3_DP_LANE3_P0_LEVEL0 (17 << 24) +#define DC_LANE3_DP_LANE3_P1_LEVEL0 (21 << 24) +#define DC_LANE3_DP_LANE3_P2_LEVEL0 (26 << 24) +#define DC_LANE3_DP_LANE3_P3_LEVEL0 (34 << 24) +#define DC_LANE3_DP_LANE3_P0_LEVEL1 (26 << 24) +#define DC_LANE3_DP_LANE3_P1_LEVEL1 (32 << 24) +#define DC_LANE3_DP_LANE3_P2_LEVEL1 (39 << 24) +#define DC_LANE3_DP_LANE3_P0_LEVEL2 (34 << 24) +#define DC_LANE3_DP_LANE3_P1_LEVEL2 (43 << 24) +#define DC_LANE3_DP_LANE3_P0_LEVEL3 (51 << 24) +#define DC_LANE2_DP_LANE0_SHIFT 16 +#define DC_LANE2_DP_LANE0_MASK (0xff << 16) +#define DC_LANE2_DP_LANE0_P0_LEVEL0 (17 << 16) +#define DC_LANE2_DP_LANE0_P1_LEVEL0 (21 << 16) +#define DC_LANE2_DP_LANE0_P2_LEVEL0 (26 << 16) +#define DC_LANE2_DP_LANE0_P3_LEVEL0 (34 << 16) +#define DC_LANE2_DP_LANE0_P0_LEVEL1 (26 << 16) +#define DC_LANE2_DP_LANE0_P1_LEVEL1 (32 << 16) +#define DC_LANE2_DP_LANE0_P2_LEVEL1 (39 << 16) +#define DC_LANE2_DP_LANE0_P0_LEVEL2 (34 << 16) +#define DC_LANE2_DP_LANE0_P1_LEVEL2 (43 << 16) +#define DC_LANE2_DP_LANE0_P0_LEVEL3 (51 << 16) +#define DC_LANE1_DP_LANE1_SHIFT 8 +#define DC_LANE1_DP_LANE1_MASK (0xff << 8) +#define DC_LANE1_DP_LANE1_P0_LEVEL0 (17 << 8) +#define DC_LANE1_DP_LANE1_P1_LEVEL0 (21 << 8) +#define DC_LANE1_DP_LANE1_P2_LEVEL0 (26 << 8) +#define DC_LANE1_DP_LANE1_P3_LEVEL0 (34 << 8) +#define DC_LANE1_DP_LANE1_P0_LEVEL1 (26 << 8) +#define DC_LANE1_DP_LANE1_P1_LEVEL1 (32 << 8) +#define DC_LANE1_DP_LANE1_P2_LEVEL1 (39 << 8) +#define DC_LANE1_DP_LANE1_P0_LEVEL2 (34 << 8) +#define DC_LANE1_DP_LANE1_P1_LEVEL2 (43 << 8) +#define DC_LANE1_DP_LANE1_P0_LEVEL3 (51 << 8) +#define DC_LANE0_DP_LANE2_SHIFT 0 +#define DC_LANE0_DP_LANE2_MASK 0xff +#define DC_LANE0_DP_LANE2_P0_LEVEL0 17 +#define DC_LANE0_DP_LANE2_P1_LEVEL0 21 +#define DC_LANE0_DP_LANE2_P2_LEVEL0 26 +#define DC_LANE0_DP_LANE2_P3_LEVEL0 34 +#define DC_LANE0_DP_LANE2_P0_LEVEL1 26 +#define DC_LANE0_DP_LANE2_P1_LEVEL1 32 +#define DC_LANE0_DP_LANE2_P2_LEVEL1 39 +#define DC_LANE0_DP_LANE2_P0_LEVEL2 34 +#define DC_LANE0_DP_LANE2_P1_LEVEL2 43 +#define DC_LANE0_DP_LANE2_P0_LEVEL3 51 +#define LANE_DRIVE_CURRENT(i) (0x4e + (i)) +#define PR(i) (0x52 + (i)) +#define PR_LANE3_DP_LANE3_SHIFT 24 +#define PR_LANE3_DP_LANE3_MASK (0xff << 24) +#define PR_LANE3_DP_LANE3_D0_LEVEL0 (0 << 24) +#define PR_LANE3_DP_LANE3_D1_LEVEL0 (0 << 24) +#define PR_LANE3_DP_LANE3_D2_LEVEL0 (0 << 24) +#define PR_LANE3_DP_LANE3_D3_LEVEL0 (0 << 24) +#define PR_LANE3_DP_LANE3_D0_LEVEL1 (4 << 24) +#define PR_LANE3_DP_LANE3_D1_LEVEL1 (6 << 24) +#define PR_LANE3_DP_LANE3_D2_LEVEL1 (17 << 24) +#define PR_LANE3_DP_LANE3_D0_LEVEL2 (8 << 24) +#define PR_LANE3_DP_LANE3_D1_LEVEL2 (13 << 24) +#define PR_LANE3_DP_LANE3_D0_LEVEL3 (17 << 24) +#define PR_LANE2_DP_LANE0_SHIFT 16 +#define PR_LANE2_DP_LANE0_MASK (0xff << 16) +#define PR_LANE2_DP_LANE0_D0_LEVEL0 (0 << 16) +#define PR_LANE2_DP_LANE0_D1_LEVEL0 (0 << 16) +#define PR_LANE2_DP_LANE0_D2_LEVEL0 (0 << 16) +#define PR_LANE2_DP_LANE0_D3_LEVEL0 (0 << 16) +#define PR_LANE2_DP_LANE0_D0_LEVEL1 (4 << 16) +#define PR_LANE2_DP_LANE0_D1_LEVEL1 (6 << 16) +#define PR_LANE2_DP_LANE0_D2_LEVEL1 (17 << 16) +#define PR_LANE2_DP_LANE0_D0_LEVEL2 (8 << 16) +#define PR_LANE2_DP_LANE0_D1_LEVEL2 (13 << 16) +#define PR_LANE2_DP_LANE0_D0_LEVEL3 (17 << 16) +#define PR_LANE1_DP_LANE1_SHIFT 8 +#define PR_LANE1_DP_LANE1_MASK (0xff >> 8) +#define PR_LANE1_DP_LANE1_D0_LEVEL0 (0 >> 8) +#define PR_LANE1_DP_LANE1_D1_LEVEL0 (0 >> 8) +#define PR_LANE1_DP_LANE1_D2_LEVEL0 (0 >> 8) +#define PR_LANE1_DP_LANE1_D3_LEVEL0 (0 >> 8) +#define PR_LANE1_DP_LANE1_D0_LEVEL1 (4 >> 8) +#define PR_LANE1_DP_LANE1_D1_LEVEL1 (6 >> 8) +#define PR_LANE1_DP_LANE1_D2_LEVEL1 (17 >> 8) +#define PR_LANE1_DP_LANE1_D0_LEVEL2 (8 >> 8) +#define PR_LANE1_DP_LANE1_D1_LEVEL2 (13 >> 8) +#define PR_LANE1_DP_LANE1_D0_LEVEL3 (17 >> 8) +#define PR_LANE0_DP_LANE2_SHIFT 0 +#define PR_LANE0_DP_LANE2_MASK 0xff +#define PR_LANE0_DP_LANE2_D0_LEVEL0 0 +#define PR_LANE0_DP_LANE2_D1_LEVEL0 0 +#define PR_LANE0_DP_LANE2_D2_LEVEL0 0 +#define PR_LANE0_DP_LANE2_D3_LEVEL0 0 +#define PR_LANE0_DP_LANE2_D0_LEVEL1 4 +#define PR_LANE0_DP_LANE2_D1_LEVEL1 6 +#define PR_LANE0_DP_LANE2_D2_LEVEL1 17 +#define PR_LANE0_DP_LANE2_D0_LEVEL2 8 +#define PR_LANE0_DP_LANE2_D1_LEVEL2 13 +#define PR_LANE0_DP_LANE2_D0_LEVEL3 17 +#define LANE4_PREEMPHASIS(i) (0x54 + (i)) +#define POSTCURSOR(i) (0x56 + (i)) +#define DP_CONFIG(i) (0x58 + (i)) +#define DP_CONFIG_RD_RESET_VAL_SHIFT 31 +#define DP_CONFIG_RD_RESET_VAL_POSITIVE (0 << 31) +#define DP_CONFIG_RD_RESET_VAL_NEGATIVE (1 << 31) +#define DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT 28 +#define DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE (0 << 28) +#define DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE (1 << 28) +#define DP_CONFIG_ACTIVESYM_CNTL_SHIFT 26 +#define DP_CONFIG_ACTIVESYM_CNTL_DISABLE (0 << 26) +#define DP_CONFIG_ACTIVESYM_CNTL_ENABLE (1 << 26) +#define DP_CONFIG_ACTIVESYM_POLARITY_SHIFT 24 +#define DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE (0 << 24) +#define DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE (1 << 24) +#define DP_CONFIG_ACTIVESYM_FRAC_SHIFT 16 +#define DP_CONFIG_ACTIVESYM_FRAC_MASK (0xf << 16) +#define DP_CONFIG_ACTIVESYM_COUNT_SHIFT 8 +#define DP_CONFIG_ACTIVESYM_COUNT_MASK (0x7f << 8) +#define DP_CONFIG_WATERMARK_SHIFT 0 +#define DP_CONFIG_WATERMARK_MASK 0x3f +#define DP_MN(i) (0x5a + i) +#define DP_MN_M_MOD_SHIFT 30 +#define DP_MN_M_MOD_DEFAULT_MASK (3 << 30) +#define DP_MN_M_MOD_NONE (0 << 30) +#define DP_MN_M_MOD_INC (1 << 30) +#define DP_MN_M_MOD_DEC (2 << 30) +#define DP_MN_M_DELTA_SHIFT 24 +#define DP_MN_M_DELTA_DEFAULT_MASK (0xf << 24) +#define DP_MN_N_VAL_SHIFT 0 +#define DP_MN_N_VAL_DEFAULT_MASK 0xffffff +#define DP_PADCTL(i) (0x5c + (i)) +#define DP_PADCTL_SPARE_SHIFT 25 +#define DP_PADCTL_SPARE_DEFAULT_MASK (0x7f << 25) +#define DP_PADCTL_VCO_2X_SHIFT 24 +#define DP_PADCTL_VCO_2X_DISABLE (0 << 24) +#define DP_PADCTL_VCO_2X_ENABLE (1 << 24) +#define DP_PADCTL_PAD_CAL_PD_SHIFT 23 +#define DP_PADCTL_PAD_CAL_PD_POWERUP (0 << 23) +#define DP_PADCTL_PAD_CAL_PD_POWERDOWN (1 << 23) +#define DP_PADCTL_TX_PU_SHIFT 22 +#define DP_PADCTL_TX_PU_DISABLE (0 << 22) +#define DP_PADCTL_TX_PU_ENABLE (1 << 22) +#define DP_PADCTL_TX_PU_MASK (1 << 22) +#define DP_PADCTL_REG_CTRL_SHIFT 20 +#define DP_PADCTL_REG_CTRL_DEFAULT_MASK (3 << 20) +#define DP_PADCTL_VCMMODE_SHIFT 16 +#define DP_PADCTL_VCMMODE_DEFAULT_MASK (0xf << 16) +#define DP_PADCTL_VCMMODE_TRISTATE (0 << 16) +#define DP_PADCTL_VCMMODE_TEST_MUX (1 << 16) +#define DP_PADCTL_VCMMODE_WEAK_PULLDOWN (2 << 16) +#define DP_PADCTL_VCMMODE_STRONG_PULLDOWN (4 << 16) +#define DP_PADCTL_TX_PU_VALUE_SHIFT 8 +#define DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK (0xff << 8) +#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT 7 +#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE (0 << 7) +#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE (1 << 7) +#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_SHIFT 6 +#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE (0 << 6) +#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE (1 << 6) +#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_SHIFT 5 +#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE (0 << 5) +#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE (1 << 5) +#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT 4 +#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE (0 << 4) +#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE (1 << 4) +#define DP_PADCTL_PD_TXD_3_SHIFT 3 +#define DP_PADCTL_PD_TXD_3_YES (0 << 3) +#define DP_PADCTL_PD_TXD_3_NO (1 << 3) +#define DP_PADCTL_PD_TXD_0_SHIFT 2 +#define DP_PADCTL_PD_TXD_0_YES (0 << 2) +#define DP_PADCTL_PD_TXD_0_NO (1 << 2) +#define DP_PADCTL_PD_TXD_1_SHIFT 1 +#define DP_PADCTL_PD_TXD_1_YES (0 << 1) +#define DP_PADCTL_PD_TXD_1_NO (1 << 1) +#define DP_PADCTL_PD_TXD_2_SHIFT 0 +#define DP_PADCTL_PD_TXD_2_YES 0 +#define DP_PADCTL_PD_TXD_2_NO 1 +#define DP_DEBUG(i) (0x5e + i) +#define DP_SPARE(i) (0x60 + (i)) +#define DP_SPARE_REG_SHIFT 3 +#define DP_SPARE_REG_DEFAULT_MASK (0x1fffffff << 3) +#define DP_SPARE_SOR_CLK_SEL_SHIFT 2 +#define DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK (1 << 2) +#define DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK (0 << 2) +#define DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK (1 << 2) +#define DP_SPARE_PANEL_SHIFT 1 +#define DP_SPARE_PANEL_EXTERNAL (0 << 1) +#define DP_SPARE_PANEL_INTERNAL (1 << 1) +#define DP_SPARE_SEQ_ENABLE_SHIFT 0 +#define DP_SPARE_SEQ_ENABLE_NO 0 +#define DP_SPARE_SEQ_ENABLE_YES 1 +#define DP_AUDIO_CTRL 0x62 +#define DP_AUDIO_HBLANK_SYMBOLS 0x63 +#define DP_AUDIO_HBLANK_SYMBOLS_MASK 0x1ffff +#define DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT 0 +#define DP_AUDIO_VBLANK_SYMBOLS 0x64 +#define DP_AUDIO_VBLANK_SYMBOLS_MASK 0x1ffff +#define DP_AUDIO_VBLANK_SYMBOLS_SHIFT 0 +#define DP_GENERIC_INFOFRAME_HEADER 0x65 +#define DP_GENERIC_INFOFRAME_SUBPACK(i) (0x66 + (i)) +#define DP_TPG 0x6d +#define DP_TPG_LANE3_CHANNELCODING_SHIFT 30 +#define DP_TPG_LANE3_CHANNELCODING_DISABLE (0 << 30) +#define DP_TPG_LANE3_CHANNELCODING_ENABLE (1 << 30) +#define DP_TPG_LANE3_SCRAMBLEREN_SHIFT 28 +#define DP_TPG_LANE3_SCRAMBLEREN_ENABLE_GALIOS (1 << 28) +#define DP_TPG_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 28) +#define DP_TPG_LANE3_PATTERN_SHIFT 24 +#define DP_TPG_LANE3_PATTERN_DEFAULT_MASK (0xf << 24) +#define DP_TPG_LANE3_PATTERN_NOPATTERN (0 << 24) +#define DP_TPG_LANE3_PATTERN_TRAINING1 (1 << 24) +#define DP_TPG_LANE3_PATTERN_TRAINING2 (2 << 24) +#define DP_TPG_LANE3_PATTERN_TRAINING3 (3 << 24) +#define DP_TPG_LANE3_PATTERN_D102 (4 << 24) +#define DP_TPG_LANE3_PATTERN_SBLERRRATE (5 << 24) +#define DP_TPG_LANE3_PATTERN_PRBS7 (6 << 24) +#define DP_TPG_LANE3_PATTERN_CSTM (7 << 24) +#define DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE (8 << 24) +#define DP_TPG_LANE2_CHANNELCODING_SHIFT 22 +#define DP_TPG_LANE2_CHANNELCODING_DISABLE (0 << 22) +#define DP_TPG_LANE2_CHANNELCODING_ENABLE (1 << 22) +#define DP_TPG_LANE2_SCRAMBLEREN_SHIFT 20 +#define DP_TPG_LANE2_SCRAMBLEREN_DEFAULT_MASK (3 << 20) +#define DP_TPG_LANE2_SCRAMBLEREN_DISABLE (0 << 20) +#define DP_TPG_LANE2_SCRAMBLEREN_ENABLE_GALIOS (1 << 20) +#define DP_TPG_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 20) +#define DP_TPG_LANE2_PATTERN_SHIFT 16 +#define DP_TPG_LANE2_PATTERN_DEFAULT_MASK (0xf << 16) +#define DP_TPG_LANE2_PATTERN_NOPATTERN (0 << 16) +#define DP_TPG_LANE2_PATTERN_TRAINING1 (1 << 16) +#define DP_TPG_LANE2_PATTERN_TRAINING2 (2 << 16) +#define DP_TPG_LANE2_PATTERN_TRAINING3 (3 << 16) +#define DP_TPG_LANE2_PATTERN_D102 (4 << 16) +#define DP_TPG_LANE2_PATTERN_SBLERRRATE (5 << 16) +#define DP_TPG_LANE2_PATTERN_PRBS7 (6 << 16) +#define DP_TPG_LANE2_PATTERN_CSTM (7 << 16) +#define DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE (8 << 16) +#define DP_TPG_LANE1_CHANNELCODING_SHIFT 14 +#define DP_TPG_LANE1_CHANNELCODING_DISABLE (0 << 14) +#define DP_TPG_LANE1_CHANNELCODING_ENABLE (1 << 14) +#define DP_TPG_LANE1_SCRAMBLEREN_SHIFT 12 +#define DP_TPG_LANE1_SCRAMBLEREN_DEFAULT_MASK (3 << 12) +#define DP_TPG_LANE1_SCRAMBLEREN_DISABLE (0 << 12) +#define DP_TPG_LANE1_SCRAMBLEREN_ENABLE_GALIOS (1 << 12) +#define DP_TPG_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 12) +#define DP_TPG_LANE1_PATTERN_SHIFT 8 +#define DP_TPG_LANE1_PATTERN_DEFAULT_MASK (0xf << 8) +#define DP_TPG_LANE1_PATTERN_NOPATTERN (0 << 8) +#define DP_TPG_LANE1_PATTERN_TRAINING1 (1 << 8) +#define DP_TPG_LANE1_PATTERN_TRAINING2 (2 << 8) +#define DP_TPG_LANE1_PATTERN_TRAINING3 (3 << 8) +#define DP_TPG_LANE1_PATTERN_D102 (4 << 8) +#define DP_TPG_LANE1_PATTERN_SBLERRRATE (5 << 8) +#define DP_TPG_LANE1_PATTERN_PRBS7 (6 << 8) +#define DP_TPG_LANE1_PATTERN_CSTM (7 << 8) +#define DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE (8 << 8) +#define DP_TPG_LANE0_CHANNELCODING_SHIFT 6 +#define DP_TPG_LANE0_CHANNELCODING_DISABLE (0 << 6) +#define DP_TPG_LANE0_CHANNELCODING_ENABLE (1 << 6) +#define DP_TPG_LANE0_SCRAMBLEREN_SHIFT 4 +#define DP_TPG_LANE0_SCRAMBLEREN_DEFAULT_MASK (3 << 4) +#define DP_TPG_LANE0_SCRAMBLEREN_DISABLE (0 << 4) +#define DP_TPG_LANE0_SCRAMBLEREN_ENABLE_GALIOS (1 << 4) +#define DP_TPG_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 4) +#define DP_TPG_LANE0_PATTERN_SHIFT 0 +#define DP_TPG_LANE0_PATTERN_DEFAULT_MASK 0xf +#define DP_TPG_LANE0_PATTERN_NOPATTERN 0 +#define DP_TPG_LANE0_PATTERN_TRAINING1 1 +#define DP_TPG_LANE0_PATTERN_TRAINING2 2 +#define DP_TPG_LANE0_PATTERN_TRAINING3 3 +#define DP_TPG_LANE0_PATTERN_D102 4 +#define DP_TPG_LANE0_PATTERN_SBLERRRATE 5 +#define DP_TPG_LANE0_PATTERN_PRBS7 6 +#define DP_TPG_LANE0_PATTERN_CSTM 7 +#define DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE 8 + +enum { + training_pattern_disabled = 0, + training_pattern_1 = 1, + training_pattern_2 = 2, + training_pattern_3 = 3, + training_pattern_none = 0xff +}; + +enum tegra_dc_sor_protocol { + SOR_DP, + SOR_LVDS, +}; + +#define SOR_LINK_SPEED_G1_62 6 +#define SOR_LINK_SPEED_G2_7 10 +#define SOR_LINK_SPEED_G5_4 20 +#define SOR_LINK_SPEED_LVDS 7 + +struct tegra_dp_link_config { + int is_valid; + + /* Supported configuration */ + u8 max_link_bw; + u8 max_lane_count; + int downspread; + int support_enhanced_framing; + u32 bits_per_pixel; + int alt_scramber_reset_cap; /* true for eDP */ + int only_enhanced_framing; /* enhanced_frame_en ignored */ + int frame_in_ms; + + /* Actual configuration */ + u8 link_bw; + u8 lane_count; + int enhanced_framing; + int scramble_ena; + + u32 activepolarity; + u32 active_count; + u32 tu_size; + u32 active_frac; + u32 watermark; + + s32 hblank_sym; + s32 vblank_sym; + + /* Training data */ + u32 drive_current; + u32 preemphasis; + u32 postcursor; + u8 aux_rd_interval; + u8 tps3_supported; +}; + +struct tegra_dc_sor_data { + void *base; + void *pmc_base; + u8 portnum; /* 0 or 1 */ + int power_is_up; +}; + +#define TEGRA_SOR_TIMEOUT_MS 1000 +#define TEGRA_SOR_ATTACH_TIMEOUT_MS 1000 + +int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *link_cfg); +int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd); +void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena, + u8 training_pattern, const struct tegra_dp_link_config *link_cfg); +void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw); +void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count); +void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor, + int power_up); +void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int); +void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw, + u8 *lane_count); +void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *link_cfg); +void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *link_cfg); +int tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *link_cfg); +int tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *cfg); +void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor); +void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, + u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported); + +int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *link_cfg, + const struct display_timing *timing); +int tegra_dc_sor_detach(struct tegra_dc_sor_data *sor); + +void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl, + int *dc_reg_ctx); +int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl); +void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl, + int *dc_reg_ctx); + +int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp); +#endif diff --git a/drivers/video/tegra124/tegra124-lcd.c b/drivers/video/tegra124/tegra124-lcd.c new file mode 100644 index 0000000..2733590 --- /dev/null +++ b/drivers/video/tegra124/tegra124-lcd.c @@ -0,0 +1,97 @@ +/* + * Copyright 2014 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <lcd.h> +#include <asm/gpio.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch-tegra/dc.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum { + /* Maximum LCD size we support */ + LCD_MAX_WIDTH = 1920, + LCD_MAX_HEIGHT = 1200, + LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ +}; + +vidinfo_t panel_info = { + /* Insert a value here so that we don't end up in the BSS */ + .vl_col = -1, +}; + +int tegra_lcd_check_next_stage(const void *blob, int wait) +{ + return 0; +} + +void tegra_lcd_early_init(const void *blob) +{ + /* + * Go with the maximum size for now. We will fix this up after + * relocation. These values are only used for memory alocation. + */ + panel_info.vl_col = LCD_MAX_WIDTH; + panel_info.vl_row = LCD_MAX_HEIGHT; + panel_info.vl_bpix = LCD_MAX_LOG2_BPP; +} + +static int tegra124_lcd_init(void *lcdbase) +{ + struct display_timing timing; + int ret; + + clock_set_up_plldp(); + clock_adjust_periph_pll_div(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, + 408000000, NULL); + + clock_enable(PERIPH_ID_HOST1X); + clock_enable(PERIPH_ID_DISP1); + clock_enable(PERIPH_ID_PWM); + clock_enable(PERIPH_ID_DPAUX); + clock_enable(PERIPH_ID_SOR0); + + udelay(2); + + reset_set_enable(PERIPH_ID_HOST1X, 0); + reset_set_enable(PERIPH_ID_DISP1, 0); + reset_set_enable(PERIPH_ID_PWM, 0); + reset_set_enable(PERIPH_ID_DPAUX, 0); + reset_set_enable(PERIPH_ID_SOR0, 0); + + ret = display_init(lcdbase, 1 << LCD_BPP, &timing); + if (ret) + return ret; + + panel_info.vl_col = roundup(timing.hactive.typ, 16); + panel_info.vl_row = timing.vactive.typ; + + lcd_set_flush_dcache(1); + + return 0; +} + +void lcd_ctrl_init(void *lcdbase) +{ + ulong start; + int ret; + + start = get_timer(0); + ret = tegra124_lcd_init(lcdbase); + debug("LCD init took %lu ms\n", get_timer(start)); + if (ret) + printf("%s: Error %d\n", __func__, ret); +} + +void lcd_enable(void) +{ +} diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 3b96b82..519bb0b 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -115,7 +115,7 @@ struct gpio_desc { unsigned long flags; #define GPIOD_REQUESTED (1 << 0) /* Requested/claimed */ #define GPIOD_IS_OUT (1 << 1) /* GPIO is an output */ -#define GPIOD_IS_IN (1 << 2) /* GPIO is an output */ +#define GPIOD_IS_IN (1 << 2) /* GPIO is an input */ #define GPIOD_ACTIVE_LOW (1 << 3) /* value has active low */ #define GPIOD_IS_OUT_ACTIVE (1 << 4) /* set output active */ @@ -336,15 +336,24 @@ int gpio_lookup_name(const char *name, struct udevice **devp, unsigned int *offsetp, unsigned int *gpiop); /** - * get_gpios() - Turn the values of a list of GPIOs into an integer + * gpio_get_values_as_int() - Turn the values of a list of GPIOs into an int * * This puts the value of the first GPIO into bit 0, the second into bit 1, * etc. then returns the resulting integer. * * @gpio_list: List of GPIOs to collect - * @return resulting integer value + * @return resulting integer value, or -ve on error */ -unsigned gpio_get_values_as_int(const int *gpio_list); +int gpio_get_values_as_int(const int *gpio_list); + +/** + * gpio_claim_vector() - claim a number of GPIOs for input + * + * @gpio_num_array: array of gpios to claim, terminated by -1 + * @fmt: format string for GPIO names, e.g. "board_id%d" + * @return 0 if OK, -ve on error + */ +int gpio_claim_vector(const int *gpio_num_array, const char *fmt); /** * gpio_request_by_name() - Locate and request a GPIO by name diff --git a/include/bcd.h b/include/bcd.h index af4aa9c..9ecd328 100644 --- a/include/bcd.h +++ b/include/bcd.h @@ -10,14 +10,12 @@ #ifndef _BCD_H #define _BCD_H -#include <linux/types.h> - -static inline unsigned int bcd2bin(u8 val) +static inline unsigned int bcd2bin(unsigned int val) { - return ((val) & 0x0f) + ((val) >> 4) * 10; + return ((val) & 0x0f) + ((val & 0xff) >> 4) * 10; } -static inline u8 bin2bcd (unsigned int val) +static inline unsigned int bin2bcd(unsigned int val) { return (((val / 10) << 4) | (val % 10)); } diff --git a/include/bootstage.h b/include/bootstage.h index be44014..fe30ab6 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -195,6 +195,8 @@ enum bootstage_id { BOOTSTAGE_ID_ACCUM_LCD, BOOTSTAGE_ID_ACCUM_SCSI, + BOOTSTAGE_ID_ACCUM_SPI, + BOOTSTAGE_ID_ACCUM_DECOMP, /* a few spare for the user, from here */ BOOTSTAGE_ID_USER, diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h deleted file mode 100644 index 932a309..0000000 --- a/include/configs/afeb9260.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org> - * - * Configuation settings for the AFEB9260 board. - * Based on configuration for AT91SAM9260-EK - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H -#define CONFIG_AT91SAM9260 /* Atmel AT91SAM9260 SoC*/ -#include <asm/arch/hardware.h> - -#define CONFIG_SYS_TEXT_BASE 0x21f00000 - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO - -#define CONFIG_AFEB9260 /* AFEB9260 Board */ -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Hardware drivers - */ -#define CONFIG_ATMEL_LEGACY -#define CONFIG_AT91_GPIO -#define CONFIG_AT91_PULLUP 1 - -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_USART3 /* USART 3 is DBGU */ - -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_SOURCE - -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - -#define CONFIG_CMD_NAND -#define CONFIG_CMD_USB - -/* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ - -/* DataFlash */ -#define CONFIG_ATMEL_DATAFLASH_SPI -#define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ -#define AT91_SPI_CLK 15000000 -#define DATAFLASH_TCSS (0x1a << 16) -#define DATAFLASH_TCHS (0x1 << 24) - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 - -#endif - -/* NOR flash - no real flash on this board */ -#define CONFIG_SYS_NO_FLASH - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RESET_PHY_R -#define CONFIG_AT91_WANTS_COMMON_PHY -#define CONFIG_NET_RETRY_COUNT 20 - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#define CONFIG_USB_STORAGE - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x21e00000 - -#define CONFIG_SYS_USE_DATAFLASH_CS1 -#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 -\ - GENERATED_GBL_DATA_SIZE) - -/* bootstrap + u-boot + env + linux in dataflash on CS1 */ -#define CONFIG_ENV_IS_IN_DATAFLASH -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400) -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xa0000 0x200000; bootm" -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock2 " \ - "rw rootfstype=jffs2 panic=20" - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - -#endif diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index a87059c..8da3325 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -83,10 +83,6 @@ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 ro\0" \ "mmcrootfstype=ext4 rootwait\0" \ - "rootpath=/export/rootfs\0" \ - "nfsopts=nolock\0" \ - "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ - "::off\0" \ "ramroot=/dev/ram0 rw\0" \ "ramrootfstype=ext2\0" \ "mmcargs=setenv bootargs console=${console} " \ @@ -102,11 +98,6 @@ "${optargs} " \ "root=${spiroot} " \ "rootfstype=${spirootfstype}\0" \ - "netargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=/dev/nfs " \ - "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ - "ip=dhcp\0" \ "bootenv=uEnv.txt\0" \ "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ @@ -159,13 +150,6 @@ "sf probe ${spibusno}:0; " \ "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \ "bootz ${loadaddr}\0" \ - "netboot=echo Booting from network ...; " \ - "setenv autoload no; " \ - "dhcp; " \ - "tftp ${loadaddr} ${bootfile}; " \ - "tftp ${fdtaddr} ${fdtfile}; " \ - "run netargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ "ramboot=echo Booting from ramdisk ...; " \ "run ramargs; " \ "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ @@ -181,6 +165,7 @@ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ NANDARGS \ + NETARGS \ DFUARGS #endif diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 6eb31e2..331fdac 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -295,6 +295,7 @@ "setenv fdtfile am437x-idk-evm.dtb; fi; " \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree; fi; \0" \ + NETARGS \ DFUARGS \ #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index d5b6e37..9e7f37d 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -106,7 +106,6 @@ #define CONFIG_LOADS_ECHO /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ -#define CONFIG_REGEX /* Enable regular expression support */ /* * BOOTP options */ diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index dedb785..94981e7 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -64,7 +64,7 @@ #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk " \ "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ - "256K(env),256k(evn_redundent),256k(spare)," \ + "256K(env),256k(env_redundent),256k(spare)," \ "512k(dtb),6M(kernel)ro,-(rootfs) " \ "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" #endif diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 6c1bd30..e43795b 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -171,7 +171,7 @@ #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk " \ "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ - "256K(env),256k(evn_redundent),256k(spare)," \ + "256K(env),256k(env_redundent),256k(spare)," \ "512k(dtb),6M(kernel)ro,-(rootfs) " \ "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 240fc46..b441fa0 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -13,6 +13,7 @@ #define __BUR_AM335X_COMMON_H__ /* ------------------------------------------------------------------------- */ #define BUR_COMMON_ENV \ +"usbscript=usb start && fatload usb 0 0x80000000 usbscript.img && source\0" \ "defaultip=192.168.60.253\0" \ "defaultsip=192.168.60.254\0" \ "netconsole=echo switching to network console ...; " \ @@ -30,12 +31,6 @@ "setenv stdout nc;setenv stdin nc;setenv stderr nc\0" #define CONFIG_CMD_TIME -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1366*767*4) -#define CONFIG_CMD_UNZIP -#define CONFIG_CMD_BMP -#define CONFIG_BMP_24BMP -#define CONFIG_BMP_32BPP #define CONFIG_SYS_GENERIC_BOARD diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 577afe7..dbe05e4 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -31,7 +31,6 @@ #undef CONFIG_CMD_MTDPARTS #define CONFIG_CMD_DFU #define CONFIG_CMD_GPT -#define CONFIG_CMD_PMIC #define CONFIG_CMD_SETEXPR /* USB Composite download gadget - g_dnl */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 2eddb07..5476248 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -149,6 +149,10 @@ #define CONFIG_OF_SPI #endif +/* Power */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C + #ifdef CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_MODE SPI_MODE_0 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index fcfc1b3..b20b338 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -8,6 +8,7 @@ #define __CONFIG_H /* SPL */ +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT @@ -44,8 +45,21 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MISC_INIT_R +/* Driver Model */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL +#define CONFIG_DM_THERMAL +#define CONFIG_CMD_DM +#endif + /* GPIO */ #define CONFIG_MXC_GPIO +#define CONFIG_CMD_GPIO + +/* Thermal */ +#define CONFIG_IMX6_THERMAL /* Serial */ #define CONFIG_MXC_UART @@ -360,7 +374,7 @@ "mmc_boot=" \ "setenv fsload 'ext2load mmc 0:1'; " \ "mmc dev 0 && mmc rescan && " \ - "run loadscript; " \ + "setenv dtype mmc; run loadscript; " \ "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/mmcblk0p1 rootfstype=ext4 " \ @@ -374,7 +388,7 @@ \ "sata_boot=" \ "setenv fsload 'ext2load sata 0:1'; sata init && " \ - "run loadscript; " \ + "setenv dtype sata; run loadscript; " \ "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/sda1 rootfstype=ext4 " \ @@ -387,7 +401,7 @@ "fi\0" \ "usb_boot=" \ "setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \ - "run loadscript; " \ + "setenv dtype usb; run loadscript; " \ "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/sda1 rootfstype=ext4 " \ @@ -451,7 +465,7 @@ "setenv root ubi0:rootfs ubi.mtd=2 " \ "rootfstype=ubifs; " \ "fi; " \ - "run loadscript; " \ + "setenv dtype nand; run loadscript; " \ "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=${root} ${video} ${extra}; " \ diff --git a/include/configs/hummingboard.h b/include/configs/hummingboard.h deleted file mode 100644 index 973f2c5..0000000 --- a/include/configs/hummingboard.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * Configuration settings for the SolidRun Hummingboard. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" -#include <asm/arch/imx-regs.h> -#include <asm/imx-common/gpio.h> -#include <linux/sizes.h> - -#define CONFIG_MX6 -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_MACH_TYPE 4773 - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_SYS_GENERIC_BOARD - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_MXC_GPIO - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* Command definition */ -#include <config_cmd_default.h> - -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_I2C - -#define CONFIG_CMD_BMODE -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_MEMTEST -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) -#define CONFIG_LOADADDR 0x12000000 -#define CONFIG_SYS_TEXT_BASE 0x17800000 - -/* MMC Configuration */ -#define CONFIG_FSL_ESDHC -#define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_USDHC_NUM 1 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -#define CONFIG_MMC -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION - -/* Ethernet Configuration */ -#define CONFIG_FEC_MXC -#ifdef CONFIG_FEC_MXC -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_MII -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_PHYLIB -#define CONFIG_PHY_ATHEROS -#endif - -#if defined(CONFIG_MX6S) -#define CONFIG_DEFAULT_FDT_FILE "imx6dl-hummingboard.dtb" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "splashpos=m,m\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x18000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "update_sd_firmware_filename=u-boot.imx\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_CMDLINE_EDITING - -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ENV_SIZE (8 * 1024) - -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ - -#ifndef CONFIG_SYS_DCACHE_OFF -#define CONFIG_CMD_CACHE -#endif - -#endif /* __CONFIG_H * */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 8c016b7..aeafbd5 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -79,4 +79,9 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" +#define CONFIG_ARMV7_PSCI 1 +/* Reserve top 1M for secure RAM */ +#define CONFIG_ARMV7_SECURE_BASE 0xfff00000 +#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 + #endif /* __CONFIG_H */ diff --git a/include/configs/kwb.h b/include/configs/kwb.h index dd30df2..d1c745e 100644 --- a/include/configs/kwb.h +++ b/include/configs/kwb.h @@ -19,6 +19,14 @@ #define CONFIG_LCD_NOSTDOUT #define CONFIG_SYS_WHITE_ON_BLACK #define LCD_BPP LCD_COLOR32 + +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1366*767*4) +#define CONFIG_CMD_UNZIP +#define CONFIG_CMD_BMP +#define CONFIG_BMP_24BMP +#define CONFIG_BMP_32BPP + /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -72,10 +80,6 @@ BUR_COMMON_ENV \ "run loadromfs; " \ "tftp ${loadaddr} arimg && go ${loadaddr}; " \ "puts 'networkboot failed!';\0" \ -"usbupdate=echo updating u-boot from usb ...; " \ - "usb start; " \ - "fatload usb 0 0x80000000 updateubootusb.img && source; " \ - "puts 'usbupdate failed!'\0" \ "netscript=echo running script from network (tftp) ...; " \ "tftp 0x80000000 netscript.img && source; " \ "puts 'netscript load failed!'\0" \ @@ -93,7 +97,7 @@ BUR_COMMON_ENV \ #endif /* !CONFIG_SPL_BUILD*/ #define CONFIG_BOOTCOMMAND \ - "run usbupdate;" + "run usbscript;" #define CONFIG_BOOTDELAY 0 /* undefine command which we not need here */ diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 5c20991..dbc00ce 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -49,7 +49,6 @@ #define CONFIG_CMD_USB #define CONFIG_VIDEO -#define CONFIG_REGEX /* Enable regular expression support */ /* Memory configuration */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index c348d38..0cc1282 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -51,7 +51,6 @@ #define CONFIG_CMD_USB #define CONFIG_VIDEO -#define CONFIG_REGEX /* Enable regular expression support */ /* * Memory configurations diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index b569f34..b6f9d4e 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -27,7 +27,7 @@ #define CONFIG_IMX6_THERMAL #define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_GPIO @@ -66,6 +66,47 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_HDMI +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_CONSOLE_MUX + +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL +#define CONFIG_PREBOOT \ + "if hdmidet; then " \ + "usb start; " \ + "setenv stdin serial,usbkbd; "\ + "setenv stdout serial,vga; " \ + "setenv stderr serial,vga; " \ + "else " \ + "setenv stdin serial; " \ + "setenv stdout serial; " \ + "setenv stderr serial; " \ + "fi;" + #define CONFIG_SYS_NO_FLASH /* Command definition */ diff --git a/include/configs/novena.h b/include/configs/novena.h index 5f83469..425db8a 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -22,7 +22,6 @@ #define CONFIG_KEYBOARD #define CONFIG_MXC_GPIO #define CONFIG_OF_LIBFDT -#define CONFIG_REGEX #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 5397599..caca98b 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -21,6 +21,8 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CONFIG_DISPLAY_BOARDINFO_LATE + /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C @@ -37,6 +39,18 @@ #define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_I2C_EDID + +/* LCD support */ +#define CONFIG_LCD +#define CONFIG_PWM_TEGRA +#define CONFIG_AS3722_POWER +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK + +/* Align LCD to 1MB boundary */ +#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE + /* SPI */ #define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ #define CONFIG_TEGRA114_SPI_CTRLS 6 diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 5ee0abe..3874baa 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -182,11 +182,6 @@ #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0 -/* POWER */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_MAX77686 - /* GPT */ #define CONFIG_RANDOM_UUID diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index c58636a..e1db29a 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -11,6 +11,12 @@ #define CONFIG_NAND #include <configs/ti_omap3_common.h> +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE (64*1024) +#undef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_TEXT_BASE 0x40200000 + +#define CONFIG_BCH /* Display CPU and Board information */ #define CONFIG_DISPLAY_CPUINFO @@ -134,6 +140,8 @@ "bootm ${loadaddr}\0" \ "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \ "loadfdt=load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "loadubizimage=ubifsload ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadubifdt=ubifsload ${fdtaddr} ${bootdir}/${fdtfile}\0" \ "mmcbootfdt=echo Booting with DT from mmc ...; " \ "run mmcargs; " \ "bootz ${loadaddr} - ${fdtaddr}\0" \ @@ -142,6 +150,13 @@ "if nand read ${loadaddr} linux; then " \ "bootm ${loadaddr};" \ "fi;\0" \ + "nanddtsboot=echo Booting from nand with DTS...; " \ + "run nandargs; " \ + "ubi part rootfs; "\ + "ubifsmount ubi0:rootfs; "\ + "run loadubifdt; "\ + "run loadubizimage; "\ + "bootz ${loadaddr} - ${fdtaddr}\0" \ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ @@ -169,6 +184,10 @@ "fi;" \ "fi;" \ "run nandboot; " \ + "if test -z \"${fdtfile}\"; then "\ + "setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \ + "fi;" \ + "run nanddtsboot; " \ /* * Miscellaneous configurable options @@ -212,17 +231,22 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ + 13, 14, 16, 17, 18, 19, 20, 21, 22, \ + 23, 24, 25, 26, 27, 28, 30, 31, 32, \ + 33, 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 44, 45, 46, 47, 48, 49, 50, 51, \ + 52, 53, 54, 55, 56} #define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW +#define CONFIG_SYS_NAND_ECCBYTES 13 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 /* NAND: SPL falcon mode configs */ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 3bf45a2..f5361d1 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -125,6 +125,8 @@ func(HOST, host, 1) \ func(HOST, host, 0) +#define CONFIG_BOOTCOMMAND "" + #include <config_distro_bootcmd.h> #define CONFIG_KEEP_SERVERADDR @@ -207,5 +209,6 @@ #define CONFIG_CMD_LZMADEC #define CONFIG_CMD_USB +#define CONFIG_CMD_DATE #endif diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h deleted file mode 100644 index e7c35ec..0000000 --- a/include/configs/sbc35_a9g20.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (C) 2009 - * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com> - * - * Configuation settings for the Calao SBC35-A9G20 board - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* SoC type is defined in boards.cfg */ -#include <asm/hardware.h> -#include <linux/sizes.h> - -#if defined(CONFIG_SYS_USE_NANDFLASH) -#define CONFIG_ENV_IS_IN_NAND -#else -#define CONFIG_ENV_IS_IN_EEPROM -#endif - -#define MACH_TYPE_SBC35_A9G20 1848 -#define CONFIG_MACH_TYPE MACH_TYPE_SBC35_A9G20 - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */ - -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* GPIO */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO - -/* Serial */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_SOURCE - -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_USB - -/* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ -#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) - -/* SPI EEPROM */ -#define CONFIG_SPI -#define CONFIG_CMD_SPI -#define CONFIG_ATMEL_SPI - -#define CONFIG_CMD_EEPROM -#define CONFIG_SPI_M95XXX -#define CONFIG_SYS_EEPROM_SIZE 0x10000 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 - -/* SPI RTC */ -#define CONFIG_CMD_DATE -#define CONFIG_RTC_M41T94 -#define CONFIG_M41T94_SPI_BUS 0 -#define CONFIG_M41T94_SPI_CS 0 - -/* NAND flash */ -#define CONFIG_CMD_NAND -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 - -/* NOR flash - no real flash on this board */ -#define CONFIG_SYS_NO_FLASH 1 - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R -#define CONFIG_MACB_SEARCH_PHY -#define CONFIG_AT91_WANTS_COMMON_PHY - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE -#define CONFIG_CMD_FAT - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - -/* Env in EEPROM, bootstrap + u-boot in NAND*/ -#ifdef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_OFFSET 0x20 -#define CONFIG_ENV_SIZE 0x1000 -#endif - -/* Env, bootstrap and u-boot in NAND */ -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_OFFSET_REDUND 0x80000 -#define CONFIG_ENV_SIZE 0x20000 -#endif - -#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000" -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock1 " \ - "mtdparts=atmel_nand:16M(kernel)ro," \ - "120M(rootfs),-(other) " \ - "rw rootfstype=jffs2" - - -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) - -#endif diff --git a/include/configs/sc3.h b/include/configs/sc3.h deleted file mode 100644 index 14e033d..0000000 --- a/include/configs/sc3.h +++ /dev/null @@ -1,549 +0,0 @@ -/* - * (C) Copyright 2007 - * Heiko Schocher, DENX Software Engineering, <hs@denx.de>. - * - * From: - * (C) Copyright 2003 - * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef USE_VGA_GRAPHICS - -/* Memory Map - * 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB) - * 0x74000000 .... 0x740FFFFF -> CS#6 - * 0x74100000 .... 0x741FFFFF -> CS#7 - * 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB - * 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE - * 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB) - * 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB) - * 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB) - * 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB) - * 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored) - * 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB) - * - * 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1) - * 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF) - * 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF) - * 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF) - * 0xEED00000 .... 0xEED00003 -> PCI-Bus - * 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers - * 0xEF40003F .... 0xEF5FFFFF -> reserved - * 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB) - * 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB) - * 0xF0200000 .... 0xF7FFFFFF -> free for flash devices - * 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB) - * 0xF8001000 .... 0xFFDFFFFF -> free for flash devices - * 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB) - */ - -#define CONFIG_SC3 1 -#define CONFIG_405GP 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ - -/* - * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range - * If undefined, IDE access uses a seperat emulation with higher access speed. - * Consider to inform your Linux IDE driver about the different addresses! - * IDE_USES_ISA_EMULATION is only used if you define CONFIG_CMD_IDE! - */ -#define IDE_USES_ISA_EMULATION - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -/* - * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz - */ -#define CONFIG_SYS_CLK_FREQ 33333333 - -/* - * define CONFIG_BAUDRATE to the baudrate value you want to use as default - */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nand_args=setenv bootargs root=/dev/mtdblock5 rw" \ - "rootfstype=jffs2\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_nand=run nand_args addip addcons;bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/sc3/uImage\0" \ - "u-boot=/tftpboot/sc3/u-boot.bin\0" \ - "setup=tftp 200000 /tftpboot/sc3/setup.img;source 200000\0" \ - "kernel_addr=FFE08000\0" \ - "" -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#if 1 /* feel free to disable for development */ -#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT \ - "\nSC3 - booting... stop with ENTER\n" -#define CONFIG_AUTOBOOT_DELAY_STR "\r" /* 1st "password" */ -#define CONFIG_AUTOBOOT_DELAY_STR2 "\n" /* 1st "password" */ -#endif - -/* - * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after - * the CONFIG_BOOTDELAY delay to boot your machine - */ -#define CONFIG_BOOTCOMMAND "bootp;dcache on;bootm" - -/* - * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't - * set different values at the u-boot prompt - */ -#ifdef USE_VGA_GRAPHICS - #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re" -#else - #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs rw ip=bootp" -#endif -/* - * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT - * This reserves memory bank #4 for this purpose - */ -#undef CONFIG_ISP1161_PRESENT - -#undef CONFIG_LOADS_ECHO /* no echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* #define CONFIG_EEPRO100_SROM_WRITE */ -/* #define CONFIG_SHOW_MAC */ -#define CONFIG_EEPRO100 - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* add 405GP MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SOURCE - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_PROMPT "SC3> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ - -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* - * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. - * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. - * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. - * The Linux BASE_BAUD define should match this configuration. - * baseBaud = cpuClock/(uartDivisor*16) - * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, - * set Linux BASE_BAUD to 403200. - * - * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to - * (see 405GP datasheet for descritpion) - */ -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ -#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CONFIG_SYS_BASE_BAUD 921600 /* internal clock */ - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -/*----------------------------------------------------------------------- - * IIC stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 - -#define I2C_INIT -#define I2C_ACTIVE 0 -#define I2C_TRISTATE 0 - -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* mask valid bits */ - -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -/* If you want to see, whats connected to your PCI bus */ -/* #define CONFIG_PCI_SCAN_SHOW */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * External peripheral base address - *----------------------------------------------------------------------- - */ -#if !defined(CONFIG_CMD_IDE) - -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#else -#define CONFIG_START_IDE 1 /* check, if use IDE */ - -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CONFIG_ATAPI -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#ifndef IDE_USES_ISA_EMULATION - -/* New and faster access */ -#define CONFIG_SYS_ATA_BASE_ADDR 0x7A000000 /* start of ISA IO emulation */ - -/* How many IDE busses are available */ -#define CONFIG_SYS_IDE_MAXBUS 1 - -/* What IDE ports are available */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x000 /* first is available */ -#undef CONFIG_SYS_ATA_IDE1_OFFSET /* second not available */ - -/* access to the data port is calculated: - CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ - -/* access to the registers is calculated: - CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ - -/* access to the alternate register is calculated: - CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x008 /* Offset for alternate registers */ - -#else /* IDE_USES_ISA_EMULATION */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0x79000000 /* start of ISA IO emulation */ - -/* How many IDE busses are available */ -#define CONFIG_SYS_IDE_MAXBUS 1 - -/* What IDE ports are available */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* first is available */ -#undef CONFIG_SYS_ATA_IDE1_OFFSET /* second not available */ - -/* access to the data port is calculated: - CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ - -/* access to the registers is calculated: - CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ - -/* access to the alternate register is calculated: - CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x03F0 /* Offset for alternate registers */ - -#endif /* IDE_USES_ISA_EMULATION */ - -#endif - -/* -#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 -#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 -*/ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * CONFIG_SYS_FLASH_BASE -> start address of internal flash - * CONFIG_SYS_MONITOR_BASE -> start of u-boot - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFE00000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ -#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MiB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization ## FIXME: lookup in datasheet - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_WRITE_SWAPPED_DATA /* swap Databytes between reading/writing */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#endif -/* let us changing anything in our environment */ -#define CONFIG_ENV_OVERWRITE - -/* - * NAND-FLASH stuff - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x77D00000 - -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ - -/* No command line, one static partition */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_SIZE 0x01000000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* - * Init Memory Controller: - * - */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE -#define FLASH_BASE1_PRELIM 0 - -/*----------------------------------------------------------------------- - * Some informations about the internal SRAM (OCM=On Chip Memory) - * - * CONFIG_SYS_OCM_DATA_ADDR -> location - * CONFIG_SYS_OCM_DATA_SIZE -> size -*/ - -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM): - * - we are using the internal 4k SRAM, so we don't need data cache mapping - * - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR - * - Stackpointer will be located to - * (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF) - * in arch/powerpc/cpu/ppc4xx/start.S - */ - -#undef CONFIG_SYS_INIT_DCACHE_CS -/* Where the internal SRAM starts */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR -/* Where the internal SRAM ends (only offset) */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x0F00 - -/* - - CONFIG_SYS_INIT_RAM_ADDR ------> ------------ lower address - | | - | ^ | - | | | - | | Stack | - CONFIG_SYS_GBL_DATA_OFFSET ----> ------------ - | | - | 64 Bytes | - | | - CONFIG_SYS_INIT_RAM_SIZE ------> ------------ higher address - (offset only) - -*/ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* Initial value of the stack pointern in internal SRAM */ -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* ################################################################################### */ -/* These defines will be used in arch/powerpc/cpu/ppc4xx/cpu_init.c to setup external chip selects */ -/* They are currently undefined cause they are initiaized in board/solidcard3/init.S */ - -/* This chip select accesses the boot device */ -/* It depends on boot select switch if this device is 16 or 8 bit */ - -#undef CONFIG_SYS_EBC_PB0AP -#undef CONFIG_SYS_EBC_PB0CR - -#undef CONFIG_SYS_EBC_PB1AP -#undef CONFIG_SYS_EBC_PB1CR - -#undef CONFIG_SYS_EBC_PB2AP -#undef CONFIG_SYS_EBC_PB2CR - -#undef CONFIG_SYS_EBC_PB3AP -#undef CONFIG_SYS_EBC_PB3CR - -#undef CONFIG_SYS_EBC_PB4AP -#undef CONFIG_SYS_EBC_PB4CR - -#undef CONFIG_SYS_EBC_PB5AP -#undef CONFIG_SYS_EBC_PB5CR - -#undef CONFIG_SYS_EBC_PB6AP -#undef CONFIG_SYS_EBC_PB6CR - -#undef CONFIG_SYS_EBC_PB7AP -#undef CONFIG_SYS_EBC_PB7CR - -#define CONFIG_SYS_EBC_CFG 0xb84ef000 - -#undef CONFIG_SDRAM_BANK0 /* use private SDRAM initialization */ -#undef CONFIG_SPD_EEPROM - -/* - * Define this to get more information about system configuration - */ -/* #define SC3_DEBUGOUT */ -#undef SC3_DEBUGOUT - -/*********************************************************************** - * External peripheral base address - ***********************************************************************/ - -#define CONFIG_SYS_ISA_MEM_BASE_ADDRESS 0x78000000 -/* - Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu. - Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die - das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen - auf ISA- und PCI-Zyklen) - */ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000 -/*#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0x79000000 */ - -/************************************************************ - * Video support - ************************************************************/ - -#ifdef USE_VGA_GRAPHICS -#define CONFIG_VIDEO /* To enable video controller support */ -#define CONFIG_VIDEO_CT69000 -#define CONFIG_CFB_CONSOLE -/* #define CONFIG_VIDEO_LOGO */ -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_SW_CURSOR -/* #define CONFIG_VIDEO_HW_CURSOR */ -#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */ - -#define VIDEO_HW_RECTFILL -#define VIDEO_HW_BITBLT - -#endif - -/************************************************************ - * Ident - ************************************************************/ -#define CONFIG_SC3_VERSION "r1.4" - -#define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x) - -#endif /* __CONFIG_H */ diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h index 668a91e..b8e1c47 100644 --- a/include/configs/socfpga_arria5.h +++ b/include/configs/socfpga_arria5.h @@ -37,7 +37,6 @@ #define CONFIG_CMD_USB #define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_REGEX /* Enable regular expression support */ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 41bb52b..e742acf 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -13,8 +13,6 @@ #define CONFIG_SYS_THUMB_BUILD -#define CONFIG_SOCFPGA - /* * High level configuration */ @@ -298,7 +296,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_CRC32_VERIFY /* Linker script for SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-socfpga/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 676144a..1227711 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -37,7 +37,6 @@ #define CONFIG_CMD_USB #define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_REGEX /* Enable regular expression support */ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 7f569fd..84cc19d 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -50,8 +50,14 @@ #define CONFIG_STM32_GPIO #define CONFIG_STM32_SERIAL - -#define CONFIG_STM32_USART1 +/* + * Configuration of the USART + * 1: TX:PA9 PX:PA10 + * 2: TX:PD5 RX:PD6 + * 3: TX:PC10 RX:PC11 + * 6: TX:PC6 RX:PC7 + */ +#define CONFIG_STM32_USART 1 #define CONFIG_STM32_HSE_HZ 8000000 diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index ab1e61c..e75e661 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -79,5 +79,7 @@ #define CONFIG_AUTOBOOT_STOP_STR " " #define CONFIG_AUTOBOOT_PROMPT \ "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay - +#define CONFIG_OF_SEPARATE +#define CONFIG_OF_CONTROL +#define CONFIG_OF_LIBFDT #endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index c8ebb54..2d6b815 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -297,6 +297,9 @@ extern int soft_i2c_gpio_scl; #endif #ifdef CONFIG_USB_EHCI +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_OHCI_SUNXI +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 #endif diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 3a88f22..b7ad7df 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -39,8 +39,6 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ @@ -104,6 +102,7 @@ #define CONFIG_MMC #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC +#define CONFIG_SUPPORT_EMMC_BOOT #define CONFIG_BOUNCE_BUFFER /* Ethernet */ @@ -163,6 +162,7 @@ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MX6 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB_MASS_STORAGE @@ -182,7 +182,13 @@ #ifdef CONFIG_USB_KEYBOARD #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE #define CONFIG_SYS_STDIO_DEREGISTER -#define CONFIG_PREBOOT "if hdmidet; then usb start; fi" +#define CONFIG_PREBOOT \ + "if hdmidet; then " \ + "usb start; " \ + "run set_con_usb_hdmi; " \ + "else " \ + "run set_con_serial; " \ + "fi;" #endif /* CONFIG_USB_KEYBOARD */ #endif /* CONFIG_CMD_USB */ @@ -241,9 +247,12 @@ "bootm 0x10800000 0x10d00000\0" \ "console=ttymxc0\0" \ "fan=gpio set 92\0" \ - "stdin=serial,usbkbd\0" \ - "stdout=serial,vga\0" \ - "stderr=serial,vga\0" + "set_con_serial=setenv stdin serial; " \ + "setenv stdout serial; " \ + "setenv stderr serial;\0" \ + "set_con_usb_hdmi=setenv stdin serial,usbkbd; " \ + "setenv stdout serial,vga; " \ + "setenv stderr serial,vga;\0" #define CONFIG_BOOTCOMMAND \ "mmc rescan; " \ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index c3ad8be..0cea795 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -34,7 +34,7 @@ #define STDIN_KBD_USB "" #endif -#ifdef CONFIG_VIDEO_TEGRA +#ifdef CONFIG_LCD #define STDOUT_LCD ",lcd" #else #define STDOUT_LCD "" @@ -50,6 +50,8 @@ #define BOARD_EXTRA_ENV_SETTINGS #endif +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 2cf1f68..7ae1792 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -89,6 +89,9 @@ #define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_STDIO_DEREGISTER +#endif /* * Miscellaneous configurable options diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 9eba5d5..252e607 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -26,13 +26,9 @@ */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* Environment information, boards can override if required */ -#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ #define CONFIG_STACKBASE 0x82800000 /* 40MB */ /*----------------------------------------------------------------------- @@ -64,10 +60,11 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ +#define CONFIG_LOADADDR 0x81000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=0x81000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index f2b3774..1aee5c8 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -18,13 +18,9 @@ */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* Environment information, boards can override if required */ -#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ #define CONFIG_STACKBASE 0x82800000 /* 40MB */ /*----------------------------------------------------------------------- @@ -56,10 +52,11 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ +#define CONFIG_LOADADDR 0x81000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=0x81000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 6330281..0841f33 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -24,13 +24,9 @@ */ #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ -/* Environment information, boards can override if required */ -#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */ #define CONFIG_STACKBASE 0x02800000 /* 40MB */ /*----------------------------------------------------------------------- @@ -62,10 +58,11 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ +#define CONFIG_LOADADDR 0x01000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x10000000\0" \ "pxefile_addr_r=0x10100000\0" \ - "kernel_addr_r=0x01000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "fdt_addr_r=0x02000000\0" \ "ramdisk_addr_r=0x02100000\0" diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index bfdbeb7..3e8e3c1 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -23,13 +23,9 @@ */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* Environment information, boards can override if required */ -#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ #define CONFIG_STACKBASE 0x82800000 /* 40MB */ /*----------------------------------------------------------------------- @@ -61,10 +57,11 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ +#define CONFIG_LOADADDR 0x81000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=0x81000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 110a4f8..f882942 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -279,4 +279,29 @@ #endif #endif /* !CONFIG_NOR_BOOT */ +/* Generic Environment Variables */ + +#ifdef CONFIG_CMD_NET +#define NETARGS \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ + "nfsopts=nolock\0" \ + "rootpath=/export/rootfs\0" \ + "netloadimage=tftp ${loadaddr} ${bootfile}\0" \ + "netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "run netloadimage; " \ + "run netloadfdt; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" + +#endif + #endif /* __CONFIG_TI_ARMV7_COMMON_H__ */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index f2be8d5..3383491 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -92,11 +92,6 @@ "vram=${vram} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ - "netargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=/dev/nfs " \ - "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ - "ip=dhcp\0" \ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ "source ${loadaddr}\0" \ @@ -123,13 +118,6 @@ "bootz ${loadaddr} - ${fdtaddr}; " \ "fi;" \ "fi;\0" \ - "netboot=echo Booting from network ...; " \ - "set env autoload no; " \ - "dhcp; " \ - "tftp ${loadaddr} ${bootfile}; " \ - "tftp ${fdtaddr} ${fdtfile}; " \ - "run netargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ "findfdt="\ "if test $board_name = omap5_uevm; then " \ "setenv fdtfile omap5-uevm.dtb; fi; " \ @@ -143,6 +131,7 @@ "echo WARNING: Could not determine device tree to use; fi; \0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \ DFUARGS \ + NETARGS \ #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h deleted file mode 100644 index 79c7fc5..0000000 --- a/include/configs/tny_a9260.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * - * Copyright (C) 2009 - * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com> - * - * Configuation settings for the Calao TNY-A9260 and TNY-A9G20 boards - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * SoC must be defined first, before hardware.h is included. - * In this case SoC is defined in boards.cfg. - */ -#include <asm/hardware.h> - -#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9G20_NANDFLASH) -#define CONFIG_ENV_IS_IN_NAND -#else -#define CONFIG_ENV_IS_IN_EEPROM -#endif - -/* Define actual evaluation board type from used processor type */ -#ifdef CONFIG_AT91SAM9G20 -# define CONFIG_TNY_A9G20 -# define MACH_TYPE_TNY_A9G20 2059 -# define CONFIG_MACH_TYPE MACH_TYPE_TNY_A9G20 -#else -# define CONFIG_TNY_A9260 -# define MACH_TYPE_TNY_A9260 2058 -# define CONFIG_MACH_TYPE MACH_TYPE_TNY_A9260 -#endif - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Hardware drivers - */ -#define CONFIG_ATMEL_LEGACY -#define CONFIG_AT91_GPIO - -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTDELAY 3 - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_SOURCE -#undef CONFIG_CMD_USB - -/* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ -# define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) - -/* SPI EEPROM */ -#define CONFIG_SPI -#define CONFIG_CMD_SPI -#define CONFIG_ATMEL_SPI - -#define CONFIG_CMD_EEPROM -#define CONFIG_SPI_M95XXX -#define CONFIG_SYS_EEPROM_SIZE 0x10000 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 - -/* NAND flash */ -#define CONFIG_CMD_NAND -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 - -/* NOR flash - no real flash on this board */ -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - -/* Env in EEPROM, bootstrap + u-boot in NAND*/ -#ifdef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_OFFSET 0x20 -#define CONFIG_ENV_SIZE 0x1000 -#endif - -/* Env, bootstrap and u-boot in NAND */ -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_OFFSET_REDUND 0x80000 -#define CONFIG_ENV_SIZE 0x20000 -#endif - -#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000" -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock1 " \ - "mtdparts=atmel_nand:16M(kernel)ro," \ - "120M(rootfs),-(other) " \ - "rw rootfstype=jffs2" - -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) - -#endif diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 012fa1c..66962aa 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -111,16 +111,19 @@ #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX -#define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ /* Fuses */ #define CONFIG_MXC_OCOTP #define CONFIG_CMD_FUSE #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC #define CONFIG_DOS_PARTITION #define CONFIG_CMD_PING diff --git a/include/configs/tseries.h b/include/configs/tseries.h index 1e41a12..9218533 100644 --- a/include/configs/tseries.h +++ b/include/configs/tseries.h @@ -16,7 +16,8 @@ /* ------------------------------------------------------------------------- */ #define CONFIG_AM335X_LCD #define CONFIG_LCD -#define CONFIG_LCD_NOSTDOUT +#define CONFIG_LCD_ROTATION +#define CONFIG_LCD_DT_SIMPLEFB #define CONFIG_SYS_WHITE_ON_BLACK #define LCD_BPP LCD_COLOR32 @@ -105,6 +106,7 @@ "mtdparts=" MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ + "${optargs_rot} " \ "root=mtd6 " \ "rootfstype=jffs2\0" \ "kernelsize=0x400000\0" \ @@ -114,6 +116,7 @@ "bootz ${loadaddr} - ${dtbaddr}\0" \ "defboot=run nandboot\0" \ "bootlimit=1\0" \ + "simplefb=1\0 " \ "altbootcmd=run usbscript\0" #else #define NANDARGS "" @@ -123,27 +126,23 @@ #define MMCARGS \ "dtbdev=mmc\0" \ "dtbpart=0:1\0" \ -"logo0=ext4load mmc 0:3 ${loadaddr} /PPTLogo.bmp.gz && " \ - "bmp display ${loadaddr} 0 0\0" \ -"logo1=ext4load mmc 0:1 ${loadaddr} /PPTLogo.bmp.gz && " \ - "bmp display ${loadaddr} 0 0\0" \ -"mmcroot0=setenv bootargs ${optargs} console=${console}\0" \ -"mmcroot1=setenv bootargs ${optargs} console=${console} root=/dev/mmcblk0p2 " \ - "rootfstype=ext4\0" \ +"mmcroot0=setenv bootargs ${optargs_rot} ${optargs} console=${console}\0" \ +"mmcroot1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \ + "root=/dev/mmcblk0p2 rootfstype=ext4\0" \ "mmcboot0=echo booting Updatesystem from mmc (ext4-fs) ...; " \ + "setenv simplefb 1; " \ "ext4load mmc 0:1 ${loadaddr} /${kernel}; " \ "ext4load mmc 0:1 ${ramaddr} /${ramdisk}; " \ "run mmcroot0; bootz ${loadaddr} ${ramaddr} ${dtbaddr};\0" \ "mmcboot1=echo booting PPT-OS from mmc (ext4-fs) ...; " \ + "setenv simplefb 0; " \ "ext4load mmc 0:2 ${loadaddr} /boot/${kernel}; " \ "run mmcroot1; bootz ${loadaddr} - ${dtbaddr};\0" \ -"defboot=run logo0 || run logo1; " \ - "ext4load mmc 0:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \ +"defboot=ext4load mmc 0:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \ "ext4load mmc 0:1 ${dtbaddr} /$dtb && run mmcboot0; " \ - "run ramboot; run usbupdate;\0" \ + "run ramboot; run usbscript;\0" \ "bootlimit=1\0" \ -"altbootcmd=run logo0 || run logo1; " \ - "run mmcboot0;\0" \ +"altbootcmd=run mmcboot0;\0" \ "upduboot=dhcp; " \ "tftp ${loadaddr} MLO && mmc write ${loadaddr} 100 100; " \ "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 400;\0" @@ -186,8 +185,6 @@ BUR_COMMON_ENV \ "then; else tftp ${dtbaddr} ${dtb}; fi;" \ "run mmcroot0; " \ "bootz ${loadaddr} ${ramaddr} ${dtbaddr}; fi;\0" \ -"usbupdate=echo Updating UBOOT from USB-Stick ...; " \ - "usb start && fatload usb 0 0x80000000 updateubootusb.img && source\0" \ "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \ "setenv autoload 0; " \ "dhcp && tftp 0x80000000 updateUBOOT.img && source;\0" \ diff --git a/include/displayport.h b/include/displayport.h new file mode 100644 index 0000000..f7c7e25 --- /dev/null +++ b/include/displayport.h @@ -0,0 +1,60 @@ +/* + * Copyright 2014 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DISPLAYPORT_H +#define _DISPLAYPORT_H + +struct udevice; +struct display_timing; + +/** + * display_port_read_edid() - Read information from EDID + * + * @dev: Device to read from + * @buf: Buffer to read into (should be EDID_SIZE bytes) + * @buf_size: Buffer size (should be EDID_SIZE) + * @return number of bytes read, <=0 for error + */ +int display_port_read_edid(struct udevice *dev, u8 *buf, int buf_size); + +/** + * display_port_enable() - Enable a display port device + * + * @dev: Device to enable + * @panel_bpp: Number of bits per pixel for panel + * @timing: Display timings + * @return 0 if OK, -ve on error + */ +int display_port_enable(struct udevice *dev, int panel_bpp, + const struct display_timing *timing); + +struct dm_display_port_ops { + /** + * read_edid() - Read information from EDID + * + * @dev: Device to read from + * @buf: Buffer to read into (should be EDID_SIZE bytes) + * @buf_size: Buffer size (should be EDID_SIZE) + * @return number of bytes read, <=0 for error + */ + int (*read_edid)(struct udevice *dev, u8 *buf, int buf_size); + + /** + * enable() - Enable the display port device + * + * @dev: Device to enable + * @panel_bpp: Number of bits per pixel for panel + * @timing: Display timings + * @return 0 if OK, -ve on error + */ + int (*enable)(struct udevice *dev, int panel_bpp, + const struct display_timing *timing); +}; + +#define display_port_get_ops(dev) \ + ((struct dm_display_port_ops *)(dev)->driver->ops) + +#endif diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 395e25a..4d737f4 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -22,30 +22,36 @@ enum uclass_id { UCLASS_I2C_EMUL, /* sandbox I2C device emulator */ UCLASS_PCI_EMUL, /* sandbox PCI device emulator */ UCLASS_USB_EMUL, /* sandbox USB bus device emulator */ - UCLASS_SIMPLE_BUS, + UCLASS_SIMPLE_BUS, /* bus with child devices */ - /* U-Boot uclasses start here */ + /* U-Boot uclasses start here - in alphabetical order */ + UCLASS_CPU, /* CPU, typically part of an SoC */ + UCLASS_CROS_EC, /* Chrome OS EC */ + UCLASS_DISPLAY_PORT, /* Display port video */ + UCLASS_ETH, /* Ethernet device */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ - UCLASS_SERIAL, /* Serial UART */ - UCLASS_SPI, /* SPI bus */ - UCLASS_SPI_GENERIC, /* Generic SPI flash target */ - UCLASS_SPI_FLASH, /* SPI flash */ - UCLASS_CROS_EC, /* Chrome OS EC */ - UCLASS_THERMAL, /* Thermal sensor */ UCLASS_I2C, /* I2C bus */ - UCLASS_I2C_GENERIC, /* Generic I2C device */ UCLASS_I2C_EEPROM, /* I2C EEPROM device */ + UCLASS_I2C_GENERIC, /* Generic I2C device */ + UCLASS_LPC, /* x86 'low pin count' interface */ + UCLASS_MASS_STORAGE, /* Mass storage device */ UCLASS_MOD_EXP, /* RSA Mod Exp device */ + UCLASS_PCH, /* x86 platform controller hub */ UCLASS_PCI, /* PCI bus */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */ - UCLASS_PCH, /* x86 platform controller hub */ - UCLASS_ETH, /* Ethernet device */ - UCLASS_LPC, /* x86 'low pin count' interface */ + UCLASS_RTC, /* Real time clock device */ + UCLASS_SERIAL, /* Serial UART */ + UCLASS_SPI, /* SPI bus */ + UCLASS_SPI_GENERIC, /* Generic SPI flash target */ + UCLASS_SPI_FLASH, /* SPI flash */ + UCLASS_THERMAL, /* Thermal sensor */ UCLASS_USB, /* USB bus */ - UCLASS_USB_HUB, /* USB hub */ UCLASS_USB_DEV_GENERIC, /* USB generic device */ - UCLASS_MASS_STORAGE, /* Mass storage device */ - UCLASS_CPU, /* CPU, typically part of an SoC */ + UCLASS_USB_HUB, /* USB hub */ + + /* Power Management */ + UCLASS_PMIC, /* PMIC I/O device */ + UCLASS_REGULATOR, /* REGULATOR device */ UCLASS_COUNT, UCLASS_INVALID = -1, diff --git a/include/dt-bindings/pmic/sandbox_pmic.h b/include/dt-bindings/pmic/sandbox_pmic.h new file mode 100644 index 0000000..c3d839b --- /dev/null +++ b/include/dt-bindings/pmic/sandbox_pmic.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_SANDBOX_PMIC_H_ +#define _DT_BINDINGS_SANDBOX_PMIC_H_ + +/* + * Sandbox PMIC - prepare reset values + * To provide the default (reset) values as in the real hardware, + * the registers are set in i2c pmic emul driver's probe() method. + * The default values are defined as below. + */ + +/* Buck operation mode IDs */ +#define BUCK_OM_OFF 0 +#define BUCK_OM_ON 1 +#define BUCK_OM_PWM 2 +#define BUCK_OM_COUNT 3 + +/* Ldo operation mode IDs */ +#define LDO_OM_OFF 0 +#define LDO_OM_ON 1 +#define LDO_OM_SLEEP 2 +#define LDO_OM_STANDBY 3 +#define LDO_OM_COUNT 4 + +/* [Value uV/uA]/[Mode ID] to register */ +#define VAL2REG(min, step, val) (((val) - (min)) / (step)) +#define VAL2OMREG(x) (x) + +#endif diff --git a/include/ec_commands.h b/include/ec_commands.h index 78baab1..7605066 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -1555,6 +1555,21 @@ struct ec_params_sb_wr_block { uint16_t data[32]; } __packed; +/* + * Entering Verified Boot Mode Command + * Default mode is VBOOT_MODE_NORMAL if EC did not receive this command. + * Valid Modes are: normal, developer, and recovery. + */ +#define EC_CMD_ENTERING_MODE 0xb6 + +struct ec_params_entering_mode { + int vboot_mode; +} __packed; + +#define VBOOT_MODE_NORMAL 0 +#define VBOOT_MODE_DEVELOPER 1 +#define VBOOT_MODE_RECOVERY 2 + /*****************************************************************************/ /* System commands */ diff --git a/include/edid.h b/include/edid.h index 18ec1d5..88b4b7d 100644 --- a/include/edid.h +++ b/include/edid.h @@ -15,6 +15,9 @@ #include <linux/types.h> +/* Size of the EDID data */ +#define EDID_SIZE 128 + #define GET_BIT(_x, _pos) \ (((_x) >> (_pos)) & 1) #define GET_BITS(_x, _pos_msb, _pos_lsb) \ @@ -287,4 +290,20 @@ int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, unsigned int *hmax, unsigned int *vmin, unsigned int *vmax); +struct display_timing; + +/** + * edid_get_timing() - Get basic digital display parameters + * + * @param buf Buffer containing EDID data + * @param buf_size Size of buffer in bytes + * @param timing Place to put preferring timing information + * @param panel_bits_per_colourp Place to put the number of bits per + * colour supported by the panel. This will be set to + * -1 if not available + * @return 0 if timings are OK, -ve on error + */ +int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, + int *panel_bits_per_colourp); + #endif /* __EDID_H_ */ diff --git a/include/fdtdec.h b/include/fdtdec.h index 6590470..6bf5f61 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -130,6 +130,9 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */ COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */ + COMPAT_NVIDIA_TEGRA124_DC, /* Tegra 124 Display controller */ + COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */ + COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ @@ -145,8 +148,6 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */ COMPAT_WOLFSON_WM8994_CODEC, /* Wolfson WM8994 Sound Codec */ COMPAT_GOOGLE_CROS_EC_KEYB, /* Google CROS_EC Keyboard */ - COMPAT_SAMSUNG_EXYNOS_EHCI, /* Exynos EHCI controller */ - COMPAT_SAMSUNG_EXYNOS5_XHCI, /* Exynos5 XHCI controller */ COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */ COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */ COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */ @@ -804,6 +805,83 @@ int fdtdec_decode_memory_region(const void *blob, int node, const char *mem_type, const char *suffix, fdt_addr_t *basep, fdt_size_t *sizep); +/* Display timings from linux include/video/display_timing.h */ +enum display_flags { + DISPLAY_FLAGS_HSYNC_LOW = 1 << 0, + DISPLAY_FLAGS_HSYNC_HIGH = 1 << 1, + DISPLAY_FLAGS_VSYNC_LOW = 1 << 2, + DISPLAY_FLAGS_VSYNC_HIGH = 1 << 3, + + /* data enable flag */ + DISPLAY_FLAGS_DE_LOW = 1 << 4, + DISPLAY_FLAGS_DE_HIGH = 1 << 5, + /* drive data on pos. edge */ + DISPLAY_FLAGS_PIXDATA_POSEDGE = 1 << 6, + /* drive data on neg. edge */ + DISPLAY_FLAGS_PIXDATA_NEGEDGE = 1 << 7, + DISPLAY_FLAGS_INTERLACED = 1 << 8, + DISPLAY_FLAGS_DOUBLESCAN = 1 << 9, + DISPLAY_FLAGS_DOUBLECLK = 1 << 10, +}; + +/* + * A single signal can be specified via a range of minimal and maximal values + * with a typical value, that lies somewhere inbetween. + */ +struct timing_entry { + u32 min; + u32 typ; + u32 max; +}; + +/* + * Single "mode" entry. This describes one set of signal timings a display can + * have in one setting. This struct can later be converted to struct videomode + * (see include/video/videomode.h). As each timing_entry can be defined as a + * range, one struct display_timing may become multiple struct videomodes. + * + * Example: hsync active high, vsync active low + * + * Active Video + * Video ______________________XXXXXXXXXXXXXXXXXXXXXX_____________________ + * |<- sync ->|<- back ->|<----- active ----->|<- front ->|<- sync.. + * | | porch | | porch | + * + * HSync _|¯¯¯¯¯¯¯¯¯¯|___________________________________________|¯¯¯¯¯¯¯¯¯ + * + * VSync ¯|__________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_________ + */ +struct display_timing { + struct timing_entry pixelclock; + + struct timing_entry hactive; /* hor. active video */ + struct timing_entry hfront_porch; /* hor. front porch */ + struct timing_entry hback_porch; /* hor. back porch */ + struct timing_entry hsync_len; /* hor. sync len */ + + struct timing_entry vactive; /* ver. active video */ + struct timing_entry vfront_porch; /* ver. front porch */ + struct timing_entry vback_porch; /* ver. back porch */ + struct timing_entry vsync_len; /* ver. sync len */ + + enum display_flags flags; /* display flags */ +}; + +/** + * fdtdec_decode_display_timing() - decode display timings + * + * Decode display timings from the supplied 'display-timings' node. + * See doc/device-tree-bindings/video/display-timing.txt for binding + * information. + * + * @param blob FDT blob + * @param node 'display-timing' node containing the timing subnodes + * @param index Index number to read (0=first timing subnode) + * @param config Place to put timings + * @return 0 if OK, -FDT_ERR_NOTFOUND if not found + */ +int fdtdec_decode_display_timing(const void *blob, int node, int index, + struct display_timing *config); /** * Set up the device tree ready for use */ diff --git a/include/i2c.h b/include/i2c.h index 6fd73fa..ddfebc4 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -54,6 +54,7 @@ struct dm_i2c_chip { uint flags; #ifdef CONFIG_SANDBOX struct udevice *emul; + bool test_mode; #endif }; @@ -124,6 +125,27 @@ int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags, struct udevice **devp); /** + * dm_i2c_reg_read() - Read a value from an I2C register + * + * This reads a single value from the given address in an I2C chip + * + * @addr: Address to read from + * @return value read, or -ve on error + */ +int dm_i2c_reg_read(struct udevice *dev, uint offset); + +/** + * dm_i2c_reg_write() - Write a value to an I2C register + * + * This writes a single value to the given address in an I2C chip + * + * @addr: Address to write to + * @val: Value to write (normally a byte) + * @return 0 on success, -ve on error + */ +int dm_i2c_reg_write(struct udevice *dev, uint offset, unsigned int val); + +/** * dm_i2c_set_bus_speed() - set the speed of a bus * * @bus: Bus to adjust @@ -171,8 +193,15 @@ int i2c_get_chip_flags(struct udevice *dev, uint *flagsp); * * @offset_len: New offset length value (typically 1 or 2) */ - int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len); + +/** + * i2c_get_offset_len() - get the offset length for a chip + * + * @return: Current offset length value (typically 1 or 2) + */ +int i2c_get_chip_offset_len(struct udevice *dev); + /** * i2c_deblock() - recover a bus that is in an unknown state * diff --git a/include/image.h b/include/image.h index 3844be6..60b924a 100644 --- a/include/image.h +++ b/include/image.h @@ -23,6 +23,7 @@ struct lmb; #ifdef USE_HOSTCC +#include <sys/types.h> /* new uImage format support enabled on host */ #define CONFIG_FIT 1 diff --git a/include/linux/drm_dp_helper.h b/include/linux/drm_dp_helper.h new file mode 100644 index 0000000..758e4a4 --- /dev/null +++ b/include/linux/drm_dp_helper.h @@ -0,0 +1,406 @@ +/* + * Copyright © 2008 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#ifndef _DRM_DP_HELPER_H_ +#define _DRM_DP_HELPER_H_ + +/* + * Unless otherwise noted, all values are from the DP 1.1a spec. Note that + * DP and DPCD versions are independent. Differences from 1.0 are not noted, + * 1.0 devices basically don't exist in the wild. + * + * Abbreviations, in chronological order: + * + * eDP: Embedded DisplayPort version 1 + * DPI: DisplayPort Interoperability Guideline v1.1a + * 1.2: DisplayPort 1.2 + * MST: Multistream Transport - part of DP 1.2a + * + * 1.2 formally includes both eDP and DPI definitions. + */ + +#define DP_AUX_I2C_WRITE 0x0 +#define DP_AUX_I2C_READ 0x1 +#define DP_AUX_I2C_STATUS 0x2 +#define DP_AUX_I2C_MOT 0x4 +#define DP_AUX_NATIVE_WRITE 0x8 +#define DP_AUX_NATIVE_READ 0x9 + +#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) +#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) +#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) +#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) + +#define DP_AUX_I2C_REPLY_ACK (0x0 << 2) +#define DP_AUX_I2C_REPLY_NACK (0x1 << 2) +#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) +#define DP_AUX_I2C_REPLY_MASK (0x3 << 2) + +/* AUX CH addresses */ +/* DPCD */ +#define DP_DPCD_REV 0x000 + +#define DP_MAX_LINK_RATE 0x001 + +#define DP_MAX_LANE_COUNT 0x002 +# define DP_MAX_LANE_COUNT_MASK 0x1f +# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ +# define DP_ENHANCED_FRAME_CAP (1 << 7) + +#define DP_MAX_DOWNSPREAD 0x003 +# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) + +#define DP_NORP 0x004 + +#define DP_DOWNSTREAMPORT_PRESENT 0x005 +# define DP_DWN_STRM_PORT_PRESENT (1 << 0) +# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 +# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) +# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) +# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) +# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) +# define DP_FORMAT_CONVERSION (1 << 3) +# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ + +#define DP_MAIN_LINK_CHANNEL_CODING 0x006 + +#define DP_DOWN_STREAM_PORT_COUNT 0x007 +# define DP_PORT_COUNT_MASK 0x0f +# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ +# define DP_OUI_SUPPORT (1 << 7) + +#define DP_I2C_SPEED_CAP 0x00c /* DPI */ +# define DP_I2C_SPEED_1K 0x01 +# define DP_I2C_SPEED_5K 0x02 +# define DP_I2C_SPEED_10K 0x04 +# define DP_I2C_SPEED_100K 0x08 +# define DP_I2C_SPEED_400K 0x10 +# define DP_I2C_SPEED_1M 0x20 + +#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ + +/* Multiple stream transport */ +#define DP_FAUX_CAP 0x020 /* 1.2 */ +# define DP_FAUX_CAP_1 (1 << 0) + +#define DP_MSTM_CAP 0x021 /* 1.2 */ +# define DP_MST_CAP (1 << 0) + +#define DP_GUID 0x030 /* 1.2 */ + +#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ +# define DP_PSR_IS_SUPPORTED 1 +#define DP_PSR_CAPS 0x071 /* XXX 1.2? */ +# define DP_PSR_NO_TRAIN_ON_EXIT 1 +# define DP_PSR_SETUP_TIME_330 (0 << 1) +# define DP_PSR_SETUP_TIME_275 (1 << 1) +# define DP_PSR_SETUP_TIME_220 (2 << 1) +# define DP_PSR_SETUP_TIME_165 (3 << 1) +# define DP_PSR_SETUP_TIME_110 (4 << 1) +# define DP_PSR_SETUP_TIME_55 (5 << 1) +# define DP_PSR_SETUP_TIME_0 (6 << 1) +# define DP_PSR_SETUP_TIME_MASK (7 << 1) +# define DP_PSR_SETUP_TIME_SHIFT 1 + +/* + * 0x80-0x8f describe downstream port capabilities, but there are two layouts + * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, + * each port's descriptor is one byte wide. If it was set, each port's is + * four bytes wide, starting with the one byte from the base info. As of + * DP interop v1.1a only VGA defines additional detail. + */ + +/* offset 0 */ +#define DP_DOWNSTREAM_PORT_0 0x80 +# define DP_DS_PORT_TYPE_MASK (7 << 0) +# define DP_DS_PORT_TYPE_DP 0 +# define DP_DS_PORT_TYPE_VGA 1 +# define DP_DS_PORT_TYPE_DVI 2 +# define DP_DS_PORT_TYPE_HDMI 3 +# define DP_DS_PORT_TYPE_NON_EDID 4 +# define DP_DS_PORT_HPD (1 << 3) +/* offset 1 for VGA is maximum megapixels per second / 8 */ +/* offset 2 */ +# define DP_DS_VGA_MAX_BPC_MASK (3 << 0) +# define DP_DS_VGA_8BPC 0 +# define DP_DS_VGA_10BPC 1 +# define DP_DS_VGA_12BPC 2 +# define DP_DS_VGA_16BPC 3 + +/* link configuration */ +#define DP_LINK_BW_SET 0x100 +# define DP_LINK_BW_1_62 0x06 +# define DP_LINK_BW_2_7 0x0a +# define DP_LINK_BW_5_4 0x14 /* 1.2 */ + +#define DP_LANE_COUNT_SET 0x101 +# define DP_LANE_COUNT_MASK 0x0f +# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) + +#define DP_TRAINING_PATTERN_SET 0x102 +# define DP_TRAINING_PATTERN_DISABLE 0 +# define DP_TRAINING_PATTERN_1 1 +# define DP_TRAINING_PATTERN_2 2 +# define DP_TRAINING_PATTERN_3 3 /* 1.2 */ +# define DP_TRAINING_PATTERN_MASK 0x3 + +# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) +# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) +# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) +# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) +# define DP_LINK_QUAL_PATTERN_MASK (3 << 2) + +# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) +# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) + +# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) +# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) +# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) +# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) + +#define DP_TRAINING_LANE0_SET 0x103 +#define DP_TRAINING_LANE1_SET 0x104 +#define DP_TRAINING_LANE2_SET 0x105 +#define DP_TRAINING_LANE3_SET 0x106 + +# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 +# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 +# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) + +# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) + +# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 +# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) + +#define DP_DOWNSPREAD_CTRL 0x107 +# define DP_SPREAD_AMP_0_5 (1 << 4) +# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ + +#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 +# define DP_SET_ANSI_8B10B (1 << 0) + +#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ +/* bitmask as for DP_I2C_SPEED_CAP */ + +#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ + +#define DP_MSTM_CTRL 0x111 /* 1.2 */ +# define DP_MST_EN (1 << 0) +# define DP_UP_REQ_EN (1 << 1) +# define DP_UPSTREAM_IS_SRC (1 << 2) + +#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ +# define DP_PSR_ENABLE (1 << 0) +# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) +# define DP_PSR_CRC_VERIFICATION (1 << 2) +# define DP_PSR_FRAME_CAPTURE (1 << 3) + +#define DP_ADAPTER_CTRL 0x1a0 +# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) + +#define DP_BRANCH_DEVICE_CTRL 0x1a1 +# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) + +#define DP_PAYLOAD_ALLOCATE_SET 0x1c0 +#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 +#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 + +#define DP_SINK_COUNT 0x200 +/* prior to 1.2 bit 7 was reserved mbz */ +# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) +# define DP_SINK_CP_READY (1 << 6) + +#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 +# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) +# define DP_AUTOMATED_TEST_REQUEST (1 << 1) +# define DP_CP_IRQ (1 << 2) +# define DP_MCCS_IRQ (1 << 3) +# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ +# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ +# define DP_SINK_SPECIFIC_IRQ (1 << 6) + +#define DP_LANE0_1_STATUS 0x202 +#define DP_LANE2_3_STATUS 0x203 +# define DP_LANE_CR_DONE (1 << 0) +# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) +# define DP_LANE_SYMBOL_LOCKED (1 << 2) + +#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ + DP_LANE_CHANNEL_EQ_DONE | \ + DP_LANE_SYMBOL_LOCKED) + +#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 + +#define DP_INTERLANE_ALIGN_DONE (1 << 0) +#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) +#define DP_LINK_STATUS_UPDATED (1 << 7) + +#define DP_SINK_STATUS 0x205 +#define DP_SINK_STATUS_PORT0_IN_SYNC (1 << 0) + +#define DP_RECEIVE_PORT_0_STATUS (1 << 0) +#define DP_RECEIVE_PORT_1_STATUS (1 << 1) + +#define DP_ADJUST_REQUEST_LANE0_1 0x206 +#define DP_ADJUST_REQUEST_LANE2_3 0x207 +# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 +# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 +# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c +# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 +# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 +# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 +# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 +# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 + +#define DP_TEST_REQUEST 0x218 +# define DP_TEST_LINK_TRAINING (1 << 0) +# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) +# define DP_TEST_LINK_EDID_READ (1 << 2) +# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ +# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ + +#define DP_TEST_LINK_RATE 0x219 +# define DP_LINK_RATE_162 (0x6) +# define DP_LINK_RATE_27 (0xa) + +#define DP_TEST_LANE_COUNT 0x220 + +#define DP_TEST_PATTERN 0x221 + +#define DP_TEST_CRC_R_CR 0x240 +#define DP_TEST_CRC_G_Y 0x242 +#define DP_TEST_CRC_B_CB 0x244 + +#define DP_TEST_SINK_MISC 0x246 +#define DP_TEST_CRC_SUPPORTED (1 << 5) + +#define DP_TEST_RESPONSE 0x260 +# define DP_TEST_ACK (1 << 0) +# define DP_TEST_NAK (1 << 1) +# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) + +#define DP_TEST_EDID_CHECKSUM 0x261 + +#define DP_TEST_SINK 0x270 +#define DP_TEST_SINK_START (1 << 0) + +#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ +# define DP_PAYLOAD_TABLE_UPDATED (1 << 0) +# define DP_PAYLOAD_ACT_HANDLED (1 << 1) + +#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ +/* up to ID_SLOT_63 at 0x2ff */ + +#define DP_SOURCE_OUI 0x300 +#define DP_SINK_OUI 0x400 +#define DP_BRANCH_OUI 0x500 + +#define DP_SET_POWER 0x600 +# define DP_SET_POWER_D0 0x1 +# define DP_SET_POWER_D3 0x2 +# define DP_SET_POWER_MASK 0x3 + +#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ + +#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ +/* 0-5 sink count */ +# define DP_SINK_COUNT_CP_READY (1 << 6) + +#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ + +#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ + +#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ + +#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ +# define DP_PSR_LINK_CRC_ERROR (1 << 0) +# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) + +#define DP_PSR_ESI 0x2007 /* XXX 1.2? */ +# define DP_PSR_CAPS_CHANGE (1 << 0) + +#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ +# define DP_PSR_SINK_INACTIVE 0 +# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 +# define DP_PSR_SINK_ACTIVE_RFB 2 +# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 +# define DP_PSR_SINK_ACTIVE_RESYNC 4 +# define DP_PSR_SINK_INTERNAL_ERROR 7 +# define DP_PSR_SINK_STATE_MASK 0x07 + +/* DP 1.2 Sideband message defines */ +/* peer device type - DP 1.2a Table 2-92 */ +#define DP_PEER_DEVICE_NONE 0x0 +#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 +#define DP_PEER_DEVICE_MST_BRANCHING 0x2 +#define DP_PEER_DEVICE_SST_SINK 0x3 +#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 + +/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ +#define DP_LINK_ADDRESS 0x01 +#define DP_CONNECTION_STATUS_NOTIFY 0x02 +#define DP_ENUM_PATH_RESOURCES 0x10 +#define DP_ALLOCATE_PAYLOAD 0x11 +#define DP_QUERY_PAYLOAD 0x12 +#define DP_RESOURCE_STATUS_NOTIFY 0x13 +#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 +#define DP_REMOTE_DPCD_READ 0x20 +#define DP_REMOTE_DPCD_WRITE 0x21 +#define DP_REMOTE_I2C_READ 0x22 +#define DP_REMOTE_I2C_WRITE 0x23 +#define DP_POWER_UP_PHY 0x24 +#define DP_POWER_DOWN_PHY 0x25 +#define DP_SINK_EVENT_NOTIFY 0x30 +#define DP_QUERY_STREAM_ENC_STATUS 0x38 + +/* DP 1.2 MST sideband nak reasons - table 2.84 */ +#define DP_NAK_WRITE_FAILURE 0x01 +#define DP_NAK_INVALID_READ 0x02 +#define DP_NAK_CRC_FAILURE 0x03 +#define DP_NAK_BAD_PARAM 0x04 +#define DP_NAK_DEFER 0x05 +#define DP_NAK_LINK_FAILURE 0x06 +#define DP_NAK_NO_RESOURCES 0x07 +#define DP_NAK_DPCD_FAIL 0x08 +#define DP_NAK_I2C_NAK 0x09 +#define DP_NAK_ALLOCATE_FAIL 0x0a + +#define MODE_I2C_START 1 +#define MODE_I2C_WRITE 2 +#define MODE_I2C_READ 4 +#define MODE_I2C_STOP 8 + +/* Rest of file omitted as it is not used in U-Boot */ + +#endif /* _DRM_DP_HELPER_H_ */ diff --git a/include/os.h b/include/os.h index a758f09..ffbdce8 100644 --- a/include/os.h +++ b/include/os.h @@ -13,6 +13,7 @@ #include <linux/types.h> +struct rtc_time; struct sandbox_state; /** @@ -277,4 +278,14 @@ int os_read_ram_buf(const char *fname); */ int os_jump_to_image(const void *dest, int size); +/** + * Read the current system time + * + * This reads the current Local Time and places it into the provided + * structure. + * + * @param rt Place to put system time + */ +void os_localtime(struct rtc_time *rt); + #endif diff --git a/include/power/as3722.h b/include/power/as3722.h index aa966d2..0f22482 100644 --- a/include/power/as3722.h +++ b/include/power/as3722.h @@ -23,5 +23,8 @@ int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio, unsigned long flags); int as3722_gpio_direction_output(struct udevice *pmic, unsigned int gpio, unsigned int level); +int as3722_read(struct udevice *pmic, u8 reg, u8 *value); +int as3722_write(struct udevice *pmic, u8 reg, u8 value); +int as3722_get(struct udevice **devp); #endif /* __POWER_AS3722_H__ */ diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h index b0e4255..2300352 100644 --- a/include/power/max77686_pmic.h +++ b/include/power/max77686_pmic.h @@ -122,11 +122,17 @@ enum { MAX77686_REG_PMIC_BBAT = 0x7e, MAX77686_REG_PMIC_32KHZ, - PMIC_NUM_OF_REGS, + MAX77686_NUM_OF_REGS, }; /* I2C device address for pmic max77686 */ -#define MAX77686_I2C_ADDR (0x12 >> 1) +#define MAX77686_I2C_ADDR (0x12 >> 1) +#define MAX77686_LDO_NUM 26 +#define MAX77686_BUCK_NUM 9 + +/* Drivers name */ +#define MAX77686_LDO_DRIVER "max77686_ldo" +#define MAX77686_BUCK_DRIVER "max77686_buck" enum { REG_DISABLE = 0, @@ -143,23 +149,29 @@ enum { enum { OPMODE_OFF = 0, - OPMODE_STANDBY, OPMODE_LPM, + OPMODE_STANDBY, + OPMODE_STANDBY_LPM, OPMODE_ON, }; +#ifdef CONFIG_POWER int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV); int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode); int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV); int max77686_set_buck_mode(struct pmic *p, int buck, char opmode); +#endif #define MAX77686_LDO_VOLT_MAX_HEX 0x3f #define MAX77686_LDO_VOLT_MASK 0x3f #define MAX77686_LDO_MODE_MASK 0xc0 #define MAX77686_LDO_MODE_OFF (0x00 << 0x06) +#define MAX77686_LDO_MODE_LPM (0x01 << 0x06) #define MAX77686_LDO_MODE_STANDBY (0x01 << 0x06) -#define MAX77686_LDO_MODE_LPM (0x02 << 0x06) +#define MAX77686_LDO_MODE_STANDBY_LPM (0x02 << 0x06) #define MAX77686_LDO_MODE_ON (0x03 << 0x06) +#define MAX77686_BUCK234_VOLT_MAX_HEX 0xff +#define MAX77686_BUCK234_VOLT_MASK 0xff #define MAX77686_BUCK_VOLT_MAX_HEX 0x3f #define MAX77686_BUCK_VOLT_MASK 0x3f #define MAX77686_BUCK_MODE_MASK 0x03 @@ -170,6 +182,15 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode); #define MAX77686_BUCK_MODE_LPM 0x02 #define MAX77686_BUCK_MODE_ON 0x03 +/* For regulator hex<->volt conversion */ +#define MAX77686_LDO_UV_MIN 800000 /* Minimum LDO uV value */ +#define MAX77686_LDO_UV_LSTEP 25000 /* uV lower value step */ +#define MAX77686_LDO_UV_HSTEP 50000 /* uV higher value step */ +#define MAX77686_BUCK_UV_LMIN 600000 /* Lower minimun BUCK value */ +#define MAX77686_BUCK_UV_HMIN 750000 /* Higher minimun BUCK value */ +#define MAX77686_BUCK_UV_LSTEP 12500 /* uV lower value step */ +#define MAX77686_BUCK_UV_HSTEP 50000 /* uV higher value step */ + /* Buck1 1 volt value */ #define MAX77686_BUCK1OUT_1V 0x5 /* Buck1 1.05 volt value */ diff --git a/include/power/pmic.h b/include/power/pmic.h index afbc5aa..eb152ef 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -1,4 +1,7 @@ /* + * Copyright (C) 2014-2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * * Copyright (C) 2011-2012 Samsung Electronics * Lukasz Majewski <l.majewski@samsung.com> * @@ -8,11 +11,14 @@ #ifndef __CORE_PMIC_H_ #define __CORE_PMIC_H_ -#include <linux/list.h> #include <i2c.h> +#include <spi.h> +#include <linux/list.h> #include <power/power_chrg.h> enum { PMIC_I2C, PMIC_SPI, PMIC_NONE}; + +#ifdef CONFIG_POWER enum { I2C_PMIC, I2C_NUM, }; enum { PMIC_READ, PMIC_WRITE, }; enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, }; @@ -77,7 +83,190 @@ struct pmic { struct pmic *parent; struct list_head list; }; +#endif /* CONFIG_POWER */ + +#ifdef CONFIG_DM_PMIC +/** + * U-Boot PMIC Framework + * ===================== + * + * UCLASS_PMIC - This is designed to provide an I/O interface for PMIC devices. + * + * For the multi-function PMIC devices, this can be used as parent I/O device + * for each IC's interface. Then, each child uses its parent for read/write. + * + * The driver model tree could look like this: + * + *_ root device + * |_ BUS 0 device (e.g. I2C0) - UCLASS_I2C/SPI/... + * | |_ PMIC device (READ/WRITE ops) - UCLASS_PMIC + * | |_ REGULATOR device (ldo/buck/... ops) - UCLASS_REGULATOR + * | |_ CHARGER device (charger ops) - UCLASS_CHARGER (in the future) + * | |_ MUIC device (microUSB connector ops) - UCLASS_MUIC (in the future) + * | |_ ... + * | + * |_ BUS 1 device (e.g. I2C1) - UCLASS_I2C/SPI/... + * |_ PMIC device (READ/WRITE ops) - UCLASS_PMIC + * |_ RTC device (rtc ops) - UCLASS_RTC (in the future) + * + * We can find two PMIC cases in boards design: + * - single I/O interface + * - multiple I/O interfaces + * We bind a single PMIC device for each interface, to provide an I/O for + * its child devices. And each child usually implements a different function, + * controlled by the same interface. + * + * The binding should be done automatically. If device tree nodes/subnodes are + * proper defined, then: + * + * |_ the ROOT driver will bind the device for I2C/SPI node: + * |_ the I2C/SPI driver should bind a device for pmic node: + * |_ the PMIC driver should bind devices for its childs: + * |_ regulator (child) + * |_ charger (child) + * |_ other (child) + * + * The same for other device nodes, for multi-interface PMIC. + * + * Note: + * Each PMIC interface driver should use a different compatible string. + * + * If a PMIC child device driver needs access the PMIC-specific registers, + * it need know only the register address and the access can be done through + * the parent pmic driver. Like in the example: + * + *_ root driver + * |_ dev: bus I2C0 - UCLASS_I2C + * | |_ dev: my_pmic (read/write) (is parent) - UCLASS_PMIC + * | |_ dev: my_regulator (set value/etc..) (is child) - UCLASS_REGULATOR + * + * To ensure such device relationship, the pmic device driver should also bind + * all its child devices, like in the example below. It can be done by calling + * the 'pmic_bind_children()' - please refer to the function description, which + * can be found in this header file. This function, should be called inside the + * driver's bind() method. + * + * For the example driver, please refer the MAX77686 driver: + * - 'drivers/power/pmic/max77686.c' + */ + +/** + * struct dm_pmic_ops - PMIC device I/O interface + * + * Should be implemented by UCLASS_PMIC device drivers. The standard + * device operations provides the I/O interface for it's childs. + * + * @reg_count: device's register count + * @read: read 'len' bytes at "reg" and store it into the 'buffer' + * @write: write 'len' bytes from the 'buffer' to the register at 'reg' address + */ +struct dm_pmic_ops { + int (*reg_count)(struct udevice *dev); + int (*read)(struct udevice *dev, uint reg, uint8_t *buffer, int len); + int (*write)(struct udevice *dev, uint reg, const uint8_t *buffer, + int len); +}; + +/** + * enum pmic_op_type - used for various pmic devices operation calls, + * for reduce a number of lines with the same code for read/write or get/set. + * + * @PMIC_OP_GET - get operation + * @PMIC_OP_SET - set operation +*/ +enum pmic_op_type { + PMIC_OP_GET, + PMIC_OP_SET, +}; + +/** + * struct pmic_child_info - basic device's child info for bind child nodes with + * the driver by the node name prefix and driver name. This is a helper struct + * for function: pmic_bind_children(). + * + * @prefix - child node name prefix (or its name if is unique or single) + * @driver - driver name for the sub-node with prefix + */ +struct pmic_child_info { + const char *prefix; + const char *driver; +}; + +/* drivers/power/pmic-uclass.c */ + +/** + * pmic_bind_children() - bind drivers for given parent pmic, using child info + * found in 'child_info' array. + * + * @pmic - pmic device - the parent of found child's + * @child_info - N-childs info array + * @return a positive number of childs, or 0 if no child found (error) + * + * Note: For N-childs the child_info array should have N+1 entries and the last + * entry prefix should be NULL - the same as for drivers compatible. + * + * For example, a single prefix info (N=1): + * static const struct pmic_child_info bind_info[] = { + * { .prefix = "ldo", .driver = "ldo_driver" }, + * { }, + * }; + * + * This function is useful for regulator sub-nodes: + * my_regulator@0xa { + * reg = <0xa>; + * (pmic - bind automatically by compatible) + * compatible = "my_pmic"; + * ... + * (pmic's childs - bind by pmic_bind_children()) + * (nodes prefix: "ldo", driver: "my_regulator_ldo") + * ldo1 { ... }; + * ldo2 { ... }; + * + * (nodes prefix: "buck", driver: "my_regulator_buck") + * buck1 { ... }; + * buck2 { ... }; + * }; + */ +int pmic_bind_children(struct udevice *pmic, int offset, + const struct pmic_child_info *child_info); + +/** + * pmic_get: get the pmic device using its name + * + * @name - device name + * @devp - returned pointer to the pmic device + * @return 0 on success or negative value of errno. + * + * The returned devp device can be used with pmic_read/write calls + */ +int pmic_get(const char *name, struct udevice **devp); + +/** + * pmic_reg_count: get the pmic register count + * + * The required pmic device can be obtained by 'pmic_get()' + * + * @dev - pointer to the UCLASS_PMIC device + * @return register count value on success or negative value of errno. + */ +int pmic_reg_count(struct udevice *dev); + +/** + * pmic_read/write: read/write to the UCLASS_PMIC device + * + * The required pmic device can be obtained by 'pmic_get()' + * + * @pmic - pointer to the UCLASS_PMIC device + * @reg - device register offset + * @buffer - pointer to read/write buffer + * @len - byte count for read/write + * @return 0 on success or negative value of errno. + */ +int pmic_read(struct udevice *dev, uint reg, uint8_t *buffer, int len); +int pmic_write(struct udevice *dev, uint reg, const uint8_t *buffer, int len); +#endif /* CONFIG_DM_PMIC */ +#ifdef CONFIG_POWER int pmic_init(unsigned char bus); int power_init_board(void); int pmic_dialog_init(unsigned char bus); @@ -88,6 +277,7 @@ int pmic_probe(struct pmic *p); int pmic_reg_read(struct pmic *p, u32 reg, u32 *val); int pmic_reg_write(struct pmic *p, u32 reg, u32 val); int pmic_set_output(struct pmic *p, u32 reg, int ldo, int on); +#endif #define pmic_i2c_addr (p->hw.i2c.addr) #define pmic_i2c_tx_num (p->hw.i2c.tx_num) diff --git a/include/power/regulator.h b/include/power/regulator.h new file mode 100644 index 0000000..03a2cef --- /dev/null +++ b/include/power/regulator.h @@ -0,0 +1,386 @@ +/* + * Copyright (C) 2014-2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _INCLUDE_REGULATOR_H_ +#define _INCLUDE_REGULATOR_H_ + +/** + * U-Boot Voltage/Current Regulator + * ================================ + * + * The regulator API is based on a driver model, with the device tree support. + * And this header describes the functions and data types for the uclass id: + * 'UCLASS_REGULATOR' and the regulator driver API. + * + * The regulator uclass - is based on uclass platform data which is allocated, + * automatically for each regulator device on bind and 'dev->uclass_platdata' + * points to it. The data type is: 'struct dm_regulator_uclass_platdata'. + * The uclass file: 'drivers/power/regulator/regulator-uclass.c' + * + * The regulator device - is based on driver's model 'struct udevice'. + * The API can use regulator name in two meanings: + * - devname - the regulator device's name: 'dev->name' + * - platname - the device's platdata's name. So in the code it looks like: + * 'uc_pdata = dev->uclass_platdata'; 'name = uc_pdata->name'. + * + * The regulator device driver - provide an implementation of uclass operations + * pointed by 'dev->driver->ops' as a struct of type 'struct dm_regulator_ops'. + * + * To proper bind the regulator device, the device tree node should provide + * regulator constraints, like in the example below: + * + * ldo1 { + * regulator-name = "VDD_MMC_1.8V"; (must be unique for proper bind) + * regulator-min-microvolt = <1000000>; (optional) + * regulator-max-microvolt = <1000000>; (optional) + * regulator-min-microamp = <1000>; (optional) + * regulator-max-microamp = <1000>; (optional) + * regulator-always-on; (optional) + * regulator-boot-on; (optional) + * }; + * + * Note: For the proper operation, at least name constraint is needed, since + * it can be used when calling regulator_get_by_platname(). And the mandatory + * rule for this name is, that it must be globally unique for the single dts. + * + * Regulator bind: + * For each regulator device, the device_bind() should be called with passed + * device tree offset. This is required for this uclass's '.post_bind' method, + * which does the scan on the device node, for the 'regulator-name' constraint. + * If the parent is not a PMIC device, and the child is not bind by function: + * 'pmic_bind_childs()', then it's recommended to bind the device by call to + * dm_scan_fdt_node() - this is usually done automatically for bus devices, + * as a post bind method. + * + * Regulator get: + * Having the device's name constraint, we can call regulator_by_platname(), + * to find the required regulator. Before return, the regulator is probed, + * and the rest of its constraints are put into the device's uclass platform + * data, by the uclass regulator '.pre_probe' method. + * + * For more info about PMIC bind, please refer to file: 'include/power/pmic.h' + * + * Note: + * Please do not use the device_bind_by_name() function, since it pass '-1' as + * device node offset - and the bind will fail on uclass .post_bind method, + * because of missing 'regulator-name' constraint. + * + * + * Fixed Voltage/Current Regulator + * =============================== + * + * When fixed voltage regulator is needed, then enable the config: + * - CONFIG_DM_REGULATOR_FIXED + * + * The driver file: 'drivers/power/regulator/fixed.c', provides basic support + * for control the GPIO, and return the device tree constraint values. + * + * To bind the fixed voltage regulator device, we usually use a 'simple-bus' + * node as a parent. And 'regulator-fixed' for the driver compatible. This is + * the same as in the kernel. The example node of fixed regulator: + * + * simple-bus { + * compatible = "simple-bus"; + * #address-cells = <1>; + * #size-cells = <0>; + * + * blue_led { + * compatible = "regulator-fixed"; + * regulator-name = "VDD_LED_3.3V"; + * regulator-min-microvolt = <3300000>; + * regulator-max-microvolt = <3300000>; + * gpio = <&gpc1 0 GPIO_ACTIVE_LOW>; + * }; + * }; + * + * The fixed regulator devices also provide regulator uclass platform data. And + * devices bound from such node, can use the regulator drivers API. +*/ + +/* enum regulator_type - used for regulator_*() variant calls */ +enum regulator_type { + REGULATOR_TYPE_LDO = 0, + REGULATOR_TYPE_BUCK, + REGULATOR_TYPE_DVS, + REGULATOR_TYPE_FIXED, + REGULATOR_TYPE_OTHER, +}; + +/** + * struct dm_regulator_mode - this structure holds an information about + * each regulator operation mode. Probably in most cases - an array. + * This will be probably a driver-static data, since it is device-specific. + * + * @id - a driver-specific mode id + * @register_value - a driver-specific value for its mode id + * @name - the name of mode - used for regulator command + * Note: + * The field 'id', should be always a positive number, since the negative values + * are reserved for the errno numbers when returns the mode id. + */ +struct dm_regulator_mode { + int id; /* Set only as >= 0 (negative value is reserved for errno) */ + int register_value; + const char *name; +}; + +/** + * struct dm_regulator_uclass_platdata - pointed by dev->uclass_platdata, and + * allocated on each regulator bind. This structure holds an information + * about each regulator's constraints and supported operation modes. + * There is no "step" voltage value - so driver should take care of this. + * + * @type - one of 'enum regulator_type' + * @mode - pointer to the regulator mode (array if more than one) + * @mode_count - number of '.mode' entries + * @min_uV* - minimum voltage (micro Volts) + * @max_uV* - maximum voltage (micro Volts) + * @min_uA* - minimum amperage (micro Amps) + * @max_uA* - maximum amperage (micro Amps) + * @always_on* - bool type, true or false + * @boot_on* - bool type, true or false + * @name** - fdt regulator name - should be taken from the device tree + * + * Note: + * * - set automatically on device probe by the uclass's '.pre_probe' method. + * ** - set automatically on device bind by the uclass's '.post_bind' method. + * The constraints: type, mode, mode_count, can be set by device driver, e.g. + * by the driver '.probe' method. + */ +struct dm_regulator_uclass_platdata { + enum regulator_type type; + struct dm_regulator_mode *mode; + int mode_count; + int min_uV; + int max_uV; + int min_uA; + int max_uA; + bool always_on; + bool boot_on; + const char *name; +}; + +/* Regulator device operations */ +struct dm_regulator_ops { + /** + * The regulator output value function calls operates on a micro Volts. + * + * get/set_value - get/set output value of the given output number + * @dev - regulator device + * Sets: + * @uV - set the output value [micro Volts] + * @return output value [uV] on success or negative errno if fail. + */ + int (*get_value)(struct udevice *dev); + int (*set_value)(struct udevice *dev, int uV); + + /** + * The regulator output current function calls operates on a micro Amps. + * + * get/set_current - get/set output current of the given output number + * @dev - regulator device + * Sets: + * @uA - set the output current [micro Amps] + * @return output value [uA] on success or negative errno if fail. + */ + int (*get_current)(struct udevice *dev); + int (*set_current)(struct udevice *dev, int uA); + + /** + * The most basic feature of the regulator output is its enable state. + * + * get/set_enable - get/set enable state of the given output number + * @dev - regulator device + * Sets: + * @enable - set true - enable or false - disable + * @return true/false for get; or 0 / -errno for set. + */ + bool (*get_enable)(struct udevice *dev); + int (*set_enable)(struct udevice *dev, bool enable); + + /** + * The 'get/set_mode()' function calls should operate on a driver- + * specific mode id definitions, which should be found in: + * field 'id' of struct dm_regulator_mode. + * + * get/set_mode - get/set operation mode of the given output number + * @dev - regulator device + * Sets + * @mode_id - set output mode id (struct dm_regulator_mode->id) + * @return id/0 for get/set on success or negative errno if fail. + * Note: + * The field 'id' of struct type 'dm_regulator_mode', should be always + * a positive number, since the negative is reserved for the error. + */ + int (*get_mode)(struct udevice *dev); + int (*set_mode)(struct udevice *dev, int mode_id); +}; + +/** + * regulator_mode: returns a pointer to the array of regulator mode info + * + * @dev - pointer to the regulator device + * @modep - pointer to the returned mode info array + * @return - count of modep entries on success or negative errno if fail. + */ +int regulator_mode(struct udevice *dev, struct dm_regulator_mode **modep); + +/** + * regulator_get_value: get microvoltage voltage value of a given regulator + * + * @dev - pointer to the regulator device + * @return - positive output value [uV] on success or negative errno if fail. + */ +int regulator_get_value(struct udevice *dev); + +/** + * regulator_set_value: set the microvoltage value of a given regulator. + * + * @dev - pointer to the regulator device + * @uV - the output value to set [micro Volts] + * @return - 0 on success or -errno val if fails + */ +int regulator_set_value(struct udevice *dev, int uV); + +/** + * regulator_get_current: get microampere value of a given regulator + * + * @dev - pointer to the regulator device + * @return - positive output current [uA] on success or negative errno if fail. + */ +int regulator_get_current(struct udevice *dev); + +/** + * regulator_set_current: set the microampere value of a given regulator. + * + * @dev - pointer to the regulator device + * @uA - set the output current [micro Amps] + * @return - 0 on success or -errno val if fails + */ +int regulator_set_current(struct udevice *dev, int uA); + +/** + * regulator_get_enable: get regulator device enable state. + * + * @dev - pointer to the regulator device + * @return - true/false of enable state + */ +bool regulator_get_enable(struct udevice *dev); + +/** + * regulator_set_enable: set regulator enable state + * + * @dev - pointer to the regulator device + * @enable - set true or false + * @return - 0 on success or -errno val if fails + */ +int regulator_set_enable(struct udevice *dev, bool enable); + +/** + * regulator_get_mode: get active operation mode id of a given regulator + * + * @dev - pointer to the regulator device + * @return - positive mode 'id' number on success or -errno val if fails + * Note: + * The device can provide an array of operating modes, which is type of struct + * dm_regulator_mode. Each mode has it's own 'id', which should be unique inside + * that array. By calling this function, the driver should return an active mode + * id of the given regulator device. + */ +int regulator_get_mode(struct udevice *dev); + +/** + * regulator_set_mode: set the given regulator's, active mode id + * + * @dev - pointer to the regulator device + * @mode_id - mode id to set ('id' field of struct type dm_regulator_mode) + * @return - 0 on success or -errno value if fails + * Note: + * The device can provide an array of operating modes, which is type of struct + * dm_regulator_mode. Each mode has it's own 'id', which should be unique inside + * that array. By calling this function, the driver should set the active mode + * of a given regulator to given by "mode_id" argument. + */ +int regulator_set_mode(struct udevice *dev, int mode_id); + +/** + * regulator_autoset: setup the regulator given by its uclass's platform data + * name field. The setup depends on constraints found in device's uclass's + * platform data (struct dm_regulator_uclass_platdata): + * - Enable - will set - if any of: 'always_on' or 'boot_on' is set to true, + * or if both are unset, then the function returns + * - Voltage value - will set - if '.min_uV' and '.max_uV' values are equal + * - Current limit - will set - if '.min_uA' and '.max_uA' values are equal + * + * The function returns on first encountered error. + * + * @platname - expected string for dm_regulator_uclass_platdata .name field + * @devp - returned pointer to the regulator device - if non-NULL passed + * @verbose - (true/false) print regulator setup info, or be quiet + * @return: 0 on success or negative value of errno. + * + * The returned 'regulator' device can be used with: + * - regulator_get/set_* + */ +int regulator_autoset(const char *platname, + struct udevice **devp, + bool verbose); + +/** + * regulator_list_autoset: setup the regulators given by list of their uclass's + * platform data name field. The setup depends on constraints found in device's + * uclass's platform data. The function loops with calls to: + * regulator_autoset() for each name from the list. + * + * @list_platname - an array of expected strings for .name field of each + * regulator's uclass platdata + * @list_devp - an array of returned pointers to the successfully setup + * regulator devices if non-NULL passed + * @verbose - (true/false) print each regulator setup info, or be quiet + * @return 0 on successfully setup of all list entries, otherwise first error. + * + * The returned 'regulator' devices can be used with: + * - regulator_get/set_* + * + * Note: The list must ends with NULL entry, like in the "platname" list below: + * char *my_regulators[] = { + * "VCC_3.3V", + * "VCC_1.8V", + * NULL, + * }; + */ +int regulator_list_autoset(const char *list_platname[], + struct udevice *list_devp[], + bool verbose); + +/** + * regulator_get_by_devname: returns the pointer to the pmic regulator device. + * Search by name, found in regulator device's name. + * + * @devname - expected string for 'dev->name' of regulator device + * @devp - returned pointer to the regulator device + * @return 0 on success or negative value of errno. + * + * The returned 'regulator' device is probed and can be used with: + * - regulator_get/set_* + */ +int regulator_get_by_devname(const char *devname, struct udevice **devp); + +/** + * regulator_get_by_platname: returns the pointer to the pmic regulator device. + * Search by name, found in regulator uclass platdata. + * + * @platname - expected string for uc_pdata->name of regulator uclass platdata + * @devp - returned pointer to the regulator device + * @return 0 on success or negative value of errno. + * + * The returned 'regulator' device is probed and can be used with: + * - regulator_get/set_* + */ +int regulator_get_by_platname(const char *platname, struct udevice **devp); + +#endif /* _INCLUDE_REGULATOR_H_ */ diff --git a/include/power/sandbox_pmic.h b/include/power/sandbox_pmic.h new file mode 100644 index 0000000..ae14292 --- /dev/null +++ b/include/power/sandbox_pmic.h @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SANDBOX_PMIC_H_ +#define _SANDBOX_PMIC_H_ + +#define SANDBOX_LDO_DRIVER "sandbox_ldo" +#define SANDBOX_OF_LDO_PREFIX "ldo" +#define SANDBOX_BUCK_DRIVER "sandbox_buck" +#define SANDBOX_OF_BUCK_PREFIX "buck" + +#define SANDBOX_BUCK_COUNT 2 +#define SANDBOX_LDO_COUNT 2 +/* + * Sandbox PMIC registers: + * We have only 12 significant registers, but we alloc 16 for padding. + */ +enum { + SANDBOX_PMIC_REG_BUCK1_UV = 0, + SANDBOX_PMIC_REG_BUCK1_UA, + SANDBOX_PMIC_REG_BUCK1_OM, + + SANDBOX_PMIC_REG_BUCK2_UV, + SANDBOX_PMIC_REG_BUCK2_UA, + SANDBOX_PMIC_REG_BUCK2_OM, + + SANDBOX_PMIC_REG_LDO_OFFSET, + SANDBOX_PMIC_REG_LDO1_UV = SANDBOX_PMIC_REG_LDO_OFFSET, + SANDBOX_PMIC_REG_LDO1_UA, + SANDBOX_PMIC_REG_LDO1_OM, + + SANDBOX_PMIC_REG_LDO2_UV, + SANDBOX_PMIC_REG_LDO2_UA, + SANDBOX_PMIC_REG_LDO2_OM, + + SANDBOX_PMIC_REG_COUNT = 16, +}; + +/* Register offset for output: micro Volts, micro Amps, Operation Mode */ +enum { + OUT_REG_UV = 0, + OUT_REG_UA, + OUT_REG_OM, + OUT_REG_COUNT, +}; + +/* Buck operation modes */ +enum { + BUCK_OM_OFF = 0, + BUCK_OM_ON, + BUCK_OM_PWM, + BUCK_OM_COUNT, +}; + +/* Ldo operation modes */ +enum { + LDO_OM_OFF = 0, + LDO_OM_ON, + LDO_OM_SLEEP, + LDO_OM_STANDBY, + LDO_OM_COUNT, +}; + +/* BUCK1 Voltage: min: 0.8V, step: 25mV, max 2.4V */ +#define OUT_BUCK1_UV_MIN 800000 +#define OUT_BUCK1_UV_MAX 2400000 +#define OUT_BUCK1_UV_STEP 25000 + +/* BUCK1 Amperage: min: 150mA, step: 25mA, max: 250mA */ +#define OUT_BUCK1_UA_MIN 150000 +#define OUT_BUCK1_UA_MAX 250000 +#define OUT_BUCK1_UA_STEP 25000 + +/* BUCK2 Voltage: min: 0.75V, step: 50mV, max 3.95V */ +#define OUT_BUCK2_UV_MIN 750000 +#define OUT_BUCK2_UV_MAX 3950000 +#define OUT_BUCK2_UV_STEP 50000 + +/* LDO1 Voltage: min: 0.8V, step: 25mV, max 2.4V */ +#define OUT_LDO1_UV_MIN 800000 +#define OUT_LDO1_UV_MAX 2400000 +#define OUT_LDO1_UV_STEP 25000 + +/* LDO1 Amperage: min: 100mA, step: 50mA, max: 200mA */ +#define OUT_LDO1_UA_MIN 100000 +#define OUT_LDO1_UA_MAX 200000 +#define OUT_LDO1_UA_STEP 50000 + +/* LDO2 Voltage: min: 0.75V, step: 50mV, max 3.95V */ +#define OUT_LDO2_UV_MIN 750000 +#define OUT_LDO2_UV_MAX 3950000 +#define OUT_LDO2_UV_STEP 50000 + +/* register <-> value conversion */ +#define REG2VAL(min, step, reg) ((min) + ((step) * (reg))) +#define VAL2REG(min, step, val) (((val) - (min)) / (step)) + +/* Operation mode id -> register value conversion */ +#define OM2REG(x) (x) + +/* Test data for: test/dm/power.c */ + +/* BUCK names */ +#define SANDBOX_BUCK1_DEVNAME "buck1" +#define SANDBOX_BUCK1_PLATNAME "SUPPLY_1.2V" +#define SANDBOX_BUCK2_DEVNAME "buck2" +#define SANDBOX_BUCK2_PLATNAME "SUPPLY_3.3V" +/* LDO names */ +#define SANDBOX_LDO1_DEVNAME "ldo1" +#define SANDBOX_LDO1_PLATNAME "VDD_EMMC_1.8V" +#define SANDBOX_LDO2_DEVNAME "ldo2" +#define SANDBOX_LDO2_PLATNAME "VDD_LCD_3.3V" + +/* + * Expected regulators setup after call of: + * - regulator_autoset() + * - regulator_list_autoset() + */ + +/* BUCK1: for testing regulator_autoset() */ +#define SANDBOX_BUCK1_AUTOSET_EXPECTED_UV 1200000 +#define SANDBOX_BUCK1_AUTOSET_EXPECTED_UA 200000 +#define SANDBOX_BUCK1_AUTOSET_EXPECTED_ENABLE true + +/* LDO1/2 for testing regulator_list_autoset() */ +#define SANDBOX_LDO1_AUTOSET_EXPECTED_UV 1800000 +#define SANDBOX_LDO1_AUTOSET_EXPECTED_UA 100000 +#define SANDBOX_LDO1_AUTOSET_EXPECTED_ENABLE true + +#define SANDBOX_LDO2_AUTOSET_EXPECTED_UV 3000000 +#define SANDBOX_LDO2_AUTOSET_EXPECTED_UA -ENOSYS +#define SANDBOX_LDO2_AUTOSET_EXPECTED_ENABLE false + +#endif diff --git a/include/rtc.h b/include/rtc.h index 54e361e..bd8621d 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -15,41 +15,143 @@ * it there instead of in evey single driver */ #include <bcd.h> +#include <rtc_def.h> -/* - * The struct used to pass data from the generic interface code to - * the hardware dependend low-level code ande vice versa. Identical - * to struct rtc_time used by the Linux kernel. - * - * Note that there are small but significant differences to the - * common "struct time": - * - * struct time: struct rtc_time: - * tm_mon 0 ... 11 1 ... 12 - * tm_year years since 1900 years since 0 - */ - -struct rtc_time { - int tm_sec; - int tm_min; - int tm_hour; - int tm_mday; - int tm_mon; - int tm_year; - int tm_wday; - int tm_yday; - int tm_isdst; +#ifdef CONFIG_DM_RTC + +struct rtc_ops { + /** + * get() - get the current time + * + * Returns the current time read from the RTC device. The driver + * is responsible for setting up every field in the structure. + * + * @dev: Device to read from + * @time: Place to put the time that is read + */ + int (*get)(struct udevice *dev, struct rtc_time *time); + + /** + * set() - set the current time + * + * Sets the time in the RTC device. The driver can expect every + * field to be set correctly. + * + * @dev: Device to read from + * @time: Time to write + */ + int (*set)(struct udevice *dev, const struct rtc_time *time); + + /** + * reset() - reset the RTC to a known-good state + * + * This function resets the RTC to a known-good state. The time may + * be unset by this method, so should be set after this method is + * called. + * + * @dev: Device to read from + * @return 0 if OK, -ve on error + */ + int (*reset)(struct udevice *dev); + + /** + * read8() - Read an 8-bit register + * + * @dev: Device to read from + * @reg: Register to read + * @return value read, or -ve on error + */ + int (*read8)(struct udevice *dev, unsigned int reg); + + /** + * write8() - Write an 8-bit register + * + * @dev: Device to write to + * @reg: Register to write + * @value: Value to write + * @return 0 if OK, -ve on error + */ + int (*write8)(struct udevice *dev, unsigned int reg, int val); }; +/* Access the operations for an RTC device */ +#define rtc_get_ops(dev) ((struct rtc_ops *)(dev)->driver->ops) + +/** + * dm_rtc_get() - Read the time from an RTC + * + * @dev: Device to read from + * @time: Place to put the current time + * @return 0 if OK, -ve on error + */ +int dm_rtc_get(struct udevice *dev, struct rtc_time *time); + +/** + * dm_rtc_put() - Write a time to an RTC + * + * @dev: Device to read from + * @time: Time to write into the RTC + * @return 0 if OK, -ve on error + */ +int dm_rtc_set(struct udevice *dev, struct rtc_time *time); + +/** + * dm_rtc_reset() - reset the RTC to a known-good state + * + * If the RTC appears to be broken (e.g. it is not counting up in seconds) + * it may need to be reset to a known good state. This function achieves this. + * After resetting the RTC the time should then be set to a known value by + * the caller. + * + * @dev: Device to read from + * @return 0 if OK, -ve on error + */ +int dm_rtc_reset(struct udevice *dev); + +/** + * rtc_read8() - Read an 8-bit register + * + * @dev: Device to read from + * @reg: Register to read + * @return value read, or -ve on error + */ +int rtc_read8(struct udevice *dev, unsigned int reg); + +/** + * rtc_write8() - Write an 8-bit register + * + * @dev: Device to write to + * @reg: Register to write + * @value: Value to write + * @return 0 if OK, -ve on error + */ +int rtc_write8(struct udevice *dev, unsigned int reg, int val); + +/** + * rtc_read32() - Read a 32-bit value from the RTC + * + * @dev: Device to read from + * @reg: Offset to start reading from + * @valuep: Place to put the value that is read + * @return 0 if OK, -ve on error + */ +int rtc_read32(struct udevice *dev, unsigned int reg, u32 *valuep); + +/** + * rtc_write32() - Write a 32-bit value to the RTC + * + * @dev: Device to write to + * @reg: Register to start writing to + * @value: Value to write + * @return 0 if OK, -ve on error + */ +int rtc_write32(struct udevice *dev, unsigned int reg, u32 value); + +#else int rtc_get (struct rtc_time *); int rtc_set (struct rtc_time *); void rtc_reset (void); -void GregorianDay (struct rtc_time *); -void to_tm (int, struct rtc_time *); -unsigned long mktime (unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int); - /** * rtc_read8() - Read an 8-bit register * @@ -86,5 +188,44 @@ void rtc_write32(int reg, u32 value); * rtc_init() - Set up the real time clock ready for use */ void rtc_init(void); +#endif + +/** + * rtc_calc_weekday() - Work out the weekday from a time + * + * This only works for the Gregorian calendar - i.e. after 1752 (in the UK). + * It sets time->tm_wdaay to the correct day of the week. + * + * @time: Time to inspect. tm_wday is updated + * @return 0 if OK, -EINVAL if the weekday could not be determined + */ +int rtc_calc_weekday(struct rtc_time *time); + +/** + * rtc_to_tm() - Convert a time_t value into a broken-out time + * + * The following fields are set up by this function: + * tm_sec, tm_min, tm_hour, tm_mday, tm_mon, tm_year, tm_wday + * + * Note that tm_yday and tm_isdst are set to 0. + * + * @time_t: Number of seconds since 1970-01-01 00:00:00 + * @time: Place to put the broken-out time + * @return 0 if OK, -EINVAL if the weekday could not be determined + */ +int rtc_to_tm(int time_t, struct rtc_time *time); + +/** + * rtc_mktime() - Convert a broken-out time into a time_t value + * + * The following fields need to be valid for this function to work: + * tm_sec, tm_min, tm_hour, tm_mday, tm_mon, tm_year + * + * Note that tm_wday and tm_yday are ignored. + * + * @time: Broken-out time to convert + * @return corresponding time_t value, seconds since 1970-01-01 00:00:00 + */ +unsigned long rtc_mktime(const struct rtc_time *time); #endif /* _RTC_H_ */ diff --git a/include/rtc_def.h b/include/rtc_def.h new file mode 100644 index 0000000..6179797 --- /dev/null +++ b/include/rtc_def.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __rtc_def_h +#define __rtc_def_h + +/* + * The struct used to pass data from the generic interface code to + * the hardware dependend low-level code ande vice versa. Identical + * to struct rtc_time used by the Linux kernel. + * + * Note that there are small but significant differences to the + * common "struct time": + * + * struct time: struct rtc_time: + * tm_mon 0 ... 11 1 ... 12 + * tm_year years since 1900 years since 0 + */ + +struct rtc_time { + int tm_sec; + int tm_min; + int tm_hour; + int tm_mday; + int tm_mon; + int tm_year; + int tm_wday; + int tm_yday; + int tm_isdst; +}; + +#endif diff --git a/include/spi.h b/include/spi.h index 9495ca5..f4b93e6 100644 --- a/include/spi.h +++ b/include/spi.h @@ -100,6 +100,8 @@ struct dm_spi_slave_platdata { * @dev: SPI slave device * @max_hz: Maximum speed for this slave * @mode: SPI mode to use for this slave (see SPI mode flags) + * @speed: Current bus speed. This is 0 until the bus is first + * claimed. * @bus: ID of the bus that the slave is attached to. For * driver model this is the sequence number of the SPI * bus (bus->seq) so does not need to be stored @@ -117,6 +119,7 @@ struct spi_slave { #ifdef CONFIG_DM_SPI struct udevice *dev; /* struct spi_slave is dev->parentdata */ uint max_hz; + uint speed; uint mode; #else unsigned int bus; @@ -613,7 +616,7 @@ int sandbox_spi_get_emul(struct sandbox_state *state, struct udevice *bus, struct udevice *slave, struct udevice **emulp); -/* Access the serial operations for a device */ +/* Access the operations for a SPI device */ #define spi_get_ops(dev) ((struct dm_spi_ops *)(dev)->driver->ops) #define spi_emul_get_ops(dev) ((struct dm_spi_emul_ops *)(dev)->driver->ops) #endif /* CONFIG_DM_SPI */ diff --git a/include/usb.h b/include/usb.h index 1984e8f..c709ce2 100644 --- a/include/usb.h +++ b/include/usb.h @@ -198,7 +198,7 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int interval); -#if defined CONFIG_USB_EHCI || defined CONFIG_MUSB_HOST +#if defined CONFIG_USB_EHCI || defined CONFIG_MUSB_HOST || defined(CONFIG_DM_USB) struct int_queue *create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, int elementsize, void *buffer, int interval); int destroy_int_queue(struct usb_device *dev, struct int_queue *queue); @@ -265,6 +265,7 @@ int usb_kbd_deregister(int force); /* routines */ int usb_init(void); /* initialize the USB Controller */ int usb_stop(void); /* stop the USB Controller */ +int usb_detect_change(void); /* detect if a USB device has been (un)plugged */ int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol); @@ -290,6 +291,7 @@ int usb_get_class_descriptor(struct usb_device *dev, int ifnum, int usb_clear_halt(struct usb_device *dev, int pipe); int usb_string(struct usb_device *dev, int index, char *buf, size_t size); int usb_set_interface(struct usb_device *dev, int interface, int alternate); +int usb_get_port_status(struct usb_device *dev, int port, void *data); /* big endian -> little endian conversion */ /* some CPUs are already little endian e.g. the ARM920T */ @@ -571,20 +573,23 @@ struct usb_platdata { * This is used by sandbox to provide emulation data also. * * @id: ID used to match this device - * @speed: Stores the speed associated with a USB device * @devnum: Device address on the USB bus - * @slot_id: USB3 slot ID, which is separate from the device address - * @portnr: Port number of this device on its parent hub, numbered from 1 - * (0 mean this device is the root hub) + * @udev: usb-uclass internal use only do NOT use * @strings: List of descriptor strings (for sandbox emulation purposes) * @desc_list: List of descriptors (for sandbox emulation purposes) */ struct usb_dev_platdata { struct usb_device_id id; - enum usb_device_speed speed; int devnum; - int slot_id; - int portnr; /* Hub port number, 1..n */ + /* + * This pointer is used to pass the usb_device used in usb_scan_device, + * to get the usb descriptors before the driver is known, to the + * actual udevice once the driver is known and the udevice is created. + * This will be NULL except during probe, do NOT use. + * + * This should eventually go away. + */ + struct usb_device *udev; #ifdef CONFIG_SANDBOX struct usb_string *strings; /* NULL-terminated list of descriptor pointers */ @@ -605,10 +610,13 @@ struct usb_dev_platdata { * @desc_before_addr: true if we can read a device descriptor before it * has been assigned an address. For XHCI this is not possible * so this will be false. + * @companion: True if this is a companion controller to another USB + * controller */ struct usb_bus_priv { int next_addr; bool desc_before_addr; + bool companion; }; /** @@ -657,6 +665,52 @@ struct dm_usb_ops { int (*interrupt)(struct udevice *bus, struct usb_device *udev, unsigned long pipe, void *buffer, int length, int interval); + + /** + * create_int_queue() - Create and queue interrupt packets + * + * Create and queue @queuesize number of interrupt usb packets of + * @elementsize bytes each. @buffer must be atleast @queuesize * + * @elementsize bytes. + * + * Note some controllers only support a queuesize of 1. + * + * @interval: Interrupt interval + * + * @return A pointer to the created interrupt queue or NULL on error + */ + struct int_queue * (*create_int_queue)(struct udevice *bus, + struct usb_device *udev, unsigned long pipe, + int queuesize, int elementsize, void *buffer, + int interval); + + /** + * poll_int_queue() - Poll an interrupt queue for completed packets + * + * Poll an interrupt queue for completed packets. The return value + * points to the part of the buffer passed to create_int_queue() + * corresponding to the completed packet. + * + * @queue: queue to poll + * + * @return Pointer to the data of the first completed packet, or + * NULL if no packets are ready + */ + void * (*poll_int_queue)(struct udevice *bus, struct usb_device *udev, + struct int_queue *queue); + + /** + * destroy_int_queue() - Destroy an interrupt queue + * + * Destroy an interrupt queue created by create_int_queue(). + * + * @queue: queue to poll + * + * @return 0 if OK, -ve on error + */ + int (*destroy_int_queue)(struct udevice *bus, struct usb_device *udev, + struct int_queue *queue); + /** * alloc_device() - Allocate a new device context (XHCI) * @@ -742,11 +796,10 @@ int usb_scan_device(struct udevice *parent, int port, * will be a device with uclass UCLASS_USB. * * @dev: Device to check - * @busp: Returns bus, or NULL if not found - * @return 0 if OK, -EXDEV is somehow this bus does not have a controller (this - * indicates a critical error in the USB stack + * @return The bus, or NULL if not found (this indicates a critical error in + * the USB stack */ -int usb_get_bus(struct udevice *dev, struct udevice **busp); +struct udevice *usb_get_bus(struct udevice *dev); /** * usb_select_config() - Set up a device ready for use diff --git a/lib/Kconfig b/lib/Kconfig index d7fd219..5b6cf3d 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -36,6 +36,14 @@ config SYS_VSNPRINTF Thumb-2, about 420 bytes). Enable this option for safety when using sprintf() with data you do not control. +config REGEX + bool "Enable regular expression support" + help + If this variable is defined, U-Boot is linked against the + SLRE (Super Light Regular Expression) library, which adds + regex support to some commands, for example "env grep" and + "setexpr". + source lib/rsa/Kconfig menu "Hashing Support" @@ -74,4 +82,12 @@ config SHA_PROG_HW_ACCEL is performed in hardware. endmenu +config ERRNO_STR + bool "Enable function for getting errno-related string message" + help + The function errno_str(int errno), returns a pointer to the errno + corresponding text message: + - if errno is null or positive number - a pointer to "Success" message + - if errno is negative - a pointer to errno related message + endmenu diff --git a/lib/display_options.c b/lib/display_options.c index 24d8f55..57fb974 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -152,7 +152,7 @@ int print_buffer(ulong addr, const void *data, uint width, uint count, else x = lb.uc[i] = *(volatile uint8_t *)data; #ifdef CONFIG_SYS_SUPPORT_64BIT_DATA - printf(" %0*" PRIx64, width * 2, x); + printf(" %0*llx", width * 2, (long long)x); #else printf(" %0*x", width * 2, x); #endif diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 80b897a..b586da2 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -30,6 +30,9 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"), COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"), COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"), + COMPAT(NVIDIA_TEGRA124_DC, "nvidia,tegra124-dc"), + COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"), + COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"), COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"), COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"), COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"), @@ -44,8 +47,6 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_EXYNOS5_SOUND, "samsung,exynos-sound"), COMPAT(WOLFSON_WM8994_CODEC, "wolfson,wm8994-codec"), COMPAT(GOOGLE_CROS_EC_KEYB, "google,cros-ec-keyb"), - COMPAT(SAMSUNG_EXYNOS_EHCI, "samsung,exynos-ehci"), - COMPAT(SAMSUNG_EXYNOS5_XHCI, "samsung,exynos5250-xhci"), COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"), COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"), COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"), @@ -55,11 +56,11 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"), COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"), COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"), - COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"), + COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686"), COMPAT(GENERIC_SPI_FLASH, "spi-flash"), COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"), COMPAT(INFINEON_SLB9635_TPM, "infineon,slb9635-tpm"), - COMPAT(INFINEON_SLB9645_TPM, "infineon,slb9645-tpm"), + COMPAT(INFINEON_SLB9645_TPM, "infineon,slb9645tt"), COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"), COMPAT(SANDBOX_LCD_SDL, "sandbox,lcd-sdl"), COMPAT(TI_TPS65090, "ti,tps65090"), @@ -1039,6 +1040,98 @@ int fdtdec_decode_memory_region(const void *blob, int config_node, return 0; } +static int decode_timing_property(const void *blob, int node, const char *name, + struct timing_entry *result) +{ + int length, ret = 0; + const u32 *prop; + + prop = fdt_getprop(blob, node, name, &length); + if (!prop) { + debug("%s: could not find property %s\n", + fdt_get_name(blob, node, NULL), name); + return length; + } + + if (length == sizeof(u32)) { + result->typ = fdtdec_get_int(blob, node, name, 0); + result->min = result->typ; + result->max = result->typ; + } else { + ret = fdtdec_get_int_array(blob, node, name, &result->min, 3); + } + + return ret; +} + +int fdtdec_decode_display_timing(const void *blob, int parent, int index, + struct display_timing *dt) +{ + int i, node, timings_node; + u32 val = 0; + int ret = 0; + + timings_node = fdt_subnode_offset(blob, parent, "display-timings"); + if (timings_node < 0) + return timings_node; + + for (i = 0, node = fdt_first_subnode(blob, timings_node); + node > 0 && i != index; + node = fdt_next_subnode(blob, node)) + i++; + + if (node < 0) + return node; + + memset(dt, 0, sizeof(*dt)); + + ret |= decode_timing_property(blob, node, "hback-porch", + &dt->hback_porch); + ret |= decode_timing_property(blob, node, "hfront-porch", + &dt->hfront_porch); + ret |= decode_timing_property(blob, node, "hactive", &dt->hactive); + ret |= decode_timing_property(blob, node, "hsync-len", &dt->hsync_len); + ret |= decode_timing_property(blob, node, "vback-porch", + &dt->vback_porch); + ret |= decode_timing_property(blob, node, "vfront-porch", + &dt->vfront_porch); + ret |= decode_timing_property(blob, node, "vactive", &dt->vactive); + ret |= decode_timing_property(blob, node, "vsync-len", &dt->vsync_len); + ret |= decode_timing_property(blob, node, "clock-frequency", + &dt->pixelclock); + + dt->flags = 0; + val = fdtdec_get_int(blob, node, "vsync-active", -1); + if (val != -1) { + dt->flags |= val ? DISPLAY_FLAGS_VSYNC_HIGH : + DISPLAY_FLAGS_VSYNC_LOW; + } + val = fdtdec_get_int(blob, node, "hsync-active", -1); + if (val != -1) { + dt->flags |= val ? DISPLAY_FLAGS_HSYNC_HIGH : + DISPLAY_FLAGS_HSYNC_LOW; + } + val = fdtdec_get_int(blob, node, "de-active", -1); + if (val != -1) { + dt->flags |= val ? DISPLAY_FLAGS_DE_HIGH : + DISPLAY_FLAGS_DE_LOW; + } + val = fdtdec_get_int(blob, node, "pixelclk-active", -1); + if (val != -1) { + dt->flags |= val ? DISPLAY_FLAGS_PIXDATA_POSEDGE : + DISPLAY_FLAGS_PIXDATA_NEGEDGE; + } + + if (fdtdec_get_bool(blob, node, "interlaced")) + dt->flags |= DISPLAY_FLAGS_INTERLACED; + if (fdtdec_get_bool(blob, node, "doublescan")) + dt->flags |= DISPLAY_FLAGS_DOUBLESCAN; + if (fdtdec_get_bool(blob, node, "doubleclk")) + dt->flags |= DISPLAY_FLAGS_DOUBLECLK; + + return 0; +} + int fdtdec_setup(void) { #ifdef CONFIG_OF_CONTROL @@ -7,6 +7,7 @@ #include <common.h> #include <command.h> +#include <dm.h> #include <net.h> #include <rtc.h> @@ -68,9 +69,20 @@ static void sntp_handler(uchar *pkt, unsigned dest, struct in_addr sip, */ memcpy(&seconds, &rpktp->transmit_timestamp, sizeof(ulong)); - to_tm(ntohl(seconds) - 2208988800UL + net_ntp_time_offset, &tm); + rtc_to_tm(ntohl(seconds) - 2208988800UL + net_ntp_time_offset, &tm); #if defined(CONFIG_CMD_DATE) +# ifdef CONFIG_DM_RTC + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RTC, 0, &dev); + if (ret) + printf("SNTP: cannot find RTC: err=%d\n", ret); + else + dm_rtc_set(dev, &tm); +# else rtc_set(&tm); +# endif #endif printf("Date: %4d-%02d-%02d Time: %2d:%02d:%02d\n", tm.tm_year, tm.tm_mon, tm.tm_mday, diff --git a/post/drivers/rtc.c b/post/drivers/rtc.c index cd19f75..c2e7391 100644 --- a/post/drivers/rtc.c +++ b/post/drivers/rtc.c @@ -59,11 +59,10 @@ static int rtc_post_skip (ulong * diff) static void rtc_post_restore (struct rtc_time *tm, unsigned int sec) { - time_t t = mktime (tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour, - tm->tm_min, tm->tm_sec) + sec; + time_t t = rtc_mktime(tm) + sec; struct rtc_time ntm; - to_tm (t, &ntm); + rtc_to_tm(t, &ntm); rtc_set (&ntm); } @@ -116,10 +115,17 @@ int rtc_post_test (int flags) rtc_get (&svtm); for (i = 0; i < 12; i++) { - time_t t = mktime (ynl, i + 1, daysnl[i], 23, 59, 59); + time_t t; struct rtc_time tm; - to_tm (t, &tm); + tm.tm_year = ynl; + tm.tm_mon = i + 1; + tm.tm_mday = daysnl[i]; + tm.tm_hour = 23; + tm.tm_min = 59; + tm.tm_sec = 59; + t = rtc_mktime(&tm); + rtc_to_tm(t, &tm); rtc_set (&tm); skipped++; @@ -140,10 +146,18 @@ int rtc_post_test (int flags) } for (i = 0; i < 12; i++) { - time_t t = mktime (yl, i + 1, daysl[i], 23, 59, 59); + time_t t; struct rtc_time tm; - to_tm (t, &tm); + tm.tm_year = yl; + tm.tm_mon = i + 1; + tm.tm_mday = daysl[i]; + tm.tm_hour = 23; + tm.tm_min = 59; + tm.tm_sec = 59; + t = rtc_mktime(&tm); + + rtc_to_tm(t, &tm); rtc_set (&tm); skipped++; diff --git a/test/Kconfig b/test/Kconfig index 1fb1716..3270c84 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -1 +1,9 @@ +config CMD_UT_TIME + bool "Unit tests for time functions" + help + Enables the 'ut_time' command which tests that the time functions + work correctly. The test is fairly simple and will not catch all + problems. But if you are having problems with udelay() and the like, + this is a good place to start. + source "test/dm/Kconfig" diff --git a/test/Makefile b/test/Makefile index 9c95805..08330e0 100644 --- a/test/Makefile +++ b/test/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_SANDBOX) += command_ut.o obj-$(CONFIG_SANDBOX) += compression.o +obj-$(CONFIG_CMD_UT_TIME) += time_ut.o diff --git a/test/dm/.gitignore b/test/dm/.gitignore deleted file mode 100644 index b741b8a..0000000 --- a/test/dm/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/test.dtb diff --git a/test/dm/Makefile b/test/dm/Makefile index fd9e29f..c7087bb 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -21,7 +21,10 @@ obj-$(CONFIG_DM_ETH) += eth.o obj-$(CONFIG_DM_GPIO) += gpio.o obj-$(CONFIG_DM_I2C) += i2c.o obj-$(CONFIG_DM_PCI) += pci.o +obj-$(CONFIG_DM_RTC) += rtc.o obj-$(CONFIG_DM_SPI_FLASH) += sf.o obj-$(CONFIG_DM_SPI) += spi.o obj-$(CONFIG_DM_USB) += usb.o +obj-$(CONFIG_DM_PMIC) += pmic.o +obj-$(CONFIG_DM_REGULATOR) += regulator.o endif diff --git a/test/dm/eth.c b/test/dm/eth.c index 4891f3a..196eba8 100644 --- a/test/dm/eth.c +++ b/test/dm/eth.c @@ -135,6 +135,7 @@ static int dm_test_net_retry(struct dm_test_state *dms) sandbox_eth_disable_response(1, true); setenv("ethact", "eth@10004000"); setenv("netretry", "yes"); + sandbox_eth_skip_timeout(); ut_assertok(net_loop(PING)); ut_asserteq_str("eth@10002000", getenv("ethact")); @@ -144,6 +145,7 @@ static int dm_test_net_retry(struct dm_test_state *dms) */ setenv("ethact", "eth@10004000"); setenv("netretry", "no"); + sandbox_eth_skip_timeout(); ut_asserteq(-ETIMEDOUT, net_loop(PING)); ut_asserteq_str("eth@10004000", getenv("ethact")); diff --git a/test/dm/i2c.c b/test/dm/i2c.c index 541b73b..c5939a1 100644 --- a/test/dm/i2c.c +++ b/test/dm/i2c.c @@ -66,6 +66,9 @@ static int dm_test_i2c_speed(struct dm_test_state *dms) uint8_t buf[5]; ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus)); + + /* Use test mode so we create the required errors for invalid speeds */ + sandbox_i2c_set_test_mode(bus, true); ut_assertok(i2c_get_chip(bus, chip, 1, &dev)); ut_assertok(dm_i2c_set_bus_speed(bus, 100000)); ut_assertok(dm_i2c_read(dev, 0, buf, 5)); @@ -73,6 +76,7 @@ static int dm_test_i2c_speed(struct dm_test_state *dms) ut_asserteq(400000, dm_i2c_get_bus_speed(bus)); ut_assertok(dm_i2c_read(dev, 0, buf, 5)); ut_asserteq(-EINVAL, dm_i2c_write(dev, 0, buf, 5)); + sandbox_i2c_set_test_mode(bus, false); return 0; } @@ -100,7 +104,11 @@ static int dm_test_i2c_probe_empty(struct dm_test_state *dms) struct udevice *bus, *dev; ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus)); + + /* Use test mode so that this chip address will always probe */ + sandbox_i2c_set_test_mode(bus, true); ut_assertok(dm_i2c_probe(bus, SANDBOX_I2C_TEST_ADDR, 0, &dev)); + sandbox_i2c_set_test_mode(bus, false); return 0; } diff --git a/test/dm/pmic.c b/test/dm/pmic.c new file mode 100644 index 0000000..e9c904c --- /dev/null +++ b/test/dm/pmic.c @@ -0,0 +1,69 @@ +/* + * Tests for the driver model pmic API + * + * Copyright (c) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <dm.h> +#include <fdtdec.h> +#include <malloc.h> +#include <dm/device-internal.h> +#include <dm/root.h> +#include <dm/ut.h> +#include <dm/util.h> +#include <dm/test.h> +#include <dm/uclass-internal.h> +#include <power/pmic.h> +#include <power/sandbox_pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Test PMIC get method */ +static int dm_test_power_pmic_get(struct dm_test_state *dms) +{ + const char *name = "sandbox_pmic"; + struct udevice *dev; + + ut_assertok(pmic_get(name, &dev)); + ut_assertnonnull(dev); + + /* Check PMIC's name */ + ut_asserteq_str(name, dev->name); + + return 0; +} +DM_TEST(dm_test_power_pmic_get, DM_TESTF_SCAN_FDT); + +/* Test PMIC I/O */ +static int dm_test_power_pmic_io(struct dm_test_state *dms) +{ + const char *name = "sandbox_pmic"; + uint8_t out_buffer, in_buffer; + struct udevice *dev; + int reg_count, i; + + ut_assertok(pmic_get(name, &dev)); + + reg_count = pmic_reg_count(dev); + ut_asserteq(reg_count, SANDBOX_PMIC_REG_COUNT); + + /* + * Test PMIC I/O - write and read a loop counter. + * usually we can't write to all PMIC's registers in the real hardware, + * but we can to the sandbox pmic. + */ + for (i = 0; i < reg_count; i++) { + out_buffer = i; + ut_assertok(pmic_write(dev, i, &out_buffer, 1)); + ut_assertok(pmic_read(dev, i, &in_buffer, 1)); + ut_asserteq(out_buffer, in_buffer); + } + + return 0; +} +DM_TEST(dm_test_power_pmic_io, DM_TESTF_SCAN_FDT); diff --git a/test/dm/regulator.c b/test/dm/regulator.c new file mode 100644 index 0000000..c4f14bd --- /dev/null +++ b/test/dm/regulator.c @@ -0,0 +1,325 @@ +/* + * Tests for the driver model regulator API + * + * Copyright (c) 2015 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <dm.h> +#include <fdtdec.h> +#include <malloc.h> +#include <dm/device-internal.h> +#include <dm/root.h> +#include <dm/ut.h> +#include <dm/util.h> +#include <dm/test.h> +#include <dm/uclass-internal.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/sandbox_pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum { + BUCK1, + BUCK2, + LDO1, + LDO2, + OUTPUT_COUNT, +}; + +enum { + DEVNAME = 0, + PLATNAME, + OUTPUT_NAME_COUNT, +}; + +static const char *regulator_names[OUTPUT_COUNT][OUTPUT_NAME_COUNT] = { + /* devname, platname */ + { SANDBOX_BUCK1_DEVNAME, SANDBOX_BUCK1_PLATNAME }, + { SANDBOX_BUCK2_DEVNAME, SANDBOX_BUCK2_PLATNAME }, + { SANDBOX_LDO1_DEVNAME, SANDBOX_LDO1_PLATNAME}, + { SANDBOX_LDO2_DEVNAME, SANDBOX_LDO2_PLATNAME}, +}; + +/* Test regulator get method */ +static int dm_test_power_regulator_get(struct dm_test_state *dms) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + struct udevice *dev_by_devname; + struct udevice *dev_by_platname; + const char *devname; + const char *platname; + int i; + + for (i = 0; i < OUTPUT_COUNT; i++) { + /* + * Do the test for each regulator's devname and platname, + * which are related to a single device. + */ + devname = regulator_names[i][DEVNAME]; + platname = regulator_names[i][PLATNAME]; + + /* + * Check, that regulator_get_by_devname() function, returns + * a device with the name equal to the requested one. + */ + ut_assertok(regulator_get_by_devname(devname, &dev_by_devname)); + ut_asserteq_str(devname, dev_by_devname->name); + + /* + * Check, that regulator_get_by_platname() function, returns + * a device with the name equal to the requested one. + */ + ut_assertok(regulator_get_by_platname(platname, &dev_by_platname)); + uc_pdata = dev_get_uclass_platdata(dev_by_platname); + ut_assert(uc_pdata); + ut_asserteq_str(platname, uc_pdata->name); + + /* + * Check, that the pointers returned by both get functions, + * points to the same regulator device. + */ + ut_asserteq_ptr(dev_by_devname, dev_by_platname); + } + + return 0; +} +DM_TEST(dm_test_power_regulator_get, DM_TESTF_SCAN_FDT); + +/* Test regulator set and get Voltage method */ +static int dm_test_power_regulator_set_get_voltage(struct dm_test_state *dms) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + struct udevice *dev; + const char *platname; + int val_set, val_get; + + /* Set and get Voltage of BUCK1 - set to 'min' constraint */ + platname = regulator_names[BUCK1][PLATNAME]; + ut_assertok(regulator_get_by_platname(platname, &dev)); + + uc_pdata = dev_get_uclass_platdata(dev); + ut_assert(uc_pdata); + + val_set = uc_pdata->min_uV; + ut_assertok(regulator_set_value(dev, val_set)); + + val_get = regulator_get_value(dev); + ut_assert(val_get >= 0); + + ut_asserteq(val_set, val_get); + + return 0; +} +DM_TEST(dm_test_power_regulator_set_get_voltage, DM_TESTF_SCAN_FDT); + +/* Test regulator set and get Current method */ +static int dm_test_power_regulator_set_get_current(struct dm_test_state *dms) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + struct udevice *dev; + const char *platname; + int val_set, val_get; + + /* Set and get the Current of LDO1 - set to 'min' constraint */ + platname = regulator_names[LDO1][PLATNAME]; + ut_assertok(regulator_get_by_platname(platname, &dev)); + + uc_pdata = dev_get_uclass_platdata(dev); + ut_assert(uc_pdata); + + val_set = uc_pdata->min_uA; + ut_assertok(regulator_set_current(dev, val_set)); + + val_get = regulator_get_current(dev); + ut_assert(val_get >= 0); + + ut_asserteq(val_set, val_get); + + /* Check LDO2 current limit constraints - should be -ENODATA */ + platname = regulator_names[LDO2][PLATNAME]; + ut_assertok(regulator_get_by_platname(platname, &dev)); + + uc_pdata = dev_get_uclass_platdata(dev); + ut_assert(uc_pdata); + ut_asserteq(-ENODATA, uc_pdata->min_uA); + ut_asserteq(-ENODATA, uc_pdata->max_uA); + + /* Try set the Current of LDO2 - should return -ENOSYS */ + ut_asserteq(-ENOSYS, regulator_set_current(dev, 0)); + + return 0; +} +DM_TEST(dm_test_power_regulator_set_get_current, DM_TESTF_SCAN_FDT); + +/* Test regulator set and get Enable method */ +static int dm_test_power_regulator_set_get_enable(struct dm_test_state *dms) +{ + const char *platname; + struct udevice *dev; + bool val_set = true; + + /* Set the Enable of LDO1 - default is disabled */ + platname = regulator_names[LDO1][PLATNAME]; + ut_assertok(regulator_get_by_platname(platname, &dev)); + ut_assertok(regulator_set_enable(dev, val_set)); + + /* Get the Enable state of LDO1 and compare it with the requested one */ + ut_asserteq(regulator_get_enable(dev), val_set); + + return 0; +} +DM_TEST(dm_test_power_regulator_set_get_enable, DM_TESTF_SCAN_FDT); + +/* Test regulator set and get mode method */ +static int dm_test_power_regulator_set_get_mode(struct dm_test_state *dms) +{ + const char *platname; + struct udevice *dev; + int val_set = LDO_OM_SLEEP; + + /* Set the mode id to LDO_OM_SLEEP of LDO1 - default is LDO_OM_OFF */ + platname = regulator_names[LDO1][PLATNAME]; + ut_assertok(regulator_get_by_platname(platname, &dev)); + ut_assertok(regulator_set_mode(dev, val_set)); + + /* Get the mode id of LDO1 and compare it with the requested one */ + ut_asserteq(regulator_get_mode(dev), val_set); + + return 0; +} +DM_TEST(dm_test_power_regulator_set_get_mode, DM_TESTF_SCAN_FDT); + +/* Test regulator autoset method */ +static int dm_test_power_regulator_autoset(struct dm_test_state *dms) +{ + const char *platname; + struct udevice *dev, *dev_autoset; + + /* + * Test the BUCK1 with fdt properties + * - min-microvolt = max-microvolt = 1200000 + * - min-microamp = max-microamp = 200000 + * - always-on = set + * - boot-on = not set + * Expected output state: uV=1200000; uA=200000; output enabled + */ + platname = regulator_names[BUCK1][PLATNAME]; + ut_assertok(regulator_autoset(platname, &dev_autoset, false)); + + /* Check, that the returned device is proper */ + ut_assertok(regulator_get_by_platname(platname, &dev)); + ut_asserteq_ptr(dev, dev_autoset); + + /* Check the setup after autoset */ + ut_asserteq(regulator_get_value(dev), + SANDBOX_BUCK1_AUTOSET_EXPECTED_UV); + ut_asserteq(regulator_get_current(dev), + SANDBOX_BUCK1_AUTOSET_EXPECTED_UA); + ut_asserteq(regulator_get_enable(dev), + SANDBOX_BUCK1_AUTOSET_EXPECTED_ENABLE); + + return 0; +} +DM_TEST(dm_test_power_regulator_autoset, DM_TESTF_SCAN_FDT); + +/* + * Struct setting: to keep the expected output settings. + * @voltage: Voltage value [uV] + * @current: Current value [uA] + * @enable: output enable state: true/false + */ +struct setting { + int voltage; + int current; + bool enable; +}; + +/* + * platname_list: an array of regulator platform names. + * For testing regulator_list_autoset() for outputs: + * - LDO1 + * - LDO2 + */ +static const char *platname_list[] = { + SANDBOX_LDO1_PLATNAME, + SANDBOX_LDO2_PLATNAME, + NULL, +}; + +/* + * expected_setting_list: an array of regulator output setting, expected after + * call of the regulator_list_autoset() for the "platname_list" array. + * For testing results of regulator_list_autoset() for outputs: + * - LDO1 + * - LDO2 + * The settings are defined in: include/power/sandbox_pmic.h + */ +static const struct setting expected_setting_list[] = { + [0] = { /* LDO1 */ + .voltage = SANDBOX_LDO1_AUTOSET_EXPECTED_UV, + .current = SANDBOX_LDO1_AUTOSET_EXPECTED_UA, + .enable = SANDBOX_LDO1_AUTOSET_EXPECTED_ENABLE, + }, + [1] = { /* LDO2 */ + .voltage = SANDBOX_LDO2_AUTOSET_EXPECTED_UV, + .current = SANDBOX_LDO2_AUTOSET_EXPECTED_UA, + .enable = SANDBOX_LDO2_AUTOSET_EXPECTED_ENABLE, + }, +}; + +static int list_count = ARRAY_SIZE(expected_setting_list); + +/* Test regulator list autoset method */ +static int dm_test_power_regulator_autoset_list(struct dm_test_state *dms) +{ + struct udevice *dev_list[2], *dev; + int i; + + /* + * Test the settings of the regulator list: + * LDO1 with fdt properties: + * - min-microvolt = max-microvolt = 1800000 + * - min-microamp = max-microamp = 100000 + * - always-on = not set + * - boot-on = set + * Expected output state: uV=1800000; uA=100000; output enabled + * + * LDO2 with fdt properties: + * - min-microvolt = max-microvolt = 3300000 + * - always-on = not set + * - boot-on = not set + * Expected output state: uV=300000(default); output disabled(default) + * The expected settings are defined in: include/power/sandbox_pmic.h. + */ + ut_assertok(regulator_list_autoset(platname_list, dev_list, false)); + + for (i = 0; i < list_count; i++) { + /* Check, that the returned device is non-NULL */ + ut_assert(dev_list[i]); + + /* Check, that the returned device is proper */ + ut_assertok(regulator_get_by_platname(platname_list[i], &dev)); + ut_asserteq_ptr(dev_list[i], dev); + + /* Check, that regulator output Voltage value is as expected */ + ut_asserteq(regulator_get_value(dev_list[i]), + expected_setting_list[i].voltage); + + /* Check, that regulator output Current value is as expected */ + ut_asserteq(regulator_get_current(dev_list[i]), + expected_setting_list[i].current); + + /* Check, that regulator output Enable state is as expected */ + ut_asserteq(regulator_get_enable(dev_list[i]), + expected_setting_list[i].enable); + } + + return 0; +} +DM_TEST(dm_test_power_regulator_autoset_list, DM_TESTF_SCAN_FDT); diff --git a/test/dm/rtc.c b/test/dm/rtc.c new file mode 100644 index 0000000..9397cf7 --- /dev/null +++ b/test/dm/rtc.c @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <common.h> +#include <dm.h> +#include <rtc.h> +#include <asm/io.h> +#include <dm/test.h> +#include <dm/ut.h> +#include <asm/test.h> + +/* Simple RTC sanity check */ +static int dm_test_rtc_base(struct dm_test_state *dms) +{ + struct udevice *dev; + + ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_RTC, 2, &dev)); + ut_assertok(uclass_get_device(UCLASS_RTC, 0, &dev)); + ut_assertok(uclass_get_device(UCLASS_RTC, 1, &dev)); + + return 0; +} +DM_TEST(dm_test_rtc_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static void show_time(const char *msg, struct rtc_time *time) +{ + printf("%s: %02d/%02d/%04d %02d:%02d:%02d\n", msg, + time->tm_mday, time->tm_mon, time->tm_year, + time->tm_hour, time->tm_min, time->tm_sec); +} + +static int cmp_times(struct rtc_time *expect, struct rtc_time *time, bool show) +{ + bool same; + + same = expect->tm_sec == time->tm_sec; + same &= expect->tm_min == time->tm_min; + same &= expect->tm_hour == time->tm_hour; + same &= expect->tm_mday == time->tm_mday; + same &= expect->tm_mon == time->tm_mon; + same &= expect->tm_year == time->tm_year; + if (!same && show) { + show_time("expected", expect); + show_time("actual", time); + } + + return same ? 0 : -EINVAL; +} + +/* Set and get the time */ +static int dm_test_rtc_set_get(struct dm_test_state *dms) +{ + struct rtc_time now, time, cmp; + struct udevice *dev, *emul; + long offset, old_offset, old_base_time; + + ut_assertok(uclass_get_device(UCLASS_RTC, 0, &dev)); + ut_assertok(dm_rtc_get(dev, &now)); + + ut_assertok(device_find_first_child(dev, &emul)); + ut_assert(emul != NULL); + + /* Tell the RTC to go into manual mode */ + old_offset = sandbox_i2c_rtc_set_offset(emul, false, 0); + old_base_time = sandbox_i2c_rtc_get_set_base_time(emul, -1); + + memset(&time, '\0', sizeof(time)); + time.tm_mday = 25; + time.tm_mon = 8; + time.tm_year = 2004; + time.tm_sec = 0; + time.tm_min = 18; + time.tm_hour = 18; + ut_assertok(dm_rtc_set(dev, &time)); + + memset(&cmp, '\0', sizeof(cmp)); + ut_assertok(dm_rtc_get(dev, &cmp)); + ut_assertok(cmp_times(&time, &cmp, true)); + + /* Increment by 1 second */ + offset = sandbox_i2c_rtc_set_offset(emul, false, 0); + sandbox_i2c_rtc_set_offset(emul, false, offset + 1); + + memset(&cmp, '\0', sizeof(cmp)); + ut_assertok(dm_rtc_get(dev, &cmp)); + ut_asserteq(1, cmp.tm_sec); + + /* Check against original offset */ + sandbox_i2c_rtc_set_offset(emul, false, old_offset); + ut_assertok(dm_rtc_get(dev, &cmp)); + ut_assertok(cmp_times(&now, &cmp, true)); + + /* Back to the original offset */ + sandbox_i2c_rtc_set_offset(emul, false, 0); + memset(&cmp, '\0', sizeof(cmp)); + ut_assertok(dm_rtc_get(dev, &cmp)); + ut_assertok(cmp_times(&now, &cmp, true)); + + /* Increment the base time by 1 emul */ + sandbox_i2c_rtc_get_set_base_time(emul, old_base_time + 1); + memset(&cmp, '\0', sizeof(cmp)); + ut_assertok(dm_rtc_get(dev, &cmp)); + if (now.tm_sec == 59) { + ut_asserteq(0, cmp.tm_sec); + } else { + ut_asserteq(now.tm_sec + 1, cmp.tm_sec); + } + + old_offset = sandbox_i2c_rtc_set_offset(emul, true, 0); + + return 0; +} +DM_TEST(dm_test_rtc_set_get, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Reset the time */ +static int dm_test_rtc_reset(struct dm_test_state *dms) +{ + struct rtc_time now; + struct udevice *dev, *emul; + long old_base_time, base_time; + + ut_assertok(uclass_get_device(UCLASS_RTC, 0, &dev)); + ut_assertok(dm_rtc_get(dev, &now)); + + ut_assertok(device_find_first_child(dev, &emul)); + ut_assert(emul != NULL); + + old_base_time = sandbox_i2c_rtc_get_set_base_time(emul, 0); + + ut_asserteq(0, sandbox_i2c_rtc_get_set_base_time(emul, -1)); + + /* Resetting the RTC should put he base time back to normal */ + ut_assertok(dm_rtc_reset(dev)); + base_time = sandbox_i2c_rtc_get_set_base_time(emul, -1); + ut_asserteq(old_base_time, base_time); + + return 0; +} +DM_TEST(dm_test_rtc_reset, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Check that two RTC devices can be used independently */ +static int dm_test_rtc_dual(struct dm_test_state *dms) +{ + struct rtc_time now1, now2, cmp; + struct udevice *dev1, *dev2; + struct udevice *emul1, *emul2; + long offset; + + ut_assertok(uclass_get_device(UCLASS_RTC, 0, &dev1)); + ut_assertok(dm_rtc_get(dev1, &now1)); + ut_assertok(uclass_get_device(UCLASS_RTC, 1, &dev2)); + ut_assertok(dm_rtc_get(dev2, &now2)); + + ut_assertok(device_find_first_child(dev1, &emul1)); + ut_assert(emul1 != NULL); + ut_assertok(device_find_first_child(dev2, &emul2)); + ut_assert(emul2 != NULL); + + offset = sandbox_i2c_rtc_set_offset(emul1, false, -1); + sandbox_i2c_rtc_set_offset(emul2, false, offset + 1); + memset(&cmp, '\0', sizeof(cmp)); + ut_assertok(dm_rtc_get(dev2, &cmp)); + ut_asserteq(-EINVAL, cmp_times(&now1, &cmp, false)); + + memset(&cmp, '\0', sizeof(cmp)); + ut_assertok(dm_rtc_get(dev1, &cmp)); + ut_assertok(cmp_times(&now1, &cmp, true)); + + return 0; +} +DM_TEST(dm_test_rtc_dual, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/test-dm.sh b/test/dm/test-dm.sh index 6158f68..5c47ffd 100755 --- a/test/dm/test-dm.sh +++ b/test/dm/test-dm.sh @@ -6,12 +6,11 @@ die() { } NUM_CPUS=$(cat /proc/cpuinfo |grep -c processor) -dtc -I dts -O dtb test/dm/test.dts -o test/dm/test.dtb make O=sandbox sandbox_config || die "Cannot configure U-Boot" make O=sandbox -s -j${NUM_CPUS} || die "Cannot build U-Boot" dd if=/dev/zero of=spi.bin bs=1M count=2 echo -n "this is a test" > testflash.bin dd if=/dev/zero bs=1M count=4 >>testflash.bin -./sandbox/u-boot -d test/dm/test.dtb -c "dm test" +./sandbox/u-boot -d ./sandbox/arch/sandbox/dts/test.dtb -c "dm test" rm spi.bin rm testflash.bin diff --git a/test/dm/test-main.c b/test/dm/test-main.c index a47bb37..7348f69 100644 --- a/test/dm/test-main.c +++ b/test/dm/test-main.c @@ -78,8 +78,7 @@ int dm_test_main(const char *test_name) */ if (!gd->fdt_blob || fdt_next_node(gd->fdt_blob, 0, NULL) < 0) { puts("Please run with test device tree:\n" - " dtc -I dts -O dtb test/dm/test.dts -o test/dm/test.dtb\n" - " ./u-boot -d test/dm/test.dtb\n"); + " ./u-boot -d arch/sandbox/dts/test.dtb\n"); ut_assert(gd->fdt_blob); } diff --git a/test/time_ut.c b/test/time_ut.c new file mode 100644 index 0000000..6b52245 --- /dev/null +++ b/test/time_ut.c @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <errno.h> + +static int test_get_timer(void) +{ + ulong base, start, next, diff; + int iter; + + base = get_timer(0); + start = get_timer(0); + for (iter = 0; iter < 10; iter++) { + do { + next = get_timer(0); + } while (start == next); + + if (start + 1 != next) { + printf("%s: iter=%d, start=%lu, next=%lu, expected a difference of 1\n", + __func__, iter, start, next); + return -EINVAL; + } + start++; + } + + /* + * Check that get_timer(base) matches our elapsed time, allowing that + * an extra millisecond may have passed. + */ + diff = get_timer(base); + if (diff != iter && diff != iter + 1) { + printf("%s: expected get_timer(base) to match elapsed time: diff=%lu, expected=%d\n", + __func__, diff, iter); + return -EINVAL; + } + + return 0; +} + +static int test_timer_get_us(void) +{ + ulong prev, next, min = 1000000; + long delta; + int iter; + + /* Find the minimum delta we can measure, in microseconds */ + prev = timer_get_us(); + for (iter = 0; iter < 100; ) { + next = timer_get_us(); + if (next != prev) { + delta = next - prev; + if (delta < 0) { + printf("%s: timer_get_us() went backwards from %lu to %lu\n", + __func__, prev, next); + return -EINVAL; + } else if (delta != 0) { + if (delta < min) + min = delta; + prev = next; + iter++; + } + } + } + + if (min != 1) { + printf("%s: Minimum microsecond delta should be 1 but is %lu\n", + __func__, min); + return -EINVAL; + } + + return 0; +} + +static int test_time_comparison(void) +{ + ulong start_us, end_us, delta_us; + long error; + ulong start; + + start = get_timer(0); + start_us = timer_get_us(); + while (get_timer(start) < 1000) + ; + end_us = timer_get_us(); + delta_us = end_us - start_us; + error = delta_us - 1000000; + printf("%s: Microsecond time for 1 second: %lu, error = %ld\n", + __func__, delta_us, error); + if (abs(error) > 1000) + return -EINVAL; + + return 0; +} + +static int test_udelay(void) +{ + long error; + ulong start, delta; + int iter; + + start = get_timer(0); + for (iter = 0; iter < 1000; iter++) + udelay(1000); + delta = get_timer(start); + error = delta - 1000; + printf("%s: Delay time for 1000 udelay(1000): %lu ms, error = %ld\n", + __func__, delta, error); + if (abs(error) > 100) + return -EINVAL; + + return 0; +} + +static int do_ut_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret = 0; + + ret |= test_get_timer(); + ret |= test_timer_get_us(); + ret |= test_time_comparison(); + ret |= test_udelay(); + + printf("Test %s\n", ret ? "failed" : "passed"); + + return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS; +} + +U_BOOT_CMD( + ut_time, 1, 1, do_ut_time, + "Very basic test of time functions", + "" +); diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 1173eea..daa02a7 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -8,6 +8,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#define _GNU_SOURCE + #include <errno.h> #include <env_flags.h> #include <fcntl.h> diff --git a/tools/imagetool.h b/tools/imagetool.h index 3e15b4e..b7874f4 100644 --- a/tools/imagetool.h +++ b/tools/imagetool.h @@ -16,6 +16,7 @@ #include <stdlib.h> #include <string.h> #include <sys/stat.h> +#include <sys/types.h> #include <time.h> #include <unistd.h> #include <u-boot/sha1.h> diff --git a/tools/logos/solidrun.bmp b/tools/logos/solidrun.bmp Binary files differnew file mode 100644 index 0000000..93db1f8 --- /dev/null +++ b/tools/logos/solidrun.bmp diff --git a/tools/proftool.c b/tools/proftool.c index 3482951..9ce7a77 100644 --- a/tools/proftool.c +++ b/tools/proftool.c @@ -16,6 +16,7 @@ #include <string.h> #include <unistd.h> #include <sys/param.h> +#include <sys/types.h> #include <compiler.h> #include <trace.h> |
