diff options
42 files changed, 1953 insertions, 1067 deletions
@@ -303,6 +303,11 @@ D: Support for Nios Stratix Development Kit (DK-1S10) D: Support for SSV ADNP/ESC1 (Nios Cyclone) W: http://www.li-pro.net +N: Dave Liu +E: daveliu@freescale.com +D: Support for MPC832x, MPC8360, MPC837x +W: www.freescale.com + N: Raymond Lo E: lo@routefree.com D: Support for DOS partitions diff --git a/MAINTAINERS b/MAINTAINERS index fa0e9ea..43b3b79 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -227,7 +227,9 @@ The LEOX team <team@leox.org> Dave Liu <daveliu@freescale.com> + MPC832XEMDS MPC832x MPC8360EMDS MPC8360 + MPC837XEMDS MPC837x Nye Liu <nyet@zumanetworks.com> @@ -313,6 +313,7 @@ LIST_83xx=" \ MPC8349ITXGP \ MPC8360EMDS \ MPC8360EMDS_ATM \ + MPC837XEMDS \ sbc8349 \ TQM834x \ " @@ -1922,6 +1922,16 @@ MPC8360EMDS_ATM_config: unconfig fi ; @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale +MPC837XEMDS_config \ +MPC837XEMDS_HOST_config: unconfig + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ + if [ "$(findstring _HOST_,$@)" ] ; then \ + echo -n "... PCI HOST " ; \ + echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ + fi ; + @$(MKCONFIG) -a MPC837XEMDS ppc mpc83xx mpc837xemds freescale + sbc8349_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index 861c143..42019fb 100644 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -23,9 +23,7 @@ */ #include <common.h> -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#elif defined(CONFIG_OF_LIBFDT) +#if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #endif #include <pci.h> @@ -103,16 +101,6 @@ void pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { -#if defined(CONFIG_OF_FLAT_TREE) - u32 *p; - int len; - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } -#endif ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index e738613..2fc4fd6 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -184,16 +184,6 @@ void pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { -#if defined(CONFIG_OF_FLAT_TREE) - u32 *p; - int len; - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } -#endif ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c index 6ba25d4..6adf7e7 100644 --- a/board/freescale/mpc832xemds/mpc832xemds.c +++ b/board/freescale/mpc832xemds/mpc832xemds.c @@ -27,9 +27,7 @@ #else #include <asm/mmu.h> #endif -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#elif defined(CONFIG_OF_LIBFDT) +#if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #endif #if defined(CONFIG_PQ_MDS_PIB) @@ -169,16 +167,6 @@ int checkboard(void) #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { -#if defined(CONFIG_OF_FLAT_TREE) - u32 *p; - int len; - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } -#endif ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c index 7818a2e..b030422 100644 --- a/board/freescale/mpc832xemds/pci.c +++ b/board/freescale/mpc832xemds/pci.c @@ -18,10 +18,9 @@ #include <common.h> #include <pci.h> #include <i2c.h> -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#elif defined(CONFIG_OF_LIBFDT) +#if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> +#include <fdt_support.h> #endif #include <asm/fsl_i2c.h> @@ -262,37 +261,26 @@ void pci_init_board(void) #endif /* CONFIG_PCISLAVE */ #if defined(CONFIG_OF_LIBFDT) -void -ft_pci_setup(void *blob, bd_t *bd) +void ft_pci_setup(void *blob, bd_t *bd) { int nodeoffset; - int err; int tmp[2]; + const char *path; - nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500"); + nodeoffset = fdt_path_offset(blob, "/aliases"); if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(hose[0].first_busno); - tmp[1] = cpu_to_be32(hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", - tmp, sizeof(tmp)); - - tmp[0] = cpu_to_be32(gd->pci_clk); - err = fdt_setprop(blob, nodeoffset, "clock-frequency", - tmp, sizeof(tmp[0])); - } -} -#elif defined(CONFIG_OF_FLAT_TREE) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); - if (p != NULL) { - p[0] = hose[0].first_busno; - p[1] = hose[0].last_busno; + path = fdt_getprop(blob, nodeoffset, "pci0", NULL); + if (path) { + tmp[0] = cpu_to_be32(hose[0].first_busno); + tmp[1] = cpu_to_be32(hose[0].last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); + } } } -#endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_OF_LIBFDT */ #endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 39c0916..3d72eb7 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -32,9 +32,7 @@ #if defined(CONFIG_SPD_EEPROM) #include <spd_sdram.h> #endif -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#elif defined(CONFIG_OF_LIBFDT) +#if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #endif @@ -256,16 +254,6 @@ void sdram_init(void) #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { -#if defined(CONFIG_OF_FLAT_TREE) - u32 *p; - int len; - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } -#endif ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index 7bcdccb..564e436 100644 --- a/board/freescale/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -25,10 +25,9 @@ #include <pci.h> #include <asm/mpc8349_pci.h> #include <i2c.h> -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#elif defined(CONFIG_OF_LIBFDT) +#if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> +#include <fdt_support.h> #endif @@ -389,58 +388,39 @@ pci_init_board(void) } #if defined(CONFIG_OF_LIBFDT) -void -ft_pci_setup(void *blob, bd_t *bd) +void ft_pci_setup(void *blob, bd_t *bd) { int nodeoffset; - int err; int tmp[2]; + const char *path; - nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500"); + nodeoffset = fdt_path_offset(blob, "/aliases"); if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", - tmp, sizeof(tmp)); - - tmp[0] = cpu_to_be32(gd->pci_clk); - err = fdt_setprop(blob, nodeoffset, "clock-frequency", - tmp, sizeof(tmp[0])); - } + path = fdt_getprop(blob, nodeoffset, "pci0", NULL); + if (path) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); + } #ifdef CONFIG_MPC83XX_PCI2 - nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8600"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(pci_hose[1].first_busno); - tmp[1] = cpu_to_be32(pci_hose[1].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", - tmp, sizeof(tmp)); - - tmp[0] = cpu_to_be32(gd->pci_clk); - err = fdt_setprop(blob, nodeoffset, "clock-frequency", - tmp, sizeof(tmp[0])); - } + path = fdt_getprop(blob, nodeoffset, "pci1", NULL); + if (path) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); + } #endif -} -#elif defined(CONFIG_OF_FLAT_TREE) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[0].first_busno; - p[1] = pci_hose[0].last_busno; - } - -#ifdef CONFIG_MPC83XX_PCI2 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[1].first_busno; - p[1] = pci_hose[1].last_busno; } -#endif } -#endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_OF_LIBFDT */ #endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index c82f784..8c19ad6 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -37,9 +37,7 @@ #else #include <asm/mmu.h> #endif -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#elif defined(CONFIG_OF_LIBFDT) +#if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #endif @@ -389,16 +387,6 @@ int misc_init_r(void) #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { -#if defined(CONFIG_OF_FLAT_TREE) - u32 *p; - int len; - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } -#endif ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c index a764a61..d33edf3 100644 --- a/board/freescale/mpc8349itx/pci.c +++ b/board/freescale/mpc8349itx/pci.c @@ -29,10 +29,9 @@ #include <pci.h> #include <asm/mpc8349_pci.h> #include <i2c.h> -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#elif defined(CONFIG_OF_LIBFDT) +#if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> +#include <fdt_support.h> #endif DECLARE_GLOBAL_DATA_PTR; @@ -335,58 +334,39 @@ void pci_init_board(void) } #if defined(CONFIG_OF_LIBFDT) -void -ft_pci_setup(void *blob, bd_t *bd) +void ft_pci_setup(void *blob, bd_t *bd) { int nodeoffset; - int err; int tmp[2]; + const char *path; - nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500"); + nodeoffset = fdt_path_offset(blob, "/aliases"); if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", - tmp, sizeof(tmp)); - - tmp[0] = cpu_to_be32(gd->pci_clk); - err = fdt_setprop(blob, nodeoffset, "clock-frequency", - tmp, sizeof(tmp[0])); - } + path = fdt_getprop(blob, nodeoffset, "pci0", NULL); + if (path) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); + } #ifdef CONFIG_MPC83XX_PCI2 - nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(pci_hose[1].first_busno); - tmp[1] = cpu_to_be32(pci_hose[1].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", - tmp, sizeof(tmp)); - - tmp[0] = cpu_to_be32(gd->pci_clk); - err = fdt_setprop(blob, nodeoffset, "clock-frequency", - tmp, sizeof(tmp[0])); - } + path = fdt_getprop(blob, nodeoffset, "pci1", NULL); + if (path) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); + } #endif -} -#elif defined(CONFIG_OF_FLAT_TREE) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[0].first_busno; - p[1] = pci_hose[0].last_busno; - } - -#ifdef CONFIG_MPC83XX_PCI2 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[1].first_busno; - p[1] = pci_hose[1].last_busno; } -#endif } -#endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_OF_LIBFDT */ #endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index e050cd4..2fcef8b 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -25,9 +25,7 @@ #else #include <asm/mmu.h> #endif -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#elif defined(CONFIG_OF_LIBFDT) +#if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #endif #if defined(CONFIG_PQ_MDS_PIB) @@ -87,6 +85,11 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 1, 3, 0, 2}, /* MDIO */ {0, 2, 1, 0, 1}, /* MDC */ + {5, 0, 1, 0, 2}, /* UART2_SOUT */ + {5, 1, 2, 0, 3}, /* UART2_CTS */ + {5, 2, 1, 0, 1}, /* UART2_RTS */ + {5, 3, 2, 0, 2}, /* UART2_SIN */ + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ }; @@ -106,6 +109,9 @@ int board_early_init_f(void) immr->sysconf.spridr == SPR_8360E_REV21) bcsr[0xe] = 0x30; + /* Enable second UART */ + bcsr[0x9] &= ~0x01; + return 0; } @@ -295,19 +301,48 @@ void sdram_init(void) #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { -#if defined(CONFIG_OF_FLAT_TREE) - u32 *p; - int len; - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } -#endif + const immap_t *immr = (immap_t *)CFG_IMMR; + ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + /* + * mpc8360ea pb mds errata 2: RGMII timing + * if on mpc8360ea rev. 2.1, + * change both ucc phy-connection-types from rgmii-id to rgmii-rxid + */ + if (immr->sysconf.spridr == SPR_8360_REV21 || + immr->sysconf.spridr == SPR_8360E_REV21) { + int nodeoffset; + const char *prop; + const char *path; + + nodeoffset = fdt_path_offset(fdt, "/aliases"); + if (nodeoffset >= 0) { +#if defined(CONFIG_HAS_ETH0) + /* fixup UCC 1 if using rgmii-id mode */ + path = fdt_getprop(blob, nodeoffset, "ethernet0", NULL); + if (path) { + prop = fdt_getprop(blob, nodeoffset, + "phy-connection-type", 0); + if (prop && (strcmp(prop, "rgmii-id") == 0)) + fdt_setprop(blob, nodeoffset, "phy-connection-type", + "rgmii-rxid", sizeof("rgmii-rxid")); + } +#endif +#if defined(CONFIG_HAS_ETH1) + /* fixup UCC 2 if using rgmii-id mode */ + path = fdt_getprop(blob, nodeoffset, "ethernet1", NULL); + if (path) { + prop = fdt_getprop(blob, nodeoffset, + "phy-connection-type", 0); + if (prop && (strcmp(prop, "rgmii-id") == 0)) + fdt_setprop(blob, nodeoffset, "phy-connection-type", + "rgmii-rxid", sizeof("rgmii-rxid")); + } +#endif + } + } } #endif diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c index f18e532..4a0d460 100644 --- a/board/freescale/mpc8360emds/pci.c +++ b/board/freescale/mpc8360emds/pci.c @@ -18,10 +18,9 @@ #include <common.h> #include <pci.h> #include <i2c.h> -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#elif defined(CONFIG_OF_LIBFDT) +#if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> +#include <fdt_support.h> #endif #include <asm/fsl_i2c.h> @@ -262,37 +261,26 @@ void pci_init_board(void) #endif /* CONFIG_PCISLAVE */ #if defined(CONFIG_OF_LIBFDT) -void -ft_pci_setup(void *blob, bd_t *bd) +void ft_pci_setup(void *blob, bd_t *bd) { int nodeoffset; - int err; int tmp[2]; + const char *path; - nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500"); + nodeoffset = fdt_path_offset(blob, "/aliases"); if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(hose[0].first_busno); - tmp[1] = cpu_to_be32(hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", - tmp, sizeof(tmp)); - - tmp[0] = cpu_to_be32(gd->pci_clk); - err = fdt_setprop(blob, nodeoffset, "clock-frequency", - tmp, sizeof(tmp[0])); - } -} -#elif defined(CONFIG_OF_FLAT_TREE) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); - if (p != NULL) { - p[0] = hose[0].first_busno; - p[1] = hose[0].last_busno; + path = fdt_getprop(blob, nodeoffset, "pci0", NULL); + if (path) { + tmp[0] = cpu_to_be32(hose[0].first_busno); + tmp[1] = cpu_to_be32(hose[0].last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); + } } } -#endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_OF_LIBFDT */ #endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile new file mode 100644 index 0000000..5ec7a87 --- /dev/null +++ b/board/freescale/mpc837xemds/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mpc837xemds/config.mk b/board/freescale/mpc837xemds/config.mk new file mode 100644 index 0000000..63c5fc3 --- /dev/null +++ b/board/freescale/mpc837xemds/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC837xEMDS +# + +TEXT_BASE = 0xFE000000 diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c new file mode 100644 index 0000000..6925d23 --- /dev/null +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * CREDITS: Kim Phillips contribute to LIBFDT code + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <i2c.h> +#include <spd.h> +#if defined(CONFIG_SPD_EEPROM) +#include <spd_sdram.h> +#endif +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif +#if defined(CONFIG_PQ_MDS_PIB) +#include "../common/pq-mds-pib.h" +#endif + +int board_early_init_f(void) +{ + u8 *bcsr = (u8 *)CFG_BCSR; + + /* Enable flash write */ + bcsr[0x9] &= ~0x04; + /* Clear all of the interrupt of BCSR */ + bcsr[0xe] = 0xff; + + return 0; +} + +int board_early_init_r(void) +{ +#ifdef CONFIG_PQ_MDS_PIB + pib_init(); +#endif + return 0; +} + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif +int fixed_sdram(void); + +long int initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(); +#else + msize = fixed_sdram(); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + /* Initialize DDR ECC byte */ + ddr_enable_ecc(msize * 1024 * 1024); +#endif + + /* return total bus DDR size(bytes) */ + return (msize * 1024 * 1024); +} + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = CFG_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + + im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; + im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); + +#if (CFG_DDR_SIZE != 512) +#warning Currenly any ddr size other than 512 is not supported +#endif + im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + udelay(50000); + + im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; + udelay(1000); + + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + udelay(1000); + + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + __asm__ __volatile__("sync"); + udelay(1000); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + udelay(2000); + return CFG_DDR_SIZE; +} +#endif /*!CFG_SPD_EEPROM */ + +int checkboard(void) +{ + puts("Board: Freescale MPC837xEMDS\n"); + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c new file mode 100644 index 0000000..ab90979 --- /dev/null +++ b/board/freescale/mpc837xemds/pci.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <asm/mmu.h> +#include <asm/io.h> +#include <common.h> +#include <mpc83xx.h> +#include <pci.h> +#include <i2c.h> +#include <asm/fsl_i2c.h> + +#if defined(CONFIG_PCI) +static struct pci_region pci_regions[] = { + { + bus_start: CFG_PCI_MEM_BASE, + phys_start: CFG_PCI_MEM_PHYS, + size: CFG_PCI_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CFG_PCI_MMIO_BASE, + phys_start: CFG_PCI_MMIO_PHYS, + size: CFG_PCI_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CFG_PCI_IO_BASE, + phys_start: CFG_PCI_IO_PHYS, + size: CFG_PCI_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; + + /* Enable all 5 PCI_CLK_OUTPUTS */ + clk->occr |= 0xf8000000; + udelay(2000); + + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + udelay(2000); + + mpc83xx_pci_init(1, reg, 0); +} +#endif /* CONFIG_PCI */ diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c index eadf230..527f7e4 100644 --- a/board/sbc8349/pci.c +++ b/board/sbc8349/pci.c @@ -30,6 +30,10 @@ #include <pci.h> #include <asm/mpc8349_pci.h> #include <i2c.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#include <fdt_support.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -323,26 +327,40 @@ pci_init_board(void) } -#ifdef CONFIG_OF_FLAT_TREE -void -ft_pci_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_LIBFDT) +void ft_pci_setup(void *blob, bd_t *bd) { - u32 *p; - int len; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[0].first_busno; - p[1] = pci_hose[0].last_busno; + int nodeoffset; + int tmp[2]; + const char *path; + + nodeoffset = fdt_path_offset(blob, "/aliases"); + if (nodeoffset >= 0) { + path = fdt_getprop(blob, nodeoffset, "pci0", NULL); + if (path) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); } - #ifdef CONFIG_MPC83XX_PCI2 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[1].first_busno; - p[1] = pci_hose[1].last_busno; - } + path = fdt_getprop(blob, nodeoffset, "pci1", NULL); + if (path) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); + } #endif + } } -#endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_OF_LIBFDT */ #endif /* CONFIG_PCI */ diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 86166ea..5446c20 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -32,12 +32,11 @@ #include <i2c.h> #include <spd.h> #include <miiphy.h> -#include <command.h> #if defined(CONFIG_SPD_EEPROM) #include <spd_sdram.h> #endif -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> #endif int fixed_sdram(void); @@ -235,348 +234,12 @@ void sdram_init(void) } #endif -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) -/* - * ECC user commands - */ -void ecc_print_status(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ddr83xx_t *ddr = &immap->ddr; - - printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); - - /* Interrupts */ - printf("Memory Error Interrupt Enable:\n"); - printf(" Multiple-Bit Error Interrupt Enable: %d\n", - (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); - printf(" Single-Bit Error Interrupt Enable: %d\n", - (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); - printf(" Memory Select Error Interrupt Enable: %d\n\n", - (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); - - /* Error disable */ - printf("Memory Error Disable:\n"); - printf(" Multiple-Bit Error Disable: %d\n", - (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); - printf(" Sinle-Bit Error Disable: %d\n", - (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); - printf(" Memory Select Error Disable: %d\n\n", - (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); - - /* Error injection */ - printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n", - ddr->data_err_inject_hi, ddr->data_err_inject_lo); - - printf("Memory Data Path Error Injection Mask ECC:\n"); - printf(" ECC Mirror Byte: %d\n", - (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); - printf(" ECC Injection Enable: %d\n", - (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); - printf(" ECC Error Injection Mask: 0x%02x\n\n", - ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); - - /* SBE counter/threshold */ - printf("Memory Single-Bit Error Management (0..255):\n"); - printf(" Single-Bit Error Threshold: %d\n", - (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); - printf(" Single-Bit Error Counter: %d\n\n", - (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); - - /* Error detect */ - printf("Memory Error Detect:\n"); - printf(" Multiple Memory Errors: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); - printf(" Multiple-Bit Error: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); - printf(" Single-Bit Error: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); - printf(" Memory Select Error: %d\n\n", - (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); - - /* Capture data */ - printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address); - printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n", - ddr->capture_data_hi, ddr->capture_data_lo); - printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", - ddr->capture_ecc & CAPTURE_ECC_ECE); - - printf("Memory Error Attributes Capture:\n"); - printf(" Data Beat Number: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT); - printf(" Transaction Size: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT); - printf(" Transaction Source: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT); - printf(" Transaction Type: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT); - printf(" Error Information Valid: %d\n\n", - ddr->capture_attributes & ECC_CAPT_ATTR_VLD); -} - -int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ddr83xx_t *ddr = &immap->ddr; - volatile u32 val; - u64 *addr, count, val64; - register u64 *i; - - if (argc > 4) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - if (argc == 2) { - if (strcmp(argv[1], "status") == 0) { - ecc_print_status(); - return 0; - } else if (strcmp(argv[1], "captureclear") == 0) { - ddr->capture_address = 0; - ddr->capture_data_hi = 0; - ddr->capture_data_lo = 0; - ddr->capture_ecc = 0; - ddr->capture_attributes = 0; - return 0; - } - } - - if (argc == 3) { - if (strcmp(argv[1], "sbecnt") == 0) { - val = simple_strtoul(argv[2], NULL, 10); - if (val > 255) { - printf("Incorrect Counter value, should be 0..255\n"); - return 1; - } - - val = (val << ECC_ERROR_MAN_SBEC_SHIFT); - val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); - - ddr->err_sbe = val; - return 0; - } else if (strcmp(argv[1], "sbethr") == 0) { - val = simple_strtoul(argv[2], NULL, 10); - if (val > 255) { - printf("Incorrect Counter value, should be 0..255\n"); - return 1; - } - - val = (val << ECC_ERROR_MAN_SBET_SHIFT); - val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); - - ddr->err_sbe = val; - return 0; - } else if (strcmp(argv[1], "errdisable") == 0) { - val = ddr->err_disable; - - if (strcmp(argv[2], "+sbe") == 0) { - val |= ECC_ERROR_DISABLE_SBED; - } else if (strcmp(argv[2], "+mbe") == 0) { - val |= ECC_ERROR_DISABLE_MBED; - } else if (strcmp(argv[2], "+mse") == 0) { - val |= ECC_ERROR_DISABLE_MSED; - } else if (strcmp(argv[2], "+all") == 0) { - val |= (ECC_ERROR_DISABLE_SBED | - ECC_ERROR_DISABLE_MBED | - ECC_ERROR_DISABLE_MSED); - } else if (strcmp(argv[2], "-sbe") == 0) { - val &= ~ECC_ERROR_DISABLE_SBED; - } else if (strcmp(argv[2], "-mbe") == 0) { - val &= ~ECC_ERROR_DISABLE_MBED; - } else if (strcmp(argv[2], "-mse") == 0) { - val &= ~ECC_ERROR_DISABLE_MSED; - } else if (strcmp(argv[2], "-all") == 0) { - val &= ~(ECC_ERROR_DISABLE_SBED | - ECC_ERROR_DISABLE_MBED | - ECC_ERROR_DISABLE_MSED); - } else { - printf("Incorrect err_disable field\n"); - return 1; - } - - ddr->err_disable = val; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - return 0; - } else if (strcmp(argv[1], "errdetectclr") == 0) { - val = ddr->err_detect; - - if (strcmp(argv[2], "mme") == 0) { - val |= ECC_ERROR_DETECT_MME; - } else if (strcmp(argv[2], "sbe") == 0) { - val |= ECC_ERROR_DETECT_SBE; - } else if (strcmp(argv[2], "mbe") == 0) { - val |= ECC_ERROR_DETECT_MBE; - } else if (strcmp(argv[2], "mse") == 0) { - val |= ECC_ERROR_DETECT_MSE; - } else if (strcmp(argv[2], "all") == 0) { - val |= (ECC_ERROR_DETECT_MME | - ECC_ERROR_DETECT_MBE | - ECC_ERROR_DETECT_SBE | - ECC_ERROR_DETECT_MSE); - } else { - printf("Incorrect err_detect field\n"); - return 1; - } - - ddr->err_detect = val; - return 0; - } else if (strcmp(argv[1], "injectdatahi") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - - ddr->data_err_inject_hi = val; - return 0; - } else if (strcmp(argv[1], "injectdatalo") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - - ddr->data_err_inject_lo = val; - return 0; - } else if (strcmp(argv[1], "injectecc") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - if (val > 0xff) { - printf("Incorrect ECC inject mask, should be 0x00..0xff\n"); - return 1; - } - val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); - - ddr->ecc_err_inject = val; - return 0; - } else if (strcmp(argv[1], "inject") == 0) { - val = ddr->ecc_err_inject; - - if (strcmp(argv[2], "en") == 0) - val |= ECC_ERR_INJECT_EIEN; - else if (strcmp(argv[2], "dis") == 0) - val &= ~ECC_ERR_INJECT_EIEN; - else - printf("Incorrect command\n"); - - ddr->ecc_err_inject = val; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - return 0; - } else if (strcmp(argv[1], "mirror") == 0) { - val = ddr->ecc_err_inject; - - if (strcmp(argv[2], "en") == 0) - val |= ECC_ERR_INJECT_EMB; - else if (strcmp(argv[2], "dis") == 0) - val &= ~ECC_ERR_INJECT_EMB; - else - printf("Incorrect command\n"); - - ddr->ecc_err_inject = val; - return 0; - } - } - - if (argc == 4) { - if (strcmp(argv[1], "test") == 0) { - addr = (u64 *)simple_strtoul(argv[2], NULL, 16); - count = simple_strtoul(argv[3], NULL, 16); - - if ((u32)addr % 8) { - printf("Address not alligned on double word boundary\n"); - return 1; - } - - disable_interrupts(); - icache_disable(); - - for (i = addr; i < addr + count; i++) { - /* enable injects */ - ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* write memory location injecting errors */ - *i = 0x1122334455667788ULL; - __asm__ __volatile__ ("sync"); - - /* disable injects */ - ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* read data, this generates ECC error */ - val64 = *i; - __asm__ __volatile__ ("sync"); - - /* disable errors for ECC */ - ddr->err_disable |= ~ECC_ERROR_ENABLE; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* re-initialize memory, write the location again - * NOT injecting errors this time */ - *i = 0xcafecafecafecafeULL; - __asm__ __volatile__ ("sync"); - - /* enable errors for ECC */ - ddr->err_disable &= ECC_ERROR_ENABLE; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - } - - icache_enable(); - enable_interrupts(); - - return 0; - } - } - - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; -} - -U_BOOT_CMD( - ecc, 4, 0, do_ecc, - "ecc - support for DDR ECC features\n", - "status - print out status info\n" - "ecc captureclear - clear capture regs data\n" - "ecc sbecnt <val> - set Single-Bit Error counter\n" - "ecc sbethr <val> - set Single-Bit Threshold\n" - "ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n" - " [-|+]sbe - Single-Bit Error\n" - " [-|+]mbe - Multiple-Bit Error\n" - " [-|+]mse - Memory Select Error\n" - " [-|+]all - all errors\n" - "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n" - " mme - Multiple Memory Errors\n" - " sbe - Single-Bit Error\n" - " mbe - Multiple-Bit Error\n" - " mse - Memory Select Error\n" - " all - all errors\n" - "ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n" - "ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n" - "ecc injectecc <ecc> - set ECC Error Injection Mask\n" - "ecc inject <en|dis> - enable/disable error injection\n" - "ecc mirror <en|dis> - enable/disable mirror byte\n" - "ecc test <addr> <cnt> - test mem region:\n" - " - enables injects\n" - " - writes pattern injecting errors\n" - " - disables injects\n" - " - reads pattern back, generates error\n" - " - re-inits memory" -); -#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ - -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - + ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif - ft_cpu_setup(blob, bd); - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } } #endif diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index 2329970..94a3cb8 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -29,7 +29,7 @@ LIB = $(obj)lib$(CPU).a START = start.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - spd_sdram.o ecc.o qe_io.o pci.o + spd_sdram.o ecc.o qe_io.o pci.o fdt.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index f1ea17d..bff3cef 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -31,12 +31,7 @@ #include <command.h> #include <mpc83xx.h> #include <asm/processor.h> -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> -#elif defined(CONFIG_OF_LIBFDT) #include <libfdt.h> -#include <fdt_support.h> -#endif DECLARE_GLOBAL_DATA_PTR; @@ -65,6 +60,10 @@ int checkcpu(void) printf("e300c3, "); break; + case PVR_E300C4: + printf("e300c4, "); + break; + default: printf("Unknown core, "); } @@ -149,6 +148,36 @@ int checkcpu(void) case SPR_8313E_REV10: puts("MPC8313E, "); break; + case SPR_8315E_REV10: + puts("MPC8315E, "); + break; + case SPR_8315_REV10: + puts("MPC8315, "); + break; + case SPR_8314E_REV10: + puts("MPC8314E, "); + break; + case SPR_8314_REV10: + puts("MPC8314, "); + break; + case SPR_8379E_REV10: + puts("MPC8379E, "); + break; + case SPR_8379_REV10: + puts("MPC8379, "); + break; + case SPR_8378E_REV10: + puts("MPC8378E, "); + break; + case SPR_8378_REV10: + puts("MPC8378, "); + break; + case SPR_8377E_REV10: + puts("MPC8377E, "); + break; + case SPR_8377_REV10: + puts("MPC8377, "); + break; default: printf("Rev: Unknown revision number:%08x\n" "Warning: Unsupported cpu revision!\n",spridr); @@ -325,313 +354,6 @@ void watchdog_reset (void) } #endif -#if defined(CONFIG_OF_LIBFDT) - -/* - * "Setter" functions used to add/modify FDT entries. - */ -static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd) -{ - /* Fix it up if it exists, don't create it if it doesn't exist */ - if (fdt_get_property(blob, nodeoffset, name, 0)) { - return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6); - } - return 0; -} -#ifdef CONFIG_HAS_ETH1 -/* second onboard ethernet port */ -static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd) -{ - /* Fix it up if it exists, don't create it if it doesn't exist */ - if (fdt_get_property(blob, nodeoffset, name, 0)) { - return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6); - } - return 0; -} -#endif -#ifdef CONFIG_HAS_ETH2 -/* third onboard ethernet port */ -static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd) -{ - /* Fix it up if it exists, don't create it if it doesn't exist */ - if (fdt_get_property(blob, nodeoffset, name, 0)) { - return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6); - } - return 0; -} -#endif -#ifdef CONFIG_HAS_ETH3 -/* fourth onboard ethernet port */ -static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd) -{ - /* Fix it up if it exists, don't create it if it doesn't exist */ - if (fdt_get_property(blob, nodeoffset, name, 0)) { - return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6); - } - return 0; -} -#endif - -static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) -{ - u32 tmp; - /* Create or update the property */ - tmp = cpu_to_be32(bd->bi_busfreq); - return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); -} - -static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) -{ - u32 tmp; - /* Create or update the property */ - tmp = cpu_to_be32(OF_TBCLK); - return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); -} - - -static int fdt_set_clockfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) -{ - u32 tmp; - /* Create or update the property */ - tmp = cpu_to_be32(gd->core_clk); - return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); -} - -#ifdef CONFIG_QE -static int fdt_set_qe_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) -{ - u32 tmp; - /* Create or update the property */ - tmp = cpu_to_be32(gd->qe_clk); - return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); -} - -static int fdt_set_qe_brgfreq(void *blob, int nodeoffset, const char *name, bd_t *bd) -{ - u32 tmp; - /* Create or update the property */ - tmp = cpu_to_be32(gd->brg_clk); - return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp)); -} -#endif - -/* - * Fixups to the fdt. - */ -static const struct { - char *node; - char *prop; - int (*set_fn)(void *blob, int nodeoffset, const char *name, bd_t *bd); -} fixup_props[] = { - { "/cpus/" OF_CPU, - "timebase-frequency", - fdt_set_tbfreq - }, - { "/cpus/" OF_CPU, - "bus-frequency", - fdt_set_busfreq - }, - { "/cpus/" OF_CPU, - "clock-frequency", - fdt_set_clockfreq - }, - { "/" OF_SOC, - "bus-frequency", - fdt_set_busfreq - }, - { "/" OF_SOC "/serial@4500", - "clock-frequency", - fdt_set_busfreq - }, - { "/" OF_SOC "/serial@4600", - "clock-frequency", - fdt_set_busfreq - }, -#ifdef CONFIG_TSEC1 - { "/" OF_SOC "/ethernet@24000", - "mac-address", - fdt_set_eth0 - }, - { "/" OF_SOC "/ethernet@24000", - "local-mac-address", - fdt_set_eth0 - }, -#endif -#ifdef CONFIG_TSEC2 - { "/" OF_SOC "/ethernet@25000", - "mac-address", - fdt_set_eth1 - }, - { "/" OF_SOC "/ethernet@25000", - "local-mac-address", - fdt_set_eth1 - }, -#endif -#ifdef CONFIG_QE - { "/" OF_QE, - "brg-frequency", - fdt_set_qe_brgfreq - }, - { "/" OF_QE, - "bus-frequency", - fdt_set_qe_busfreq - }, -#ifdef CONFIG_UEC_ETH1 -#if CFG_UEC1_UCC_NUM == 0 /* UCC1 */ - { "/" OF_QE "/ucc@2000", - "mac-address", - fdt_set_eth0 - }, - { "/" OF_QE "/ucc@2000", - "local-mac-address", - fdt_set_eth0 - }, -#elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */ - { "/" OF_QE "/ucc@2200", - "mac-address", - fdt_set_eth0 - }, - { "/" OF_QE "/ucc@2200", - "local-mac-address", - fdt_set_eth0 - }, -#endif -#endif /* CONFIG_UEC_ETH1 */ -#ifdef CONFIG_UEC_ETH2 -#if CFG_UEC2_UCC_NUM == 1 /* UCC2 */ - { "/" OF_QE "/ucc@3000", - "mac-address", - fdt_set_eth1 - }, - { "/" OF_QE "/ucc@3000", - "local-mac-address", - fdt_set_eth1 - }, -#elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */ - { "/" OF_QE "/ucc@3200", - "mac-address", - fdt_set_eth1 - }, - { "/" OF_QE "/ucc@3200", - "local-mac-address", - fdt_set_eth1 - }, -#endif -#endif /* CONFIG_UEC_ETH2 */ -#endif /* CONFIG_QE */ -}; - -void -ft_cpu_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int err; - int j; - - for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) { - nodeoffset = fdt_path_offset(blob, fixup_props[j].node); - if (nodeoffset >= 0) { - err = fixup_props[j].set_fn(blob, nodeoffset, - fixup_props[j].prop, bd); - if (err < 0) - debug("Problem setting %s = %s: %s\n", - fixup_props[j].node, fixup_props[j].prop, - fdt_strerror(err)); - } else { - debug("Couldn't find %s: %s\n", - fixup_props[j].node, fdt_strerror(nodeoffset)); - } - } - - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -} -#elif defined(CONFIG_OF_FLAT_TREE) -void -ft_cpu_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - ulong clock; - - clock = bd->bi_busfreq; - p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(clock); - - p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(clock); - - p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(clock); - - p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len); - if (p != NULL) - *p = cpu_to_be32(clock); - -#ifdef CONFIG_TSEC1 - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enetaddr, 6); - - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enetaddr, 6); -#endif - -#ifdef CONFIG_TSEC2 - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enet1addr, 6); - - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enet1addr, 6); -#endif - -#ifdef CONFIG_UEC_ETH1 -#if CFG_UEC1_UCC_NUM == 0 /* UCC1 */ - p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enetaddr, 6); - - p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enetaddr, 6); -#elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */ - p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enetaddr, 6); - - p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enetaddr, 6); -#endif -#endif - -#ifdef CONFIG_UEC_ETH2 -#if CFG_UEC2_UCC_NUM == 1 /* UCC2 */ - p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enet1addr, 6); - - p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enet1addr, 6); -#elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */ - p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enet1addr, 6); - - p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len); - if (p != NULL) - memcpy(p, bd->bi_enet1addr, 6); -#endif -#endif -} -#endif - #if defined(CONFIG_DDR_ECC) void dma_init(void) { diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 7224979..2b92be0 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -155,6 +155,10 @@ void cpu_init_f (volatile immap_t * im) #ifdef CFG_DDRCDR im->sysconf.ddrcdr = CFG_DDRCDR; #endif + /* Output buffer impedance register */ +#ifdef CFG_OBIR + im->sysconf.obir = CFG_OBIR; +#endif #ifdef CONFIG_QE /* Config QE ioports */ diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c new file mode 100644 index 0000000..f21c54e --- /dev/null +++ b/cpu/mpc83xx/fdt.c @@ -0,0 +1,72 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CONFIG_OF_LIBFDT) + +#include <libfdt.h> +#include <fdt_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +void ft_cpu_setup(void *blob, bd_t *bd) +{ +#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ + defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) + fdt_fixup_ethernet(blob, bd); +#endif + + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", (bd->bi_busfreq / 4), 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "clock-frequency", gd->core_clk, 1); + do_fixup_by_prop_u32(blob, "device_type", "soc", 4, + "bus-frequency", bd->bi_busfreq, 1); +#ifdef CONFIG_QE + do_fixup_by_prop_u32(blob, "device_type", "qe", 4, + "bus-frequency", gd->qe_clk, 1); + do_fixup_by_prop_u32(blob, "device_type", "qe", 4, + "brg-frequency", gd->brg_clk, 1); +#endif + +#ifdef CFG_NS16550 + do_fixup_by_compat_u32(blob, "ns16550", + "clock-frequency", bd->bi_busfreq, 1); +#endif + +#ifdef CONFIG_CPM2 + do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", + "current-speed", bd->bi_baudrate, 1); + + do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", + "clock-frequency", bd->bi_brgfreq, 1); +#endif + + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +} +#endif /* CONFIG_OF_LIBFDT */ diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index 0defb0e..18558db 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -28,8 +28,7 @@ #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> -#elif defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> +#include <fdt_support.h> #endif #include <asm/mpc8349_pci.h> @@ -173,63 +172,41 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot) void ft_pci_setup(void *blob, bd_t *bd) { int nodeoffset; - int err; int tmp[2]; + const char *path; if (pci_num_buses < 1) return; - nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500"); + nodeoffset = fdt_path_offset(blob, "/aliases"); if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", - tmp, sizeof(tmp)); - - tmp[0] = cpu_to_be32(gd->pci_clk); - err = fdt_setprop(blob, nodeoffset, "clock-frequency", - tmp, sizeof(tmp[0])); - } - - if (pci_num_buses < 2) - return; - - nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8600"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", - tmp, sizeof(tmp)); - - tmp[0] = cpu_to_be32(gd->pci_clk); - err = fdt_setprop(blob, nodeoffset, "clock-frequency", - tmp, sizeof(tmp[0])); - } -} -#elif CONFIG_OF_FLAT_TREE -void ft_pci_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - - if (pci_num_buses < 1) - return; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); - if (p) { - p[0] = pci_hose[0].first_busno; - p[1] = pci_hose[0].last_busno; - } - - if (pci_num_buses < 2) - return; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); - if (p) { - p[0] = pci_hose[1].first_busno; - p[1] = pci_hose[1].last_busno; + path = fdt_getprop(blob, nodeoffset, "pci0", NULL); + if (path) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); + } + + if (pci_num_buses < 2) + return; + + path = fdt_getprop(blob, nodeoffset, "pci1", NULL); + if (path) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); + } } } -#endif /* CONFIG_OF_FLAT_TREE */ - +#endif /* CONFIG_OF_LIBFDT */ #endif /* CONFIG_83XX_GENERIC_PCI */ diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index ee2d038..29dd470 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 Freescale Semiconductor, Inc. + * (C) Copyright 2006-2007 Freescale Semiconductor, Inc. * * (C) Copyright 2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -198,6 +198,7 @@ long int spd_sdram() if(spd.mem_type == SPD_MEMTYPE_DDR2) { immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE; } + udelay(50000); #endif /* @@ -576,7 +577,7 @@ long int spd_sdram() if (effective_data_rate == 266 || effective_data_rate == 333) { cpo = 0x7; /* READ_LAT + 5/4 */ } else if (effective_data_rate == 400) { - cpo = 0x9; /* READ_LAT + 7/4 */ + cpo = 0x7; /* READ_LAT + 5/4 */ } else { /* Automatic calibration */ cpo = 0x1f; @@ -705,9 +706,11 @@ long int spd_sdram() * SDRAM Cfg 2 */ odt_cfg = 0; +#ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU if (odt_rd_cfg | odt_wr_cfg) { odt_cfg = 0x2; /* ODT to IOs during reads */ } +#endif if (spd.mem_type == SPD_MEMTYPE_DDR2) { ddr->sdram_cfg2 = (0 | (0 << 26) /* True DQS */ diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index cba57fa..4f5a866 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -100,7 +100,7 @@ int get_clocks(void) u32 lcrr; u32 csb_clk; -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; @@ -113,6 +113,12 @@ int get_clocks(void) #if !defined(CONFIG_MPC832X) u32 i2c2_clk; #endif +#if defined(CONFIG_MPC8315) + u32 tdm_clk; +#endif +#if defined(CONFIG_MPC837X) + u32 sdhc_clk; +#endif u32 enc_clk; u32 lbiu_clk; u32 lclk_clk; @@ -126,6 +132,13 @@ int get_clocks(void) u32 qe_clk; u32 brg_clk; #endif +#if defined(CONFIG_MPC837X) + u32 pciexp1_clk; + u32 pciexp2_clk; +#endif +#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) + u32 sata_clk; +#endif if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) return -1; @@ -151,7 +164,7 @@ int get_clocks(void) sccr = im->clk.sccr; -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -167,7 +180,7 @@ int get_clocks(void) break; default: /* unkown SCCR_TSEC1CM value */ - return -4; + return -2; } switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { @@ -185,11 +198,11 @@ int get_clocks(void) break; default: /* unkown SCCR_USBDRCM value */ - return -8; + return -3; } #endif -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: tsec2_clk = 0; @@ -205,11 +218,18 @@ int get_clocks(void) break; default: /* unkown SCCR_TSEC2CM value */ - return -5; + return -4; } +#elif defined(CONFIG_MPC8313) + tsec2_clk = tsec1_clk; - i2c1_clk = tsec2_clk; + if (!(sccr & SCCR_TSEC1ON)) + tsec1_clk = 0; + if (!(sccr & SCCR_TSEC2ON)) + tsec2_clk = 0; +#endif +#if defined(CONFIG_MPC834X) switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { case 0: usbmph_clk = 0; @@ -225,7 +245,7 @@ int get_clocks(void) break; default: /* unkown SCCR_USBMPHCM value */ - return -7; + return -5; } if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) { @@ -233,41 +253,138 @@ int get_clocks(void) * USB DR clock is not disabled then * USB MPH & USB DR must have the same rate */ - return -9; + return -6; + } +#endif + switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { + case 0: + enc_clk = 0; + break; + case 1: + enc_clk = csb_clk; + break; + case 2: + enc_clk = csb_clk / 2; + break; + case 3: + enc_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_ENCCM value */ + return -7; } -#elif defined(CONFIG_MPC831X) - tsec2_clk = tsec1_clk; - if (!(sccr & SCCR_TSEC1ON)) - tsec1_clk = 0; - if (!(sccr & SCCR_TSEC2ON)) - tsec2_clk = 0; +#if defined(CONFIG_MPC837X) + switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) { + case 0: + sdhc_clk = 0; + break; + case 1: + sdhc_clk = csb_clk; + break; + case 2: + sdhc_clk = csb_clk / 2; + break; + case 3: + sdhc_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_SDHCCM value */ + return -8; + } +#endif +#if defined(CONFIG_MPC8315) + switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) { + case 0: + tdm_clk = 0; + break; + case 1: + tdm_clk = csb_clk; + break; + case 2: + tdm_clk = csb_clk / 2; + break; + case 3: + tdm_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_TDMCM value */ + return -8; + } #endif -#if !defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834X) + i2c1_clk = tsec2_clk; +#elif defined(CONFIG_MPC8360) i2c1_clk = csb_clk; +#elif defined(CONFIG_MPC832X) + i2c1_clk = enc_clk; +#elif defined(CONFIG_MPC831X) + i2c1_clk = enc_clk; +#elif defined(CONFIG_MPC837X) + i2c1_clk = sdhc_clk; #endif #if !defined(CONFIG_MPC832X) - i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ + i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ #endif - switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { +#if defined(CONFIG_MPC837X) + switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { case 0: - enc_clk = 0; + pciexp1_clk = 0; break; case 1: - enc_clk = csb_clk; + pciexp1_clk = csb_clk; break; case 2: - enc_clk = csb_clk / 2; + pciexp1_clk = csb_clk / 2; break; case 3: - enc_clk = csb_clk / 3; + pciexp1_clk = csb_clk / 3; break; default: - /* unkown SCCR_ENCCM value */ - return -6; + /* unkown SCCR_PCIEXP1CM value */ + return -9; + } + + switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) { + case 0: + pciexp2_clk = 0; + break; + case 1: + pciexp2_clk = csb_clk; + break; + case 2: + pciexp2_clk = csb_clk / 2; + break; + case 3: + pciexp2_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_PCIEXP2CM value */ + return -10; } +#endif + +#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) + switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { + case 0: + sata_clk = 0; + break; + case 1: + sata_clk = csb_clk; + break; + case 2: + sata_clk = csb_clk / 2; + break; + case 3: + sata_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_SATA1CM value */ + return -11; + } +#endif lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); @@ -280,7 +397,7 @@ int get_clocks(void) break; default: /* unknown lcrr */ - return -10; + return -12; } ddr_clk = csb_clk * @@ -316,7 +433,7 @@ int get_clocks(void) break; default: /* unkown core to csb ratio */ - return -12; + return -13; } #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) @@ -327,7 +444,7 @@ int get_clocks(void) #endif gd->csb_clk = csb_clk; -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) gd->tsec1_clk = tsec1_clk; gd->tsec2_clk = tsec2_clk; gd->usbdr_clk = usbdr_clk; @@ -335,6 +452,12 @@ int get_clocks(void) #if defined(CONFIG_MPC834X) gd->usbmph_clk = usbmph_clk; #endif +#if defined(CONFIG_MPC8315) + gd->tdm_clk = tdm_clk; +#endif +#if defined(CONFIG_MPC837X) + gd->sdhc_clk = sdhc_clk; +#endif gd->core_clk = core_clk; gd->i2c1_clk = i2c1_clk; #if !defined(CONFIG_MPC832X) @@ -351,6 +474,13 @@ int get_clocks(void) gd->qe_clk = qe_clk; gd->brg_clk = brg_clk; #endif +#if defined(CONFIG_MPC837X) + gd->pciexp1_clk = pciexp1_clk; + gd->pciexp2_clk = pciexp2_clk; +#endif +#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) + gd->sata_clk = sata_clk; +#endif gd->pci_clk = pci_sync_in; gd->cpu_clk = gd->core_clk; gd->bus_clk = gd->csb_clk; @@ -387,7 +517,13 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) #if !defined(CONFIG_MPC832X) printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000); #endif -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) +#if defined(CONFIG_MPC8315) + printf(" TDM: %4d MHz\n", gd->tdm_clk / 1000000); +#endif +#if defined(CONFIG_MPC837X) + printf(" SDHC: %4d MHz\n", gd->sdhc_clk / 1000000); +#endif +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000); printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000); printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000); @@ -395,6 +531,13 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_MPC834X) printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000); #endif +#if defined(CONFIG_MPC837X) + printf(" PCIEXP1: %4d MHz\n", gd->pciexp1_clk / 1000000); + printf(" PCIEXP2: %4d MHz\n", gd->pciexp2_clk / 1000000); +#endif +#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) + printf(" SATA: %4d MHz\n", gd->sata_clk / 1000000); +#endif return 0; } diff --git a/doc/README.mpc837xemds b/doc/README.mpc837xemds new file mode 100644 index 0000000..3f0cdf7 --- /dev/null +++ b/doc/README.mpc837xemds @@ -0,0 +1,104 @@ +Freescale MPC837xEMDS Board +----------------------------------------- +1. Board Switches and Jumpers +1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board + For some reason, the HW designers describe the switch settings + in terms of 0 and 1, and then map that to physical switches where + the label "On" refers to logic 0 and "Off" is logic 1. + + Switch bits are numbered 1 through, like, 4 6 8 or 10, but the + bits may contribute to signals that are numbered based at 0, + and some of those signals may be high-bit-number-0 too. Heed + well the names and labels and do not get confused. + + "Off" == 1 + "On" == 0 + + SW4[8] is the bit labled 8 on Switch 4. + SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. + SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On" + and bits labeled 8 is set as "Off". + +1.1 For the MPC837xEMDS Processor Board + + First, make sure the board default setting is consistent with the + document shipped with your board. Then apply the following setting: + SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting) + SW4[1-8]= 0000_0110 (core PLL setting) + SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash) + SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH) + SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII) + J3 2-3, TSEC1 LVDD1 with 2.5V + J6 2-3, TSEC2 LVDD2 with 2.5V + J9 2-3, CLKIN from osc on board + J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND + J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND) + mounted, HRCW load from BCSR. + + on board Oscillator: 66M + +2. Memory Map + +2.1. The memory map should look pretty much like this: + + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M + 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M + 0xc000_0000 0xdfff_ffff Empty 512M + 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M + 0xe010_0000 0xe02f_ffff Empty 2M + 0xe030_0000 0xe03f_ffff PCI IO 1M + 0xe040_0000 0xe05f_ffff Empty 2M + 0xe060_0000 0xe060_8000 NAND Flash 32K + 0xf400_0000 0xf7ff_ffff Empty 64M + 0xf800_0000 0xf800_7fff BCSR on CS1 32K + 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC837XEMDS.h + + CONFIG_MPC83XX MPC83xx family for both MPC837x and MPC8360 + CONFIG_MPC837X MPC837x specific + CONFIG_MPC837XEMDS MPC837XEMDS board specific + +4. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC837XEMDS_config + make + +5. Downloading and Flashing Images + +5.0 Download over serial line using Kermit: + + loadb + [Drop to kermit: + ^\c + send <u-boot-bin-image> + c + ] + + + Or via tftp: + + tftp 40000 u-boot.bin + +5.1 Reflash U-boot Image using U-boot + + tftp 40000 u-boot.bin + protect off fe000000 fe1fffff + erase fe000000 fe1fffff + + cp.b 40000 fe000000 xxxx + +You have to supply the correct byte count with 'xxxx' from the TFTP result log. + +6. Notes + 1) The console baudrate for MPC837XEMDS is 115200bps. diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index ca6284b..108cebd 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -674,6 +674,15 @@ uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) return MIIM_CIS8204_EPHYCON_INIT; } +uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) +{ + uint mii_data = read_phy_reg(priv, mii_reg); + + if (priv->flags & TSEC_REDUCED) + mii_data = (mii_data & 0xfff0) | 0x000b; + return mii_data; +} + /* Initialized required registers to appropriate values, zeroing * those we don't care about (unless zero is bad, in which case, * choose a more appropriate value) @@ -1034,6 +1043,7 @@ struct phy_info phy_info_M88E1111S = { (struct phy_cmd[]){ /* config */ /* Reset and configure the PHY */ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1b, 0x848f, &mii_m88e1111s_setmode}, {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index dc2765b..a27c12a 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -69,6 +69,25 @@ static uec_info_t eth2_uec_info = { }; #endif +#ifdef CONFIG_UEC_ETH3 +static uec_info_t eth3_uec_info = { + .uf_info = { + .ucc_num = CFG_UEC3_UCC_NUM, + .rx_clock = CFG_UEC3_RX_CLK, + .tx_clock = CFG_UEC3_TX_CLK, + .eth_type = CFG_UEC3_ETH_TYPE, + }, + .num_threads_tx = UEC_NUM_OF_THREADS_4, + .num_threads_rx = UEC_NUM_OF_THREADS_4, + .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .tx_bd_ring_len = 16, + .rx_bd_ring_len = 16, + .phy_address = CFG_UEC3_PHY_ADDR, + .enet_interface = CFG_UEC3_INTERFACE_MODE, +}; +#endif + static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode) { uec_t *uec_regs; @@ -1238,6 +1257,10 @@ int uec_initialize(int index) #ifdef CONFIG_UEC_ETH2 uec_info = ð2_uec_info; #endif + } else if (index == 2) { +#ifdef CONFIG_UEC_ETH3 + uec_info = ð3_uec_info; +#endif } else { printf("%s: index is illegal.\n", __FUNCTION__); return -EINVAL; diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 05aee74..91acf9b 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -55,7 +55,7 @@ typedef struct global_data { #if defined(CONFIG_MPC83XX) /* There are other clocks in the MPC83XX */ u32 csb_clk; -#if defined (CONFIG_MPC834X) || defined(CONFIG_MPC831X) +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; @@ -63,6 +63,12 @@ typedef struct global_data { #if defined (CONFIG_MPC834X) u32 usbmph_clk; #endif /* CONFIG_MPC834X */ +#if defined(CONFIG_MPC815) + u32 tdm_clk; +#endif +#if defined(CONFIG_MPC837X) + u32 sdhc_clk; +#endif u32 core_clk; u32 i2c1_clk; u32 i2c2_clk; @@ -71,6 +77,13 @@ typedef struct global_data { u32 lclk_clk; u32 ddr_clk; u32 pci_clk; +#if defined(CONFIG_MPC837X) + u32 pciexp1_clk; + u32 pciexp2_clk; +#endif +#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) + u32 sata_clk; +#endif #if defined(CONFIG_MPC8360) u32 ddr_sec_clk; #endif /* CONFIG_MPC8360 */ diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 0de9338..34ea295 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2006 Freescale Semiconductor, Inc. + * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. * * MPC83xx Internal Memory Map * @@ -63,7 +63,8 @@ typedef struct sysconf83xx { u8 res6[0x0C]; u32 ddrcdr; /* DDR Control Driver Register */ u32 ddrdsr; /* DDR Debug Status Register */ - u8 res7[0xD0]; + u32 obir; /* Output Buffer Impedance Register */ + u8 res7[0xCC]; } sysconf83xx_t; /* @@ -553,6 +554,55 @@ typedef struct security83xx { u8 fixme[0x10000]; } security83xx_t; +/* + * PCI Express + */ +typedef struct pex83xx { + u8 fixme[0x1000]; +} pex83xx_t; + +/* + * SATA + */ +typedef struct sata83xx { + u8 fixme[0x1000]; +} sata83xx_t; + +/* + * eSDHC + */ +typedef struct sdhc83xx { + u8 fixme[0x1000]; +} sdhc83xx_t; + +/* + * SerDes + */ +typedef struct serdes83xx { + u8 fixme[0x100]; +} serdes83xx_t; + +/* + * On Chip ROM + */ +typedef struct rom83xx { + u8 mem[0x10000]; +} rom83xx_t; + +/* + * TDM + */ +typedef struct tdm83xx { + u8 fixme[0x200]; +} tdm83xx_t; + +/* + * TDM DMAC + */ +typedef struct tdmdmac83xx { + u8 fixme[0x2000]; +} tdmdmac83xx_t; + #if defined(CONFIG_MPC834X) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ @@ -590,7 +640,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; -#elif defined(CONFIG_MPC831X) +#elif defined(CONFIG_MPC8313) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ @@ -625,6 +675,95 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; +#elif defined(CONFIG_MPC8315) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[2]; /* Global Timers Module */ + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + gpio83xx_t gpio[1]; /* General purpose I/O module */ + u8 res0[0x1300]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res1[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res2[0x900]; + lbus83xx_t lbus; /* Local Bus Controller Registers */ + u8 res3[0x1000]; + spi83xx_t spi; /* Serial Peripheral Interface */ + dma83xx_t dma; /* DMA */ + pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ + u8 res4[0x80]; + ios83xx_t ios; /* Sequencer */ + pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ + u8 res5[0xa00]; + pex83xx_t pciexp[2]; /* PCI Express Controller */ + u8 res6[0xb000]; + tdm83xx_t tdm; /* TDM Controller */ + u8 res7[0x1e00]; + sata83xx_t sata[2]; /* SATA Controller */ + u8 res8[0x9000]; + usb83xx_t usb[1]; /* USB DR Controller */ + tsec83xx_t tsec[2]; + u8 res9[0x6000]; + tdmdmac83xx_t tdmdmac; /* TDM DMAC */ + u8 res10[0x2000]; + security83xx_t security; + u8 res11[0xA3000]; + serdes83xx_t serdes[1]; /* SerDes Registers */ + u8 res12[0x1CF00]; +} immap_t; + +#elif defined(CONFIG_MPC837X) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[2]; /* Global Timers Module */ + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + gpio83xx_t gpio[2]; /* General purpose I/O module */ + u8 res0[0x1200]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res1[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res2[0x900]; + lbus83xx_t lbus; /* Local Bus Controller Registers */ + u8 res3[0x1000]; + spi83xx_t spi; /* Serial Peripheral Interface */ + dma83xx_t dma; /* DMA */ + pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ + u8 res4[0x80]; + ios83xx_t ios; /* Sequencer */ + pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ + u8 res5[0xa00]; + pex83xx_t pciexp[2]; /* PCI Express Controller */ + u8 res6[0xd000]; + sata83xx_t sata[4]; /* SATA Controller */ + u8 res7[0x7000]; + usb83xx_t usb[1]; /* USB DR Controller */ + tsec83xx_t tsec[2]; + u8 res8[0x8000]; + sdhc83xx_t sdhc; /* SDHC Controller */ + u8 res9[0x1000]; + security83xx_t security; + u8 res10[0xA3000]; + serdes83xx_t serdes[2]; /* SerDes Registers */ + u8 res11[0xCE00]; + rom83xx_t rom; /* On Chip ROM */ +} immap_t; + #elif defined(CONFIG_MPC8360) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 6568fe1..c9a9c83 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -178,6 +178,7 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ @@ -230,11 +231,7 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8313@0" -#define OF_SOC "soc8313@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500" +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * Serial Port @@ -326,7 +323,7 @@ */ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 376973b..564de02 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -116,6 +116,7 @@ #undef CFG_RAMBOOT #endif +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ @@ -269,12 +270,7 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8323@0" -#define OF_SOC "soc8323@e0000000" -#define OF_QE "qe@e0100000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500" +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -354,8 +350,8 @@ */ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define CFG_ENV_SECT_SIZE 0x20000 #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index c9c6d88..a48b311 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -145,6 +145,7 @@ #undef CFG_RAMBOOT #endif +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ @@ -320,12 +321,7 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8323@0" -#define OF_SOC "soc8323@e0000000" -#define OF_QE "qe@e0100000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500" +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -410,8 +406,8 @@ */ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define CFG_ENV_SECT_SIZE 0x20000 #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 92555ba..03409bb 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -341,11 +341,7 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8349@0" -#define OF_SOC "soc8349@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ @@ -456,7 +452,7 @@ */ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 54cab52..49dc0de 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -261,6 +261,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ @@ -297,12 +298,8 @@ boards, we say we have two, but don't display a message if we find only one. */ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP - -#define OF_CPU "PowerPC,8349@0" -#define OF_SOC "soc8349@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * PCI @@ -404,8 +401,8 @@ boards, we say we have two, but don't display a message if we find only one. */ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE)) #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH /* Flash is not usable now */ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 41f062c..fedb8a9 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -170,6 +170,7 @@ #undef CFG_RAMBOOT #endif +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ @@ -346,16 +347,8 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 -#undef CONFIG_OF_FLAT_TREE #define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_HAS_BD_T 1 -#define CONFIG_OF_HAS_UBOOT_ENV 1 - -#define OF_CPU "PowerPC,8360@0" -#define OF_SOC "soc8360@e0000000" -#define OF_QE "qe@e0100000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8360@e0000000/serial@4500" +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -443,8 +436,8 @@ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define CFG_ENV_SECT_SIZE 0x20000 #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h new file mode 100644 index 0000000..0958e6b --- /dev/null +++ b/include/configs/MPC837XEMDS.h @@ -0,0 +1,600 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC837X 1 /* MPC837X CPU specific */ +#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ + +/* + * System Clock Setup + */ +#ifdef CONFIG_PCISLAVE +#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ +#else +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 66000000 +#endif + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66MHz, then + * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz + */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_SVCOD_DIV_2 |\ + HRCWL_CSB_TO_CLKIN_6X1 |\ + HRCWL_CORE_TO_CSB_1_5X1) + +#ifdef CONFIG_PCISLAVE +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_AGENT |\ + HRCWH_PCI1_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LDP_CLEAR) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LDP_CLEAR) +#endif + +/* + * eTSEC Clock Config + */ +#define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ +#define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ + +/* + * System IO Config + */ +#define CFG_SICRH 0x00000000 +#define CFG_SICRL 0x00000000 + +/* + * Output Buffer Impedance + */ +#define CFG_OBIR 0x31100000 + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R + +/* + * IMMR new address + */ +#define CFG_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CFG_83XX_DDR_USES_CS0 +#define CFG_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */ + +#undef CONFIG_DDR_ECC /* support DDR ECC function */ +#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ + +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ + +#if defined(CONFIG_SPD_EEPROM) +#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ +#else +/* + * Manually set up DDR parameters + * WHITE ELECTRONIC DESGGNS - W3HG64M72EEU403PD4 SO-DIMM + * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 + */ +#define CFG_DDR_SIZE 512 /* MB */ +#define CFG_DDR_CS0_BNDS 0x0000001f +#define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ + | 0x00010000 /* ODT_WR to CSn */ \ + | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 ) + /* 0x80010202 */ +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ + | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ + | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) + /* 0x00620802 */ +#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ + | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ + | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ + | (13 << TIMING_CFG1_REFREC_SHIFT ) \ + | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) + /* 0x3935d322 */ +#define CFG_DDR_TIMING_2 ( ( 2 << TIMING_CFG2_ADD_LAT_SHIFT ) \ + | ( 6 << TIMING_CFG2_CPO_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ + | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ + | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ + | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) ) + /* 0x231088c8 */ +#define CFG_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \ + | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) + /* 0x03E00100 */ +#define CFG_DDR_SDRAM_CFG 0x43000000 +#define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ +#define CFG_DDR_MODE ( ( 0x0450 << SDRAM_MODE_ESD_SHIFT ) \ + | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) ) + /* ODT 150ohm CL=3, AL=2 on SDRAM */ +#define CFG_DDR_MODE2 0x00000000 +#endif + +/* + * Memory test + */ +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00040000 /* memtest region */ +#define CFG_MEMTEST_END 0x00140000 + +/* + * The reserved memory + */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CFG_LBC_LBCR 0x00000000 + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ + +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * BCSR on the Local Bus + */ +#define CFG_BCSR 0xF8000000 +#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ +#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ + +#define CFG_BR1_PRELIM (CFG_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */ +#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ + +/* + * NAND Flash on the Local Bus + */ +#define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ +#define CFG_BR3_PRELIM ( CFG_NAND_BASE \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V ) /* valid */ +#define CFG_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR ) + /* 0xFFFF8396 */ + +#define CFG_LBLAWBAR3_PRELIM CFG_NAND_BASE +#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI_MEM_BASE 0x80000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_MMIO_BASE 0x90000000 +#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE +#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_PHYS 0xE0300000 +#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ + +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE +#define CFG_PCI_SLV_MEM_BUS 0x00000000 +#define CFG_PCI_SLV_MEM_SIZE 0x80000000 + +#ifdef CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ +#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#endif /* CONFIG_PCI */ + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 3 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC1" + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + +#if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS +#endif + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CFG_HID2 HID2_HBE + +/* + * Cache Config + */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if defined(CONFIG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ +#endif + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CFG_SDRAM_LOWER CFG_SDRAM_BASE +#define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) + +#define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U + +#define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ +#define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +/* BCSR: cache-inhibit and guarded */ +#define CFG_IBAT3L (CFG_BCSR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT3U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U CFG_IBAT4U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) +#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else +#define CFG_IBAT6L (0) +#define CFG_IBAT6U (0) +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 00:E0:0C:00:83:79 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:83:78 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=ramfs.83xx\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc837xemds.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index e7d8a5a..9efe3c4 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -310,13 +310,9 @@ #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8349@0" -#define OF_SOC "soc8349@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ @@ -458,7 +454,7 @@ #define CONFIG_CMD_PING #if defined(CONFIG_PCI) - #define CONFG_CMD_PCI + #define CONFIG_CMD_PCI #endif #if defined(CFG_RAMBOOT) diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 4d32c6a..dba1aea 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -98,10 +98,21 @@ #define SPR_8321E_REV11 0x80660011 #define SPR_8321_REV11 0x80670011 -#define SPR_8311_REV10 0x80B30010 -#define SPR_8311E_REV10 0x80B20010 -#define SPR_8313_REV10 0x80B10010 #define SPR_8313E_REV10 0x80B00010 +#define SPR_8313_REV10 0x80B10010 +#define SPR_8311E_REV10 0x80B20010 +#define SPR_8311_REV10 0x80B30010 +#define SPR_8315E_REV10 0x80B40010 +#define SPR_8315_REV10 0x80B50010 +#define SPR_8314E_REV10 0x80B60010 +#define SPR_8314_REV10 0x80B70010 + +#define SPR_8379E_REV10 0x80C20010 +#define SPR_8379_REV10 0x80C30010 +#define SPR_8378E_REV10 0x80C40010 +#define SPR_8378_REV10 0x80C50010 +#define SPR_8377E_REV10 0x80C60010 +#define SPR_8377_REV10 0x80C70010 /* SPCR - System Priority Configuration Register */ @@ -130,8 +141,8 @@ #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ #define SPCR_TSEC2EP_SHIFT (31-31) -#elif defined(CONFIG_MPC831X) -/* SPCR bits - MPC831x specific */ +#elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) +/* SPCR bits - MPC831x and MPC837x specific */ #define SPCR_TSECDP 0x00003000 /* TSEC data priority */ #define SPCR_TSECDP_SHIFT (31-19) #define SPCR_TSECEP 0x00000C00 /* TSEC emergency priority */ @@ -213,8 +224,8 @@ #define SICRL_URT_CTPR 0x06000000 #define SICRL_IRQ_CTPR 0x00C00000 -#elif defined(CONFIG_MPC831X) -/* SICRL bits - MPC831x specific */ +#elif defined(CONFIG_MPC8313) +/* SICRL bits - MPC8313 specific */ #define SICRL_LBC 0x30000000 #define SICRL_UART 0x0C000000 #define SICRL_SPI_A 0x03000000 @@ -225,7 +236,7 @@ #define SICRL_ETSEC1_A 0x0000000C #define SICRL_ETSEC2_A 0x00000003 -/* SICRH bits - MPC831x specific */ +/* SICRH bits - MPC8313 specific */ #define SICRH_INTR_A 0x02000000 #define SICRH_INTR_B 0x00C00000 #define SICRH_IIC 0x00300000 @@ -242,6 +253,90 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001 +#elif defined(CONFIG_MPC8315) +/* SICRL bits - MPC8315 specific */ +#define SICRL_DMA_CH0 0xc0000000 +#define SICRL_DMA_SPI 0x30000000 +#define SICRL_UART 0x0c000000 +#define SICRL_IRQ4 0x02000000 +#define SICRL_IRQ5 0x01800000 +#define SICRL_IRQ6_7 0x00400000 +#define SICRL_IIC1 0x00300000 +#define SICRL_TDM 0x000c0000 +#define SICRL_TDM_SHARED 0x00030000 +#define SICRL_PCI_A 0x0000c000 +#define SICRL_ELBC_A 0x00003000 +#define SICRL_ETSEC1_A 0x000000c0 +#define SICRL_ETSEC1_B 0x00000030 +#define SICRL_ETSEC1_C 0x0000000c +#define SICRL_TSEXPOBI 0x00000001 + +/* SICRH bits - MPC8315 specific */ +#define SICRH_GPIO_0 0xc0000000 +#define SICRH_GPIO_1 0x30000000 +#define SICRH_GPIO_2 0x0c000000 +#define SICRH_GPIO_3 0x03000000 +#define SICRH_GPIO_4 0x00c00000 +#define SICRH_GPIO_5 0x00300000 +#define SICRH_GPIO_6 0x000c0000 +#define SICRH_GPIO_7 0x00030000 +#define SICRH_GPIO_8 0x0000c000 +#define SICRH_GPIO_9 0x00003000 +#define SICRH_GPIO_10 0x00000c00 +#define SICRH_GPIO_11 0x00000300 +#define SICRH_ETSEC2_A 0x000000c0 +#define SICRH_TSOBI1 0x00000002 +#define SICRH_TSOBI2 0x00000001 + +#elif defined(CONFIG_MPC837X) +/* SICRL bits - MPC837x specific */ +#define SICRL_USB_A 0xC0000000 +#define SICRL_USB_B 0x30000000 +#define SICRL_UART 0x0C000000 +#define SICRL_GPIO_A 0x02000000 +#define SICRL_GPIO_B 0x01000000 +#define SICRL_GPIO_C 0x00800000 +#define SICRL_GPIO_D 0x00400000 +#define SICRL_GPIO_E 0x00200000 +#define SICRL_GPIO_F 0x00180000 +#define SICRL_GPIO_G 0x00040000 +#define SICRL_GPIO_H 0x00020000 +#define SICRL_GPIO_I 0x00010000 +#define SICRL_GPIO_J 0x00008000 +#define SICRL_GPIO_K 0x00004000 +#define SICRL_GPIO_L 0x00003000 +#define SICRL_DMA_A 0x00000800 +#define SICRL_DMA_B 0x00000400 +#define SICRL_DMA_C 0x00000200 +#define SICRL_DMA_D 0x00000100 +#define SICRL_DMA_E 0x00000080 +#define SICRL_DMA_F 0x00000040 +#define SICRL_DMA_G 0x00000020 +#define SICRL_DMA_H 0x00000010 +#define SICRL_DMA_I 0x00000008 +#define SICRL_DMA_J 0x00000004 +#define SICRL_LDP_A 0x00000002 +#define SICRL_LDP_B 0x00000001 + +/* SICRH bits - MPC837x specific */ +#define SICRH_DDR 0x80000000 +#define SICRH_TSEC1_A 0x10000000 +#define SICRH_TSEC1_B 0x08000000 +#define SICRH_TSEC2_A 0x00400000 +#define SICRH_TSEC2_B 0x00200000 +#define SICRH_TSEC2_C 0x00100000 +#define SICRH_TSEC2_D 0x00080000 +#define SICRH_TSEC2_E 0x00040000 +#define SICRH_TMR 0x00010000 +#define SICRH_GPIO2_A 0x00008000 +#define SICRH_GPIO2_B 0x00004000 +#define SICRH_GPIO2_C 0x00002000 +#define SICRH_GPIO2_D 0x00001000 +#define SICRH_GPIO2_E 0x00000C00 +#define SICRH_GPIO2_F 0x00000300 +#define SICRH_GPIO2_G 0x000000C0 +#define SICRH_GPIO2_H 0x00000030 +#define SICRH_SPI 0x00000003 #endif /* SWCRR - System Watchdog Control Register @@ -390,6 +485,14 @@ #define HRCWL_CE_TO_PLL_1X29 0x0000001D #define HRCWL_CE_TO_PLL_1X30 0x0000001E #define HRCWL_CE_TO_PLL_1X31 0x0000001F + +#elif defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) +#define HRCWL_SVCOD 0x30000000 +#define HRCWL_SVCOD_SHIFT 28 +#define HRCWL_SVCOD_DIV_4 0x00000000 +#define HRCWL_SVCOD_DIV_8 0x10000000 +#define HRCWL_SVCOD_DIV_2 0x20000000 +#define HRCWL_SVCOD_DIV_1 0x30000000 #endif /* HRCWH - Hardware Reset Configuration Word High @@ -436,11 +539,14 @@ #if defined(CONFIG_MPC834X) #define HRCWH_ROM_LOC_PCI2 0x00200000 #endif +#if defined(CONIFG_MPC837X) +#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 +#endif #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 -#if defined(CONFIG_MPC831X) +#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 @@ -489,8 +595,13 @@ /* RSR - Reset Status Register */ +#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) +#define RSR_RSTSRC 0xF0000000 /* Reset source */ +#define RSR_RSTSRC_SHIFT 28 +#else #define RSR_RSTSRC 0xE0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 29 +#endif #define RSR_BSF 0x00010000 /* Boot seq. fail */ #define RSR_BSF_SHIFT 16 #define RSR_SWSR 0x00002000 /* software soft reset */ @@ -577,8 +688,8 @@ #define SCCR_PCICM 0x00010000 #define SCCR_PCICM_SHIFT 16 -/* SCCR bits - MPC8349 specific */ -#ifdef CONFIG_MPC834X +#if defined(CONFIG_MPC834X) +/* SCCR bits - MPC834x specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 #define SCCR_TSEC1CM_0 0x00000000 @@ -593,7 +704,19 @@ #define SCCR_TSEC2CM_2 0x20000000 #define SCCR_TSEC2CM_3 0x30000000 -#elif defined(CONFIG_MPC831X) +/* The MPH must have the same clock ratio as DR, unless its clock disabled */ +#define SCCR_USBMPHCM 0x00c00000 +#define SCCR_USBMPHCM_SHIFT 22 +#define SCCR_USBDRCM 0x00300000 +#define SCCR_USBDRCM_SHIFT 20 +#define SCCR_USBCM 0x00f00000 +#define SCCR_USBCM_SHIFT 20 +#define SCCR_USBCM_0 0x00000000 +#define SCCR_USBCM_1 0x00500000 +#define SCCR_USBCM_2 0x00A00000 +#define SCCR_USBCM_3 0x00F00000 + +#elif defined(CONFIG_MPC8313) /* TSEC1 bits are for TSEC2 as well */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 @@ -606,17 +729,109 @@ #define SCCR_TSEC2ON 0x10000000 #define SCCR_TSEC2ON_SHIFT 28 -#endif +#define SCCR_USBDRCM 0x00300000 +#define SCCR_USBDRCM_SHIFT 20 +#define SCCR_USBDRCM_0 0x00000000 +#define SCCR_USBDRCM_1 0x00100000 +#define SCCR_USBDRCM_2 0x00200000 +#define SCCR_USBDRCM_3 0x00300000 + +#elif defined(CONFIG_MPC8315) +/* SCCR bits - MPC8315 specific */ +#define SCCR_TSEC1CM 0xc0000000 +#define SCCR_TSEC1CM_SHIFT 30 +#define SCCR_TSEC1CM_0 0x00000000 +#define SCCR_TSEC1CM_1 0x40000000 +#define SCCR_TSEC1CM_2 0x80000000 +#define SCCR_TSEC1CM_3 0xC0000000 + +#define SCCR_TSEC2CM 0x30000000 +#define SCCR_TSEC2CM_SHIFT 28 +#define SCCR_TSEC2CM_0 0x00000000 +#define SCCR_TSEC2CM_1 0x10000000 +#define SCCR_TSEC2CM_2 0x20000000 +#define SCCR_TSEC2CM_3 0x30000000 -#define SCCR_USBMPHCM 0x00c00000 -#define SCCR_USBMPHCM_SHIFT 22 #define SCCR_USBDRCM 0x00300000 #define SCCR_USBDRCM_SHIFT 20 +#define SCCR_USBDRCM_0 0x00000000 +#define SCCR_USBDRCM_1 0x00100000 +#define SCCR_USBDRCM_2 0x00200000 +#define SCCR_USBDRCM_3 0x00300000 + +#define SCCR_PCIEXP1CM 0x00080000 +#define SCCR_PCIEXP2CM 0x00040000 + +#define SCCR_SATA1CM 0x0000c000 +#define SCCR_SATA1CM_SHIFT 14 +#define SCCR_SATACM 0x0000f000 +#define SCCR_SATACM_SHIFT 8 +#define SCCR_SATACM_0 0x00000000 +#define SCCR_SATACM_1 0x00005000 +#define SCCR_SATACM_2 0x0000a000 +#define SCCR_SATACM_3 0x0000f000 + +#define SCCR_TDMCM 0x000000c0 +#define SCCR_TDMCM_SHIFT 6 +#define SCCR_TDMCM_0 0x00000000 +#define SCCR_TDMCM_1 0x00000040 +#define SCCR_TDMCM_2 0x00000080 +#define SCCR_TDMCM_3 0x000000c0 + +#elif defined(CONFIG_MPC837X) +/* SCCR bits - MPC837x specific */ +#define SCCR_TSEC1CM 0xc0000000 +#define SCCR_TSEC1CM_SHIFT 30 +#define SCCR_TSEC1CM_0 0x00000000 +#define SCCR_TSEC1CM_1 0x40000000 +#define SCCR_TSEC1CM_2 0x80000000 +#define SCCR_TSEC1CM_3 0xC0000000 -#define SCCR_USBCM_0 0x00000000 -#define SCCR_USBCM_1 0x00500000 -#define SCCR_USBCM_2 0x00A00000 -#define SCCR_USBCM_3 0x00F00000 +#define SCCR_TSEC2CM 0x30000000 +#define SCCR_TSEC2CM_SHIFT 28 +#define SCCR_TSEC2CM_0 0x00000000 +#define SCCR_TSEC2CM_1 0x10000000 +#define SCCR_TSEC2CM_2 0x20000000 +#define SCCR_TSEC2CM_3 0x30000000 + +#define SCCR_SDHCCM 0x0c000000 +#define SCCR_SDHCCM_SHIFT 26 +#define SCCR_SDHCCM_0 0x00000000 +#define SCCR_SDHCCM_1 0x04000000 +#define SCCR_SDHCCM_2 0x08000000 +#define SCCR_SDHCCM_3 0x0c000000 + +#define SCCR_USBDRCM 0x00c00000 +#define SCCR_USBDRCM_SHIFT 22 +#define SCCR_USBDRCM_0 0x00000000 +#define SCCR_USBDRCM_1 0x00400000 +#define SCCR_USBDRCM_2 0x00800000 +#define SCCR_USBDRCM_3 0x00c00000 + +#define SCCR_PCIEXP1CM 0x00300000 +#define SCCR_PCIEXP1CM_SHIFT 20 +#define SCCR_PCIEXP1CM_0 0x00000000 +#define SCCR_PCIEXP1CM_1 0x00100000 +#define SCCR_PCIEXP1CM_2 0x00200000 +#define SCCR_PCIEXP1CM_3 0x00300000 + +#define SCCR_PCIEXP2CM 0x000c0000 +#define SCCR_PCIEXP2CM_SHIFT 18 +#define SCCR_PCIEXP2CM_0 0x00000000 +#define SCCR_PCIEXP2CM_1 0x00040000 +#define SCCR_PCIEXP2CM_2 0x00080000 +#define SCCR_PCIEXP2CM_3 0x000c0000 + +/* All of the four SATA controllers must have the same clock ratio */ +#define SCCR_SATA1CM 0x000000c0 +#define SCCR_SATA1CM_SHIFT 6 +#define SCCR_SATACM 0x000000ff +#define SCCR_SATACM_SHIFT 0 +#define SCCR_SATACM_0 0x00000000 +#define SCCR_SATACM_1 0x00000055 +#define SCCR_SATACM_2 0x000000aa +#define SCCR_SATACM_3 0x000000ff +#endif /* CSn_BDNS - Chip Select memory Bounds Register */ @@ -860,7 +1075,7 @@ #define BR_MS_UPMA 0x00000080 /* UPMA */ #define BR_MS_UPMB 0x000000A0 /* UPMB */ #define BR_MS_UPMC 0x000000C0 /* UPMC */ -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) +#if !defined(CONFIG_MPC834X) #define BR_ATOM 0x0000000C #define BR_ATOM_SHIFT 2 #endif @@ -869,7 +1084,7 @@ #if defined(CONFIG_MPC834X) #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) -#elif defined(CONFIG_MPC8360) +#else #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) #endif @@ -1255,7 +1470,7 @@ #define LTESR_CS 0x00080000 #define LTESR_CC 0x00000001 -/* DDR Control Driver Register +/* DDRCDR - DDR Control Driver Register */ #define DDRCDR_EN 0x40000000 #define DDRCDR_PZ 0x3C000000 @@ -214,6 +214,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_UEC_ETH2) uec_initialize(1); #endif +#if defined(CONFIG_UEC_ETH3) + uec_initialize(2); +#endif #if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC) fec_initialize(bis); |