diff options
105 files changed, 5093 insertions, 2344 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 9485070..7e66e8d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -998,6 +998,8 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org> BF548-EZKIT BF548 BF561-EZKIT BF561 + BF527-AD7160-EVAL BF527 + Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> Blackfin Team <u-boot-devel@blackfin.uclinux.org> @@ -892,6 +892,7 @@ LIST_avr32=" \ LIST_blackfin=" \ bf518f-ezbrd \ bf526-ezbrd \ + bf527-ad7160-eval \ bf527-ezkit \ bf527-ezkit-v2 \ bf533-ezkit \ @@ -2436,7 +2436,6 @@ clean: $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \ $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \ $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \ - $(obj)arch/blackfin/lib/u-boot.lds \ $(obj)u-boot.lds \ $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] @rm -f $(obj)include/bmp_logo.h diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile index 211b8d5..b7f991d 100644 --- a/arch/blackfin/cpu/Makefile +++ b/arch/blackfin/cpu/Makefile @@ -17,7 +17,10 @@ EXTRA := CEXTRA := initcode.o SEXTRA := start.o SOBJS := interrupt.o cache.o +COBJS-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount.o +COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o COBJS-y += cpu.o +COBJS-y += gpio.o COBJS-y += interrupts.o COBJS-$(CONFIG_JTAG_CONSOLE) += jtag-console.o COBJS-y += os_log.o diff --git a/arch/blackfin/cpu/bootcount.c b/arch/blackfin/cpu/bootcount.c new file mode 100644 index 0000000..6cf6dd5 --- /dev/null +++ b/arch/blackfin/cpu/bootcount.c @@ -0,0 +1,34 @@ +/* + * functions for handling bootcount support + * + * Copyright (c) 2010 Analog Devices Inc. + * + * Licensed under the 2-clause BSD. + */ + +/* This version uses one 32bit storage and combines the magic/count */ + +#include <common.h> + +/* We abuse the EVT0 MMR for bootcount storage by default */ +#ifndef CONFIG_SYS_BOOTCOUNT_ADDR +# define CONFIG_SYS_BOOTCOUNT_ADDR EVT0 +#endif + +#define MAGIC_MASK 0xffff0000 +#define COUNT_MASK 0x0000ffff + +void bootcount_store(ulong cnt) +{ + ulong magic = (BOOTCOUNT_MAGIC & MAGIC_MASK) | (cnt & COUNT_MASK); + bfin_write32(CONFIG_SYS_BOOTCOUNT_ADDR, magic); +} + +ulong bootcount_load(void) +{ + ulong magic = bfin_read32(CONFIG_SYS_BOOTCOUNT_ADDR); + if ((magic & MAGIC_MASK) == (BOOTCOUNT_MAGIC & MAGIC_MASK)) + return magic & COUNT_MASK; + else + return 0; +} diff --git a/arch/blackfin/cpu/cmd_gpio.c b/arch/blackfin/cpu/cmd_gpio.c new file mode 100644 index 0000000..9e505b6 --- /dev/null +++ b/arch/blackfin/cpu/cmd_gpio.c @@ -0,0 +1,120 @@ +/* + * Control GPIO pins on the fly + * + * Copyright (c) 2008-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <command.h> + +#include <asm/blackfin.h> +#include <asm/gpio.h> + +enum { + GPIO_INPUT, + GPIO_SET, + GPIO_CLEAR, + GPIO_TOGGLE, +}; + +int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc == 2 && !strcmp(argv[1], "status")) { + bfin_gpio_labels(); + return 0; + } + + if (argc != 3) { + show_usage: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* parse the behavior */ + ulong sub_cmd; + switch (argv[1][0]) { + case 'i': sub_cmd = GPIO_INPUT; break; + case 's': sub_cmd = GPIO_SET; break; + case 'c': sub_cmd = GPIO_CLEAR; break; + case 't': sub_cmd = GPIO_TOGGLE; break; + default: goto show_usage; + } + + /* parse the pin with format: [p][port]<#> */ + const char *str_pin = argv[2]; + + /* grab the [p]<port> portion */ + ulong port_base; + if (*str_pin == 'p') ++str_pin; + switch (*str_pin) { +#ifdef GPIO_PA0 + case 'a': port_base = GPIO_PA0; break; +#endif +#ifdef GPIO_PB0 + case 'b': port_base = GPIO_PB0; break; +#endif +#ifdef GPIO_PC0 + case 'c': port_base = GPIO_PC0; break; +#endif +#ifdef GPIO_PD0 + case 'd': port_base = GPIO_PD0; break; +#endif +#ifdef GPIO_PE0 + case 'e': port_base = GPIO_PE0; break; +#endif +#ifdef GPIO_PF0 + case 'f': port_base = GPIO_PF0; break; +#endif +#ifdef GPIO_PG0 + case 'g': port_base = GPIO_PG0; break; +#endif +#ifdef GPIO_PH0 + case 'h': port_base = GPIO_PH0; break; +#endif +#ifdef GPIO_PI0 + case 'i': port_base = GPIO_PI0; break; +#endif +#ifdef GPIO_PJ + case 'j': port_base = GPIO_PJ0; break; +#endif + default: goto show_usage; + } + + /* grab the <#> portion */ + ulong pin = simple_strtoul(str_pin + 1, NULL, 10); + if (pin > 15) + goto show_usage; + + /* grab the pin before we tweak it */ + ulong gpio = port_base + pin; + gpio_request(gpio, "cmd_gpio"); + + /* finally, let's do it: set direction and exec command */ + if (sub_cmd == GPIO_INPUT) { + gpio_direction_input(gpio); + printf("gpio: pin %lu on port %c set to input\n", pin, *str_pin); + return 0; + } + + ulong value; + switch (sub_cmd) { + case GPIO_SET: value = 1; break; + case GPIO_CLEAR: value = 0; break; + case GPIO_TOGGLE: value = !gpio_get_value(gpio); break; + default: goto show_usage; + } + gpio_direction_output(gpio, value); + printf("gpio: pin %lu on port %c (gpio %lu) value is %lu\n", + pin, *str_pin, gpio, value); + + gpio_free(gpio); + + return 0; +} + +U_BOOT_CMD(gpio, 3, 0, do_gpio, + "set/clear/toggle gpio output pins", + "<set|clear|toggle> <port><pin>\n" + " - set/clear/toggle the specified pin (e.g. PF10)"); diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c index 2c8fd86..18dbdf7 100644 --- a/arch/blackfin/cpu/cpu.c +++ b/arch/blackfin/cpu/cpu.c @@ -91,7 +91,9 @@ int irq_init(void) #else bfin_write_SIC_IMASK(0); #endif - bfin_write_EVT2(evt_default); /* NMI */ + /* Set up a dummy NMI handler if needed. */ + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219) + bfin_write_EVT2(evt_nmi); /* NMI */ bfin_write_EVT5(evt_default); /* hardware error */ bfin_write_EVT6(evt_default); /* core timer */ bfin_write_EVT7(evt_default); diff --git a/arch/blackfin/cpu/cpu.h b/arch/blackfin/cpu/cpu.h index 0a13c28..ba85e0b 100644 --- a/arch/blackfin/cpu/cpu.h +++ b/arch/blackfin/cpu/cpu.h @@ -29,10 +29,12 @@ void board_reset(void) __attribute__((__weak__)); void bfin_reset_or_hang(void) __attribute__((__noreturn__)); +void bfin_dump(struct pt_regs *reg); void bfin_panic(struct pt_regs *reg); void dump(struct pt_regs *regs); asmlinkage void trap(void); +asmlinkage void evt_nmi(void); asmlinkage void evt_default(void); #endif diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c new file mode 100644 index 0000000..488ca11 --- /dev/null +++ b/arch/blackfin/cpu/gpio.c @@ -0,0 +1,854 @@ +/* + * GPIO Abstraction Layer + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/portmux.h> + +#if ANOMALY_05000311 || ANOMALY_05000323 +enum { + AWA_data = SYSCR, + AWA_data_clear = SYSCR, + AWA_data_set = SYSCR, + AWA_toggle = SYSCR, + AWA_maska = UART_SCR, + AWA_maska_clear = UART_SCR, + AWA_maska_set = UART_SCR, + AWA_maska_toggle = UART_SCR, + AWA_maskb = UART_GCTL, + AWA_maskb_clear = UART_GCTL, + AWA_maskb_set = UART_GCTL, + AWA_maskb_toggle = UART_GCTL, + AWA_dir = SPORT1_STAT, + AWA_polar = SPORT1_STAT, + AWA_edge = SPORT1_STAT, + AWA_both = SPORT1_STAT, +#if ANOMALY_05000311 + AWA_inen = TIMER_ENABLE, +#elif ANOMALY_05000323 + AWA_inen = DMA1_1_CONFIG, +#endif +}; + /* Anomaly Workaround */ +#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name) +#else +#define AWA_DUMMY_READ(...) do { } while (0) +#endif + +static struct gpio_port_t * const gpio_array[] = { +#if defined(BF533_FAMILY) + (struct gpio_port_t *) FIO_FLAG_D, +#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) \ + || defined(BF538_FAMILY) + (struct gpio_port_t *) PORTFIO, +# if !defined(BF538_FAMILY) + (struct gpio_port_t *) PORTGIO, + (struct gpio_port_t *) PORTHIO, +# endif +#elif defined(BF561_FAMILY) + (struct gpio_port_t *) FIO0_FLAG_D, + (struct gpio_port_t *) FIO1_FLAG_D, + (struct gpio_port_t *) FIO2_FLAG_D, +#elif defined(CONFIG_BF54x) + (struct gpio_port_t *)PORTA_FER, + (struct gpio_port_t *)PORTB_FER, + (struct gpio_port_t *)PORTC_FER, + (struct gpio_port_t *)PORTD_FER, + (struct gpio_port_t *)PORTE_FER, + (struct gpio_port_t *)PORTF_FER, + (struct gpio_port_t *)PORTG_FER, + (struct gpio_port_t *)PORTH_FER, + (struct gpio_port_t *)PORTI_FER, + (struct gpio_port_t *)PORTJ_FER, +#else +# error no gpio arrays defined +#endif +}; + +#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) +static unsigned short * const port_fer[] = { + (unsigned short *) PORTF_FER, + (unsigned short *) PORTG_FER, + (unsigned short *) PORTH_FER, +}; + +# if !defined(BF537_FAMILY) +static unsigned short * const port_mux[] = { + (unsigned short *) PORTF_MUX, + (unsigned short *) PORTG_MUX, + (unsigned short *) PORTH_MUX, +}; + +static const +u8 pmux_offset[][16] = { +# if defined(CONFIG_BF52x) + { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */ + { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */ + { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */ +# elif defined(CONFIG_BF51x) + { 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */ + { 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */ + { 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */ +# endif +}; +# endif + +#elif defined(BF538_FAMILY) +static unsigned short * const port_fer[] = { + (unsigned short *) PORTCIO_FER, + (unsigned short *) PORTDIO_FER, + (unsigned short *) PORTEIO_FER, +}; +#endif + +#ifdef CONFIG_BFIN_GPIO_TRACK +#define RESOURCE_LABEL_SIZE 16 + +static struct str_ident { + char name[RESOURCE_LABEL_SIZE]; +} str_ident[MAX_RESOURCES]; + +static void gpio_error(unsigned gpio) +{ + printf("bfin-gpio: GPIO %d wasn't requested!\n", gpio); +} + +static void set_label(unsigned short ident, const char *label) +{ + if (label) { + strncpy(str_ident[ident].name, label, + RESOURCE_LABEL_SIZE); + str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0; + } +} + +static char *get_label(unsigned short ident) +{ + return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN"); +} + +static int cmp_label(unsigned short ident, const char *label) +{ + if (label == NULL) + printf("bfin-gpio: please provide none-null label\n"); + + if (label) + return strcmp(str_ident[ident].name, label); + else + return -EINVAL; +} + +#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)] +#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i)) +#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i)) +#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i)) +#define DECLARE_RESERVED_MAP(m, c) static unsigned short reserved_##m##_map[c] +#else +#define is_reserved(m, i, e) (!(e)) +#define reserve(m, i) +#define unreserve(m, i) +#define DECLARE_RESERVED_MAP(m, c) +#define gpio_error(gpio) +#define set_label(...) +#define get_label(...) "" +#define cmp_label(...) 1 +#endif + +DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM); +DECLARE_RESERVED_MAP(peri, gpio_bank(MAX_RESOURCES)); + +inline int check_gpio(unsigned gpio) +{ +#if defined(CONFIG_BF54x) + if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 + || gpio == GPIO_PH14 || gpio == GPIO_PH15 + || gpio == GPIO_PJ14 || gpio == GPIO_PJ15) + return -EINVAL; +#endif + if (gpio >= MAX_BLACKFIN_GPIOS) + return -EINVAL; + return 0; +} + +static void port_setup(unsigned gpio, unsigned short usage) +{ +#if defined(BF538_FAMILY) + /* + * BF538/9 Port C,D and E are special. + * Inverted PORT_FER polarity on CDE and no PORF_FER on F + * Regular PORT F GPIOs are handled here, CDE are exclusively + * managed by GPIOLIB + */ + + if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES) + return; + + gpio -= MAX_BLACKFIN_GPIOS; + + if (usage == GPIO_USAGE) + *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); + else + *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio); + SSYNC(); + return; +#endif + + if (check_gpio(gpio)) + return; + +#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) + if (usage == GPIO_USAGE) + *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio); + else + *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); + SSYNC(); +#elif defined(CONFIG_BF54x) + if (usage == GPIO_USAGE) + gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio); + else + gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio); + SSYNC(); +#endif +} + +#ifdef BF537_FAMILY +static struct { + unsigned short res; + unsigned short offset; +} port_mux_lut[] = { + {.res = P_PPI0_D13, .offset = 11}, + {.res = P_PPI0_D14, .offset = 11}, + {.res = P_PPI0_D15, .offset = 11}, + {.res = P_SPORT1_TFS, .offset = 11}, + {.res = P_SPORT1_TSCLK, .offset = 11}, + {.res = P_SPORT1_DTPRI, .offset = 11}, + {.res = P_PPI0_D10, .offset = 10}, + {.res = P_PPI0_D11, .offset = 10}, + {.res = P_PPI0_D12, .offset = 10}, + {.res = P_SPORT1_RSCLK, .offset = 10}, + {.res = P_SPORT1_RFS, .offset = 10}, + {.res = P_SPORT1_DRPRI, .offset = 10}, + {.res = P_PPI0_D8, .offset = 9}, + {.res = P_PPI0_D9, .offset = 9}, + {.res = P_SPORT1_DRSEC, .offset = 9}, + {.res = P_SPORT1_DTSEC, .offset = 9}, + {.res = P_TMR2, .offset = 8}, + {.res = P_PPI0_FS3, .offset = 8}, + {.res = P_TMR3, .offset = 7}, + {.res = P_SPI0_SSEL4, .offset = 7}, + {.res = P_TMR4, .offset = 6}, + {.res = P_SPI0_SSEL5, .offset = 6}, + {.res = P_TMR5, .offset = 5}, + {.res = P_SPI0_SSEL6, .offset = 5}, + {.res = P_UART1_RX, .offset = 4}, + {.res = P_UART1_TX, .offset = 4}, + {.res = P_TMR6, .offset = 4}, + {.res = P_TMR7, .offset = 4}, + {.res = P_UART0_RX, .offset = 3}, + {.res = P_UART0_TX, .offset = 3}, + {.res = P_DMAR0, .offset = 3}, + {.res = P_DMAR1, .offset = 3}, + {.res = P_SPORT0_DTSEC, .offset = 1}, + {.res = P_SPORT0_DRSEC, .offset = 1}, + {.res = P_CAN0_RX, .offset = 1}, + {.res = P_CAN0_TX, .offset = 1}, + {.res = P_SPI0_SSEL7, .offset = 1}, + {.res = P_SPORT0_TFS, .offset = 0}, + {.res = P_SPORT0_DTPRI, .offset = 0}, + {.res = P_SPI0_SSEL2, .offset = 0}, + {.res = P_SPI0_SSEL3, .offset = 0}, +}; + +static void portmux_setup(unsigned short per) +{ + u16 y, offset, muxreg; + u16 function = P_FUNCT2MUX(per); + + for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) { + if (port_mux_lut[y].res == per) { + + /* SET PORTMUX REG */ + + offset = port_mux_lut[y].offset; + muxreg = bfin_read_PORT_MUX(); + + if (offset != 1) + muxreg &= ~(1 << offset); + else + muxreg &= ~(3 << 1); + + muxreg |= (function << offset); + bfin_write_PORT_MUX(muxreg); + } + } +} +#elif defined(CONFIG_BF54x) +inline void portmux_setup(unsigned short per) +{ + u32 pmux; + u16 ident = P_IDENT(per); + u16 function = P_FUNCT2MUX(per); + + pmux = gpio_array[gpio_bank(ident)]->port_mux; + + pmux &= ~(0x3 << (2 * gpio_sub_n(ident))); + pmux |= (function & 0x3) << (2 * gpio_sub_n(ident)); + + gpio_array[gpio_bank(ident)]->port_mux = pmux; +} + +inline u16 get_portmux(unsigned short per) +{ + u32 pmux; + u16 ident = P_IDENT(per); + + pmux = gpio_array[gpio_bank(ident)]->port_mux; + + return (pmux >> (2 * gpio_sub_n(ident)) & 0x3); +} +#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) +inline void portmux_setup(unsigned short per) +{ + u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per); + u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)]; + + pmux = *port_mux[gpio_bank(ident)]; + pmux &= ~(3 << offset); + pmux |= (function & 3) << offset; + *port_mux[gpio_bank(ident)] = pmux; + SSYNC(); +} +#else +# define portmux_setup(...) do { } while (0) +#endif + +#ifndef CONFIG_BF54x +/*********************************************************** +* +* FUNCTIONS: Blackfin General Purpose Ports Access Functions +* +* INPUTS/OUTPUTS: +* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS +* +* +* DESCRIPTION: These functions abstract direct register access +* to Blackfin processor General Purpose +* Ports Regsiters +* +* CAUTION: These functions do not belong to the GPIO Driver API +************************************************************* +* MODIFICATION HISTORY : +**************************************************************/ + +/* Set a specific bit */ + +#define SET_GPIO(name) \ +void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ +{ \ + unsigned long flags; \ + local_irq_save(flags); \ + if (arg) \ + gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \ + else \ + gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \ + AWA_DUMMY_READ(name); \ + local_irq_restore(flags); \ +} + +SET_GPIO(dir) /* set_gpio_dir() */ +SET_GPIO(inen) /* set_gpio_inen() */ +SET_GPIO(polar) /* set_gpio_polar() */ +SET_GPIO(edge) /* set_gpio_edge() */ +SET_GPIO(both) /* set_gpio_both() */ + + +#define SET_GPIO_SC(name) \ +void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ +{ \ + unsigned long flags; \ + if (ANOMALY_05000311 || ANOMALY_05000323) \ + local_irq_save(flags); \ + if (arg) \ + gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \ + else \ + gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \ + if (ANOMALY_05000311 || ANOMALY_05000323) { \ + AWA_DUMMY_READ(name); \ + local_irq_restore(flags); \ + } \ +} + +SET_GPIO_SC(maska) +SET_GPIO_SC(maskb) +SET_GPIO_SC(data) + +void set_gpio_toggle(unsigned gpio) +{ + unsigned long flags; + if (ANOMALY_05000311 || ANOMALY_05000323) + local_irq_save(flags); + gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio); + if (ANOMALY_05000311 || ANOMALY_05000323) { + AWA_DUMMY_READ(toggle); + local_irq_restore(flags); + } +} + +/* Set current PORT date (16-bit word) */ + +#define SET_GPIO_P(name) \ +void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \ +{ \ + unsigned long flags; \ + if (ANOMALY_05000311 || ANOMALY_05000323) \ + local_irq_save(flags); \ + gpio_array[gpio_bank(gpio)]->name = arg; \ + if (ANOMALY_05000311 || ANOMALY_05000323) { \ + AWA_DUMMY_READ(name); \ + local_irq_restore(flags); \ + } \ +} + +SET_GPIO_P(data) +SET_GPIO_P(dir) +SET_GPIO_P(inen) +SET_GPIO_P(polar) +SET_GPIO_P(edge) +SET_GPIO_P(both) +SET_GPIO_P(maska) +SET_GPIO_P(maskb) + +/* Get a specific bit */ +#define GET_GPIO(name) \ +unsigned short get_gpio_ ## name(unsigned gpio) \ +{ \ + unsigned long flags; \ + unsigned short ret; \ + if (ANOMALY_05000311 || ANOMALY_05000323) \ + local_irq_save(flags); \ + ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \ + if (ANOMALY_05000311 || ANOMALY_05000323) { \ + AWA_DUMMY_READ(name); \ + local_irq_restore(flags); \ + } \ + return ret; \ +} + +GET_GPIO(data) +GET_GPIO(dir) +GET_GPIO(inen) +GET_GPIO(polar) +GET_GPIO(edge) +GET_GPIO(both) +GET_GPIO(maska) +GET_GPIO(maskb) + +/* Get current PORT date (16-bit word) */ + +#define GET_GPIO_P(name) \ +unsigned short get_gpiop_ ## name(unsigned gpio) \ +{ \ + unsigned long flags; \ + unsigned short ret; \ + if (ANOMALY_05000311 || ANOMALY_05000323) \ + local_irq_save(flags); \ + ret = (gpio_array[gpio_bank(gpio)]->name); \ + if (ANOMALY_05000311 || ANOMALY_05000323) { \ + AWA_DUMMY_READ(name); \ + local_irq_restore(flags); \ + } \ + return ret; \ +} + +GET_GPIO_P(data) +GET_GPIO_P(dir) +GET_GPIO_P(inen) +GET_GPIO_P(polar) +GET_GPIO_P(edge) +GET_GPIO_P(both) +GET_GPIO_P(maska) +GET_GPIO_P(maskb) + +#else /* CONFIG_BF54x */ + +unsigned short get_gpio_dir(unsigned gpio) +{ + return (0x01 & (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio))); +} + +#endif /* CONFIG_BF54x */ + +/*********************************************************** +* +* FUNCTIONS: Blackfin Peripheral Resource Allocation +* and PortMux Setup +* +* INPUTS/OUTPUTS: +* per Peripheral Identifier +* label String +* +* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API +* +* CAUTION: +************************************************************* +* MODIFICATION HISTORY : +**************************************************************/ + +int peripheral_request(unsigned short per, const char *label) +{ + unsigned short ident = P_IDENT(per); + + /* + * Don't cares are pins with only one dedicated function + */ + + if (per & P_DONTCARE) + return 0; + + if (!(per & P_DEFINED)) + return -ENODEV; + + BUG_ON(ident >= MAX_RESOURCES); + + /* If a pin can be muxed as either GPIO or peripheral, make + * sure it is not already a GPIO pin when we request it. + */ + if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) { + printf("%s: Peripheral %d is already reserved as GPIO by %s !\n", + __func__, ident, get_label(ident)); + return -EBUSY; + } + + if (unlikely(is_reserved(peri, ident, 1))) { + + /* + * Pin functions like AMC address strobes my + * be requested and used by several drivers + */ + +#ifdef CONFIG_BF54x + if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) { +#else + if (!(per & P_MAYSHARE)) { +#endif + /* + * Allow that the identical pin function can + * be requested from the same driver twice + */ + + if (cmp_label(ident, label) == 0) + goto anyway; + + printf("%s: Peripheral %d function %d is already reserved by %s !\n", + __func__, ident, P_FUNCT2MUX(per), get_label(ident)); + return -EBUSY; + } + } + + anyway: + reserve(peri, ident); + + portmux_setup(per); + port_setup(ident, PERIPHERAL_USAGE); + + set_label(ident, label); + + return 0; +} + +int peripheral_request_list(const unsigned short per[], const char *label) +{ + u16 cnt; + int ret; + + for (cnt = 0; per[cnt] != 0; cnt++) { + + ret = peripheral_request(per[cnt], label); + + if (ret < 0) { + for ( ; cnt > 0; cnt--) + peripheral_free(per[cnt - 1]); + + return ret; + } + } + + return 0; +} + +void peripheral_free(unsigned short per) +{ + unsigned short ident = P_IDENT(per); + + if (per & P_DONTCARE) + return; + + if (!(per & P_DEFINED)) + return; + + if (unlikely(!is_reserved(peri, ident, 0))) + return; + + if (!(per & P_MAYSHARE)) + port_setup(ident, GPIO_USAGE); + + unreserve(peri, ident); + + set_label(ident, "free"); +} + +void peripheral_free_list(const unsigned short per[]) +{ + u16 cnt; + for (cnt = 0; per[cnt] != 0; cnt++) + peripheral_free(per[cnt]); +} + +/*********************************************************** +* +* FUNCTIONS: Blackfin GPIO Driver +* +* INPUTS/OUTPUTS: +* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS +* label String +* +* DESCRIPTION: Blackfin GPIO Driver API +* +* CAUTION: +************************************************************* +* MODIFICATION HISTORY : +**************************************************************/ + +int bfin_gpio_request(unsigned gpio, const char *label) +{ + if (check_gpio(gpio) < 0) + return -EINVAL; + + /* + * Allow that the identical GPIO can + * be requested from the same driver twice + * Do nothing and return - + */ + + if (cmp_label(gpio, label) == 0) + return 0; + + if (unlikely(is_reserved(gpio, gpio, 1))) { + printf("bfin-gpio: GPIO %d is already reserved by %s !\n", + gpio, get_label(gpio)); + return -EBUSY; + } + if (unlikely(is_reserved(peri, gpio, 1))) { + printf("bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", + gpio, get_label(gpio)); + return -EBUSY; + } +#ifndef CONFIG_BF54x + else { /* Reset POLAR setting when acquiring a gpio for the first time */ + set_gpio_polar(gpio, 0); + } +#endif + + reserve(gpio, gpio); + set_label(gpio, label); + + port_setup(gpio, GPIO_USAGE); + + return 0; +} + +void bfin_gpio_free(unsigned gpio) +{ + if (check_gpio(gpio) < 0) + return; + + if (unlikely(!is_reserved(gpio, gpio, 0))) { + gpio_error(gpio); + return; + } + + unreserve(gpio, gpio); + + set_label(gpio, "free"); +} + +#ifdef BFIN_SPECIAL_GPIO_BANKS +DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES)); + +int bfin_special_gpio_request(unsigned gpio, const char *label) +{ + /* + * Allow that the identical GPIO can + * be requested from the same driver twice + * Do nothing and return - + */ + + if (cmp_label(gpio, label) == 0) + return 0; + + if (unlikely(is_reserved(special_gpio, gpio, 1))) { + printf("bfin-gpio: GPIO %d is already reserved by %s !\n", + gpio, get_label(gpio)); + return -EBUSY; + } + if (unlikely(is_reserved(peri, gpio, 1))) { + printf("bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", + gpio, get_label(gpio)); + + return -EBUSY; + } + + reserve(special_gpio, gpio); + reserve(peri, gpio); + + set_label(gpio, label); + port_setup(gpio, GPIO_USAGE); + + return 0; +} + +void bfin_special_gpio_free(unsigned gpio) +{ + if (unlikely(!is_reserved(special_gpio, gpio, 0))) { + gpio_error(gpio); + return; + } + + reserve(special_gpio, gpio); + reserve(peri, gpio); + set_label(gpio, "free"); +} +#endif + +static inline void __bfin_gpio_direction_input(unsigned gpio) +{ +#ifdef CONFIG_BF54x + gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio); +#else + gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio); +#endif + gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio); +} + +int bfin_gpio_direction_input(unsigned gpio) +{ + unsigned long flags; + + if (!is_reserved(gpio, gpio, 0)) { + gpio_error(gpio); + return -EINVAL; + } + + local_irq_save(flags); + __bfin_gpio_direction_input(gpio); + AWA_DUMMY_READ(inen); + local_irq_restore(flags); + + return 0; +} + +void bfin_gpio_toggle_value(unsigned gpio) +{ +#ifdef CONFIG_BF54x + gpio_set_value(gpio, !gpio_get_value(gpio)); +#else + gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio); +#endif +} + +void bfin_gpio_set_value(unsigned gpio, int arg) +{ + if (arg) + gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio); + else + gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio); +} + +int bfin_gpio_direction_output(unsigned gpio, int value) +{ + unsigned long flags; + + if (!is_reserved(gpio, gpio, 0)) { + gpio_error(gpio); + return -EINVAL; + } + + local_irq_save(flags); + + gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); + gpio_set_value(gpio, value); +#ifdef CONFIG_BF54x + gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio); +#else + gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio); +#endif + + AWA_DUMMY_READ(dir); + local_irq_restore(flags); + + return 0; +} + +int bfin_gpio_get_value(unsigned gpio) +{ +#ifdef CONFIG_BF54x + return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio))); +#else + unsigned long flags; + + if (unlikely(get_gpio_edge(gpio))) { + int ret; + local_irq_save(flags); + set_gpio_edge(gpio, 0); + ret = get_gpio_data(gpio); + set_gpio_edge(gpio, 1); + local_irq_restore(flags); + return ret; + } else + return get_gpio_data(gpio); +#endif +} + +/* If we are booting from SPI and our board lacks a strong enough pull up, + * the core can reset and execute the bootrom faster than the resistor can + * pull the signal logically high. To work around this (common) error in + * board design, we explicitly set the pin back to GPIO mode, force /CS + * high, and wait for the electrons to do their thing. + * + * This function only makes sense to be called from reset code, but it + * lives here as we need to force all the GPIO states w/out going through + * BUG() checks and such. + */ +void bfin_reset_boot_spi_cs(unsigned short pin) +{ + unsigned short gpio = P_IDENT(pin); + port_setup(gpio, GPIO_USAGE); + gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio); + AWA_DUMMY_READ(data_set); + udelay(1); +} + +#ifdef CONFIG_BFIN_GPIO_TRACK +void bfin_gpio_labels(void) +{ + int c, gpio; + + for (c = 0; c < MAX_RESOURCES; c++) { + gpio = is_reserved(gpio, c, 1); + if (!check_gpio(c) && gpio) + printf("GPIO_%d:\t%s\tGPIO %s\n", c, + get_label(c), + get_gpio_dir(c) ? "OUTPUT" : "INPUT"); + else if (is_reserved(peri, c, 1)) + printf("GPIO_%d:\t%s\tPeripheral\n", c, get_label(c)); + else + continue; + } +} +#endif diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 5f80ad6..007f5ce 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -101,6 +101,28 @@ static inline void serial_putc(char c) continue; } +__attribute__((always_inline)) static inline void +program_nmi_handler(void) +{ + u32 tmp1, tmp2; + + /* Older bootroms don't create a dummy NMI handler, + * so make one ourselves ASAP in case it fires. + */ + if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219) + return; + + asm volatile ( + "%0 = RETS;" /* Save current RETS */ + "CALL 1f;" /* Figure out current PC */ + "RTN;" /* The simple NMI handler */ + "1:" + "%1 = RETS;" /* Load addr of NMI handler */ + "RETS = %0;" /* Restore RETS */ + "[%2] = %1;" /* Write NMI handler */ + : "=r"(tmp1), "=r"(tmp2) : "ab"(EVT2) + ); +} /* Max SCLK can be 133MHz ... dividing that by (2*4) gives * us a freq of 16MHz for SPI which should generally be @@ -640,6 +662,9 @@ void initcode(ADI_BOOT_DATA *bs) { ADI_BOOT_DATA bootstruct_scratch; + /* Setup NMI handler before anything else */ + program_nmi_handler(); + serial_init(); serial_putc('A'); @@ -675,7 +700,12 @@ void initcode(ADI_BOOT_DATA *bs) #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1 serial_putc('I'); - /* tell the bootrom where our entry point is */ + /* Tell the bootrom where our entry point is so that it knows + * where to jump to when finishing processing the LDR. This + * allows us to avoid small jump blocks in the LDR, and also + * works around anomaly 05000389 (init address in external + * memory causes bootrom to trigger external addressing IVHW). + */ if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE); #endif diff --git a/arch/blackfin/cpu/interrupt.S b/arch/blackfin/cpu/interrupt.S index 69bba3f..0e5e59e 100644 --- a/arch/blackfin/cpu/interrupt.S +++ b/arch/blackfin/cpu/interrupt.S @@ -150,3 +150,8 @@ ENTRY(_evt_default) RESTORE_ALL_SYS rti; ENDPROC(_evt_default) + +/* NMI handler */ +ENTRY(_evt_nmi) + rtn; +ENDPROC(_evt_nmi) diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h index 5f9be86..f9e311f 100644 --- a/arch/blackfin/cpu/serial.h +++ b/arch/blackfin/cpu/serial.h @@ -26,6 +26,8 @@ #ifndef __ASSEMBLY__ +#include <asm/portmux.h> + #define LOB(x) ((x) & 0xFF) #define HIB(x) (((x) >> 8) & 0xFF) @@ -103,6 +105,23 @@ struct bfin_mmr_serial { __attribute__((always_inline)) static inline void serial_do_portmux(void) { + if (!BFIN_DEBUG_EARLY_SERIAL) { + const unsigned short pins[] = { +#if CONFIG_UART_CONSOLE == 0 + P_UART0_TX, P_UART0_RX, +#elif CONFIG_UART_CONSOLE == 1 + P_UART1_TX, P_UART1_RX, +#elif CONFIG_UART_CONSOLE == 2 + P_UART2_TX, P_UART2_RX, +#elif CONFIG_UART_CONSOLE == 3 + P_UART3_TX, P_UART3_RX, +#endif + 0, + }; + peripheral_request_list(pins, "bfin-uart"); + return; + } + #if defined(__ADSPBF51x__) # define DO_MUX(port, mux_tx, mux_rx, tx, rx) \ bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \ diff --git a/arch/blackfin/cpu/traps.c b/arch/blackfin/cpu/traps.c index caaea94..09388aa 100644 --- a/arch/blackfin/cpu/traps.c +++ b/arch/blackfin/cpu/traps.c @@ -29,14 +29,26 @@ #include <asm/deferred.h> #include "cpu.h" +#ifdef CONFIG_DEBUG_DUMP +# define ENABLE_DUMP 1 +#else +# define ENABLE_DUMP 0 +#endif + #define trace_buffer_save(x) \ do { \ + if (!ENABLE_DUMP) \ + break; \ (x) = bfin_read_TBUFCTL(); \ bfin_write_TBUFCTL((x) & ~TBUFEN); \ } while (0) #define trace_buffer_restore(x) \ - bfin_write_TBUFCTL((x)) + do { \ + if (!ENABLE_DUMP) \ + break; \ + bfin_write_TBUFCTL((x)); \ + } while (0); /* The purpose of this map is to provide a mapping of address<->cplb settings * rather than an exact map of what is actually addressable on the part. This @@ -82,8 +94,16 @@ int trap_c(struct pt_regs *regs, uint32_t level) { uint32_t ret = 0; uint32_t trapnr = (regs->seqstat & EXCAUSE); + unsigned long tflags; bool data = false; + /* + * Keep the trace buffer so that a miss here points people + * to the right place (their code). Crashes here rarely + * happen. If they do, only the Blackfin maintainer cares. + */ + trace_buffer_save(tflags); + switch (trapnr) { /* 0x26 - Data CPLB Miss */ case VEC_CPLB_M: @@ -97,7 +117,7 @@ int trap_c(struct pt_regs *regs, uint32_t level) */ if (last_cplb_fault_retx != regs->retx) { last_cplb_fault_retx = regs->retx; - return ret; + break; } } @@ -110,7 +130,6 @@ int trap_c(struct pt_regs *regs, uint32_t level) uint32_t new_cplb_addr = 0, new_cplb_data = 0; static size_t last_evicted; size_t i; - unsigned long tflags; #ifdef CONFIG_EXCEPTION_DEFER /* This should never happen */ @@ -118,13 +137,6 @@ int trap_c(struct pt_regs *regs, uint32_t level) bfin_panic(regs); #endif - /* - * Keep the trace buffer so that a miss here points people - * to the right place (their code). Crashes here rarely - * happen. If they do, only the Blackfin maintainer cares. - */ - trace_buffer_save(tflags); - new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1); for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) { @@ -180,7 +192,6 @@ int trap_c(struct pt_regs *regs, uint32_t level) for (i = 0; i < 16; ++i) debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++); - trace_buffer_restore(tflags); break; } #ifdef CONFIG_CMD_KGDB @@ -208,23 +219,21 @@ int trap_c(struct pt_regs *regs, uint32_t level) #ifdef CONFIG_CMD_KGDB if (level == 3) { /* We need to handle this at EVT5, so try again */ + bfin_dump(regs); ret = 1; break; } if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return 0; + break; #endif bfin_panic(regs); } + + trace_buffer_restore(tflags); + return ret; } -#ifdef CONFIG_DEBUG_DUMP -# define ENABLE_DUMP 1 -#else -# define ENABLE_DUMP 0 -#endif - #ifndef CONFIG_KALLSYMS const char *symbol_lookup(unsigned long addr, unsigned long *caddr) { @@ -364,17 +373,14 @@ void dump(struct pt_regs *fp) printf("\n"); } -void dump_bfin_trace_buffer(void) +static void _dump_bfin_trace_buffer(void) { char buf[150]; - unsigned long tflags; int i = 0; if (!ENABLE_DUMP) return; - trace_buffer_save(tflags); - printf("Hardware Trace:\n"); if (bfin_read_TBUFSTAT() & TBUFCNT) { @@ -385,16 +391,21 @@ void dump_bfin_trace_buffer(void) printf(" Source : %s\n", buf); } } +} +void dump_bfin_trace_buffer(void) +{ + unsigned long tflags; + trace_buffer_save(tflags); + _dump_bfin_trace_buffer(); trace_buffer_restore(tflags); } -void bfin_panic(struct pt_regs *regs) +void bfin_dump(struct pt_regs *regs) { - if (ENABLE_DUMP) { - unsigned long tflags; - trace_buffer_save(tflags); - } + unsigned long tflags; + + trace_buffer_save(tflags); puts( "\n" @@ -404,7 +415,16 @@ void bfin_panic(struct pt_regs *regs) "\n" ); dump(regs); - dump_bfin_trace_buffer(); + _dump_bfin_trace_buffer(); puts("\n"); + + trace_buffer_restore(tflags); +} + +void bfin_panic(struct pt_regs *regs) +{ + unsigned long tflags; + trace_buffer_save(tflags); + bfin_dump(regs); bfin_reset_or_hang(); } diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h index 3fd34b3..48f793a 100644 --- a/arch/blackfin/include/asm/blackfin_local.h +++ b/arch/blackfin/include/asm/blackfin_local.h @@ -75,7 +75,15 @@ extern void blackfin_dcache_flush_invalidate_range(const void *, const void *); * regions can only be accessed via DMA, so if the address in question is in * that region, make sure we attempt to DMA indirectly. */ -# define addr_bfin_on_chip_mem(addr) (((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) +# ifdef __ADSPBF561__ + /* Core B regions all need dma from Core A */ +# define addr_bfin_on_chip_mem(addr) \ + ((((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) || \ + (((unsigned long)(addr) & 0xFFC00000) == 0xFF400000)) +# else +# define addr_bfin_on_chip_mem(addr) \ + (((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) +# endif # include <asm/system.h> diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h new file mode 100644 index 0000000..b650ef0 --- /dev/null +++ b/arch/blackfin/include/asm/gpio.h @@ -0,0 +1,201 @@ +/* + * Copyright 2006-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ARCH_BLACKFIN_GPIO_H__ +#define __ARCH_BLACKFIN_GPIO_H__ + +#define gpio_bank(x) ((x) >> 4) +#define gpio_bit(x) (1<<((x) & 0xF)) +#define gpio_sub_n(x) ((x) & 0xF) + +#define GPIO_BANKSIZE 16 +#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE) + +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 +#define GPIO_4 4 +#define GPIO_5 5 +#define GPIO_6 6 +#define GPIO_7 7 +#define GPIO_8 8 +#define GPIO_9 9 +#define GPIO_10 10 +#define GPIO_11 11 +#define GPIO_12 12 +#define GPIO_13 13 +#define GPIO_14 14 +#define GPIO_15 15 +#define GPIO_16 16 +#define GPIO_17 17 +#define GPIO_18 18 +#define GPIO_19 19 +#define GPIO_20 20 +#define GPIO_21 21 +#define GPIO_22 22 +#define GPIO_23 23 +#define GPIO_24 24 +#define GPIO_25 25 +#define GPIO_26 26 +#define GPIO_27 27 +#define GPIO_28 28 +#define GPIO_29 29 +#define GPIO_30 30 +#define GPIO_31 31 +#define GPIO_32 32 +#define GPIO_33 33 +#define GPIO_34 34 +#define GPIO_35 35 +#define GPIO_36 36 +#define GPIO_37 37 +#define GPIO_38 38 +#define GPIO_39 39 +#define GPIO_40 40 +#define GPIO_41 41 +#define GPIO_42 42 +#define GPIO_43 43 +#define GPIO_44 44 +#define GPIO_45 45 +#define GPIO_46 46 +#define GPIO_47 47 + +#define PERIPHERAL_USAGE 1 +#define GPIO_USAGE 0 + +#ifndef __ASSEMBLY__ + +#ifndef CONFIG_BF54x +void set_gpio_dir(unsigned, unsigned short); +void set_gpio_inen(unsigned, unsigned short); +void set_gpio_polar(unsigned, unsigned short); +void set_gpio_edge(unsigned, unsigned short); +void set_gpio_both(unsigned, unsigned short); +void set_gpio_data(unsigned, unsigned short); +void set_gpio_maska(unsigned, unsigned short); +void set_gpio_maskb(unsigned, unsigned short); +void set_gpio_toggle(unsigned); +void set_gpiop_dir(unsigned, unsigned short); +void set_gpiop_inen(unsigned, unsigned short); +void set_gpiop_polar(unsigned, unsigned short); +void set_gpiop_edge(unsigned, unsigned short); +void set_gpiop_both(unsigned, unsigned short); +void set_gpiop_data(unsigned, unsigned short); +void set_gpiop_maska(unsigned, unsigned short); +void set_gpiop_maskb(unsigned, unsigned short); +unsigned short get_gpio_dir(unsigned); +unsigned short get_gpio_inen(unsigned); +unsigned short get_gpio_polar(unsigned); +unsigned short get_gpio_edge(unsigned); +unsigned short get_gpio_both(unsigned); +unsigned short get_gpio_maska(unsigned); +unsigned short get_gpio_maskb(unsigned); +unsigned short get_gpio_data(unsigned); +unsigned short get_gpiop_dir(unsigned); +unsigned short get_gpiop_inen(unsigned); +unsigned short get_gpiop_polar(unsigned); +unsigned short get_gpiop_edge(unsigned); +unsigned short get_gpiop_both(unsigned); +unsigned short get_gpiop_maska(unsigned); +unsigned short get_gpiop_maskb(unsigned); +unsigned short get_gpiop_data(unsigned); + +struct gpio_port_t { + unsigned short data; + unsigned short dummy1; + unsigned short data_clear; + unsigned short dummy2; + unsigned short data_set; + unsigned short dummy3; + unsigned short toggle; + unsigned short dummy4; + unsigned short maska; + unsigned short dummy5; + unsigned short maska_clear; + unsigned short dummy6; + unsigned short maska_set; + unsigned short dummy7; + unsigned short maska_toggle; + unsigned short dummy8; + unsigned short maskb; + unsigned short dummy9; + unsigned short maskb_clear; + unsigned short dummy10; + unsigned short maskb_set; + unsigned short dummy11; + unsigned short maskb_toggle; + unsigned short dummy12; + unsigned short dir; + unsigned short dummy13; + unsigned short polar; + unsigned short dummy14; + unsigned short edge; + unsigned short dummy15; + unsigned short both; + unsigned short dummy16; + unsigned short inen; +}; +#endif + +#ifdef CONFIG_BFIN_GPIO_TRACK +void bfin_gpio_labels(void); +#else +#define bfin_gpio_labels() +#define bfin_gpio_request(gpio, label) bfin_gpio_request(gpio) +#define bfin_special_gpio_request(gpio, label) bfin_special_gpio_request(gpio) +#endif + +#ifdef BFIN_SPECIAL_GPIO_BANKS +void bfin_special_gpio_free(unsigned gpio); +int bfin_special_gpio_request(unsigned gpio, const char *label); +#endif + +int bfin_gpio_request(unsigned gpio, const char *label); +void bfin_gpio_free(unsigned gpio); +int bfin_gpio_direction_input(unsigned gpio); +int bfin_gpio_direction_output(unsigned gpio, int value); +int bfin_gpio_get_value(unsigned gpio); +void bfin_gpio_set_value(unsigned gpio, int value); +void bfin_gpio_toggle_value(unsigned gpio); + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return bfin_gpio_request(gpio, label); +} + +static inline void gpio_free(unsigned gpio) +{ + return bfin_gpio_free(gpio); +} + +static inline int gpio_direction_input(unsigned gpio) +{ + return bfin_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + return bfin_gpio_direction_output(gpio, value); +} + +static inline int gpio_get_value(unsigned gpio) +{ + return bfin_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + return bfin_gpio_set_value(gpio, value); +} + +static inline int gpio_is_valid(int number) +{ + return number >= 0 && number < MAX_BLACKFIN_GPIOS; +} + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_BLACKFIN_GPIO_H__ */ diff --git a/arch/blackfin/include/asm/mach-bf527/anomaly.h b/arch/blackfin/include/asm/mach-bf527/anomaly.h index 0fd7e31..9358afa 100644 --- a/arch/blackfin/include/asm/mach-bf527/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf527/anomaly.h @@ -1,19 +1,28 @@ /* - * File: include/asm-blackfin/mach-bf527/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2010 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List - * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List + * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List + * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ +/* We do not support old silicon - sorry */ +#if __SILICON_REVISION__ < 0 +# error will not work on BF526/BF527 silicon version +#endif + #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) # define ANOMALY_BF526 1 #else @@ -25,10 +34,14 @@ # define ANOMALY_BF527 0 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526) +#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527) +#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527)) + +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ +#define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ @@ -40,167 +53,226 @@ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ -#define ANOMALY_05000313 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Incorrect Access of OTP_STATUS During otp_write() Function */ -#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000328 (_ANOMALY_BF527(< 2)) /* Host DMA Boot Modes Are Not Functional */ #define ANOMALY_05000330 (__SILICON_REVISION__ < 2) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000337 (_ANOMALY_BF527(< 2)) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ -#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000341 (_ANOMALY_BF527(< 2)) /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ -#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000342 (_ANOMALY_BF527(< 2)) /* USB Calibration Value Is Not Initialized */ -#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2)) /* USB Calibration Value to use */ #define ANOMALY_05000346_value 0xE510 /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ -#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000347 (_ANOMALY_BF527(< 2)) /* Security Features Are Not Functional */ -#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1) +#define ANOMALY_05000348 (_ANOMALY_BF527(< 1)) /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ -#define ANOMALY_05000353 (ANOMALY_BF526) +#define ANOMALY_05000353 (_ANOMALY_BF526(< 1)) /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ -#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000355 (_ANOMALY_BF527(< 2)) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000357 (_ANOMALY_BF527(< 2)) /* Incorrect Revision Number in DSPID Register */ -#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1) +#define ANOMALY_05000364 (_ANOMALY_BF527(== 1)) /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ #define ANOMALY_05000366 (1) /* Incorrect Default CSEL Value in PLL_DIV */ -#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000368 (_ANOMALY_BF527(< 2)) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000371 (_ANOMALY_BF527(< 2)) /* Authentication Fails To Initiate */ -#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000376 (_ANOMALY_BF527(< 2)) /* Data Read From L3 Memory by USB DMA May be Corrupted */ -#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000380 (_ANOMALY_BF527(< 2)) /* 8-Bit NAND Flash Boot Mode Not Functional */ -#define ANOMALY_05000382 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Boot from OTP Memory Not Functional */ -#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000385 (_ANOMALY_BF527(< 2)) /* bfrom_SysControl() Firmware Routine Not Functional */ -#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000386 (_ANOMALY_BF527(< 2)) /* Programmable Preboot Settings Not Functional */ -#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000387 (_ANOMALY_BF527(< 2)) /* CRC32 Checksum Support Not Functional */ -#define ANOMALY_05000388 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Reset Vector Must Not Be in SDRAM Memory Space */ -#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000389 (_ANOMALY_BF527(< 2)) /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000392 (_ANOMALY_BF527(< 2)) /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000393 (_ANOMALY_BF527(< 2)) /* Log Buffer Not Functional */ -#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000394 (_ANOMALY_BF527(< 2)) /* Hook Routine Not Functional */ -#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000395 (_ANOMALY_BF527(< 2)) /* Header Indirect Bit Not Functional */ -#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000396 (_ANOMALY_BF527(< 2)) /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ -#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000397 (_ANOMALY_BF527(< 2)) /* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */ -#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000398 (_ANOMALY_BF527(< 2)) /* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */ -#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000399 (_ANOMALY_BF527(< 2)) /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ -#define ANOMALY_05000401 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ -#define ANOMALY_05000403 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Lockbox SESR Disallows Certain User Interrupts */ -#define ANOMALY_05000404 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ #define ANOMALY_05000405 (1) /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ -#define ANOMALY_05000407 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ #define ANOMALY_05000408 (1) /* Lockbox firmware leaves MDMA0 channel enabled */ -#define ANOMALY_05000409 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Incorrect Default Internal Voltage Regulator Setting */ -#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000410 (_ANOMALY_BF527(< 2)) /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ -#define ANOMALY_05000411 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2)) /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ -#define ANOMALY_05000414 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2)) /* DEB2_URGENT Bit Not Functional */ -#define ANOMALY_05000415 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Speculative Fetches Can Cause Undesired External FIFO Operations */ #define ANOMALY_05000416 (1) /* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */ -#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000417 (_ANOMALY_BF527(< 2)) /* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ -#define ANOMALY_05000418 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2)) /* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */ -#define ANOMALY_05000420 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2)) /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ #define ANOMALY_05000421 (1) /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ -#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) +#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1)) /* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */ -#define ANOMALY_05000423 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Internal Voltage Regulator Not Trimmed */ -#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000424 (_ANOMALY_BF527(< 2)) /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ #define ANOMALY_05000426 (1) /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ -#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Software System Reset Corrupts PLL_LOCKCNT Register */ -#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) +#define ANOMALY_05000430 (_ANOMALY_BF527(> 1)) /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ #define ANOMALY_05000431 (1) /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ -#define ANOMALY_05000432 (ANOMALY_BF526) +#define ANOMALY_05000432 (_ANOMALY_BF526(< 1)) +/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ +#define ANOMALY_05000434 (1) /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ -#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527) +#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0)) /* Preboot Cannot be Used to Alter the PLL_DIV Register */ -#define ANOMALY_05000439 (1) +#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0)) /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ -#define ANOMALY_05000440 (1) +#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0)) /* OTP Write Accesses Not Supported */ -#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) +#define ANOMALY_05000442 (_ANOMALY_BF527(< 1)) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) /* The WURESET Bit in the SYSCR Register is not Functional */ #define ANOMALY_05000445 (1) +/* USB DMA Mode 1 Short Packet Data Corruption */ +#define ANOMALY_05000450 (1) /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ #define ANOMALY_05000451 (1) /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ -#define ANOMALY_05000452 (1) +#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0)) /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ #define ANOMALY_05000456 (1) /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ #define ANOMALY_05000457 (1) +/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ +#define ANOMALY_05000460 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ +#define ANOMALY_05000462 (1) +/* USB Rx DMA hang */ +#define ANOMALY_05000465 (1) +/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ +#define ANOMALY_05000466 (1) +/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ +#define ANOMALY_05000467 (1) +/* PLL Latches Incorrect Settings During Reset */ +#define ANOMALY_05000469 (1) +/* Incorrect Default MSEL Value in PLL_CTL */ +#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0)) +/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000473 (1) +/* Possible Lockup Condition whem Modifying PLL from External Memory */ +#define ANOMALY_05000475 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ +#define ANOMALY_05000483 (1) +/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ +#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3)) +/* IFLUSH sucks at life */ +#define ANOMALY_05000491 (1) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000099 (0) +#define ANOMALY_05000120 (0) #define ANOMALY_05000125 (0) +#define ANOMALY_05000149 (0) #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) +#define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) +#define ANOMALY_05000189 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) +#define ANOMALY_05000215 (0) +#define ANOMALY_05000219 (0) +#define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) +#define ANOMALY_05000231 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000244 (0) +#define ANOMALY_05000248 (0) +#define ANOMALY_05000250 (0) +#define ANOMALY_05000257 (0) #define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) +#define ANOMALY_05000274 (0) #define ANOMALY_05000278 (0) +#define ANOMALY_05000281 (0) +#define ANOMALY_05000283 (0) #define ANOMALY_05000285 (0) +#define ANOMALY_05000287 (0) +#define ANOMALY_05000301 (0) #define ANOMALY_05000305 (0) #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000312 (0) +#define ANOMALY_05000315 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000400 (0) +#define ANOMALY_05000402 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) +#define ANOMALY_05000474 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf527/def_local.h b/arch/blackfin/include/asm/mach-bf527/def_local.h index 81eca83..1ffa239 100644 --- a/arch/blackfin/include/asm/mach-bf527/def_local.h +++ b/arch/blackfin/include/asm/mach-bf527/def_local.h @@ -1,2 +1,6 @@ +#include "gpio.h" #include "mem_map.h" +#include "portmux.h" #include "ports.h" + +#define CONFIG_BF52x 1 /* Linux glue */ diff --git a/arch/blackfin/include/asm/mach-bf527/gpio.h b/arch/blackfin/include/asm/mach-bf527/gpio.h new file mode 100644 index 0000000..f80c299 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf527/gpio.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2008 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define MAX_BLACKFIN_GPIOS 48 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PG0 16 +#define GPIO_PG1 17 +#define GPIO_PG2 18 +#define GPIO_PG3 19 +#define GPIO_PG4 20 +#define GPIO_PG5 21 +#define GPIO_PG6 22 +#define GPIO_PG7 23 +#define GPIO_PG8 24 +#define GPIO_PG9 25 +#define GPIO_PG10 26 +#define GPIO_PG11 27 +#define GPIO_PG12 28 +#define GPIO_PG13 29 +#define GPIO_PG14 30 +#define GPIO_PG15 31 +#define GPIO_PH0 32 +#define GPIO_PH1 33 +#define GPIO_PH2 34 +#define GPIO_PH3 35 +#define GPIO_PH4 36 +#define GPIO_PH5 37 +#define GPIO_PH6 38 +#define GPIO_PH7 39 +#define GPIO_PH8 40 +#define GPIO_PH9 41 +#define GPIO_PH10 42 +#define GPIO_PH11 43 +#define GPIO_PH12 44 +#define GPIO_PH13 45 +#define GPIO_PH14 46 +#define GPIO_PH15 47 + +#define PORT_F GPIO_PF0 +#define PORT_G GPIO_PG0 +#define PORT_H GPIO_PH0 + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf527/portmux.h b/arch/blackfin/include/asm/mach-bf527/portmux.h new file mode 100644 index 0000000..aa16558 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf527/portmux.h @@ -0,0 +1,220 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) + +#if !defined(CONFIG_BF527_SPORT0_PORTG) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#else +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) +#if !defined(CONFIG_BF527_SPORT0_TSCLK_PG14) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) +#else +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#endif +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#endif + +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) + +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2)) + +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2)) + +#if !defined(CONFIG_BF527_UART1_PORTG) +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2)) +#else +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) +#endif + +#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3)) +#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3)) +#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3)) + +#define P_HWAIT (P_DONTCARE) + +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1 +#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 + +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2)) +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */ +#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) +#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) +#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) + +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2)) + +#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2)) +#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2)) +#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2)) +#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2)) +#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2)) + +#if defined(CONFIG_BF527_NAND_D_PORTF) +#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2)) +#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2)) +#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2)) +#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2)) +#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2)) +#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2)) +#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2)) +#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2)) +#else /*if defined(CONFIG_BF527_NAND_D_PORTH)*/ +#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) +#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) +#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) +#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) +#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) +#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) +#endif + +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) +#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) +#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) +#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) +#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) +#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0)) +#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0)) + +#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2)) +#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2)) +#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2)) +#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2)) +#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) +#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2)) +#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2)) +#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2)) +#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2)) +#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2)) +#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2)) +#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2)) +#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2)) +#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2)) +#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2)) +#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2)) + +#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) +#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1)) +#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1)) +#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1)) +#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1)) +#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) +#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1)) +#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) +#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1)) +#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1)) +#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1)) +#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1)) +#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1)) +#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) +#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) +#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) +#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) +#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) + +#define P_TWI0_SCL (P_DONTCARE) +#define P_TWI0_SDA (P_DONTCARE) +#define P_PPI0_FS1 (P_DONTCARE) +#define P_TMR0 (P_DONTCARE) +#define P_TMRCLK (P_DONTCARE) +#define P_PPI0_CLK (P_DONTCARE) + +#define P_MII0 {\ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxD2, \ + P_MII0_ETxD3, \ + P_MII0_ETxEN, \ + P_MII0_TxCLK, \ + P_MII0_PHYINT, \ + P_MII0_COL, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxD2, \ + P_MII0_ERxD3, \ + P_MII0_ERxDV, \ + P_MII0_ERxCLK, \ + P_MII0_ERxER, \ + P_MII0_CRS, \ + P_MDC, \ + P_MDIO, 0} + +#define P_RMII0 {\ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxEN, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxER, \ + P_RMII0_REF_CLK, \ + P_RMII0_MDINT, \ + P_RMII0_CRS_DV, \ + P_MDC, \ + P_MDIO, 0} + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf533/anomaly.h b/arch/blackfin/include/asm/mach-bf533/anomaly.h index c98747f..78f8721 100644 --- a/arch/blackfin/include/asm/mach-bf533/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf533/anomaly.h @@ -1,9 +1,13 @@ /* - * File: include/asm-blackfin/mach-bf533/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2010 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: @@ -34,7 +38,7 @@ # define ANOMALY_BF533 0 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) @@ -46,7 +50,7 @@ #define ANOMALY_05000122 (1) /* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ #define ANOMALY_05000158 (__SILICON_REVISION__ < 5) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ #define ANOMALY_05000167 (1) @@ -56,13 +60,13 @@ #define ANOMALY_05000180 (1) /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ #define ANOMALY_05000183 (__SILICON_REVISION__ < 4) -/* False Protection Exceptions */ +/* False Protection Exceptions when Speculative Fetch Is Cancelled */ #define ANOMALY_05000189 (__SILICON_REVISION__ < 4) /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ #define ANOMALY_05000193 (__SILICON_REVISION__ < 4) /* Restarting SPORT in Specific Modes May Cause Data Corruption */ #define ANOMALY_05000194 (__SILICON_REVISION__ < 4) -/* Failing MMR Accesses When Stalled by Preceding Memory Read */ +/* Failing MMR Accesses when Preceding Memory Read Stalls */ #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) /* Current DMA Address Shows Wrong Value During Carry Fix */ #define ANOMALY_05000199 (__SILICON_REVISION__ < 4) @@ -74,7 +78,7 @@ #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) /* Specific Sequence That Can Cause DMA Error or DMA Stopping */ #define ANOMALY_05000203 (__SILICON_REVISION__ < 4) -/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ +/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ #define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) /* Recovery from "Brown-Out" Condition */ #define ANOMALY_05000207 (__SILICON_REVISION__ < 4) @@ -106,7 +110,7 @@ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) -/* Data CPLBs Should Prevent Spurious Hardware Errors */ +/* Data CPLBs Should Prevent False Hardware Errors */ #define ANOMALY_05000246 (__SILICON_REVISION__ < 5) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ == 4) @@ -148,21 +152,21 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 6) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 6) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 6) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 6) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (__SILICON_REVISION__ < 6) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 6) /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ #define ANOMALY_05000301 (__SILICON_REVISION__ < 6) -/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ +/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) -/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ +/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */ #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) /* SCKELOW Bit Does Not Maintain State Through Hibernate */ #define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ @@ -170,11 +174,11 @@ #define ANOMALY_05000310 (1) /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ #define ANOMALY_05000311 (__SILICON_REVISION__ < 6) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (__SILICON_REVISION__ < 6) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (__SILICON_REVISION__ < 6) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 6) /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ #define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) @@ -200,6 +204,18 @@ #define ANOMALY_05000426 (1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000473 (1) +/* Possible Lockup Condition whem Modifying PLL from External Memory */ +#define ANOMALY_05000475 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* IFLUSH sucks at life */ +#define ANOMALY_05000491 (1) /* These anomalies have been "phased" out of analog.com anomaly sheets and are * here to show running on older silicon just isn't feasible. @@ -213,17 +229,17 @@ #define ANOMALY_05000070 (__SILICON_REVISION__ < 2) /* Writing FIO_DIR can corrupt a programmable flag's data */ #define ANOMALY_05000079 (__SILICON_REVISION__ < 2) -/* Timer Auto-Baud Mode requires the UART clock to be enabled */ +/* Timer Auto-Baud Mode requires the UART clock to be enabled. */ #define ANOMALY_05000086 (__SILICON_REVISION__ < 2) /* Internal Clocking Modes on SPORT0 not supported */ #define ANOMALY_05000088 (__SILICON_REVISION__ < 2) /* Internal voltage regulator does not wake up from an RTC wakeup */ #define ANOMALY_05000092 (__SILICON_REVISION__ < 2) -/* The IFLUSH instruction must be preceded by a CSYNC instruction */ +/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */ #define ANOMALY_05000093 (__SILICON_REVISION__ < 2) -/* Vectoring to an instruction that is presently being filled into the instruction cache may cause erroneous behavior */ +/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */ #define ANOMALY_05000095 (__SILICON_REVISION__ < 2) -/* PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC */ +/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */ #define ANOMALY_05000096 (__SILICON_REVISION__ < 2) /* Performance Monitor 0 and 1 are swapped when monitoring memory events */ #define ANOMALY_05000097 (__SILICON_REVISION__ < 2) @@ -233,45 +249,45 @@ #define ANOMALY_05000100 (__SILICON_REVISION__ < 2) /* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ #define ANOMALY_05000101 (__SILICON_REVISION__ < 2) -/* Descriptor-based MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ +/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ #define ANOMALY_05000102 (__SILICON_REVISION__ < 2) -/* Incorrect value written to the cycle counters */ +/* Incorrect Value Written to the Cycle Counters */ #define ANOMALY_05000103 (__SILICON_REVISION__ < 2) -/* Stores to L1 Data memory incorrect when a specific sequence is followed */ +/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */ #define ANOMALY_05000104 (__SILICON_REVISION__ < 2) /* Programmable Flag (PF3) functionality not supported in all PPI modes */ #define ANOMALY_05000106 (__SILICON_REVISION__ < 2) /* Data store can be lost when targeting a cache line fill */ #define ANOMALY_05000107 (__SILICON_REVISION__ < 2) -/* Reserved bits in SYSCFG register not set at power on */ +/* Reserved Bits in SYSCFG Register Not Set at Power-On */ #define ANOMALY_05000109 (__SILICON_REVISION__ < 3) /* Infinite Core Stall */ #define ANOMALY_05000114 (__SILICON_REVISION__ < 2) -/* PPI_FSx may glitch when generated by the on chip Timers */ +/* PPI_FSx may glitch when generated by the on chip Timers. */ #define ANOMALY_05000115 (__SILICON_REVISION__ < 2) -/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ +/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) /* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ #define ANOMALY_05000117 (__SILICON_REVISION__ < 2) /* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ #define ANOMALY_05000118 (__SILICON_REVISION__ < 2) -/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ +/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */ #define ANOMALY_05000123 (__SILICON_REVISION__ < 3) /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ #define ANOMALY_05000124 (__SILICON_REVISION__ < 3) -/* Erroneous exception when enabling cache */ +/* Erroneous Exception when Enabling Cache */ #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) /* SPI clock polarity and phase bits incorrect during booting */ #define ANOMALY_05000126 (__SILICON_REVISION__ < 3) -/* DMEM_CONTROL is not set on Reset */ +/* DMEM_CONTROL<12> Is Not Set on Reset */ #define ANOMALY_05000137 (__SILICON_REVISION__ < 3) /* SPI boot will not complete if there is a zero fill block in the loader file */ #define ANOMALY_05000138 (__SILICON_REVISION__ == 2) -/* Timerx_Config must be set for using the PPI in GP output mode with internal Frame Syncs */ +/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */ #define ANOMALY_05000139 (__SILICON_REVISION__ < 2) /* Allowing the SPORT RX FIFO to fill will cause an overflow */ #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) @@ -285,7 +301,7 @@ #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ +/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */ #define ANOMALY_05000148 (__SILICON_REVISION__ < 3) /* Frame Delay in SPORT Multichannel Mode */ #define ANOMALY_05000153 (__SILICON_REVISION__ < 3) @@ -293,13 +309,13 @@ #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ #define ANOMALY_05000155 (__SILICON_REVISION__ < 3) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) -/* SPORT transmit data is not gated by external frame sync in certain conditions */ +/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* SDRAM auto-refresh and subsequent Power Ups */ +/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ #define ANOMALY_05000168 (__SILICON_REVISION__ < 3) -/* DATA CPLB page miss can result in lost write-through cache data writes */ +/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ #define ANOMALY_05000169 (__SILICON_REVISION__ < 3) /* DMA vs Core accesses to external memory */ #define ANOMALY_05000173 (__SILICON_REVISION__ < 3) @@ -307,32 +323,47 @@ #define ANOMALY_05000174 (__SILICON_REVISION__ < 3) /* Overlapping Sequencer and Memory Stalls */ #define ANOMALY_05000175 (__SILICON_REVISION__ < 3) -/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ +/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ #define ANOMALY_05000176 (__SILICON_REVISION__ < 3) -/* Disabling the PPI resets the PPI configuration registers */ +/* Disabling the PPI Resets the PPI Configuration Registers */ #define ANOMALY_05000181 (__SILICON_REVISION__ < 3) -/* PPI TX Mode with 2 External Frame Syncs */ +/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ #define ANOMALY_05000185 (__SILICON_REVISION__ < 3) /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) -/* In PPI Transmit Modes with External Frame Syncs POLC */ +/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */ #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) /* Internal Voltage Regulator may not start up */ #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000120 (0) +#define ANOMALY_05000149 (0) #define ANOMALY_05000171 (0) +#define ANOMALY_05000182 (0) +#define ANOMALY_05000220 (0) +#define ANOMALY_05000248 (0) #define ANOMALY_05000266 (0) +#define ANOMALY_05000274 (0) +#define ANOMALY_05000287 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000353 (1) #define ANOMALY_05000362 (1) +#define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) #define ANOMALY_05000386 (1) +#define ANOMALY_05000389 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000430 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) +#define ANOMALY_05000474 (0) +#define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf533/def_local.h b/arch/blackfin/include/asm/mach-bf533/def_local.h index 14c111f..c545b54 100644 --- a/arch/blackfin/include/asm/mach-bf533/def_local.h +++ b/arch/blackfin/include/asm/mach-bf533/def_local.h @@ -1 +1,5 @@ +#include "gpio.h" +#include "portmux.h" #include "ports.h" + +#define BF533_FAMILY 1 /* Linux glue */ diff --git a/arch/blackfin/include/asm/mach-bf533/gpio.h b/arch/blackfin/include/asm/mach-bf533/gpio.h new file mode 100644 index 0000000..e02416d --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf533/gpio.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2008 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define MAX_BLACKFIN_GPIOS 16 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 + +#define PORT_F GPIO_PF0 + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf533/portmux.h b/arch/blackfin/include/asm/mach-bf533/portmux.h new file mode 100644 index 0000000..96f5d91 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf533/portmux.h @@ -0,0 +1,71 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + +#define P_PPI0_CLK (P_DONTCARE) +#define P_PPI0_FS1 (P_DONTCARE) +#define P_PPI0_FS2 (P_DONTCARE) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11)) +#define P_PPI0_D0 (P_DONTCARE) +#define P_PPI0_D1 (P_DONTCARE) +#define P_PPI0_D2 (P_DONTCARE) +#define P_PPI0_D3 (P_DONTCARE) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12)) + +#define P_SPORT1_TSCLK (P_DONTCARE) +#define P_SPORT1_RSCLK (P_DONTCARE) +#define P_SPORT0_TSCLK (P_DONTCARE) +#define P_SPORT0_RSCLK (P_DONTCARE) +#define P_UART0_RX (P_DONTCARE) +#define P_UART0_TX (P_DONTCARE) +#define P_SPORT1_DRSEC (P_DONTCARE) +#define P_SPORT1_RFS (P_DONTCARE) +#define P_SPORT1_DTPRI (P_DONTCARE) +#define P_SPORT1_DTSEC (P_DONTCARE) +#define P_SPORT1_TFS (P_DONTCARE) +#define P_SPORT1_DRPRI (P_DONTCARE) +#define P_SPORT0_DRSEC (P_DONTCARE) +#define P_SPORT0_RFS (P_DONTCARE) +#define P_SPORT0_DTPRI (P_DONTCARE) +#define P_SPORT0_DTSEC (P_DONTCARE) +#define P_SPORT0_TFS (P_DONTCARE) +#define P_SPORT0_DRPRI (P_DONTCARE) + +#define P_SPI0_MOSI (P_DONTCARE) +#define P_SPI0_MISO (P_DONTCARE) +#define P_SPI0_SCK (P_DONTCARE) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2 +#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 + +#define P_TMR2 (P_DONTCARE) +#define P_TMR1 (P_DONTCARE) +#define P_TMR0 (P_DONTCARE) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1)) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf537/anomaly.h b/arch/blackfin/include/asm/mach-bf537/anomaly.h index b7f1a3f..43df6af 100644 --- a/arch/blackfin/include/asm/mach-bf537/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf537/anomaly.h @@ -1,9 +1,13 @@ /* - * File: include/asm-blackfin/mach-bf537/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2010 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: @@ -34,13 +38,13 @@ # define ANOMALY_BF537 0 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 2) /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) @@ -50,11 +54,11 @@ #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) -/* CLKIN Buffer Output Enable Reset Behavior Is Changed */ +/* Buffered CLKIN Output Is Disabled by Default */ #define ANOMALY_05000247 (1) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ < 3) -/* EMAC Tx DMA error after an early frame abort */ +/* EMAC TX DMA Error After an Early Frame Abort */ #define ANOMALY_05000252 (__SILICON_REVISION__ < 3) /* Maximum External Clock Speed for Timers */ #define ANOMALY_05000253 (__SILICON_REVISION__ < 3) @@ -62,7 +66,7 @@ #define ANOMALY_05000254 (__SILICON_REVISION__ > 2) /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ #define ANOMALY_05000255 (__SILICON_REVISION__ < 3) -/* EMAC MDIO input latched on wrong MDC edge */ +/* EMAC MDIO Input Latched on Wrong MDC Edge */ #define ANOMALY_05000256 (__SILICON_REVISION__ < 3) /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ #define ANOMALY_05000257 (__SILICON_REVISION__ < 3) @@ -80,7 +84,7 @@ #define ANOMALY_05000264 (__SILICON_REVISION__ < 3) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) -/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ +/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */ #define ANOMALY_05000268 (__SILICON_REVISION__ < 3) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ #define ANOMALY_05000270 (__SILICON_REVISION__ < 3) @@ -92,15 +96,15 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) -/* SPI Master boot mode does not work well with Atmel Data flash devices */ +/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */ #define ANOMALY_05000280 (1) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 3) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 3) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (__SILICON_REVISION__ < 3) -/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ +/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */ #define ANOMALY_05000285 (__SILICON_REVISION__ < 3) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 3) @@ -112,25 +116,25 @@ #define ANOMALY_05000305 (__SILICON_REVISION__ < 3) /* SCKELOW Bit Does Not Maintain State Through Hibernate */ #define ANOMALY_05000307 (__SILICON_REVISION__ < 3) -/* Writing UART_THR while UART clock is disabled sends erroneous start bit */ +/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */ #define ANOMALY_05000309 (__SILICON_REVISION__ < 3) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode: collisions occur in Full Duplex mode */ +/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */ #define ANOMALY_05000316 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */ +/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */ #define ANOMALY_05000321 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ +/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */ #define ANOMALY_05000322 (1) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) -/* New Feature: UART Remains Enabled after UART Boot */ +/* UART Gets Disabled after UART Boot */ #define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ #define ANOMALY_05000355 (1) @@ -143,7 +147,7 @@ /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) +#define ANOMALY_05000402 (__SILICON_REVISION__ == 2) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) /* Speculative Fetches Can Cause Undesired External FIFO Operations */ @@ -154,29 +158,66 @@ #define ANOMALY_05000426 (1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000473 (1) +/* Possible Lockup Condition whem Modifying PLL from External Memory */ +#define ANOMALY_05000475 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* IFLUSH sucks at life */ +#define ANOMALY_05000491 (1) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000099 (0) +#define ANOMALY_05000120 (0) #define ANOMALY_05000125 (0) +#define ANOMALY_05000149 (0) #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) +#define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) +#define ANOMALY_05000189 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) +#define ANOMALY_05000215 (0) +#define ANOMALY_05000219 (0) +#define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) +#define ANOMALY_05000231 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) +#define ANOMALY_05000248 (0) #define ANOMALY_05000266 (0) +#define ANOMALY_05000274 (0) +#define ANOMALY_05000287 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000353 (1) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) #define ANOMALY_05000386 (1) +#define ANOMALY_05000389 (0) +#define ANOMALY_05000400 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000430 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) +#define ANOMALY_05000474 (0) +#define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf537/def_local.h b/arch/blackfin/include/asm/mach-bf537/def_local.h index 14c111f..e210db9 100644 --- a/arch/blackfin/include/asm/mach-bf537/def_local.h +++ b/arch/blackfin/include/asm/mach-bf537/def_local.h @@ -1 +1,5 @@ +#include "gpio.h" +#include "portmux.h" #include "ports.h" + +#define BF537_FAMILY 1 /* Linux glue */ diff --git a/arch/blackfin/include/asm/mach-bf537/gpio.h b/arch/blackfin/include/asm/mach-bf537/gpio.h new file mode 100644 index 0000000..f80c299 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf537/gpio.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2008 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define MAX_BLACKFIN_GPIOS 48 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PG0 16 +#define GPIO_PG1 17 +#define GPIO_PG2 18 +#define GPIO_PG3 19 +#define GPIO_PG4 20 +#define GPIO_PG5 21 +#define GPIO_PG6 22 +#define GPIO_PG7 23 +#define GPIO_PG8 24 +#define GPIO_PG9 25 +#define GPIO_PG10 26 +#define GPIO_PG11 27 +#define GPIO_PG12 28 +#define GPIO_PG13 29 +#define GPIO_PG14 30 +#define GPIO_PG15 31 +#define GPIO_PH0 32 +#define GPIO_PH1 33 +#define GPIO_PH2 34 +#define GPIO_PH3 35 +#define GPIO_PH4 36 +#define GPIO_PH5 37 +#define GPIO_PH6 38 +#define GPIO_PH7 39 +#define GPIO_PH8 40 +#define GPIO_PH9 41 +#define GPIO_PH10 42 +#define GPIO_PH11 43 +#define GPIO_PH12 44 +#define GPIO_PH13 45 +#define GPIO_PH14 46 +#define GPIO_PH15 47 + +#define PORT_F GPIO_PF0 +#define PORT_G GPIO_PG0 +#define PORT_H GPIO_PH0 + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf537/portmux.h b/arch/blackfin/include/asm/mach-bf537/portmux.h new file mode 100644 index 0000000..71d9eae --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf537/portmux.h @@ -0,0 +1,152 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */ + +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) +#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10 +#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 + +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) + +#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) +#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) +#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) +#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) +#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) +#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) +#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) +#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) +#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) +#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) +#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) +#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) +#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0)) +#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0)) +#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) +#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) +#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1)) + +#define PORT_PJ0 (GPIO_PH15 + 1) +#define PORT_PJ1 (GPIO_PH15 + 2) +#define PORT_PJ2 (GPIO_PH15 + 3) +#define PORT_PJ3 (GPIO_PH15 + 4) +#define PORT_PJ4 (GPIO_PH15 + 5) +#define PORT_PJ5 (GPIO_PH15 + 6) +#define PORT_PJ6 (GPIO_PH15 + 7) +#define PORT_PJ7 (GPIO_PH15 + 8) +#define PORT_PJ8 (GPIO_PH15 + 9) +#define PORT_PJ9 (GPIO_PH15 + 10) +#define PORT_PJ10 (GPIO_PH15 + 11) +#define PORT_PJ11 (GPIO_PH15 + 12) + +#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0)) +#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0)) +#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0)) +#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0)) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0)) +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0)) +#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1)) +#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2)) + +#define P_MII0 {\ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxD2, \ + P_MII0_ETxD3, \ + P_MII0_ETxEN, \ + P_MII0_TxCLK, \ + P_MII0_PHYINT, \ + P_MII0_COL, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxD2, \ + P_MII0_ERxD3, \ + P_MII0_ERxDV, \ + P_MII0_ERxCLK, \ + P_MII0_ERxER, \ + P_MII0_CRS, \ + P_MDC, \ + P_MDIO, 0} + +#define P_RMII0 {\ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxEN, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxER, \ + P_RMII0_REF_CLK, \ + P_RMII0_MDINT, \ + P_RMII0_CRS_DV, \ + P_MDC, \ + P_MDIO, 0} + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf548/anomaly.h b/arch/blackfin/include/asm/mach-bf548/anomaly.h index 192dd67..7bda09c 100644 --- a/arch/blackfin/include/asm/mach-bf548/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf548/anomaly.h @@ -1,41 +1,54 @@ /* - * File: include/asm-blackfin/mach-bf548/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2010 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List + * - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* We do not support 0.0 or 0.1 silicon - sorry */ +/* XXX: let u-boot slide +#if __SILICON_REVISION__ < 2 +# error will not work on BF548 silicon version 0.0, or 0.1 +#endif +*/ + +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) +/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ +#define ANOMALY_05000220 (1) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 1) /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ #define ANOMALY_05000304 (__SILICON_REVISION__ < 1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (__SILICON_REVISION__ < 1) /* TWI Slave Boot Mode Is Not Functional */ #define ANOMALY_05000324 (__SILICON_REVISION__ < 1) -/* External FIFO Boot Mode Is Not Functional */ +/* FIFO Boot Mode Not Functional */ #define ANOMALY_05000325 (__SILICON_REVISION__ < 2) /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ #define ANOMALY_05000327 (__SILICON_REVISION__ < 1) @@ -157,6 +170,8 @@ #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ #define ANOMALY_05000431 (__SILICON_REVISION__ < 3) +/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ +#define ANOMALY_05000434 (1) /* OTP Write Accesses Not Supported */ #define ANOMALY_05000442 (__SILICON_REVISION__ < 1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ @@ -170,32 +185,93 @@ /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ #define ANOMALY_05000449 (__SILICON_REVISION__ == 1) /* USB DMA Mode 1 Short Packet Data Corruption */ -#define ANOMALY_05000450 (1 +#define ANOMALY_05000450 (1) +/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ +#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) +/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ +#define ANOMALY_05000456 (1) +/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ +#define ANOMALY_05000457 (1) +/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ +#define ANOMALY_05000460 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ +#define ANOMALY_05000462 (1) +/* USB DMA RX Data Corruption */ +#define ANOMALY_05000463 (1) +/* USB TX DMA Hang */ +#define ANOMALY_05000464 (1) +/* USB Rx DMA hang */ +#define ANOMALY_05000465 (1) +/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ +#define ANOMALY_05000466 (1) +/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ +#define ANOMALY_05000467 (1) +/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000473 (1) +/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */ +#define ANOMALY_05000474 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ +#define ANOMALY_05000483 (1) +/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ +#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2) +/* IFLUSH sucks at life */ +#define ANOMALY_05000491 (1) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000099 (0) +#define ANOMALY_05000120 (0) #define ANOMALY_05000125 (0) +#define ANOMALY_05000149 (0) #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) +#define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) +#define ANOMALY_05000189 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) +#define ANOMALY_05000215 (0) +#define ANOMALY_05000219 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) +#define ANOMALY_05000231 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000244 (0) +#define ANOMALY_05000248 (0) +#define ANOMALY_05000250 (0) +#define ANOMALY_05000254 (0) +#define ANOMALY_05000257 (0) #define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) +#define ANOMALY_05000274 (0) #define ANOMALY_05000278 (0) +#define ANOMALY_05000283 (0) +#define ANOMALY_05000287 (0) +#define ANOMALY_05000301 (0) #define ANOMALY_05000305 (0) #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) +#define ANOMALY_05000315 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000400 (0) +#define ANOMALY_05000402 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) +#define ANOMALY_05000475 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf548/def_local.h b/arch/blackfin/include/asm/mach-bf548/def_local.h index 81eca83..f1e69a7 100644 --- a/arch/blackfin/include/asm/mach-bf548/def_local.h +++ b/arch/blackfin/include/asm/mach-bf548/def_local.h @@ -1,2 +1,6 @@ +#include "gpio.h" #include "mem_map.h" +#include "portmux.h" #include "ports.h" + +#define CONFIG_BF54x 1 /* Linux glue */ diff --git a/arch/blackfin/include/asm/mach-bf548/gpio.h b/arch/blackfin/include/asm/mach-bf548/gpio.h new file mode 100644 index 0000000..28037e3 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf548/gpio.h @@ -0,0 +1,203 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define GPIO_PA0 0 +#define GPIO_PA1 1 +#define GPIO_PA2 2 +#define GPIO_PA3 3 +#define GPIO_PA4 4 +#define GPIO_PA5 5 +#define GPIO_PA6 6 +#define GPIO_PA7 7 +#define GPIO_PA8 8 +#define GPIO_PA9 9 +#define GPIO_PA10 10 +#define GPIO_PA11 11 +#define GPIO_PA12 12 +#define GPIO_PA13 13 +#define GPIO_PA14 14 +#define GPIO_PA15 15 +#define GPIO_PB0 16 +#define GPIO_PB1 17 +#define GPIO_PB2 18 +#define GPIO_PB3 19 +#define GPIO_PB4 20 +#define GPIO_PB5 21 +#define GPIO_PB6 22 +#define GPIO_PB7 23 +#define GPIO_PB8 24 +#define GPIO_PB9 25 +#define GPIO_PB10 26 +#define GPIO_PB11 27 +#define GPIO_PB12 28 +#define GPIO_PB13 29 +#define GPIO_PB14 30 +#define GPIO_PB15 31 /* N/A */ +#define GPIO_PC0 32 +#define GPIO_PC1 33 +#define GPIO_PC2 34 +#define GPIO_PC3 35 +#define GPIO_PC4 36 +#define GPIO_PC5 37 +#define GPIO_PC6 38 +#define GPIO_PC7 39 +#define GPIO_PC8 40 +#define GPIO_PC9 41 +#define GPIO_PC10 42 +#define GPIO_PC11 43 +#define GPIO_PC12 44 +#define GPIO_PC13 45 +#define GPIO_PC14 46 /* N/A */ +#define GPIO_PC15 47 /* N/A */ +#define GPIO_PD0 48 +#define GPIO_PD1 49 +#define GPIO_PD2 50 +#define GPIO_PD3 51 +#define GPIO_PD4 52 +#define GPIO_PD5 53 +#define GPIO_PD6 54 +#define GPIO_PD7 55 +#define GPIO_PD8 56 +#define GPIO_PD9 57 +#define GPIO_PD10 58 +#define GPIO_PD11 59 +#define GPIO_PD12 60 +#define GPIO_PD13 61 +#define GPIO_PD14 62 +#define GPIO_PD15 63 +#define GPIO_PE0 64 +#define GPIO_PE1 65 +#define GPIO_PE2 66 +#define GPIO_PE3 67 +#define GPIO_PE4 68 +#define GPIO_PE5 69 +#define GPIO_PE6 70 +#define GPIO_PE7 71 +#define GPIO_PE8 72 +#define GPIO_PE9 73 +#define GPIO_PE10 74 +#define GPIO_PE11 75 +#define GPIO_PE12 76 +#define GPIO_PE13 77 +#define GPIO_PE14 78 +#define GPIO_PE15 79 +#define GPIO_PF0 80 +#define GPIO_PF1 81 +#define GPIO_PF2 82 +#define GPIO_PF3 83 +#define GPIO_PF4 84 +#define GPIO_PF5 85 +#define GPIO_PF6 86 +#define GPIO_PF7 87 +#define GPIO_PF8 88 +#define GPIO_PF9 89 +#define GPIO_PF10 90 +#define GPIO_PF11 91 +#define GPIO_PF12 92 +#define GPIO_PF13 93 +#define GPIO_PF14 94 +#define GPIO_PF15 95 +#define GPIO_PG0 96 +#define GPIO_PG1 97 +#define GPIO_PG2 98 +#define GPIO_PG3 99 +#define GPIO_PG4 100 +#define GPIO_PG5 101 +#define GPIO_PG6 102 +#define GPIO_PG7 103 +#define GPIO_PG8 104 +#define GPIO_PG9 105 +#define GPIO_PG10 106 +#define GPIO_PG11 107 +#define GPIO_PG12 108 +#define GPIO_PG13 109 +#define GPIO_PG14 110 +#define GPIO_PG15 111 +#define GPIO_PH0 112 +#define GPIO_PH1 113 +#define GPIO_PH2 114 +#define GPIO_PH3 115 +#define GPIO_PH4 116 +#define GPIO_PH5 117 +#define GPIO_PH6 118 +#define GPIO_PH7 119 +#define GPIO_PH8 120 +#define GPIO_PH9 121 +#define GPIO_PH10 122 +#define GPIO_PH11 123 +#define GPIO_PH12 124 +#define GPIO_PH13 125 +#define GPIO_PH14 126 /* N/A */ +#define GPIO_PH15 127 /* N/A */ +#define GPIO_PI0 128 +#define GPIO_PI1 129 +#define GPIO_PI2 130 +#define GPIO_PI3 131 +#define GPIO_PI4 132 +#define GPIO_PI5 133 +#define GPIO_PI6 134 +#define GPIO_PI7 135 +#define GPIO_PI8 136 +#define GPIO_PI9 137 +#define GPIO_PI10 138 +#define GPIO_PI11 139 +#define GPIO_PI12 140 +#define GPIO_PI13 141 +#define GPIO_PI14 142 +#define GPIO_PI15 143 +#define GPIO_PJ0 144 +#define GPIO_PJ1 145 +#define GPIO_PJ2 146 +#define GPIO_PJ3 147 +#define GPIO_PJ4 148 +#define GPIO_PJ5 149 +#define GPIO_PJ6 150 +#define GPIO_PJ7 151 +#define GPIO_PJ8 152 +#define GPIO_PJ9 153 +#define GPIO_PJ10 154 +#define GPIO_PJ11 155 +#define GPIO_PJ12 156 +#define GPIO_PJ13 157 +#define GPIO_PJ14 158 /* N/A */ +#define GPIO_PJ15 159 /* N/A */ + +#define MAX_BLACKFIN_GPIOS 160 + +#ifndef __ASSEMBLY__ + +struct gpio_port_t { + unsigned short port_fer; + unsigned short dummy1; + unsigned short data; + unsigned short dummy2; + unsigned short data_set; + unsigned short dummy3; + unsigned short data_clear; + unsigned short dummy4; + unsigned short dir_set; + unsigned short dummy5; + unsigned short dir_clear; + unsigned short dummy6; + unsigned short inen; + unsigned short dummy7; + unsigned int port_mux; +}; + +struct gpio_port_s { + unsigned short fer; + unsigned short data; + unsigned short dir; + unsigned short inen; + unsigned int mux; +}; + +#endif + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf548/portmux.h b/arch/blackfin/include/asm/mach-bf548/portmux.h new file mode 100644 index 0000000..e222462 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf548/portmux.h @@ -0,0 +1,320 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + +#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) +#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) +#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) +#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0)) +#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0)) +#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0)) +#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0)) +#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0)) +#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0)) +#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0)) +#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0)) +#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0)) +#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0)) +#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0)) +#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0)) +#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1)) + +#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0)) +#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0)) +#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0)) +#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0)) +#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0)) +#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0)) +#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0)) +#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0)) +#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0)) +#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0)) +#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0)) +#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0)) +#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0)) +#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0)) +#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1)) + +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0)) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0)) +#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0)) +#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0)) +#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0)) +#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0)) +#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0)) +#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0)) +#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1)) +#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1)) + +#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0)) +#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0)) +#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0)) +#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0)) +#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0)) +#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0)) +#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0)) +#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0)) +#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0)) +#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0)) +#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0)) +#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0)) +#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0)) +#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0)) +#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0)) +#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0)) + +#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1)) +#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1)) +#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1)) +#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1)) +#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1)) +#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1)) +#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1)) +#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1)) +#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1)) +#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1)) +#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1)) +#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1)) +#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1)) +#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1)) +#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1)) +#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2)) +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2)) +#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2)) +#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2)) +#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2)) +#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2)) +#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2)) +#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2)) +#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2)) +#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2)) +#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3)) +#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3)) +#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3)) +#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3)) +#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3)) +#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3)) +#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3)) +#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3)) +#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3)) +#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3)) +#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3)) +#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3)) +#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3)) +#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3)) + +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4 +#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0)) +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0)) +#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0)) +#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0)) +#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0)) +#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0)) +#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0)) +#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0)) +#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0)) +#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1)) +#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1)) +#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1)) +#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1)) +#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1)) +#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1)) +#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1)) +#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1)) + +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) + +#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT +# define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +# define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +# define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +# define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +# define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +# define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +# define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +# define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +# define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +# define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +# define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) +# define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) +# define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) +# define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) +# define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +# define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) +#else +# define P_ATAPI_D0A (P_DONTCARE) +# define P_ATAPI_D1A (P_DONTCARE) +# define P_ATAPI_D2A (P_DONTCARE) +# define P_ATAPI_D3A (P_DONTCARE) +# define P_ATAPI_D4A (P_DONTCARE) +# define P_ATAPI_D5A (P_DONTCARE) +# define P_ATAPI_D6A (P_DONTCARE) +# define P_ATAPI_D7A (P_DONTCARE) +# define P_ATAPI_D8A (P_DONTCARE) +# define P_ATAPI_D9A (P_DONTCARE) +# define P_ATAPI_D10A (P_DONTCARE) +# define P_ATAPI_D11A (P_DONTCARE) +# define P_ATAPI_D12A (P_DONTCARE) +# define P_ATAPI_D13A (P_DONTCARE) +# define P_ATAPI_D14A (P_DONTCARE) +# define P_ATAPI_D15A (P_DONTCARE) +#endif + +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) +#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) +#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) +#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT +# define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1)) +# define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) +# define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) +#else +# define P_ATAPI_A0A (P_DONTCARE) +# define P_ATAPI_A1A (P_DONTCARE) +# define P_ATAPI_A2A (P_DONTCARE) +#endif +#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) +#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) +#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) +#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2)) +#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) +#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) +#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3)) + +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) +#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) +#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) +#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) +#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) +#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) +#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) +#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) +#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) +#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) +#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) +#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) +#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) +#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) +#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1)) +#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) +#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) +#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2)) +#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2)) +#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) + +#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0)) +#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0)) +#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0)) +#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0)) +#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0)) +#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0)) +#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0)) +#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0)) +#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0)) +#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0)) +#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0)) +#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0)) +#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0)) +#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0)) +#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0)) +#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0)) +#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1)) + +#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0)) +#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0)) +#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0)) +#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0)) +#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0)) +#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0)) +#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0)) +#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0)) +#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0)) +#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0)) +#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0)) +#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0)) +#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0)) +#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0)) + + +#define P_NAND_D0 (P_DONTCARE) +#define P_NAND_D1 (P_DONTCARE) +#define P_NAND_D2 (P_DONTCARE) +#define P_NAND_D3 (P_DONTCARE) +#define P_NAND_D4 (P_DONTCARE) +#define P_NAND_D5 (P_DONTCARE) +#define P_NAND_D6 (P_DONTCARE) +#define P_NAND_D7 (P_DONTCARE) +#define P_NAND_WE (P_DONTCARE) +#define P_NAND_RE (P_DONTCARE) +#define P_NAND_CLE (P_DONTCARE) +#define P_NAND_ALE (P_DONTCARE) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf561/anomaly.h b/arch/blackfin/include/asm/mach-bf561/anomaly.h index e4aa20c..4c108c9 100644 --- a/arch/blackfin/include/asm/mach-bf561/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf561/anomaly.h @@ -1,9 +1,13 @@ /* - * File: include/asm-blackfin/mach-bf561/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2010 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: @@ -18,19 +22,19 @@ # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ +/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) -/* Testset instructions restricted to 32-bit aligned memory locations */ +/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ #define ANOMALY_05000120 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Erroneous exception when enabling cache */ +/* Erroneous Exception when Enabling Cache */ #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) -/* Signbits instruction not functional under certain conditions */ +/* SIGNBITS Instruction Not Functional under Certain Conditions */ #define ANOMALY_05000127 (1) /* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ #define ANOMALY_05000134 (__SILICON_REVISION__ < 3) @@ -40,7 +44,7 @@ #define ANOMALY_05000136 (__SILICON_REVISION__ < 3) /* Allowing the SPORT RX FIFO to fill will cause an overflow */ #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) @@ -52,7 +56,7 @@ #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* IMDMA S1/D1 channel may stall */ +/* IMDMA S1/D1 Channel May Stall */ #define ANOMALY_05000149 (1) /* DMA engine may lose data due to incorrect handshaking */ #define ANOMALY_05000150 (__SILICON_REVISION__ < 3) @@ -66,7 +70,7 @@ #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ #define ANOMALY_05000156 (__SILICON_REVISION__ < 4) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ #define ANOMALY_05000159 (__SILICON_REVISION__ < 3) @@ -76,17 +80,17 @@ #define ANOMALY_05000161 (__SILICON_REVISION__ < 3) /* DMEM_CONTROL<12> is not set on Reset */ #define ANOMALY_05000162 (__SILICON_REVISION__ < 3) -/* SPORT transmit data is not gated by external frame sync in certain conditions */ +/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ #define ANOMALY_05000167 (1) -/* SDRAM auto-refresh and subsequent Power Ups */ +/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ #define ANOMALY_05000168 (__SILICON_REVISION__ < 5) -/* DATA CPLB page miss can result in lost write-through cache data writes */ +/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ #define ANOMALY_05000169 (__SILICON_REVISION__ < 5) -/* Boot-ROM code modifies SICA_IWRx wakeup registers */ +/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ #define ANOMALY_05000171 (__SILICON_REVISION__ < 5) /* DSPID register values incorrect */ #define ANOMALY_05000172 (__SILICON_REVISION__ < 3) @@ -96,29 +100,29 @@ #define ANOMALY_05000174 (__SILICON_REVISION__ < 5) /* Overlapping Sequencer and Memory Stalls */ #define ANOMALY_05000175 (__SILICON_REVISION__ < 5) -/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ +/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ #define ANOMALY_05000176 (__SILICON_REVISION__ < 5) /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) -/* Disabling the PPI resets the PPI configuration registers */ +/* Disabling the PPI Resets the PPI Configuration Registers */ #define ANOMALY_05000181 (__SILICON_REVISION__ < 5) -/* IMDMA does not operate to full speed for 600MHz and higher devices */ +/* Internal Memory DMA Does Not Operate at Full Speed */ #define ANOMALY_05000182 (1) -/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */ +/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ #define ANOMALY_05000184 (__SILICON_REVISION__ < 5) -/* PPI TX Mode with 2 External Frame Syncs */ +/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ #define ANOMALY_05000185 (__SILICON_REVISION__ < 5) -/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */ +/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */ #define ANOMALY_05000186 (__SILICON_REVISION__ < 5) /* IMDMA Corrupted Data after a Halt */ #define ANOMALY_05000187 (1) /* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ #define ANOMALY_05000188 (__SILICON_REVISION__ < 5) -/* False Protection Exceptions */ +/* False Protection Exceptions when Speculative Fetch Is Cancelled */ #define ANOMALY_05000189 (__SILICON_REVISION__ < 5) -/* PPI not functional at core voltage < 1Volt */ +/* PPI Not Functional at Core Voltage < 1Volt */ #define ANOMALY_05000190 (1) /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) @@ -126,7 +130,7 @@ #define ANOMALY_05000193 (__SILICON_REVISION__ < 5) /* Restarting SPORT in Specific Modes May Cause Data Corruption */ #define ANOMALY_05000194 (__SILICON_REVISION__ < 5) -/* Failing MMR Accesses When Stalled by Preceding Memory Read */ +/* Failing MMR Accesses when Preceding Memory Read Stalls */ #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) /* Current DMA Address Shows Wrong Value During Carry Fix */ #define ANOMALY_05000199 (__SILICON_REVISION__ < 5) @@ -134,9 +138,9 @@ #define ANOMALY_05000200 (__SILICON_REVISION__ < 5) /* Possible Infinite Stall with Specific Dual-DAG Situation */ #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) -/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ +/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ #define ANOMALY_05000204 (__SILICON_REVISION__ < 5) -/* Specific sequence that can cause DMA error or DMA stopping */ +/* Specific Sequence that Can Cause DMA Error or DMA Stopping */ #define ANOMALY_05000205 (__SILICON_REVISION__ < 5) /* Recovery from "Brown-Out" Condition */ #define ANOMALY_05000207 (__SILICON_REVISION__ < 5) @@ -148,8 +152,8 @@ #define ANOMALY_05000215 (__SILICON_REVISION__ < 5) /* NMI Event at Boot Time Results in Unpredictable State */ #define ANOMALY_05000219 (__SILICON_REVISION__ < 5) -/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ -#define ANOMALY_05000220 (__SILICON_REVISION__ < 5) +/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ +#define ANOMALY_05000220 (__SILICON_REVISION__ < 4) /* Incorrect Pulse-Width of UART Start Bit */ #define ANOMALY_05000225 (__SILICON_REVISION__ < 5) /* Scratchpad Memory Bank Reads May Return Incorrect Data */ @@ -158,7 +162,7 @@ #define ANOMALY_05000230 (__SILICON_REVISION__ < 5) /* UART STB Bit Incorrectly Affects Receiver Setting */ #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) -/* SPORT data transmit lines are incorrectly driven in multichannel mode */ +/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */ #define ANOMALY_05000232 (__SILICON_REVISION__ < 5) /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) @@ -166,7 +170,7 @@ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (__SILICON_REVISION__ < 5) -/* TESTSET operation forces stall on the other core */ +/* TESTSET Operation Forces Stall on the Other Core */ #define ANOMALY_05000248 (__SILICON_REVISION__ < 5) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) @@ -192,9 +196,9 @@ #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (__SILICON_REVISION__ < 5) -/* IMDMA destination IRQ status must be read prior to using IMDMA */ +/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */ #define ANOMALY_05000266 (__SILICON_REVISION__ > 3) -/* IMDMA may corrupt data under certain conditions */ +/* IMDMA May Corrupt Data under Certain Conditions */ #define ANOMALY_05000267 (1) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ #define ANOMALY_05000269 (1) @@ -202,7 +206,7 @@ #define ANOMALY_05000270 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* Data cache write back to external synchronous memory may be lost */ +/* Data Cache Write Back to External Synchronous Memory May Be Lost */ #define ANOMALY_05000274 (1) /* PPI Timing and Sampling Information Updates */ #define ANOMALY_05000275 (__SILICON_REVISION__ > 2) @@ -212,17 +216,21 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) -/* False Hardware Error Exception When ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 5) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* Temporarily walk around for bug 5423 till this issue is confirmed by + * official anomaly document. It looks 05000281 still exists on bf561 + * v0.5. + */ +#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5) +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (1) -/* A read will receive incorrect data under certain conditions */ +/* Reads Will Receive Incorrect Data under Certain Conditions */ #define ANOMALY_05000287 (__SILICON_REVISION__ < 5) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 5) /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ #define ANOMALY_05000301 (1) -/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ +/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ #define ANOMALY_05000302 (1) /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) @@ -230,25 +238,25 @@ #define ANOMALY_05000307 (__SILICON_REVISION__ < 5) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (1) -/* PF2 Output Remains Asserted After SPI Master Boot */ +/* PF2 Output Remains Asserted after SPI Master Boot */ #define ANOMALY_05000320 (__SILICON_REVISION__ > 3) -/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */ +/* Erroneous GPIO Flag Pin Operations under Specific Sequences */ #define ANOMALY_05000323 (1) -/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */ +/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */ #define ANOMALY_05000326 (__SILICON_REVISION__ > 3) -/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */ +/* 24-Bit SPI Boot Mode Is Not Functional */ #define ANOMALY_05000331 (__SILICON_REVISION__ < 5) -/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */ +/* Slave SPI Boot Mode Is Not Functional */ #define ANOMALY_05000332 (__SILICON_REVISION__ < 5) -/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ +/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */ #define ANOMALY_05000333 (__SILICON_REVISION__ < 5) -/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */ +/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000339 (__SILICON_REVISION__ < 5) /* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ #define ANOMALY_05000343 (__SILICON_REVISION__ < 5) @@ -262,6 +270,8 @@ #define ANOMALY_05000366 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ == 4) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ @@ -276,19 +286,43 @@ #define ANOMALY_05000428 (__SILICON_REVISION__ > 3) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000473 (1) +/* Possible Lockup Condition whem Modifying PLL from External Memory */ +#define ANOMALY_05000475 (__SILICON_REVISION__ < 4) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* IFLUSH sucks at life */ +#define ANOMALY_05000491 (1) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000119 (0) #define ANOMALY_05000158 (0) #define ANOMALY_05000183 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000353 (1) +#define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) #define ANOMALY_05000386 (1) +#define ANOMALY_05000389 (0) +#define ANOMALY_05000400 (0) #define ANOMALY_05000430 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) +#define ANOMALY_05000474 (0) +#define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf561/def_local.h b/arch/blackfin/include/asm/mach-bf561/def_local.h index 597dcec..08e37e5 100644 --- a/arch/blackfin/include/asm/mach-bf561/def_local.h +++ b/arch/blackfin/include/asm/mach-bf561/def_local.h @@ -9,4 +9,8 @@ #define bfin_write_WDOG_CTL(val) bfin_write_WDOGA_CTL(val) #define bfin_write_WDOG_STAT(val) bfin_write_WDOGA_STAT(val) +#include "gpio.h" +#include "portmux.h" #include "ports.h" + +#define BF561_FAMILY 1 /* Linux glue */ diff --git a/arch/blackfin/include/asm/mach-bf561/gpio.h b/arch/blackfin/include/asm/mach-bf561/gpio.h new file mode 100644 index 0000000..4f8aa5d --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf561/gpio.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2008 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define MAX_BLACKFIN_GPIOS 48 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PF16 16 +#define GPIO_PF17 17 +#define GPIO_PF18 18 +#define GPIO_PF19 19 +#define GPIO_PF20 20 +#define GPIO_PF21 21 +#define GPIO_PF22 22 +#define GPIO_PF23 23 +#define GPIO_PF24 24 +#define GPIO_PF25 25 +#define GPIO_PF26 26 +#define GPIO_PF27 27 +#define GPIO_PF28 28 +#define GPIO_PF29 29 +#define GPIO_PF30 30 +#define GPIO_PF31 31 +#define GPIO_PF32 32 +#define GPIO_PF33 33 +#define GPIO_PF34 34 +#define GPIO_PF35 35 +#define GPIO_PF36 36 +#define GPIO_PF37 37 +#define GPIO_PF38 38 +#define GPIO_PF39 39 +#define GPIO_PF40 40 +#define GPIO_PF41 41 +#define GPIO_PF42 42 +#define GPIO_PF43 43 +#define GPIO_PF44 44 +#define GPIO_PF45 45 +#define GPIO_PF46 46 +#define GPIO_PF47 47 + +#define PORT_FIO0 GPIO_0 +#define PORT_FIO1 GPIO_16 +#define PORT_FIO2 GPIO_32 + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf561/portmux.h b/arch/blackfin/include/asm/mach-bf561/portmux.h new file mode 100644 index 0000000..2339ffd --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf561/portmux.h @@ -0,0 +1,97 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + +#define P_PPI0_CLK (P_DONTCARE) +#define P_PPI0_FS1 (P_DONTCARE) +#define P_PPI0_FS2 (P_DONTCARE) +#define P_PPI0_FS3 (P_DONTCARE) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40)) +#define P_PPI0_D0 (P_DONTCARE) +#define P_PPI0_D1 (P_DONTCARE) +#define P_PPI0_D2 (P_DONTCARE) +#define P_PPI0_D3 (P_DONTCARE) +#define P_PPI0_D4 (P_DONTCARE) +#define P_PPI0_D5 (P_DONTCARE) +#define P_PPI0_D6 (P_DONTCARE) +#define P_PPI0_D7 (P_DONTCARE) +#define P_PPI1_CLK (P_DONTCARE) +#define P_PPI1_FS1 (P_DONTCARE) +#define P_PPI1_FS2 (P_DONTCARE) +#define P_PPI1_FS3 (P_DONTCARE) +#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39)) +#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38)) +#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37)) +#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36)) +#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35)) +#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34)) +#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33)) +#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32)) +#define P_PPI1_D0 (P_DONTCARE) +#define P_PPI1_D1 (P_DONTCARE) +#define P_PPI1_D2 (P_DONTCARE) +#define P_PPI1_D3 (P_DONTCARE) +#define P_PPI1_D4 (P_DONTCARE) +#define P_PPI1_D5 (P_DONTCARE) +#define P_PPI1_D6 (P_DONTCARE) +#define P_PPI1_D7 (P_DONTCARE) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27)) +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21)) +#define P_SPORT1_DRPRI (P_DONTCARE) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17)) +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16)) +#define P_SPORT0_DRPRI (P_DONTCARE) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) +#define P_TMR11 (P_DONTCARE) +#define P_TMR10 (P_DONTCARE) +#define P_TMR9 (P_DONTCARE) +#define P_TMR8 (P_DONTCARE) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0)) +#define P_SPI0_MOSI (P_DONTCARE) +#define P_SPI0_MISO (P_DONTCARE) +#define P_SPI0_SCK (P_DONTCARE) +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2 +#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h new file mode 100644 index 0000000..b17207f --- /dev/null +++ b/arch/blackfin/include/asm/portmux.h @@ -0,0 +1,1194 @@ +/* + * Common header file for Blackfin family of processors + * + * Copyright 2007-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _PORTMUX_H_ +#define _PORTMUX_H_ + +#define P_IDENT(x) ((x) & 0x1FF) +#define P_FUNCT(x) (((x) & 0x3) << 9) +#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3) +#define P_DEFINED 0x8000 +#define P_UNDEF 0x4000 +#define P_MAYSHARE 0x2000 +#define P_DONTCARE 0x1000 + +#ifndef CONFIG_BFIN_GPIO_TRACK +#define peripheral_request(per, label) peripheral_request(per) +#define peripheral_request_list(per, label) peripheral_request_list(per) +#endif + +int peripheral_request(unsigned short per, const char *label); +void peripheral_free(unsigned short per); +int peripheral_request_list(const unsigned short per[], const char *label); +void peripheral_free_list(const unsigned short per[]); + +#include <asm/blackfin.h> + +#ifndef P_SPORT2_TFS +#define P_SPORT2_TFS P_UNDEF +#endif + +#ifndef P_SPORT2_DTSEC +#define P_SPORT2_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT2_DTPRI +#define P_SPORT2_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT2_TSCLK +#define P_SPORT2_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT2_RFS +#define P_SPORT2_RFS P_UNDEF +#endif + +#ifndef P_SPORT2_DRSEC +#define P_SPORT2_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT2_DRPRI +#define P_SPORT2_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT2_RSCLK +#define P_SPORT2_RSCLK P_UNDEF +#endif + +#ifndef P_SPORT3_TFS +#define P_SPORT3_TFS P_UNDEF +#endif + +#ifndef P_SPORT3_DTSEC +#define P_SPORT3_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT3_DTPRI +#define P_SPORT3_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT3_TSCLK +#define P_SPORT3_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT3_RFS +#define P_SPORT3_RFS P_UNDEF +#endif + +#ifndef P_SPORT3_DRSEC +#define P_SPORT3_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT3_DRPRI +#define P_SPORT3_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT3_RSCLK +#define P_SPORT3_RSCLK P_UNDEF +#endif + +#ifndef P_TMR4 +#define P_TMR4 P_UNDEF +#endif + +#ifndef P_TMR5 +#define P_TMR5 P_UNDEF +#endif + +#ifndef P_TMR6 +#define P_TMR6 P_UNDEF +#endif + +#ifndef P_TMR7 +#define P_TMR7 P_UNDEF +#endif + +#ifndef P_TWI1_SCL +#define P_TWI1_SCL P_UNDEF +#endif + +#ifndef P_TWI1_SDA +#define P_TWI1_SDA P_UNDEF +#endif + +#ifndef P_UART3_RTS +#define P_UART3_RTS P_UNDEF +#endif + +#ifndef P_UART3_CTS +#define P_UART3_CTS P_UNDEF +#endif + +#ifndef P_UART2_TX +#define P_UART2_TX P_UNDEF +#endif + +#ifndef P_UART2_RX +#define P_UART2_RX P_UNDEF +#endif + +#ifndef P_UART3_TX +#define P_UART3_TX P_UNDEF +#endif + +#ifndef P_UART3_RX +#define P_UART3_RX P_UNDEF +#endif + +#ifndef P_SPI2_SS +#define P_SPI2_SS P_UNDEF +#endif + +#ifndef P_SPI2_SSEL1 +#define P_SPI2_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL2 +#define P_SPI2_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL3 +#define P_SPI2_SSEL3 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL4 +#define P_SPI2_SSEL4 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL5 +#define P_SPI2_SSEL5 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL6 +#define P_SPI2_SSEL6 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL7 +#define P_SPI2_SSEL7 P_UNDEF +#endif + +#ifndef P_SPI2_SCK +#define P_SPI2_SCK P_UNDEF +#endif + +#ifndef P_SPI2_MOSI +#define P_SPI2_MOSI P_UNDEF +#endif + +#ifndef P_SPI2_MISO +#define P_SPI2_MISO P_UNDEF +#endif + +#ifndef P_TMR0 +#define P_TMR0 P_UNDEF +#endif + +#ifndef P_TMR1 +#define P_TMR1 P_UNDEF +#endif + +#ifndef P_TMR2 +#define P_TMR2 P_UNDEF +#endif + +#ifndef P_TMR3 +#define P_TMR3 P_UNDEF +#endif + +#ifndef P_SPORT0_TFS +#define P_SPORT0_TFS P_UNDEF +#endif + +#ifndef P_SPORT0_DTSEC +#define P_SPORT0_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT0_DTPRI +#define P_SPORT0_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT0_TSCLK +#define P_SPORT0_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT0_RFS +#define P_SPORT0_RFS P_UNDEF +#endif + +#ifndef P_SPORT0_DRSEC +#define P_SPORT0_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT0_DRPRI +#define P_SPORT0_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT0_RSCLK +#define P_SPORT0_RSCLK P_UNDEF +#endif + +#ifndef P_SD_D0 +#define P_SD_D0 P_UNDEF +#endif + +#ifndef P_SD_D1 +#define P_SD_D1 P_UNDEF +#endif + +#ifndef P_SD_D2 +#define P_SD_D2 P_UNDEF +#endif + +#ifndef P_SD_D3 +#define P_SD_D3 P_UNDEF +#endif + +#ifndef P_SD_CLK +#define P_SD_CLK P_UNDEF +#endif + +#ifndef P_SD_CMD +#define P_SD_CMD P_UNDEF +#endif + +#ifndef P_MMCLK +#define P_MMCLK P_UNDEF +#endif + +#ifndef P_MBCLK +#define P_MBCLK P_UNDEF +#endif + +#ifndef P_PPI1_D0 +#define P_PPI1_D0 P_UNDEF +#endif + +#ifndef P_PPI1_D1 +#define P_PPI1_D1 P_UNDEF +#endif + +#ifndef P_PPI1_D2 +#define P_PPI1_D2 P_UNDEF +#endif + +#ifndef P_PPI1_D3 +#define P_PPI1_D3 P_UNDEF +#endif + +#ifndef P_PPI1_D4 +#define P_PPI1_D4 P_UNDEF +#endif + +#ifndef P_PPI1_D5 +#define P_PPI1_D5 P_UNDEF +#endif + +#ifndef P_PPI1_D6 +#define P_PPI1_D6 P_UNDEF +#endif + +#ifndef P_PPI1_D7 +#define P_PPI1_D7 P_UNDEF +#endif + +#ifndef P_PPI1_D8 +#define P_PPI1_D8 P_UNDEF +#endif + +#ifndef P_PPI1_D9 +#define P_PPI1_D9 P_UNDEF +#endif + +#ifndef P_PPI1_D10 +#define P_PPI1_D10 P_UNDEF +#endif + +#ifndef P_PPI1_D11 +#define P_PPI1_D11 P_UNDEF +#endif + +#ifndef P_PPI1_D12 +#define P_PPI1_D12 P_UNDEF +#endif + +#ifndef P_PPI1_D13 +#define P_PPI1_D13 P_UNDEF +#endif + +#ifndef P_PPI1_D14 +#define P_PPI1_D14 P_UNDEF +#endif + +#ifndef P_PPI1_D15 +#define P_PPI1_D15 P_UNDEF +#endif + +#ifndef P_HOST_D8 +#define P_HOST_D8 P_UNDEF +#endif + +#ifndef P_HOST_D9 +#define P_HOST_D9 P_UNDEF +#endif + +#ifndef P_HOST_D10 +#define P_HOST_D10 P_UNDEF +#endif + +#ifndef P_HOST_D11 +#define P_HOST_D11 P_UNDEF +#endif + +#ifndef P_HOST_D12 +#define P_HOST_D12 P_UNDEF +#endif + +#ifndef P_HOST_D13 +#define P_HOST_D13 P_UNDEF +#endif + +#ifndef P_HOST_D14 +#define P_HOST_D14 P_UNDEF +#endif + +#ifndef P_HOST_D15 +#define P_HOST_D15 P_UNDEF +#endif + +#ifndef P_HOST_D0 +#define P_HOST_D0 P_UNDEF +#endif + +#ifndef P_HOST_D1 +#define P_HOST_D1 P_UNDEF +#endif + +#ifndef P_HOST_D2 +#define P_HOST_D2 P_UNDEF +#endif + +#ifndef P_HOST_D3 +#define P_HOST_D3 P_UNDEF +#endif + +#ifndef P_HOST_D4 +#define P_HOST_D4 P_UNDEF +#endif + +#ifndef P_HOST_D5 +#define P_HOST_D5 P_UNDEF +#endif + +#ifndef P_HOST_D6 +#define P_HOST_D6 P_UNDEF +#endif + +#ifndef P_HOST_D7 +#define P_HOST_D7 P_UNDEF +#endif + +#ifndef P_SPORT1_TFS +#define P_SPORT1_TFS P_UNDEF +#endif + +#ifndef P_SPORT1_DTSEC +#define P_SPORT1_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT1_DTPRI +#define P_SPORT1_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT1_TSCLK +#define P_SPORT1_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT1_RFS +#define P_SPORT1_RFS P_UNDEF +#endif + +#ifndef P_SPORT1_DRSEC +#define P_SPORT1_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT1_DRPRI +#define P_SPORT1_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT1_RSCLK +#define P_SPORT1_RSCLK P_UNDEF +#endif + +#ifndef P_PPI2_D0 +#define P_PPI2_D0 P_UNDEF +#endif + +#ifndef P_PPI2_D1 +#define P_PPI2_D1 P_UNDEF +#endif + +#ifndef P_PPI2_D2 +#define P_PPI2_D2 P_UNDEF +#endif + +#ifndef P_PPI2_D3 +#define P_PPI2_D3 P_UNDEF +#endif + +#ifndef P_PPI2_D4 +#define P_PPI2_D4 P_UNDEF +#endif + +#ifndef P_PPI2_D5 +#define P_PPI2_D5 P_UNDEF +#endif + +#ifndef P_PPI2_D6 +#define P_PPI2_D6 P_UNDEF +#endif + +#ifndef P_PPI2_D7 +#define P_PPI2_D7 P_UNDEF +#endif + +#ifndef P_PPI0_D18 +#define P_PPI0_D18 P_UNDEF +#endif + +#ifndef P_PPI0_D19 +#define P_PPI0_D19 P_UNDEF +#endif + +#ifndef P_PPI0_D20 +#define P_PPI0_D20 P_UNDEF +#endif + +#ifndef P_PPI0_D21 +#define P_PPI0_D21 P_UNDEF +#endif + +#ifndef P_PPI0_D22 +#define P_PPI0_D22 P_UNDEF +#endif + +#ifndef P_PPI0_D23 +#define P_PPI0_D23 P_UNDEF +#endif + +#ifndef P_KEY_ROW0 +#define P_KEY_ROW0 P_UNDEF +#endif + +#ifndef P_KEY_ROW1 +#define P_KEY_ROW1 P_UNDEF +#endif + +#ifndef P_KEY_ROW2 +#define P_KEY_ROW2 P_UNDEF +#endif + +#ifndef P_KEY_ROW3 +#define P_KEY_ROW3 P_UNDEF +#endif + +#ifndef P_KEY_COL0 +#define P_KEY_COL0 P_UNDEF +#endif + +#ifndef P_KEY_COL1 +#define P_KEY_COL1 P_UNDEF +#endif + +#ifndef P_KEY_COL2 +#define P_KEY_COL2 P_UNDEF +#endif + +#ifndef P_KEY_COL3 +#define P_KEY_COL3 P_UNDEF +#endif + +#ifndef P_SPI0_SCK +#define P_SPI0_SCK P_UNDEF +#endif + +#ifndef P_SPI0_MISO +#define P_SPI0_MISO P_UNDEF +#endif + +#ifndef P_SPI0_MOSI +#define P_SPI0_MOSI P_UNDEF +#endif + +#ifndef P_SPI0_SS +#define P_SPI0_SS P_UNDEF +#endif + +#ifndef P_SPI0_SSEL1 +#define P_SPI0_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL2 +#define P_SPI0_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL3 +#define P_SPI0_SSEL3 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL4 +#define P_SPI0_SSEL4 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL5 +#define P_SPI0_SSEL5 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL6 +#define P_SPI0_SSEL6 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL7 +#define P_SPI0_SSEL7 P_UNDEF +#endif + +#ifndef P_UART0_TX +#define P_UART0_TX P_UNDEF +#endif + +#ifndef P_UART0_RX +#define P_UART0_RX P_UNDEF +#endif + +#ifndef P_UART1_RTS +#define P_UART1_RTS P_UNDEF +#endif + +#ifndef P_UART1_CTS +#define P_UART1_CTS P_UNDEF +#endif + +#ifndef P_PPI1_CLK +#define P_PPI1_CLK P_UNDEF +#endif + +#ifndef P_PPI1_FS1 +#define P_PPI1_FS1 P_UNDEF +#endif + +#ifndef P_PPI1_FS2 +#define P_PPI1_FS2 P_UNDEF +#endif + +#ifndef P_TWI0_SCL +#define P_TWI0_SCL P_UNDEF +#endif + +#ifndef P_TWI0_SDA +#define P_TWI0_SDA P_UNDEF +#endif + +#ifndef P_KEY_COL7 +#define P_KEY_COL7 P_UNDEF +#endif + +#ifndef P_KEY_ROW6 +#define P_KEY_ROW6 P_UNDEF +#endif + +#ifndef P_KEY_COL6 +#define P_KEY_COL6 P_UNDEF +#endif + +#ifndef P_KEY_ROW5 +#define P_KEY_ROW5 P_UNDEF +#endif + +#ifndef P_KEY_COL5 +#define P_KEY_COL5 P_UNDEF +#endif + +#ifndef P_KEY_ROW4 +#define P_KEY_ROW4 P_UNDEF +#endif + +#ifndef P_KEY_COL4 +#define P_KEY_COL4 P_UNDEF +#endif + +#ifndef P_KEY_ROW7 +#define P_KEY_ROW7 P_UNDEF +#endif + +#ifndef P_PPI0_D0 +#define P_PPI0_D0 P_UNDEF +#endif + +#ifndef P_PPI0_D1 +#define P_PPI0_D1 P_UNDEF +#endif + +#ifndef P_PPI0_D2 +#define P_PPI0_D2 P_UNDEF +#endif + +#ifndef P_PPI0_D3 +#define P_PPI0_D3 P_UNDEF +#endif + +#ifndef P_PPI0_D4 +#define P_PPI0_D4 P_UNDEF +#endif + +#ifndef P_PPI0_D5 +#define P_PPI0_D5 P_UNDEF +#endif + +#ifndef P_PPI0_D6 +#define P_PPI0_D6 P_UNDEF +#endif + +#ifndef P_PPI0_D7 +#define P_PPI0_D7 P_UNDEF +#endif + +#ifndef P_PPI0_D8 +#define P_PPI0_D8 P_UNDEF +#endif + +#ifndef P_PPI0_D9 +#define P_PPI0_D9 P_UNDEF +#endif + +#ifndef P_PPI0_D10 +#define P_PPI0_D10 P_UNDEF +#endif + +#ifndef P_PPI0_D11 +#define P_PPI0_D11 P_UNDEF +#endif + +#ifndef P_PPI0_D12 +#define P_PPI0_D12 P_UNDEF +#endif + +#ifndef P_PPI0_D13 +#define P_PPI0_D13 P_UNDEF +#endif + +#ifndef P_PPI0_D14 +#define P_PPI0_D14 P_UNDEF +#endif + +#ifndef P_PPI0_D15 +#define P_PPI0_D15 P_UNDEF +#endif + +#ifndef P_ATAPI_D0A +#define P_ATAPI_D0A P_UNDEF +#endif + +#ifndef P_ATAPI_D1A +#define P_ATAPI_D1A P_UNDEF +#endif + +#ifndef P_ATAPI_D2A +#define P_ATAPI_D2A P_UNDEF +#endif + +#ifndef P_ATAPI_D3A +#define P_ATAPI_D3A P_UNDEF +#endif + +#ifndef P_ATAPI_D4A +#define P_ATAPI_D4A P_UNDEF +#endif + +#ifndef P_ATAPI_D5A +#define P_ATAPI_D5A P_UNDEF +#endif + +#ifndef P_ATAPI_D6A +#define P_ATAPI_D6A P_UNDEF +#endif + +#ifndef P_ATAPI_D7A +#define P_ATAPI_D7A P_UNDEF +#endif + +#ifndef P_ATAPI_D8A +#define P_ATAPI_D8A P_UNDEF +#endif + +#ifndef P_ATAPI_D9A +#define P_ATAPI_D9A P_UNDEF +#endif + +#ifndef P_ATAPI_D10A +#define P_ATAPI_D10A P_UNDEF +#endif + +#ifndef P_ATAPI_D11A +#define P_ATAPI_D11A P_UNDEF +#endif + +#ifndef P_ATAPI_D12A +#define P_ATAPI_D12A P_UNDEF +#endif + +#ifndef P_ATAPI_D13A +#define P_ATAPI_D13A P_UNDEF +#endif + +#ifndef P_ATAPI_D14A +#define P_ATAPI_D14A P_UNDEF +#endif + +#ifndef P_ATAPI_D15A +#define P_ATAPI_D15A P_UNDEF +#endif + +#ifndef P_PPI0_CLK +#define P_PPI0_CLK P_UNDEF +#endif + +#ifndef P_PPI0_FS1 +#define P_PPI0_FS1 P_UNDEF +#endif + +#ifndef P_PPI0_FS2 +#define P_PPI0_FS2 P_UNDEF +#endif + +#ifndef P_PPI0_D16 +#define P_PPI0_D16 P_UNDEF +#endif + +#ifndef P_PPI0_D17 +#define P_PPI0_D17 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL1 +#define P_SPI1_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL2 +#define P_SPI1_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL3 +#define P_SPI1_SSEL3 P_UNDEF +#endif + + +#ifndef P_SPI1_SSEL4 +#define P_SPI1_SSEL4 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL5 +#define P_SPI1_SSEL5 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL6 +#define P_SPI1_SSEL6 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL7 +#define P_SPI1_SSEL7 P_UNDEF +#endif + +#ifndef P_SPI1_SCK +#define P_SPI1_SCK P_UNDEF +#endif + +#ifndef P_SPI1_MISO +#define P_SPI1_MISO P_UNDEF +#endif + +#ifndef P_SPI1_MOSI +#define P_SPI1_MOSI P_UNDEF +#endif + +#ifndef P_SPI1_SS +#define P_SPI1_SS P_UNDEF +#endif + +#ifndef P_CAN0_TX +#define P_CAN0_TX P_UNDEF +#endif + +#ifndef P_CAN0_RX +#define P_CAN0_RX P_UNDEF +#endif + +#ifndef P_CAN1_TX +#define P_CAN1_TX P_UNDEF +#endif + +#ifndef P_CAN1_RX +#define P_CAN1_RX P_UNDEF +#endif + +#ifndef P_ATAPI_A0A +#define P_ATAPI_A0A P_UNDEF +#endif + +#ifndef P_ATAPI_A1A +#define P_ATAPI_A1A P_UNDEF +#endif + +#ifndef P_ATAPI_A2A +#define P_ATAPI_A2A P_UNDEF +#endif + +#ifndef P_HOST_CE +#define P_HOST_CE P_UNDEF +#endif + +#ifndef P_HOST_RD +#define P_HOST_RD P_UNDEF +#endif + +#ifndef P_HOST_WR +#define P_HOST_WR P_UNDEF +#endif + +#ifndef P_MTXONB +#define P_MTXONB P_UNDEF +#endif + +#ifndef P_PPI2_FS2 +#define P_PPI2_FS2 P_UNDEF +#endif + +#ifndef P_PPI2_FS1 +#define P_PPI2_FS1 P_UNDEF +#endif + +#ifndef P_PPI2_CLK +#define P_PPI2_CLK P_UNDEF +#endif + +#ifndef P_CNT_CZM +#define P_CNT_CZM P_UNDEF +#endif + +#ifndef P_UART1_TX +#define P_UART1_TX P_UNDEF +#endif + +#ifndef P_UART1_RX +#define P_UART1_RX P_UNDEF +#endif + +#ifndef P_ATAPI_RESET +#define P_ATAPI_RESET P_UNDEF +#endif + +#ifndef P_HOST_ADDR +#define P_HOST_ADDR P_UNDEF +#endif + +#ifndef P_HOST_ACK +#define P_HOST_ACK P_UNDEF +#endif + +#ifndef P_MTX +#define P_MTX P_UNDEF +#endif + +#ifndef P_MRX +#define P_MRX P_UNDEF +#endif + +#ifndef P_MRXONB +#define P_MRXONB P_UNDEF +#endif + +#ifndef P_A4 +#define P_A4 P_UNDEF +#endif + +#ifndef P_A5 +#define P_A5 P_UNDEF +#endif + +#ifndef P_A6 +#define P_A6 P_UNDEF +#endif + +#ifndef P_A7 +#define P_A7 P_UNDEF +#endif + +#ifndef P_A8 +#define P_A8 P_UNDEF +#endif + +#ifndef P_A9 +#define P_A9 P_UNDEF +#endif + +#ifndef P_PPI1_FS3 +#define P_PPI1_FS3 P_UNDEF +#endif + +#ifndef P_PPI2_FS3 +#define P_PPI2_FS3 P_UNDEF +#endif + +#ifndef P_TMR8 +#define P_TMR8 P_UNDEF +#endif + +#ifndef P_TMR9 +#define P_TMR9 P_UNDEF +#endif + +#ifndef P_TMR10 +#define P_TMR10 P_UNDEF +#endif +#ifndef P_TMR11 +#define P_TMR11 P_UNDEF +#endif + +#ifndef P_DMAR0 +#define P_DMAR0 P_UNDEF +#endif + +#ifndef P_DMAR1 +#define P_DMAR1 P_UNDEF +#endif + +#ifndef P_PPI0_FS3 +#define P_PPI0_FS3 P_UNDEF +#endif + +#ifndef P_CNT_CDG +#define P_CNT_CDG P_UNDEF +#endif + +#ifndef P_CNT_CUD +#define P_CNT_CUD P_UNDEF +#endif + +#ifndef P_A10 +#define P_A10 P_UNDEF +#endif + +#ifndef P_A11 +#define P_A11 P_UNDEF +#endif + +#ifndef P_A12 +#define P_A12 P_UNDEF +#endif + +#ifndef P_A13 +#define P_A13 P_UNDEF +#endif + +#ifndef P_A14 +#define P_A14 P_UNDEF +#endif + +#ifndef P_A15 +#define P_A15 P_UNDEF +#endif + +#ifndef P_A16 +#define P_A16 P_UNDEF +#endif + +#ifndef P_A17 +#define P_A17 P_UNDEF +#endif + +#ifndef P_A18 +#define P_A18 P_UNDEF +#endif + +#ifndef P_A19 +#define P_A19 P_UNDEF +#endif + +#ifndef P_A20 +#define P_A20 P_UNDEF +#endif + +#ifndef P_A21 +#define P_A21 P_UNDEF +#endif + +#ifndef P_A22 +#define P_A22 P_UNDEF +#endif + +#ifndef P_A23 +#define P_A23 P_UNDEF +#endif + +#ifndef P_A24 +#define P_A24 P_UNDEF +#endif + +#ifndef P_A25 +#define P_A25 P_UNDEF +#endif + +#ifndef P_NOR_CLK +#define P_NOR_CLK P_UNDEF +#endif + +#ifndef P_TMRCLK +#define P_TMRCLK P_UNDEF +#endif + +#ifndef P_AMC_ARDY_NOR_WAIT +#define P_AMC_ARDY_NOR_WAIT P_UNDEF +#endif + +#ifndef P_NAND_CE +#define P_NAND_CE P_UNDEF +#endif + +#ifndef P_NAND_RB +#define P_NAND_RB P_UNDEF +#endif + +#ifndef P_ATAPI_DIOR +#define P_ATAPI_DIOR P_UNDEF +#endif + +#ifndef P_ATAPI_DIOW +#define P_ATAPI_DIOW P_UNDEF +#endif + +#ifndef P_ATAPI_CS0 +#define P_ATAPI_CS0 P_UNDEF +#endif + +#ifndef P_ATAPI_CS1 +#define P_ATAPI_CS1 P_UNDEF +#endif + +#ifndef P_ATAPI_DMACK +#define P_ATAPI_DMACK P_UNDEF +#endif + +#ifndef P_ATAPI_DMARQ +#define P_ATAPI_DMARQ P_UNDEF +#endif + +#ifndef P_ATAPI_INTRQ +#define P_ATAPI_INTRQ P_UNDEF +#endif + +#ifndef P_ATAPI_IORDY +#define P_ATAPI_IORDY P_UNDEF +#endif + +#ifndef P_AMC_BR +#define P_AMC_BR P_UNDEF +#endif + +#ifndef P_AMC_BG +#define P_AMC_BG P_UNDEF +#endif + +#ifndef P_AMC_BGH +#define P_AMC_BGH P_UNDEF +#endif + +/* EMAC */ + +#ifndef P_MII0_ETxD0 +#define P_MII0_ETxD0 P_UNDEF +#endif + +#ifndef P_MII0_ETxD1 +#define P_MII0_ETxD1 P_UNDEF +#endif + +#ifndef P_MII0_ETxD2 +#define P_MII0_ETxD2 P_UNDEF +#endif + +#ifndef P_MII0_ETxD3 +#define P_MII0_ETxD3 P_UNDEF +#endif + +#ifndef P_MII0_ETxEN +#define P_MII0_ETxEN P_UNDEF +#endif + +#ifndef P_MII0_TxCLK +#define P_MII0_TxCLK P_UNDEF +#endif + +#ifndef P_MII0_PHYINT +#define P_MII0_PHYINT P_UNDEF +#endif + +#ifndef P_MII0_COL +#define P_MII0_COL P_UNDEF +#endif + +#ifndef P_MII0_ERxD0 +#define P_MII0_ERxD0 P_UNDEF +#endif + +#ifndef P_MII0_ERxD1 +#define P_MII0_ERxD1 P_UNDEF +#endif + +#ifndef P_MII0_ERxD2 +#define P_MII0_ERxD2 P_UNDEF +#endif + +#ifndef P_MII0_ERxD3 +#define P_MII0_ERxD3 P_UNDEF +#endif + +#ifndef P_MII0_ERxDV +#define P_MII0_ERxDV P_UNDEF +#endif + +#ifndef P_MII0_ERxCLK +#define P_MII0_ERxCLK P_UNDEF +#endif + +#ifndef P_MII0_ERxER +#define P_MII0_ERxER P_UNDEF +#endif + +#ifndef P_MII0_CRS +#define P_MII0_CRS P_UNDEF +#endif + +#ifndef P_RMII0_REF_CLK +#define P_RMII0_REF_CLK P_UNDEF +#endif + +#ifndef P_RMII0_MDINT +#define P_RMII0_MDINT P_UNDEF +#endif + +#ifndef P_RMII0_CRS_DV +#define P_RMII0_CRS_DV P_UNDEF +#endif + +#ifndef P_MDC +#define P_MDC P_UNDEF +#endif + +#ifndef P_MDIO +#define P_MDIO P_UNDEF +#endif + +#endif /* _PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h index 6bc7208..952438e 100644 --- a/arch/blackfin/include/asm/system.h +++ b/arch/blackfin/include/asm/system.h @@ -118,4 +118,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, return tmp; } +void bfin_reset_boot_spi_cs(unsigned short pin); + #endif /* _BLACKFIN_SYSTEM_H */ diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c index 85b350f..ff1ac4c 100644 --- a/board/bf518f-ezbrd/bf518f-ezbrd.c +++ b/board/bf518f-ezbrd/bf518f-ezbrd.c @@ -14,6 +14,7 @@ #include <spi.h> #include <asm/blackfin.h> #include <asm/net.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/otp.h> #include <asm/sdh.h> @@ -61,6 +62,7 @@ static void board_init_enetaddr(uchar *mac_addr) #define KSZ_WRITE 0x02 #define KSZ_READ 0x03 +#define KSZ_REG_CHID 0x00 /* Register 0: Chip ID0 */ #define KSZ_REG_STPID 0x01 /* Register 1: Chip ID1 / Start Switch */ #define KSZ_REG_GC9 0x0b /* Register 11: Global Control 9 */ #define KSZ_REG_P3C0 0x30 /* Register 48: Port 3 Control 0 */ @@ -78,15 +80,17 @@ static int ksz8893m_reg_set(struct spi_slave *slave, uchar reg, uchar data) return ksz8893m_transfer(slave, KSZ_WRITE, reg, data, din); } -static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask) +static int ksz8893m_reg_read(struct spi_slave *slave, uchar reg) { - int ret = 0; + int ret; unsigned char din[3]; + ret = ksz8893m_transfer(slave, KSZ_READ, reg, 0, din); + return ret ? ret : din[2]; +} - ret |= ksz8893m_transfer(slave, KSZ_READ, reg, 0, din); - ret |= ksz8893m_reg_set(slave, reg, din[2] & mask); - - return ret; +static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask) +{ + return ksz8893m_reg_set(slave, reg, ksz8893m_reg_read(slave, reg) & mask); } static int ksz8893m_reset(struct spi_slave *slave) @@ -107,16 +111,16 @@ static int ksz8893m_reset(struct spi_slave *slave) int board_eth_init(bd_t *bis) { - static bool switch_is_alive = false; + static bool switch_is_alive = false, phy_is_ksz = true; int ret; if (!switch_is_alive) { struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, SPI_MODE_3); if (slave) { if (!spi_claim_bus(slave)) { - ret = ksz8893m_reset(slave); - if (!ret) - switch_is_alive = true; + phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88); + ret = phy_is_ksz ? ksz8893m_reset(slave) : 0; + switch_is_alive = (ret == 0); spi_release_bus(slave); } spi_free_slave(slave); @@ -143,18 +147,11 @@ int misc_init_r(void) int board_early_init_f(void) { -#if !defined(CONFIG_SYS_NO_FLASH) - /* setup BF518-EZBRD GPIO pin PG11 to AMS2. */ - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG11); - -# if !defined(CONFIG_BFIN_SPI) - /* setup BF518-EZBRD GPIO pin PG15 to AMS3. */ - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_7_MASK) | PORT_x_MUX_7_FUNC_3); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG15); -# endif -#endif - return 0; + /* connect async banks by default */ + const unsigned short pins[] = { + P_AMS2, P_AMS3, 0, + }; + return peripheral_request_list(pins, "async"); } #ifdef CONFIG_BFIN_SDH diff --git a/board/bf526-ezbrd/Makefile b/board/bf526-ezbrd/Makefile index a9ff760..f2bd2c2 100644 --- a/board/bf526-ezbrd/Makefile +++ b/board/bf526-ezbrd/Makefile @@ -30,7 +30,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS-y := $(BOARD).o -COBJS-$(CONFIG_STATUS_LED) += status-led.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/bf526-ezbrd/status-led.c b/board/bf526-ezbrd/status-led.c deleted file mode 100644 index 6327022..0000000 --- a/board/bf526-ezbrd/status-led.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * U-boot - status leds - * - * Copyright (c) 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <config.h> -#include <command.h> -#include <status_led.h> - -static void set_led_f(int pf, int state) -{ - switch (state) { - case STATUS_LED_OFF: bfin_write_PORTFIO_CLEAR(pf); break; - case STATUS_LED_BLINKING: bfin_write_PORTFIO_TOGGLE(pf); break; - case STATUS_LED_ON: bfin_write_PORTFIO_SET(pf); break; - } -} -static void set_led_g(int pf, int state) -{ - switch (state) { - case STATUS_LED_OFF: bfin_write_PORTGIO_CLEAR(pf); break; - case STATUS_LED_BLINKING: bfin_write_PORTGIO_TOGGLE(pf); break; - case STATUS_LED_ON: bfin_write_PORTGIO_SET(pf); break; - } -} - -static void set_leds(led_id_t mask, int state) -{ - if (mask & 0x1) set_led_f(PF8, state); - if (mask & 0x2) set_led_g(PG11, state); - if (mask & 0x4) set_led_g(PG12, state); -} - -void __led_init(led_id_t mask, int state) -{ - bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~(PF8)); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~(PG11 | PG12)); - bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() & ~(PF8)); - bfin_write_PORTGIO_INEN(bfin_read_PORTGIO_INEN() & ~(PG11 | PG12)); - bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (PF8)); - bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | (PG11 | PG12)); -} - -void __led_set(led_id_t mask, int state) -{ - set_leds(mask, state); -} - -void __led_toggle(led_id_t mask) -{ - set_leds(mask, STATUS_LED_BLINKING); -} diff --git a/board/bf527-ad7160-eval/Makefile b/board/bf527-ad7160-eval/Makefile new file mode 100644 index 0000000..f2bd2c2 --- /dev/null +++ b/board/bf527-ad7160-eval/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bf527-ad7160-eval/bf527-ad7160-eval.c b/board/bf527-ad7160-eval/bf527-ad7160-eval.c new file mode 100644 index 0000000..b06d5ab --- /dev/null +++ b/board/bf527-ad7160-eval/bf527-ad7160-eval.c @@ -0,0 +1,25 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <asm/blackfin.h> +#include <asm/mach-common/bits/pll.h> + +int checkboard(void) +{ + printf("Board: ADI BF527 AD7160-EVAL board\n"); + printf(" Support: http://blackfin.uclinux.org/\n"); + return 0; +} + +int misc_init_r(void) +{ + /* CLKIN Buffer Output Enable */ + *pVR_CTL |= CLKBUFOE; + return 0; +} diff --git a/board/bf527-ad7160-eval/config.mk b/board/bf527-ad7160-eval/config.mk new file mode 100644 index 0000000..f85bef5 --- /dev/null +++ b/board/bf527-ad7160-eval/config.mk @@ -0,0 +1,33 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c index a911880..211cf24 100644 --- a/board/bf527-ezkit/bf527-ezkit.c +++ b/board/bf527-ezkit/bf527-ezkit.c @@ -12,6 +12,7 @@ #include <net.h> #include <netdev.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/net.h> #include <asm/mach-common/bits/otp.h> @@ -75,9 +76,7 @@ void board_musb_init(void) /* * BF527 EZ-KITs require PG13 to be high for HOST mode */ - bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~PG13); - bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | PG13); - bfin_write_PORTGIO_SET(PG13); - SSYNC(); + gpio_request(GPIO_PG13, "musb-vbus"); + gpio_direction_output(GPIO_PG13, 1); } #endif diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c index 8f6ea23..891070b 100644 --- a/board/bf527-ezkit/video.c +++ b/board/bf527-ezkit/video.c @@ -11,6 +11,7 @@ #include <config.h> #include <malloc.h> #include <asm/blackfin.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/dma.h> #include <spi.h> #include <linux/types.h> @@ -171,13 +172,11 @@ void DisablePPI(void) void Init_Ports(void) { - *pPORTF_MUX &= ~PORT_x_MUX_0_MASK; - *pPORTF_MUX |= PORT_x_MUX_0_FUNC_1; - *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7; - - *pPORTG_MUX &= ~PORT_x_MUX_1_MASK; - *pPORTG_MUX |= PORT_x_MUX_1_FUNC_1; - *pPORTG_FER |= PG5; + const unsigned short pins[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4, + P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_FS2, 0, + }; + peripheral_request_list(pins, "lcd"); } void Init_PPI(void) diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index 4abad08..935aad2 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -27,8 +27,7 @@ #include <common.h> #include <netdev.h> -#include <asm/io.h> -#include "bf533-stamp.h" +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -46,15 +45,10 @@ int checkboard(void) */ void swap_to(int device_id) { - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); - SSYNC(); - bfin_write_FIO_FLAG_C(PF1); - if (device_id == ETHERNET) - bfin_write_FIO_FLAG_S(PF0); - else if (device_id == FLASH) - bfin_write_FIO_FLAG_C(PF0); - else - printf("Unknown device to switch\n"); + gpio_request(GPIO_PF0, "eth_flash_swap"); + gpio_request(GPIO_PF1, "eth_flash_swap"); + gpio_direction_output(GPIO_PF0, device_id == ETHERNET); + gpio_direction_output(GPIO_PF1, 0); SSYNC(); } @@ -75,24 +69,23 @@ int misc_init_r(void) #define STATUS_LED_OFF 0 #define STATUS_LED_ON 1 +static int gpio_setup; + static void stamp_led_set(int LED1, int LED2, int LED3) { - bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4)); - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4)); - - if (LED1 == STATUS_LED_OFF) - *pFIO_FLAG_S = PF2; - else - *pFIO_FLAG_C = PF2; - if (LED2 == STATUS_LED_OFF) - *pFIO_FLAG_S = PF3; - else - *pFIO_FLAG_C = PF3; - if (LED3 == STATUS_LED_OFF) - *pFIO_FLAG_S = PF4; - else - *pFIO_FLAG_C = PF4; - SSYNC(); + if (!gpio_setup) { + gpio_request(GPIO_PF2, "boot_progress"); + gpio_request(GPIO_PF3, "boot_progress"); + gpio_request(GPIO_PF4, "boot_progress"); + gpio_direction_output(GPIO_PF2, LED1); + gpio_direction_output(GPIO_PF3, LED2); + gpio_direction_output(GPIO_PF4, LED3); + gpio_setup = 1; + } else { + gpio_set_value(GPIO_PF2, LED1); + gpio_set_value(GPIO_PF3, LED2); + gpio_set_value(GPIO_PF4, LED3); + } } void show_boot_progress(int status) @@ -134,43 +127,6 @@ void show_boot_progress(int status) } #endif -#ifdef CONFIG_STATUS_LED -#include <status_led.h> - -static void set_led(int pf, int state) -{ - switch (state) { - case STATUS_LED_OFF: bfin_write_FIO_FLAG_S(pf); break; - case STATUS_LED_BLINKING: bfin_write_FIO_FLAG_T(pf); break; - case STATUS_LED_ON: bfin_write_FIO_FLAG_C(pf); break; - } -} - -static void set_leds(led_id_t mask, int state) -{ - if (mask & 0x1) set_led(PF2, state); - if (mask & 0x2) set_led(PF3, state); - if (mask & 0x4) set_led(PF4, state); -} - -void __led_init(led_id_t mask, int state) -{ - bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4)); - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4)); -} - -void __led_set(led_id_t mask, int state) -{ - set_leds(mask, state); -} - -void __led_toggle(led_id_t mask) -{ - set_leds(mask, STATUS_LED_BLINKING); -} - -#endif - #ifdef CONFIG_SMC91111 int board_eth_init(bd_t *bis) { diff --git a/board/bf533-stamp/bf533-stamp.h b/board/bf533-stamp/bf533-stamp.h deleted file mode 100644 index ebd39c7..0000000 --- a/board/bf533-stamp/bf533-stamp.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * U-boot - stamp.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __STAMP_H__ -#define __STAMP_H__ - -extern void init_Flags(void); - -extern volatile unsigned long *ambctl0; -extern volatile unsigned long *ambctl1; -extern volatile unsigned long *amgctl; - -/* Definitions used in Compact Flash Boot support */ -#define FIO_EDGE_CF_BITS 0x0000 -#define FIO_POLAR_CF_BITS 0x0000 -#define FIO_EDGE_BITS 0x1E0 -#define FIO_POLAR_BITS 0x160 - -/* Compact flash status bits in status register */ -#define CF_STAT_BITS 0x00000060 - -/* CF Flags used to switch between expansion and external - * memory banks - */ -#define CF_PF0 0x0001 -#define CF_PF1 0x0002 -#define CF_PF1_PF0 0x0003 - -#endif diff --git a/board/bf533-stamp/ide-cf.c b/board/bf533-stamp/ide-cf.c index 23e786b..3e4080e 100644 --- a/board/bf533-stamp/ide-cf.c +++ b/board/bf533-stamp/ide-cf.c @@ -11,7 +11,6 @@ #include <common.h> #include <config.h> #include <asm/blackfin.h> -#include "bf533-stamp.h" void cf_outb(unsigned char val, volatile unsigned char *addr) { @@ -66,6 +65,15 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) swap_to(FLASH); } +/* Definitions used in Compact Flash Boot support */ +#define FIO_EDGE_CF_BITS 0x0000 +#define FIO_POLAR_CF_BITS 0x0000 +#define FIO_EDGE_BITS 0x1E0 +#define FIO_POLAR_BITS 0x160 + +/* Compact flash status bits in status register */ +#define CF_STAT_BITS 0x00000060 + void cf_ide_init(void) { int i, cf_stat; diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile index f728e2c..4f8985b 100644 --- a/board/bf537-stamp/Makefile +++ b/board/bf537-stamp/Makefile @@ -29,9 +29,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o cmd_bf537led.o +COBJS-y := $(BOARD).o COBJS-$(CONFIG_BFIN_IDE) += ide-cf.o -COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o COBJS-$(CONFIG_POST) += post.o post-memory.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 3911be6..ec888d4 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -46,11 +46,8 @@ int checkboard(void) void board_reset(void) { /* workaround for weak pull ups on ssel */ - if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) { - bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10); - bfin_write_PORTFIO_SET(PF10); - udelay(1); - } + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) + bfin_reset_boot_spi_cs(GPIO_PF10); } #ifdef CONFIG_BFIN_MAC diff --git a/board/bf537-stamp/cmd_bf537led.c b/board/bf537-stamp/cmd_bf537led.c deleted file mode 100644 index 7d8f3ea..0000000 --- a/board/bf537-stamp/cmd_bf537led.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * U-boot - cmd_bf537led.c - * - * Copyright (C) 2006 Aaron Gage, Ocean Optics Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <config.h> -#include <command.h> -#include <asm/blackfin.h> -#include <asm/string.h> -#ifdef CONFIG_BF537_STAMP_LEDCMD - -/* Define the command usage in a reusable way */ -#define USAGE_LONG \ - "led <number> <action>\n" \ - " <number> - Index (0-5) of LED to change, or \"all\"\n" \ - " <action> - Must be one of:\n" \ - " on off toggle" - -/* Number of LEDs supported by the board */ -#define NUMBER_LEDS 6 -/* The BF537 stamp has 6 LEDs. This mask indicates that all should be lit. */ -#define LED_ALL_MASK 0x003F - -void show_cmd_usage(void); -void set_led_state(int index, int state); -void configure_GPIO_to_output(int index); - -/* Map of LEDs according to their GPIO ports. This can be rearranged or - * otherwise changed to account for different GPIO configurations. - */ -int led_ports[] = { PF6, PF7, PF8, PF9, PF10, PF11 }; - -#define ACTION_TOGGLE -1 -#define ACTION_OFF 0 -#define ACTION_ON 1 - -#define LED_STATE_OFF 0 -#define LED_STATE_ON 1 - -/* This is a trivial atoi implementation since we don't have one available */ -int atoi(char *string) -{ - int length; - int retval = 0; - int i; - int sign = 1; - - length = strlen(string); - for (i = 0; i < length; i++) { - if (0 == i && string[0] == '-') { - sign = -1; - continue; - } - if (string[i] > '9' || string[i] < '0') { - break; - } - retval *= 10; - retval += string[i] - '0'; - } - retval *= sign; - return retval; -} - -int do_bf537led(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - int led_mask = 0; - int led_current_state = 0; - int action = ACTION_OFF; - int temp; - - if (3 != argc) { - /* Not enough arguments, so just show usage information */ - show_cmd_usage(); - return 1; - } - - if (strcmp(argv[1], "all") == 0) { - led_mask = LED_ALL_MASK; - } else { - temp = atoi(argv[1]); - if (temp < 0 || temp >= NUMBER_LEDS) { - printf("Invalid LED number [%s]\n", argv[1]); - show_cmd_usage(); - return 2; - } - led_mask |= (1 << temp); - } - - if (strcmp(argv[2], "off") == 0) { - action = ACTION_OFF; - } else if (strcmp(argv[2], "on") == 0) { - action = ACTION_ON; - } else if (strcmp(argv[2], "toggle") == 0) { - action = ACTION_TOGGLE; - } else { - printf("Invalid action [%s]\n", argv[2]); - show_cmd_usage(); - return 3; - } - - for (temp = 0; temp < NUMBER_LEDS; temp++) { - if ((led_mask & (1 << temp)) > 0) { - /* - * It is possible that the user has wired one of PF6-PF11 to - * something other than an LED, so this will only change a pin - * to output if the user has indicated a state change. This may - * happen a lot, but this way is safer than just setting all pins - * to output. - */ - configure_GPIO_to_output(temp); - - led_current_state = - ((*pPORTFIO & led_ports[temp]) > - 0) ? LED_STATE_ON : LED_STATE_OFF; - /* - printf("LED state for index %d (%x) is %d\n", temp, led_ports[temp], - led_current_state); - printf("*pPORTFIO is %x\n", *pPORTFIO); - */ - if (ACTION_ON == action - || (ACTION_TOGGLE == action - && 0 == led_current_state)) { - printf("Turning LED %d on\n", temp); - set_led_state(temp, LED_STATE_ON); - } else { - printf("Turning LED %d off\n", temp); - set_led_state(temp, LED_STATE_OFF); - } - } - } - - return 0; -} - -/* - * The GPIO pins that go to the LEDs on the BF537 stamp must be configured - * as output. This function simply configures them that way. This could - * be done to all of the GPIO lines at once, but if a user is using a - * custom board, this will try to be nice and only change the GPIO lines - * that the user specifically names. - */ -void configure_GPIO_to_output(int index) -{ - int port; - - port = led_ports[index]; - - /* Clear the Port F Function Enable Register */ - *pPORTF_FER &= ~port; - /* Set the Port F I/O direction register */ - *pPORTFIO_DIR |= port; - /* Clear the Port F I/O Input Enable Register */ - *pPORTFIO_INEN &= ~port; -} - -/* Enforce the given state on the GPIO line for the indicated LED */ -void set_led_state(int index, int state) -{ - int port; - - port = led_ports[index]; - - if (LED_STATE_OFF == state) { - /* Clear the bit to turn off the LED */ - *pPORTFIO &= ~port; - } else { - /* Set the bit to turn on the LED */ - *pPORTFIO |= port; - } -} - -/* Display usage information */ -void show_cmd_usage() -{ - printf("Usage:\n%s\n", USAGE_LONG); -} - -/* Register information for u-boot to find this command */ -U_BOOT_CMD(led, 3, 1, do_bf537led, - "Control BF537 stamp LEDs", USAGE_LONG); - -#endif diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c deleted file mode 100644 index 7b753ad..0000000 --- a/board/bf537-stamp/spi_flash.c +++ /dev/null @@ -1,996 +0,0 @@ -/* - * SPI flash driver - * - * Enter bugs at http://blackfin.uclinux.org/ - * - * Copyright (c) 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -/* Configuration options: - * CONFIG_SPI_BAUD - value to load into SPI_BAUD (divisor of SCLK to get SPI CLK) - * CONFIG_SPI_FLASH_SLOW_READ - force usage of the slower read - * WARNING: make sure your SCLK + SPI_BAUD is slow enough - */ - -#include <common.h> -#include <malloc.h> -#include <asm/io.h> -#include <asm/mach-common/bits/spi.h> -#include <asm/mach-common/bits/dma.h> - -/* Forcibly phase out these */ -#ifdef CONFIG_SPI_FLASH_NUM_SECTORS -# error do not set CONFIG_SPI_FLASH_NUM_SECTORS -#endif -#ifdef CONFIG_SPI_FLASH_SECTOR_SIZE -# error do not set CONFIG_SPI_FLASH_SECTOR_SIZE -#endif - -#if defined(CONFIG_SPI) - -struct flash_info { - char *name; - uint16_t id; - uint16_t ext_id; - unsigned sector_size; - unsigned num_sectors; -}; - -/* SPI Speeds: 50 MHz / 33 MHz */ -static struct flash_info flash_spansion_serial_flash[] = { - { "S25FL016", 0x0215, 0, 64 * 1024, 32 }, - { "S25FL032", 0x0216, 0, 64 * 1024, 64 }, - { "S25FL064", 0x0217, 0, 64 * 1024, 128 }, - { "S25FL128-00", 0x2018, 0x0301, 64 * 1024, 256 }, /* Package marking FL128PIF */ - { "S25FL128-01", 0x2018, 0x0300, 128 * 1024, 64 }, /* Package marking FL128PIFL */ - { NULL, 0, 0, 0, 0 } -}; - -/* SPI Speeds: 50 MHz / 20 MHz */ -static struct flash_info flash_st_serial_flash[] = { - { "m25p05", 0x2010, 0, 32 * 1024, 2 }, - { "m25p10", 0x2011, 0, 32 * 1024, 4 }, - { "m25p20", 0x2012, 0, 64 * 1024, 4 }, - { "m25p40", 0x2013, 0, 64 * 1024, 8 }, - { "m25p80", 0x20FF, 0, 64 * 1024, 16 }, - { "m25p16", 0x2015, 0, 64 * 1024, 32 }, - { "m25p32", 0x2016, 0, 64 * 1024, 64 }, - { "m25p64", 0x2017, 0, 64 * 1024, 128 }, - { "m25p128", 0x2018, 0, 256 * 1024, 64 }, - { NULL, 0, 0, 0, 0 } -}; - -/* SPI Speeds: 20 MHz / 40 MHz */ -static struct flash_info flash_sst_serial_flash[] = { - { "SST25WF512", 0x2501, 0, 4 * 1024, 128 }, - { "SST25WF010", 0x2502, 0, 4 * 1024, 256 }, - { "SST25WF020", 0x2503, 0, 4 * 1024, 512 }, - { "SST25WF040", 0x2504, 0, 4 * 1024, 1024 }, - { NULL, 0, 0, 0, 0 } -}; - -/* SPI Speeds: 66 MHz / 33 MHz */ -static struct flash_info flash_atmel_dataflash[] = { - { "AT45DB011x", 0x0c, 0, 264, 512 }, - { "AT45DB021x", 0x14, 0, 264, 1025 }, - { "AT45DB041x", 0x1c, 0, 264, 2048 }, - { "AT45DB081x", 0x24, 0, 264, 4096 }, - { "AT45DB161x", 0x2c, 0, 528, 4096 }, - { "AT45DB321x", 0x34, 0, 528, 8192 }, - { "AT45DB642x", 0x3c, 0, 1056, 8192 }, - { NULL, 0, 0, 0, 0 } -}; - -/* SPI Speed: 50 MHz / 25 MHz or 40 MHz / 20 MHz */ -static struct flash_info flash_winbond_serial_flash[] = { - { "W25X10", 0x3011, 0, 16 * 256, 32 }, - { "W25X20", 0x3012, 0, 16 * 256, 64 }, - { "W25X40", 0x3013, 0, 16 * 256, 128 }, - { "W25X80", 0x3014, 0, 16 * 256, 256 }, - { "W25P80", 0x2014, 0, 256 * 256, 16 }, - { "W25P16", 0x2015, 0, 256 * 256, 32 }, - { NULL, 0, 0, 0, 0 } -}; - -struct flash_ops { - uint8_t read, write, erase, status; -}; - -#ifdef CONFIG_SPI_FLASH_SLOW_READ -# define OP_READ 0x03 -#else -# define OP_READ 0x0B -#endif -static struct flash_ops flash_st_ops = { - .read = OP_READ, - .write = 0x02, - .erase = 0xD8, - .status = 0x05, -}; - -static struct flash_ops flash_sst_ops = { - .read = OP_READ, - .write = 0x02, - .erase = 0x20, - .status = 0x05, -}; - -static struct flash_ops flash_atmel_ops = { - .read = OP_READ, - .write = 0x82, - .erase = 0x81, - .status = 0xD7, -}; - -static struct flash_ops flash_winbond_ops = { - .read = OP_READ, - .write = 0x02, - .erase = 0x20, - .status = 0x05, -}; - -struct manufacturer_info { - const char *name; - uint8_t id; - struct flash_info *flashes; - struct flash_ops *ops; -}; - -static struct { - struct manufacturer_info *manufacturer; - struct flash_info *flash; - struct flash_ops *ops; - uint8_t manufacturer_id, device_id1, device_id2, device_extid1, device_extid2; - unsigned int write_length; - unsigned long sector_size, num_sectors; -} flash; - -enum { - JED_MANU_SPANSION = 0x01, - JED_MANU_ST = 0x20, - JED_MANU_SST = 0xBF, - JED_MANU_ATMEL = 0x1F, - JED_MANU_WINBOND = 0xEF, -}; - -static struct manufacturer_info flash_manufacturers[] = { - { - .name = "Spansion", - .id = JED_MANU_SPANSION, - .flashes = flash_spansion_serial_flash, - .ops = &flash_st_ops, - }, - { - .name = "ST", - .id = JED_MANU_ST, - .flashes = flash_st_serial_flash, - .ops = &flash_st_ops, - }, - { - .name = "SST", - .id = JED_MANU_SST, - .flashes = flash_sst_serial_flash, - .ops = &flash_sst_ops, - }, - { - .name = "Atmel", - .id = JED_MANU_ATMEL, - .flashes = flash_atmel_dataflash, - .ops = &flash_atmel_ops, - }, - { - .name = "Winbond", - .id = JED_MANU_WINBOND, - .flashes = flash_winbond_serial_flash, - .ops = &flash_winbond_ops, - }, -}; - -#define TIMEOUT 5000 /* timeout of 5 seconds */ - -/* If part has multiple SPI flashes, assume SPI0 as that is - * the one we can boot off of ... - */ -#ifndef pSPI_CTL -# define pSPI_CTL pSPI0_CTL -# define pSPI_BAUD pSPI0_BAUD -# define pSPI_FLG pSPI0_FLG -# define pSPI_RDBR pSPI0_RDBR -# define pSPI_STAT pSPI0_STAT -# define pSPI_TDBR pSPI0_TDBR -#endif - -/* Default to the SPI SSEL that we boot off of: - * BF54x, BF537, (everything new?): SSEL1 - * BF51x, BF533, BF561: SSEL2 - */ -#ifndef CONFIG_SPI_FLASH_SSEL -# define CONFIG_SPI_FLASH_SSEL BFIN_BOOT_SPI_SSEL -#endif -#define SSEL_MASK (1 << CONFIG_SPI_FLASH_SSEL) - -static void SPI_INIT(void) -{ - /* [#3541] This delay appears to be necessary, but not sure - * exactly why as the history behind it is non-existant. - */ - *pSPI_CTL = 0; - udelay(CONFIG_CCLK_HZ / 25000000); - - /* enable SPI pins: SSEL, MOSI, MISO, SCK */ -#ifdef __ADSPBF54x__ - *pPORTE_FER |= (PE0 | PE1 | PE2 | PE4); -#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) - *pPORTF_FER |= (PF10 | PF11 | PF12 | PF13); -#elif defined(__ADSPBF52x__) - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_3); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG1 | PG2 | PG3 | PG4); -#elif defined(__ADSPBF51x__) - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_7_MASK) | PORT_x_MUX_7_FUNC_1); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG12 | PG13 | PG14 | PG15); -#endif - - /* initate communication upon write of TDBR */ - *pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE); - *pSPI_BAUD = CONFIG_SPI_BAUD; -} - -static void SPI_DEINIT(void) -{ - *pSPI_CTL = 0; - *pSPI_BAUD = 0; - SSYNC(); -} - -static void SPI_ON(void) -{ - /* toggle SSEL to reset the device so it'll take a new command */ - *pSPI_FLG = 0xFF00 | SSEL_MASK; - SSYNC(); - - *pSPI_FLG = ((0xFF & ~SSEL_MASK) << 8) | SSEL_MASK; - SSYNC(); -} - -static void SPI_OFF(void) -{ - /* put SPI settings back to reset state */ - *pSPI_FLG = 0xFF00; - SSYNC(); -} - -static uint8_t spi_write_read_byte(uint8_t transmit) -{ - *pSPI_TDBR = transmit; - SSYNC(); - - while ((*pSPI_STAT & TXS)) - if (ctrlc()) - break; - while (!(*pSPI_STAT & SPIF)) - if (ctrlc()) - break; - while (!(*pSPI_STAT & RXS)) - if (ctrlc()) - break; - - /* Read dummy to empty the receive register */ - return *pSPI_RDBR; -} - -static uint8_t read_status_register(void) -{ - uint8_t status_register; - - /* send instruction to read status register */ - SPI_ON(); - spi_write_read_byte(flash.ops->status); - /* send dummy to receive the status register */ - status_register = spi_write_read_byte(0); - SPI_OFF(); - - return status_register; -} - -static int wait_for_ready_status(void) -{ - ulong start = get_timer(0); - - while (get_timer(0) - start < TIMEOUT) { - switch (flash.manufacturer_id) { - case JED_MANU_SPANSION: - case JED_MANU_ST: - case JED_MANU_SST: - case JED_MANU_WINBOND: - if (!(read_status_register() & 0x01)) - return 0; - break; - - case JED_MANU_ATMEL: - if (read_status_register() & 0x80) - return 0; - break; - } - - if (ctrlc()) { - puts("\nAbort\n"); - return -1; - } - } - - puts("Timeout\n"); - return -1; -} - -static int enable_writing(void) -{ - ulong start; - - if (flash.manufacturer_id == JED_MANU_ATMEL) - return 0; - - /* A write enable instruction must previously have been executed */ - SPI_ON(); - spi_write_read_byte(0x06); - SPI_OFF(); - - /* The status register will be polled to check the write enable latch "WREN" */ - start = get_timer(0); - while (get_timer(0) - start < TIMEOUT) { - if (read_status_register() & 0x02) - return 0; - - if (ctrlc()) { - puts("\nAbort\n"); - return -1; - } - } - - puts("Timeout\n"); - return -1; -} - -static void write_status_register(uint8_t val) -{ - if (flash.manufacturer_id != JED_MANU_SST) - hang(); - - if (enable_writing()) - return; - - /* send instruction to write status register */ - SPI_ON(); - spi_write_read_byte(0x01); - /* and clear it! */ - spi_write_read_byte(val); - SPI_OFF(); -} - -/* Request and read the manufacturer and device id of parts which - * are compatible with the JEDEC standard (JEP106) and use that to - * setup other operating conditions. - */ -static int spi_detect_part(void) -{ - uint16_t dev_id, dev_extid; - size_t i; - - static char called_init; - if (called_init) - return 0; - -#ifdef CONFIG_SPI_FLASH_M25P80 - flash.manufacturer_id = JED_MANU_ST; - flash.device_id1 = 0x20; - flash.device_id2 = 0xFF; -#else - SPI_ON(); - - /* Send the request for the part identification */ - spi_write_read_byte(0x9F); - - /* Now read in the manufacturer id bytes */ - do { - flash.manufacturer_id = spi_write_read_byte(0); - if (flash.manufacturer_id == 0x7F) - puts("Warning: unhandled manufacturer continuation byte!\n"); - } while (flash.manufacturer_id == 0x7F); - - /* Now read in the first device id byte */ - flash.device_id1 = spi_write_read_byte(0); - - /* Now read in the second device id byte */ - flash.device_id2 = spi_write_read_byte(0); - - /* Read extended device ids */ - flash.device_extid1 = spi_write_read_byte(0); - flash.device_extid2 = spi_write_read_byte(0); - - SPI_OFF(); -#endif - - dev_id = (flash.device_id1 << 8) | flash.device_id2; - dev_extid = (flash.device_extid1 << 8) | flash.device_extid2; - - for (i = 0; i < ARRAY_SIZE(flash_manufacturers); ++i) { - if (flash.manufacturer_id == flash_manufacturers[i].id) - break; - } - if (i == ARRAY_SIZE(flash_manufacturers)) - goto unknown; - - flash.manufacturer = &flash_manufacturers[i]; - flash.ops = flash_manufacturers[i].ops; - - switch (flash.manufacturer_id) { - case JED_MANU_SPANSION: - case JED_MANU_ST: - case JED_MANU_SST: - case JED_MANU_WINBOND: - for (i = 0; flash.manufacturer->flashes[i].name; ++i) { - if (dev_id == flash.manufacturer->flashes[i].id && - (flash.manufacturer->flashes[i].ext_id == 0 || - flash.manufacturer->flashes[i].ext_id == dev_extid)) - break; - } - if (!flash.manufacturer->flashes[i].name) - goto unknown; - - flash.flash = &flash.manufacturer->flashes[i]; - flash.sector_size = flash.flash->sector_size; - flash.num_sectors = flash.flash->num_sectors; - - if (flash.manufacturer_id == JED_MANU_SST) - flash.write_length = 1; /* pwnt :( */ - else - flash.write_length = 256; - break; - - case JED_MANU_ATMEL: { - uint8_t status = read_status_register(); - - for (i = 0; flash.manufacturer->flashes[i].name; ++i) { - if ((status & 0x3c) == flash.manufacturer->flashes[i].id) - break; - } - if (!flash.manufacturer->flashes[i].name) - goto unknown; - - flash.flash = &flash.manufacturer->flashes[i]; - flash.sector_size = flash.flash->sector_size; - flash.num_sectors = flash.flash->num_sectors; - - /* see if flash is in "power of 2" mode */ - if (status & 0x1) - flash.sector_size &= ~(1 << (ffs(flash.sector_size) - 1)); - - flash.write_length = flash.sector_size; - break; - } - } - - /* the SST parts power up with software protection enabled by default */ - if (flash.manufacturer_id == JED_MANU_SST) - write_status_register(0); - - called_init = 1; - return 0; - - unknown: - printf("Unknown SPI device: 0x%02X 0x%02X 0x%02X\n", - flash.manufacturer_id, flash.device_id1, flash.device_id2); - return 1; -} - -/* - * Function: spi_init_f - * Description: Init SPI-Controller (ROM part) - * return: --- - */ -void spi_init_f(void) -{ -} - -/* - * Function: spi_init_r - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * return: --- - */ -void spi_init_r(void) -{ -#if defined(CONFIG_POST) && (CONFIG_POST & CONFIG_SYS_POST_SPI) - /* Our testing strategy here is pretty basic: - * - fill src memory with an 8-bit pattern - * - write the src memory to the SPI flash - * - read the SPI flash into the dst memory - * - compare src and dst memory regions - * - repeat a few times - * The variations we test for: - * - change the 8-bit pattern a bit - * - change the read/write block size so we know: - * - writes smaller/equal/larger than the buffer work - * - writes smaller/equal/larger than the sector work - * - change the SPI offsets so we know: - * - writing partial sectors works - */ - uint8_t *mem_src, *mem_dst; - size_t i, c, l, o; - size_t test_count, errors; - uint8_t pattern; - - SPI_INIT(); - - if (spi_detect_part()) - goto out; - eeprom_info(); - - ulong lengths[] = { - flash.write_length, - flash.write_length * 2, - flash.write_length / 2, - flash.sector_size, - flash.sector_size * 2, - flash.sector_size / 2 - }; - ulong offsets[] = { - 0, - flash.write_length, - flash.write_length * 2, - flash.write_length / 2, - flash.write_length / 4, - flash.sector_size, - flash.sector_size * 2, - flash.sector_size / 2, - flash.sector_size / 4, - }; - - /* the exact addresses are arbitrary ... they just need to not overlap */ - mem_src = (void *)(0); - mem_dst = (void *)(max(flash.write_length, flash.sector_size) * 2); - - test_count = 0; - errors = 0; - pattern = 0x00; - - for (i = 0; i < 16; ++i) { /* 16 = 8 bits * 2 iterations */ - for (l = 0; l < ARRAY_SIZE(lengths); ++l) { - for (o = 0; o < ARRAY_SIZE(offsets); ++o) { - ulong len = lengths[l]; - ulong off = offsets[o]; - - printf("Testing pattern 0x%02X of length %5lu and offset %5lu: ", pattern, len, off); - - /* setup the source memory region */ - memset(mem_src, pattern, len); - - test_count += 4; - for (c = 0; c < 4; ++c) { /* 4 is just a random repeat count */ - if (ctrlc()) { - puts("\nAbort\n"); - goto out; - } - - /* make sure background fill pattern != pattern */ - memset(mem_dst, pattern ^ 0xFF, len); - - /* write out the source memory and then read it back and compare */ - eeprom_write(0, off, mem_src, len); - eeprom_read(0, off, mem_dst, len); - - if (memcmp(mem_src, mem_dst, len)) { - for (c = 0; c < len; ++c) - if (mem_src[c] != mem_dst[c]) - break; - printf(" FAIL @ offset %u, skipping repeats ", c); - ++errors; - break; - } - - /* XXX: should shrink write region here to test with - * leading/trailing canaries so we know surrounding - * bytes don't get screwed. - */ - } - puts("\n"); - } - } - - /* invert the pattern every other run and shift out bits slowly */ - pattern ^= 0xFF; - if (i % 2) - pattern = (pattern | 0x01) << 1; - } - - if (errors) - printf("SPI FAIL: Out of %i tests, there were %i errors ;(\n", test_count, errors); - else - printf("SPI PASS: %i tests worked!\n", test_count); - - out: - SPI_DEINIT(); - -#endif -} - -static void transmit_address(uint32_t addr) -{ - /* Send the highest byte of the 24 bit address at first */ - spi_write_read_byte(addr >> 16); - /* Send the middle byte of the 24 bit address at second */ - spi_write_read_byte(addr >> 8); - /* Send the lowest byte of the 24 bit address finally */ - spi_write_read_byte(addr); -} - -/* - * Read a value from flash for verify purpose - * Inputs: unsigned long ulStart - holds the SPI start address - * int pnData - pointer to store value read from flash - * long lCount - number of elements to read - */ -#ifdef CONFIG_SPI_READFLASH_NODMA -static int read_flash(unsigned long address, long count, uchar *buffer) -{ - size_t i, j; - - /* Send the read command to SPI device */ - SPI_ON(); - spi_write_read_byte(flash.ops->read); - transmit_address(address); - -#ifndef CONFIG_SPI_FLASH_SLOW_READ - /* Send dummy byte when doing SPI fast reads */ - spi_write_read_byte(0); -#endif - - /* After the SPI device address has been placed on the MOSI pin the data can be */ - /* received on the MISO pin. */ - j = flash.sector_size << 1; - for (i = 1; i <= count; ++i) { - *buffer++ = spi_write_read_byte(0); - if (!j--) { - puts("."); - j = flash.sector_size; - } - } - - SPI_OFF(); - - return 0; -} -#else - -#ifdef __ADSPBF54x__ -#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA4_IRQ_STATUS -#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA4_IRQ_STATUS -#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA4_CURR_DESC_PTR -#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA4_CONFIG -#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \ - defined(__ADSPBF538__) || defined(__ADSPBF539__) -#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA5_IRQ_STATUS -#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA5_IRQ_STATUS -#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA5_CURR_DESC_PTR -#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA5_CONFIG -#elif defined(__ADSPBF561__) -#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA16_IRQ_STATUS -#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA16_IRQ_STATUS -#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA16_CURR_DESC_PTR -#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA16_CONFIG -#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \ - defined(__ADSPBF52x__) || defined(__ADSPBF51x__) -#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA7_IRQ_STATUS -#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA7_IRQ_STATUS -#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA7_CURR_DESC_PTR -#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA7_CONFIG -#else -#error "Please provide SPI DMA channel defines" -#endif - -struct dmadesc_array { - unsigned long start_addr; - unsigned short cfg; - unsigned short x_count; - short x_modify; - unsigned short y_count; - short y_modify; -} __attribute__((packed)); - -/* - * Read a value from flash for verify purpose - * Inputs: unsigned long ulStart - holds the SPI start address - * int pnData - pointer to store value read from flash - * long lCount - number of elements to read - */ - -static int read_flash(unsigned long address, long count, uchar *buffer) -{ - unsigned int ndsize; - struct dmadesc_array dma[2]; - /* Send the read command to SPI device */ - - if (!count) - return 0; - - dma[0].start_addr = (unsigned long)buffer; - dma[0].x_modify = 1; - if (count <= 65536) { - blackfin_dcache_flush_invalidate_range(buffer, buffer + count); - ndsize = NDSIZE_5; - dma[0].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN; - dma[0].x_count = count; - } else { - blackfin_dcache_flush_invalidate_range(buffer, buffer + 65536 - 1); - ndsize = NDSIZE_7; - dma[0].cfg = NDSIZE_5 | WNR | WDSIZE_8 | FLOW_ARRAY | DMAEN | DMA2D; - dma[0].x_count = 0; /* 2^16 */ - dma[0].y_count = count >> 16; /* count / 2^16 */ - dma[0].y_modify = 1; - dma[1].start_addr = (unsigned long)(buffer + (count & ~0xFFFF)); - dma[1].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN; - dma[1].x_count = count & 0xFFFF; /* count % 2^16 */ - dma[1].x_modify = 1; - } - - bfin_write_DMA_SPI_CONFIG(0); - bfin_write_DMA_SPI_IRQ_STATUS(DMA_DONE | DMA_ERR); - bfin_write_DMA_SPI_CURR_DESC_PTR(dma); - - SPI_ON(); - - spi_write_read_byte(flash.ops->read); - transmit_address(address); - -#ifndef CONFIG_SPI_FLASH_SLOW_READ - /* Send dummy byte when doing SPI fast reads */ - spi_write_read_byte(0); -#endif - - bfin_write_DMA_SPI_CONFIG(ndsize | FLOW_ARRAY | DMAEN); - *pSPI_CTL = (MSTR | CPHA | CPOL | RDBR_DMA | SPE | SZ); - SSYNC(); - - /* - * We already invalidated the first 64k, - * now while we just wait invalidate the remaining part. - * Its not likely that the DMA is going to overtake - */ - if (count > 65536) - blackfin_dcache_flush_invalidate_range(buffer + 65536, - buffer + count); - - while (!(bfin_read_DMA_SPI_IRQ_STATUS() & DMA_DONE)) - if (ctrlc()) - break; - - SPI_OFF(); - - *pSPI_CTL = 0; - - bfin_write_DMA_SPI_CONFIG(0); - - *pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE); - - return 0; -} -#endif - -static long address_to_sector(unsigned long address) -{ - if (address > (flash.num_sectors * flash.sector_size) - 1) - return -1; - return address / flash.sector_size; -} - -static int erase_sector(int address) -{ - /* sector gets checked in higher function, so assume it's valid - * here and figure out the offset of the sector in flash - */ - if (enable_writing()) - return -1; - - /* - * Send the erase block command to the flash followed by the 24 address - * to point to the start of a sector - */ - SPI_ON(); - spi_write_read_byte(flash.ops->erase); - transmit_address(address); - SPI_OFF(); - - return wait_for_ready_status(); -} - -/* Write [count] bytes out of [buffer] into the given SPI [address] */ -static long write_flash(unsigned long address, long count, uchar *buffer) -{ - long i, write_buffer_size; - - if (enable_writing()) - return -1; - - /* Send write command followed by the 24 bit address */ - SPI_ON(); - spi_write_read_byte(flash.ops->write); - transmit_address(address); - - /* Shoot out a single write buffer */ - write_buffer_size = min(count, flash.write_length); - for (i = 0; i < write_buffer_size; ++i) - spi_write_read_byte(buffer[i]); - - SPI_OFF(); - - /* Wait for the flash to do its thing */ - if (wait_for_ready_status()) { - puts("SPI Program Time out! "); - return -1; - } - - return i; -} - -/* Write [count] bytes out of [buffer] into the given SPI [address] */ -static int write_sector(unsigned long address, long count, uchar *buffer) -{ - long write_cnt; - - while (count != 0) { - write_cnt = write_flash(address, count, buffer); - if (write_cnt == -1) - return -1; - - /* Now that we've sent some bytes out to the flash, update - * our counters a bit - */ - count -= write_cnt; - address += write_cnt; - buffer += write_cnt; - } - - /* return the appropriate error code */ - return 0; -} - -/* - * Function: spi_write - */ -ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) -{ - unsigned long offset; - int start_sector, end_sector; - int start_byte, end_byte; - uchar *temp = NULL; - int num, ret = 0; - - SPI_INIT(); - - if (spi_detect_part()) - goto out; - - offset = addr[0] << 16 | addr[1] << 8 | addr[2]; - - /* Get the start block number */ - start_sector = address_to_sector(offset); - if (start_sector == -1) { - puts("Invalid sector! "); - goto out; - } - end_sector = address_to_sector(offset + len - 1); - if (end_sector == -1) { - puts("Invalid sector! "); - goto out; - } - - /* Since flashes operate in sector units but the eeprom command - * operates as a continuous stream of bytes, we need to emulate - * the eeprom behavior. So here we read in the sector, overlay - * any bytes we're actually modifying, erase the sector, and - * then write back out the new sector. - */ - temp = malloc(flash.sector_size); - if (!temp) { - puts("Malloc for sector failed! "); - goto out; - } - - for (num = start_sector; num <= end_sector; num++) { - unsigned long address = num * flash.sector_size; - - /* XXX: should add an optimization when spanning sectors: - * No point in reading in a sector if we're going to be - * clobbering the whole thing. Need to also add a test - * case to make sure the optimization is correct. - */ - if (read_flash(address, flash.sector_size, temp)) { - puts("Read sector failed! "); - len = 0; - break; - } - - start_byte = max(address, offset); - end_byte = address + flash.sector_size - 1; - if (end_byte > (offset + len)) - end_byte = (offset + len - 1); - - memcpy(temp + start_byte - address, - buffer + start_byte - offset, - end_byte - start_byte + 1); - - if (erase_sector(address)) { - puts("Erase sector failed! "); - goto out; - } - - if (write_sector(address, flash.sector_size, temp)) { - puts("Write sector failed! "); - goto out; - } - - puts("."); - } - - ret = len; - - out: - free(temp); - - SPI_DEINIT(); - - return ret; -} - -/* - * Function: spi_read - */ -ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) -{ - unsigned long offset; - - SPI_INIT(); - - if (spi_detect_part()) - len = 0; - else { - offset = addr[0] << 16 | addr[1] << 8 | addr[2]; - read_flash(offset, len, buffer); - } - - SPI_DEINIT(); - - return len; -} - -/* - * Spit out some useful information about the SPI eeprom - */ -int eeprom_info(void) -{ - int ret = 0; - - SPI_INIT(); - - if (spi_detect_part()) - ret = 1; - else - printf("SPI Device: %s 0x%02X (%s) 0x%02X 0x%02X\n" - "Parameters: num sectors = %lu, sector size = %lu, write size = %i\n" - "Flash Size: %lu mbit (%lu mbyte)\n" - "Status: 0x%02X\n", - flash.flash->name, flash.manufacturer_id, flash.manufacturer->name, - flash.device_id1, flash.device_id2, flash.num_sectors, - flash.sector_size, flash.write_length, - (flash.num_sectors * flash.sector_size) >> 17, - (flash.num_sectors * flash.sector_size) >> 20, - read_status_register()); - - SPI_DEINIT(); - - return ret; -} - -#endif diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c index 65fb81a..cb9ee86 100644 --- a/board/bf548-ezkit/bf548-ezkit.c +++ b/board/bf548-ezkit/bf548-ezkit.c @@ -7,10 +7,12 @@ */ #include <common.h> -#include <netdev.h> #include <config.h> #include <command.h> +#include <netdev.h> #include <asm/blackfin.h> +#include <asm/gpio.h> +#include <asm/portmux.h> #include <asm/sdh.h> DECLARE_GLOBAL_DATA_PTR; @@ -24,53 +26,13 @@ int checkboard(void) int board_early_init_f(void) { - /* Port H: PH8 - PH13 == A4 - A9 - * address lines of the parallel asynchronous memory interface - */ - - /************************************************ - * configure GPIO * - * set port H function enable register * - * configure PH8-PH13 as peripheral (not GPIO) * - *************************************************/ - bfin_write_PORTH_FER(0x3F03); - - /************************************************ - * set port H MUX to configure PH8-PH13 * - * 1st Function (MUX = 00) (bits 16-27 == 0) * - * Set to address signals A4-A9 * - *************************************************/ - bfin_write_PORTH_MUX(0); - - /************************************************ - * set port H direction register * - * enable PH8-PH13 as outputs * - *************************************************/ - bfin_write_PORTH_DIR_SET(0x3F00); - - /* Port I: PI0 - PH14 == A10 - A24 - * address lines of the parallel asynchronous memory interface - */ - - /************************************************ - * set port I function enable register * - * configure PI0-PI14 as peripheral (not GPIO) * - *************************************************/ - bfin_write_PORTI_FER(0x7fff); - - /************************************************** - * set PORT I MUX to configure PI14-PI0 as * - * 1st Function (MUX=00) - address signals A10-A24 * - ***************************************************/ - bfin_write_PORTI_MUX(0); - - /**************************************** - * set PORT I direction register * - * enable PI0 - PI14 as outputs * - *****************************************/ - bfin_write_PORTI_DIR_SET(0x7fff); - - return 0; + /* Set async addr lines as peripheral */ + const unsigned short pins[] = { + P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, + P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, + P_A21, P_A22, P_A23, P_A24, 0 + }; + return peripheral_request_list(pins, "async"); } #ifdef CONFIG_SMC911X @@ -96,9 +58,7 @@ void board_musb_init(void) * be low for device mode and high for host mode. We set it high * here because we are in host mode. */ - bfin_write_PORTE_FER(bfin_read_PORTE_FER() & ~PE7); - bfin_write_PORTE_DIR_SET(PE7); - bfin_write_PORTE_SET(PE7); - SSYNC(); + gpio_request(GPIO_PE7, "musb-vbus"); + gpio_direction_output(GPIO_PE7, 1); } #endif diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c index 10b08e2..af3d58b 100644 --- a/board/bf548-ezkit/video.c +++ b/board/bf548-ezkit/video.c @@ -11,6 +11,8 @@ #include <config.h> #include <malloc.h> #include <asm/blackfin.h> +#include <asm/gpio.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/dma.h> #include <i2c.h> #include <linux/types.h> @@ -173,22 +175,21 @@ void Init_DMA(void *dst) void Init_Ports(void) { - *pPORTF_MUX = 0x00000000; - *pPORTF_FER |= 0xFFFF; /* PPI0..15 */ - - *pPORTG_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK); - *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */ - + const unsigned short pins[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4, + P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9, + P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, + P_PPI0_D15, P_PPI0_D16, P_PPI0_D17, #if !defined(CONFIG_VIDEO_RGB666) - *pPORTD_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK); - *pPORTD_MUX |= (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 | PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4); - *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */ + P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, + P_PPI0_D23, #endif + P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0, + }; + peripheral_request_list(pins, "lcd"); - *pPORTE_FER &= ~PE3; /* DISP */ - *pPORTE_DIR_SET = PE3; - *pPORTE_SET = PE3; - + gpio_request(GPIO_PE3, "lcd-disp"); + gpio_direction_output(GPIO_PE3, 1); } void EnableDMA(void) diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c index 6355c10..06d004a 100644 --- a/board/blackstamp/blackstamp.c +++ b/board/blackstamp/blackstamp.c @@ -13,7 +13,7 @@ #include <common.h> #include <netdev.h> -#include <asm/io.h> +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -27,14 +27,8 @@ int checkboard(void) #ifdef SHARED_RESOURCES void swap_to(int device_id) { - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0); - SSYNC(); - if (device_id == ETHERNET) - bfin_write_FIO_FLAG_S(PF0); - else if (device_id == FLASH) - bfin_write_FIO_FLAG_C(PF0); - else - printf("Unknown device to switch\n"); + gpio_request(GPIO_PF0, "eth_flash_swap"); + gpio_direction_output(GPIO_PF0, device_id == ETHERNET); SSYNC(); } #endif diff --git a/board/cm-bf527/Makefile b/board/cm-bf527/Makefile index c2cd244..bad018a 100644 --- a/board/cm-bf527/Makefile +++ b/board/cm-bf527/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o gpio.o gpio_cfi_flash.o +COBJS-y := $(BOARD).o gpio_cfi_flash.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/cm-bf527/gpio.c b/board/cm-bf527/gpio.c deleted file mode 100644 index 7e0babe..0000000 --- a/board/cm-bf527/gpio.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Control GPIO pins on the fly - * - * Copyright (c) 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <command.h> - -#include <asm/blackfin.h> - -int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc != 3) { - show_usage: - printf("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - /* parse the behavior */ - ulong port_cmd = 0; - switch (argv[1][0]) { - case 'i': break; - case 's': port_cmd = (PORTFIO_SET - PORTFIO); break; - case 'c': port_cmd = (PORTFIO_CLEAR - PORTFIO); break; - case 't': port_cmd = (PORTFIO_TOGGLE - PORTFIO); break; - default: goto show_usage; - } - - /* parse the pin with format: [p]<fgh><#> */ - const char *str_pin = argv[2]; - - /* grab the [p]<fgh> portion */ - ulong port_base; - if (*str_pin == 'p') ++str_pin; - switch (*str_pin) { - case 'f': port_base = PORTFIO; break; - case 'g': port_base = PORTGIO; break; - case 'h': port_base = PORTHIO; break; - default: goto show_usage; - } - - /* grab the <#> portion */ - ulong pin = simple_strtoul(str_pin+1, NULL, 10); - ulong pin_mask = (1 << pin); - if (pin > 15) - goto show_usage; - - /* finally, let's do it: set direction and exec command */ - switch (*str_pin) { - case 'f': bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~pin_mask); break; - case 'g': bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~pin_mask); break; - case 'h': bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~pin_mask); break; - } - - ulong port_dir = port_base + (PORTFIO_DIR - PORTFIO); - if (argv[1][0] == 'i') - bfin_write16(port_dir, bfin_read16(port_dir) & ~pin_mask); - else { - bfin_write16(port_dir, bfin_read16(port_dir) | pin_mask); - bfin_write16(port_base + port_cmd, pin_mask); - } - - printf("gpio: pin %li on port %c has been %c\n", pin, *str_pin, argv[1][0]); - - return 0; -} - -U_BOOT_CMD(gpio, 3, 0, do_gpio, - "gpio - set/clear/toggle gpio output pins\n", - "<s|c|t> <port><pin>\n" - " - set/clear/toggle the specified pin\n"); diff --git a/board/cm-bf527/gpio_cfi_flash.c b/board/cm-bf527/gpio_cfi_flash.c index 7167680..f8ccc07 100644 --- a/board/cm-bf527/gpio_cfi_flash.c +++ b/board/cm-bf527/gpio_cfi_flash.c @@ -8,12 +8,13 @@ #include <common.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/io.h> #include "gpio_cfi_flash.h" -#define GPIO_PIN_1 PH9 +#define GPIO_PIN_1 GPIO_PH9 #define GPIO_MASK_1 (1 << 21) -#define GPIO_PIN_2 PG11 +#define GPIO_PIN_2 GPIO_PG11 #define GPIO_MASK_2 (1 << 22) #define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2) @@ -21,16 +22,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr) { unsigned long addr = (unsigned long)vaddr; - if (addr & GPIO_MASK_1) - bfin_write_PORTHIO_SET(GPIO_PIN_1); - else - bfin_write_PORTHIO_CLEAR(GPIO_PIN_1); + gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); #ifdef GPIO_MASK_2 - if (addr & GPIO_MASK_2) - bfin_write_PORTGIO_SET(GPIO_PIN_2); - else - bfin_write_PORTGIO_CLEAR(GPIO_PIN_2); + gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); #endif SSYNC(); @@ -57,7 +52,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ void gpio_cfi_flash_init(void) { - bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | GPIO_PIN_1); - bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | GPIO_PIN_2); + gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); +#ifdef GPIO_MASK_2 + gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); +#endif gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); } diff --git a/board/cm-bf537e/Makefile b/board/cm-bf537e/Makefile index 3812ba1..bad018a 100644 --- a/board/cm-bf537e/Makefile +++ b/board/cm-bf537e/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o +COBJS-y := $(BOARD).o gpio_cfi_flash.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/cm-bf537e/flash.c b/board/cm-bf537e/flash.c deleted file mode 100644 index a4c1ec0..0000000 --- a/board/cm-bf537e/flash.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * flash.c - helper commands for working with GPIO-assisted flash - * - * Copyright (c) 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <command.h> -#include <asm/blackfin.h> -#include "gpio_cfi_flash.h" - -int do_pf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong faddr = CONFIG_SYS_FLASH_BASE; - ushort data; - ulong dflg; - - if (argc > 1) { - dflg = simple_strtoul(argv[1], NULL, 16); - faddr |= (dflg << 21); - gpio_cfi_flash_swizzle((void *)faddr); - } else { - data = bfin_read_PORTFIO(); - printf("Port F data %04x (PF4:%i)\n", data, !!(data & PF4)); - } - - return 0; -} - -U_BOOT_CMD(pf, 3, 0, do_pf, - "set/clear PF4 GPIO flash bank switch\n", - "<pf4> - set PF4 GPIO pin state\n"); diff --git a/board/cm-bf537e/gpio_cfi_flash.c b/board/cm-bf537e/gpio_cfi_flash.c index a9e69cf..79ee844 100644 --- a/board/cm-bf537e/gpio_cfi_flash.c +++ b/board/cm-bf537e/gpio_cfi_flash.c @@ -8,10 +8,11 @@ #include <common.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/io.h> #include "gpio_cfi_flash.h" -#define GPIO_PIN_1 PF4 +#define GPIO_PIN_1 GPIO_PF4 #define GPIO_MASK_1 (1 << 21) #define GPIO_MASK (GPIO_MASK_1) @@ -19,16 +20,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr) { unsigned long addr = (unsigned long)vaddr; - if (addr & GPIO_MASK_1) - bfin_write_PORTFIO_SET(GPIO_PIN_1); - else - bfin_write_PORTFIO_CLEAR(GPIO_PIN_1); + gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); #ifdef GPIO_MASK_2 - if (addr & GPIO_MASK_2) - bfin_write_PORTGIO_SET(GPIO_PIN_2); - else - bfin_write_PORTGIO_CLEAR(GPIO_PIN_2); + gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); #endif SSYNC(); @@ -55,6 +50,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ void gpio_cfi_flash_init(void) { - bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | GPIO_PIN_1); + gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); +#ifdef GPIO_MASK_2 + gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); +#endif gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); } diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile index 3812ba1..bad018a 100644 --- a/board/cm-bf537u/Makefile +++ b/board/cm-bf537u/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o +COBJS-y := $(BOARD).o gpio_cfi_flash.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/cm-bf537u/flash.c b/board/cm-bf537u/flash.c deleted file mode 100644 index 52abe79..0000000 --- a/board/cm-bf537u/flash.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * flash.c - helper commands for working with GPIO-assisted flash - * - * Copyright (c) 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <command.h> -#include <asm/blackfin.h> -#include "gpio_cfi_flash.h" - -int do_ph(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong faddr = CONFIG_SYS_FLASH_BASE; - ushort data; - ulong dflg; - - if (argc > 1) { - dflg = simple_strtoul(argv[1], NULL, 16); - faddr |= (dflg << 21); - gpio_cfi_flash_swizzle((void *)faddr); - } else { - data = bfin_read_PORTHIO(); - printf("Port H data %04x (PH0:%i)\n", data, !!(data & PH0)); - } - - return 0; -} - -U_BOOT_CMD(ph, 3, 0, do_ph, - "set/clear PH0 GPIO flash bank switch\n", - "<ph0> - set PH0 GPIO pin state\n"); diff --git a/board/cm-bf537u/gpio_cfi_flash.c b/board/cm-bf537u/gpio_cfi_flash.c index 68633ec..416c689 100644 --- a/board/cm-bf537u/gpio_cfi_flash.c +++ b/board/cm-bf537u/gpio_cfi_flash.c @@ -8,10 +8,11 @@ #include <common.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/io.h> #include "gpio_cfi_flash.h" -#define GPIO_PIN_1 PH0 +#define GPIO_PIN_1 GPIO_PH0 #define GPIO_MASK_1 (1 << 21) #define GPIO_MASK (GPIO_MASK_1) @@ -19,16 +20,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr) { unsigned long addr = (unsigned long)vaddr; - if (addr & GPIO_MASK_1) - bfin_write_PORTHIO_SET(GPIO_PIN_1); - else - bfin_write_PORTHIO_CLEAR(GPIO_PIN_1); + gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); #ifdef GPIO_MASK_2 - if (addr & GPIO_MASK_2) - bfin_write_PORTGIO_SET(GPIO_PIN_2); - else - bfin_write_PORTGIO_CLEAR(GPIO_PIN_2); + gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); #endif SSYNC(); @@ -55,6 +50,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ void gpio_cfi_flash_init(void) { - bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | GPIO_PIN_1); + gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); +#ifdef GPIO_MASK_2 + gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); +#endif gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); } diff --git a/board/cm-bf548/cm-bf548.c b/board/cm-bf548/cm-bf548.c index 3627586..90ce4c3 100644 --- a/board/cm-bf548/cm-bf548.c +++ b/board/cm-bf548/cm-bf548.c @@ -11,6 +11,7 @@ #include <command.h> #include <netdev.h> #include <asm/blackfin.h> +#include <asm/portmux.h> DECLARE_GLOBAL_DATA_PTR; @@ -23,53 +24,13 @@ int checkboard(void) int board_early_init_f(void) { - /* Port H: PH8 - PH13 == A4 - A9 - * address lines of the parallel asynchronous memory interface - */ - - /************************************************ - * configure GPIO * - * set port H function enable register * - * configure PH8-PH13 as peripheral (not GPIO) * - *************************************************/ - bfin_write_PORTH_FER(0x3F03); - - /************************************************ - * set port H MUX to configure PH8-PH13 * - * 1st Function (MUX = 00) (bits 16-27 == 0) * - * Set to address signals A4-A9 * - *************************************************/ - bfin_write_PORTH_MUX(0); - - /************************************************ - * set port H direction register * - * enable PH8-PH13 as outputs * - *************************************************/ - bfin_write_PORTH_DIR_SET(0x3F00); - - /* Port I: PI0 - PH14 == A10 - A24 - * address lines of the parallel asynchronous memory interface - */ - - /************************************************ - * set port I function enable register * - * configure PI0-PI14 as peripheral (not GPIO) * - *************************************************/ - bfin_write_PORTI_FER(0x7fff); - - /************************************************** - * set PORT I MUX to configure PI14-PI0 as * - * 1st Function (MUX=00) - address signals A10-A24 * - ***************************************************/ - bfin_write_PORTI_MUX(0); - - /**************************************** - * set PORT I direction register * - * enable PI0 - PI14 as outputs * - *****************************************/ - bfin_write_PORTI_DIR_SET(0x7fff); - - return 0; + /* Set async addr lines as peripheral */ + const unsigned short pins[] = { + P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, + P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, + P_A21, P_A22, P_A23, P_A24, 0 + }; + return peripheral_request_list(pins, "async"); } int board_eth_init(bd_t *bis) diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c index 4097f09..d43f5a1 100644 --- a/board/cm-bf548/video.c +++ b/board/cm-bf548/video.c @@ -11,6 +11,8 @@ #include <config.h> #include <malloc.h> #include <asm/blackfin.h> +#include <asm/gpio.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/dma.h> #include <i2c.h> #include <linux/types.h> @@ -174,28 +176,21 @@ void Init_DMA(void *dst) void Init_Ports(void) { - *pPORTF_MUX = 0x00000000; - *pPORTF_FER |= 0xFFFF; /* PPI0..15 */ - - *pPORTG_MUX &= - ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | - PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK); - *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */ - + const unsigned short pins[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4, + P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9, + P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, + P_PPI0_D15, P_PPI0_D16, P_PPI0_D17, #if !defined(CONFIG_VIDEO_RGB666) - *pPORTD_MUX &= - ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | - PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK); - *pPORTD_MUX |= - (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 | - PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4); - *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */ + P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, + P_PPI0_D23, #endif + P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0, + }; + peripheral_request_list(pins, "lcd"); - *pPORTE_FER &= ~PE3; /* DISP */ - *pPORTE_DIR_SET = PE3; - *pPORTE_SET = PE3; - + gpio_request(GPIO_PE3, "lcd-disp"); + gpio_direction_output(GPIO_PE3, 1); } void EnableDMA(void) diff --git a/board/ibf-dsp561/ibf-dsp561.c b/board/ibf-dsp561/ibf-dsp561.c index b5bebd4..d2ac7a5 100644 --- a/board/ibf-dsp561/ibf-dsp561.c +++ b/board/ibf-dsp561/ibf-dsp561.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -16,3 +17,10 @@ int checkboard(void) printf(" Support: http://www.i-syst.com/\n"); return 0; } + +#ifdef CONFIG_DRIVER_AX88180 +int board_eth_init(bd_t *bis) +{ + return ax88180_initialize(bis); +} +#endif diff --git a/board/tcm-bf537/Makefile b/board/tcm-bf537/Makefile index 3812ba1..bad018a 100644 --- a/board/tcm-bf537/Makefile +++ b/board/tcm-bf537/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o +COBJS-y := $(BOARD).o gpio_cfi_flash.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/tcm-bf537/flash.c b/board/tcm-bf537/flash.c deleted file mode 100644 index 14055c6..0000000 --- a/board/tcm-bf537/flash.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * flash.c - helper commands for working with GPIO-assisted flash - * - * Copyright (c) 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <command.h> -#include <asm/blackfin.h> -#include "gpio_cfi_flash.h" - -int do_pf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong faddr = CONFIG_SYS_FLASH_BASE; - ushort data; - ulong dflg; - - if (argc == 3) { - dflg = simple_strtoul(argv[1], NULL, 16); - faddr |= (dflg << 21); - dflg = simple_strtoul(argv[2], NULL, 16); - faddr |= (dflg << 22); - gpio_cfi_flash_swizzle((void *)faddr); - } else { - data = bfin_read_PORTFIO(); - printf("Port F data %04x (PF4:%i PF5:%i)\n", data, - !!(data & PF4), !!(data & PF5)); - } - - return 0; -} - -U_BOOT_CMD(pf, 3, 0, do_pf, - "set/clear PF4/PF5 GPIO flash bank switch\n", - "<pf4> <pf5> - set PF4/PF5 GPIO pin state\n"); diff --git a/board/tcm-bf537/gpio_cfi_flash.c b/board/tcm-bf537/gpio_cfi_flash.c index ac8587c..08ea7af 100644 --- a/board/tcm-bf537/gpio_cfi_flash.c +++ b/board/tcm-bf537/gpio_cfi_flash.c @@ -8,12 +8,13 @@ #include <common.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/io.h> #include "gpio_cfi_flash.h" -#define GPIO_PIN_1 PF4 +#define GPIO_PIN_1 GPIO_PF4 #define GPIO_MASK_1 (1 << 21) -#define GPIO_PIN_2 PF5 +#define GPIO_PIN_2 GPIO_PF5 #define GPIO_MASK_2 (1 << 22) #define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2) @@ -21,16 +22,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr) { unsigned long addr = (unsigned long)vaddr; - if (addr & GPIO_MASK_1) - bfin_write_PORTFIO_SET(GPIO_PIN_1); - else - bfin_write_PORTFIO_CLEAR(GPIO_PIN_1); + gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); #ifdef GPIO_MASK_2 - if (addr & GPIO_MASK_2) - bfin_write_PORTFIO_SET(GPIO_PIN_2); - else - bfin_write_PORTFIO_CLEAR(GPIO_PIN_2); + gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); #endif SSYNC(); @@ -57,6 +52,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ void gpio_cfi_flash_init(void) { - bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | GPIO_PIN_1 | GPIO_PIN_2); + gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); +#ifdef GPIO_MASK_2 + gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); +#endif gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); } @@ -282,6 +282,7 @@ favr-32-ezkit avr32 at32ap - earthlcd at32ap700x hammerhead avr32 at32ap - miromico at32ap700x bf518f-ezbrd blackfin blackfin bf526-ezbrd blackfin blackfin +bf527-ad7160-eval blackfin blackfin bf527-ezkit blackfin blackfin bf533-ezkit blackfin blackfin bf533-stamp blackfin blackfin diff --git a/common/cmd_nand.c b/common/cmd_nand.c index ea80555..84b6272 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -4,6 +4,10 @@ * (c) 1999 Machine Vision Holdings, Inc. * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org> * + * Ported 'dynenv' to 'nand env.oob' command + * (C) 2010 Nanometrics, Inc. + * 'dynenv' -- Dynamic environment offset in NAND OOB + * (C) Copyright 2006-2007 OpenMoko, Inc. * Added 16-bit nand support * (C) 2004 Texas Instruments */ @@ -193,6 +197,90 @@ static void do_nand_status(nand_info_t *nand) } #endif +#ifdef CONFIG_ENV_OFFSET_OOB +unsigned long nand_env_oob_offset; + +int do_nand_env_oob(cmd_tbl_t *cmdtp, nand_info_t *nand, + int argc, char * const argv[]) +{ + int ret; + uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)]; + + char *cmd = argv[1]; + + if (!strcmp(cmd, "get")) { + ret = get_nand_env_oob(nand, &nand_env_oob_offset); + if (ret) + return 1; + + printf("0x%08lx\n", nand_env_oob_offset); + } else if (!strcmp(cmd, "set")) { + ulong addr; + size_t dummy_size; + struct mtd_oob_ops ops; + + if (argc < 3) + goto usage; + + if (arg_off_size(argc - 2, argv + 2, nand, &addr, + &dummy_size) < 0) { + printf("Offset or partition name expected\n"); + return 1; + } + + if (nand->oobavail < ENV_OFFSET_SIZE) { + printf("Insufficient available OOB bytes:\n" + "%d OOB bytes available but %d required for " + "env.oob support\n", + nand->oobavail, ENV_OFFSET_SIZE); + return 1; + } + + if ((addr & (nand->erasesize - 1)) != 0) { + printf("Environment offset must be block-aligned\n"); + return 1; + } + + ops.datbuf = NULL; + ops.mode = MTD_OOB_AUTO; + ops.ooboffs = 0; + ops.ooblen = ENV_OFFSET_SIZE; + ops.oobbuf = (void *) oob_buf; + + oob_buf[0] = ENV_OOB_MARKER; + oob_buf[1] = addr / nand->erasesize; + + ret = nand->write_oob(nand, ENV_OFFSET_SIZE, &ops); + if (ret) { + printf("Error writing OOB block 0\n"); + return ret; + } + + ret = get_nand_env_oob(nand, &nand_env_oob_offset); + if (ret) { + printf("Error reading env offset in OOB\n"); + return ret; + } + + if (addr != nand_env_oob_offset) { + printf("Verification of env offset in OOB failed: " + "0x%08lx expected but got 0x%08lx\n", + addr, nand_env_oob_offset); + return 1; + } + } else { + goto usage; + } + + return ret; + +usage: + cmd_usage(cmdtp); + return 1; +} + +#endif + static void nand_print_info(int idx) { nand_info_t *nand = &nand_info[idx]; @@ -272,9 +360,21 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 && strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 && strcmp(cmd, "biterr") != 0 && - strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 ) + strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 +#ifdef CONFIG_ENV_OFFSET_OOB + && strcmp(cmd, "env.oob") != 0 +#endif + ) goto usage; +#ifdef CONFIG_ENV_OFFSET_OOB + /* this command operates only on the first nand device */ + if (strcmp(cmd, "env.oob") == 0) { + return do_nand_env_oob(cmdtp, &nand_info[0], + argc - 1, argv + 1); + } +#endif + /* the following commands operate on the current device */ if (nand_curr_device < 0 || nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[nand_curr_device].name) { @@ -502,6 +602,13 @@ U_BOOT_CMD(nand, CONFIG_SYS_MAXARGS, 1, do_nand, " bring nand to lock state or display locked pages\n" "nand unlock [offset] [size] - unlock section" #endif +#ifdef CONFIG_ENV_OFFSET_OOB + "\n" + "nand env.oob - environment offset in OOB of block 0 of" + " first device.\n" + "nand env.oob set off|partition - set enviromnent offset\n" + "nand env.oob get - get environment offset" +#endif ); static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, diff --git a/common/env_nand.c b/common/env_nand.c index 50bc111..a5e1038 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -38,6 +38,7 @@ #include <linux/stddef.h> #include <malloc.h> #include <nand.h> +#include <asm/errno.h> #if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_NAND) #define CMD_SAVEENV @@ -284,6 +285,38 @@ int readenv (size_t offset, u_char * buf) return 0; } +#ifdef CONFIG_ENV_OFFSET_OOB +int get_nand_env_oob(nand_info_t *nand, unsigned long *result) +{ + struct mtd_oob_ops ops; + uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)]; + int ret; + + ops.datbuf = NULL; + ops.mode = MTD_OOB_AUTO; + ops.ooboffs = 0; + ops.ooblen = ENV_OFFSET_SIZE; + ops.oobbuf = (void *) oob_buf; + + ret = nand->read_oob(nand, ENV_OFFSET_SIZE, &ops); + if (ret) { + printf("error reading OOB block 0\n"); + return ret; + } + + if (oob_buf[0] == ENV_OOB_MARKER) { + *result = oob_buf[1] * nand->erasesize; + } else if (oob_buf[0] == ENV_OOB_MARKER_OLD) { + *result = oob_buf[1]; + } else { + printf("No dynamic environment marker in OOB block 0\n"); + return -ENOENT; + } + + return 0; +} +#endif + #ifdef CONFIG_ENV_OFFSET_REDUND void env_relocate_spec (void) { @@ -353,6 +386,17 @@ void env_relocate_spec (void) #if !defined(ENV_IS_EMBEDDED) int ret; +#if defined(CONFIG_ENV_OFFSET_OOB) + ret = get_nand_env_oob(&nand_info[0], &nand_env_oob_offset); + /* If unable to read environment offset from NAND OOB then fall through + * to the normal environment reading code below + */ + if (!ret) + printf("Found Environment offset in OOB..\n"); + else + return use_default(); +#endif + ret = readenv(CONFIG_ENV_OFFSET, (u_char *) env_ptr); if (ret) return use_default(); diff --git a/drivers/block/pata_bfin.c b/drivers/block/pata_bfin.c index f16dabe..847c032 100644 --- a/drivers/block/pata_bfin.c +++ b/drivers/block/pata_bfin.c @@ -14,6 +14,7 @@ #include <asm/byteorder.h> #include <asm/io.h> #include <asm/errno.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/pata.h> #include <ata.h> #include <libata.h> @@ -769,19 +770,17 @@ static int bfin_ata_reset_port(struct ata_port *ap) */ static int bfin_config_atapi_gpio(struct ata_port *ap) { - bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0x4); - bfin_write_PORTH_MUX(bfin_read_PORTH_MUX() & ~0x30); - bfin_write_PORTH_DIR_SET(0x4); - - bfin_write_PORTJ_FER(0x7f8); - bfin_write_PORTJ_MUX(bfin_read_PORTI_MUX() & ~0x3fffc0); - bfin_write_PORTJ_DIR_SET(0x5f8); - bfin_write_PORTJ_DIR_CLEAR(0x200); - bfin_write_PORTJ_INEN(0x200); - - bfin_write_PINT2_ASSIGN(0x0707); - bfin_write_PINT2_MASK_SET(0x200); - SSYNC(); + const unsigned short pins[] = { + P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0, + P_ATAPI_CS1, P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ, + P_ATAPI_IORDY, P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A, + P_ATAPI_D3A, P_ATAPI_D4A, P_ATAPI_D5A, P_ATAPI_D6A, + P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A, P_ATAPI_D10A, + P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A, + P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A, 0, + }; + + peripheral_request_list(pins, "pata_bfin"); return 0; } diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index f9d560a..4a77779 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -15,6 +15,7 @@ #include <asm/errno.h> #include <asm/byteorder.h> #include <asm/blackfin.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/sdh.h> #include <asm/mach-common/bits/dma.h> @@ -41,11 +42,15 @@ # define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT # define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY # define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG +# define PORTMUX_PINS \ + { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 } #elif defined(__ADSPBF54x__) # define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR # define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT # define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY # define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG +# define PORTMUX_PINS \ + { P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 } #else # error no support for this proc yet #endif @@ -208,18 +213,13 @@ static void bfin_sdh_set_ios(struct mmc *mmc) static int bfin_sdh_init(struct mmc *mmc) { - + const unsigned short pins[] = PORTMUX_PINS; u16 pwr_ctl = 0; -/* Initialize sdh controller */ + + /* Initialize sdh controller */ + peripheral_request_list(pins, "bfin_sdh"); #if defined(__ADSPBF54x__) bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1); - bfin_write_PORTC_FER(bfin_read_PORTC_FER() | 0x3F00); - bfin_write_PORTC_MUX(bfin_read_PORTC_MUX() & ~0xFFF0000); -#elif defined(__ADSPBF51x__) - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | 0x01F8); - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~0x3FC) | 0x154); -#else -# error no portmux for this proc yet #endif bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN); /* Disable card detect pin */ diff --git a/drivers/mtd/nand/bfin_nand.c b/drivers/mtd/nand/bfin_nand.c index 6d3d450..3ee060f 100644 --- a/drivers/mtd/nand/bfin_nand.c +++ b/drivers/mtd/nand/bfin_nand.c @@ -26,6 +26,7 @@ #include <nand.h> #include <asm/blackfin.h> +#include <asm/portmux.h> /* Bit masks for NFC_CTL */ @@ -337,6 +338,12 @@ static struct nand_ecclayout bootrom_ecclayout = { */ int board_nand_init(struct nand_chip *chip) { + const unsigned short pins[] = { + P_NAND_CE, P_NAND_RB, P_NAND_D0, P_NAND_D1, P_NAND_D2, + P_NAND_D3, P_NAND_D4, P_NAND_D5, P_NAND_D6, P_NAND_D7, + P_NAND_WE, P_NAND_RE, P_NAND_CLE, P_NAND_ALE, 0, + }; + pr_stamp(); /* set width/ecc/timings/etc... */ @@ -347,14 +354,7 @@ int board_nand_init(struct nand_chip *chip) bfin_write_NFC_IRQSTAT(0xffff); /* enable GPIO function enable register */ -#ifdef __ADSPBF54x__ - bfin_write_PORTJ_FER(bfin_read_PORTJ_FER() | 6); -#elif defined(__ADSPBF52x__) - bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0xFCFF); - bfin_write_PORTH_MUX(0); -#else -# error no support for this variant -#endif + peripheral_request_list(pins, "bfin_nand"); chip->cmd_ctrl = bfin_nfc_cmd_ctrl; chip->read_buf = bfin_nfc_read_buf; diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 7171bdd..ed1c9c9 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2652,8 +2652,12 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, } } - if (!type) + if (!type) { + printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:" + " 0x%02x, Chip ID: 0x%02x\n", __func__, + *maf_id, dev_id); return ERR_PTR(-ENODEV); + } if (!mtd->name) mtd->name = type->name; diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 077c305..25b22ec 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -83,6 +83,7 @@ struct nand_flash_dev nand_flash_ids[] = { /* 1 Gigabit */ {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS}, {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS}, + {"NAND 128MiB 3,3V 8-bit", 0xD1, 0, 128, 0, LP_OPTIONS}, {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16}, {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16}, diff --git a/drivers/mtd/nand/nand_plat.c b/drivers/mtd/nand/nand_plat.c index b35492b..37a0206 100644 --- a/drivers/mtd/nand/nand_plat.c +++ b/drivers/mtd/nand/nand_plat.c @@ -16,6 +16,10 @@ #include <common.h> #include <asm/io.h> +#ifdef NAND_PLAT_GPIO_DEV_READY +# include <asm/gpio.h> +# define NAND_PLAT_DEV_READY(chip) gpio_get_value(NAND_PLAT_GPIO_DEV_READY) +#endif #include <nand.h> @@ -43,7 +47,14 @@ static int plat_dev_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { +#ifdef NAND_PLAT_GPIO_DEV_READY + gpio_request(NAND_PLAT_GPIO_DEV_READY, "nand-plat"); + gpio_direction_input(NAND_PLAT_GPIO_DEV_READY); +#endif + +#ifdef NAND_PLAT_INIT NAND_PLAT_INIT(); +#endif nand->cmd_ctrl = plat_cmd_ctrl; nand->dev_ready = plat_dev_ready; diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index 720e126..e691bdf 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -16,6 +16,7 @@ #include <linux/mii.h> #include <asm/blackfin.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/dma.h> #include <asm/mach-common/bits/emac.h> #include <asm/mach-common/bits/pll.h> @@ -98,7 +99,7 @@ int bfin_EMAC_initialize(bd_t *bis) hang(); memset(dev, 0, sizeof(*dev)); - sprintf(dev->name, "Blackfin EMAC"); + strcpy(dev->name, "bfin_mac"); dev->iobase = 0; dev->priv = 0; @@ -213,8 +214,17 @@ static int bfin_EMAC_recv(struct eth_device *dev) /* MDC = SCLK / MDC_freq / 2 - 1 */ #define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1) +#ifndef CONFIG_BFIN_MAC_PINS +# ifdef CONFIG_RMII +# define CONFIG_BFIN_MAC_PINS P_RMII0 +# else +# define CONFIG_BFIN_MAC_PINS P_MII0 +# endif +#endif + static int bfin_miiphy_init(struct eth_device *dev, int *opmode) { + const unsigned short pins[] = CONFIG_BFIN_MAC_PINS; u16 phydat; size_t count; @@ -222,42 +232,7 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) *pVR_CTL |= CLKBUFOE; /* Set all the pins to peripheral mode */ -#ifdef CONFIG_RMII - /* grab RMII pins */ -# if defined(__ADSPBF51x__) - *pPORTF_MUX = (*pPORTF_MUX & \ - ~(PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \ - PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1; - *pPORTF_FER |= PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15; - *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1; - *pPORTG_FER |= PG0 | PG1 | PG2; -# elif defined(__ADSPBF52x__) - *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2; - *pPORTG_FER |= PG14 | PG15; - *pPORTH_MUX = (*pPORTH_MUX & ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK)) | \ - PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2; - *pPORTH_FER |= PH0 | PH1 | PH2 | PH3 | PH4 | PH5 | PH6 | PH7 | PH8; -# else - *pPORTH_FER |= PH0 | PH1 | PH4 | PH5 | PH6 | PH8 | PH9 | PH14 | PH15; -# endif -#else - /* grab MII & RMII pins */ -# if defined(__ADSPBF51x__) - *pPORTF_MUX = (*pPORTF_MUX & \ - ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \ - PORT_x_MUX_0_FUNC_1 | PORT_x_MUX_1_FUNC_1 | PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1; - *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15; - *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1; - *pPORTG_FER |= PG0 | PG1 | PG2; -# elif defined(__ADSPBF52x__) - *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2; - *pPORTG_FER |= PG14 | PG15; - *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2; - *pPORTH_FER = -1; /* all pins */ -# else - *pPORTH_FER = -1; /* all pins */ -# endif -#endif + peripheral_request_list(pins, "bfin_mac"); /* Odd word alignment for Receive Frame DMA word */ /* Configure checksum support and rcve frame word alignment */ diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c index f28d42b..e0ad029 100644 --- a/drivers/spi/bfin_spi.c +++ b/drivers/spi/bfin_spi.c @@ -13,6 +13,8 @@ #include <spi.h> #include <asm/blackfin.h> +#include <asm/gpio.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/spi.h> struct bfin_spi_slave { @@ -33,54 +35,110 @@ MAKE_SPI_FUNC(SPI_BAUD, 0x14) #define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave) -__attribute__((weak)) +#define MAX_CTRL_CS 7 + +#define gpio_cs(cs) ((cs) - MAX_CTRL_CS) +#ifdef CONFIG_BFIN_SPI_GPIO_CS +# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS) +#else +# define is_gpio_cs(cs) 0 +#endif + int spi_cs_is_valid(unsigned int bus, unsigned int cs) { -#if defined(__ADSPBF538__) || defined(__ADSPBF539__) - /* The SPI1/SPI2 buses are weird ... only 1 CS */ - if (bus > 0 && cs != 1) - return 0; -#endif - return (cs >= 1 && cs <= 7); + if (is_gpio_cs(cs)) + return gpio_is_valid(gpio_cs(cs)); + else + return (cs >= 1 && cs <= MAX_CTRL_CS); } -__attribute__((weak)) void spi_cs_activate(struct spi_slave *slave) { struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); - write_SPI_FLG(bss, - (read_SPI_FLG(bss) & - ~((!bss->flg << 8) << slave->cs)) | - (1 << slave->cs)); + + if (is_gpio_cs(slave->cs)) { + unsigned int cs = gpio_cs(slave->cs); + gpio_set_value(cs, bss->flg); + debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs)); + } else { + write_SPI_FLG(bss, + (read_SPI_FLG(bss) & + ~((!bss->flg << 8) << slave->cs)) | + (1 << slave->cs)); + debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss)); + } + SSYNC(); - debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss)); } -__attribute__((weak)) void spi_cs_deactivate(struct spi_slave *slave) { struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); - u16 flg; - - /* make sure we force the cs to deassert rather than let the - * pin float back up. otherwise, exact timings may not be - * met some of the time leading to random behavior (ugh). - */ - flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs); - write_SPI_FLG(bss, flg); - SSYNC(); - debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss)); - flg &= ~(1 << slave->cs); - write_SPI_FLG(bss, flg); + if (is_gpio_cs(slave->cs)) { + unsigned int cs = gpio_cs(slave->cs); + gpio_set_value(cs, !bss->flg); + debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs)); + } else { + u16 flg; + + /* make sure we force the cs to deassert rather than let the + * pin float back up. otherwise, exact timings may not be + * met some of the time leading to random behavior (ugh). + */ + flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs); + write_SPI_FLG(bss, flg); + SSYNC(); + debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss)); + + flg &= ~(1 << slave->cs); + write_SPI_FLG(bss, flg); + debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss)); + } + SSYNC(); - debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss)); } void spi_init() { } +#ifdef SPI_CTL +# define SPI0_CTL SPI_CTL +#endif + +#define SPI_PINS(n) \ + [n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 } +static unsigned short pins[][5] = { +#ifdef SPI0_CTL + SPI_PINS(0), +#endif +#ifdef SPI1_CTL + SPI_PINS(1), +#endif +#ifdef SPI2_CTL + SPI_PINS(2), +#endif +}; + +#define SPI_CS_PINS(n) \ + [n] = { \ + P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \ + P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \ + P_SPI##n##_SSEL7, \ + } +static const unsigned short cs_pins[][7] = { +#ifdef SPI0_CTL + SPI_CS_PINS(0), +#endif +#ifdef SPI1_CTL + SPI_CS_PINS(1), +#endif +#ifdef SPI2_CTL + SPI_CS_PINS(2), +#endif +}; + struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { @@ -92,11 +150,14 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs)) return NULL; + if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) { + debug("%s: invalid bus %u\n", __func__, bus); + return NULL; + } switch (bus) { -#ifdef SPI_CTL -# define SPI0_CTL SPI_CTL -#endif +#ifdef SPI0_CTL case 0: mmr_base = SPI0_CTL; break; +#endif #ifdef SPI1_CTL case 1: mmr_base = SPI1_CTL; break; #endif @@ -142,168 +203,21 @@ void spi_free_slave(struct spi_slave *slave) free(bss); } -static void spi_portmux(struct spi_slave *slave) -{ -#if defined(__ADSPBF51x__) -#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func) - u16 f_mux = bfin_read_PORTF_MUX(); - u16 f_fer = bfin_read_PORTF_FER(); - u16 g_mux = bfin_read_PORTG_MUX(); - u16 g_fer = bfin_read_PORTG_FER(); - u16 h_mux = bfin_read_PORTH_MUX(); - u16 h_fer = bfin_read_PORTH_FER(); - switch (slave->bus) { - case 0: - /* set SCK/MISO/MOSI */ - SET_MUX(g, 7, 1); - g_fer |= PG12 | PG13 | PG14; - switch (slave->cs) { - case 1: SET_MUX(f, 2, 1); f_fer |= PF7; break; - case 2: /* see G above */ g_fer |= PG15; break; - case 3: SET_MUX(h, 1, 3); f_fer |= PH4; break; - case 4: /* no muxing */ h_fer |= PH8; break; - case 5: SET_MUX(g, 1, 3); h_fer |= PG3; break; - case 6: /* no muxing */ break; - case 7: /* no muxing */ break; - } - case 1: - /* set SCK/MISO/MOSI */ - SET_MUX(h, 0, 2); - h_fer |= PH1 | PH2 | PH3; - switch (slave->cs) { - case 1: SET_MUX(h, 2, 3); h_fer |= PH6; break; - case 2: SET_MUX(f, 0, 3); f_fer |= PF0; break; - case 3: SET_MUX(g, 0, 3); g_fer |= PG0; break; - case 4: SET_MUX(f, 3, 3); f_fer |= PF8; break; - case 5: SET_MUX(g, 6, 3); h_fer |= PG11; break; - case 6: /* no muxing */ break; - case 7: /* no muxing */ break; - } - } - bfin_write_PORTF_MUX(f_mux); - bfin_write_PORTF_FER(f_fer); - bfin_write_PORTG_MUX(g_mux); - bfin_write_PORTG_FER(g_fer); - bfin_write_PORTH_MUX(h_mux); - bfin_write_PORTH_FER(h_fer); -#elif defined(__ADSPBF52x__) -#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func) - u16 f_mux = bfin_read_PORTF_MUX(); - u16 f_fer = bfin_read_PORTF_FER(); - u16 g_mux = bfin_read_PORTG_MUX(); - u16 g_fer = bfin_read_PORTG_FER(); - u16 h_mux = bfin_read_PORTH_MUX(); - u16 h_fer = bfin_read_PORTH_FER(); - /* set SCK/MISO/MOSI */ - SET_MUX(g, 0, 3); - g_fer |= PG2 | PG3 | PG4; - switch (slave->cs) { - case 1: /* see G above */ g_fer |= PG1; break; - case 2: SET_MUX(f, 4, 3); f_fer |= PF12; break; - case 3: SET_MUX(f, 4, 3); f_fer |= PF13; break; - case 4: SET_MUX(h, 1, 1); h_fer |= PH8; break; - case 5: SET_MUX(h, 2, 1); h_fer |= PH9; break; - case 6: SET_MUX(f, 1, 3); f_fer |= PF9; break; - case 7: SET_MUX(f, 2, 3); f_fer |= PF10; break; - } - bfin_write_PORTF_MUX(f_mux); - bfin_write_PORTF_FER(f_fer); - bfin_write_PORTG_MUX(g_mux); - bfin_write_PORTG_FER(g_fer); - bfin_write_PORTH_MUX(h_mux); - bfin_write_PORTH_FER(h_fer); -#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) - u16 mux = bfin_read_PORT_MUX(); - u16 f_fer = bfin_read_PORTF_FER(); - /* set SCK/MISO/MOSI */ - f_fer |= PF11 | PF12 | PF13; - switch (slave->cs) { - case 1: f_fer |= PF10; break; - case 2: mux |= PJSE; break; - case 3: mux |= PJSE; break; - case 4: mux |= PFS4E; f_fer |= PF6; break; - case 5: mux |= PFS5E; f_fer |= PF5; break; - case 6: mux |= PFS6E; f_fer |= PF4; break; - case 7: mux |= PJCE_SPI; break; - } - bfin_write_PORT_MUX(mux); - bfin_write_PORTF_FER(f_fer); -#elif defined(__ADSPBF538__) || defined(__ADSPBF539__) - u16 fer, pins; - if (slave->bus == 1) - pins = PD0 | PD1 | PD2 | (slave->cs == 1 ? PD4 : 0); - else if (slave->bus == 2) - pins = PD5 | PD6 | PD7 | (slave->cs == 1 ? PD9 : 0); - else - pins = 0; - if (pins) { - fer = bfin_read_PORTDIO_FER(); - fer &= ~pins; - bfin_write_PORTDIO_FER(fer); - } -#elif defined(__ADSPBF54x__) -#define DO_MUX(port, pin) \ - mux = ((mux & ~PORT_x_MUX_##pin##_MASK) | PORT_x_MUX_##pin##_FUNC_1); \ - fer |= P##port##pin; - u32 mux; - u16 fer; - switch (slave->bus) { - case 0: - mux = bfin_read_PORTE_MUX(); - fer = bfin_read_PORTE_FER(); - /* set SCK/MISO/MOSI */ - DO_MUX(E, 0); - DO_MUX(E, 1); - DO_MUX(E, 2); - switch (slave->cs) { - case 1: DO_MUX(E, 4); break; - case 2: DO_MUX(E, 5); break; - case 3: DO_MUX(E, 6); break; - } - bfin_write_PORTE_MUX(mux); - bfin_write_PORTE_FER(fer); - break; - case 1: - mux = bfin_read_PORTG_MUX(); - fer = bfin_read_PORTG_FER(); - /* set SCK/MISO/MOSI */ - DO_MUX(G, 8); - DO_MUX(G, 9); - DO_MUX(G, 10); - switch (slave->cs) { - case 1: DO_MUX(G, 5); break; - case 2: DO_MUX(G, 6); break; - case 3: DO_MUX(G, 7); break; - } - bfin_write_PORTG_MUX(mux); - bfin_write_PORTG_FER(fer); - break; - case 2: - mux = bfin_read_PORTB_MUX(); - fer = bfin_read_PORTB_FER(); - /* set SCK/MISO/MOSI */ - DO_MUX(B, 12); - DO_MUX(B, 13); - DO_MUX(B, 14); - switch (slave->cs) { - case 1: DO_MUX(B, 9); break; - case 2: DO_MUX(B, 10); break; - case 3: DO_MUX(B, 11); break; - } - bfin_write_PORTB_MUX(mux); - bfin_write_PORTB_FER(fer); - break; - } -#endif -} - int spi_claim_bus(struct spi_slave *slave) { struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); - spi_portmux(slave); + if (is_gpio_cs(slave->cs)) { + unsigned int cs = gpio_cs(slave->cs); + gpio_request(cs, "bfin-spi"); + gpio_direction_output(cs, !bss->flg); + pins[slave->bus][0] = P_DONTCARE; + } else + pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1]; + peripheral_request_list(pins[slave->bus], "bfin-spi"); + write_SPI_CTL(bss, bss->ctl); write_SPI_BAUD(bss, bss->baud); SSYNC(); @@ -314,7 +228,13 @@ int spi_claim_bus(struct spi_slave *slave) void spi_release_bus(struct spi_slave *slave) { struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + + peripheral_free_list(pins[slave->bus]); + if (is_gpio_cs(slave->cs)) + gpio_free(gpio_cs(slave->cs)); + write_SPI_CTL(bss, 0); SSYNC(); } diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index 1e821d9..6eec1c9 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -63,6 +63,26 @@ #if !defined(__ADSPBF512__) && !defined(__ADSPBF514__) #define ADI_CMDS_NETWORK 1 #define CONFIG_BFIN_MAC +#define CONFIG_BFIN_MAC_PINS \ + { \ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxD2, \ + P_MII0_ETxD3, \ + P_MII0_ETxEN, \ + P_MII0_TxCLK, \ + P_MII0_PHYINT, \ + P_MII0_COL, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxD2, \ + P_MII0_ERxD3, \ + P_MII0_ERxDV, \ + P_MII0_ERxCLK, \ + P_MII0_CRS, \ + P_MII0_MDC, \ + P_MII0_MDIO, \ + 0 } #define CONFIG_NETCONSOLE 1 #define CONFIG_NET_MULTI 1 #endif @@ -117,8 +137,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index 711fa27..82396d0 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -134,8 +134,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* @@ -160,23 +158,19 @@ /* define to enable run status via led */ /* #define CONFIG_STATUS_LED */ #ifdef CONFIG_STATUS_LED +#define CONFIG_GPIO_LED #define CONFIG_BOARD_SPECIFIC_LED -#ifndef __ASSEMBLY__ -typedef unsigned int led_id_t; -void __led_init(led_id_t mask, int state); -void __led_set(led_id_t mask, int state); -void __led_toggle(led_id_t mask); -#endif /* use LED0 to indicate booting/alive */ #define STATUS_LED_BOOT 0 -#define STATUS_LED_BIT 1 +#define STATUS_LED_BIT GPIO_PF8 #define STATUS_LED_STATE STATUS_LED_ON #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4) /* use LED1 to indicate crash */ #define STATUS_LED_CRASH 1 -#define STATUS_LED_BIT1 2 +#define STATUS_LED_BIT1 GPIO_PG11 #define STATUS_LED_STATE1 STATUS_LED_ON #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* #define STATUS_LED_BIT2 GPIO_PG12 */ #endif diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h new file mode 100644 index 0000000..eb3a2b7 --- /dev/null +++ b/include/configs/bf527-ad7160-eval.h @@ -0,0 +1,148 @@ +/* + * U-boot - Configuration file for BF527 AD7160-EVAL board + */ + +#ifndef __CONFIG_BF527_AD7160_EVAL_H__ +#define __CONFIG_BF527_AD7160_EVAL_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf527-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 24000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 25 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 10 +#define CONFIG_MEM_SIZE 64 + +#define CONFIG_EBIU_SDRRC_VAL 0x03F6 +#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) + +#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (640 * 1024) + + +/* + * NAND Settings + * (can't be used same time as ethernet) + */ +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) +# define CONFIG_BFIN_NFC +# define CONFIG_BFIN_NFC_BOOTROM_ECC +#endif +#ifdef CONFIG_BFIN_NFC +#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 +#define CONFIG_DRIVER_NAND_BFIN +#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#endif + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 259 + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + + +/* + * Env Storage Settings + */ +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x2000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#endif + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 + + +/* + * SPI_MMC Settings + */ +#define CONFIG_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_SPI_MMC +#define CONFIG_SPI_MMC_DEFAULT_CS (7 + GPIO_PH3) + + +/* + * Misc Settings + */ +#define CONFIG_MISC_INIT_R +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index 7800c32..07e4ce8 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -138,8 +138,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index c80ddca..37a7059 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -136,8 +136,6 @@ } while (0) #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 #endif diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 80c4884..02c8bc3 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -180,8 +180,6 @@ } while (0) #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 #endif @@ -230,23 +228,19 @@ /* define to enable run status via led */ /* #define CONFIG_STATUS_LED */ #ifdef CONFIG_STATUS_LED +#define CONFIG_GPIO_LED #define CONFIG_BOARD_SPECIFIC_LED -#ifndef __ASSEMBLY__ -typedef unsigned int led_id_t; -void __led_init(led_id_t mask, int state); -void __led_set(led_id_t mask, int state); -void __led_toggle(led_id_t mask); -#endif -/* use LED1 to indicate booting/alive */ +/* use LED0 to indicate booting/alive */ #define STATUS_LED_BOOT 0 -#define STATUS_LED_BIT 1 +#define STATUS_LED_BIT GPIO_PF2 #define STATUS_LED_STATE STATUS_LED_ON #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4) -/* use LED2 to indicate crash */ +/* use LED1 to indicate crash */ #define STATUS_LED_CRASH 1 -#define STATUS_LED_BIT1 2 +#define STATUS_LED_BIT1 GPIO_PF3 #define STATUS_LED_STATE1 STATUS_LED_ON #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* #define STATUS_LED_BIT2 GPIO_PF4 */ #endif /* define to enable splash screen support */ diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index cf40d06..39bbb41 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -132,7 +132,6 @@ #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_READY PF12 #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ @@ -141,13 +140,7 @@ #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTHIO() & BFIN_NAND_READY) -#define NAND_PLAT_INIT() \ - do { \ - bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \ - bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \ - bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \ - } while (0) +#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12 /* @@ -155,8 +148,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 92ceb38..96704d7 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -137,8 +137,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* @@ -157,7 +155,6 @@ #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_READY PF3 #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ @@ -166,13 +163,7 @@ #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTFIO() & BFIN_NAND_READY) -#define NAND_PLAT_INIT() \ - do { \ - bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~BFIN_NAND_READY); \ - bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~BFIN_NAND_READY); \ - bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | BFIN_NAND_READY); \ - } while (0) +#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3 /* @@ -268,8 +259,6 @@ #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 -/* #define CONFIG_BF537_STAMP_LEDCMD 1 */ - /* Define if want to do post memory test */ #undef CONFIG_POST #ifdef CONFIG_POST diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index 59e0565..1c14b6b 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -134,8 +134,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index f9c9711..60cca0c 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -140,8 +140,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h index 0be170c..0c0204f 100644 --- a/include/configs/bf561-acvilon.h +++ b/include/configs/bf561-acvilon.h @@ -131,7 +131,6 @@ #define CONFIG_ENV_SECT_SIZE (1056 * 8) #define CONFIG_ENV_OFFSET ((16 + 256) * 1056) #define CONFIG_ENV_SIZE (8 * 1056) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) /* @@ -145,7 +144,6 @@ #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3)) -#define BFIN_NAND_READY PF10 #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ @@ -154,12 +152,7 @@ #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO0_FLAG_D() & BFIN_NAND_READY) -#define NAND_PLAT_INIT() \ - do { \ - bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() & ~BFIN_NAND_READY); \ - bfin_write_FIO0_INEN(bfin_read_FIO0_INEN() | BFIN_NAND_READY); \ - } while (0) +#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10 /* diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 1e3fdef..036bfe4 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -151,8 +151,6 @@ } while (0) #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 #endif diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 1896cf5..901a32f 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -83,6 +83,7 @@ # define CONFIG_CMD_CPLBINFO # define CONFIG_CMD_ELF # define CONFIG_ELF_SIMPLE_LOAD +# define CONFIG_CMD_GPIO # define CONFIG_CMD_KGDB # define CONFIG_CMD_REGINFO # define CONFIG_CMD_STRINGS @@ -247,12 +248,26 @@ # define CONFIG_SYS_AUTOLOAD "no" # endif # endif +# define CONFIG_IP_DEFRAG # define CONFIG_NET_RETRY_COUNT 20 #endif /* + * I2C Settings + */ +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) +# ifndef CONFIG_SYS_I2C_SPEED +# define CONFIG_SYS_I2C_SPEED 50000 +# endif +# ifndef CONFIG_SYS_I2C_SLAVE +# define CONFIG_SYS_I2C_SLAVE 0 +# endif +#endif + +/* * Misc Settings */ +#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */ #define CONFIG_LZMA #endif diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h index ad1dd12..e0c6d53 100644 --- a/include/configs/cm-bf527.h +++ b/include/configs/cm-bf527.h @@ -117,8 +117,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index 8d0bc12..742df9c 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -119,8 +119,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index bbea3ab..9def99f 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -120,8 +120,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h index 93c4c8d..63b9399 100644 --- a/include/configs/cm-bf548.h +++ b/include/configs/cm-bf548.h @@ -107,8 +107,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h index 2eef5ef..2c0a263 100644 --- a/include/configs/ibf-dsp561.h +++ b/include/configs/ibf-dsp561.h @@ -58,6 +58,18 @@ /* + * Network Settings + */ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_NET_MULTI +#define CONFIG_DRIVER_AX88180 1 +#define AX88180_BASE 0x2c000000 +#define CONFIG_HOSTNAME ibf-dsp561 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* * Flash Settings */ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ @@ -126,8 +138,6 @@ } while (0) #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 #endif diff --git a/include/configs/ip04.h b/include/configs/ip04.h index 425a745..c024d78 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -116,7 +116,6 @@ #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_READY PF10 #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ @@ -125,14 +124,7 @@ #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY) -#define NAND_PLAT_INIT() \ - do { \ - bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \ - bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \ - bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \ - bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \ - } while (0) +#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10 /* diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h index 9c04d8a..52055e8 100644 --- a/include/configs/tcm-bf518.h +++ b/include/configs/tcm-bf518.h @@ -106,8 +106,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 409a042..24ce8f8 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -120,8 +120,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/environment.h b/include/environment.h index 203f731..fbccf6a 100644 --- a/include/environment.h +++ b/include/environment.h @@ -74,15 +74,24 @@ #endif /* CONFIG_ENV_IS_IN_FLASH */ #if defined(CONFIG_ENV_IS_IN_NAND) -# ifndef CONFIG_ENV_OFFSET -# error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_NAND" -# endif +# if defined(CONFIG_ENV_OFFSET_OOB) +# ifdef CONFIG_ENV_OFFSET_REDUND +# error "CONFIG_ENV_OFFSET_REDUND is not supported when CONFIG_ENV_OFFSET_OOB" +# error "is set" +# endif +extern unsigned long nand_env_oob_offset; +# define CONFIG_ENV_OFFSET nand_env_oob_offset +# else +# ifndef CONFIG_ENV_OFFSET +# error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_NAND" +# endif +# ifdef CONFIG_ENV_OFFSET_REDUND +# define CONFIG_SYS_REDUNDAND_ENVIRONMENT +# endif +# endif /* CONFIG_ENV_OFFSET_OOB */ # ifndef CONFIG_ENV_SIZE # error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_NAND" # endif -# ifdef CONFIG_ENV_OFFSET_REDUND -# define CONFIG_SYS_REDUNDAND_ENVIRONMENT -# endif #endif /* CONFIG_ENV_IS_IN_NAND */ #if defined(CONFIG_ENV_IS_IN_MG_DISK) diff --git a/include/nand.h b/include/nand.h index 2a81597..8bdf419 100644 --- a/include/nand.h +++ b/include/nand.h @@ -130,3 +130,12 @@ void board_nand_select_device(struct nand_chip *nand, int chip); __attribute__((noreturn)) void nand_boot(void); #endif + +#ifdef CONFIG_ENV_OFFSET_OOB +#define ENV_OOB_MARKER 0x30425645 /*"EVB0" in little-endian -- offset is stored + as block number*/ +#define ENV_OOB_MARKER_OLD 0x30564e45 /*"ENV0" in little-endian -- offset is + stored as byte number */ +#define ENV_OFFSET_SIZE 8 +int get_nand_env_oob(nand_info_t *nand, unsigned long *result); +#endif diff --git a/include/status_led.h b/include/status_led.h index 9dbf01f..f213595 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -346,9 +346,6 @@ void status_led_set (int led, int state); #elif defined(CONFIG_NIOS2) /* XXX empty just to avoid the error */ /************************************************************************/ -#elif defined(CONFIG_BLACKFIN) -/* XXX empty just to avoid the error */ -/************************************************************************/ #elif defined(CONFIG_V38B) # define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */ |