diff options
53 files changed, 689 insertions, 418 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 4ee0e9a..fe851f1 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -58,7 +58,9 @@ COBJS-$(CONFIG_P1021) += ddr-gen3.o COBJS-$(CONFIG_P1022) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o +COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index fe2b52d..f15d43c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -179,7 +179,7 @@ int checkcpu (void) #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { - printf(" FMAN%d: %s MHz\n", i, + printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freqFMan[i])); } #endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index d491e2a..5d5b4c2 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -39,10 +39,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_MPC8536 -extern void fsl_serdes_init(void); -#endif - #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -185,9 +181,6 @@ void cpu_init_f (void) /* Config QE ioports */ config_qe_ioports(); #endif -#if defined(CONFIG_MPC8536) - fsl_serdes_init(); -#endif #if defined(CONFIG_FSL_DMA) dma_init(); #endif @@ -332,6 +325,11 @@ int cpu_init_r(void) qe_reset(); #endif +#if defined(CONFIG_SYS_HAS_SERDES) + /* needs to be in ram since code uses global static vars */ + fsl_serdes_init(); +#endif + #if defined(CONFIG_MP) setup_mp(); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 2628cc5..932466e 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -298,17 +298,17 @@ void fdt_add_enet_stashing(void *fdt) } #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) -static void ft_fixup_clks(void *blob, const char *alias, unsigned long freq) +static void ft_fixup_clks(void *blob, const char *compat, u32 offset, + unsigned long freq) { - const char *path = fdt_get_alias(blob, alias); - - int off = fdt_path_offset(blob, path); + phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; + int off = fdt_node_offset_by_compat_reg(blob, compat, phys); if (off >= 0) { off = fdt_setprop_cell(blob, off, "clock-frequency", freq); if (off > 0) printf("WARNING enable to set clock-frequency " - "for %s: %s\n", alias, fdt_strerror(off)); + "for %s: %s\n", compat, fdt_strerror(off)); } } @@ -317,14 +317,17 @@ static void ft_fixup_dpaa_clks(void *blob) sys_info_t sysinfo; get_sys_info(&sysinfo); - ft_fixup_clks(blob, "fman0", sysinfo.freqFMan[0]); + ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, + sysinfo.freqFMan[0]); #if (CONFIG_SYS_NUM_FMAN == 2) - ft_fixup_clks(blob, "fman1", sysinfo.freqFMan[1]); + ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, + sysinfo.freqFMan[1]); #endif #ifdef CONFIG_SYS_DPAA_PME - ft_fixup_clks(blob, "pme", sysinfo.freqPME); + do_fixup_by_compat_u32(blob, "fsl,pme", + "clock-frequency", sysinfo.freqPME, 1); #endif } #else @@ -400,6 +403,11 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", bd->bi_brgfreq, 1); #endif +#ifdef CONFIG_FSL_CORENET + do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", + "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); +#endif + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); #ifdef CONFIG_MP diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c index 7e72f5f..6dadeb8 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c @@ -66,10 +66,11 @@ #define FSL_SRDSCR3_LANEE_SGMII 0x00000000 #define FSL_SRDSCR3_LANEE_SATA 0x00150005 - #define SRDS1_MAX_LANES 8 #define SRDS2_MAX_LANES 2 +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE}, [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, @@ -86,39 +87,12 @@ static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl device) { - int i; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 pordevsr = in_be32(&gur->pordevsr); - u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int ret = (1 << device) & serdes1_prtcl_map; - u32 srds2_cfg = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> - GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT; - - debug("%s: dev = %d\n", __FUNCTION__, device); - debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg); - debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_cfg); - - if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { - printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg); - return 0; - } - - if (srds2_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { - printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_cfg); - return 0; - } - - for (i = 0; i < SRDS1_MAX_LANES; i++) { - if (serdes1_cfg_tbl[srds1_cfg][i] == device) - return 1; - } - for (i = 0; i < SRDS2_MAX_LANES; i++) { - if (serdes2_cfg_tbl[srds2_cfg][i] == device) - return 1; - } + if (ret) + return ret; - return 0; + return (1 << device) & serdes2_prtcl_map; } void fsl_serdes_init(void) @@ -126,13 +100,20 @@ void fsl_serdes_init(void) void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR; u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS); - u32 srds2_io_sel; + u32 srds1_io_sel, srds2_io_sel; u32 tmp; + int lane; + + srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; /* parse the SRDS2_IO_SEL of PORDEVSR */ srds2_io_sel = (pordevsr & GUTS_PORDEVSR_SERDES2_IO_SEL) >> GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT; + debug("PORDEVSR[SRDS1_IO_SEL] = %x\n", srds1_io_sel); + debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_io_sel); + switch (srds2_io_sel) { case 1: /* Lane A - SATA1, Lane E - SATA2 */ /* CR 0 */ @@ -246,4 +227,23 @@ void fsl_serdes_init(void) default: break; } + + if (srds1_io_sel > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[SRDS1_IO_SEL] = %d\n", srds1_io_sel); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_io_sel][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds2_io_sel > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } } diff --git a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c index 6b0fbf2..e4c9c22 100644 --- a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c @@ -17,6 +17,8 @@ #define SRDS1_MAX_LANES 4 #define SRDS2_MAX_LANES 2 +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { [0x00] = {NONE, NONE, NONE, NONE}, [0x01] = {NONE, NONE, NONE, NONE}, @@ -73,26 +75,40 @@ static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl device) { + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; - unsigned int i; + int lane; - debug("%s: dev = %d\n", __FUNCTION__, device); - debug("PORDEVSR[IO_SEL] = 0x%x\n", srds_cfg); + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { - printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds_cfg); - return 0; + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); } - for (i = 0; i < SRDS1_MAX_LANES; i++) { - if (serdes1_cfg_tbl[srds_cfg][i] == device) - return 1; - if (serdes2_cfg_tbl[srds_cfg][i] == device) - return 1; + if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; } - return 0; + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } } diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 22f3423..dc3da16 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -80,10 +80,16 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), CPU_TYPE_ENTRY(P2020, P2020_E, 2), + CPU_TYPE_ENTRY(P3041, P3041, 4), + CPU_TYPE_ENTRY(P3041, P3041_E, 4), CPU_TYPE_ENTRY(P4040, P4040, 4), CPU_TYPE_ENTRY(P4040, P4040_E, 4), CPU_TYPE_ENTRY(P4080, P4080, 8), CPU_TYPE_ENTRY(P4080, P4080_E, 8), + CPU_TYPE_ENTRY(P5010, P5010, 1), + CPU_TYPE_ENTRY(P5010, P5010_E, 1), + CPU_TYPE_ENTRY(P5020, P5020, 2), + CPU_TYPE_ENTRY(P5020, P5020_E, 2), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index d88c282..f70699d 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -44,8 +44,12 @@ defined(CONFIG_P1021) || defined(CONFIG_P1022) || \ defined(CONFIG_P2020) || defined(CONFIG_MPC8641) #define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_PPC_P3041) +#define CONFIG_MAX_CPUS 4 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 +#elif defined(CONFIG_PPC_P5020) +#define CONFIG_MAX_CPUS 2 #else #define CONFIG_MAX_CPUS 1 #endif diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index bb87543..dc5c579 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -1,5 +1,5 @@ /* - * Copyright 2007,2009 Freescale Semiconductor, Inc. + * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -29,8 +29,8 @@ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); -void ft_fsl_pci_setup(void *blob, const char *pci_alias, - struct pci_controller *hose); +void ft_fsl_pci_setup(void *blob, const char *pci_compat, + struct pci_controller *hose, unsigned long ctrl_addr); /* * Common PCI/PCIE Register structure for mpc85xx and mpc86xx @@ -202,4 +202,82 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, x.pci_num = num; \ } +#define __FT_FSL_PCI_SETUP(blob, compat, num) \ + ft_fsl_pci_setup(blob, compat, &pci##num##_hose, \ + CONFIG_SYS_PCI##num##_ADDR) + +#define __FT_FSL_PCI_DEL(blob, compat, num) \ + ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCI##num##_ADDR) + +#define __FT_FSL_PCIE_SETUP(blob, compat, num) \ + ft_fsl_pci_setup(blob, compat, &pcie##num##_hose, \ + CONFIG_SYS_PCIE##num##_ADDR) + +#define __FT_FSL_PCIE_DEL(blob, compat, num) \ + ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCIE##num##_ADDR) + +#ifdef CONFIG_PCI1 +#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1) +#else +#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 1) +#endif + +#ifdef CONFIG_PCI2 +#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2) +#else +#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 2) +#endif + +#ifdef CONFIG_PCIE1 +#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1) +#else +#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 1) +#endif + +#ifdef CONFIG_PCIE2 +#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2) +#else +#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 2) +#endif + +#ifdef CONFIG_PCIE3 +#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3) +#else +#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 3) +#endif + +#ifdef CONFIG_PCIE4 +#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4) +#else +#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 4) +#endif + +#if defined(CONFIG_FSL_CORENET) +#define FSL_PCIE_COMPAT "fsl,p4080-pcie" +#define FT_FSL_PCI_SETUP \ + FT_FSL_PCIE1_SETUP; \ + FT_FSL_PCIE2_SETUP; \ + FT_FSL_PCIE3_SETUP; \ + FT_FSL_PCIE4_SETUP; +#elif defined(CONFIG_MPC85xx) +#define FSL_PCI_COMPAT "fsl,mpc8540-pci" +#define FSL_PCIE_COMPAT "fsl,mpc8548-pcie" +#define FT_FSL_PCI_SETUP \ + FT_FSL_PCI1_SETUP; \ + FT_FSL_PCI2_SETUP; \ + FT_FSL_PCIE1_SETUP; \ + FT_FSL_PCIE2_SETUP; \ + FT_FSL_PCIE3_SETUP; +#elif defined(CONFIG_MPC86xx) +#define FSL_PCI_COMPAT "fsl,mpc8610-pci" +#define FSL_PCIE_COMPAT "fsl,mpc8641-pcie" +#define FT_FSL_PCI_SETUP \ + FT_FSL_PCI1_SETUP; \ + FT_FSL_PCIE1_SETUP; \ + FT_FSL_PCIE2_SETUP; +#else +#error FT_FSL_PCI_SETUP not defined +#endif + + #endif diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index d4839f4..c7877b9 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -44,5 +44,6 @@ enum srds_prtcl { }; int is_serdes_configured(enum srds_prtcl device); +void fsl_serdes_init(void); #endif /* __FSL_SERDES_H */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 4e665d3..b1d219b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2060,8 +2060,17 @@ typedef struct ccsr_sec { #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000 +#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000 +#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 +#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 +#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 +#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) +#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 +#else +#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000 +#endif #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 @@ -2138,6 +2147,17 @@ typedef struct ccsr_sec { #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_PCI1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) +#define CONFIG_SYS_PCI2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET) +#define CONFIG_SYS_PCIE1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET) +#define CONFIG_SYS_PCIE2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET) +#define CONFIG_SYS_PCIE3_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET) + #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index b9e02db..4bebb68 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -1257,6 +1257,23 @@ extern immap_t *immr; #define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000) #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET) +#define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000 +#ifdef CONFIG_MPC8610 +#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0xa000 +#else +#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0x8000 +#endif +#define CONFIG_SYS_MPC86xx_PCIE2_OFFSET 0x9000 + +#define CONFIG_SYS_PCI1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI1_OFFSET) +#define CONFIG_SYS_PCI2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI2_OFFSET) +#define CONFIG_SYS_PCIE1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE1_OFFSET) +#define CONFIG_SYS_PCIE2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE2_OFFSET) + #define CONFIG_SYS_TSEC1_OFFSET 0x24000 #define CONFIG_SYS_MDIO1_OFFSET 0x24000 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 844552c..89f283a 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1052,10 +1052,16 @@ #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 #define SVR_P2020_E 0x80EA00 +#define SVR_P3041 0x821103 +#define SVR_P3041_E 0x821903 #define SVR_P4040 0x820100 #define SVR_P4040_E 0x820900 #define SVR_P4080 0x820000 #define SVR_P4080_E 0x820800 +#define SVR_P5010 0x822100 +#define SVR_P5010_E 0x822900 +#define SVR_P5020 0x822000 +#define SVR_P5020_E 0x822800 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 4f7d935..671f9e9 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -292,14 +292,6 @@ void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -#endif -#ifdef CONFIG_PCI2 - ft_fsl_pci_setup(blob, "pci1", &pci2_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); -#endif + FT_FSL_PCI_SETUP; } #endif diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 50ca3ca..c8e0856 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -396,26 +396,8 @@ void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -#else - ft_fsl_pci_setup(blob, "pci0", NULL); -#endif -#ifdef CONFIG_PCIE2 - ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); -#else - ft_fsl_pci_setup(blob, "pci1", NULL); -#endif -#ifdef CONFIG_PCIE2 - ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); -#else - ft_fsl_pci_setup(blob, "pci2", NULL); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); -#else - ft_fsl_pci_setup(blob, "pci3", NULL); -#endif + FT_FSL_PCI_SETUP; + #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 581d5f2..da3a2b6 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007,2009 Freescale Semiconductor, Inc. + * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -360,19 +360,8 @@ void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + FT_FSL_PCI_SETUP; -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -#endif -#ifdef CONFIG_PCIE2 - ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci2", &pcie3_hose); -#endif -#ifdef CONFIG_PCIE3 - ft_fsl_pci_setup(blob, "pci3", &pcie2_hose); -#endif #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index f016995..23e552b 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007, 200 Freescale Semiconductor, Inc. + * Copyright 2004, 2007, 2009-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> * @@ -388,11 +388,6 @@ int last_stage_init(void) #if defined(CONFIG_OF_BOARD_SETUP) void ft_pci_setup(void *blob, bd_t *bd) { -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); -#endif + FT_FSL_PCI_SETUP; } #endif diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 036bf95..bd859e4 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007,2009 Freescale Semiconductor, Inc. + * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> * @@ -426,11 +426,6 @@ void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); -#endif + FT_FSL_PCI_SETUP; } #endif diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 81e8ff5..01b7dcb 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor. + * Copyright 2009-2010 Freescale Semiconductor. * * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> * @@ -635,9 +635,8 @@ void ft_board_setup(void *blob, bd_t *bd) #endif ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); -#endif + FT_FSL_PCI_SETUP; + fdt_board_fixup_esdhc(blob, bd); fdt_board_fixup_qe_uart(blob, bd); fdt_board_fixup_qe_usb(blob, bd); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 81d481a..6b96dfc 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -345,15 +345,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); -#ifdef CONFIG_PCIE3 - ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); -#endif -#ifdef CONFIG_PCIE2 - ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); -#endif + FT_FSL_PCI_SETUP; + #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 2ef7b23..6578f58 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -1,5 +1,5 @@ /* - * Copyright 2007,2009 Freescale Semiconductor, Inc. + * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -309,15 +309,7 @@ ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); -#endif -#ifdef CONFIG_PCIE2 - ft_fsl_pci_setup(blob, "pci2", &pcie2_hose); -#endif + FT_FSL_PCI_SETUP; } #endif diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c index bd357b8..8c8ce95 100644 --- a/board/freescale/mpc8641hpcn/law.c +++ b/board/freescale/mpc8641hpcn/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008,2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -32,14 +32,14 @@ * * 0x0000_0000 0x7fff_ffff DDR 2G * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT) - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0x8000_0000 0x9fff_ffff PCIE1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCIE2 MEM 512M * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT) * 0x8000_0000 0x9fff_ffff RapidIO 512M * endif * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT) - * 0xffc0_0000 0xffc0_ffff PCI1 IO 64K - * 0xffc1_0000 0xffc1_ffff PCI2 IO 64K + * 0xffc0_0000 0xffc0_ffff PCIE1 IO 64K + * 0xffc1_0000 0xffc1_ffff PCIE2 IO 64K * 0xffe0_0000 0xffef_ffff CCSRBAR 1M * 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K * 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M @@ -54,10 +54,10 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), #endif #ifdef CONFIG_PCI - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2), #elif defined(CONFIG_RIO) SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), #endif diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index b352c33..d86ca12 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -1,5 +1,5 @@ /* - * Copyright 2006, 2007 Freescale Semiconductor. + * Copyright 2006, 2007, 2010 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -129,21 +129,21 @@ fixed_sdram(void) #if defined(CONFIG_PCI) -static struct pci_controller pci1_hose; +static struct pci_controller pcie1_hose; #endif /* CONFIG_PCI */ -#ifdef CONFIG_PCI2 -static struct pci_controller pci2_hose; -#endif /* CONFIG_PCI2 */ +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif /* CONFIG_PCIE2 */ int first_free_busno = 0; void pci_init_board(void) { -#ifdef CONFIG_PCI1 +#ifdef CONFIG_PCIE1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; + struct pci_controller *hose = &pcie1_hose; struct pci_region *r = hose->regions; volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; @@ -169,16 +169,16 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, + CONFIG_SYS_PCIE1_MEM_BUS, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, + CONFIG_SYS_PCIE1_IO_BUS, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; @@ -195,8 +195,8 @@ void pci_init_board(void) * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ - in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT - + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000))); + in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT + + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); } else { puts("PCI-EXPRESS 1: Disabled\n"); @@ -204,26 +204,26 @@ void pci_init_board(void) } #else puts("PCI-EXPRESS1: Disabled\n"); -#endif /* CONFIG_PCI1 */ +#endif /* CONFIG_PCIE1 */ -#ifdef CONFIG_PCI2 +#ifdef CONFIG_PCIE2 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; - struct pci_controller *hose = &pci2_hose; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; + struct pci_controller *hose = &pcie2_hose; struct pci_region *r = hose->regions; /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI2_MEM_BUS, - CONFIG_SYS_PCI2_MEM_PHYS, - CONFIG_SYS_PCI2_MEM_SIZE, + CONFIG_SYS_PCIE2_MEM_BUS, + CONFIG_SYS_PCIE2_MEM_PHYS, + CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI2_IO_BUS, - CONFIG_SYS_PCI2_IO_PHYS, - CONFIG_SYS_PCI2_IO_SIZE, + CONFIG_SYS_PCIE2_IO_BUS, + CONFIG_SYS_PCIE2_IO_PHYS, + CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; @@ -238,7 +238,7 @@ void pci_init_board(void) } #else puts("PCI-EXPRESS 2: Disabled\n"); -#endif /* CONFIG_PCI2 */ +#endif /* CONFIG_PCIE2 */ } @@ -253,12 +253,7 @@ ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -#endif -#ifdef CONFIG_PCI2 - ft_fsl_pci_setup(blob, "pci1", &pci2_hose); -#endif + FT_FSL_PCI_SETUP; /* * Warn if it looks like the device tree doesn't match u-boot. diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index be692cb..5cdee9f 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -322,23 +322,7 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci0", &pcie1_hose); -#else - ft_fsl_pci_setup(blob, "pci0", NULL); -#endif - -#ifdef CONFIG_PCIE2 - ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); -#else - ft_fsl_pci_setup(blob, "pci1", NULL); -#endif - -#ifdef CONFIG_PCIE3 - ft_fsl_pci_setup(blob, "pci2", &pcie3_hose); -#else - ft_fsl_pci_setup(blob, "pci2", NULL); -#endif + FT_FSL_PCI_SETUP; #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index aa2f64c..97d4f83 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -100,16 +100,5 @@ void pci_init_board(void) void ft_pci_board_setup(void *blob) { -/* According to h/w manual, PCIE2 is at lower address(0x9000) - * than PCIE1(0xa000). - * Hence PCIE2 is made to occupy the pci1 position in dts to - * keep the addresses sorted there. - * Generally the case with all FSL SOCs. - */ -#ifdef CONFIG_PCIE2 - ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); -#endif + FT_FSL_PCI_SETUP; } diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index be4b2eb..3fd1b34 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -366,15 +366,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); -#ifdef CONFIG_PCIE3 - ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); -#endif -#ifdef CONFIG_PCIE2 - ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); -#endif + FT_FSL_PCI_SETUP; + #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index d62cfd1..733979c 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -398,11 +398,9 @@ int last_stage_init(void) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); + +#ifdef CONFIG_FSL_PCI_INIT + FT_FSL_PCI_SETUP; #endif } #endif diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c index d20fa51..705e1c2 100644 --- a/board/sbc8641d/law.c +++ b/board/sbc8641d/law.c @@ -32,11 +32,11 @@ * * 0x0000_0000 DDR 256M * 0x1000_0000 DDR2 256M - * 0x8000_0000 PCI1 MEM 512M - * 0xa000_0000 PCI2 MEM 512M + * 0x8000_0000 PCIE1 MEM 512M + * 0xa000_0000 PCIE2 MEM 512M * 0xc000_0000 RapidIO 512M - * 0xe200_0000 PCI1 IO 16M - * 0xe300_0000 PCI2 IO 16M + * 0xe200_0000 PCIE1 IO 16M + * 0xe300_0000 PCIE2 IO 16M * 0xf800_0000 CCSRBAR 2M * 0xfe00_0000 FLASH (boot bank) 32M * @@ -49,11 +49,11 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), #endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) }; diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index c4e9875..54b2d0b 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -191,16 +191,16 @@ static struct pci_config_table pci_fsl86xxads_config_table[] = { }; #endif -static struct pci_controller pci1_hose = { +static struct pci_controller pcie1_hose = { #ifndef CONFIG_PCI_PNP config_table:pci_mpc86xxcts_config_table #endif }; #endif /* CONFIG_PCI */ -#ifdef CONFIG_PCI2 -static struct pci_controller pci2_hose; -#endif /* CONFIG_PCI2 */ +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif /* CONFIG_PCIE2 */ int first_free_busno = 0; @@ -212,10 +212,10 @@ void pci_init_board(void) uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) >> MPC8641_PORDEVSR_IO_SEL_SHIFT; -#ifdef CONFIG_PCI1 +#ifdef CONFIG_PCIE1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; + struct pci_controller *hose = &pcie1_hose; struct pci_region *r = hose->regions; #ifdef DEBUG uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) @@ -236,16 +236,16 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, + CONFIG_SYS_PCIE1_MEM_BUS, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, + CONFIG_SYS_PCIE1_IO_BUS, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; @@ -264,26 +264,26 @@ void pci_init_board(void) } #else puts("PCI-EXPRESS1: Disabled\n"); -#endif /* CONFIG_PCI1 */ +#endif /* CONFIG_PCIE1 */ -#ifdef CONFIG_PCI2 +#ifdef CONFIG_PCIE2 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; - struct pci_controller *hose = &pci2_hose; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; + struct pci_controller *hose = &pcie2_hose; struct pci_region *r = hose->regions; /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI2_MEM_BUS, - CONFIG_SYS_PCI2_MEM_PHYS, - CONFIG_SYS_PCI2_MEM_SIZE, + CONFIG_SYS_PCIE2_MEM_BUS, + CONFIG_SYS_PCIE2_MEM_PHYS, + CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI2_IO_BUS, - CONFIG_SYS_PCI2_IO_PHYS, - CONFIG_SYS_PCI2_IO_SIZE, + CONFIG_SYS_PCIE2_IO_BUS, + CONFIG_SYS_PCIE2_IO_PHYS, + CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; @@ -298,7 +298,7 @@ void pci_init_board(void) } #else puts("PCI-EXPRESS 2: Disabled\n"); -#endif /* CONFIG_PCI2 */ +#endif /* CONFIG_PCIE2 */ } @@ -308,12 +308,7 @@ void ft_board_setup (void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -#endif -#ifdef CONFIG_PCI2 - ft_fsl_pci_setup(blob, "pci1", &pci2_hose); -#endif + FT_FSL_PCI_SETUP; } #endif diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index fc2a6cb..dda2cb6 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -687,12 +687,7 @@ void ft_board_setup (void *blob, bd_t *bd) { ft_cpu_setup (blob, bd); -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); -#endif + FT_FSL_PCI_SETUP; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c index 3a81827..ece7882 100644 --- a/board/xes/common/fsl_8xxx_pci.c +++ b/board/xes/common/fsl_8xxx_pci.c @@ -398,18 +398,6 @@ void pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_pci_setup(void *blob, bd_t *bd) { - /* TODO - make node name (eg pci0) dynamic */ -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -#endif -#ifdef CONFIG_PCIE1 - ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); -#endif -#ifdef CONFIG_PCIE2 - ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); -#endif -#ifdef CONFIG_PCIE3 - ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); -#endif + FT_FSL_PCI_SETUP; } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/common/fdt_support.c b/common/fdt_support.c index 4d87135..718b635 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -2,6 +2,8 @@ * (C) Copyright 2007 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com * + * Copyright 2010 Freescale Semiconductor, Inc. + * * See file CREDITS for list of people who contributed to this * project. * @@ -861,3 +863,292 @@ void fdt_del_node_and_alias(void *blob, const char *alias) off = fdt_path_offset(blob, "/aliases"); fdt_delprop(blob, off, alias); } + +/* Helper to read a big number; size is in cells (not bytes) */ +static inline u64 of_read_number(const __be32 *cell, int size) +{ + u64 r = 0; + while (size--) + r = (r << 32) | be32_to_cpu(*(cell++)); + return r; +} + +static int of_n_cells(const void *blob, int nodeoffset, const char *name) +{ + int np; + const int *ip; + + do { + np = fdt_parent_offset(blob, nodeoffset); + + if (np >= 0) + nodeoffset = np; + ip = (int *)fdt_getprop(blob, nodeoffset, name, NULL); + if (ip) + return be32_to_cpup(ip); + } while (np >= 0); + + /* No #<NAME>-cells property for the root node */ + return 1; +} + +int of_n_addr_cells(const void *blob, int nodeoffset) +{ + return of_n_cells(blob, nodeoffset, "#address-cells"); +} + +int of_n_size_cells(const void *blob, int nodeoffset) +{ + return of_n_cells(blob, nodeoffset, "#size-cells"); +} + +#define PRu64 "%llx" + +/* Max address size we deal with */ +#define OF_MAX_ADDR_CELLS 4 +#define OF_BAD_ADDR ((u64)-1) +#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \ + (ns) > 0) + +/* Debug utility */ +#ifdef DEBUG +static void of_dump_addr(const char *s, const u32 *addr, int na) +{ + printf("%s", s); + while(na--) + printf(" %08x", *(addr++)); + printf("\n"); +} +#else +static void of_dump_addr(const char *s, const u32 *addr, int na) { } +#endif + +/* Callbacks for bus specific translators */ +struct of_bus { + const char *name; + const char *addresses; + void (*count_cells)(void *blob, int offset, + int *addrc, int *sizec); + u64 (*map)(u32 *addr, const u32 *range, + int na, int ns, int pna); + int (*translate)(u32 *addr, u64 offset, int na); +}; + +/* Default translator (generic bus) */ +static void of_bus_default_count_cells(void *blob, int offset, + int *addrc, int *sizec) +{ + if (addrc) + *addrc = of_n_addr_cells(blob, offset); + if (sizec) + *sizec = of_n_size_cells(blob, offset); +} + +static u64 of_bus_default_map(u32 *addr, const u32 *range, + int na, int ns, int pna) +{ + u64 cp, s, da; + + cp = of_read_number(range, na); + s = of_read_number(range + na + pna, ns); + da = of_read_number(addr, na); + + debug("OF: default map, cp="PRu64", s="PRu64", da="PRu64"\n", + cp, s, da); + + if (da < cp || da >= (cp + s)) + return OF_BAD_ADDR; + return da - cp; +} + +static int of_bus_default_translate(u32 *addr, u64 offset, int na) +{ + u64 a = of_read_number(addr, na); + memset(addr, 0, na * 4); + a += offset; + if (na > 1) + addr[na - 2] = a >> 32; + addr[na - 1] = a & 0xffffffffu; + + return 0; +} + +/* Array of bus specific translators */ +static struct of_bus of_busses[] = { + /* Default */ + { + .name = "default", + .addresses = "reg", + .count_cells = of_bus_default_count_cells, + .map = of_bus_default_map, + .translate = of_bus_default_translate, + }, +}; + +static int of_translate_one(void * blob, int parent, struct of_bus *bus, + struct of_bus *pbus, u32 *addr, + int na, int ns, int pna, const char *rprop) +{ + const u32 *ranges; + int rlen; + int rone; + u64 offset = OF_BAD_ADDR; + + /* Normally, an absence of a "ranges" property means we are + * crossing a non-translatable boundary, and thus the addresses + * below the current not cannot be converted to CPU physical ones. + * Unfortunately, while this is very clear in the spec, it's not + * what Apple understood, and they do have things like /uni-n or + * /ht nodes with no "ranges" property and a lot of perfectly + * useable mapped devices below them. Thus we treat the absence of + * "ranges" as equivalent to an empty "ranges" property which means + * a 1:1 translation at that level. It's up to the caller not to try + * to translate addresses that aren't supposed to be translated in + * the first place. --BenH. + */ + ranges = (u32 *)fdt_getprop(blob, parent, rprop, &rlen); + if (ranges == NULL || rlen == 0) { + offset = of_read_number(addr, na); + memset(addr, 0, pna * 4); + debug("OF: no ranges, 1:1 translation\n"); + goto finish; + } + + debug("OF: walking ranges...\n"); + + /* Now walk through the ranges */ + rlen /= 4; + rone = na + pna + ns; + for (; rlen >= rone; rlen -= rone, ranges += rone) { + offset = bus->map(addr, ranges, na, ns, pna); + if (offset != OF_BAD_ADDR) + break; + } + if (offset == OF_BAD_ADDR) { + debug("OF: not found !\n"); + return 1; + } + memcpy(addr, ranges + na, 4 * pna); + + finish: + of_dump_addr("OF: parent translation for:", addr, pna); + debug("OF: with offset: "PRu64"\n", offset); + + /* Translate it into parent bus space */ + return pbus->translate(addr, offset, pna); +} + +/* + * Translate an address from the device-tree into a CPU physical address, + * this walks up the tree and applies the various bus mappings on the + * way. + * + * Note: We consider that crossing any level with #size-cells == 0 to mean + * that translation is impossible (that is we are not dealing with a value + * that can be mapped to a cpu physical address). This is not really specified + * that way, but this is traditionally the way IBM at least do things + */ +u64 __of_translate_address(void *blob, int node_offset, const u32 *in_addr, + const char *rprop) +{ + int parent; + struct of_bus *bus, *pbus; + u32 addr[OF_MAX_ADDR_CELLS]; + int na, ns, pna, pns; + u64 result = OF_BAD_ADDR; + + debug("OF: ** translation for device %s **\n", + fdt_get_name(blob, node_offset, NULL)); + + /* Get parent & match bus type */ + parent = fdt_parent_offset(blob, node_offset); + if (parent < 0) + goto bail; + bus = &of_busses[0]; + + /* Cound address cells & copy address locally */ + bus->count_cells(blob, node_offset, &na, &ns); + if (!OF_CHECK_COUNTS(na, ns)) { + printf("%s: Bad cell count for %s\n", __FUNCTION__, + fdt_get_name(blob, node_offset, NULL)); + goto bail; + } + memcpy(addr, in_addr, na * 4); + + debug("OF: bus is %s (na=%d, ns=%d) on %s\n", + bus->name, na, ns, fdt_get_name(blob, parent, NULL)); + of_dump_addr("OF: translating address:", addr, na); + + /* Translate */ + for (;;) { + /* Switch to parent bus */ + node_offset = parent; + parent = fdt_parent_offset(blob, node_offset); + + /* If root, we have finished */ + if (parent < 0) { + debug("OF: reached root node\n"); + result = of_read_number(addr, na); + break; + } + + /* Get new parent bus and counts */ + pbus = &of_busses[0]; + pbus->count_cells(blob, node_offset, &pna, &pns); + if (!OF_CHECK_COUNTS(pna, pns)) { + printf("%s: Bad cell count for %s\n", __FUNCTION__, + fdt_get_name(blob, node_offset, NULL)); + break; + } + + debug("OF: parent bus is %s (na=%d, ns=%d) on %s\n", + pbus->name, pna, pns, fdt_get_name(blob, parent, NULL)); + + /* Apply bus translation */ + if (of_translate_one(blob, node_offset, bus, pbus, + addr, na, ns, pna, rprop)) + break; + + /* Complete the move up one level */ + na = pna; + ns = pns; + bus = pbus; + + of_dump_addr("OF: one level translation:", addr, na); + } + bail: + + return result; +} + +u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr) +{ + return __of_translate_address(blob, node_offset, in_addr, "ranges"); +} + +/** + * fdt_node_offset_by_compat_reg: Find a node that matches compatiable and + * who's reg property matches a physical cpu address + * + * @blob: ptr to device tree + * @compat: compatiable string to match + * @compat_off: property name + * + */ +int fdt_node_offset_by_compat_reg(void *blob, const char *compat, + phys_addr_t compat_off) +{ + int len, off = fdt_node_offset_by_compatible(blob, -1, compat); + while (off != -FDT_ERR_NOTFOUND) { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len); + if (reg) { + if (compat_off == fdt_translate_address(blob, off, reg)) + return off; + } + off = fdt_node_offset_by_compatible(blob, off, compat); + } + + return -FDT_ERR_NOTFOUND; +} + + diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 628bd59..6589076 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -43,7 +43,8 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_P1013) || defined(CONFIG_P1022) || \ defined(CONFIG_P2010) || defined(CONFIG_P2020) #define FSL_HW_NUM_LAWS 12 -#elif defined(CONFIG_PPC_P4080) +#elif defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P4080) || \ + defined(CONFIG_PPC_P5020) #define FSL_HW_NUM_LAWS 32 #else #error FSL_HW_NUM_LAWS not defined for this platform diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 5a63fa2..001e6eb 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -510,18 +510,25 @@ void fsl_pci_config_unlock(struct pci_controller *hose) #include <libfdt.h> #include <fdt_support.h> -void ft_fsl_pci_setup(void *blob, const char *pci_alias, - struct pci_controller *hose) +void ft_fsl_pci_setup(void *blob, const char *pci_compat, + struct pci_controller *hose, unsigned long ctrl_addr) { - int off = fdt_path_offset(blob, pci_alias); + int off; u32 bus_range[2]; + phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr; + + /* convert ctrl_addr to true physical address */ + p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR; + p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS; + + off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr); if (off < 0) return; /* We assume a cfg_addr not being set means we didn't setup the controller */ if ((hose == NULL) || (hose->cfg_addr == NULL)) { - fdt_del_node_and_alias(blob, pci_alias); + fdt_del_node(blob, off); } else { bus_range[0] = 0; bus_range[1] = hose->last_busno - hose->first_busno; diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index 49a86fd..c133033 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -91,9 +91,6 @@ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ #define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index a014ad0..890a6c9 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -65,6 +65,7 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#define CONFIG_SYS_HAS_SERDES /* has SERDES */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ @@ -125,11 +126,6 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) - /* DDR Setup */ #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index faba353..96fd024 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -79,11 +79,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index fdd3597..23594a7 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -80,10 +80,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 0cc2d47..bc6c5c7 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -75,9 +75,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index bb7bb47..92c2b49 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -103,9 +103,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR3 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 57c2f2f..51e5d06 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -89,10 +89,6 @@ #endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 8382e3c..4d9606e 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -82,10 +82,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) - #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000) /* DDR Setup */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 94e4d24..0d1f779 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -1,5 +1,5 @@ /* - * Copyright 2006 Freescale Semiconductor. + * Copyright 2006, 2010 Freescale Semiconductor. * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -58,8 +58,8 @@ #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ -#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ -#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #endif @@ -122,9 +122,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW #endif -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) - /* * DDR Setup */ @@ -328,43 +325,43 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x0000000c00000000ULL #else -#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_VIRT +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT #endif -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \ +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_PCIE1_IO_VIRT \ | CONFIG_SYS_PHYS_ADDR_HIGH) -#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */ +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ #ifdef CONFIG_PHYS_64BIT /* - * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT. + * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. * This will increase the amount of PCI address space available for * for mapping RAM. */ -#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS #else -#define CONFIG_SYS_PCI2_MEM_BUS (CONFIG_SYS_PCI1_MEM_BUS \ - + CONFIG_SYS_PCI1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ + + CONFIG_SYS_PCIE1_MEM_SIZE) #endif -#define CONFIG_SYS_PCI2_MEM_VIRT (CONFIG_SYS_PCI1_MEM_VIRT \ - + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \ - + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \ - + CONFIG_SYS_PCI1_IO_SIZE) -#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \ - + CONFIG_SYS_PCI1_IO_SIZE) -#define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE +#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ + + CONFIG_SYS_PCIE1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ + + CONFIG_SYS_PCIE1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ + + CONFIG_SYS_PCIE1_IO_SIZE) +#define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ + + CONFIG_SYS_PCIE1_IO_SIZE) +#define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE #if defined(CONFIG_PCI) @@ -393,10 +390,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 /*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT /*PCI video card used*/ -/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ +/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ /* video */ #define CONFIG_VIDEO @@ -409,7 +406,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ATI_RADEON_FB #define CONFIG_VIDEO_LOGO /*#define CONFIG_CONSOLE_CURSOR*/ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -425,8 +422,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE #endif -#define CONFIG_MPC86XX_PCI2 - #endif /* CONFIG_PCI */ #if defined(CONFIG_TSEC_ENET) @@ -497,17 +492,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U /* if CONFIG_PCI: - * BAT2 PCI1 and PCI1 MEM + * BAT2 PCIE1 and PCIE1 MEM * if CONFIG_RIO * BAT2 Rapidio Memory */ #ifdef CONFIG_PCI -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ +#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \ +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ +#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #else /* CONFIG_RIO */ @@ -556,14 +551,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* - * BAT4 PCI1_IO and PCI2_IO + * BAT4 PCIE1_IO and PCIE2_IO */ -#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ +#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \ +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ +#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index b42b5d0..f9d12f5 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -30,6 +30,7 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +#define CONFIG_SYS_HAS_SERDES /* has SERDES */ #define CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS @@ -60,10 +61,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* pci0 */ -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) /* pci1 */ -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) /* pci2 */ - /* DDR Setup */ #define CONFIG_DDR_SPD #define CONFIG_VERY_BIG_RAM diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 3cebbab..fca3cdd 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -129,9 +129,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 569da4f..bf2acbf 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -90,10 +90,6 @@ #endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR3 1 diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 90abe14..d8f2602 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -137,10 +137,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) - /* * DDR Setup */ diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h index c63fd42..8770a8d 100644 --- a/include/configs/XPEDITE5170.h +++ b/include/configs/XPEDITE5170.h @@ -97,8 +97,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* * Diagnostics diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index df5ef78..83aeffd 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -81,7 +81,6 @@ #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) /* * Diagnostics diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 1d6091c..fc4a986 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -99,8 +99,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* * Diagnostics diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 3f4056e..c8b8d0d 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -109,10 +109,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 315eebe..618513a 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -56,8 +56,8 @@ #define CONFIG_SYS_SCRATCH_VA 0xe8000000 #define CONFIG_PCI 1 /* Enable PCIE */ -#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ @@ -108,9 +108,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) - /* * DDR Setup */ @@ -307,23 +304,23 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS -#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BUS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS -#define CONFIG_SYS_PCI1_IO_VIRT CONFIG_SYS_PCI1_IO_BUS -#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS -#define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BUS -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BUS 0xe3000000 -#define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BUS -#define CONFIG_SYS_PCI2_IO_VIRT CONFIG_SYS_PCI2_IO_BUS -#define CONFIG_SYS_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 +#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS +#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS +#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ + +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 +#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS +#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS +#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ #if defined(CONFIG_PCI) @@ -409,10 +406,10 @@ * 0xa000_0000 512M PCI-Express 2 Memory * Changed it for operating from 0xd0000000 */ -#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ +#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U /* @@ -452,10 +449,10 @@ * 0xe300_0000 16M PCI-Express 2 I/0 * Note that this is at 0xe0000000 */ -#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \ +#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U /* diff --git a/include/fdt_support.h b/include/fdt_support.h index fc16159..54af9fe 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -83,6 +83,9 @@ int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size); void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size); void fdt_del_node_and_alias(void *blob, const char *alias); +u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr); +int fdt_node_offset_by_compat_reg(void *blob, const char *compat, + phys_addr_t compat_off); #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ |