diff options
| -rw-r--r-- | include/asm-arm/arch-omap3/clocks_omap3.h | 285 | ||||
| -rw-r--r-- | include/asm-arm/arch-omap3/cpu.h | 402 | ||||
| -rw-r--r-- | include/asm-arm/arch-omap3/mux.h | 412 |
3 files changed, 1099 insertions, 0 deletions
diff --git a/include/asm-arm/arch-omap3/clocks_omap3.h b/include/asm-arm/arch-omap3/clocks_omap3.h new file mode 100644 index 0000000..661407b --- /dev/null +++ b/include/asm-arm/arch-omap3/clocks_omap3.h @@ -0,0 +1,285 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CLOCKS_OMAP3_H_ +#define _CLOCKS_OMAP3_H_ + +#define PLL_STOP 1 /* PER & IVA */ +#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ +#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ +#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ + +/* + * The following configurations are OPP and SysClk value independant + * and hence are defined here. All the other DPLL related values are + * tabulated in lowlevel_init.S. + */ + +/* CORE DPLL */ +#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ +#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ +#define CORE_FUSB_DIV 2 /* 41.5MHz: */ +#define CORE_L4_DIV 2 /* 83MHz : L4 */ +#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ +#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ +#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ + +/* PER DPLL */ +#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ +#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ +#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ +#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ + +#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50)) + +/* MPU DPLL */ + +#define MPU_M_12_ES1 0x0FE +#define MPU_N_12_ES1 0x07 +#define MPU_FSEL_12_ES1 0x05 +#define MPU_M2_12_ES1 0x01 + +#define MPU_M_12_ES2 0x0FA +#define MPU_N_12_ES2 0x05 +#define MPU_FSEL_12_ES2 0x07 +#define MPU_M2_ES2 0x01 + +#define MPU_M_12 0x085 +#define MPU_N_12 0x05 +#define MPU_FSEL_12 0x07 +#define MPU_M2_12 0x01 + +#define MPU_M_13_ES1 0x17D +#define MPU_N_13_ES1 0x0C +#define MPU_FSEL_13_ES1 0x03 +#define MPU_M2_13_ES1 0x01 + +#define MPU_M_13_ES2 0x1F4 +#define MPU_N_13_ES2 0x0C +#define MPU_FSEL_13_ES2 0x03 +#define MPU_M2_13_ES2 0x01 + +#define MPU_M_13 0x10A +#define MPU_N_13 0x0C +#define MPU_FSEL_13 0x03 +#define MPU_M2_13 0x01 + +#define MPU_M_19P2_ES1 0x179 +#define MPU_N_19P2_ES1 0x12 +#define MPU_FSEL_19P2_ES1 0x04 +#define MPU_M2_19P2_ES1 0x01 + +#define MPU_M_19P2_ES2 0x271 +#define MPU_N_19P2_ES2 0x17 +#define MPU_FSEL_19P2_ES2 0x03 +#define MPU_M2_19P2_ES2 0x01 + +#define MPU_M_19P2 0x14C +#define MPU_N_19P2 0x17 +#define MPU_FSEL_19P2 0x03 +#define MPU_M2_19P2 0x01 + +#define MPU_M_26_ES1 0x17D +#define MPU_N_26_ES1 0x19 +#define MPU_FSEL_26_ES1 0x03 +#define MPU_M2_26_ES1 0x01 + +#define MPU_M_26_ES2 0x0FA +#define MPU_N_26_ES2 0x0C +#define MPU_FSEL_26_ES2 0x07 +#define MPU_M2_26_ES2 0x01 + +#define MPU_M_26 0x085 +#define MPU_N_26 0x0C +#define MPU_FSEL_26 0x07 +#define MPU_M2_26 0x01 + +#define MPU_M_38P4_ES1 0x1FA +#define MPU_N_38P4_ES1 0x32 +#define MPU_FSEL_38P4_ES1 0x03 +#define MPU_M2_38P4_ES1 0x01 + +#define MPU_M_38P4_ES2 0x271 +#define MPU_N_38P4_ES2 0x2F +#define MPU_FSEL_38P4_ES2 0x03 +#define MPU_M2_38P4_ES2 0x01 + +#define MPU_M_38P4 0x14C +#define MPU_N_38P4 0x2F +#define MPU_FSEL_38P4 0x03 +#define MPU_M2_38P4 0x01 + +/* IVA DPLL */ + +#define IVA_M_12_ES1 0x07D +#define IVA_N_12_ES1 0x05 +#define IVA_FSEL_12_ES1 0x07 +#define IVA_M2_12_ES1 0x01 + +#define IVA_M_12_ES2 0x0B4 +#define IVA_N_12_ES2 0x05 +#define IVA_FSEL_12_ES2 0x07 +#define IVA_M2_12_ES2 0x01 + +#define IVA_M_12 0x085 +#define IVA_N_12 0x05 +#define IVA_FSEL_12 0x07 +#define IVA_M2_12 0x01 + +#define IVA_M_13_ES1 0x0FA +#define IVA_N_13_ES1 0x0C +#define IVA_FSEL_13_ES1 0x03 +#define IVA_M2_13_ES1 0x01 + +#define IVA_M_13_ES2 0x168 +#define IVA_N_13_ES2 0x0C +#define IVA_FSEL_13_ES2 0x03 +#define IVA_M2_13_ES2 0x01 + +#define IVA_M_13 0x10A +#define IVA_N_13 0x0C +#define IVA_FSEL_13 0x03 +#define IVA_M2_13 0x01 + +#define IVA_M_19P2_ES1 0x082 +#define IVA_N_19P2_ES1 0x09 +#define IVA_FSEL_19P2_ES1 0x07 +#define IVA_M2_19P2_ES1 0x01 + +#define IVA_M_19P2_ES2 0x0E1 +#define IVA_N_19P2_ES2 0x0B +#define IVA_FSEL_19P2_ES2 0x06 +#define IVA_M2_19P2_ES2 0x01 + +#define IVA_M_19P2 0x14C +#define IVA_N_19P2 0x17 +#define IVA_FSEL_19P2 0x03 +#define IVA_M2_19P2 0x01 + +#define IVA_M_26_ES1 0x07D +#define IVA_N_26_ES1 0x0C +#define IVA_FSEL_26_ES1 0x07 +#define IVA_M2_26_ES1 0x01 + +#define IVA_M_26_ES2 0x0B4 +#define IVA_N_26_ES2 0x0C +#define IVA_FSEL_26_ES2 0x07 +#define IVA_M2_26_ES2 0x01 + +#define IVA_M_26 0x085 +#define IVA_N_26 0x0C +#define IVA_FSEL_26 0x07 +#define IVA_M2_26 0x01 + +#define IVA_M_38P4_ES1 0x13F +#define IVA_N_38P4_ES1 0x30 +#define IVA_FSEL_38P4_ES1 0x03 +#define IVA_M2_38P4_ES1 0x01 + +#define IVA_M_38P4_ES2 0x0E1 +#define IVA_N_38P4_ES2 0x17 +#define IVA_FSEL_38P4_ES2 0x06 +#define IVA_M2_38P4_ES2 0x01 + +#define IVA_M_38P4 0x14C +#define IVA_N_38P4 0x2F +#define IVA_FSEL_38P4 0x03 +#define IVA_M2_38P4 0x01 + +/* CORE DPLL */ + +#define CORE_M_12 0xA6 +#define CORE_N_12 0x05 +#define CORE_FSEL_12 0x07 +#define CORE_M2_12 0x01 /* M3 of 2 */ + +#define CORE_M_12_ES1 0x19F +#define CORE_N_12_ES1 0x0E +#define CORE_FSL_12_ES1 0x03 +#define CORE_M2_12_ES1 0x1 /* M3 of 2 */ + +#define CORE_M_13 0x14C +#define CORE_N_13 0x0C +#define CORE_FSEL_13 0x03 +#define CORE_M2_13 0x01 /* M3 of 2 */ + +#define CORE_M_13_ES1 0x1B2 +#define CORE_N_13_ES1 0x10 +#define CORE_FSL_13_ES1 0x03 +#define CORE_M2_13_ES1 0x01 /* M3 of 2 */ + +#define CORE_M_19P2 0x19F +#define CORE_N_19P2 0x17 +#define CORE_FSEL_19P2 0x03 +#define CORE_M2_19P2 0x01 /* M3 of 2 */ + +#define CORE_M_19P2_ES1 0x19F +#define CORE_N_19P2_ES1 0x17 +#define CORE_FSL_19P2_ES1 0x03 +#define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */ + +#define CORE_M_26 0xA6 +#define CORE_N_26 0x0C +#define CORE_FSEL_26 0x07 +#define CORE_M2_26 0x01 /* M3 of 2 */ + +#define CORE_M_26_ES1 0x1B2 +#define CORE_N_26_ES1 0x21 +#define CORE_FSL_26_ES1 0x03 +#define CORE_M2_26_ES1 0x01 /* M3 of 2 */ + +#define CORE_M_38P4 0x19F +#define CORE_N_38P4 0x2F +#define CORE_FSEL_38P4 0x03 +#define CORE_M2_38P4 0x01 /* M3 of 2 */ + +#define CORE_M_38P4_ES1 0x19F +#define CORE_N_38P4_ES1 0x2F +#define CORE_FSL_38P4_ES1 0x03 +#define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */ + +/* PER DPLL */ + +#define PER_M_12 0xD8 +#define PER_N_12 0x05 +#define PER_FSEL_12 0x07 +#define PER_M2_12 0x09 + +#define PER_M_13 0x1B0 +#define PER_N_13 0x0C +#define PER_FSEL_13 0x03 +#define PER_M2_13 0x09 + +#define PER_M_19P2 0xE1 +#define PER_N_19P2 0x09 +#define PER_FSEL_19P2 0x07 +#define PER_M2_19P2 0x09 + +#define PER_M_26 0xD8 +#define PER_N_26 0x0C +#define PER_FSEL_26 0x07 +#define PER_M2_26 0x09 + +#define PER_M_38P4 0xE1 +#define PER_N_38P4 0x13 +#define PER_FSEL_38P4 0x07 +#define PER_M2_38P4 0x09 + +#endif /* endif _CLOCKS_OMAP3_H_ */ diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h new file mode 100644 index 0000000..69c0b36 --- /dev/null +++ b/include/asm-arm/arch-omap3/cpu.h @@ -0,0 +1,402 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _CPU_H +#define _CPU_H + +/* Register offsets of common modules */ +/* Control */ +#ifndef __ASSEMBLY__ +typedef struct ctrl { + unsigned char res1[0xC0]; + unsigned short gpmc_nadv_ale; /* 0xC0 */ + unsigned short gpmc_noe; /* 0xC2 */ + unsigned short gpmc_nwe; /* 0xC4 */ + unsigned char res2[0x22A]; + unsigned int status; /* 0x2F0 */ +} ctrl_t; +#else /* __ASSEMBLY__ */ +#define CONTROL_STATUS 0x2F0 +#endif /* __ASSEMBLY__ */ + +/* device type */ +#define DEVICE_MASK (0x7 << 8) +#define SYSBOOT_MASK 0x1F +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/* GPMC CS3/cs4/cs6 not avaliable */ +#define GPMC_BASE (OMAP34XX_GPMC_BASE) +#define GPMC_CONFIG_CS0 0x60 +#define GPMC_CONFIG_CS6 0x150 +#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) +#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6) +#define GPMC_CONFIG_WP 0x10 + +#define GPMC_CONFIG_WIDTH 0x30 + +#ifndef __ASSEMBLY__ +typedef struct gpmc { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned char res2[0x4]; + unsigned int irqstatus; /* 0x18 */ + unsigned int irqenable; /* 0x1C */ + unsigned char res3[0x20]; + unsigned int timeout_control; /* 0x40 */ + unsigned char res4[0xC]; + unsigned int config; /* 0x50 */ + unsigned int status; /* 0x54 */ + unsigned char res5[0x19C]; + unsigned int ecc_config; /* 0x1F4 */ + unsigned int ecc_control; /* 0x1F8 */ + unsigned int ecc_size_config; /* 0x1FC */ + unsigned int ecc1_result; /* 0x200 */ + unsigned int ecc2_result; /* 0x204 */ + unsigned int ecc3_result; /* 0x208 */ + unsigned int ecc4_result; /* 0x20C */ + unsigned int ecc5_result; /* 0x210 */ + unsigned int ecc6_result; /* 0x214 */ + unsigned int ecc7_result; /* 0x218 */ + unsigned int ecc8_result; /* 0x21C */ + unsigned int ecc9_result; /* 0x220 */ +} gpmc_t; + +typedef struct gpmc_csx { + unsigned int config1; /* 0x00 */ + unsigned int config2; /* 0x04 */ + unsigned int config3; /* 0x08 */ + unsigned int config4; /* 0x0C */ + unsigned int config5; /* 0x10 */ + unsigned int config6; /* 0x14 */ + unsigned int config7; /* 0x18 */ + unsigned int nand_cmd; /* 0x1C */ + unsigned int nand_adr; /* 0x20 */ + unsigned int nand_dat; /* 0x24 */ +} gpmc_csx_t; +#else /* __ASSEMBLY__ */ +#define GPMC_CONFIG1 0x00 +#define GPMC_CONFIG2 0x04 +#define GPMC_CONFIG3 0x08 +#define GPMC_CONFIG4 0x0C +#define GPMC_CONFIG5 0x10 +#define GPMC_CONFIG6 0x14 +#define GPMC_CONFIG7 0x18 +#endif /* __ASSEMBLY__ */ + +/* GPMC Mapping */ +#define FLASH_BASE 0x10000000 /* NOR flash, */ + /* aligned to 256 Meg */ +#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */ + /* aligned to 64 Meg */ +#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */ + /* aligned to 256 Meg */ +#define DEBUG_BASE 0x08000000 /* debug board */ +#define NAND_BASE 0x30000000 /* NAND addr */ + /* (actual size small port) */ +#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ +#define ONENAND_MAP 0x20000000 /* OneNand addr */ + /* (actual size small port) */ +/* SMS */ +#ifndef __ASSEMBLY__ +typedef struct sms { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned char res2[0x34]; + unsigned int rg_att0; /* 0x48 */ + unsigned char res3[0x84]; + unsigned int class_arb0; /* 0xD0 */ +} sms_t; +#endif /* __ASSEMBLY__ */ + +#define BURSTCOMPLETE_GROUP7 (0x1 << 31) + +/* SDRC */ +#ifndef __ASSEMBLY__ +typedef struct sdrc_cs { + unsigned int mcfg; /* 0x80 || 0xB0 */ + unsigned int mr; /* 0x84 || 0xB4 */ + unsigned char res1[0x4]; + unsigned int emr2; /* 0x8C || 0xBC */ + unsigned char res2[0x14]; + unsigned int rfr_ctrl; /* 0x84 || 0xD4 */ + unsigned int manual; /* 0xA8 || 0xD8 */ + unsigned char res3[0x4]; +} sdrc_cs_t; + +typedef struct sdrc_actim { + unsigned int ctrla; /* 0x9C || 0xC4 */ + unsigned int ctrlb; /* 0xA0 || 0xC8 */ +} sdrc_actim_t; + +typedef struct sdrc { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned int status; /* 0x14 */ + unsigned char res2[0x28]; + unsigned int cs_cfg; /* 0x40 */ + unsigned int sharing; /* 0x44 */ + unsigned char res3[0x18]; + unsigned int dlla_ctrl; /* 0x60 */ + unsigned int dlla_status; /* 0x64 */ + unsigned int dllb_ctrl; /* 0x68 */ + unsigned int dllb_status; /* 0x6C */ + unsigned int power; /* 0x70 */ + unsigned char res4[0xC]; + sdrc_cs_t cs[2]; /* 0x80 || 0xB0 */ +} sdrc_t; +#endif /* __ASSEMBLY__ */ + +#define DLLPHASE_90 (0x1 << 1) +#define LOADDLL (0x1 << 2) +#define ENADLL (0x1 << 3) +#define DLL_DELAY_MASK 0xFF00 +#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) + +#define PAGEPOLICY_HIGH (0x1 << 0) +#define SRFRONRESET (0x1 << 7) +#define WAKEUPPROC (0x1 << 26) + +#define DDR_SDRAM (0x1 << 0) +#define DEEPPD (0x1 << 3) +#define B32NOT16 (0x1 << 4) +#define BANKALLOCATION (0x2 << 6) +#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */ +#define ADDRMUXLEGACY (0x1 << 19) +#define CASWIDTH_10BITS (0x5 << 20) +#define RASWIDTH_13BITS (0x2 << 24) +#define BURSTLENGTH4 (0x2 << 0) +#define CASL3 (0x3 << 4) +#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C) +#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4) +#define ARE_ARCV_1 (0x1 << 0) +#define ARCV (0x4e2 << 8) /* Autorefresh count */ +#define OMAP34XX_SDRC_CS0 0x80000000 +#define OMAP34XX_SDRC_CS1 0xA0000000 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET (0x1 << 1) +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + +/* timer regs offsets (32 bit regs) */ + +#ifndef __ASSEMBLY__ +typedef struct gptimer { + unsigned int tidr; /* 0x00 r */ + unsigned char res[0xc]; + unsigned int tiocp_cfg; /* 0x10 rw */ + unsigned int tistat; /* 0x14 r */ + unsigned int tisr; /* 0x18 rw */ + unsigned int tier; /* 0x1c rw */ + unsigned int twer; /* 0x20 rw */ + unsigned int tclr; /* 0x24 rw */ + unsigned int tcrr; /* 0x28 rw */ + unsigned int tldr; /* 0x2c rw */ + unsigned int ttgr; /* 0x30 rw */ + unsigned int twpc; /* 0x34 r*/ + unsigned int tmar; /* 0x38 rw*/ + unsigned int tcar1; /* 0x3c r */ + unsigned int tcicr; /* 0x40 rw */ + unsigned int tcar2; /* 0x44 r */ +} gptimer_t; +#endif /* __ASSEMBLY__ */ + +/* enable sys_clk NO-prescale /1 */ +#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) + +/* Watchdog */ +#ifndef __ASSEMBLY__ +typedef struct watchdog { + unsigned char res1[0x34]; + unsigned int wwps; /* 0x34 r */ + unsigned char res2[0x10]; + unsigned int wspr; /* 0x48 rw */ +} watchdog_t; +#endif /* __ASSEMBLY__ */ + +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define PRCM_BASE 0x48004000 + +#ifndef __ASSEMBLY__ +typedef struct prcm { + unsigned int fclken_iva2; /* 0x00 */ + unsigned int clken_pll_iva2; /* 0x04 */ + unsigned char res1[0x1c]; + unsigned int idlest_pll_iva2; /* 0x24 */ + unsigned char res2[0x18]; + unsigned int clksel1_pll_iva2 ; /* 0x40 */ + unsigned int clksel2_pll_iva2; /* 0x44 */ + unsigned char res3[0x8bc]; + unsigned int clken_pll_mpu; /* 0x904 */ + unsigned char res4[0x1c]; + unsigned int idlest_pll_mpu; /* 0x924 */ + unsigned char res5[0x18]; + unsigned int clksel1_pll_mpu; /* 0x940 */ + unsigned int clksel2_pll_mpu; /* 0x944 */ + unsigned char res6[0xb8]; + unsigned int fclken1_core; /* 0xa00 */ + unsigned char res7[0xc]; + unsigned int iclken1_core; /* 0xa10 */ + unsigned int iclken2_core; /* 0xa14 */ + unsigned char res8[0x28]; + unsigned int clksel_core; /* 0xa40 */ + unsigned char res9[0xbc]; + unsigned int fclken_gfx; /* 0xb00 */ + unsigned char res10[0xc]; + unsigned int iclken_gfx; /* 0xb10 */ + unsigned char res11[0x2c]; + unsigned int clksel_gfx; /* 0xb40 */ + unsigned char res12[0xbc]; + unsigned int fclken_wkup; /* 0xc00 */ + unsigned char res13[0xc]; + unsigned int iclken_wkup; /* 0xc10 */ + unsigned char res14[0xc]; + unsigned int idlest_wkup; /* 0xc20 */ + unsigned char res15[0x1c]; + unsigned int clksel_wkup; /* 0xc40 */ + unsigned char res16[0xbc]; + unsigned int clken_pll; /* 0xd00 */ + unsigned char res17[0x1c]; + unsigned int idlest_ckgen; /* 0xd20 */ + unsigned char res18[0x1c]; + unsigned int clksel1_pll; /* 0xd40 */ + unsigned int clksel2_pll; /* 0xd44 */ + unsigned int clksel3_pll; /* 0xd48 */ + unsigned char res19[0xb4]; + unsigned int fclken_dss; /* 0xe00 */ + unsigned char res20[0xc]; + unsigned int iclken_dss; /* 0xe10 */ + unsigned char res21[0x2c]; + unsigned int clksel_dss; /* 0xe40 */ + unsigned char res22[0xbc]; + unsigned int fclken_cam; /* 0xf00 */ + unsigned char res23[0xc]; + unsigned int iclken_cam; /* 0xf10 */ + unsigned char res24[0x2c]; + unsigned int clksel_cam; /* 0xf40 */ + unsigned char res25[0xbc]; + unsigned int fclken_per; /* 0x1000 */ + unsigned char res26[0xc]; + unsigned int iclken_per; /* 0x1010 */ + unsigned char res27[0x2c]; + unsigned int clksel_per; /* 0x1040 */ + unsigned char res28[0xfc]; + unsigned int clksel1_emu; /* 0x1140 */ +} prcm_t; +#else /* __ASSEMBLY__ */ +#define CM_CLKSEL_CORE 0x48004a40 +#define CM_CLKSEL_GFX 0x48004b40 +#define CM_CLKSEL_WKUP 0x48004c40 +#define CM_CLKEN_PLL 0x48004d00 +#define CM_CLKSEL1_PLL 0x48004d40 +#define CM_CLKSEL1_EMU 0x48005140 +#endif /* __ASSEMBLY__ */ + +#define PRM_BASE 0x48306000 + +#ifndef __ASSEMBLY__ +typedef struct prm { + unsigned char res1[0xd40]; + unsigned int clksel; /* 0xd40 */ + unsigned char res2[0x50c]; + unsigned int rstctrl; /* 0x1250 */ + unsigned char res3[0x1c]; + unsigned int clksrc_ctrl; /* 0x1270 */ +} prm_t; +#else /* __ASSEMBLY__ */ +#define PRM_RSTCTRL 0x48307250 +#endif /* __ASSEMBLY__ */ + +#define SYSCLKDIV_1 (0x1 << 6) +#define SYSCLKDIV_2 (0x1 << 7) + +#define CLKSEL_GPT1 (0x1 << 0) + +#define EN_GPT1 (0x1 << 0) +#define EN_32KSYNC (0x1 << 2) + +#define ST_WDT2 (0x1 << 5) + +#define ST_MPU_CLK (0x1 << 0) + +#define ST_CORE_CLK (0x1 << 0) + +#define ST_PERIPH_CLK (0x1 << 1) + +#define ST_IVA2_CLK (0x1 << 0) + +#define RESETDONE (0x1 << 0) + +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* SMX-APE */ +#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) +#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) + +#ifndef __ASSEMBLY__ +typedef struct pm { + unsigned char res1[0x48]; + unsigned int req_info_permission_0; /* 0x48 */ + unsigned char res2[0x4]; + unsigned int read_permission_0; /* 0x50 */ + unsigned char res3[0x4]; + unsigned int wirte_permission_0; /* 0x58 */ + unsigned char res4[0x4]; + unsigned int addr_match_1; /* 0x58 */ + unsigned char res5[0x4]; + unsigned int req_info_permission_1; /* 0x68 */ + unsigned char res6[0x14]; + unsigned int addr_match_2; /* 0x80 */ +} pm_t; +#endif /*__ASSEMBLY__ */ + +/* Permission values for registers -Full fledged permissions to all */ +#define UNLOCK_1 0xFFFFFFFF +#define UNLOCK_2 0x00000000 +#define UNLOCK_3 0x0000FFFF + +#define NOT_EARLY 0 + +/* I2C base */ +#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) +#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) +#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) + +#endif /* _CPU_H */ diff --git a/include/asm-arm/arch-omap3/mux.h b/include/asm-arm/arch-omap3/mux.h new file mode 100644 index 0000000..0c01c73 --- /dev/null +++ b/include/asm-arm/arch-omap3/mux.h @@ -0,0 +1,412 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <x0khasim@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUX_H_ +#define _MUX_H_ + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + */ + +#define IEN (1 << 8) + +#define IDIS (0 << 8) +#define PTU (1 << 4) +#define PTD (0 << 4) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +/* + * To get the actual address the offset has to added + * with OMAP34XX_CTRL_BASE to get the actual address + */ + +/*SDRC*/ +#define CONTROL_PADCONF_SDRC_D0 0x0030 +#define CONTROL_PADCONF_SDRC_D1 0x0032 +#define CONTROL_PADCONF_SDRC_D2 0x0034 +#define CONTROL_PADCONF_SDRC_D3 0x0036 +#define CONTROL_PADCONF_SDRC_D4 0x0038 +#define CONTROL_PADCONF_SDRC_D5 0x003A +#define CONTROL_PADCONF_SDRC_D6 0x003C +#define CONTROL_PADCONF_SDRC_D7 0x003E +#define CONTROL_PADCONF_SDRC_D8 0x0040 +#define CONTROL_PADCONF_SDRC_D9 0x0042 +#define CONTROL_PADCONF_SDRC_D10 0x0044 +#define CONTROL_PADCONF_SDRC_D11 0x0046 +#define CONTROL_PADCONF_SDRC_D12 0x0048 +#define CONTROL_PADCONF_SDRC_D13 0x004A +#define CONTROL_PADCONF_SDRC_D14 0x004C +#define CONTROL_PADCONF_SDRC_D15 0x004E +#define CONTROL_PADCONF_SDRC_D16 0x0050 +#define CONTROL_PADCONF_SDRC_D17 0x0052 +#define CONTROL_PADCONF_SDRC_D18 0x0054 +#define CONTROL_PADCONF_SDRC_D19 0x0056 +#define CONTROL_PADCONF_SDRC_D20 0x0058 +#define CONTROL_PADCONF_SDRC_D21 0x005A +#define CONTROL_PADCONF_SDRC_D22 0x005C +#define CONTROL_PADCONF_SDRC_D23 0x005E +#define CONTROL_PADCONF_SDRC_D24 0x0060 +#define CONTROL_PADCONF_SDRC_D25 0x0062 +#define CONTROL_PADCONF_SDRC_D26 0x0064 +#define CONTROL_PADCONF_SDRC_D27 0x0066 +#define CONTROL_PADCONF_SDRC_D28 0x0068 +#define CONTROL_PADCONF_SDRC_D29 0x006A +#define CONTROL_PADCONF_SDRC_D30 0x006C +#define CONTROL_PADCONF_SDRC_D31 0x006E +#define CONTROL_PADCONF_SDRC_CLK 0x0070 +#define CONTROL_PADCONF_SDRC_DQS0 0x0072 +#define CONTROL_PADCONF_SDRC_DQS1 0x0074 +#define CONTROL_PADCONF_SDRC_DQS2 0x0076 +#define CONTROL_PADCONF_SDRC_DQS3 0x0078 +/*GPMC*/ +#define CONTROL_PADCONF_GPMC_A1 0x007A +#define CONTROL_PADCONF_GPMC_A2 0x007C +#define CONTROL_PADCONF_GPMC_A3 0x007E +#define CONTROL_PADCONF_GPMC_A4 0x0080 +#define CONTROL_PADCONF_GPMC_A5 0x0082 +#define CONTROL_PADCONF_GPMC_A6 0x0084 +#define CONTROL_PADCONF_GPMC_A7 0x0086 +#define CONTROL_PADCONF_GPMC_A8 0x0088 +#define CONTROL_PADCONF_GPMC_A9 0x008A +#define CONTROL_PADCONF_GPMC_A10 0x008C +#define CONTROL_PADCONF_GPMC_D0 0x008E +#define CONTROL_PADCONF_GPMC_D1 0x0090 +#define CONTROL_PADCONF_GPMC_D2 0x0092 +#define CONTROL_PADCONF_GPMC_D3 0x0094 +#define CONTROL_PADCONF_GPMC_D4 0x0096 +#define CONTROL_PADCONF_GPMC_D5 0x0098 +#define CONTROL_PADCONF_GPMC_D6 0x009A +#define CONTROL_PADCONF_GPMC_D7 0x009C +#define CONTROL_PADCONF_GPMC_D8 0x009E +#define CONTROL_PADCONF_GPMC_D9 0x00A0 +#define CONTROL_PADCONF_GPMC_D10 0x00A2 +#define CONTROL_PADCONF_GPMC_D11 0x00A4 +#define CONTROL_PADCONF_GPMC_D12 0x00A6 +#define CONTROL_PADCONF_GPMC_D13 0x00A8 +#define CONTROL_PADCONF_GPMC_D14 0x00AA +#define CONTROL_PADCONF_GPMC_D15 0x00AC +#define CONTROL_PADCONF_GPMC_NCS0 0x00AE +#define CONTROL_PADCONF_GPMC_NCS1 0x00B0 +#define CONTROL_PADCONF_GPMC_NCS2 0x00B2 +#define CONTROL_PADCONF_GPMC_NCS3 0x00B4 +#define CONTROL_PADCONF_GPMC_NCS4 0x00B6 +#define CONTROL_PADCONF_GPMC_NCS5 0x00B8 +#define CONTROL_PADCONF_GPMC_NCS6 0x00BA +#define CONTROL_PADCONF_GPMC_NCS7 0x00BC +#define CONTROL_PADCONF_GPMC_CLK 0x00BE +#define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0 +#define CONTROL_PADCONF_GPMC_NOE 0x00C2 +#define CONTROL_PADCONF_GPMC_NWE 0x00C4 +#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6 +#define CONTROL_PADCONF_GPMC_NBE1 0x00C8 +#define CONTROL_PADCONF_GPMC_NWP 0x00CA +#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC +#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE +#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 +#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 +/*DSS*/ +#define CONTROL_PADCONF_DSS_PCLK 0x00D4 +#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 +#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 +#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA +#define CONTROL_PADCONF_DSS_DATA0 0x00DC +#define CONTROL_PADCONF_DSS_DATA1 0x00DE +#define CONTROL_PADCONF_DSS_DATA2 0x00E0 +#define CONTROL_PADCONF_DSS_DATA3 0x00E2 +#define CONTROL_PADCONF_DSS_DATA4 0x00E4 +#define CONTROL_PADCONF_DSS_DATA5 0x00E6 +#define CONTROL_PADCONF_DSS_DATA6 0x00E8 +#define CONTROL_PADCONF_DSS_DATA7 0x00EA +#define CONTROL_PADCONF_DSS_DATA8 0x00EC +#define CONTROL_PADCONF_DSS_DATA9 0x00EE +#define CONTROL_PADCONF_DSS_DATA10 0x00F0 +#define CONTROL_PADCONF_DSS_DATA11 0x00F2 +#define CONTROL_PADCONF_DSS_DATA12 0x00F4 +#define CONTROL_PADCONF_DSS_DATA13 0x00F6 +#define CONTROL_PADCONF_DSS_DATA14 0x00F8 +#define CONTROL_PADCONF_DSS_DATA15 0x00FA +#define CONTROL_PADCONF_DSS_DATA16 0x00FC +#define CONTROL_PADCONF_DSS_DATA17 0x00FE +#define CONTROL_PADCONF_DSS_DATA18 0x0100 +#define CONTROL_PADCONF_DSS_DATA19 0x0102 +#define CONTROL_PADCONF_DSS_DATA20 0x0104 +#define CONTROL_PADCONF_DSS_DATA21 0x0106 +#define CONTROL_PADCONF_DSS_DATA22 0x0108 +#define CONTROL_PADCONF_DSS_DATA23 0x010A +/*CAMERA*/ +#define CONTROL_PADCONF_CAM_HS 0x010C +#define CONTROL_PADCONF_CAM_VS 0x010E +#define CONTROL_PADCONF_CAM_XCLKA 0x0110 +#define CONTROL_PADCONF_CAM_PCLK 0x0112 +#define CONTROL_PADCONF_CAM_FLD 0x0114 +#define CONTROL_PADCONF_CAM_D0 0x0116 +#define CONTROL_PADCONF_CAM_D1 0x0118 +#define CONTROL_PADCONF_CAM_D2 0x011A +#define CONTROL_PADCONF_CAM_D3 0x011C +#define CONTROL_PADCONF_CAM_D4 0x011E +#define CONTROL_PADCONF_CAM_D5 0x0120 +#define CONTROL_PADCONF_CAM_D6 0x0122 +#define CONTROL_PADCONF_CAM_D7 0x0124 +#define CONTROL_PADCONF_CAM_D8 0x0126 +#define CONTROL_PADCONF_CAM_D9 0x0128 +#define CONTROL_PADCONF_CAM_D10 0x012A +#define CONTROL_PADCONF_CAM_D11 0x012C +#define CONTROL_PADCONF_CAM_XCLKB 0x012E +#define CONTROL_PADCONF_CAM_WEN 0x0130 +#define CONTROL_PADCONF_CAM_STROBE 0x0132 +#define CONTROL_PADCONF_CSI2_DX0 0x0134 +#define CONTROL_PADCONF_CSI2_DY0 0x0136 +#define CONTROL_PADCONF_CSI2_DX1 0x0138 +#define CONTROL_PADCONF_CSI2_DY1 0x013A +/*Audio Interface */ +#define CONTROL_PADCONF_MCBSP2_FSX 0x013C +#define CONTROL_PADCONF_MCBSP2_CLKX 0x013E +#define CONTROL_PADCONF_MCBSP2_DR 0x0140 +#define CONTROL_PADCONF_MCBSP2_DX 0x0142 +#define CONTROL_PADCONF_MMC1_CLK 0x0144 +#define CONTROL_PADCONF_MMC1_CMD 0x0146 +#define CONTROL_PADCONF_MMC1_DAT0 0x0148 +#define CONTROL_PADCONF_MMC1_DAT1 0x014A +#define CONTROL_PADCONF_MMC1_DAT2 0x014C +#define CONTROL_PADCONF_MMC1_DAT3 0x014E +#define CONTROL_PADCONF_MMC1_DAT4 0x0150 +#define CONTROL_PADCONF_MMC1_DAT5 0x0152 +#define CONTROL_PADCONF_MMC1_DAT6 0x0154 +#define CONTROL_PADCONF_MMC1_DAT7 0x0156 +/*Wireless LAN */ +#define CONTROL_PADCONF_MMC2_CLK 0x0158 +#define CONTROL_PADCONF_MMC2_CMD 0x015A +#define CONTROL_PADCONF_MMC2_DAT0 0x015C +#define CONTROL_PADCONF_MMC2_DAT1 0x015E +#define CONTROL_PADCONF_MMC2_DAT2 0x0160 +#define CONTROL_PADCONF_MMC2_DAT3 0x0162 +#define CONTROL_PADCONF_MMC2_DAT4 0x0164 +#define CONTROL_PADCONF_MMC2_DAT5 0x0166 +#define CONTROL_PADCONF_MMC2_DAT6 0x0168 +#define CONTROL_PADCONF_MMC2_DAT7 0x016A +/*Bluetooth*/ +#define CONTROL_PADCONF_MCBSP3_DX 0x016C +#define CONTROL_PADCONF_MCBSP3_DR 0x016E +#define CONTROL_PADCONF_MCBSP3_CLKX 0x0170 +#define CONTROL_PADCONF_MCBSP3_FSX 0x0172 +#define CONTROL_PADCONF_UART2_CTS 0x0174 +#define CONTROL_PADCONF_UART2_RTS 0x0176 +#define CONTROL_PADCONF_UART2_TX 0x0178 +#define CONTROL_PADCONF_UART2_RX 0x017A +/*Modem Interface */ +#define CONTROL_PADCONF_UART1_TX 0x017C +#define CONTROL_PADCONF_UART1_RTS 0x017E +#define CONTROL_PADCONF_UART1_CTS 0x0180 +#define CONTROL_PADCONF_UART1_RX 0x0182 +#define CONTROL_PADCONF_MCBSP4_CLKX 0x0184 +#define CONTROL_PADCONF_MCBSP4_DR 0x0186 +#define CONTROL_PADCONF_MCBSP4_DX 0x0188 +#define CONTROL_PADCONF_MCBSP4_FSX 0x018A +#define CONTROL_PADCONF_MCBSP1_CLKR 0x018C +#define CONTROL_PADCONF_MCBSP1_FSR 0x018E +#define CONTROL_PADCONF_MCBSP1_DX 0x0190 +#define CONTROL_PADCONF_MCBSP1_DR 0x0192 +#define CONTROL_PADCONF_MCBSP_CLKS 0x0194 +#define CONTROL_PADCONF_MCBSP1_FSX 0x0196 +#define CONTROL_PADCONF_MCBSP1_CLKX 0x0198 +/*Serial Interface*/ +#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A +#define CONTROL_PADCONF_UART3_RTS_SD 0x019C +#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E +#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 +#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 +#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 +#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 +#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 +#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA +#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC +#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE +#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 +#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 +#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 +#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 +#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 +#define CONTROL_PADCONF_I2C1_SCL 0x01BA +#define CONTROL_PADCONF_I2C1_SDA 0x01BC +#define CONTROL_PADCONF_I2C2_SCL 0x01BE +#define CONTROL_PADCONF_I2C2_SDA 0x01C0 +#define CONTROL_PADCONF_I2C3_SCL 0x01C2 +#define CONTROL_PADCONF_I2C3_SDA 0x01C4 +#define CONTROL_PADCONF_I2C4_SCL 0x0A00 +#define CONTROL_PADCONF_I2C4_SDA 0x0A02 +#define CONTROL_PADCONF_HDQ_SIO 0x01C6 +#define CONTROL_PADCONF_MCSPI1_CLK 0x01C8 +#define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA +#define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC +#define CONTROL_PADCONF_MCSPI1_CS0 0x01CE +#define CONTROL_PADCONF_MCSPI1_CS1 0x01D0 +#define CONTROL_PADCONF_MCSPI1_CS2 0x01D2 +#define CONTROL_PADCONF_MCSPI1_CS3 0x01D4 +#define CONTROL_PADCONF_MCSPI2_CLK 0x01D6 +#define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8 +#define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA +#define CONTROL_PADCONF_MCSPI2_CS0 0x01DC +#define CONTROL_PADCONF_MCSPI2_CS1 0x01DE +/*Control and debug */ +#define CONTROL_PADCONF_SYS_32K 0x0A04 +#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 +#define CONTROL_PADCONF_SYS_NIRQ 0x01E0 +#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A +#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C +#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E +#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 +#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 +#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 +#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 +#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 +#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A +#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 +#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C +#define CONTROL_PADCONF_JTAG_TCK 0x0A1E +#define CONTROL_PADCONF_JTAG_TMS 0x0A20 +#define CONTROL_PADCONF_JTAG_TDI 0x0A22 +#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 +#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 +#define CONTROL_PADCONF_ETK_CLK 0x0A28 +#define CONTROL_PADCONF_ETK_CTL 0x0A2A +#define CONTROL_PADCONF_ETK_D0 0x0A2C +#define CONTROL_PADCONF_ETK_D1 0x0A2E +#define CONTROL_PADCONF_ETK_D2 0x0A30 +#define CONTROL_PADCONF_ETK_D3 0x0A32 +#define CONTROL_PADCONF_ETK_D4 0x0A34 +#define CONTROL_PADCONF_ETK_D5 0x0A36 +#define CONTROL_PADCONF_ETK_D6 0x0A38 +#define CONTROL_PADCONF_ETK_D7 0x0A3A +#define CONTROL_PADCONF_ETK_D8 0x0A3C +#define CONTROL_PADCONF_ETK_D9 0x0A3E +#define CONTROL_PADCONF_ETK_D10 0x0A40 +#define CONTROL_PADCONF_ETK_D11 0x0A42 +#define CONTROL_PADCONF_ETK_D12 0x0A44 +#define CONTROL_PADCONF_ETK_D13 0x0A46 +#define CONTROL_PADCONF_ETK_D14 0x0A48 +#define CONTROL_PADCONF_ETK_D15 0x0A4A +#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 +#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA +#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC +#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE +#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 +#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 +#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 +#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 +#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 +#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA +#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC +#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE +#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 +#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 +#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 +#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 +#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 +#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA +/*Die to Die */ +#define CONTROL_PADCONF_D2D_MCAD0 0x01E4 +#define CONTROL_PADCONF_D2D_MCAD1 0x01E6 +#define CONTROL_PADCONF_D2D_MCAD2 0x01E8 +#define CONTROL_PADCONF_D2D_MCAD3 0x01EA +#define CONTROL_PADCONF_D2D_MCAD4 0x01EC +#define CONTROL_PADCONF_D2D_MCAD5 0x01EE +#define CONTROL_PADCONF_D2D_MCAD6 0x01F0 +#define CONTROL_PADCONF_D2D_MCAD7 0x01F2 +#define CONTROL_PADCONF_D2D_MCAD8 0x01F4 +#define CONTROL_PADCONF_D2D_MCAD9 0x01F6 +#define CONTROL_PADCONF_D2D_MCAD10 0x01F8 +#define CONTROL_PADCONF_D2D_MCAD11 0x01FA +#define CONTROL_PADCONF_D2D_MCAD12 0x01FC +#define CONTROL_PADCONF_D2D_MCAD13 0x01FE +#define CONTROL_PADCONF_D2D_MCAD14 0x0200 +#define CONTROL_PADCONF_D2D_MCAD15 0x0202 +#define CONTROL_PADCONF_D2D_MCAD16 0x0204 +#define CONTROL_PADCONF_D2D_MCAD17 0x0206 +#define CONTROL_PADCONF_D2D_MCAD18 0x0208 +#define CONTROL_PADCONF_D2D_MCAD19 0x020A +#define CONTROL_PADCONF_D2D_MCAD20 0x020C +#define CONTROL_PADCONF_D2D_MCAD21 0x020E +#define CONTROL_PADCONF_D2D_MCAD22 0x0210 +#define CONTROL_PADCONF_D2D_MCAD23 0x0212 +#define CONTROL_PADCONF_D2D_MCAD24 0x0214 +#define CONTROL_PADCONF_D2D_MCAD25 0x0216 +#define CONTROL_PADCONF_D2D_MCAD26 0x0218 +#define CONTROL_PADCONF_D2D_MCAD27 0x021A +#define CONTROL_PADCONF_D2D_MCAD28 0x021C +#define CONTROL_PADCONF_D2D_MCAD29 0x021E +#define CONTROL_PADCONF_D2D_MCAD30 0x0220 +#define CONTROL_PADCONF_D2D_MCAD31 0x0222 +#define CONTROL_PADCONF_D2D_MCAD32 0x0224 +#define CONTROL_PADCONF_D2D_MCAD33 0x0226 +#define CONTROL_PADCONF_D2D_MCAD34 0x0228 +#define CONTROL_PADCONF_D2D_MCAD35 0x022A +#define CONTROL_PADCONF_D2D_MCAD36 0x022C +#define CONTROL_PADCONF_D2D_CLK26MI 0x022E +#define CONTROL_PADCONF_D2D_NRESPWRON 0x0230 +#define CONTROL_PADCONF_D2D_NRESWARM 0x0232 +#define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234 +#define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236 +#define CONTROL_PADCONF_D2D_SPINT 0x0238 +#define CONTROL_PADCONF_D2D_FRINT 0x023A +#define CONTROL_PADCONF_D2D_DMAREQ0 0x023C +#define CONTROL_PADCONF_D2D_DMAREQ1 0x023E +#define CONTROL_PADCONF_D2D_DMAREQ2 0x0240 +#define CONTROL_PADCONF_D2D_DMAREQ3 0x0242 +#define CONTROL_PADCONF_D2D_N3GTRST 0x0244 +#define CONTROL_PADCONF_D2D_N3GTDI 0x0246 +#define CONTROL_PADCONF_D2D_N3GTDO 0x0248 +#define CONTROL_PADCONF_D2D_N3GTMS 0x024A +#define CONTROL_PADCONF_D2D_N3GTCK 0x024C +#define CONTROL_PADCONF_D2D_N3GRTCK 0x024E +#define CONTROL_PADCONF_D2D_MSTDBY 0x0250 +#define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C +#define CONTROL_PADCONF_D2D_IDLEREQ 0x0252 +#define CONTROL_PADCONF_D2D_IDLEACK 0x0254 +#define CONTROL_PADCONF_D2D_MWRITE 0x0256 +#define CONTROL_PADCONF_D2D_SWRITE 0x0258 +#define CONTROL_PADCONF_D2D_MREAD 0x025A +#define CONTROL_PADCONF_D2D_SREAD 0x025C +#define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E +#define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260 +#define CONTROL_PADCONF_SDRC_CKE0 0x0262 +#define CONTROL_PADCONF_SDRC_CKE1 0x0264 + +#define MUX_VAL(OFFSET,VALUE)\ + writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) + +#endif |