diff options
37 files changed, 1804 insertions, 708 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 2cf29dd..e235884 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -501,6 +501,10 @@ Detlev Zundel <dzu@denx.de> inka4x0 MPC5200 +Tirumala Marri <tmarri@apm.com> + + bluestone APM821XX + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index 6009b0c..67f1fff 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -250,6 +250,20 @@ static char *bootstrap_str[] = { }; static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; #endif +#if defined(CONFIG_APM821XX) +#define SDR0_PINSTP_SHIFT 29 +static char *bootstrap_str[] = { + "RESERVED", + "RESERVED", + "RESERVED", + "NAND (8 bits)", + "NOR (8 bits)", + "NOR (8 bits) w/PLL Bypassed", + "I2C (Addr 0x54)", + "I2C (Addr 0x52)", +}; +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; +#endif #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) @@ -590,6 +604,11 @@ int checkcpu (void) strcpy(addstr, "No Security support"); break; + case PVR_APM821XX_RA: + puts("APM821XX Rev. A"); + strcpy(addstr, "Security support"); + break; + case PVR_VIRTEX5: puts("440x5 VIRTEX5"); break; diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index d54b30e..2a727b1 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -237,7 +237,8 @@ cpu_init_f (void) reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); -#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) +#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \ + !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE) /* * GPIO0 setup (select GPIO or alternate function) */ @@ -393,7 +394,7 @@ cpu_init_f (void) #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index abd4e91..09d6671 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -189,7 +189,7 @@ ulong get_PCI_freq (void) #elif defined(CONFIG_440) #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) static u8 pll_fwdv_multi_bits[] = { /* values for: 1 - 16 */ 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c, @@ -250,6 +250,78 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv) return 0; } +#if defined(CONFIG_APM821XX) + +void get_sys_info(sys_info_t *sysInfo) +{ + unsigned long plld; + unsigned long temp; + unsigned long mul; + unsigned long cpudv; + unsigned long plb2dv; + unsigned long ddr2dv; + + /* Calculate Forward divisor A and Feeback divisor */ + mfcpr(CPR0_PLLD, plld); + + temp = CPR0_PLLD_FWDVA(plld); + sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); + + temp = CPR0_PLLD_FDV(plld); + sysInfo->pllFbkDiv = get_cpr0_fbdv(temp); + + /* Calculate OPB clock divisor */ + mfcpr(CPR0_OPBD, temp); + temp = CPR0_OPBD_OPBDV(temp); + sysInfo->pllOpbDiv = temp ? temp : 4; + + /* Calculate Peripheral clock divisor */ + mfcpr(CPR0_PERD, temp); + temp = CPR0_PERD_PERDV(temp); + sysInfo->pllExtBusDiv = temp ? temp : 4; + + /* Calculate CPU clock divisor */ + mfcpr(CPR0_CPUD, temp); + temp = CPR0_CPUD_CPUDV(temp); + cpudv = temp ? temp : 8; + + /* Calculate PLB2 clock divisor */ + mfcpr(CPR0_PLB2D, temp); + temp = CPR0_PLB2D_PLB2DV(temp); + plb2dv = temp ? temp : 4; + + /* Calculate DDR2 clock divisor */ + mfcpr(CPR0_DDR2D, temp); + temp = CPR0_DDR2D_DDR2DV(temp); + ddr2dv = temp ? temp : 4; + + /* Calculate 'M' based on feedback source */ + mfcpr(CPR0_PLLC, temp); + temp = CPR0_PLLC_SEL(temp); + if (temp == 0) { + /* PLL internal feedback */ + mul = sysInfo->pllFbkDiv; + } else { + /* PLL PerClk feedback */ + mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv + * plb2dv * 2 * sysInfo->pllOpbDiv * + sysInfo->pllExtBusDiv; + } + + /* Now calculate the individual clocks */ + sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1); + sysInfo->freqProcessor = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv; + sysInfo->freqPLB = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv / plb2dv / 2; + sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; + sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; + sysInfo->freqDDR = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv / ddr2dv / 2; + sysInfo->freqUART = sysInfo->freqPLB; +} + +#else /* * AMCC_TODO: verify this routine against latest EAS, cause stuff changed * with latest EAS @@ -307,6 +379,7 @@ void get_sys_info (sys_info_t * sysInfo) return; } +#endif #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 7a65d9f..c2d52bf 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -703,7 +703,8 @@ _start: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460SX) mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) lis r1, 0x0000 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ mtdcr L2_CACHE_CFG,r1 @@ -731,7 +732,8 @@ _start: lis r1, 0x8003 ori r1,r1, 0x0980 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \ + defined(CONFIG_460GT) || defined(CONFIG_APM821XX) lis r1,0x0000 /* BAS = X_0000_0000 */ ori r1,r1,0x0984 /* first 64k */ mtdcr ISRAM0_SB0CR,r1 @@ -744,7 +746,8 @@ _start: lis r1, 0x0003 ori r1,r1, 0x0984 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) lis r2,0x7fff ori r2,r2,0xffff mfdcr r1,ISRAM1_DPC @@ -755,7 +758,7 @@ _start: mtdcr ISRAM1_PMEG,r1 lis r1,0x0004 /* BAS = 4_0004_0000 */ - ori r1,r1,0x0984 /* 64k */ + ori r1,r1,ISRAM1_SIZE /* ocm size */ mtdcr ISRAM1_SB0CR,r1 #endif #elif defined(CONFIG_460SX) diff --git a/arch/powerpc/include/asm/apm821xx.h b/arch/powerpc/include/asm/apm821xx.h new file mode 100644 index 0000000..8841bc9 --- /dev/null +++ b/arch/powerpc/include/asm/apm821xx.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri@apm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _APM821XX_H_ +#define _APM821XX_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ + +/* Memory mapped registers */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) + +#define SDR0_SRST0_DMC 0x00200000 +#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ + +/* AHB config. */ +#define AHB_TOP 0xA4 +#define AHB_BOT 0xA5 + +/* clk divisors */ +#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ +#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ +#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ +#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ +#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ +#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/ +#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ +#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ + +/* + + * Clocking Controller + + */ +#define CPR0_CLKUPD 0x0020 +#define CPR0_PLLC 0x0040 +#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) +#define CPR0_PLLD 0x0060 +#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) +#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) +#define CPR0_CPUD 0x0080 +#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) +#define CPR0_PLB2D 0x00a0 +#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) +#define CPR0_OPBD 0x00c0 +#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) +#define CPR0_PERD 0x00e0 +#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) +#define CPR0_DDR2D 0x0100 +#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) +#define CLK_ICFG 0x0140 + +#endif /* _APM821XX_H_ */ diff --git a/arch/powerpc/include/asm/ppc440epx_grx.h b/arch/powerpc/include/asm/ppc440epx_grx.h index 252f35b..6c21472 100644 --- a/arch/powerpc/include/asm/ppc440epx_grx.h +++ b/arch/powerpc/include/asm/ppc440epx_grx.h @@ -36,6 +36,8 @@ #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600) #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00) #define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00) diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h index 9c17e46..75af130 100644 --- a/arch/powerpc/include/asm/ppc4xx-ebc.h +++ b/arch/powerpc/include/asm/ppc4xx-ebc.h @@ -69,7 +69,8 @@ #define EBC_NUM_BANKS 6 #endif -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_APM821XX) #define EBC_NUM_BANKS 3 #endif diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h index d6d17ac..32e1297 100644 --- a/arch/powerpc/include/asm/ppc4xx-isram.h +++ b/arch/powerpc/include/asm/ppc4xx-isram.h @@ -25,7 +25,8 @@ /* * Internal SRAM */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_APM821XX) #define ISRAM0_DCR_BASE 0x380 #else #define ISRAM0_DCR_BASE 0x020 @@ -42,7 +43,8 @@ #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) #define ISRAM1_DCR_BASE 0x0B0 #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ @@ -54,13 +56,19 @@ #define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */ #endif /* CONFIG_460EX || CONFIG_460GT */ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define ISRAM1_SIZE 0x0984 /* OCM size 64k */ +#elif defined(CONFIG_APM821XX) +#define ISRAM1_SIZE 0x0784 /* OCM size 32k */ +#endif + /* * L2 Cache */ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define L2_CACHE_BASE 0x030 #define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index ac150c2..d570d79 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -292,7 +292,7 @@ */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) @@ -365,7 +365,7 @@ /* * Memory controller registers */ -#ifdef CONFIG_405EX +#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ #define SDRAM_BEARL 0x02 /* PLB bus error address low */ @@ -375,9 +375,9 @@ #define SDRAM_PLBOPT 0x08 /* PLB slave options */ #define SDRAM_PUABA 0x09 /* PLB upper address base */ #define SDRAM_MCSTAT 0x1F /* memory controller status */ -#else /* CONFIG_405EX */ +#else /* CONFIG_405EX || CONFIG_APM821XX */ #define SDRAM_MCSTAT 0x14 /* memory controller status */ -#endif /* CONFIG_405EX */ +#endif /* CONFIG_405EX || CONFIG_APM821XX */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ @@ -423,12 +423,12 @@ #define SDRAM_MEMODE 0x89 /* memory extended mode */ #define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ -#ifndef CONFIG_405EX +#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX) #define SDRAM_RID 0xA8 /* revision ID */ #endif #define SDRAM_FCSR 0xB0 /* feedback calibration status */ #define SDRAM_RTSR 0xB1 /* run time status tracking */ -#ifdef CONFIG_405EX +#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) #define SDRAM_RID 0xF8 /* revision ID */ #endif diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h index 782d045..3714a0a 100644 --- a/arch/powerpc/include/asm/ppc4xx-uic.h +++ b/arch/powerpc/include/asm/ppc4xx-uic.h @@ -31,7 +31,7 @@ */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define UIC_MAX 4 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) @@ -252,7 +252,8 @@ #define VECNUM_ETH0 (32 + 28) #endif /* CONFIG_440SPE */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) /* UIC 0 */ #define VECNUM_UIC2NCI 10 #define VECNUM_UIC2CI 11 diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h index 87a16ec..633f793 100644 --- a/arch/powerpc/include/asm/ppc4xx.h +++ b/arch/powerpc/include/asm/ppc4xx.h @@ -79,10 +79,13 @@ #include <asm/ppc460sx.h> #endif +#if defined(CONFIG_APM821XX) +#include <asm/apm821xx.h> +#endif + /* * Configure which SDRAM/DDR/DDR2 controller is equipped */ -// test-only: what to do with these??? #if defined(CONFIG_AP1000) || defined(CONFIG_ML2) #define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ #endif @@ -202,22 +205,6 @@ #define GPT0_DCT0 0x00000110 #define GPT0_DCIS 0x0000011C -#if 0 // test-only -/* - * All PPC4xx share the same NS16550 UART(s). Only base addresses - * may differ. We define here the integration of the common NS16550 - * driver for all PPC4xx SoC's. The board config header must specify - * on which UART the console should be located via CONFIG_CONS_INDEX. - */ -#if 0 /* test-only */ -#define CONFIG_SERIAL_MULTI -#endif -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#endif - #if defined(CONFIG_440) #include <asm/ppc440.h> #else diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 84a1e2e..9cafe85 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -916,6 +916,7 @@ #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ #define PVR_460GX_RA 0x13541802 /* 460GX rev A */ #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ +#define PVR_APM821XX_RA 0x12C41C80 /* APM821XX rev A */ #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 diff --git a/board/amcc/bluestone/Makefile b/board/amcc/bluestone/Makefile new file mode 100644 index 0000000..41751c8 --- /dev/null +++ b/board/amcc/bluestone/Makefile @@ -0,0 +1,52 @@ +# +# Copyright (c) 2010, Applied Micro Circuits Corporation +# Author: Tirumala R Marri <tmarri@apm.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +SOBJS := init.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/bluestone/bluestone.c b/board/amcc/bluestone/bluestone.c new file mode 100644 index 0000000..fe8929c --- /dev/null +++ b/board/amcc/bluestone/bluestone.c @@ -0,0 +1,111 @@ +/* + * Bluestone board support + * + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri@apm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/apm821xx.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <i2c.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <asm/ppc4xx-gpio.h> + +int board_early_init_f(void) +{ + /* + * Setup the interrupt controller polarities, triggers, etc. + */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + mtdcr(UIC3ER, 0x00000000); /* disable all */ + mtdcr(UIC3CR, 0x00000000); /* all non-critical */ + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + + /* + * Configure PFC (Pin Function Control) registers + * UART0: 2 pins + */ + mtsdr(SDR0_PFC1, 0x0000000); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: Bluestone Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +int misc_init_r(void) +{ + u32 sdr0_srst1 = 0; + + /* Setup PLB4-AHB bridge based on the system address map */ + mtdcr(AHB_TOP, 0x8000004B); + mtdcr(AHB_BOT, 0x8000004B); + + /* + * The AHB Bridge core is held in reset after power-on or reset + * so enable it now + */ + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~SDR0_SRST1_AHB; + mtsdr(SDR0_SRST1, sdr0_srst1); + + return 0; +} diff --git a/board/amcc/bluestone/config.mk b/board/amcc/bluestone/config.mk new file mode 100644 index 0000000..e2194e4 --- /dev/null +++ b/board/amcc/bluestone/config.mk @@ -0,0 +1,40 @@ +# +# Copyright (c) 2010, Applied Micro Circuits Corporation +# Author: Tirumala R Marri <tmarri@apm.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Applied Micro APM821XX Evaluation board. +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0xFFFA0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S new file mode 100644 index 0000000..e969fcf --- /dev/null +++ b/board/amcc/bluestone/init.S @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri@apm.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm/mmu.h> +#include <asm/ppc4xx.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* TLB 0 */ + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, + 4, AC_RWX | SA_G) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, + 0, AC_RWX | SA_G) + + /* TLB-entry for OCM */ + tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4, + AC_RWX | SA_I) + + /* TLB-entry for Local Configuration registers => peripherals */ + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, + CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG) + tlbtab_end diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index b26cadb..faa3720 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -34,16 +34,16 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch DECLARE_GLOBAL_DATA_PTR; - struct board_bcsr { - u8 board_id; - u8 cpld_rev; - u8 led_user; - u8 board_status; - u8 reset_ctrl; - u8 flash_ctrl; - u8 eth_ctrl; - u8 usb_ctrl; - u8 irq_ctrl; +struct board_bcsr { + u8 board_id; + u8 cpld_rev; + u8 led_user; + u8 board_status; + u8 reset_ctrl; + u8 flash_ctrl; + u8 eth_ctrl; + u8 usb_ctrl; + u8 irq_ctrl; }; #define BOARD_CANYONLANDS_PCIE 1 @@ -195,16 +195,6 @@ int board_early_init_f(void) mtdcr(AHB_TOP, 0x8000004B); mtdcr(AHB_BOT, 0x8000004B); - if (pvr_460ex()) { - /* - * Configure USB-STP pins as alternate and not GPIO - * It seems to be neccessary to configure the STP pins as GPIO - * input at powerup (perhaps while USB reset is asserted). So - * we configure those pins to their "real" function now. - */ - gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - } #endif return 0; @@ -222,6 +212,15 @@ int usb_board_init(void) val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); out_8(&bcsr_data->usb_ctrl, val); + /* + * Configure USB-STP pins as alternate and not GPIO + * It seems to be neccessary to configure the STP pins as GPIO + * input at powerup (perhaps while USB reset is asserted). So + * we configure those pins to their "real" function now. + */ + gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + return 0; } @@ -236,6 +235,10 @@ int usb_board_stop(void) val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); out_8(&bcsr_data->usb_ctrl, val); + /* Reconfigure USB-STP pins as input */ + gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0); + gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0); + return 0; } diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c index 0e26b89..5231c7a 100644 --- a/board/lwmon5/kbd.c +++ b/board/lwmon5/kbd.c @@ -45,6 +45,10 @@ static int compare_magic (uchar *kbd_data, uchar *str); /*--------------------- Local macros and constants --------------------*/ #define _NOT_USED_ 0xFFFFFFFF +/*------------------------- dspic io expander -----------------------*/ +#define DSPIC_PON_STATUS_REG 0x80A +#define DSPIC_PON_INV_STATUS_REG 0x80C +#define DSPIC_PON_KEY_REG 0x810 /*------------------------- Keyboard controller -----------------------*/ /* command codes */ #define KEYBD_CMD_READ_KEYS 0x01 @@ -75,6 +79,7 @@ static int compare_magic (uchar *kbd_data, uchar *str); /* maximum number of "magic" key codes that can be assigned */ static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR; +static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR; static uchar *key_match (uchar *); @@ -167,6 +172,23 @@ static void kbd_init (void) } } + +/* Read a register from the dsPIC. */ +int _dspic_read(ushort reg, ushort *data) +{ + uchar buf[sizeof(*data)]; + int rval; + + if (i2c_read(dspic_addr, reg, 2, buf, 2)) + return -1; + + rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data)); + *data = (buf[0] << 8) | buf[1]; + + return rval; +} + + /*********************************************************************** F* Function: int misc_init_r (void) P*A*Z* * @@ -197,6 +219,7 @@ int misc_init_r_kbd (void) uchar kbd_init_status = gd->kbd_status >> 8; uchar kbd_status = gd->kbd_status; uchar val; + ushort data, inv_data; char *str; int i; @@ -231,9 +254,31 @@ int misc_init_r_kbd (void) i2c_write (kbd_addr, 0, 0, &val, 1); i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + /* read out start key from bse01 received via can */ + _dspic_read(DSPIC_PON_STATUS_REG, &data); + /* check highbyte from status register */ + if (data > 0xFF) { + _dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data); + + /* check inverse data */ + if ((data+inv_data) == 0xFFFF) { + /* don't overwrite local key */ + if (kbd_data[1] == 0) { + /* read key value */ + _dspic_read(DSPIC_PON_KEY_REG, &data); + str = (char *)&data; + /* swap bytes */ + kbd_data[1] = str[1]; + kbd_data[2] = str[0]; + printf("CAN received startkey: 0x%X\n", data); + } + } + } + for (i = 0; i < KEYBD_DATALEN; ++i) { sprintf (keybd_env + i + i, "%02X", kbd_data[i]); } + setenv ("keybd", keybd_env); str = strdup ((char *)key_match (kbd_data)); /* decode keys */ diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 9622b70..dd275bf 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -24,10 +24,13 @@ #include <asm/processor.h> #include <asm/ppc4xx-gpio.h> #include <asm/io.h> +#include <post.h> +#include <flash.h> +#include <mtd/cfi_flash.h> DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST; ulong flash_get_size(ulong base, int banknum); int misc_init_r_kbd(void); @@ -97,16 +100,18 @@ int board_early_init_f(void) gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1); #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 - gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1); + /* enable the LSB transmitter */ + gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); + /* enable the CAN transmitter */ + gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1); reg = 0; /* reuse as counter */ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) & ~CONFIG_SYS_DSPIC_TEST_MASK); - while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { + while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { udelay(1000); } - gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0); if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) { /* set "boot error" flag */ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, @@ -135,9 +140,61 @@ int board_early_init_f(void) return 0; } -/*---------------------------------------------------------------------------+ - | misc_init_r. - +---------------------------------------------------------------------------*/ +/* + * Override weak default with board specific version + */ +phys_addr_t cfi_flash_bank_addr(int bank) +{ + return lwmon5_cfi_flash_bank_addr[bank]; +} + +/* + * Override the weak default mapping function with a board specific one + */ +u32 flash_get_bank_size(int cs, int idx) +{ + return flash_info[idx].size; +} + +int board_early_init_r(void) +{ + u32 val0, val1; + + /* + * lwmon5 is manufactured in 2 different board versions: + * The lwmon5a board has 64MiB NOR flash instead of the + * 128MiB of the original lwmon5. Unfortunately the CFI driver + * will report 2 banks of 64MiB even for the smaller flash + * chip, since the bank is mirrored. To fix this, we bring + * one bank into CFI query mode and read its response. This + * enables us to detect the real number of flash devices/ + * banks which will be used later on by the common CFI driver. + */ + + /* Put bank 0 into CFI command mode and read */ + out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098); + val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP); + val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP); + + /* Reset flash again out of query mode */ + out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0); + + /* When not identical, we have 2 different flash devices/banks */ + if (val0 != val1) + return 0; + + /* + * Now we're sure that we're running on a LWMON5a board with + * only 64MiB NOR flash in one bank: + * + * Set flash base address and bank count for CFI driver probing. + */ + cfi_flash_num_flash_banks = 1; + lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0; + + return 0; +} + int misc_init_r(void) { u32 pbcr; @@ -145,7 +202,7 @@ int misc_init_r(void) u32 reg; unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; - unsigned long sdr0_pfc1; + unsigned long sdr0_pfc1, sdr0_srst; /* * FLASH stuff... @@ -158,32 +215,7 @@ int misc_init_r(void) gd->bd->bi_flashoffset = 0; mfebc(PB0CR, pbcr); - switch (gd->bd->bi_flashsize) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - case 32 << 20: - size_val = 5; - break; - case 64 << 20: - size_val = 6; - break; - case 128 << 20: - size_val = 7; - break; - } + size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); mtebc(PB0CR, pbcr); @@ -193,53 +225,92 @@ int misc_init_r(void) flash_get_size(gd->bd->bi_flashstart, 0); /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[1]); + flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff, + &flash_info[cfi_flash_num_flash_banks - 1]); /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, - &flash_info[1]); + flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1, + &flash_info[cfi_flash_num_flash_banks - 1]); /* * USB suff... */ + + /* Reset USB */ + /* Reset of USB2PHY0 must be active at least 10 us */ + mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D); + udelay(2000); + + mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI | + SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 | + SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40); + udelay(2000); + + /* Errata CHIP_6 */ + + /* 1. Set internal PHY configuration */ /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); mfsdr(SDR0_USB0, usb2d0cr); mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); mfsdr(SDR0_USB2H0CR, usb2h0cr); - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ - - /* An 8-bit/60MHz interface is the only possible alternative - when connecting the Device to the PHY */ - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + + /* + * An 8-bit/60MHz interface is the only possible alternative + * when connecting the Device to the PHY + */ + usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ mtsdr(SDR0_PFC1, sdr0_pfc1); mtsdr(SDR0_USB0, usb2d0cr); mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr); + /* 2. De-assert internal PHY reset */ + mfsdr(SDR0_SRST1, sdr0_srst); + sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY; + mtsdr(SDR0_SRST1, sdr0_srst); + + /* 3. Wait for more than 1 ms */ + udelay(2000); + + /* 4. De-assert USB 2.0 Host main reset */ + mfsdr(SDR0_SRST0, sdr0_srst); + sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H; + mtsdr(SDR0_SRST0, sdr0_srst); + udelay(1000); + + /* 5. De-assert reset of OPB2 cores */ + mfsdr(SDR0_SRST1, sdr0_srst); + sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1; + sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40; + sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2; + mtsdr(SDR0_SRST1, sdr0_srst); + udelay(1000); + + /* 6. Set EHCI Configure FLAG */ + + /* 7. Reassert internal PHY reset: */ + mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY); + udelay(1000); + /* * Clear resets */ - udelay (1000); mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); mtsdr(SDR0_SRST0, 0x00000000); printf("USB: Host(int phy) Device(ext phy)\n"); @@ -264,7 +335,7 @@ int checkboard(void) { char *s = getenv("serial#"); - printf("Board: lwmon5"); + puts("Board: lwmon5"); if (s != NULL) { puts(", serial# "); @@ -331,34 +402,33 @@ U_BOOT_CMD( extern GraphicDevice mb862xx; -static const gdc_regs init_regs [] = -{ - {0x0100, 0x00000f00}, - {0x0020, 0x801401df}, - {0x0024, 0x00000000}, - {0x0028, 0x00000000}, - {0x002c, 0x00000000}, - {0x0110, 0x00000000}, - {0x0114, 0x00000000}, - {0x0118, 0x01df0280}, - {0x0004, 0x031f0000}, - {0x0008, 0x027f027f}, - {0x000c, 0x015f028f}, - {0x0010, 0x020c0000}, - {0x0014, 0x01df01ea}, - {0x0018, 0x00000000}, - {0x001c, 0x01e00280}, - {0x0100, 0x80010f00}, - {0x0, 0x0} +static const gdc_regs init_regs [] = { + { 0x0100, 0x00000f00 }, + { 0x0020, 0x801401df }, + { 0x0024, 0x00000000 }, + { 0x0028, 0x00000000 }, + { 0x002c, 0x00000000 }, + { 0x0110, 0x00000000 }, + { 0x0114, 0x00000000 }, + { 0x0118, 0x01df0280 }, + { 0x0004, 0x031f0000 }, + { 0x0008, 0x027f027f }, + { 0x000c, 0x015f028f }, + { 0x0010, 0x020c0000 }, + { 0x0014, 0x01df01ea }, + { 0x0018, 0x00000000 }, + { 0x001c, 0x01e00280 }, + { 0x0100, 0x80010f00 }, + { 0x0, 0x0 } }; -const gdc_regs *board_get_regs (void) +const gdc_regs *board_get_regs(void) { return init_regs; } /* Returns Lime base address */ -unsigned int board_video_init (void) +unsigned int board_video_init(void) { /* * Reset Lime controller @@ -375,7 +445,7 @@ unsigned int board_video_init (void) return CONFIG_SYS_LIME_BASE_0; } -#define DEFAULT_BRIGHTNESS 0x64 +#define DEFAULT_BRIGHTNESS 0x64 static void board_backlight_brightness(int brightness) { @@ -390,7 +460,7 @@ static void board_backlight_brightness(int brightness) } } -void board_backlight_switch (int flag) +void board_backlight_switch(int flag) { char * param; int rc; @@ -410,15 +480,14 @@ void board_backlight_switch (int flag) /* * Return text to be printed besides the logo. */ -void video_get_info_str (int line_number, char *info) +void video_get_info_str(int line_number, char *info) { - if (line_number == 1) { - strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)"); - } else { + if (line_number == 1) + strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)"); + else info [0] = '\0'; - } } -#endif +#endif /* CONFIG_CONSOLE_EXTRA_INFO */ #endif /* CONFIG_VIDEO */ void board_reset(void) @@ -184,6 +184,7 @@ t3corp powerpc ppc4xx zeus powerpc ppc4xx acadia powerpc ppc4xx - amcc bamboo powerpc ppc4xx - amcc +bluestone powerpc ppc4xx - amcc bubinga powerpc ppc4xx - amcc ebony powerpc ppc4xx - amcc katmai powerpc ppc4xx - amcc diff --git a/common/fdt_support.c b/common/fdt_support.c index 6f32e3f..0ed6e77 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -620,7 +620,7 @@ int fdt_fixup_nor_flash_size(void *blob) int off; int len; struct fdt_property *prop; - u32 *reg; + u32 *reg, *reg2; int i; for (i = 0; i < 2; i++) { @@ -640,18 +640,21 @@ int fdt_fixup_nor_flash_size(void *blob) * There might be multiple reg-tuples, * so loop through them all */ - len /= tuple_size; - reg = (u32 *)&prop->data[0]; - for (idx = 0; idx < len; idx++) { + reg = reg2 = (u32 *)&prop->data[0]; + for (idx = 0; idx < (len / tuple_size); idx++) { /* * Update size in reg property */ reg[2] = flash_get_bank_size(reg[0], idx); - fdt_setprop(blob, off, "reg", reg, - tuple_size); - reg += tuple_size; + + /* + * Point to next reg tuple + */ + reg += 3; } + + fdt_setprop(blob, off, "reg", reg2, len); } /* Move to next compatible node */ diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h new file mode 100644 index 0000000..560c64f --- /dev/null +++ b/include/configs/bluestone.h @@ -0,0 +1,178 @@ +/* + * bluestone.h - configuration for Bluestone (APM821XX) + * + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri@apm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_APM821XX 1 /* APM821XX series */ +#define CONFIG_HOSTNAME bluestone + +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" +#define CONFIG_SYS_CLK_FREQ 50000000 + +#define CONFIG_BOARD_TYPES 1 /* support board types */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +/* EBC stuff */ +/* later mapped to this addr */ +#define CONFIG_SYS_FLASH_BASE 0xFFF00000 +#define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */ + +/* EBC Boot Space: 0xFF000000 */ +#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 +#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */ +#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/ + +#define CONFIG_SYS_SRAM_SIZE (256 << 10) +/* + * Initial RAM & stack pointer (placed in OCM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Environment + */ +/* + * Define here the location of the environment variables (FLASH). + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 80 +/* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 +/* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 +/* use buffered writes (20x faster) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +/* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* SDRAM */ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */ +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ +#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ +#define CONFIG_DDR_ECC 1 /* with ECC support */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */ + +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 + +/* + * Ethernet + */ +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII +#define CONFIG_HAS_ETH0 +/* PHY address, See schematics */ +#define CONFIG_PHY_ADDR 0x1f +/* reset phy upon startup */ +#define CONFIG_PHY_RESET 1 +/* Include GbE speed/duplex detection */ +#define CONFIG_PHY_GIGE 1 +#define CONFIG_PHY_DYNAMIC_ANEG 1 + +/* + * External Bus Controller (EBC) Setup + **/ +#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \ + EBC_CFG_PTD_ENABLE | \ + EBC_CFG_RTC_2048PERCLK | \ + EBC_CFG_ATC_HI | \ + EBC_CFG_DTC_HI | \ + EBC_CFG_CTC_HI | \ + EBC_CFG_OEO_PREVIOUS) +/* NOR Flash */ +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(64) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(1) | \ + EBC_BXAP_OEN_ENCODE(2) | \ + EBC_BXAP_WBN_ENCODE(2) | \ + EBC_BXAP_WBF_ENCODE(2) | \ + EBC_BXAP_TH_ENCODE(7) | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +/* Peripheral Bank Configuration Register - EBC_BxCR */ +#define CONFIG_SYS_EBC_PB0CR \ + (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_8BIT) + + +#endif /* __CONFIG_H */ diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h index 26992e7..68bf998 100644 --- a/include/configs/hcu4.h +++ b/include/configs/hcu4.h @@ -191,7 +191,7 @@ CONFIG_SYS_POST_ETHER | \ CONFIG_SYS_POST_SPR) -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE} +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 } #undef CONFIG_LOGBUFFER #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index f2ab50c..5aa304d 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -208,7 +208,7 @@ CONFIG_SYS_POST_ETHER | \ CONFIG_SYS_POST_SPR) -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE} +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 } #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 37eaf8f..612a0fe 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -457,7 +457,8 @@ CONFIG_SYS_POST_UART) /* Define here the base-addresses of the UARTs to test in POST */ -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE} +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ + CONFIG_SYS_NS16550_COM2 } #define CONFIG_LOGBUFFER #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 72e02f8..4a3b1dc 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2008 + * (C) Copyright 2007-2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -18,58 +18,63 @@ * MA 02111-1307 USA */ -/************************************************************************ +/* * lwmon5.h - configuration for lwmon5 board - ***********************************************************************/ + */ #ifndef __CONFIG_H #define __CONFIG_H -/*----------------------------------------------------------------------- +/* + * Liebherr extra version info + */ +#define CONFIG_IDENT_STRING " - v2.0" + +/* * High Level Configuration Options - *----------------------------------------------------------------------*/ + */ #define CONFIG_LWMON5 1 /* Board is lwmon5 */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_BOARD_RESET 1 /* Call board_reset */ +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ +#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */ +#define CONFIG_MISC_INIT_R /* Call misc_init_r */ +#define CONFIG_BOARD_RESET /* Call board_reset */ -/*----------------------------------------------------------------------- +/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */ + */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of U-Boot */ +#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1) +#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */ #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_LIME_BASE_0 0xc0000000 -#define CONFIG_SYS_LIME_BASE_1 0xc1000000 -#define CONFIG_SYS_LIME_BASE_2 0xc2000000 -#define CONFIG_SYS_LIME_BASE_3 0xc3000000 -#define CONFIG_SYS_FPGA_BASE_0 0xc4000000 -#define CONFIG_SYS_FPGA_BASE_1 0xc4200000 +#define CONFIG_SYS_LIME_BASE_0 0xc0000000 +#define CONFIG_SYS_LIME_BASE_1 0xc1000000 +#define CONFIG_SYS_LIME_BASE_2 0xc2000000 +#define CONFIG_SYS_LIME_BASE_3 0xc3000000 +#define CONFIG_SYS_FPGA_BASE_0 0xc4000000 +#define CONFIG_SYS_FPGA_BASE_1 0xc4200000 #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 -#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 -#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000) +#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000) +#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000) #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer - *----------------------------------------------------------------------*/ /* + * Initial RAM & stack pointer + * * On LWMON5 we use D-cache as init-ram and stack pointer. We also move * the POST_WORD from OCM to a 440EPx register that preserves it's * content during reset (GPT0_COMP6). This way we reserve the OCM (16k) @@ -77,18 +82,18 @@ */ #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ -#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_INIT_RAM_END (4 << 10) #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data*/ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +/* unused GPT0 COMP reg */ #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) - /* unused GPT0 COMP reg */ -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ - /* 440EPx errata CHIP 11 */ #define CONFIG_SYS_OCM_SIZE (16 << 10) +/* 440EPx errata CHIP 11: don't use last 4kbytes */ +#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* Additional registers for watchdog timer post test */ - #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2) #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1) #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR @@ -100,9 +105,9 @@ #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300 #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00 -/*----------------------------------------------------------------------- +/* * Serial Port - *----------------------------------------------------------------------*/ + */ #define CONFIG_CONS_INDEX 2 /* Use UART1 */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL @@ -110,77 +115,80 @@ #define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_SERIAL_MULTI #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -/*----------------------------------------------------------------------- +/* * Environment - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + */ +#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ -/*----------------------------------------------------------------------- +/* * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CONFIG_SYS_FLASH0 0xFC000000 #define CONFIG_SYS_FLASH1 0xF8000000 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ +#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ +#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */ #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -/*----------------------------------------------------------------------- +/* * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */ + */ +#define CONFIG_SYS_MBYTES_SDRAM 256 #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ -#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */ -#define CONFIG_DDR_ECC 1 /* enable ECC */ -#define CONFIG_SYS_POST_ECC_ON CONFIG_SYS_POST_ECC +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ +#define CONFIG_DDR_ECC /* enable ECC */ /* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_ECC_ON | \ - CONFIG_SYS_POST_ETHER | \ - CONFIG_SYS_POST_FPU | \ - CONFIG_SYS_POST_I2C | \ - CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_OCM | \ - CONFIG_SYS_POST_RTC | \ - CONFIG_SYS_POST_SPR | \ - CONFIG_SYS_POST_UART | \ - CONFIG_SYS_POST_SYSMON | \ - CONFIG_SYS_POST_WATCHDOG | \ - CONFIG_SYS_POST_DSP | \ - CONFIG_SYS_POST_BSPEC1 | \ - CONFIG_SYS_POST_BSPEC2 | \ - CONFIG_SYS_POST_BSPEC3 | \ - CONFIG_SYS_POST_BSPEC4 | \ +#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ + CONFIG_SYS_POST_CPU | \ + CONFIG_SYS_POST_ECC | \ + CONFIG_SYS_POST_ETHER | \ + CONFIG_SYS_POST_FPU | \ + CONFIG_SYS_POST_I2C | \ + CONFIG_SYS_POST_MEMORY | \ + CONFIG_SYS_POST_OCM | \ + CONFIG_SYS_POST_RTC | \ + CONFIG_SYS_POST_SPR | \ + CONFIG_SYS_POST_UART | \ + CONFIG_SYS_POST_SYSMON | \ + CONFIG_SYS_POST_WATCHDOG | \ + CONFIG_SYS_POST_DSP | \ + CONFIG_SYS_POST_BSPEC1 | \ + CONFIG_SYS_POST_BSPEC2 | \ + CONFIG_SYS_POST_BSPEC3 | \ + CONFIG_SYS_POST_BSPEC4 | \ CONFIG_SYS_POST_BSPEC5) -#define CONFIG_POST_WATCHDOG {\ +/* Define here the base-addresses of the UARTs to test in POST */ +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ + CONFIG_SYS_NS16550_COM2 } + +#define CONFIG_POST_WATCHDOG { \ "Watchdog timer test", \ "watchdog", \ "This test checks the watchdog timer.", \ @@ -188,10 +196,10 @@ &lwmon5_watchdog_post_test, \ NULL, \ NULL, \ - CONFIG_SYS_POST_WATCHDOG \ + CONFIG_SYS_POST_WATCHDOG \ } -#define CONFIG_POST_BSPEC1 {\ +#define CONFIG_POST_BSPEC1 { \ "dsPIC init test", \ "dspic_init", \ "This test returns result of dsPIC READY test run earlier.", \ @@ -199,10 +207,10 @@ &dspic_init_post_test, \ NULL, \ NULL, \ - CONFIG_SYS_POST_BSPEC1 \ + CONFIG_SYS_POST_BSPEC1 \ } -#define CONFIG_POST_BSPEC2 {\ +#define CONFIG_POST_BSPEC2 { \ "dsPIC test", \ "dspic", \ "This test gets result of dsPIC POST and dsPIC version.", \ @@ -210,32 +218,32 @@ &dspic_post_test, \ NULL, \ NULL, \ - CONFIG_SYS_POST_BSPEC2 \ + CONFIG_SYS_POST_BSPEC2 \ } -#define CONFIG_POST_BSPEC3 {\ +#define CONFIG_POST_BSPEC3 { \ "FPGA test", \ "fpga", \ "This test checks FPGA registers and memory.", \ - POST_RAM | POST_ALWAYS, \ + POST_RAM | POST_ALWAYS | POST_MANUAL, \ &fpga_post_test, \ NULL, \ NULL, \ - CONFIG_SYS_POST_BSPEC3 \ + CONFIG_SYS_POST_BSPEC3 \ } -#define CONFIG_POST_BSPEC4 {\ +#define CONFIG_POST_BSPEC4 { \ "GDC test", \ "gdc", \ "This test checks GDC registers and memory.", \ - POST_RAM | POST_ALWAYS, \ + POST_RAM | POST_ALWAYS | POST_MANUAL,\ &gdc_post_test, \ NULL, \ NULL, \ - CONFIG_SYS_POST_BSPEC4 \ + CONFIG_SYS_POST_BSPEC4 \ } -#define CONFIG_POST_BSPEC5 {\ +#define CONFIG_POST_BSPEC5 { \ "SYSMON1 test", \ "sysmon1", \ "This test checks GPIO_62_EPX pin indicating power failure.", \ @@ -243,7 +251,7 @@ &sysmon1_post_test, \ NULL, \ NULL, \ - CONFIG_SYS_POST_BSPEC5 \ + CONFIG_SYS_POST_BSPEC5 \ } #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ @@ -253,34 +261,53 @@ #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE) #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ -/*----------------------------------------------------------------------- +/* * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ + */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */ +#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */ +#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */ +#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */ +#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */ +#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */ +#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */ + #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */ /* 64 byte page write mode using*/ /* last 6 bits of the address */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE + +#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ +#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ +#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */ + +#define I2C_ADDR_LIST { \ + CONFIG_SYS_I2C_RTC_ADDR, \ + CONFIG_SYS_I2C_EEPROM_CPU_ADDR, \ + CONFIG_SYS_I2C_EEPROM_MB_ADDR, \ + CONFIG_SYS_I2C_DSPIC_ADDR, \ + CONFIG_SYS_I2C_DSPIC_2_ADDR, \ + CONFIG_SYS_I2C_DSPIC_KEYB_ADDR, \ + CONFIG_SYS_I2C_DSPIC_IO_ADDR } -#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ -#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ -#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */ +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +/* Update size in "reg" property of NOR FLASH device tree nodes */ +#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ -#if 0 -#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ -#define CONFIG_AUTOBOOT_PROMPT \ - "\nEnter password - autoboot in %d sec...\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ -#endif #define CONFIG_PREBOOT "setenv bootdelay 15" @@ -314,15 +341,11 @@ "cp.b 200000 FFF80000 80000\0" \ "upd=run load update\0" \ "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ - "source 200000\0" \ + "autoscr 200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -410,9 +433,9 @@ #define CONFIG_CMD_USB #endif -/*----------------------------------------------------------------------- +/* * Miscellaneous configurable options - *----------------------------------------------------------------------*/ + */ #define CONFIG_SUPPORT_VFAT #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -445,9 +468,9 @@ #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -/*----------------------------------------------------------------------- +/* * PCI stuff - *----------------------------------------------------------------------*/ + */ /* General PCI */ #define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ @@ -461,29 +484,32 @@ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ +#ifndef DEBUG #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ +#endif #define CONFIG_WD_PERIOD 40000 /* in usec */ #define CONFIG_WD_MAX_RATE 66600 /* in ticks */ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the 40x Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ -/*----------------------------------------------------------------------- +/* * External Bus Controller (EBC) Setup - *----------------------------------------------------------------------*/ + */ #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE /* Memory Bank 0 (NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x03050200 +#define CONFIG_SYS_EBC_PB0AP 0x03000280 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000) /* Memory Bank 1 (Lime) initialization */ #define CONFIG_SYS_EBC_PB1AP 0x01004380 -#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xdc000) +#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000) /* Memory Bank 2 (FPGA) initialization */ #define CONFIG_SYS_EBC_PB2AP 0x01004400 @@ -495,19 +521,27 @@ #define CONFIG_SYS_EBC_CFG 0xb8400000 -/*----------------------------------------------------------------------- +/* * Graphics (Fujitsu Lime) - *----------------------------------------------------------------------*/ + */ +/* SDRAM Clock frequency adjustment register */ +#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038 +#if 1 /* 133MHz is not tested enough, use 100MHz for now */ /* Lime Clock frequency is to set 100MHz */ #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000 -#if 0 +#else /* Lime Clock frequency for 133MHz */ #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000 #endif -/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars - and pixel flare on display when 133MHz was configured. According to - SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */ +/* SDRAM Parameter register */ +#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC +/* + * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars + * and pixel flare on display when 133MHz was configured. According to + * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed + * Grade + */ #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ @@ -516,13 +550,15 @@ #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ #endif -/*----------------------------------------------------------------------- +/* * GPIO Setup - *----------------------------------------------------------------------*/ + */ #define CONFIG_SYS_GPIO_PHY1_RST 12 #define CONFIG_SYS_GPIO_FLASH_WP 14 #define CONFIG_SYS_GPIO_PHY0_RST 22 #define CONFIG_SYS_GPIO_DSPIC_READY 51 +#define CONFIG_SYS_GPIO_CAN_ENABLE 53 +#define CONFIG_SYS_GPIO_LSB_ENABLE 54 #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55 #define CONFIG_SYS_GPIO_HIGHSIDE 56 #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57 @@ -532,7 +568,7 @@ #define CONFIG_SYS_GPIO_SYSMON_STATUS 62 #define CONFIG_SYS_GPIO_WATCHDOG 63 -/*----------------------------------------------------------------------- +/* * PPC440 GPIO Configuration */ #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 905c719..80163d4 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -264,7 +264,8 @@ CONFIG_SYS_POST_UART) /* Define here the base-addresses of the UARTs to test in POST */ -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE} +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ + CONFIG_SYS_NS16550_COM2 } #define CONFIG_LOGBUFFER #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h index 3e04cfe..8dd87cb 100644 --- a/include/configs/mcu25.h +++ b/include/configs/mcu25.h @@ -192,7 +192,7 @@ CONFIG_SYS_POST_ETHER | \ CONFIG_SYS_POST_SPR) -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE} +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 } #undef CONFIG_LOGBUFFER #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ diff --git a/include/configs/zeus.h b/include/configs/zeus.h index aa250cc..06d4526 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -94,7 +94,7 @@ #define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */ /* Define here the base-addresses of the UARTs to test in POST */ -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE} +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 } #define CONFIG_LOGBUFFER #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ diff --git a/post/board/lwmon5/dsp.c b/post/board/lwmon5/dsp.c index 0e6d908..913cd97 100644 --- a/post/board/lwmon5/dsp.c +++ b/post/board/lwmon5/dsp.c @@ -33,20 +33,37 @@ DECLARE_GLOBAL_DATA_PTR; -#define DSP_STATUS_REG 0xC4000008 +#define DSP_STATUS_REG 0xC4000008 +#define FPGA_STATUS_REG 0xC400000C int dsp_post_test(int flags) { + uint old_value; uint read_value; int ret; + /* momorize fpga status */ + old_value = in_be32((void *)FPGA_STATUS_REG); + /* enable outputs */ + out_be32((void *)FPGA_STATUS_REG, 0x30); + + /* generate sync signal */ + out_be32((void *)DSP_STATUS_REG, 0x300); + udelay(5); + out_be32((void *)DSP_STATUS_REG, 0); + udelay(500); + + /* read status */ ret = 0; read_value = in_be32((void *)DSP_STATUS_REG) & 0x3; - if (read_value != 0x3) { + if (read_value != 0x03) { post_log("\nDSP status read %08X\n", read_value); ret = 1; } + /* restore fpga status */ + out_be32((void *)FPGA_STATUS_REG, old_value); + return ret; } diff --git a/post/board/lwmon5/dspic.c b/post/board/lwmon5/dspic.c index ff2ed05..8616739 100644 --- a/post/board/lwmon5/dspic.c +++ b/post/board/lwmon5/dspic.c @@ -38,14 +38,16 @@ DECLARE_GLOBAL_DATA_PTR; #define DSPIC_POST_ERROR_REG 0x800 #define DSPIC_SYS_ERROR_REG 0x802 -#define DSPIC_VERSION_REG 0x804 +#define DSPIC_SYS_VERSION_REG 0x804 +#define DSPIC_FW_VERSION_REG 0x808 #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 /* Verify that dsPIC ready test done early at hw init passed ok */ int dspic_init_post_test(int flags) { - if (in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) & CONFIG_SYS_DSPIC_TEST_MASK) { + if (in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) & + CONFIG_SYS_DSPIC_TEST_MASK) { post_log("dsPIC init test failed\n"); return 1; } @@ -57,46 +59,60 @@ int dspic_init_post_test(int flags) #if CONFIG_POST & CONFIG_SYS_POST_BSPEC2 /* Read a register from the dsPIC. */ -int dspic_read(ushort reg) +int dspic_read(ushort reg, ushort *data) { - uchar buf[2]; + uchar buf[sizeof(*data)]; + int rval; if (i2c_read(CONFIG_SYS_I2C_DSPIC_IO_ADDR, reg, 2, buf, 2)) return -1; + rval = i2c_read(CONFIG_SYS_I2C_DSPIC_IO_ADDR, reg, sizeof(reg), + buf, sizeof(*data)); + *data = (buf[0] << 8) | buf[1]; - return (uint)((buf[0] << 8) | buf[1]); + return rval; } /* Verify error codes regs, display version */ int dspic_post_test(int flags) { - int data; + ushort data; int ret = 0; post_log("\n"); - data = dspic_read(DSPIC_VERSION_REG); - if (data == -1) { - post_log("dsPIC : failed read version\n"); + + /* read dspic FW-Version */ + if (dspic_read(DSPIC_FW_VERSION_REG, &data)) { + post_log("dsPIC: failed read FW-Version\n"); + ret = 1; + } else { + post_log("dsPIC FW-Version: %u.%u\n", + (data >> 8) & 0xFF, data & 0xFF); + } + + /* read dspic SYS-Version */ + if (dspic_read(DSPIC_SYS_VERSION_REG, &data)) { + post_log("dsPIC: failed read version\n"); ret = 1; } else { - post_log("dsPIC version: %u.%u\n", - (data >> 8) & 0xFF, data & 0xFF); + post_log("dsPIC SYS-Version: %u.%u\n", + (data >> 8) & 0xFF, data & 0xFF); } - data = dspic_read(DSPIC_POST_ERROR_REG); - if (data != 0) ret = 1; - if (data == -1) { - post_log("dsPIC : failed read POST code\n"); + /* read dspic POST error code */ + if (dspic_read(DSPIC_POST_ERROR_REG, &data)) { + post_log("dsPIC: failed read POST code\n"); + ret = 1; } else { - post_log("dsPIC POST code 0x%04X\n", data); + post_log("dsPIC POST-ERROR code: 0x%04X\n", data); } - data = dspic_read(DSPIC_SYS_ERROR_REG); - if (data == -1) { - post_log("dsPIC : failed read system error\n"); + /* read dspic SYS error code */ + if ((data = dspic_read(DSPIC_SYS_ERROR_REG, &data))) { + post_log("dsPIC: failed read system error\n"); ret = 1; } else { - post_log("dsPIC SYS-ERROR code: 0x%04X\n", data); + post_log("dsPIC SYS-ERROR code: 0x%04X\n", data); } return ret; diff --git a/post/board/lwmon5/fpga.c b/post/board/lwmon5/fpga.c index 2b84290..3067548 100644 --- a/post/board/lwmon5/fpga.c +++ b/post/board/lwmon5/fpga.c @@ -28,7 +28,7 @@ */ #include <post.h> - +#include <watchdog.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -38,18 +38,28 @@ DECLARE_GLOBAL_DATA_PTR; #define FPGA_RAM_START 0xC4200000 #define FPGA_RAM_END 0xC4203FFF #define FPGA_STAT 0xC400000C +#define FPGA_BUFFER 0x00800000 +#define FPGA_RAM_SIZE (FPGA_RAM_END - FPGA_RAM_START + 1) #if CONFIG_POST & CONFIG_SYS_POST_BSPEC3 -/* Testpattern for fpga memorytest */ -static uint pattern[] = { +const static unsigned long pattern[] = { + 0xffffffff, + 0xaaaaaaaa, + 0xcccccccc, + 0xf0f0f0f0, + 0xff00ff00, + 0xffff0000, + 0x0000ffff, + 0x00ff00ff, + 0x0f0f0f0f, + 0x33333333, 0x55555555, - 0xAAAAAAAA, - 0xAA5555AA, - 0x55AAAA55, - 0x0 + 0x00000000, }; +const static unsigned long otherpattern = 0x01234567; + static int one_scratch_test(uint value) { uint read_value; @@ -62,51 +72,226 @@ static int one_scratch_test(uint value) read_value = in_be32((void *)FPGA_SCRATCH_REG); if (read_value != value) { post_log("FPGA SCRATCH test failed write %08X, read %08X\n", - value, read_value); - ret = 1; + value, read_value); + ret = -1; + } + + return ret; +} + +static int fpga_post_test1(ulong *start, ulong size, ulong val) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = val; + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != val) { + post_log("FPGA Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, val, readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + return ret; +} + +static int fpga_post_test2(ulong *start, ulong size) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = 1 << (i % 32); + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != 1 << (i % 32)) { + post_log("FPGA Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, 1 << (i % 32), readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + return ret; +} + +static int fpga_post_test3(ulong *start, ulong size) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = i; + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != i) { + post_log("FPGA Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, i, readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + return ret; +} + +static int fpga_post_test4(ulong *start, ulong size) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = ~i; + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != ~i) { + post_log("FPGA Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, ~i, readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); } return ret; } /* FPGA Memory-pattern-test */ -static int fpga_mem_test(void * address) +static int fpga_mem_test(void) { - int ret = 1; - uint read_value; - uint old_value; - uint i = 0; - /* save content */ - old_value = in_be32(address); - - while (pattern[i] != 0) { - out_be32(address, pattern[i]); - /* read other location (protect against data lines capacity) */ - ret = in_be16((void *)FPGA_VERSION_REG); - /* verify test pattern */ - read_value = in_be32(address); - - if (read_value != pattern[i]) { - post_log("FPGA Memory test failed."); - post_log(" write %08X, read %08X at address %08X\n", - pattern[i], read_value, address); + int ret = 0; + ulong* start = (ulong *)FPGA_RAM_START; + ulong size = FPGA_RAM_SIZE; + + if (ret == 0) + ret = fpga_post_test1(start, size, 0x00000000); + + if (ret == 0) + ret = fpga_post_test1(start, size, 0xffffffff); + + if (ret == 0) + ret = fpga_post_test1(start, size, 0x55555555); + + if (ret == 0) + ret = fpga_post_test1(start, size, 0xaaaaaaaa); + + WATCHDOG_RESET(); + + if (ret == 0) + ret = fpga_post_test2(start, size); + + if (ret == 0) + ret = fpga_post_test3(start, size); + + if (ret == 0) + ret = fpga_post_test4(start, size); + + return ret; +} + + + +/* Verify FPGA addresslines */ +static int fpga_post_addrline(ulong *address, ulong *base, ulong size) +{ + unsigned long *target; + unsigned long *end; + unsigned long readback; + unsigned long xor; + int ret = 0; + + end = (ulong *)((ulong)base + size); + xor = 0; + + for (xor = sizeof(ulong); xor > 0; xor <<= 1) { + target = (ulong*)((ulong)address ^ xor); + if ((target >= base) && (target < end)) { + *address = ~*target; + readback = *target; + + if (readback == *address) { + post_log("Memory (address line) error at %08x" + "XOR value %08x !\n", + address, target, xor); + ret = -1; + break; + } + } + } + + return ret; +} + +/* Verify FPGA addresslines */ +static int fpga_post_dataline(ulong *address) +{ + unsigned long temp32 = 0; + int i = 0; + int ret = 0; + + for (i = 0; i < ARRAY_SIZE(pattern); i++) { + *address = pattern[i]; + /* + * Put a different pattern on the data lines: otherwise they + * may float long enough to read back what we wrote. + */ + *(address + 1) = otherpattern; + temp32 = *address; + + if (temp32 != pattern[i]){ + post_log("Memory (date line) error at %08x, " + "wrote %08x, read %08x !\n", + address, pattern[i], temp32); ret = 1; - goto out; } - i++; } - ret = 0; -out: - out_be32(address, old_value); return ret; } + /* Verify FPGA, get version & memory size */ int fpga_post_test(int flags) { - uint address; uint old_value; - ushort version; + uint version; uint read_value; int ret = 0; @@ -120,24 +305,57 @@ int fpga_post_test(int flags) out_be32((void *)FPGA_SCRATCH_REG, old_value); - version = in_be16((void *)FPGA_VERSION_REG); - post_log("FPGA : version %u.%u\n", - (version >> 8) & 0xFF, version & 0xFF); + version = in_be32((void *)FPGA_VERSION_REG); + post_log("FPGA version %u.%u\n", + (version >> 8) & 0xFF, version & 0xFF); /* Enable write to FPGA RAM */ out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000); - read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, 0x4000); - post_log("FPGA RAM size: %d bytes\n", read_value); + /* get RAM size */ + read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, FPGA_RAM_SIZE); + post_log("FPGA RAM size %d bytes\n", read_value); + WATCHDOG_RESET(); - for (address = 0; address < 0x1000; address++) { - if (fpga_mem_test((void *)(FPGA_RAM_START + 4*address)) == 1) { - ret = 1; - goto out; - } + /* copy fpga memory to DDR2 RAM*/ + memcpy((void *)FPGA_BUFFER,(void *)FPGA_RAM_START, FPGA_RAM_SIZE); + WATCHDOG_RESET(); + + /* Test datalines */ + if (fpga_post_dataline((ulong *)FPGA_RAM_START)) { + ret = 1; + goto out; + } + WATCHDOG_RESET(); + + /* Test addresslines */ + if (fpga_post_addrline((ulong *)FPGA_RAM_START, + (ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) { + ret = 1; + goto out; } + WATCHDOG_RESET(); + if (fpga_post_addrline((ulong *)FPGA_RAM_END - sizeof(long), + (ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) { + ret = 1; + goto out; + } + WATCHDOG_RESET(); + + /* Memory Pattern Test */ + if (fpga_mem_test()) { + ret = 1; + goto out; + } + WATCHDOG_RESET(); + + /* restore memory */ + memcpy((void *)FPGA_RAM_START,(void *)FPGA_BUFFER, FPGA_RAM_SIZE); + WATCHDOG_RESET(); out: + /* Disable write to RAM */ + out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) & 0xEFFF); return ret; } diff --git a/post/board/lwmon5/gdc.c b/post/board/lwmon5/gdc.c index eb16e36..719194b 100644 --- a/post/board/lwmon5/gdc.c +++ b/post/board/lwmon5/gdc.c @@ -28,18 +28,39 @@ */ #include <post.h> - +#include <watchdog.h> #include <asm/io.h> +#include <video.h> DECLARE_GLOBAL_DATA_PTR; -#define GDC_SCRATCH_REG 0xC1FF8044 -#define GDC_VERSION_REG 0xC1FF8084 -#define GDC_RAM_START 0xC0000000 -#define GDC_RAM_END 0xC2000000 +#define GDC_SCRATCH_REG 0xC1FF8044 +#define GDC_VERSION_REG 0xC1FF8084 +#define GDC_HOST_BASE 0xC1FC0000 +#define GDC_RAM_START 0xC0000000 +#define GDC_RAM_END (GDC_HOST_BASE - 1) +#define GDC_RAM_SIZE (GDC_RAM_END - GDC_RAM_START) #if CONFIG_POST & CONFIG_SYS_POST_BSPEC4 +const static unsigned long pattern[] = { + 0xffffffff, + 0xaaaaaaaa, + 0xcccccccc, + 0xf0f0f0f0, + 0xff00ff00, + 0xffff0000, + 0x0000ffff, + 0x00ff00ff, + 0x0f0f0f0f, + 0x33333333, + 0x55555555, + 0x00000000 +}; + +const static unsigned long otherpattern = 0x01234567; + +/* test write/read og a given LIME Register */ static int gdc_test_reg_one(uint value) { int ret; @@ -53,17 +74,229 @@ static int gdc_test_reg_one(uint value) read_value = in_be32((void *)GDC_SCRATCH_REG); if (read_value != value) { post_log("GDC SCRATCH test failed write %08X, read %08X\n", - value, read_value); + value, read_value); } return (read_value != value); } -/* Verify GDC, get memory size */ +/* test with a given static 32 bit pattern in a given memory addressrange */ +static int gdc_post_test1(ulong *start, ulong size, ulong val) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = val; + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != val) { + post_log("GDC Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, val, readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + return ret; +} + +/* test with dynamic 32 bit pattern in a given memory addressrange */ +static int gdc_post_test2(ulong *start, ulong size) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = 1 << (i % 32); + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != 1 << (i % 32)) { + post_log("GDC Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, 1 << (i % 32), readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + return ret; +} + +/* test with dynamic 32 bit pattern in a given memory addressrange */ +static int gdc_post_test3(ulong *start, ulong size) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = i; + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != i) { + post_log("GDC Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, i, readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + return ret; +} + +/* test with dynamic 32 bit pattern in a given memory addressrange */ +static int gdc_post_test4(ulong *start, ulong size) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = ~i; + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != ~i) { + post_log("GDC Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, ~i, readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + return ret; +} + +/* do some patterntests in a given addressrange */ +int gdc_mem_test(ulong *start, ulong size) +{ + int ret = 0; + + /* + * check addressrange and do different static and dynamic + * pattern tests with it. + */ + if (((void *)start) + size <= (void *)GDC_RAM_END) { + if (ret == 0) + ret = gdc_post_test1(start, size, 0x00000000); + + if (ret == 0) + ret = gdc_post_test1(start, size, 0xffffffff); + + if (ret == 0) + ret = gdc_post_test1(start, size, 0x55555555); + + if (ret == 0) + ret = gdc_post_test1(start, size, 0xaaaaaaaa); + + if (ret == 0) + ret = gdc_post_test2(start, size); + + if (ret == 0) + ret = gdc_post_test3(start, size); + + if (ret == 0) + ret = gdc_post_test4(start, size); + } + + return ret; +} + +/* test function of gdc memory addresslines*/ +static int gdc_post_addrline(ulong *address, ulong *base, ulong size) +{ + ulong *target; + ulong *end; + ulong readback = 0; + ulong xor = 0; + int ret = 0; + + end = (ulong *)((ulong)base + size); + + for (xor = sizeof(long); xor > 0; xor <<= 1) { + target = (ulong *)((ulong)address ^ xor); + if ((target >= base) && (target < end)) { + *address = ~*target; + readback = *target; + } + + if (readback == *address) { + post_log("GDC Memory (address line) error at %08x" + "XOR value %08x !\n", + address, target , xor); + ret = -1; + break; + } + } + + return ret; +} + +static int gdc_post_dataline(ulong *address) +{ + unsigned long temp32 = 0; + int i = 0; + int ret = 0; + + for (i = 0; i < ARRAY_SIZE(pattern); i++) { + *address = pattern[i]; + /* + * Put a different pattern on the data lines: otherwise they + * may float long enough to read back what we wrote. + */ + *(address + 1) = otherpattern; + temp32 = *address; + + if (temp32 != pattern[i]){ + post_log("GDC Memory (date line) error at %08x, " + "wrote %08x, read %08x !\n", + address, pattern[i], temp32); + ret = 1; + } + } + + return ret; +} + +/* Verify GDC, get memory size, verify GDC memory */ int gdc_post_test(int flags) { - uint old_value; - int ret = 0; + uint old_value; + int i = 0; + int ret = 0; post_log("\n"); old_value = in_be32((void *)GDC_SCRATCH_REG); @@ -84,13 +317,64 @@ int gdc_post_test(int flags) old_value = in_be32((void *)GDC_VERSION_REG); post_log("GDC chip version %u.%u, year %04X\n", - (old_value >> 8) & 0xFF, old_value & 0xFF, - (old_value >> 16) & 0xFFFF); + (old_value >> 8) & 0xFF, old_value & 0xFF, + (old_value >> 16) & 0xFFFF); old_value = get_ram_size((void *)GDC_RAM_START, - GDC_RAM_END - GDC_RAM_START); + 0x02000000); + + debug("GDC RAM size (ist): %d bytes\n", old_value); + debug("GDC RAM size (soll): %d bytes\n", GDC_RAM_SIZE); post_log("GDC RAM size: %d bytes\n", old_value); + /* Test SDRAM datalines */ + if (gdc_post_dataline((ulong *)GDC_RAM_START)) { + ret = 1; + goto out; + } + WATCHDOG_RESET(); + + /* Test SDRAM adresslines */ + if (gdc_post_addrline((ulong *)GDC_RAM_START, + (ulong *)GDC_RAM_START, GDC_RAM_SIZE)) { + ret = 1; + goto out; + } + WATCHDOG_RESET(); + if (gdc_post_addrline((ulong *)GDC_RAM_END - sizeof(long), + (ulong *)GDC_RAM_START, GDC_RAM_SIZE)) { + ret = 1; + goto out; + } + WATCHDOG_RESET(); + + /* memory pattern test */ + debug("GDC Memory test (flags %8x:%8x)\n", flags, + POST_SLOWTEST | POST_MANUAL); + + if (flags & POST_MANUAL) { + debug("Full memory test\n"); + if (gdc_mem_test((ulong *)GDC_RAM_START, GDC_RAM_SIZE)) { + ret = 1; + goto out; + } + /* load splashscreen again */ + } else { + debug("smart memory test\n"); + for (i = 0; i < (GDC_RAM_SIZE >> 20) && ret == 0; i++) { + if (ret == 0) + ret = gdc_mem_test((ulong *)(GDC_RAM_START + + (i << 20)), + 0x800); + if (ret == 0) + ret = gdc_mem_test((ulong *)(GDC_RAM_START + + (i << 20) + 0xff800), + 0x800); + } + } + WATCHDOG_RESET(); + +out: return ret; } #endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC4 */ diff --git a/post/board/lwmon5/sysmon.c b/post/board/lwmon5/sysmon.c index 9c49d0e..4a78240 100644 --- a/post/board/lwmon5/sysmon.c +++ b/post/board/lwmon5/sysmon.c @@ -56,7 +56,7 @@ DECLARE_GLOBAL_DATA_PTR; /* from dspic.c */ -extern int dspic_read(ushort reg); +extern int dspic_read(ushort reg, ushort *data); #define REG_TEMPERATURE 0x12BC #define REG_VOLTAGE_5V 0x12CA @@ -76,31 +76,38 @@ extern int dspic_read(ushort reg); typedef struct sysmon_s sysmon_t; typedef struct sysmon_table_s sysmon_table_t; -static void sysmon_dspic_init (sysmon_t * this); -static int sysmon_dspic_read (sysmon_t * this, uint addr); -static void sysmon_backlight_disable (sysmon_table_t * this); +static void sysmon_dspic_init(sysmon_t *this); +static int sysmon_dspic_read(sysmon_t *this, uint addr, int *val); +static int sysmon_dspic_read_sgn(sysmon_t *this, uint addr, int *val); +static void sysmon_backlight_disable(sysmon_table_t *this); -struct sysmon_s -{ +struct sysmon_s { uchar chip; void (*init)(sysmon_t *); - int (*read)(sysmon_t *, uint); + int (*read)(sysmon_t *, uint, int *); }; -static sysmon_t sysmon_dspic = - {CONFIG_SYS_I2C_DSPIC_IO_ADDR, sysmon_dspic_init, sysmon_dspic_read}; +static sysmon_t sysmon_dspic = { + CONFIG_SYS_I2C_DSPIC_IO_ADDR, + sysmon_dspic_init, + sysmon_dspic_read +}; -static sysmon_t * sysmon_list[] = -{ +static sysmon_t sysmon_dspic_sgn = { + CONFIG_SYS_I2C_DSPIC_IO_ADDR, + sysmon_dspic_init, + sysmon_dspic_read_sgn +}; + +static sysmon_t *sysmon_list[] = { &sysmon_dspic, NULL }; -struct sysmon_table_s -{ - char * name; - char * unit_name; - sysmon_t * sysmon; +struct sysmon_table_s { + char *name; + char *unit_name; + sysmon_t *sysmon; void (*exec_before)(sysmon_table_t *); void (*exec_after)(sysmon_table_t *); @@ -118,37 +125,43 @@ struct sysmon_table_s uint addr; }; -static sysmon_table_t sysmon_table[] = -{ +static sysmon_table_t sysmon_table[] = { { - "Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable, - 1, 1, -32768, 32767, 0xFFFF, - 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0, - 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0, - REG_TEMPERATURE, + "Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable, + 1, 1, -32768, 32767, 0xFFFF, + 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0, + 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0, + REG_TEMPERATURE, }, { - "+ 5 V", "V", &sysmon_dspic, NULL, NULL, - 100, 1000, -0x8000, 0x7FFF, 0xFFFF, - 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0, - 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0, - REG_VOLTAGE_5V, + "+ 5 V", "V", &sysmon_dspic, NULL, NULL, + 100, 1000, -0x8000, 0x7FFF, 0xFFFF, + 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0, + 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0, + REG_VOLTAGE_5V, }, { - "+ 5 V standby", "V", &sysmon_dspic, NULL, NULL, - 100, 1000, -0x8000, 0x7FFF, 0xFFFF, - 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0, - 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0, - REG_VOLTAGE_5V_STANDBY, + "+ 5 V standby", "V", &sysmon_dspic, NULL, NULL, + 100, 1000, -0x8000, 0x7FFF, 0xFFFF, + 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0, + 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0, + REG_VOLTAGE_5V_STANDBY, + }, + + { + "Temperature", "°C", &sysmon_dspic_sgn, NULL, sysmon_backlight_disable, + 1, 1, -32768, 32767, 0xFFFF, + 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0, + 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0, + REG_TEMPERATURE, }, }; -static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]); -int sysmon_init_f (void) +int sysmon_init_f(void) { - sysmon_t ** l; + sysmon_t **l; for (l = sysmon_list; *l; l++) (*l)->init(*l); @@ -156,12 +169,12 @@ int sysmon_init_f (void) return 0; } -void sysmon_reloc (void) +void sysmon_reloc(void) { /* Do nothing for now, sysmon_reloc() is required by the sysmon post */ } -static char *sysmon_unit_value (sysmon_table_t *s, uint val) +static char *sysmon_unit_value(sysmon_table_t *s, uint val) { static char buf[32]; char *p, sign; @@ -176,14 +189,13 @@ static char *sysmon_unit_value (sysmon_table_t *s, uint val) if (unit_val < 0) { sign = '-'; unit_val = -unit_val; - } else + } else { sign = '+'; + } p = buf + sprintf(buf, "%c%2d", sign, unit_val / s->unit_div); - frac = unit_val % s->unit_div; - frac /= (s->unit_div / s->unit_precision); decimal = s->unit_precision; @@ -197,58 +209,84 @@ static char *sysmon_unit_value (sysmon_table_t *s, uint val) return buf; } -static void sysmon_dspic_init (sysmon_t * this) +static void sysmon_dspic_init(sysmon_t *this) { } -static int sysmon_dspic_read (sysmon_t * this, uint addr) +static int sysmon_dspic_read(sysmon_t *this, uint addr, int *val) { - int res = dspic_read(addr); + ushort data; + + if (dspic_read(addr, &data) == 0){ + /* To fit into the table range we should add 0x8000 */ + *val = data + 0x8000; + return 0; + } - /* To fit into the table range we should add 0x8000 */ - return (res == -1) ? -1 : (res + 0x8000); + return -1; } -static void sysmon_backlight_disable (sysmon_table_t * this) +static int sysmon_dspic_read_sgn(sysmon_t *this, uint addr, int *val) +{ + ushort data; + + if (dspic_read(addr, &data) == 0){ + /* To fit into the table range we should add 0x8000 */ + *val = (signed short)data + 0x8000; + return 0; + } + + return -1; +} + +static void sysmon_backlight_disable(sysmon_table_t *this) { #if defined(CONFIG_VIDEO) board_backlight_switch(this->val_valid_alt); #endif } -int sysmon_post_test (int flags) +int sysmon_post_test(int flags) { int res = 0; sysmon_table_t * t; int val; - for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) { + for (t = sysmon_table; t < sysmon_table + ARRAY_SIZE(sysmon_table); t++) { + t->val_valid = 1; if (t->exec_before) t->exec_before(t); - val = t->sysmon->read(t->sysmon, t->addr); - if (val != -1) { - t->val_valid = val >= t->val_min && val <= t->val_max; - t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt; - } else { + if (t->sysmon->read(t->sysmon, t->addr, &val) != 0) { t->val_valid = 0; t->val_valid_alt = 0; + post_log(": read failed\n"); + res = 1; + break; + } + + if (t->val_valid != 0) { + t->val_valid = val >= t->val_min && val <= t->val_max; + t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt; } if (t->exec_after) t->exec_after(t); - if ((!t->val_valid) || (flags & POST_MANUAL)) { - printf("%-17s = %-10s ", t->name, sysmon_unit_value(t, val)); - printf("allowed range"); - printf(" %-8s ..", sysmon_unit_value(t, t->val_min)); - printf(" %-8s", sysmon_unit_value(t, t->val_max)); - printf(" %s\n", t->val_valid ? "OK" : "FAIL"); + if ((!t->val_valid) || (flags)) { + post_log("\n\t%-17s = %-10s ", t->name, sysmon_unit_value(t, val)); + post_log("allowed range"); + post_log(" %-8s ..", sysmon_unit_value(t, t->val_min)); + post_log(" %-8s", sysmon_unit_value(t, t->val_max)); + post_log(" %s", t->val_valid ? "OK" : "FAIL"); } - if (!t->val_valid) + if (!t->val_valid) { res = 1; + break; + } } + post_log("\n"); return res; } diff --git a/post/board/lwmon5/watchdog.c b/post/board/lwmon5/watchdog.c index f181506..4e5ed0d 100644 --- a/post/board/lwmon5/watchdog.c +++ b/post/board/lwmon5/watchdog.c @@ -57,8 +57,11 @@ int sysmon1_post_test(int flags) * 3.1. GPIO62 is low * Assuming system voltage failure. */ - post_log("Abnormal voltage detected (GPIO62)\n"); + post_log("sysmon1 Abnormal voltage detected (GPIO62)\n"); + post_log("POST sysmon1 FAILED\n"); return 1; + } else { + post_log("sysmon1 PASSED\n"); } return 0; @@ -117,10 +120,16 @@ int lwmon5_watchdog_post_test(int flags) ulong time; /* 3.3.1. So, the test succeed, save measured time to syslog. */ time = in_be32((void *)CONFIG_SYS_WATCHDOG_TIME_ADDR); - post_log("hw watchdog time : %u ms, passed ", time); - /* 3.3.2. Set scratch register 1 to 0x0000xxxx */ - watchdog_magic_write(0); - return 0; + if (time > 90 ) { /* ms*/ + post_log("hw watchdog time : %u ms, passed ", time); + /* 3.3.2. Set scratch register 1 to 0x0000xxxx */ + watchdog_magic_write(0); + return 0; + } else { + /*test minimum watchdogtime */ + post_log("hw watchdog time : %u ms, failed ", time); + return 2; + } } return -1; } diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c index 6b61cc1..d768956 100644 --- a/post/cpu/ppc4xx/uart.c +++ b/post/cpu/ppc4xx/uart.c @@ -26,9 +26,10 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ns16550.h> #include <asm/io.h> +#include <serial.h> /* * UART test @@ -46,299 +47,40 @@ * be overridden in the board config file */ #ifndef CONFIG_SYS_POST_UART_TABLE -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE} -#endif - -#include <asm/processor.h> -#include <serial.h> - -#if defined(CONFIG_440) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define UART0_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000300 -#define UART1_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 -#define UART2_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000500 -#define UART3_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000600 -#else -#define UART0_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000200 -#define UART1_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000300 -#endif - -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define UART2_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000600 -#endif - -#if defined(CONFIG_440GP) -#define CR0_MASK 0x3fff0000 -#define CR0_EXTCLK_ENA 0x00600000 -#define CR0_UDIV_POS 16 -#define UDIV_SUBTRACT 1 -#define UART0_SDR CPC0_CR0 -#define MFREG(a, d) d = mfdcr(a) -#define MTREG(a, d) mtdcr(a, d) -#else /* #if defined(CONFIG_440GP) */ -/* all other 440 PPC's access clock divider via sdr register */ -#define CR0_MASK 0xdfffffff -#define CR0_EXTCLK_ENA 0x00800000 -#define CR0_UDIV_POS 0 -#define UDIV_SUBTRACT 0 -#define UART0_SDR SDR0_UART0 -#define UART1_SDR SDR0_UART1 -#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define UART2_SDR SDR0_UART2 -#endif -#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRX) -#define UART3_SDR SDR0_UART3 -#endif -#define MFREG(a, d) mfsdr(a, d) -#define MTREG(a, d) mtsdr(a, d) -#endif /* #if defined(CONFIG_440GP) */ -#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ) -#define UART0_BASE 0xef600300 -#define UART1_BASE 0xef600400 -#define UCR0_MASK 0x0000007f -#define UCR1_MASK 0x00007f00 -#define UCR0_UDIV_POS 0 -#define UCR1_UDIV_POS 8 -#define UDIV_MAX 127 -#elif defined(CONFIG_405EX) -#define UART0_BASE 0xef600200 -#define UART1_BASE 0xef600300 -#define CR0_MASK 0x000000ff -#define CR0_EXTCLK_ENA 0x00800000 -#define CR0_UDIV_POS 0 -#define UDIV_SUBTRACT 0 -#define UART0_SDR SDR0_UART0 -#define UART1_SDR SDR0_UART1 -#define MFREG(a, d) mfsdr(a, d) -#define MTREG(a, d) mtsdr(a, d) -#else /* CONFIG_405GP || CONFIG_405CR */ -#define UART0_BASE 0xef600300 -#define UART1_BASE 0xef600400 -#define CR0_MASK 0x00001fff -#define CR0_EXTCLK_ENA 0x000000c0 -#define CR0_UDIV_POS 1 -#define UDIV_MAX 32 +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ + CONFIG_SYS_NS16550_COM2, CONFIG_SYS_NS16550_COM3, \ + CONFIG_SYS_NS16550_COM4 } #endif DECLARE_GLOBAL_DATA_PTR; -static void uart_post_init_common(struct NS16550 *com_port, unsigned short bdiv) -{ - volatile char val; - - out_8(&com_port->lcr, 0x80); /* set DLAB bit */ - out_8(&com_port->dll, bdiv); /* set baudrate divisor */ - out_8(&com_port->dlm, bdiv >> 8); /* set baudrate divisor */ - out_8(&com_port->lcr, 0x03); /* clear DLAB; set 8 bits, no parity */ - out_8(&com_port->fcr, 0x00); /* disable FIFO */ - out_8(&com_port->mcr, 0x10); /* enable loopback mode */ - val = in_8(&com_port->lsr); /* clear line status */ - val = in_8(&com_port->rbr); /* read receive buffer */ - out_8(&com_port->scr, 0x00); /* set scratchpad */ - out_8(&com_port->ier, 0x00); /* set interrupt enable reg */ -} - -#if defined(CONFIG_440) || defined(CONFIG_405EX) -#if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK) -static void serial_divs (int baudrate, unsigned long *pudiv, - unsigned short *pbdiv) -{ - sys_info_t sysinfo; - unsigned long div; /* total divisor udiv * bdiv */ - unsigned long umin; /* minimum udiv */ - unsigned short diff; /* smallest diff */ - unsigned long udiv; /* best udiv */ - unsigned short idiff; /* current diff */ - unsigned short ibdiv; /* current bdiv */ - unsigned long i; - unsigned long est; /* current estimate */ - - get_sys_info(&sysinfo); - - udiv = 32; /* Assume lowest possible serial clk */ - div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ - umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ - diff = 32; /* highest possible */ - - /* i is the test udiv value -- start with the largest - * possible (32) to minimize serial clock and constrain - * search to umin. - */ - for (i = 32; i > umin; i--) { - ibdiv = div / i; - est = i * ibdiv; - idiff = (est > div) ? (est-div) : (div-est); - if (idiff == 0) { - udiv = i; - break; /* can't do better */ - } else if (idiff < diff) { - udiv = i; /* best so far */ - diff = idiff; /* update lowest diff*/ - } - } - - *pudiv = udiv; - *pbdiv = div / udiv; -} -#endif - -static int uart_post_init (struct NS16550 *com_port) +static int test_ctlr (struct NS16550 *com_port, int index) { - unsigned long reg = 0; - unsigned long udiv; - unsigned short bdiv; -#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - unsigned long tmp; -#endif + int res = -1; + char test_str[] = "*** UART Test String ***\r\n"; int i; + int divisor; - for (i = 0; i < 3500; i++) { - if (in_8(&com_port->lsr) & UART_LSR_THRE) - break; - udelay (100); - } - MFREG(UART0_SDR, reg); - reg &= ~CR0_MASK; - -#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - reg |= CR0_EXTCLK_ENA; - udiv = 1; - tmp = gd->baudrate * 16; - bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp; -#else - /* For 440, the cpu clock is on divider chain A, UART on divider - * chain B ... so cpu clock is irrelevant. Get the "optimized" - * values that are subject to the 1/2 opb clock constraint - */ - serial_divs (gd->baudrate, &udiv, &bdiv); -#endif - - reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ + divisor = (get_serial_clock() + (gd->baudrate * (16 / 2))) / + (16 * gd->baudrate); + NS16550_init(com_port, divisor); /* - * Configure input clock to baudrate generator for all - * available serial ports here + * Set internal loopback mode in UART */ - MTREG(UART0_SDR, reg); -#if defined(UART1_SDR) - MTREG(UART1_SDR, reg); -#endif -#if defined(UART2_SDR) - MTREG(UART2_SDR, reg); -#endif -#if defined(UART3_SDR) - MTREG(UART3_SDR, reg); -#endif - - uart_post_init_common(com_port, bdiv); - - return 0; -} - -#else /* CONFIG_440 */ - -static int uart_post_init (struct NS16550 *com_port) -{ - unsigned long reg; - unsigned long tmp; - unsigned long clk; - unsigned long udiv; - unsigned short bdiv; - int i; - - for (i = 0; i < 3500; i++) { - if (in_8(&com_port->lsr) & UART_LSR_THRE) - break; - udelay (100); - } - -#if defined(CONFIG_405EZ) - serial_divs(gd->baudrate, &udiv, &bdiv); - clk = tmp = reg = 0; -#else -#ifdef CONFIG_405EP - reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); - clk = gd->cpu_clk; - tmp = CONFIG_SYS_BASE_BAUD * 16; - udiv = (clk + tmp / 2) / tmp; - if (udiv > UDIV_MAX) /* max. n bits for udiv */ - udiv = UDIV_MAX; - reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ - reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ - mtdcr (CPC0_UCR, reg); -#else /* CONFIG_405EP */ - reg = mfdcr(CPC0_CR0) & ~CR0_MASK; -#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - clk = CONFIG_SYS_EXT_SERIAL_CLOCK; - udiv = 1; - reg |= CR0_EXTCLK_ENA; -#else - clk = gd->cpu_clk; -#ifdef CONFIG_SYS_405_UART_ERRATA_59 - udiv = 31; /* Errata 59: stuck at 31 */ -#else - tmp = CONFIG_SYS_BASE_BAUD * 16; - udiv = (clk + tmp / 2) / tmp; - if (udiv > UDIV_MAX) /* max. n bits for udiv */ - udiv = UDIV_MAX; -#endif -#endif - reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ - mtdcr (CPC0_CR0, reg); -#endif /* CONFIG_405EP */ - tmp = gd->baudrate * udiv * 16; - bdiv = (clk + tmp / 2) / tmp; -#endif /* CONFIG_405EZ */ - - uart_post_init_common(com_port, bdiv); + out_8(&com_port->mcr, in_8(&com_port->mcr) | UART_MCR_LOOP); - return 0; -} -#endif /* CONFIG_440 */ - -static void uart_post_putc (struct NS16550 *com_port, char c) -{ - int i; - - out_8(&com_port->thr, c); /* put character out */ - - /* Wait for transfer completion */ - for (i = 0; i < 3500; i++) { - if (in_8(&com_port->lsr) & UART_LSR_THRE) - break; - udelay (100); - } -} - -static int uart_post_getc (struct NS16550 *com_port) -{ - int i; - - /* Wait for character available */ - for (i = 0; i < 3500; i++) { - if (in_8(&com_port->lsr) & UART_LSR_DR) - break; - udelay (100); - } - - return 0xff & in_8(&com_port->rbr); -} - -static int test_ctlr (struct NS16550 *com_port, int index) -{ - int res = -1; - char test_str[] = "*** UART Test String ***\r\n"; - int i; + /* Reset FIFOs */ + out_8(&com_port->fcr, UART_FCR_RXSR | UART_FCR_TXSR); + udelay(100); - uart_post_init (com_port); + /* Flush RX-FIFO */ + while (NS16550_tstc(com_port)) + NS16550_getc(com_port); for (i = 0; i < sizeof (test_str) - 1; i++) { - uart_post_putc (com_port, test_str[i]); - if (uart_post_getc (com_port) != test_str[i]) + NS16550_putc(com_port, test_str[i]); + if (NS16550_getc(com_port) != test_str[i]) goto done; } res = 0; |