diff options
| -rw-r--r-- | CHANGELOG | 6 | ||||
| -rw-r--r-- | cpu/ixp/npe/include/IxEthDB.h | 4 | ||||
| -rw-r--r-- | cpu/ppc4xx/spd_sdram.c | 2 | ||||
| -rw-r--r-- | include/configs/pcs440ep.h | 8 |
4 files changed, 13 insertions, 7 deletions
@@ -72,6 +72,12 @@ Changes since U-Boot 1.1.4: * Change mtdparts definition on trab board to match current flash map Patch by Martin Krause, 27 Oct 2005 +* Fix IxEthDB.h to compile again + Patch by Stefan Roese, 14 Jun 2006 + +* Minor cleanup for PCS440EP board + Patch by Stefan Roese, 13 Jun 2006 + * Add MCF5282 support (without preloader) relocate ichache_State to ram u-boot can run from internal flash diff --git a/cpu/ixp/npe/include/IxEthDB.h b/cpu/ixp/npe/include/IxEthDB.h index 43ee802..1189c9a 100644 --- a/cpu/ixp/npe/include/IxEthDB.h +++ b/cpu/ixp/npe/include/IxEthDB.h @@ -799,10 +799,10 @@ IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBR * @verbatim IxEthDBPortMap portMap; - /* clear all ports from port map */ + // clear all ports from port map memset(portMap, 0, sizeof (portMap)); - /* include portID in port map */ + // include portID in port map portMap[portID / 8] = 1 << (portID % 8); @endverbatim * diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c index ebd5f39..c0a6933 100644 --- a/cpu/ppc4xx/spd_sdram.c +++ b/cpu/ppc4xx/spd_sdram.c @@ -745,7 +745,7 @@ long int spd_sdram(void) { */ check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) /* * Soft-reset SDRAM controller. */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 64bbca3..50c1c4f 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -116,18 +116,17 @@ *----------------------------------------------------------------------*/ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ #undef CONFIG_DDR_ECC /* don't use ECC */ -#define SPD_EEPROM_ADDRESS {0x50, 0x51} +#define SPD_EEPROM_ADDRESS {0x50} /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR (0xa4>>1) #define CFG_I2C_EEPROM_ADDR_LEN 1 #define CFG_EEPROM_PAGE_WRITE_ENABLE #define CFG_EEPROM_PAGE_WRITE_BITS 3 @@ -211,6 +210,7 @@ CFG_CMD_ASKENV | \ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ |