diff options
100 files changed, 1219 insertions, 321 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index bb03f17..0658bc3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -616,6 +616,10 @@ Simon Kagstrom <simon.kagstrom@netinsight.net> openrd_base ARM926EJS (Kirkwood SoC) +Minkyu Kang <mk7.kang@samsung.com> + + SMDKC100 ARM CORTEX-A8 (S5PC100 SoC) + Nishant Kamat <nskamat@ti.com> omap1610h2 ARM926EJS @@ -630,17 +634,17 @@ Sergey Kubushyn <ksi@koi8.net> SONATA ARM926EJS SCHMOOGIE ARM926EJS -Sandeep Paulraj <s-paulraj@ti.com> - - davinci_dm355evm ARM926EJS - davinci_dm355leopard ARM926EJS - davinci_dm365evm ARM926EJS - davinci_dm6467evm ARM926EJS - Prakash Kumar <prakash@embedx.com> cerf250 xscale +Vipin Kumar <vipin.kumar@st.com> + + spear300 ARM926EJS (spear300 Soc) + spear310 ARM926EJS (spear310 Soc) + spear320 ARM926EJS (spear320 Soc) + spear600 ARM926EJS (spear600 Soc) + Sergey Lapin <slapin@ossfans.org> afeb9260 ARM926EJS (AT91SAM9260 SoC) @@ -673,6 +677,13 @@ Kyungmin Park <kyungmin.park@samsung.com> apollon ARM1136EJS +Sandeep Paulraj <s-paulraj@ti.com> + + davinci_dm355evm ARM926EJS + davinci_dm355leopard ARM926EJS + davinci_dm365evm ARM926EJS + davinci_dm6467evm ARM926EJS + Peter Pearse <peter.pearse@arm.com> integratorcp All current ARM supplied & supported core modules -see http://www.arm.com/products/DevTools/Hardware_Platforms.html @@ -773,10 +784,6 @@ Alex Züpke <azu@sysgo.de> lart SA1100 dnp1110 SA1110 -Minkyu Kang <mk7.kang@samsung.com> - - SMDKC100 ARM CORTEX-A8 (S5PC100 SoC) - ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/board/altera/common/AMDLV065D.c b/board/altera/common/AMDLV065D.c index 0fcf354..7a1b4d3 100644 --- a/board/altera/common/AMDLV065D.c +++ b/board/altera/common/AMDLV065D.c @@ -122,12 +122,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ addr2 = (unsigned char *) info->start[sect]; - writeb (addr, 0xaa); - writeb (addr, 0x55); - writeb (addr, 0x80); - writeb (addr, 0xaa); - writeb (addr, 0x55); - writeb (addr2, 0x30); + writeb (0xaa, addr); + writeb (0x55, addr); + writeb (0x80, addr); + writeb (0xaa, addr); + writeb (0x55, addr); + writeb (0x30, addr2); /* Now just wait for 0xff & provide some user * feedback while we wait. */ @@ -169,10 +169,10 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) return (2); } - writeb (cmd, 0xaa); - writeb (cmd, 0x55); - writeb (cmd, 0xa0); - writeb (dst, b); + writeb (0xaa, cmd); + writeb (0x55, cmd); + writeb (0xa0, cmd); + writeb (b, dst); /* Verify write */ start = get_timer (0); diff --git a/board/altera/common/epled.c b/board/altera/common/epled.c index e5e7705..d019735 100644 --- a/board/altera/common/epled.c +++ b/board/altera/common/epled.c @@ -39,7 +39,7 @@ void __led_init (led_id_t mask, int state) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_set (led_id_t mask, int state) @@ -50,7 +50,7 @@ void __led_set (led_id_t mask, int state) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_toggle (led_id_t mask) @@ -58,5 +58,5 @@ void __led_toggle (led_id_t mask) nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; val ^= mask; - writel (&pio->data, val); + writel (val, &pio->data); } diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 518944e..9bb56b5 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -132,9 +132,7 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_SMC91111 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); #endif -#ifdef CONFIG_PCI rc += pci_eth_init(bis); -#endif return rc; } #endif diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c index 0fcf354..72b0a9f 100644 --- a/board/psyent/common/AMDLV065D.c +++ b/board/psyent/common/AMDLV065D.c @@ -122,12 +122,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ addr2 = (unsigned char *) info->start[sect]; - writeb (addr, 0xaa); - writeb (addr, 0x55); - writeb (addr, 0x80); - writeb (addr, 0xaa); - writeb (addr, 0x55); - writeb (addr2, 0x30); + writeb (0xaa, addr); + writeb (0x55, addr); + writeb (0x80, addr); + writeb (0xaa, addr); + writeb (0x55, addr); + writeb (0x30, addr2); /* Now just wait for 0xff & provide some user * feedback while we wait. */ @@ -169,9 +169,9 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) return (2); } - writeb (cmd, 0xaa); - writeb (cmd, 0x55); - writeb (cmd, 0xa0); + writeb (0xaa, cmd); + writeb (0x55, cmd); + writeb (0xa0, cmd); writeb (dst, b); /* Verify write */ diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c index e5e7705..d019735 100644 --- a/board/psyent/pk1c20/led.c +++ b/board/psyent/pk1c20/led.c @@ -39,7 +39,7 @@ void __led_init (led_id_t mask, int state) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_set (led_id_t mask, int state) @@ -50,7 +50,7 @@ void __led_set (led_id_t mask, int state) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_toggle (led_id_t mask) @@ -58,5 +58,5 @@ void __led_toggle (led_id_t mask) nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; val ^= mask; - writel (&pio->data, val); + writel (val, &pio->data); } diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 15a1a27..fb466c6 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -23,10 +23,40 @@ */ #include <common.h> +#include <asm/io.h> +#include <asm/arch/smc.h> +#include <asm/arch/gpio.h> +#include <netdev.h> + DECLARE_GLOBAL_DATA_PTR; +/* + * Miscellaneous platform dependent initialisations + */ +static void smc9115_pre_init(void) +{ + u32 smc_bw_conf, smc_bc_conf; + + struct s5pc100_gpio *const gpio = + (struct s5pc100_gpio *)S5PC100_GPIO_BASE; + + /* gpio configuration GPK0CON */ + gpio_cfg_pin(&gpio->gpio_k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + + /* Ethernet needs bus width of 16 bits */ + smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); + smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe) + | SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4) + | SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0); + + /* Select and configure the SROMC bank */ + s5pc1xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); +} + int board_init(void) { + smc9115_pre_init(); + gd->bd->bi_arch_number = MACH_TYPE_SMDKC100; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; @@ -49,3 +79,12 @@ int checkboard(void) return 0; } #endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c index 2c0014f..befa0cd 100644 --- a/cpu/arm1176/cpu.c +++ b/cpu/arm1176/cpu.c @@ -33,7 +33,9 @@ #include <common.h> #include <command.h> +#ifdef CONFIG_S3C64XX #include <asm/arch/s3c6400.h> +#endif #include <asm/system.h> static void cache_flush (void); diff --git a/cpu/arm1176/start.S b/cpu/arm1176/start.S index 68a356d..e2b6c9b 100644 --- a/cpu/arm1176/start.S +++ b/cpu/arm1176/start.S @@ -35,7 +35,9 @@ #ifdef CONFIG_ENABLE_MMU #include <asm/proc/domain.h> #endif +#ifdef CONFIG_S3C64XX #include <asm/arch/s3c6400.h> +#endif #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE @@ -190,10 +192,12 @@ mmu_disable: #endif mmu_disable_phys: +#ifdef CONFIG_S3C64XX /* Peri port setup */ ldr r0, =0x70000000 orr r0, r0, #0x13 mcr p15,0,r0,c15,c2,4 @ 256M (0x70000000 - 0x7fffffff) +#endif /* * Go setup Memory and board specific bits prior to relocation. diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c index 31304b7..4a0ce4d 100644 --- a/cpu/arm920t/ep93xx/timer.c +++ b/cpu/arm920t/ep93xx/timer.c @@ -1,8 +1,7 @@ /* * Cirrus Logic EP93xx timer support. * - * Copyright (C) 2009, 2010 - * Matthias Kaehlcke <matthias@kaehlcke.net> + * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net> * * Copyright (C) 2004, 2005 * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com> @@ -42,17 +41,9 @@ static struct ep93xx_timer { unsigned long long ticks; - unsigned long last_update; + unsigned long last_read; } timer; -static inline unsigned long clk_to_systicks(unsigned long long clk_ticks) -{ - unsigned long long sys_ticks = (clk_ticks * CONFIG_SYS_HZ); - do_div(sys_ticks, TIMER_FREQ); - - return (unsigned long)sys_ticks; -} - static inline unsigned long long usecs_to_ticks(unsigned long usecs) { unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ; @@ -61,11 +52,18 @@ static inline unsigned long long usecs_to_ticks(unsigned long usecs) return ticks; } -static inline unsigned long read_timer(void) +static inline void read_timer(void) { - struct timer_regs *timer = (struct timer_regs *)TIMER_BASE; + struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE; + const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value); + + if (now >= timer.last_read) + timer.ticks += now - timer.last_read; + else + /* an overflow occurred */ + timer.ticks += TIMER_MAX_VAL - timer.last_read + now; - return TIMER_MAX_VAL - readl(&timer->timer3.value); + timer.last_read = now; } /* @@ -73,17 +71,14 @@ static inline unsigned long read_timer(void) */ unsigned long long get_ticks(void) { - const unsigned long now = read_timer(); + unsigned long long sys_ticks; - if (now >= timer.last_update) - timer.ticks += now - timer.last_update; - else - /* an overflow occurred */ - timer.ticks += TIMER_MAX_VAL - timer.last_update + now; + read_timer(); - timer.last_update = now; + sys_ticks = timer.ticks * CONFIG_SYS_HZ; + do_div(sys_ticks, TIMER_FREQ); - return clk_to_systicks(timer.ticks); + return sys_ticks; } unsigned long get_timer_masked(void) @@ -98,7 +93,7 @@ unsigned long get_timer(unsigned long base) void reset_timer_masked(void) { - timer.last_update = read_timer(); + read_timer(); timer.ticks = 0; } @@ -109,28 +104,29 @@ void reset_timer(void) void __udelay(unsigned long usec) { - /* read the timer and update timer.ticks */ - get_ticks(); + unsigned long long target; + + read_timer(); - const unsigned long long target = timer.ticks + usecs_to_ticks(usec); + target = timer.ticks + usecs_to_ticks(usec); while (timer.ticks < target) - get_ticks(); + read_timer(); } int timer_init(void) { - struct timer_regs *timer = (struct timer_regs *)TIMER_BASE; + struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE; - /* use timer 3 with 508KHz and free running */ - writel(TIMER_CLKSEL, &timer->timer3.control); + /* use timer 3 with 508KHz and free running, not enabled now */ + writel(TIMER_CLKSEL, &timer_regs->timer3.control); - /* set initial timer value 3 */ - writel(TIMER_MAX_VAL, &timer->timer3.load); + /* set initial timer value */ + writel(TIMER_MAX_VAL, &timer_regs->timer3.load); /* Enable the timer */ writel(TIMER_ENABLE | TIMER_CLKSEL, - &timer->timer3.control); + &timer_regs->timer3.control); reset_timer_masked(); diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c index b06d760..ecf91f5 100644 --- a/cpu/arm926ejs/at91/clock.c +++ b/cpu/arm926ejs/at91/clock.c @@ -203,7 +203,8 @@ int at91_clock_init(unsigned long main_clock) if (mckr & AT91_PMC_MCKR_MDIV_MASK) freq /= 2; /* processor clock division */ #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) - mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == AT91SAM9_PMC_MDIV_3 + mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == + (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4) ? freq / 3 : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #else diff --git a/cpu/arm926ejs/nomadik/timer.c b/cpu/arm926ejs/nomadik/timer.c index 047b9e3..1d98ef3 100644 --- a/cpu/arm926ejs/nomadik/timer.c +++ b/cpu/arm926ejs/nomadik/timer.c @@ -34,8 +34,8 @@ #define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) #define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) -/* macro to read the 32 bit timer: since it decrements, we invert read value */ -#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0))) +/* macro to read the decrementing 32 bit timer as an increasing count */ +#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0))) /* Configure a free-running, auto-wrap counter with no prescaler */ int timer_init(void) @@ -49,7 +49,16 @@ int timer_init(void) /* Restart counting from 0 */ void reset_timer(void) { - writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); /* Immediate effect */ + ulong val; + writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); + /* + * The load-register isn't really immediate: it changes on clock + * edges, so we must wait for our newly-written value to appear. + * Since we might miss reading 0, wait for any change in value. + */ + val = READ_TIMER(); + while (READ_TIMER() == val) + ; } /* Return how many HZ passed since "base" */ diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile index 4f922e6..01c93fe 100644 --- a/cpu/arm_cortexa8/s5pc1xx/Makefile +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile @@ -33,6 +33,8 @@ SOBJS += reset.o COBJS += clock.o COBJS += cpu_info.o +COBJS += gpio.o +COBJS += sromc.o COBJS += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm_cortexa8/s5pc1xx/clock.c b/cpu/arm_cortexa8/s5pc1xx/clock.c index a9e78dd..19619f9 100644 --- a/cpu/arm_cortexa8/s5pc1xx/clock.c +++ b/cpu/arm_cortexa8/s5pc1xx/clock.c @@ -25,12 +25,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> - -#define APLL 0 -#define MPLL 1 -#define EPLL 2 -#define HPLL 3 -#define VPLL 4 +#include <asm/arch/clk.h> #define CLK_M 0 #define CLK_D 1 diff --git a/cpu/arm_cortexa8/s5pc1xx/gpio.c b/cpu/arm_cortexa8/s5pc1xx/gpio.c new file mode 100644 index 0000000..a97244b --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/gpio.c @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> + +#define CON_MASK(x) (0xf << ((x) << 2)) +#define CON_SFR(x, v) ((v) << ((x) << 2)) + +#define DAT_MASK(x) (0x1 << (x)) +#define DAT_SET(x) (0x1 << (x)) + +#define PULL_MASK(x) (0x3 << ((x) << 1)) +#define PULL_MODE(x, v) ((v) << ((x) << 1)) + +#define DRV_MASK(x) (0x3 << ((x) << 1)) +#define DRV_SET(x, m) ((m) << ((x) << 1)) +#define RATE_MASK(x) (0x1 << (x + 16)) +#define RATE_SET(x) (0x1 << (x + 16)) + +void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg) +{ + unsigned int value; + + value = readl(&bank->con); + value &= ~CON_MASK(gpio); + value |= CON_SFR(gpio, cfg); + writel(value, &bank->con); +} + +void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en) +{ + unsigned int value; + + gpio_cfg_pin(bank, gpio, GPIO_OUTPUT); + + value = readl(&bank->dat); + value &= ~DAT_MASK(gpio); + if (en) + value |= DAT_SET(gpio); + writel(value, &bank->dat); +} + +void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio) +{ + gpio_cfg_pin(bank, gpio, GPIO_INPUT); +} + +void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en) +{ + unsigned int value; + + value = readl(&bank->dat); + value &= ~DAT_MASK(gpio); + if (en) + value |= DAT_SET(gpio); + writel(value, &bank->dat); +} + +unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio) +{ + unsigned int value; + + value = readl(&bank->dat); + return !!(value & DAT_MASK(gpio)); +} + +void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->pull); + value &= ~PULL_MASK(gpio); + + switch (mode) { + case GPIO_PULL_DOWN: + case GPIO_PULL_UP: + value |= PULL_MODE(gpio, mode); + break; + default: + return; + } + + writel(value, &bank->pull); +} + +void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->drv); + value &= ~DRV_MASK(gpio); + + switch (mode) { + case GPIO_DRV_1X: + case GPIO_DRV_2X: + case GPIO_DRV_3X: + case GPIO_DRV_4X: + value |= DRV_SET(gpio, mode); + break; + default: + return; + } + + writel(value, &bank->drv); +} + +void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->drv); + value &= ~RATE_MASK(gpio); + + switch (mode) { + case GPIO_DRV_FAST: + case GPIO_DRV_SLOW: + value |= RATE_SET(gpio); + break; + default: + return; + } + + writel(value, &bank->drv); +} diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c b/cpu/arm_cortexa8/s5pc1xx/sromc.c new file mode 100644 index 0000000..380be81 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * Naveen Krishna Ch <ch.naveen@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/smc.h> + +/* + * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the + * band width control and bank control registers + * srom_bank - SROM Bank 0 to 5 + * smc_bw_conf - SMC Band witdh reg configuration value + * smc_bc_conf - SMC Bank Control reg configuration value + */ +void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf) +{ + u32 tmp; + struct s5pc1xx_smc *srom; + + if (cpu_is_s5pc100()) + srom = (struct s5pc1xx_smc *)S5PC100_SROMC_BASE; + else + srom = (struct s5pc1xx_smc *)S5PC110_SROMC_BASE; + + /* Configure SMC_BW register to handle proper SROMC bank */ + tmp = srom->bw; + tmp &= ~(0xF << (srom_bank * 4)); + tmp |= smc_bw_conf; + srom->bw = tmp; + + /* Configure SMC_BC register */ + srom->bc[srom_bank] = smc_bc_conf; +} diff --git a/cpu/nios2/Makefile b/cpu/nios2/Makefile index 75f30b4..3dfaa83 100644 --- a/cpu/nios2/Makefile +++ b/cpu/nios2/Makefile @@ -27,7 +27,7 @@ LIB = $(obj)lib$(CPU).a START = start.o SOBJS = exceptions.o -COBJS = cpu.o interrupts.o serial.o sysid.o traps.o epcs.o +COBJS = cpu.o interrupts.o sysid.o traps.o epcs.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/nios2/epcs.c b/cpu/nios2/epcs.c index 483b249..ab7d746 100644 --- a/cpu/nios2/epcs.c +++ b/cpu/nios2/epcs.c @@ -85,7 +85,7 @@ static int epcs_cs (int assert) if (assert) { tmp = readl (&epcs->control); - writel (&epcs->control, tmp | NIOS_SPI_SSO); + writel (tmp | NIOS_SPI_SSO, &epcs->control); } else { /* Let all bits shift out */ start = get_timer (0); @@ -93,7 +93,7 @@ static int epcs_cs (int assert) if (get_timer (start) > EPCS_TIMEOUT) return (-1); tmp = readl (&epcs->control); - writel (&epcs->control, tmp & ~NIOS_SPI_SSO); + writel (tmp & ~NIOS_SPI_SSO, &epcs->control); } return (0); } @@ -106,7 +106,7 @@ static int epcs_tx (unsigned char c) while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0) if (get_timer (start) > EPCS_TIMEOUT) return (-1); - writel (&epcs->txdata, c); + writel (c, &epcs->txdata); return (0); } @@ -207,6 +207,8 @@ static void epcs_status_wr (unsigned char status) static struct epcs_devinfo_t devinfo[] = { { "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c }, { "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c }, + { "EPCS16", 0x14, 21, 32, 16, 8, 0x1c }, + { "EPCS64", 0x16, 23,128, 16, 8, 0x1c }, { 0, 0, 0, 0, 0, 0 } }; @@ -501,15 +503,17 @@ void do_epcs_info (struct epcs_devinfo_t *dev, int argc, char *argv[]) } /* Sector info */ - for (i=0; i<dev->num_sects; i++) { + for (i=0; (i < dev->num_sects) && (argc > 1); i++) { erased = epcs_sect_erased (i, &tmp, dev); - printf (" %d: %06x ", + if ((i & 0x03) == 0) printf ("\n"); + printf ("%4d: %07x ", i, i*(1<<dev->sz_sect) ); if (erased) - printf ("erased\n"); + printf ("E "); else - printf ("data @ 0x%06x\n", tmp); + printf (" "); } + printf ("\n"); return; } diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c index 1c3566e..b552db4 100644 --- a/cpu/nios2/interrupts.c +++ b/cpu/nios2/interrupts.c @@ -56,7 +56,40 @@ volatile ulong timestamp = 0; void reset_timer (void) { + nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE; + + /* From Embedded Peripherals Handbook: + * + * "When the hardware is configured with Writeable period + * disabled, writing to one of the period_n registers causes + * the counter to reset to the fixed Timeout Period specified + * at system generation time." + * + * Here we force a reload to prevent early timeouts from + * get_timer() when the interrupt period is greater than + * than 1 msec. + * + * Simply write to periodl with its own value to force an + * internal counter reload, THEN reset the timestamp. + */ + writel (readl (&tmr->periodl), &tmr->periodl); timestamp = 0; + + /* From Embedded Peripherals Handbook: + * + * "Writing to one of the period_n registers stops the internal + * counter, except when the hardware is configured with Start/Stop + * control bits off. If Start/Stop control bits is off, writing + * either register does not stop the counter." + * + * In order to accomodate either configuration, the control + * register is re-written. If the counter is stopped, it will + * be restarted. If it is running, the write is essentially + * a nop. + */ + writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START, + &tmr->control); + } ulong get_timer (ulong base) @@ -81,7 +114,7 @@ void tmr_isr (void *arg) /* Interrupt is cleared by writing anything to the * status register. */ - writel (&tmr->status, 0); + writel (0, &tmr->status); timestamp += CONFIG_SYS_NIOS_TMRMS; #ifdef CONFIG_STATUS_LED status_led_tick(timestamp); @@ -92,16 +125,16 @@ static void tmr_init (void) { nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE; - writel (&tmr->status, 0); - writel (&tmr->control, 0); - writel (&tmr->control, NIOS_TIMER_STOP); + writel (0, &tmr->status); + writel (0, &tmr->control); + writel (NIOS_TIMER_STOP, &tmr->control); #if defined(CONFIG_SYS_NIOS_TMRCNT) - writel (&tmr->periodl, CONFIG_SYS_NIOS_TMRCNT & 0xffff); - writel (&tmr->periodh, (CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff); + writel (CONFIG_SYS_NIOS_TMRCNT & 0xffff, &tmr->periodl); + writel ((CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff, &tmr->periodh); #endif - writel (&tmr->control, NIOS_TIMER_ITO | NIOS_TIMER_CONT | - NIOS_TIMER_START ); + writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START, + &tmr->control); irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ, tmr_isr, (void *)tmr); } diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 365f966..88d53fb 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -52,7 +52,6 @@ COBJS += denali_data_eye.o COBJS += denali_spd_ddr2.o COBJS += ecc.o COBJS += fdt.o -COBJS += i2c.o COBJS += interrupts.o COBJS += iop480_uart.o ifdef CONFIG_CMD_REGINFO diff --git a/doc/README.s5pc1xx b/doc/README.s5pc1xx index 5a0fe33..ab1f024 100644 --- a/doc/README.s5pc1xx +++ b/doc/README.s5pc1xx @@ -41,7 +41,23 @@ To check SoC: printf("cpu is s5pc110\n"); gpio - not supported yet. + + struct s5pc100_gpio *gpio = (struct s5pc100_gpio*)S5PC100_GPIO_BASE; + + /* GPA[0] pin set to irq */ + gpio_cfg_pin(&gpio->gpio_a, 0, GPIO_IRQ); + + /* GPA[0] pin set to input */ + gpio_direction_input(&gpio->gpio_a, 0); + + /* GPA[0] pin set to output/high */ + gpio_direction_output(&gpio->gpio_a, 0, 1); + + /* GPA[0] value set to low */ + gpio_set_value(&gpio->gpio_a, 0, 0); + + /* get GPA[0] value */ + value = gpio_get_value(&gpio->gpio_a, 0); Links ===== diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 29bda85..d2c2515 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o +COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o diff --git a/cpu/ppc4xx/i2c.c b/drivers/i2c/ppc4xx_i2c.c index 9b86187..9b86187 100644 --- a/cpu/ppc4xx/i2c.c +++ b/drivers/i2c/ppc4xx_i2c.c diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 3c77a7c..d2b4820 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,11 +25,14 @@ include $(TOPDIR)/config.mk LIB := $(obj)libserial.a +COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o +COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o COBJS-$(CONFIG_AT91RM9200_USART) += at91rm9200_usart.o COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o COBJS-$(CONFIG_MCFUART) += mcfuart.o COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o +COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o COBJS-$(CONFIG_SYS_NS16550) += ns16550.o COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o COBJS-$(CONFIG_S3C64XX) += s3c64xx.o diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c new file mode 100644 index 0000000..fb28aa9 --- /dev/null +++ b/drivers/serial/altera_jtag_uart.c @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/io.h> +#include <nios2-io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/*------------------------------------------------------------------ + * JTAG acts as the serial port + *-----------------------------------------------------------------*/ +static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE; + +void serial_setbrg( void ){ return; } +int serial_init( void ) { return(0);} + +void serial_putc (char c) +{ + while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0) + WATCHDOG_RESET (); + writel ((unsigned char)c, &jtag->data); +} + +void serial_puts (const char *s) +{ + while (*s != 0) + serial_putc (*s++); +} + +int serial_tstc (void) +{ + return ( readl (&jtag->control) & NIOS_JTAG_RRDY); +} + +int serial_getc (void) +{ + int c; + unsigned val; + + while (1) { + WATCHDOG_RESET (); + val = readl (&jtag->data); + if (val & NIOS_JTAG_RVALID) + break; + } + c = val & 0x0ff; + return (c); +} diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c new file mode 100644 index 0000000..045f119 --- /dev/null +++ b/drivers/serial/altera_uart.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#include <watchdog.h> +#include <asm/io.h> +#include <nios2-io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/*------------------------------------------------------------------ + * UART the serial port + *-----------------------------------------------------------------*/ + +static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE; + +#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) + +/* Everything's already setup for fixed-baud PTF + * assignment + */ +void serial_setbrg (void){ return; } +int serial_init (void) { return (0);} + +#else + +void serial_setbrg (void) +{ + unsigned div; + + div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1; + writel (div, &uart->divisor); + return; +} + +int serial_init (void) +{ + serial_setbrg (); + return (0); +} + +#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ + +/*----------------------------------------------------------------------- + * UART CONSOLE + *---------------------------------------------------------------------*/ +void serial_putc (char c) +{ + if (c == '\n') + serial_putc ('\r'); + while ((readl (&uart->status) & NIOS_UART_TRDY) == 0) + WATCHDOG_RESET (); + writel ((unsigned char)c, &uart->txdata); +} + +void serial_puts (const char *s) +{ + while (*s != 0) { + serial_putc (*s++); + } +} + +int serial_tstc (void) +{ + return (readl (&uart->status) & NIOS_UART_RRDY); +} + +int serial_getc (void) +{ + while (serial_tstc () == 0) + WATCHDOG_RESET (); + return (readl (&uart->rxdata) & 0x00ff ); +} diff --git a/cpu/nios2/serial.c b/drivers/serial/opencores_yanu.c index 6c835af..f18f7f4 100644 --- a/cpu/nios2/serial.c +++ b/drivers/serial/opencores_yanu.c @@ -1,8 +1,4 @@ /* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * YANU Support: * Copyright 2010, Renato Andreola <renato.andreola@imagos.it> * * See file CREDITS for list of people who contributed to this @@ -24,61 +20,13 @@ * MA 02111-1307 USA */ - #include <common.h> #include <watchdog.h> #include <asm/io.h> -#include <nios2-io.h> #include <nios2-yanu.h> DECLARE_GLOBAL_DATA_PTR; -/*------------------------------------------------------------------ - * JTAG acts as the serial port - *-----------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) - -static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE; - -void serial_setbrg( void ){ return; } -int serial_init( void ) { return(0);} - -void serial_putc (char c) -{ - unsigned val; - - while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0) - WATCHDOG_RESET (); - writel (&jtag->data, (unsigned char)c); -} - -void serial_puts (const char *s) -{ - while (*s != 0) - serial_putc (*s++); -} - -int serial_tstc (void) -{ - return ( readl (&jtag->control) & NIOS_JTAG_RRDY); -} - -int serial_getc (void) -{ - int c; - unsigned val; - - while (1) { - WATCHDOG_RESET (); - val = readl (&jtag->data); - if (val & NIOS_JTAG_RVALID) - break; - } - c = val & 0x0ff; - return (c); -} - -#elif defined(CONFIG_CONSOLE_YANU) /*-----------------------------------------------------------------*/ /* YANU Imagos serial port */ /*-----------------------------------------------------------------*/ @@ -113,7 +61,7 @@ void serial_setbrg (void) ((unsigned)CONFIG_SYS_CLK_FREQ >> k); baud = best_m + best_n * YANU_BAUDE; - writel(&uart->baud, baud); + writel(baud, &uart->baud); return; } @@ -144,7 +92,7 @@ void serial_setbrg (void) ((unsigned)CONFIG_SYS_CLK_FREQ >> k); baud = best_m + best_n * YANU_BAUDE; - writel(&uart->baud, baud); + writel(baud, &uart->baud); return; } @@ -165,7 +113,7 @@ int serial_init (void) YANU_ACTION_RPE | YANU_ACTION_RFE | YANU_ACTION_RFIFO_CLEAR | YANU_ACTION_TFIFO_CLEAR; - writel(&uart->action, action); + writel(action, &uart->action); /* control register cleanup */ /* no interrupts enabled */ @@ -179,7 +127,7 @@ int serial_init (void) control |= YANU_CONTROL_RDYDLY * YANU_RXFIFO_DLY; control |= YANU_CONTROL_TXTHR * YANU_TXFIFO_THR; - writel(&uart->control, control); + writel(control, &uart->control); /* to set baud rate */ serial_setbrg(); @@ -208,7 +156,7 @@ void serial_putc (char c) WATCHDOG_RESET (); } - writel(&uart->data, (unsigned char)c); + writel((unsigned char)c, &uart->data); } void serial_puts (const char *s) @@ -234,76 +182,7 @@ int serial_getc (void) WATCHDOG_RESET (); /* first we pull the char */ - writel(&uart->action, YANU_ACTION_RFIFO_PULL); + writel(YANU_ACTION_RFIFO_PULL, &uart->action); return(readl(&uart->data) & YANU_DATA_CHAR_MASK); } - -#else /*CONFIG_CONSOLE_YANU*/ - -/*------------------------------------------------------------------ - * UART the serial port - *-----------------------------------------------------------------*/ - -static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE; - -#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) - -/* Everything's already setup for fixed-baud PTF - * assignment - */ -void serial_setbrg (void){ return; } -int serial_init (void) { return (0);} - -#else - -void serial_setbrg (void) -{ - unsigned div; - - div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1; - writel (&uart->divisor,div); - return; -} - -int serial_init (void) -{ - serial_setbrg (); - return (0); -} - -#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ - - -/*----------------------------------------------------------------------- - * UART CONSOLE - *---------------------------------------------------------------------*/ -void serial_putc (char c) -{ - if (c == '\n') - serial_putc ('\r'); - while ((readl (&uart->status) & NIOS_UART_TRDY) == 0) - WATCHDOG_RESET (); - writel (&uart->txdata,(unsigned char)c); -} - -void serial_puts (const char *s) -{ - while (*s != 0) { - serial_putc (*s++); - } -} - -int serial_tstc (void) -{ - return (readl (&uart->status) & NIOS_UART_RRDY); -} - -int serial_getc (void) -{ - while (serial_tstc () == 0) - WATCHDOG_RESET (); - return (readl (&uart->rxdata) & 0x00ff ); -} - -#endif /* CONFIG_JTAG_CONSOLE */ diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 29f3ba1..b2e03bc 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -25,11 +25,6 @@ #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) -#ifndef CONFIG_AT91_LEGACY -#define CONFIG_AT91_LEGACY -#warning Please update to use C structur SoC access ! -#endif - #include <asm/arch/hardware.h> #include <asm/arch/io.h> #include <asm/arch/at91_pmc.h> @@ -37,22 +32,23 @@ int usb_cpu_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE; #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ defined(CONFIG_AT91SAM9261) /* Enable PLLB */ - at91_sys_write(AT91_CKGR_PLLBR, get_pllb_init()); - while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) + writel(get_pllb_init(), &pmc->pllbr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) ; #endif /* Enable USB host clock. */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP); + writel(1 << AT91_ID_UHP, &pmc->pcer); #ifdef CONFIG_AT91SAM9261 - at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP | AT91_PMC_HCK0); + writel(AT91_PMC_UHP | AT91_PMC_HCK0, &pmc->scer); #else - at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP); + writel(AT91_PMC_UHP, &pmc->scer); #endif return 0; @@ -60,19 +56,21 @@ int usb_cpu_init(void) int usb_cpu_stop(void) { + at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE; + /* Disable USB host clock. */ - at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP); + writel(1 << AT91_ID_UHP, &pmc->pcdr); #ifdef CONFIG_AT91SAM9261 - at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_HCK0); + writel(AT91_PMC_UHP | AT91_PMC_HCK0, &pmc->scdr); #else - at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP); + writel(AT91_PMC_UHP, &pmc->scdr); #endif #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) /* Disable PLLB */ - at91_sys_write(AT91_CKGR_PLLBR, 0); - while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != 0) + writel(0, &pmc->pllbr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) ; #endif diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index 5bb8b77..25afae7 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -42,11 +42,10 @@ static int at91_wdt_settimeout(unsigned int timeout) { unsigned int reg; - unsigned int mr; + at91_wdt_t *wd = (at91_wdt_t *) AT91_WDT_BASE; /* Check if disabled */ - mr = at91_sys_read(AT91_WDT_MR); - if (mr & AT91_WDT_WDDIS) { + if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) { printf("sorry, watchdog is disabled\n"); return -1; } @@ -57,19 +56,21 @@ static int at91_wdt_settimeout(unsigned int timeout) * Since WDV is a 12-bit counter, the maximum period is * 4096 / 256 = 16 seconds. */ - reg = AT91_WDT_WDRSTEN /* causes watchdog reset */ - /* | AT91_WDT_WDRPROC causes processor reset only */ - | AT91_WDT_WDDBGHLT /* disabled in debug mode */ - | AT91_WDT_WDD /* restart at any time */ - | (timeout & AT91_WDT_WDV); /* timer value */ - at91_sys_write(AT91_WDT_MR, reg); + + reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ + | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */ + | AT91_WDT_MR_WDD(0xfff) /* restart at any time */ + | AT91_WDT_MR_WDV(timeout); /* timer value */ + + writel(reg, &wd->mr); return 0; } void hw_watchdog_reset(void) { - at91_sys_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT); + at91_wdt_t *wd = (at91_wdt_t *) AT91_WDT_BASE; + writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr); } void hw_watchdog_init(void) diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index 680fe33..5b1a85d 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -108,11 +108,12 @@ typedef struct at91_pmc { #define AT91_PMC_IXR_PCKRDY3 0x00000800 #ifdef CONFIG_AT91_LEGACY - #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ +#endif + #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ @@ -128,27 +129,34 @@ typedef struct at91_pmc { #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ +#endif + #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ +#ifdef CONFIG_AT91_LEGACY #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ +#endif #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ - +#ifdef CONFIG_AT91_LEGACY #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ +#endif #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ - +#ifdef CONFIG_AT91_LEGACY #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ +#endif #define AT91_PMC_DIV (0xff << 0) /* Divider */ #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ @@ -160,7 +168,9 @@ typedef struct at91_pmc { #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ #define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ +#endif #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ #define AT91_PMC_CSS_SLOW (0 << 0) #define AT91_PMC_CSS_MAIN (1 << 0) @@ -188,11 +198,13 @@ typedef struct at91_pmc { #define AT91_PMC_PDIV_1 (0 << 12) #define AT91_PMC_PDIV_2 (1 << 12) +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ +#endif #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ @@ -203,12 +215,13 @@ typedef struct at91_pmc { #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ #define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ +#endif #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ - +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ - #endif /* CONFIG_AT91_LEGACY */ #endif diff --git a/include/asm-arm/arch-s5pc1xx/clk.h b/include/asm-arm/arch-s5pc1xx/clk.h index f1aa44f..3e59abe 100644 --- a/include/asm-arm/arch-s5pc1xx/clk.h +++ b/include/asm-arm/arch-s5pc1xx/clk.h @@ -23,6 +23,12 @@ #ifndef __ASM_ARM_ARCH_CLK_H_ #define __ASM_ARM_ARCH_CLK_H_ +#define APLL 0 +#define MPLL 1 +#define EPLL 2 +#define HPLL 3 +#define VPLL 4 + void s5pc1xx_clock_init(void); extern unsigned long (*get_pll_clk)(int pllreg); diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h index afbc7ea..8e4bb86 100644 --- a/include/asm-arm/arch-s5pc1xx/gpio.h +++ b/include/asm-arm/arch-s5pc1xx/gpio.h @@ -124,6 +124,35 @@ struct s5pc110_gpio { struct s5pc1xx_gpio_bank gpio_h2; struct s5pc1xx_gpio_bank gpio_h3; }; + +/* functions */ +void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg); +void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en); +void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio); +void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en); +unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio); +void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); +void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); +void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); #endif +/* Pin configurations */ +#define GPIO_INPUT 0x0 +#define GPIO_OUTPUT 0x1 +#define GPIO_IRQ 0xf +#define GPIO_FUNC(x) (x) + +/* Pull mode */ +#define GPIO_PULL_NONE 0x0 +#define GPIO_PULL_DOWN 0x1 +#define GPIO_PULL_UP 0x2 + +/* Drive Strength level */ +#define GPIO_DRV_1X 0x0 +#define GPIO_DRV_2X 0x1 +#define GPIO_DRV_3X 0x2 +#define GPIO_DRV_4X 0x3 +#define GPIO_DRV_FAST 0x0 +#define GPIO_DRV_SLOW 0x1 + #endif diff --git a/include/asm-arm/arch-s5pc1xx/smc.h b/include/asm-arm/arch-s5pc1xx/smc.h new file mode 100644 index 0000000..88f4ffe --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/smc.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Naveen Krishna Ch <ch.naveen@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: This file contains the register description for Memory subsystem + * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. + * + * Only SROMC is defined as of now + */ + +#ifndef __ASM_ARCH_SMC_H_ +#define __ASM_ARCH_SMC_H_ + +#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) +#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ + /* 1-> Byte base address*/ +#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) +#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) + +#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ +#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ +#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ +#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ +#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ +#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ +#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ + +#ifndef __ASSEMBLY__ +struct s5pc1xx_smc { + unsigned int bw; + unsigned int bc[6]; +}; +#endif /* __ASSEMBLY__ */ + +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ +void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf); + +#endif /* __ASM_ARCH_SMC_H_ */ diff --git a/include/asm-nios2/bitops.h b/include/asm-nios2/bitops.h index 5776bda..cf48ff7 100644 --- a/include/asm-nios2/bitops.h +++ b/include/asm-nios2/bitops.h @@ -24,15 +24,9 @@ #ifndef __ASM_NIOS2_BITOPS_H_ #define __ASM_NIOS2_BITOPS_H_ - -extern void set_bit(int nr, volatile void * a); -extern void clear_bit(int nr, volatile void * a); -extern int test_and_clear_bit(int nr, volatile void * a); -extern void change_bit(unsigned long nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void * a); -extern int test_and_change_bit(int nr, volatile void * addr); -extern int test_bit(int nr, volatile void * a); -extern int ffs(int i); -#define PLATFORM_FFS +/* copied from linux-2.6/include/asm-generic/bitops */ +#include <asm/bitops/atomic.h> +#include <asm/bitops/non-atomic.h> +#include <asm/bitops/ffs.h> #endif /* __ASM_NIOS2_BITOPS_H */ diff --git a/include/asm-nios2/bitops/atomic.h b/include/asm-nios2/bitops/atomic.h new file mode 100644 index 0000000..c894646 --- /dev/null +++ b/include/asm-nios2/bitops/atomic.h @@ -0,0 +1,189 @@ +#ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_ +#define _ASM_GENERIC_BITOPS_ATOMIC_H_ + +#include <asm/types.h> +#include <asm/system.h> + +#ifdef CONFIG_SMP +#include <asm/spinlock.h> +#include <asm/cache.h> /* we use L1_CACHE_BYTES */ + +/* Use an array of spinlocks for our atomic_ts. + * Hash function to index into a different SPINLOCK. + * Since "a" is usually an address, use one spinlock per cacheline. + */ +# define ATOMIC_HASH_SIZE 4 +# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ])) + +extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; + +/* Can't use raw_spin_lock_irq because of #include problems, so + * this is the substitute */ +#define _atomic_spin_lock_irqsave(l,f) do { \ + raw_spinlock_t *s = ATOMIC_HASH(l); \ + local_irq_save(f); \ + __raw_spin_lock(s); \ +} while(0) + +#define _atomic_spin_unlock_irqrestore(l,f) do { \ + raw_spinlock_t *s = ATOMIC_HASH(l); \ + __raw_spin_unlock(s); \ + local_irq_restore(f); \ +} while(0) + + +#else +# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0) +# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0) +#endif + +/* + * NMI events can occur at any time, including when interrupts have been + * disabled by *_irqsave(). So you can get NMI events occurring while a + * *_bit function is holding a spin lock. If the NMI handler also wants + * to do bit manipulation (and they do) then you can get a deadlock + * between the original caller of *_bit() and the NMI handler. + * + * by Keith Owens + */ + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * This function is atomic and may not be reordered. See __set_bit() + * if you do not require the atomic guarantees. + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p |= mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * clear_bit() is atomic and may not be reordered. However, it does + * not contain a memory barrier, so if it is used for locking purposes, + * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * in order to ensure changes are visible on other processors. + */ +static inline void clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p &= ~mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * change_bit - Toggle a bit in memory + * @nr: Bit to change + * @addr: Address to start counting from + * + * change_bit() is atomic and may not be reordered. It may be + * reordered on other architectures than x86. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p ^= mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It may be reordered on other architectures than x86. + * It also implies a memory barrier. + */ +static inline int test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old | mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +/** + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It can be reorderdered on other architectures other than x86. + * It also implies a memory barrier. + */ +static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old & ~mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +/** + * test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static inline int test_and_change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old ^ mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +#endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */ diff --git a/include/asm-nios2/bitops/ffs.h b/include/asm-nios2/bitops/ffs.h new file mode 100644 index 0000000..fbbb43a --- /dev/null +++ b/include/asm-nios2/bitops/ffs.h @@ -0,0 +1,41 @@ +#ifndef _ASM_GENERIC_BITOPS_FFS_H_ +#define _ASM_GENERIC_BITOPS_FFS_H_ + +/** + * ffs - find first bit set + * @x: the word to search + * + * This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ +static inline int ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} + +#endif /* _ASM_GENERIC_BITOPS_FFS_H_ */ diff --git a/include/asm-nios2/bitops/non-atomic.h b/include/asm-nios2/bitops/non-atomic.h new file mode 100644 index 0000000..697cc2b --- /dev/null +++ b/include/asm-nios2/bitops/non-atomic.h @@ -0,0 +1,108 @@ +#ifndef _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ +#define _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ + +#include <asm/types.h> + +/** + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p |= mask; +} + +static inline void __clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p &= ~mask; +} + +/** + * __change_bit - Toggle a bit in memory + * @nr: the bit to change + * @addr: the address to start counting from + * + * Unlike change_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p ^= mask; +} + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old | mask; + return (old & mask) != 0; +} + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old & ~mask; + return (old & mask) != 0; +} + +/* WARNING: non atomic and it can be reordered! */ +static inline int __test_and_change_bit(int nr, + volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old ^ mask; + return (old & mask) != 0; +} + +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static inline int test_bit(int nr, const volatile unsigned long *addr) +{ + return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); +} + +#endif /* _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ */ diff --git a/include/asm-nios2/errno.h b/include/asm-nios2/errno.h new file mode 100644 index 0000000..4c82b50 --- /dev/null +++ b/include/asm-nios2/errno.h @@ -0,0 +1 @@ +#include <asm-generic/errno.h> diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h index 01d11ef..121405c 100644 --- a/include/asm-nios2/io.h +++ b/include/asm-nios2/io.h @@ -80,19 +80,19 @@ extern unsigned inl (unsigned port); ({unsigned long val;\ asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) -#define writeb(addr,val)\ - asm volatile ("stbio %1, 0(%0)" : : "r" (addr), "r" (val)) -#define writew(addr,val)\ - asm volatile ("sthio %1, 0(%0)" : : "r" (addr), "r" (val)) -#define writel(addr,val)\ - asm volatile ("stwio %1, 0(%0)" : : "r" (addr), "r" (val)) +#define writeb(val,addr)\ + asm volatile ("stbio %0, 0(%1)" : : "r" (val), "r" (addr)) +#define writew(val,addr)\ + asm volatile ("sthio %0, 0(%1)" : : "r" (val), "r" (addr)) +#define writel(val,addr)\ + asm volatile ("stwio %0, 0(%1)" : : "r" (val), "r" (addr)) #define inb(addr) readb(addr) #define inw(addr) readw(addr) #define inl(addr) readl(addr) -#define outb(addr,val) writeb(addr,val) -#define outw(addr,val) writew(addr,val) -#define outl(addr,val) writel(addr,val) +#define outb(val, addr) writeb(val,addr) +#define outw(val, addr) writew(val,addr) +#define outl(val, addr) writel(val,addr) static inline void insb (unsigned long port, void *dst, unsigned long count) { diff --git a/include/asm-nios2/system.h b/include/asm-nios2/system.h index ec84f59..bb03ca5 100644 --- a/include/asm-nios2/system.h +++ b/include/asm-nios2/system.h @@ -23,4 +23,37 @@ #ifndef __ASM_NIOS2_SYSTEM_H_ #define __ASM_NIOS2_SYSTEM_H_ +#define local_irq_enable() __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "ori r8, r8, 1\n" \ + "wrctl status, r8\n" \ + : : : "r8") + +#define local_irq_disable() __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "andi r8, r8, 0xfffe\n" \ + "wrctl status, r8\n" \ + : : : "r8") + +#define local_save_flags(x) __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "mov %0, r8\n" \ + : "=r" (x) : : "r8", "memory") + +#define local_irq_restore(x) __asm__ __volatile__ ( \ + "mov r8, %0\n" \ + "wrctl status, r8\n" \ + : : "r" (x) : "r8", "memory") + +/* For spinlocks etc */ +#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } \ + while (0) + +#define irqs_disabled() \ +({ \ + unsigned long flags; \ + local_save_flags(flags); \ + ((flags & NIOS2_STATUS_PIE_MSK) == 0x0); \ +}) + #endif /* __ASM_NIOS2_SYSTEM_H */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 5cb0f1e..4cb8052 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -244,6 +244,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index e3e6e75..cdba81d 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -173,6 +173,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index ae8494d..2b6786b 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -224,6 +224,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 5c88c47..9221211 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -207,6 +207,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index d131aea..3e7020d 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -256,6 +256,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 07c4e35..d3000f6 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -283,6 +283,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index c78552b..d376344 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -259,6 +259,7 @@ * I2C EEPROM (CAT24WC32) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 59e0778..07acab0 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -278,6 +278,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index b2679e5..5b50bcf 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -189,6 +189,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index 96bf161..9ab30ec 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -65,6 +65,7 @@ #define CONFIG_ETHADDR 00:40:a6:80:14:5 */ #define CONFIG_HARD_I2C 1 /* hardware support for i2c */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SDRAM_BANK0 1 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 49ecb6f..4423f2a 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -174,6 +174,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DU405.h b/include/configs/DU405.h index cfb3023..8f1fc78 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -212,6 +212,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 65dc235..830466f 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -169,6 +169,7 @@ */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_I2C_MULTI_BUS 1 diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h index 61d8e20..3920d35 100644 --- a/include/configs/EP1C20.h +++ b/include/configs/EP1C20.h @@ -94,7 +94,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ @@ -123,14 +124,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h index 41e64e6..bfbf8c1 100644 --- a/include/configs/EP1S10.h +++ b/include/configs/EP1S10.h @@ -92,7 +92,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ @@ -118,14 +119,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h index 5b332e4..4d905fe 100644 --- a/include/configs/EP1S40.h +++ b/include/configs/EP1S40.h @@ -92,7 +92,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ @@ -118,14 +119,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec) */ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index 023f33e..e07f9a1 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -54,6 +54,7 @@ #endif /* total size of a X1240 is 2048 bytes */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/G2000.h b/include/configs/G2000.h index 6819c3e..d2883eb 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -295,6 +295,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 9233523..01e0bc6 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -331,6 +331,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #if 0 /* test-only */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #else diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index ea502d4..8c6d5ed 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -244,6 +244,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 80c70e4..98f5661 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -217,6 +217,7 @@ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 4b67c94..49a7378 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -132,6 +132,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C hardware support */ #undef CONFIG_SOFT_I2C /* I2C !bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 518173a..e7429dd 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -194,6 +194,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C hardware support */ #undef CONFIG_SOFT_I2C /* I2C !bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 7ac9342..7e6484e 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -97,6 +97,7 @@ ***************************************************************/ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 860ec52..55471af 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -210,6 +210,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index b2e2d41..1424713 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -208,6 +208,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 4e39799..0d443ea 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -204,6 +204,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h index 831a60d..c60a9f7 100644 --- a/include/configs/PCI5441.h +++ b/include/configs/PCI5441.h @@ -92,7 +92,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x009208a0 /* UART base addr */ @@ -113,14 +114,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /* diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 962b29e..3e57c0b 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -86,6 +86,7 @@ * The Atmel EEPROM uses 16Bit addressing. ***************************************************************/ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index cf6f7a9..874c20b 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -94,7 +94,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ @@ -123,14 +124,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period */ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 3d59454..f917eb5 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -278,6 +278,7 @@ * I2C EEPROM (24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 87ea7b6..00a12fb 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -235,6 +235,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 7198632..2c048dd 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -215,6 +215,7 @@ * I2C EEPROM (24W16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 89799af..c2fb56c 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -226,6 +226,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 8e9d928..44f03dc 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -414,6 +414,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 38a1d0d..9c91fcc 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -277,6 +277,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 4717869..871e4c3 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -203,6 +203,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index c017915..f06bfe5 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -273,6 +273,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 1d4ad13..be8c9f8 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -280,6 +280,7 @@ * I2C EEPROM (ATMEL 24C04N) */ #define CONFIG_HARD_I2C 1 /* Hardware assisted I2C */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 5c281a1..be9ac62 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -241,6 +241,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/XPEDITE1000.h b/include/configs/XPEDITE1000.h index 658e947..cf39aea 100644 --- a/include/configs/XPEDITE1000.h +++ b/include/configs/XPEDITE1000.h @@ -141,6 +141,7 @@ extern void out32(unsigned int, unsigned long); * I2C */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7f #define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 0fed9ad..f2392f6 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -118,6 +118,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 8cd97b8..13a941e 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -40,6 +40,7 @@ * I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* diff --git a/include/configs/csb272.h b/include/configs/csb272.h index aed6f50..9ded330 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -171,6 +171,7 @@ * */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 24b961f..71eb083 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -170,6 +170,7 @@ * */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ diff --git a/include/configs/korat.h b/include/configs/korat.h index 026dd08..f95df68 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -153,6 +153,7 @@ */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 011dd5c..6461124 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -258,6 +258,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/meesc.h b/include/configs/meesc.h index d002b97..e085f4a 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -82,7 +82,6 @@ */ #include <config_cmd_default.h> #undef CONFIG_CMD_BDI -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h index 4bed7ae..cb7efe7 100644 --- a/include/configs/netstal-common.h +++ b/include/configs/netstal-common.h @@ -42,6 +42,7 @@ * I2C */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/otc570.h b/include/configs/otc570.h index 4fde012..fb0f576 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -131,7 +131,6 @@ * Command line configuration. */ #include <config_cmd_default.h> -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 729ca6a..d6b9207 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -92,6 +92,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 000ae5c..1f744b8 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -138,6 +138,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index b08dcd4..403837e 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -150,6 +150,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index 242f42f..429b11c 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -166,6 +166,7 @@ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/sc3.h b/include/configs/sc3.h index a5eca39..d00f248 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -251,6 +251,7 @@ */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define I2C_INIT #define I2C_ACTIVE 0 diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index a8ba052..09bce6d 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -83,7 +83,6 @@ #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS #undef CONFIG_CMD_NAND -#undef CONFIG_CMD_NET #define CONFIG_CMD_CACHE #define CONFIG_CMD_REGINFO @@ -235,4 +234,15 @@ #define CONFIG_DOS_PARTITION 1 +/* + * Ethernet Contoller driver + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X 1 /* we have a SMC9115 on-board */ +#define CONFIG_SMC911X_16_BIT 1 /* SMC911X_16_BIT Mode */ +#define CONFIG_SMC911X_BASE 0x98800300 /* SMC911X Drive Base */ +#define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ +#endif /* CONFIG_CMD_NET */ + #endif /* __CONFIG_H */ diff --git a/include/configs/zeus.h b/include/configs/zeus.h index 1a77c71..3b2aede 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -167,6 +167,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/linux/stat.h b/include/linux/stat.h index 2ce1c25..cef6369 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -68,7 +68,7 @@ struct stat { #endif /* __PPC__ */ #if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\ - defined (__microblaze__) + defined (__microblaze__) || defined (__nios2__) struct stat { unsigned short st_dev; diff --git a/lib_nios2/board.c b/lib_nios2/board.c index 41d3297..8ec66a3 100644 --- a/lib_nios2/board.c +++ b/lib_nios2/board.c @@ -139,6 +139,13 @@ void board_init (void) board_late_init (); #endif +#if defined(CONFIG_CMD_NET) +#if defined(CONFIG_NET_MULTI) + puts ("Net: "); +#endif + eth_initialize (bd); +#endif + /* main_loop */ for (;;) { WATCHDOG_RESET (); diff --git a/lib_nios2/bootm.c b/lib_nios2/bootm.c index 675bfac..5d25edf 100644 --- a/lib_nios2/bootm.c +++ b/lib_nios2/bootm.c @@ -26,21 +26,26 @@ #include <asm/byteorder.h> #include <asm/cache.h> +#define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */ + int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) { - void (*kernel)(void) = (void (*)(void))images->ep; + void (*kernel)(int, int, int, char *) = (void *)images->ep; + char *commandline = getenv("bootargs"); + ulong initrd_start = images->rd_start; + ulong initrd_end = images->rd_end; if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1; /* flushes data and instruction caches before calling the kernel */ - flush_dcache (0,CONFIG_SYS_DCACHE_SIZE); - flush_icache (0,CONFIG_SYS_ICACHE_SIZE); + disable_interrupts(); + flush_dcache((ulong)kernel, CONFIG_SYS_DCACHE_SIZE); + flush_icache((ulong)kernel, CONFIG_SYS_ICACHE_SIZE); - /* For now we assume the Microtronix linux ... which only - * needs to be called ;-) - */ - kernel (); + debug("bootargs=%s @ 0x%lx\n", commandline, (ulong)&commandline); + debug("initrd=0x%lx-0x%lx\n", (ulong)initrd_start, (ulong)initrd_end); + kernel(NIOS_MAGIC, initrd_start, initrd_end, commandline); /* does not return */ return 1; |