diff options
| -rw-r--r-- | README | 5 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 9 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_pci.h | 6 | ||||
| -rw-r--r-- | common/cmd_nand.c | 2 | ||||
| -rw-r--r-- | common/env_nand.c | 8 |
5 files changed, 22 insertions, 8 deletions
@@ -363,6 +363,11 @@ The following options need to be configured: system clock. On most PQ3 devices this is 8, on newer QorIQ devices it can be 16 or 32. The ratio varies from SoC to Soc. + CONFIG_SYS_FSL_PCIE_COMPAT + + Defines the string to utilize when trying to match PCIe device + tree nodes for the given platform. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 41c2d20..d5c0aee 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -96,6 +96,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" /* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) @@ -175,6 +176,7 @@ #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS 2 @@ -216,6 +218,7 @@ #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_P1024) @@ -265,6 +268,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -280,6 +284,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -291,6 +296,7 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -305,6 +311,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 @@ -330,6 +337,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -345,6 +353,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index fc47a9f..49bd2bf 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -233,7 +233,7 @@ int fsl_pcie_init_board(int busno); #if !defined(CONFIG_PCI) #define FT_FSL_PCI_SETUP #elif defined(CONFIG_FSL_CORENET) -#define FSL_PCIE_COMPAT "fsl,p4080-pcie" +#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT #define FT_FSL_PCI_SETUP \ FT_FSL_PCIE1_SETUP; \ FT_FSL_PCIE2_SETUP; \ @@ -242,7 +242,11 @@ int fsl_pcie_init_board(int busno); #define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP #elif defined(CONFIG_MPC85xx) #define FSL_PCI_COMPAT "fsl,mpc8540-pci" +#ifdef CONFIG_SYS_FSL_PCIE_COMPAT +#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT +#else #define FSL_PCIE_COMPAT "fsl,mpc8548-pcie" +#endif #define FT_FSL_PCI_SETUP \ FT_FSL_PCI1_SETUP; \ FT_FSL_PCI2_SETUP; \ diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 7bd37de..44c4d1f 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -693,7 +693,7 @@ U_BOOT_CMD( " write 'size' bytes starting at offset 'off' with yaffs format\n" " from memory address 'addr', skipping bad blocks.\n" #endif - "nand erase[.spread] [clean] [off [size]] - erase 'size' bytes " + "nand erase[.spread] [clean] off size - erase 'size' bytes " "from offset 'off'\n" " With '.spread', erase enough for given file size, otherwise,\n" " 'size' includes skipped bad blocks.\n" diff --git a/common/env_nand.c b/common/env_nand.c index 980425a..14446a6 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -193,10 +193,8 @@ int saveenv(void) int ret = 0; nand_erase_options_t nand_erase_options; + memset(&nand_erase_options, 0, sizeof(nand_erase_options)); nand_erase_options.length = CONFIG_ENV_RANGE; - nand_erase_options.quiet = 0; - nand_erase_options.jffs2 = 0; - nand_erase_options.scrub = 0; if (CONFIG_ENV_RANGE < CONFIG_ENV_SIZE) return 1; @@ -249,10 +247,8 @@ int saveenv(void) char *res; nand_erase_options_t nand_erase_options; + memset(&nand_erase_options, 0, sizeof(nand_erase_options)); nand_erase_options.length = CONFIG_ENV_RANGE; - nand_erase_options.quiet = 0; - nand_erase_options.jffs2 = 0; - nand_erase_options.scrub = 0; nand_erase_options.offset = CONFIG_ENV_OFFSET; if (CONFIG_ENV_RANGE < CONFIG_ENV_SIZE) |