diff options
37 files changed, 1633 insertions, 105 deletions
@@ -354,6 +354,7 @@ LIST_85xx=" \ sbc8540 \ sbc8548 \ sbc8560 \ + socrates \ stxgp3 \ stxssa \ TQM8540 \ @@ -2208,6 +2208,9 @@ sbc8560_66_config: unconfig fi @$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560 +socrates_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates + stxgp3_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3 diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile index b93bee1..f4dacce 100644 --- a/board/ads5121/Makefile +++ b/board/ads5121/Makefile @@ -23,9 +23,14 @@ include $(TOPDIR)/config.mk +$(shell mkdir -p $(OBJTREE)/board/freescale/common) + LIB = $(obj)lib$(BOARD).a COBJS-y := $(BOARD).o +COBJS-${CONFIG_FSL_DIU_FB} += ads5121_diu.o +COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_diu_fb.o +COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_logo_bmp.o COBJS-$(CONFIG_PCI) += pci.o COBJS := $(COBJS-y) diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 8629b03..2892665 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -39,17 +39,35 @@ #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_DIU_EN | \ CLOCK_SCCR2_I2C_EN) #define CSAW_START(start) ((start) & 0xFFFF0000) #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) +#define MPC5121_IOCTL_PSC6_0 (0x284/4) +#define MPC5121_IO_DIU_START (0x288/4) +#define MPC5121_IO_DIU_END (0x2fc/4) + +/* Functional pin muxing */ +#define MPC5121_IO_FUNC1 (0 << 7) +#define MPC5121_IO_FUNC2 (1 << 7) +#define MPC5121_IO_FUNC3 (2 << 7) +#define MPC5121_IO_FUNC4 (3 << 7) +#define MPC5121_IO_ST (1 << 2) +#define MPC5121_IO_DS_1 (0) +#define MPC5121_IO_DS_2 (1) +#define MPC5121_IO_DS_3 (2) +#define MPC5121_IO_DS_4 (3) + long int fixed_sdram(void); int board_early_init_f (void) { volatile immap_t *im = (immap_t *) CFG_IMMR; - u32 lpcaw; + u32 lpcaw, tmp32; + volatile ioctrl512x_t *ioctl = &(im->io_ctrl); + int i; /* * Initialize Local Window for the CPLD registers access (CS2 selects @@ -81,6 +99,16 @@ int board_early_init_f (void) im->clk.sccr[0] = SCCR1_CLOCKS_EN; im->clk.sccr[1] = SCCR2_CLOCKS_EN; + /* Configure DIU clock pin */ + tmp32 = ioctl->regs[MPC5121_IOCTL_PSC6_0]; + tmp32 &= ~0x1ff; + tmp32 |= MPC5121_IO_FUNC3 | MPC5121_IO_DS_4; + ioctl->regs[MPC5121_IOCTL_PSC6_0] = tmp32; + + /* Initialize IO pins (pin mux) for DIU function */ + for (i = MPC5121_IO_DIU_START; i < MPC5121_IO_DIU_END; i++) + ioctl->regs[i] |= (MPC5121_IO_FUNC3 | MPC5121_IO_DS_4); + return 0; } @@ -186,6 +214,38 @@ long int fixed_sdram (void) return msize; } +int misc_init_r(void) +{ + u8 tmp_val; + + /* Using this for DIU init before the driver in linux takes over + * Enable the TFP410 Encoder (I2C address 0x38) + */ + + i2c_set_bus_num(2); + tmp_val = 0xBF; + i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); + /* Verify if enabled */ + tmp_val = 0; + i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); + debug("DVI Encoder Read: 0x%02lx\n", tmp_val); + + tmp_val = 0x10; + i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); + /* Verify if enabled */ + tmp_val = 0; + i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); + debug("DVI Encoder Read: 0x%02lx\n", tmp_val); + +#ifdef CONFIG_FSL_DIU_FB +#if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) + ads5121_diu_init(); +#endif +#endif + + return 0; +} + int checkboard (void) { ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00); diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c new file mode 100644 index 0000000..87cf0cb --- /dev/null +++ b/board/ads5121/ads5121_diu.c @@ -0,0 +1,165 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * York Sun <yorksun@freescale.com> + * + * FSL DIU Framebuffer driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#ifdef CONFIG_FSL_DIU_FB + +#include "../freescale/common/pixis.h" +#include "../freescale/common/fsl_diu_fb.h" + +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) +#include <devices.h> +#include <video_fb.h> +#endif + +extern unsigned int FSL_Logo_BMP[]; + +static int xres, yres; + +void diu_set_pixel_clock(unsigned int pixclock) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile clk512x_t *clk = &immap->clk; + volatile unsigned int *clkdvdr = &clk->scfr[0]; + unsigned long speed_ccb, temp, pixval; + + speed_ccb = get_bus_freq(0) * 4; + temp = 1000000000/pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + debug("DIU pixval = %lu\n", pixval); + + /* Modify PXCLK in GUTS CLKDVDR */ + debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr); + temp = *clkdvdr & 0xFFFFFF00; + *clkdvdr = temp | (pixval & 0x1F); + debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr); +} + +int ads5121_diu_init(void) +{ + unsigned int pixel_format; + + xres = 1024; + yres = 768; + pixel_format = 0x88883316; + + return fsl_diu_init(xres, pixel_format, 0, + (unsigned char *)FSL_Logo_BMP); +} + +int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp, + int flag, int argc, char *argv[]) +{ + unsigned int addr; + + if (argc < 2) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (!strncmp(argv[1], "init", 4)) { +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) + fsl_diu_clear_screen(); + drv_video_init(); +#else + return ads5121_diu_init(); +#endif + } else { + addr = simple_strtoul(argv[1], NULL, 16); + fsl_diu_clear_screen(); + fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0); + } + + return 0; +} + +U_BOOT_CMD( + diufb, CFG_MAXARGS, 1, ads5121diu_init_show_bmp, + "diufb init | addr - Init or Display BMP file\n", + "init\n - initialize DIU\n" + "addr\n - display bmp at address 'addr'\n" + ); + + +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) + +/* + * The Graphic Device + */ +GraphicDevice ctfb; +void *video_hw_init(void) +{ + GraphicDevice *pGD = (GraphicDevice *) &ctfb; + struct fb_info *info; + + if (ads5121_diu_init() < 0) + return; + + /* fill in Graphic device struct */ + sprintf(pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", + xres, yres, 32, 64, 60); + + pGD->frameAdrs = (unsigned int)fsl_fb_open(&info); + pGD->winSizeX = xres; + pGD->winSizeY = yres - info->logo_height; + pGD->plnSizeX = pGD->winSizeX; + pGD->plnSizeY = pGD->winSizeY; + + pGD->gdfBytesPP = 4; + pGD->gdfIndex = GDF_32BIT_X888RGB; + + pGD->isaBase = 0; + pGD->pciBase = 0; + pGD->memSize = info->screen_size - info->logo_size; + + /* Cursor Start Address */ + pGD->dprBase = 0; + pGD->vprBase = 0; + pGD->cprBase = 0; + + return (void *)pGD; +} + +/** + * Set the LUT + * + * @index: color number + * @r: red + * @b: blue + * @g: green + */ +void video_set_lut + (unsigned int index, unsigned char r, unsigned char g, unsigned char b) +{ + return; +} + +#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ + +#endif /* CONFIG_FSL_DIU_FB */ diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index 6189ec9..75f782e 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -29,12 +29,6 @@ #include "fsl_diu_fb.h" -#ifdef DEBUG -#define DPRINTF(fmt, args...) printf("%s: " fmt,__FUNCTION__,## args) -#else -#define DPRINTF(fmt, args...) -#endif - struct fb_videomode { const char *name; /* optional */ unsigned int refresh; /* optional */ @@ -163,8 +157,6 @@ struct diu_addr { unsigned int offset; }; -#define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of Display Interface Unit */ - /* * Modes of operation of DIU */ @@ -197,7 +189,7 @@ static void disable_lcdc(void); static int fsl_diu_enable_panel(struct fb_info *info); static int fsl_diu_disable_panel(struct fb_info *info); static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align); -static u32 get_busfreq(void); +void diu_set_pixel_clock(unsigned int pixclock); int fsl_diu_init(int xres, unsigned int pixel_format, @@ -209,15 +201,11 @@ int fsl_diu_init(int xres, struct diu *hw; struct fb_info *info = &fsl_fb_info; struct fb_var_screeninfo *var = &info->var; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile unsigned int *guts_clkdvdr = &gur->clkdvdr; unsigned char *gamma_table_base; unsigned int i, j; - unsigned long speed_ccb, temp, pixval; - DPRINTF("Enter fsl_diu_init\n"); - dr.diu_reg = (struct diu *) (CFG_IMMR + FSL_DIU_BASE_OFFSET); + debug("Enter fsl_diu_init\n"); + dr.diu_reg = (struct diu *) (CFG_DIU_ADDR); hw = (struct diu *) dr.diu_reg; disable_lcdc(); @@ -230,10 +218,10 @@ int fsl_diu_init(int xres, if (0 == fb_initialized) { allocate_buf(&gamma, 768, 32); - DPRINTF("gamma is allocated @ 0x%x\n", + debug("gamma is allocated @ 0x%x\n", (unsigned int)gamma.paddr); allocate_buf(&cursor, MAX_CURS * MAX_CURS * 2, 32); - DPRINTF("curosr is allocated @ 0x%x\n", + debug("curosr is allocated @ 0x%x\n", (unsigned int)cursor.paddr); /* create a dummy fb and dummy ad */ @@ -261,8 +249,8 @@ int fsl_diu_init(int xres, dr.diu_reg->desc[0] = (unsigned int) &dummy_ad; dr.diu_reg->desc[1] = (unsigned int) &dummy_ad; dr.diu_reg->desc[2] = (unsigned int) &dummy_ad; - DPRINTF("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]); - DPRINTF("dummy desc[0] = 0x%x\n", hw->desc[0]); + debug("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]); + debug("dummy desc[0] = 0x%x\n", hw->desc[0]); /* read mode info */ var->xres = fsl_diu_mode_db->xres; @@ -300,7 +288,7 @@ int fsl_diu_init(int xres, ad->ckmin_b = 255; gamma_table_base = gamma.paddr; - DPRINTF("gamma_table_base is allocated @ 0x%x\n", + debug("gamma_table_base is allocated @ 0x%x\n", (unsigned int)gamma_table_base); /* Prep for DIU init - gamma table */ @@ -310,7 +298,7 @@ int fsl_diu_init(int xres, *gamma_table_base++ = j; if (gamma_fix == 1) { /* fix the gamma */ - DPRINTF("Fix gamma table\n"); + debug("Fix gamma table\n"); gamma_table_base = gamma.paddr; for (i = 0; i < 256*3; i++) { gamma_table_base[i] = (gamma_table_base[i] << 2) @@ -318,7 +306,7 @@ int fsl_diu_init(int xres, } } - DPRINTF("update-lcdc: HW - %p\n Disabling DIU\n", hw); + debug("update-lcdc: HW - %p\n Disabling DIU\n", hw); /* Program DIU registers */ @@ -336,37 +324,22 @@ int fsl_diu_init(int xres, var->vsync_len << 11 | /* PW_V */ var->lower_margin; /* FP_V */ - /* Pixel Clock configuration */ - DPRINTF("DIU: Bus Frequency = %d\n", get_busfreq()); - speed_ccb = get_busfreq(); - - DPRINTF("DIU pixclock in ps - %d\n", var->pixclock); - temp = 1; - temp *= 1000000000; - temp /= var->pixclock; - temp *= 1000; - pixval = speed_ccb / temp; - DPRINTF("DIU pixval = %lu\n", pixval); - hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */ hw->thresholds = 0x00037800; /* The Thresholds */ hw->int_status = 0; /* INTERRUPT STATUS */ hw->int_mask = 0; /* INT MASK */ hw->plut = 0x01F5F666; - /* Modify PXCLK in GUTS CLKDVDR */ - DPRINTF("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); - temp = *guts_clkdvdr & 0x2000FFFF; - *guts_clkdvdr = temp; /* turn off clock */ - *guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16); - DPRINTF("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); + /* Pixel Clock configuration */ + debug("DIU pixclock in ps - %d\n", var->pixclock); + diu_set_pixel_clock(var->pixclock); fb_initialized = 1; if (splash_bmp) { info->logo_height = fsl_diu_display_bmp(splash_bmp, 0, 0, 0); info->logo_size = info->logo_height * info->line_length; - DPRINTF("logo height %d, logo_size 0x%x\n", + debug("logo height %d, logo_size 0x%x\n", info->logo_height,info->logo_size); } @@ -395,10 +368,10 @@ static int fsl_diu_enable_panel(struct fb_info *info) struct diu *hw = dr.diu_reg; struct diu_ad *ad = &fsl_diu_fb_ad; - DPRINTF("Entered: enable_panel\n"); + debug("Entered: enable_panel\n"); if (hw->desc[0] != (unsigned int)ad) hw->desc[0] = (unsigned int)ad; - DPRINTF("desc[0] = 0x%x\n", hw->desc[0]); + debug("desc[0] = 0x%x\n", hw->desc[0]); return 0; } @@ -406,7 +379,7 @@ static int fsl_diu_disable_panel(struct fb_info *info) { struct diu *hw = dr.diu_reg; - DPRINTF("Entered: disable_panel\n"); + debug("Entered: disable_panel\n"); if (hw->desc[0] != (unsigned int)&dummy_ad) hw->desc[0] = (unsigned int)&dummy_ad; return 0; @@ -417,10 +390,10 @@ static int map_video_memory(struct fb_info *info, unsigned long bytes_align) unsigned long offset; unsigned long mask; - DPRINTF("Entered: map_video_memory\n"); + debug("Entered: map_video_memory\n"); /* allocate maximum 1280*1024 with 32bpp */ info->smem_len = 1280 * 4 *1024 + bytes_align; - DPRINTF("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len); + debug("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len); info->screen_base = malloc(info->smem_len); if (info->screen_base == NULL) { printf("Unable to allocate fb memory\n"); @@ -437,7 +410,7 @@ static int map_video_memory(struct fb_info *info, unsigned long bytes_align) info->screen_size = info->smem_len; - DPRINTF("Allocated fb @ 0x%08lx, size=%d.\n", + debug("Allocated fb @ 0x%08lx, size=%d.\n", info->smem_start, info->smem_len); return 0; @@ -447,33 +420,25 @@ static void enable_lcdc(void) { struct diu *hw = dr.diu_reg; - DPRINTF("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled); + debug("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled); if (!fb_enabled) { hw->diu_mode = dr.mode; fb_enabled++; } - DPRINTF("diu_mode = %d\n", hw->diu_mode); + debug("diu_mode = %d\n", hw->diu_mode); } static void disable_lcdc(void) { struct diu *hw = dr.diu_reg; - DPRINTF("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled); + debug("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled); if (fb_enabled) { hw->diu_mode = 0; fb_enabled = 0; } } -static u32 get_busfreq(void) -{ - u32 fs_busfreq = 0; - - fs_busfreq = get_bus_freq(0); - return fs_busfreq; -} - /* * Align to 64-bit(8-byte), 32-byte, etc. */ @@ -482,7 +447,7 @@ static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align) u32 offset, ssize; u32 mask; - DPRINTF("Entered: allocate_buf\n"); + debug("Entered: allocate_buf\n"); ssize = size + bytes_align; buf->paddr = malloc(ssize); if (!buf->paddr) @@ -524,16 +489,16 @@ int fsl_diu_display_bmp(unsigned char *bmp, bitmap = bmp + raster; cpp = info->var.bits_per_pixel / 8; - DPRINTF("bmp = 0x%08x\n", (unsigned int)bmp); - DPRINTF("bitmap = 0x%08x\n", (unsigned int)bitmap); - DPRINTF("width = %d\n", width); - DPRINTF("height = %d\n", height); - DPRINTF("bpp = %d\n", bpp); - DPRINTF("ncolors = %d\n", ncolors); + debug("bmp = 0x%08x\n", (unsigned int)bmp); + debug("bitmap = 0x%08x\n", (unsigned int)bitmap); + debug("width = %d\n", width); + debug("height = %d\n", height); + debug("bpp = %d\n", bpp); + debug("ncolors = %d\n", ncolors); - DPRINTF("xres = %d\n", info->var.xres); - DPRINTF("yres = %d\n", info->var.yres); - DPRINTF("Screen_base = 0x%x\n", (unsigned int)info->screen_base); + debug("xres = %d\n", info->var.xres); + debug("yres = %d\n", info->var.yres); + debug("Screen_base = 0x%x\n", (unsigned int)info->screen_base); if (((width+xoffset) > info->var.xres) || ((height+yoffset) > info->var.yres)) { diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c index b70637f..4db941c 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c @@ -41,6 +41,26 @@ extern unsigned int FSL_Logo_BMP[]; static int xres, yres; +void diu_set_pixel_clock(unsigned int pixclock) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile unsigned int *guts_clkdvdr = &gur->clkdvdr; + unsigned long speed_ccb, temp, pixval; + + speed_ccb = get_bus_freq(0); + temp = 1000000000/pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + debug("DIU pixval = %lu\n", pixval); + + /* Modify PXCLK in GUTS CLKDVDR */ + debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); + temp = *guts_clkdvdr & 0x2000FFFF; + *guts_clkdvdr = temp; /* turn off clock */ + *guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16); + debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); +} void mpc8610hpcd_diu_init(void) { diff --git a/board/socrates/Makefile b/board/socrates/Makefile new file mode 100644 index 0000000..6453f24 --- /dev/null +++ b/board/socrates/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2008 +# Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a +# + +COBJS := $(BOARD).o law.o tlb.o sdram.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/socrates/config.mk b/board/socrates/config.mk new file mode 100644 index 0000000..1cf5d38 --- /dev/null +++ b/board/socrates/config.mk @@ -0,0 +1,30 @@ +# Copyright 2004 Freescale Semiconductor. +# +# Modified by Sergei Poselenov +# (C) Copyright 2008, Emcraft Systems. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# socrates board +# default CCARBAR is at 0xff700000 +# assume U-Boot is less than 256k +# +TEXT_BASE = 0xfffc0000 diff --git a/board/socrates/law.c b/board/socrates/law.c new file mode 100644 index 0000000..5f4b8ca --- /dev/null +++ b/board/socrates/law.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c new file mode 100644 index 0000000..329eacc --- /dev/null +++ b/board/socrates/sdram.c @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <spd_sdram.h> + + +#if !defined(CONFIG_SPD_EEPROM) +/* + * Autodetect onboard DDR SDRAM on 85xx platforms + * + * NOTE: Some of the hardcoded values are hardware dependant, + * so this should be extended for other future boards + * using this routine! + */ +long int sdram_setup(int casl) +{ + volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); + + /* + * Disable memory controller. + */ + ddr->cs0_config = 0; + ddr->sdram_cfg = 0; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->timing_cfg_0 = CFG_DDR_TIMING_0; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode = CFG_DDR_MODE; + ddr->sdram_interval = CFG_DDR_INTERVAL; + ddr->sdram_cfg_2 = CFG_DDR_CONFIG_2; + ddr->sdram_clk_cntl = CFG_DDR_CLK_CONTROL; + + asm ("sync;isync;msync"); + udelay(1000); + + ddr->sdram_cfg = CFG_DDR_CONFIG; + asm ("sync; isync; msync"); + udelay(1000); + + if (get_ram_size(0, CFG_SDRAM_SIZE<<20) == CFG_SDRAM_SIZE<<20) { + /* + * OK, size detected -> all done + */ + return CFG_SDRAM_SIZE<<20; + } + + return 0; /* nothing found ! */ +} +#endif + +long int initdram (int board_type) +{ + long dram_size = 0; +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL); +#endif + return dram_size; +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf ("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("SDRAM test passed.\n"); + return 0; +} +#endif diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c new file mode 100644 index 0000000..cb58994 --- /dev/null +++ b/board/socrates/socrates.c @@ -0,0 +1,211 @@ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003, Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <ioports.h> +#include <flash.h> +#include <libfdt.h> +#include <fdt_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[]; /* FLASH chips info */ + +void local_bus_init (void); +ulong flash_get_size (ulong base, int banknum); + +int checkboard (void) +{ + char *s = getenv("serial#"); + + puts("Board: Socrates"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + +#ifdef CONFIG_PCI + printf ("PCI1: 32 bit, %d MHz (compiled)\n", + CONFIG_SYS_CLK_FREQ / 1000000); +#else + printf ("PCI1: disabled\n"); +#endif + + /* + * Initialize local bus. + */ + local_bus_init (); + + return 0; +} + +int misc_init_r (void) +{ + volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); + + /* + * Adjust flash start and offset to detected values + */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Check if boot FLASH isn't max size + */ + if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) { + memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff); + memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); + } + + /* + * Check if only one FLASH bank is available + */ + if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { + memctl->or1 = 0; + memctl->br1 = 0; + + /* + * Re-do flash protection upon new addresses + */ + flash_protect (FLAG_PROTECT_CLEAR, + gd->bd->bi_flashstart, 0xffffffff, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Redundant environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + } + + return 0; +} + +/* + * Initialize Local Bus + */ +void local_bus_init (void) +{ + + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); + + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ + ecm->eedr = 0xffffffff; /* Clear ecm errors */ + ecm->eeer = 0xffffffff; /* Enable ecm errors */ + +} + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxads_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER}}, + {} +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc85xxads_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void pci_init_board (void) +{ +#ifdef CONFIG_PCI + pci_mpc85xx_init (&hose); +#endif /* CONFIG_PCI */ +} + +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r (void) +{ +#ifdef CONFIG_PS2MULT + ps2mult_early_init(); +#endif /* CONFIG_PS2MULT */ + return (0); +} +#endif /* CONFIG_BOARD_EARLY_INIT_R */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 0; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize; + + rc = fdt_find_and_setprop(blob, "/localbus", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c new file mode 100644 index 0000000..b80caea --- /dev/null +++ b/board/socrates/tlb.c @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + + /* + * TLB 0, 1: 128M Non-cacheable, guarded + * 0xf8000000 128M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_64M, 1), + SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 6: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7+8: 512M DDR, cache disabled (needed for memory test) + * 0x00000000 512M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_256M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/socrates/u-boot.lds b/board/socrates/u-boot.lds new file mode 100644 index 0000000..8d2f65c --- /dev/null +++ b/board/socrates/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * (C) Copyright 2002,2003, Motorola,Inc. + * Xianghua Xiao, X.Xiao@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/common/cmd_log.c b/common/cmd_log.c index b9f9ba0..c6e72ac 100644 --- a/common/cmd_log.c +++ b/common/cmd_log.c @@ -107,7 +107,7 @@ void logbuff_init_ptrs (void) if ((s = getenv ("loglevel")) != NULL) console_loglevel = (int)simple_strtoul (s, NULL, 10); - gd->post_log_word |= LOGBUFF_INITIALIZED; + gd->flags |= GD_FLG_LOGINIT; } void logbuff_reset (void) @@ -168,7 +168,7 @@ static void logbuff_puts (const char *s) void logbuff_log(char *msg) { - if ((gd->post_log_word & LOGBUFF_INITIALIZED)) { + if ((gd->flags & GD_FLG_LOGINIT)) { logbuff_printk (msg); } else { /* Can happen only for pre-relocated errors as logging */ diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 74b210c..9873383 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -174,28 +174,33 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { uint pvr; uint ver; + unsigned long val, msr; + pvr = get_pvr(); ver = PVR_VER(pvr); + if (ver & 1){ /* e500 v2 core has reset control register */ volatile unsigned int * rstcr; rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0); *rstcr = 0x2; /* HRESET_REQ */ - }else{ + udelay(100); + } + /* + * Fallthrough if the code above failed * Initiate hard reset in debug control register DBCR0 * Make sure MSR[DE] = 1 */ - unsigned long val, msr; - msr = mfmsr (); - msr |= MSR_DE; - mtmsr (msr); + msr = mfmsr (); + msr |= MSR_DE; + mtmsr (msr); + + val = mfspr(DBCR0); + val |= 0x70000000; + mtspr(DBCR0,val); - val = mfspr(DBCR0); - val |= 0x70000000; - mtspr(DBCR0,val); - } return 1; } diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h index 0410b5e..7564ff1 100644 --- a/include/asm-arm/global_data.h +++ b/include/asm-arm/global_data.h @@ -61,6 +61,8 @@ typedef struct global_data { #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h index daf64bc..007cfe4 100644 --- a/include/asm-avr32/global_data.h +++ b/include/asm-avr32/global_data.h @@ -52,6 +52,8 @@ typedef struct global_data { #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */ #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5") diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h index 6debfc7..4c88639 100644 --- a/include/asm-blackfin/global_data.h +++ b/include/asm-blackfin/global_data.h @@ -62,6 +62,8 @@ typedef struct global_data { #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */ #define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P5") diff --git a/include/asm-i386/global_data.h b/include/asm-i386/global_data.h index 68a9ad6..3235063 100644 --- a/include/asm-i386/global_data.h +++ b/include/asm-i386/global_data.h @@ -55,6 +55,8 @@ typedef struct { #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ extern gd_t *global_data; diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h index c897f2b..7377d31 100644 --- a/include/asm-m68k/global_data.h +++ b/include/asm-m68k/global_data.h @@ -73,6 +73,8 @@ typedef struct global_data { #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #if 0 extern gd_t *global_data; diff --git a/include/asm-microblaze/global_data.h b/include/asm-microblaze/global_data.h index 91243b2..376786f 100644 --- a/include/asm-microblaze/global_data.h +++ b/include/asm-microblaze/global_data.h @@ -53,6 +53,8 @@ typedef struct global_data { #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31") diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h index bd9e4dd..0c0ba50 100644 --- a/include/asm-mips/global_data.h +++ b/include/asm-mips/global_data.h @@ -55,6 +55,8 @@ typedef struct global_data { #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0") diff --git a/include/asm-nios/global_data.h b/include/asm-nios/global_data.h index ddd66cf..a8cc987 100644 --- a/include/asm-nios/global_data.h +++ b/include/asm-nios/global_data.h @@ -46,6 +46,8 @@ typedef struct global_data { #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("%g7") diff --git a/include/asm-nios2/global_data.h b/include/asm-nios2/global_data.h index ae5f617..7290489 100644 --- a/include/asm-nios2/global_data.h +++ b/include/asm-nios2/global_data.h @@ -45,6 +45,8 @@ typedef struct global_data { #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r15") diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 202c844..ea70266 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -168,6 +168,8 @@ typedef struct global_data { #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #if 1 #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2") diff --git a/include/asm-sh/global_data.h b/include/asm-sh/global_data.h index 521a66f..69af24a 100644 --- a/include/asm-sh/global_data.h +++ b/include/asm-sh/global_data.h @@ -45,6 +45,8 @@ typedef struct global_data #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13") diff --git a/include/asm-sparc/global_data.h b/include/asm-sparc/global_data.h index 7c29fc6..de2c84b 100644 --- a/include/asm-sparc/global_data.h +++ b/include/asm-sparc/global_data.h @@ -79,6 +79,9 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("%g7") diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index f55d91f..c975a24 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -45,14 +45,25 @@ */ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ +#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ + +/* video */ +#undef CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif /* CONFIG_PCI is defined at config time */ #define CFG_MPC512X_CLKIN 66000000 /* in Hz */ #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R #define CFG_IMMR 0x80000000 +#define CFG_DIU_ADDR (CFG_IMMR+0x2100) #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 @@ -127,28 +138,28 @@ #define CFG_MICRON_OCD_DEFAULT 0x01010780 /* DDR Priority Manager Configuration */ -#define CFG_MDDRCGRP_PM_CFG1 0x000777AA -#define CFG_MDDRCGRP_PM_CFG2 0x00000055 -#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000 -#define CFG_MDDRCGRP_LUT0_MU 0x11111117 -#define CFG_MDDRCGRP_LUT0_ML 0x7777777A -#define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE -#define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE -#define CFG_MDDRCGRP_LUT2_MU 0x44444444 +#define CFG_MDDRCGRP_PM_CFG1 0x00077777 +#define CFG_MDDRCGRP_PM_CFG2 0x00000000 +#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000001 +#define CFG_MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define CFG_MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define CFG_MDDRCGRP_LUT1_MU 0x66666666 +#define CFG_MDDRCGRP_LUT1_ML 0x55555555 +#define CFG_MDDRCGRP_LUT2_MU 0x44444444 #define CFG_MDDRCGRP_LUT2_ML 0x44444444 -#define CFG_MDDRCGRP_LUT3_MU 0x55555555 +#define CFG_MDDRCGRP_LUT3_MU 0x55555555 #define CFG_MDDRCGRP_LUT3_ML 0x55555558 -#define CFG_MDDRCGRP_LUT4_MU 0x11111111 -#define CFG_MDDRCGRP_LUT4_ML 0x1111117C -#define CFG_MDDRCGRP_LUT0_AU 0x33333377 -#define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE -#define CFG_MDDRCGRP_LUT1_AU 0x11111111 -#define CFG_MDDRCGRP_LUT1_AL 0x11111111 -#define CFG_MDDRCGRP_LUT2_AU 0x11111111 +#define CFG_MDDRCGRP_LUT4_MU 0x11111111 +#define CFG_MDDRCGRP_LUT4_ML 0x11111122 +#define CFG_MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define CFG_MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define CFG_MDDRCGRP_LUT1_AU 0x66666666 +#define CFG_MDDRCGRP_LUT1_AL 0x66666666 +#define CFG_MDDRCGRP_LUT2_AU 0x11111111 #define CFG_MDDRCGRP_LUT2_AL 0x11111111 -#define CFG_MDDRCGRP_LUT3_AU 0x11111111 +#define CFG_MDDRCGRP_LUT3_AU 0x11111111 #define CFG_MDDRCGRP_LUT3_AL 0x11111111 -#define CFG_MDDRCGRP_LUT4_AU 0x11111111 +#define CFG_MDDRCGRP_LUT4_AU 0x11111111 #define CFG_MDDRCGRP_LUT4_AL 0x11111111 /* @@ -189,7 +200,11 @@ #define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ +#ifdef CONFIG_FSL_DIU_FB +#define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ +#else +#define CFG_MALLOC_LEN (512 * 1024) +#endif /* * Serial Port diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 1f669aa..cf406c8 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -88,15 +88,20 @@ /* unused GPT0 COMP reg */ #define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ /* 440EPx errata CHIP 11 */ +#define CFG_OCM_SIZE (16 << 10) /* Additional registers for watchdog timer post test */ #define CFG_WATCHDOG_TIME_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK2) #define CFG_WATCHDOG_FLAGS_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK1) #define CFG_DSPIC_TEST_ADDR CFG_WATCHDOG_FLAGS_ADDR +#define CFG_OCM_STATUS_ADDR CFG_WATCHDOG_FLAGS_ADDR #define CFG_WATCHDOG_MAGIC 0x12480000 #define CFG_WATCHDOG_MAGIC_MASK 0xFFFF0000 #define CFG_DSPIC_TEST_MASK 0x00000001 +#define CFG_OCM_STATUS_OK 0x00009A00 +#define CFG_OCM_STATUS_FAIL 0x0000A300 +#define CFG_OCM_STATUS_MASK 0x0000FF00 /*----------------------------------------------------------------------- * Serial Port @@ -162,6 +167,7 @@ CFG_POST_FPU | \ CFG_POST_I2C | \ CFG_POST_MEMORY | \ + CFG_POST_OCM | \ CFG_POST_RTC | \ CFG_POST_SPR | \ CFG_POST_UART | \ diff --git a/include/configs/socrates.h b/include/configs/socrates.h new file mode 100644 index 0000000..5d37383 --- /dev/null +++ b/include/configs/socrates.h @@ -0,0 +1,402 @@ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * Wolfgang Denk <wd@denx.de> + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao <X.Xiao@motorola.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Socrates + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ +#define CONFIG_MPC8544 1 +#define CONFIG_SOCRATES 1 + +#define CONFIG_PCI + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ + +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +/* + * sysclk for MPC85xx + * + * Two valid values are: + * 33000000 + * 66000000 + * + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz + * is likely the desired value here, so that is now the default. + * The board, however, can run at 66MHz. In any event, this value + * must match the settings of some switches. Details can be found + * in the README.mpc85xxads. + */ + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 66666666 +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 +#define CFG_MEMTEST_END 0x10000000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ + +/* Hardcoded values, to use instead of SPD */ +#define CFG_DDR_CS0_BNDS 0x0000000f +#define CFG_DDR_CS0_CONFIG 0x80010102 +#define CFG_DDR_TIMING_0 0x00260802 +#define CFG_DDR_TIMING_1 0x3935D322 +#define CFG_DDR_TIMING_2 0x14904CC8 +#define CFG_DDR_MODE 0x00480432 +#define CFG_DDR_INTERVAL 0x030C0100 +#define CFG_DDR_CONFIG_2 0x04400000 +#define CFG_DDR_CONFIG 0xC3008000 +#define CFG_DDR_CLK_CONTROL 0x03800000 +#define CFG_SDRAM_SIZE 256 /* in Megs */ + +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/ +#define SPD_EEPROM_ADDRESS 0x50 /* DDR DIMM */ +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +/* + * Flash on the Local Bus + */ +/* + * Flash on the LocalBus + */ +#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ + +#define CFG_FLASH0 0xFE000000 +#define CFG_FLASH1 0xFC000000 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } + +#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ +#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ + +#define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */ +#define CFG_OR0_PRELIM 0xfe000ff7 /* 32MB Flash */ +#define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */ +#define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */ + +#define CFG_FLASH_CFI /* flash is CFI compat. */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ + +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 + +/* I2C RTC */ +#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */ + +/* RapidIO MMU */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Memory space is mapped 1-1. + */ +#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ + + +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xE2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "TSEC1" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 0 +#define TSEC3_PHY_ADDR 1 + +#define TSEC1_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0,1] */ +#define CONFIG_ETHPRIME "TSEC0" +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_TIMESTAMP /* Print image info with ts */ + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#undef CONFIG_CMD_RTC +#define CONFIG_CMD_SNTP + + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootfile=/tftpboot/socrates/uImage\0" \ + "netdev=eth0\0" \ + "consdev=ttyS0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ + ":$hostname:$netdev:off panic=1\0" \ + "addcons=setenv bootargs $bootargs " \ + "console=$consdev,$baudrate\0" \ + "flash_self=run ramargs addip addcons;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addcons;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "tftp ${fdt_addr_r} ${fdt_file}; " \ + "run nfsargs addip addcons;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "fdt_file=socrates/socrates.dtb\0" \ + "fdt_addr_r=B00000\0" \ + "fdt_addr=FC1E0000\0" \ + "rootpath=/opt/eldk/ppc_85xx\0" \ + "kernel_addr=FC000000\0" \ + "kernel_addr_r=200000\0" \ + "ramdisk_addr=FC200000\0" \ + "ramdisk_addr_r=400000\0" \ + "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#endif /* __CONFIG_H */ diff --git a/include/logbuff.h b/include/logbuff.h index d415729..d06d208 100644 --- a/include/logbuff.h +++ b/include/logbuff.h @@ -31,8 +31,6 @@ #define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */ #define LOGBUFF_RESERVE (LOGBUFF_LEN+LOGBUFF_OVERHEAD) -#define LOGBUFF_INITIALIZED (1<<31) - /* The mapping used here has to be the same as in setup_ext_logbuff () in linux/kernel/printk */ diff --git a/include/post.h b/include/post.h index ee07d2c..123623f 100644 --- a/include/post.h +++ b/include/post.h @@ -43,6 +43,7 @@ #define POST_PREREL 0x1000 /* test runs before relocation */ #define POST_CRITICAL 0x2000 /* Use failbootcmd if test failed */ +#define POST_STOP 0x4000 /* Interrupt POST sequence on fail */ #define POST_MEM (POST_RAM | POST_ROM) #define POST_ALWAYS (POST_NORMAL | \ @@ -94,7 +95,7 @@ extern int post_hotkeys_pressed(void); #define CFG_POST_SPR 0x00000400 #define CFG_POST_SYSMON 0x00000800 #define CFG_POST_DSP 0x00001000 -#define CFG_POST_CODEC 0x00002000 +#define CFG_POST_OCM 0x00002000 #define CFG_POST_FPU 0x00004000 #define CFG_POST_ECC 0x00008000 #define CFG_POST_BSPEC1 0x00010000 @@ -102,6 +103,7 @@ extern int post_hotkeys_pressed(void); #define CFG_POST_BSPEC3 0x00040000 #define CFG_POST_BSPEC4 0x00080000 #define CFG_POST_BSPEC5 0x00100000 +#define CFG_POST_CODEC 0x00200000 #endif /* CONFIG_POST */ diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile index f19dc5d..1cfd3bb 100644 --- a/post/cpu/ppc4xx/Makefile +++ b/post/cpu/ppc4xx/Makefile @@ -29,6 +29,7 @@ COBJS-$(CONFIG_HAS_POST) += cache.o COBJS-$(CONFIG_HAS_POST) += denali_ecc.o COBJS-$(CONFIG_HAS_POST) += ether.o COBJS-$(CONFIG_HAS_POST) += fpu.o +COBJS-$(CONFIG_HAS_POST) += ocm.o COBJS-$(CONFIG_HAS_POST) += spr.o COBJS-$(CONFIG_HAS_POST) += uart.o COBJS-$(CONFIG_HAS_POST) += watchdog.o diff --git a/post/cpu/ppc4xx/ocm.c b/post/cpu/ppc4xx/ocm.c new file mode 100644 index 0000000..88aa93e --- /dev/null +++ b/post/cpu/ppc4xx/ocm.c @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2008 Ilya Yanok, EmCraft Systems, yanok@emcraft.com + * + * Developed for DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +/* + * This test attempts to verify on-chip memory (OCM). Result is written + * to the scratch register and if test succeed it won't be run till next + * power on. + */ + +#include <post.h> + +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define OCM_TEST_PATTERN1 0x55555555 +#define OCM_TEST_PATTERN2 0xAAAAAAAA + +#if CONFIG_POST & CFG_POST_OCM + +static uint ocm_status_read(void) +{ + return in_be32((void *)CFG_OCM_STATUS_ADDR) & + CFG_OCM_STATUS_MASK; +} + +static void ocm_status_write(uint value) +{ + out_be32((void *)CFG_OCM_STATUS_ADDR, value | + (in_be32((void *)CFG_OCM_STATUS_ADDR) & + ~CFG_OCM_STATUS_MASK)); +} + +static inline int ocm_test_word(uint value, uint *address) +{ + uint read_value; + + *address = value; + sync(); + read_value = *address; + + return (read_value != value); +} + +int ocm_post_test(int flags) +{ + uint old_value; + int ret = 0; + uint *address = (uint*)CFG_OCM_BASE; + + if (ocm_status_read() == CFG_OCM_STATUS_OK) + return 0; + for (; address < (uint*)(CFG_OCM_BASE + CFG_OCM_SIZE); address++) { + old_value = *address; + if (ocm_test_word(OCM_TEST_PATTERN1, address) || + ocm_test_word(OCM_TEST_PATTERN2, address)) { + ret = 1; + *address = old_value; + printf("OCM POST failed at %p!\n", address); + break; + } + *address = old_value; + } + ocm_status_write(ret ? CFG_OCM_STATUS_FAIL : CFG_OCM_STATUS_OK); + return ret; +} +#endif /* CONFIG_POST & CFG_POST_OCM */ diff --git a/post/post.c b/post/post.c index c016c3a..d31829b 100644 --- a/post/post.c +++ b/post/post.c @@ -238,14 +238,20 @@ static int post_run_single (struct post_test *test, if (test_flags & POST_PREREL) { if ((*test->test) (flags) == 0) post_log_mark_succ ( test->testid ); - else if (test_flags & POST_CRITICAL) - gd->flags |= GD_FLG_POSTFAIL; + else { + if (test_flags & POST_CRITICAL) + gd->flags |= GD_FLG_POSTFAIL; + if (test_flags & POST_STOP) + gd->flags |= GD_FLG_POSTSTOP; + } } else { if ((*test->test) (flags) != 0) { post_log ("FAILED\n"); show_boot_progress (-32); if (test_flags & POST_CRITICAL) gd->flags |= GD_FLG_POSTFAIL; + if (test_flags & POST_STOP) + gd->flags |= GD_FLG_POSTSTOP; } else post_log ("PASSED\n"); @@ -271,6 +277,9 @@ int post_run (char *name, int flags) if (name == NULL) { unsigned int last; + if (gd->flags & GD_FLG_POSTSTOP) + return 0; + if (post_bootmode_get (&last) & POST_POWERTEST) { if (last & POST_FAIL_SAVE) { last &= ~POST_FAIL_SAVE; @@ -285,6 +294,8 @@ int post_run (char *name, int flags) flags | POST_REBOOT, last); for (i = last + 1; i < post_list_size; i++) { + if (gd->flags & GD_FLG_POSTSTOP) + break; post_run_single (post_list + i, test_flags[i], flags, i); @@ -292,6 +303,8 @@ int post_run (char *name, int flags) } } else { for (i = 0; i < post_list_size; i++) { + if (gd->flags & GD_FLG_POSTSTOP) + break; post_run_single (post_list + i, test_flags[i], flags, i); diff --git a/post/tests.c b/post/tests.c index 36473e3..a790c78 100644 --- a/post/tests.c +++ b/post/tests.c @@ -29,6 +29,7 @@ #include <post.h> +extern int ocm_post_test (int flags); extern int cache_post_test (int flags); extern int watchdog_post_test (int flags); extern int i2c_post_test (int flags); @@ -60,6 +61,18 @@ extern void sysmon_reloc (void); struct post_test post_list[] = { +#if CONFIG_POST & CFG_POST_OCM + { + "OCM test", + "ocm", + "This test checks on chip memory (OCM).", + POST_ROM | POST_ALWAYS | POST_PREREL | POST_CRITICAL | POST_STOP, + &ocm_post_test, + NULL, + NULL, + CFG_POST_OCM + }, +#endif #if CONFIG_POST & CFG_POST_CACHE { "Cache test", @@ -270,7 +283,7 @@ struct post_test post_list[] = #if CONFIG_POST & CFG_POST_BSPEC4 CONFIG_POST_BSPEC4, #endif -#if CONFIG_POST & CFG_POST_BSPEC4 +#if CONFIG_POST & CFG_POST_BSPEC5 CONFIG_POST_BSPEC5, #endif }; |