diff options
| -rw-r--r-- | cpu/mpc86xx/cpu.c | 60 | ||||
| -rw-r--r-- | cpu/mpc86xx/cpu_init.c | 8 | ||||
| -rw-r--r-- | cpu/mpc86xx/i2c.c | 34 | ||||
| -rw-r--r-- | cpu/mpc86xx/interrupts.c | 88 | ||||
| -rw-r--r-- | cpu/mpc86xx/pci.c | 77 | ||||
| -rw-r--r-- | cpu/mpc86xx/pcie_indirect.c | 116 | ||||
| -rw-r--r-- | cpu/mpc86xx/speed.c | 14 | ||||
| -rw-r--r-- | cpu/mpc86xx/start.S | 197 | ||||
| -rw-r--r-- | cpu/mpc86xx/traps.c | 89 |
9 files changed, 331 insertions, 352 deletions
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 0e82e74..ddd0ad3 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -38,7 +38,8 @@ extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, #endif -int checkcpu (void) +int +checkcpu(void) { sys_info_t sysinfo; uint pvr, svr; @@ -59,11 +60,11 @@ int checkcpu (void) switch (ver) { case PVR_VER(PVR_86xx): - puts("E600"); - break; + puts("E600"); + break; default: - puts("Unknown"); - break; + puts("Unknown"); + break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); @@ -75,8 +76,8 @@ int checkcpu (void) puts(" System: "); switch (ver) { case SVR_8641: - puts("8641"); - break; + puts("8641"); + break; case SVR_8641D: puts("8641D"); break; @@ -97,10 +98,10 @@ int checkcpu (void) lcrr = CFG_LBC_LCRR; #else { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc= &immap->im_lbc; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; - lcrr = lbc->lcrr; + lcrr = lbc->lcrr; } #endif clkdiv = lcrr & 0x0f; @@ -126,8 +127,10 @@ soft_restart(unsigned long addr) { #ifndef CONFIG_MPC8641HPCN - /* SRR0 has system reset vector, SRR1 has default MSR value */ - /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ + /* + * SRR0 has system reset vector, SRR1 has default MSR value + * rfi restores MSR from SRR1 and sets the PC to the SRR0 value + */ __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); @@ -140,7 +143,7 @@ soft_restart(unsigned long addr) #endif /* !CONFIG_MPC8641HPCN */ - while(1); /* not reached */ + while (1) ; /* not reached */ } @@ -185,16 +188,17 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif /* !CONFIG_MPC8641HPCN */ - while(1); /* not reached */ + while (1) ; /* not reached */ } /* * Get timebase clock frequency */ -unsigned long get_tbclk(void) +unsigned long +get_tbclk(void) { - sys_info_t sys_info; + sys_info_t sys_info; get_sys_info(&sys_info); return (sys_info.freqSystemBus + 3L) / 4L; @@ -210,9 +214,10 @@ watchdog_reset(void) #if defined(CONFIG_DDR_ECC) -void dma_init(void) +void +dma_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; dma->satr0 = 0x00040000; @@ -220,26 +225,28 @@ void dma_init(void) asm("sync; isync"); } -uint dma_check(void) +uint +dma_check(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; volatile uint status = dma->sr0; /* While the channel is busy, spin */ - while((status & 4) == 4) { + while ((status & 4) == 4) { status = dma->sr0; } if (status != 0) { - printf ("DMA Error: status = %x\n", status); + printf("DMA Error: status = %x\n", status); } return status; } -int dma_xfer(void *dest, uint count, void *src) +int +dma_xfer(void *dest, uint count, void *src) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; dma->dar0 = (uint) dest; @@ -256,7 +263,8 @@ int dma_xfer(void *dest, uint count, void *src) #ifdef CONFIG_OF_FLAT_TREE -void ft_cpu_setup(void *blob, bd_t *bd) +void +ft_cpu_setup(void *blob, bd_t *bd) { u32 *p; ulong clock; @@ -292,7 +300,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_MPC86XX_TSEC4) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); - memcpy(p, bd->bi_enet3addr, 6); + memcpy(p, bd->bi_enet3addr, 6); #endif } diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 93b7338..6ed7c37 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -38,11 +38,11 @@ void cpu_init_f(void) { - DECLARE_GLOBAL_DATA_PTR; + DECLARE_GLOBAL_DATA_PTR; volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_lbc_t *memctl = &immap->im_lbc; - /* Pointer is writable since we allocated a register for it */ + /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); /* Clear initial global data */ @@ -104,8 +104,8 @@ void cpu_init_f(void) /* enable the timebase bit in HID0 */ set_hid0(get_hid0() | 0x4000000); - /* enable SYNCBE | ABE bits in HID1 */ - set_hid1(get_hid1() | 0x00000C00); + /* enable SYNCBE | ABE bits in HID1 */ + set_hid1(get_hid1() | 0x00000C00); } /* diff --git a/cpu/mpc86xx/i2c.c b/cpu/mpc86xx/i2c.c index b3ac848..d99ecb9 100644 --- a/cpu/mpc86xx/i2c.c +++ b/cpu/mpc86xx/i2c.c @@ -61,7 +61,7 @@ i2c_init(int speed, int slaveadd) writeb(0x3f, I2CFDR); /* set default filter */ - writeb(0x10,I2CDFSRR); + writeb(0x10, I2CDFSRR); /* write slave address */ writeb(slaveadd, I2CADR); @@ -76,7 +76,7 @@ i2c_init(int speed, int slaveadd) static __inline__ int i2c_wait4bus(void) { - ulong timeval = get_timer (0); + ulong timeval = get_timer(0); while (readb(I2CCSR) & MPC86xx_I2CSR_MBB) { if (get_timer(timeval) > TIMEOUT) { @@ -91,7 +91,7 @@ static __inline__ int i2c_wait(int write) { u32 csr; - ulong timeval = get_timer (0); + ulong timeval = get_timer(0); do { csr = readb(I2CCSR); @@ -105,7 +105,7 @@ i2c_wait(int write) return -1; } - if (!(csr & MPC86xx_I2CSR_MCF)) { + if (!(csr & MPC86xx_I2CSR_MCF)) { debug("i2c_wait: unfinished\n"); return -1; } @@ -123,7 +123,7 @@ i2c_wait(int write) } static __inline__ int -i2c_write_addr (u8 dev, u8 dir, int rsta) +i2c_write_addr(u8 dev, u8 dir, int rsta) { writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX | (rsta ? MPC86xx_I2CCR_RSTA : 0), @@ -138,7 +138,7 @@ i2c_write_addr (u8 dev, u8 dir, int rsta) } static __inline__ int -__i2c_write (u8 *data, int length) +__i2c_write(u8 *data, int length) { int i; @@ -156,7 +156,7 @@ __i2c_write (u8 *data, int length) } static __inline__ int -__i2c_read (u8 *data, int length) +__i2c_read(u8 *data, int length) { int i; @@ -174,8 +174,7 @@ __i2c_read (u8 *data, int length) /* Generate ack on last next to last byte */ if (i == length - 2) writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA - | MPC86xx_I2CCR_TXAK, - I2CCCR); + | MPC86xx_I2CCR_TXAK, I2CCCR); /* Generate stop on last byte */ if (i == length - 1) @@ -188,10 +187,10 @@ __i2c_read (u8 *data, int length) } int -i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) +i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) { int i = 0; - u8 *a = (u8*)&addr; + u8 *a = (u8 *) &addr; if (i2c_wait4bus() < 0) goto exit; @@ -214,10 +213,10 @@ exit: } int -i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) +i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) { int i = 0; - u8 *a = (u8*)&addr; + u8 *a = (u8 *) &addr; if (i2c_wait4bus() < 0) goto exit; @@ -236,7 +235,8 @@ exit: return !(i == length); } -int i2c_probe (uchar chip) +int +i2c_probe(uchar chip) { int tmp; @@ -250,7 +250,8 @@ int i2c_probe (uchar chip) return i2c_read(chip, 0, 1, (char *)&tmp, 1); } -uchar i2c_reg_read (uchar i2c_addr, uchar reg) +uchar +i2c_reg_read(uchar i2c_addr, uchar reg) { char buf[1]; @@ -259,7 +260,8 @@ uchar i2c_reg_read (uchar i2c_addr, uchar reg) return buf[0]; } -void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) +void +i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) { i2c_write(i2c_addr, reg, 1, &val, 1); } diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index a8bcb98..1df6cdc 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -41,7 +41,7 @@ unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */ unsigned long timestamp; -static __inline__ unsigned long get_msr (void) +static __inline__ unsigned long get_msr(void) { unsigned long msr; @@ -50,12 +50,12 @@ static __inline__ unsigned long get_msr (void) return msr; } -static __inline__ void set_msr (unsigned long msr) +static __inline__ void set_msr(unsigned long msr) { asm volatile ("mtmsr %0"::"r" (msr)); } -static __inline__ unsigned long get_dec (void) +static __inline__ unsigned long get_dec(void) { unsigned long val; @@ -64,58 +64,58 @@ static __inline__ unsigned long get_dec (void) return val; } - -static __inline__ void set_dec (unsigned long val) +static __inline__ void set_dec(unsigned long val) { if (val) asm volatile ("mtdec %0"::"r" (val)); } /* interrupt is not supported yet */ -int interrupt_init_cpu (unsigned *decrementer_count) +int interrupt_init_cpu(unsigned *decrementer_count) { return 0; } - -int interrupt_init (void) +int interrupt_init(void) { int ret; /* call cpu specific function from $(CPU)/interrupts.c */ - ret = interrupt_init_cpu (&decrementer_count); + ret = interrupt_init_cpu(&decrementer_count); if (ret) return ret; - decrementer_count = get_tbclk()/CFG_HZ; - debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count); + decrementer_count = get_tbclk() / CFG_HZ; + debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", + (get_tbclk() / 1000000), + decrementer_count); - set_dec (decrementer_count); + set_dec(decrementer_count); - set_msr (get_msr () | MSR_EE); + set_msr(get_msr() | MSR_EE); - debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec()); + debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", + get_msr(), + get_dec()); return 0; } - -void enable_interrupts (void) +void enable_interrupts(void) { - set_msr (get_msr () | MSR_EE); + set_msr(get_msr() | MSR_EE); } /* returns flag if MSR_EE was set before */ -int disable_interrupts (void) +int disable_interrupts(void) { - ulong msr = get_msr (); + ulong msr = get_msr(); - set_msr (msr & ~MSR_EE); + set_msr(msr & ~MSR_EE); return (msr & MSR_EE) != 0; } - void increment_timestamp(void) { timestamp++; @@ -126,52 +126,49 @@ void increment_timestamp(void) * with interrupts disabled. * Trivial implementation - no need to be really accurate. */ -void -timer_interrupt_cpu (struct pt_regs *regs) +void timer_interrupt_cpu(struct pt_regs *regs) { /* nothing to do here */ } - -void timer_interrupt (struct pt_regs *regs) +void timer_interrupt(struct pt_regs *regs) { /* call cpu specific function from $(CPU)/interrupts.c */ - timer_interrupt_cpu (regs); + timer_interrupt_cpu(regs); timestamp++; ppcDcbf(×tamp); /* Restore Decrementer Count */ - set_dec (decrementer_count); + set_dec(decrementer_count); #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0) - WATCHDOG_RESET (); -#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ + WATCHDOG_RESET(); +#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ #ifdef CONFIG_STATUS_LED - status_led_tick (timestamp); + status_led_tick(timestamp); #endif /* CONFIG_STATUS_LED */ #ifdef CONFIG_SHOW_ACTIVITY - board_show_activity (timestamp); + board_show_activity(timestamp); #endif /* CONFIG_SHOW_ACTIVITY */ - } -void reset_timer (void) +void reset_timer(void) { timestamp = 0; } -ulong get_timer (ulong base) +ulong get_timer(ulong base) { return timestamp - base; } -void set_timer (ulong t) +void set_timer(ulong t) { timestamp = t; } @@ -180,24 +177,20 @@ void set_timer (ulong t) * Install and free a interrupt handler. Not implemented yet. */ -void -irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) +void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) { } -void -irq_free_handler(int vec) +void irq_free_handler(int vec) { } - /* * irqinfo - print information about PCI devices,not implemented. */ -int -do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - printf ("\nInterrupt-unsupported:\n"); + printf("\nInterrupt-unsupported:\n"); return 0; } @@ -205,14 +198,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * Handle external interrupts */ -void -external_interrupt(struct pt_regs *regs) +void external_interrupt(struct pt_regs *regs) { puts("external_interrupt (oops!)\n"); } - - - - - - diff --git a/cpu/mpc86xx/pci.c b/cpu/mpc86xx/pci.c index deb66aa..b86548d 100644 --- a/cpu/mpc86xx/pci.c +++ b/cpu/mpc86xx/pci.c @@ -34,7 +34,7 @@ void pci_mpc86xx_init(struct pci_controller *hose) { - volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile ccsr_pex_t *pcie1 = &immap->im_pex1; u16 temp16; u32 temp32; @@ -46,62 +46,69 @@ pci_mpc86xx_init(struct pci_controller *hose) uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - if ((io_sel ==2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || - io_sel == 7 || io_sel == 0xf) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ - printf ("PCI-EXPRESS 1: Configured as %s \n", - pcie1_agent ? "Agent" : "Host"); - if(pcie1_agent) return; /*Don't scan bus when configured as agent*/ - printf (" Scanning PCIE bus"); - debug("0x%08x=0x%08x ", &pcie1->pme_msg_det,pcie1->pme_msg_det); + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || + io_sel == 7 || io_sel == 0xf) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + printf("PCI-EXPRESS 1: Configured as %s \n", + pcie1_agent ? "Agent" : "Host"); + if (pcie1_agent) + return; /*Don't scan bus when configured as agent */ + printf(" Scanning PCIE bus"); + debug("0x%08x=0x%08x ", + &pcie1->pme_msg_det, + pcie1->pme_msg_det); if (pcie1->pme_msg_det) { pcie1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x", - pcie1->pme_msg_det); + debug(" with errors. Clearing. Now 0x%08x", + pcie1->pme_msg_det); } - debug ("\n"); - } - else{ + debug("\n"); + } else { printf("PCI-EXPRESS 1 disabled!\n"); return; } - /*set first_bus=0 only skipped B0:D0:F0 which is + /* + * Set first_bus=0 only skipped B0:D0:F0 which is * a reserved device in M1575, but make it easy for * most of the scan process. */ hose->first_busno = 0x00; hose->last_busno = 0xfe; - pcie_setup_indirect(hose, - (CFG_IMMR+0x8000), - (CFG_IMMR+0x8004)); + pcie_setup_indirect(hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004)); - pci_hose_read_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, &temp16); + pci_hose_read_config_word(hose, + PCI_BDF(0, 0, 0), PCI_COMMAND, &temp16); temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, temp16); + PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_hose_write_config_word(hose, + PCI_BDF(0, 0, 0), PCI_COMMAND, temp16); - pci_hose_write_config_word(hose,PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_word(hose, PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, + PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80); - pci_hose_read_config_dword(hose, PCI_BDF(0,0,0), PCI_PRIMARY_BUS, &temp32); + pci_hose_read_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, + &temp32); temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16); - pci_hose_write_config_dword(hose, PCI_BDF(0,0,0), PCI_PRIMARY_BUS, temp32); + pci_hose_write_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, + temp32); pcie1->powar1 = 0; pcie1->powar2 = 0; pcie1->piwar1 = 0; pcie1->piwar1 = 0; - pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcie1->powar1 = 0x8004401c; /* 512M MEM space */ - pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcie1->potear1 = 0x00000000; + pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcie1->powar1 = 0x8004401c; /* 512M MEM space */ + pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcie1->potear1 = 0x00000000; - pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; - pcie1->powar2 = 0x80088017; /* 16M IO space */ - pcie1->potar2 = 0x00000000; - pcie1->potear2 = 0x00000000; + pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcie1->powar2 = 0x80088017; /* 16M IO space */ + pcie1->potar2 = 0x00000000; + pcie1->potear2 = 0x00000000; pcie1->pitar1 = 0x00000000; pcie1->piwbar1 = 0x00000000; @@ -131,9 +138,9 @@ pci_mpc86xx_init(struct pci_controller *hose) pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); - debug("pcie_mpc86xx_init: last_busno %x\n",hose->last_busno); - debug("pcie_mpc86xx init: current_busno %x\n ",hose->current_busno); + debug("pcie_mpc86xx_init: last_busno %x\n", hose->last_busno); + debug("pcie_mpc86xx init: current_busno %x\n ", hose->current_busno); printf("....PCIE1 scan & enumeration done\n"); } -#endif /* CONFIG_PCI */ +#endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/pcie_indirect.c b/cpu/mpc86xx/pcie_indirect.c index 6c63b38..b00ad76 100644 --- a/cpu/mpc86xx/pcie_indirect.c +++ b/cpu/mpc86xx/pcie_indirect.c @@ -28,8 +28,10 @@ static int indirect_read_config_pcie(struct pci_controller *hose, - pci_dev_t dev, int offset, - int len,u32 *val) + pci_dev_t dev, + int offset, + int len, + u32 *val) { int bus = PCI_BUS(dev); @@ -37,10 +39,12 @@ indirect_read_config_pcie(struct pci_controller *hose, u32 temp; PEX_FIX; - if( bus == 0xff) { - PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); - }else { - PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); + if (bus == 0xff) { + PCI_CFG_OUT(hose->cfg_addr, + dev | (offset & 0xfc) | 0x80000001); + } else { + PCI_CFG_OUT(hose->cfg_addr, + dev | (offset & 0xfc) | 0x80000000); } /* * Note: the caller has already checked that offset is @@ -49,13 +53,13 @@ indirect_read_config_pcie(struct pci_controller *hose, /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ cfg_data = hose->cfg_data; PEX_FIX; - temp = in_le32((u32 *)cfg_data); + temp = in_le32((u32 *) cfg_data); switch (len) { case 1: - *val = (temp >> (((offset & 3))*8)) & 0xff; + *val = (temp >> (((offset & 3)) * 8)) & 0xff; break; case 2: - *val = (temp >> (((offset & 3))*8)) & 0xffff; + *val = (temp >> (((offset & 3)) * 8)) & 0xffff; break; default: *val = temp; @@ -67,20 +71,22 @@ indirect_read_config_pcie(struct pci_controller *hose, static int indirect_write_config_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - int len, - u32 val) + pci_dev_t dev, + int offset, + int len, + u32 val) { int bus = PCI_BUS(dev); volatile unsigned char *cfg_data; u32 temp; PEX_FIX; - if( bus == 0xff) { - PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); - }else { - PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); + if (bus == 0xff) { + PCI_CFG_OUT(hose->cfg_addr, + dev | (offset & 0xfc) | 0x80000001); + } else { + PCI_CFG_OUT(hose->cfg_addr, + dev | (offset & 0xfc) | 0x80000000); } /* @@ -92,23 +98,23 @@ indirect_write_config_pcie(struct pci_controller *hose, switch (len) { case 1: PEX_FIX; - temp = in_le32((u32 *)cfg_data); + temp = in_le32((u32 *) cfg_data); temp = (temp & ~(0xff << ((offset & 3) * 8))) | - (val << ((offset & 3) * 8)); + (val << ((offset & 3) * 8)); PEX_FIX; - out_le32((u32 *)cfg_data, temp); + out_le32((u32 *) cfg_data, temp); break; case 2: PEX_FIX; - temp = in_le32((u32 *)cfg_data); + temp = in_le32((u32 *) cfg_data); temp = (temp & ~(0xffff << ((offset & 3) * 8))); - temp |= (val << ((offset & 3) * 8)) ; + temp |= (val << ((offset & 3) * 8)); PEX_FIX; - out_le32((u32 *)cfg_data, temp); + out_le32((u32 *) cfg_data, temp); break; default: PEX_FIX; - out_le32((u32 *)cfg_data, val); + out_le32((u32 *) cfg_data, val); break; } PEX_FIX; @@ -117,68 +123,66 @@ indirect_write_config_pcie(struct pci_controller *hose, static int indirect_read_config_byte_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u8 *val) + pci_dev_t dev, + int offset, + u8 *val) { u32 val32; - indirect_read_config_pcie(hose,dev,offset,1,&val32); - *val = (u8)val32; + indirect_read_config_pcie(hose, dev, offset, 1, &val32); + *val = (u8) val32; return 0; } static int indirect_read_config_word_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u16 *val) + pci_dev_t dev, + int offset, + u16 *val) { u32 val32; - indirect_read_config_pcie(hose,dev,offset,2,&val32); - *val = (u16)val32; + indirect_read_config_pcie(hose, dev, offset, 2, &val32); + *val = (u16) val32; return 0; } static int indirect_read_config_dword_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u32 *val) + pci_dev_t dev, + int offset, + u32 *val) { - return indirect_read_config_pcie(hose,dev, offset,4,val); + return indirect_read_config_pcie(hose, dev, offset, 4, val); } static int indirect_write_config_byte_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u8 val) + pci_dev_t dev, + int offset, + u8 val) { - return indirect_write_config_pcie(hose,dev, offset,1,(u32)val); + return indirect_write_config_pcie(hose, dev, offset, 1, (u32) val); } static int indirect_write_config_word_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - unsigned short val) + pci_dev_t dev, + int offset, + unsigned short val) { - return indirect_write_config_pcie(hose,dev, offset,2,(u32)val); + return indirect_write_config_pcie(hose, dev, offset, 2, (u32) val); } static int indirect_write_config_dword_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u32 val) + pci_dev_t dev, + int offset, + u32 val) { - return indirect_write_config_pcie(hose,dev, offset,4,val); + return indirect_write_config_pcie(hose, dev, offset, 4, val); } void -pcie_setup_indirect(struct pci_controller* hose, - u32 cfg_addr, - u32 cfg_data) +pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) { pci_set_ops(hose, indirect_read_config_byte_pcie, @@ -188,8 +192,8 @@ pcie_setup_indirect(struct pci_controller* hose, indirect_write_config_word_pcie, indirect_write_config_dword_pcie); - hose->cfg_addr = (unsigned int *) cfg_addr; - hose->cfg_data = (unsigned char *) cfg_data; + hose->cfg_addr = (unsigned int *)cfg_addr; + hose->cfg_data = (unsigned char *)cfg_data; } -#endif /* CONFIG_PCI */ +#endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index e130705..312ca12 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -30,16 +30,16 @@ #include <asm/processor.h> -void get_sys_info (sys_info_t *sysInfo) +void get_sys_info(sys_info_t *sysInfo) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; uint plat_ratio, e600_ratio; plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; - switch(plat_ratio) { + switch (plat_ratio) { case 0x0: sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ; break; @@ -56,7 +56,7 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; break; default: - sysInfo->freqSystemBus = 0; + sysInfo->freqSystemBus = 0; break; } @@ -68,19 +68,19 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus; break; case 0x19: - sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus/2; + sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus / 2; break; case 0x20: sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; break; case 0x39: - sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus/2; + sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus / 2; break; case 0x28: sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus; break; case 0x1d: - sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus/2; + sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus / 2; break; default: sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 25687f8..e537dcb 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -74,7 +74,7 @@ * r4 - 2nd arg to board_init(): boot flag */ .text - .long 0x27051956 /* U-Boot Magic Number */ + .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: .ascii U_BOOT_VERSION @@ -92,7 +92,7 @@ _start: .globl _start_warm _start_warm: - li r21, BOOTFLAG_WARM /* Software reboot */ + li r21, BOOTFLAG_WARM /* Software reboot */ b boot_warm sync @@ -183,7 +183,7 @@ boot_cold: boot_warm: /* if this is a multi-core system we need to check which cpu - * this is, if it is not cpu 0 send the cpu to the linux reset + * this is, if it is not cpu 0 send the cpu to the linux reset * vector */ #if (CONFIG_NUM_CPUS > 1) mfspr r0, MSSCR0 @@ -194,7 +194,7 @@ boot_warm: bl secondary_cpu_setup #endif - + /* disable everything */ 1: li r0, 0 mtspr HID0, r0 @@ -202,17 +202,17 @@ boot_warm: mtmsr 0 bl invalidate_bats sync - + #ifdef CFG_L2 /* init the L2 cache */ addis r3, r0, L2_INIT@h ori r3, r3, L2_INIT@l - mtspr l2cr, r3 + mtspr l2cr, r3 /* invalidate the L2 cache */ bl l2cache_invalidate sync #endif - + /* * Calculate absolute address in FLASH and jump there *------------------------------------------------------*/ @@ -231,7 +231,7 @@ in_flash: /* enable extended addressing */ bl enable_ext_addr - + /* setup the bats */ bl setup_bats sync @@ -240,7 +240,7 @@ in_flash: /* setup ccsrbar */ bl setup_ccsrbar #endif - + /* Fix for SMP linux - Changing arbitration to round-robin */ lis r3, CFG_CCSRBAR@h ori r3, r3, 0x1000 @@ -279,7 +279,7 @@ in_flash: stw r4, 0(r3) sync #endif -#if 1 +#if 1 /* make sure timer enabled in guts register too */ lis r3, CFG_CCSRBAR@h oris r3,r3, 0xE @@ -289,7 +289,7 @@ in_flash: ori r5,r5,0x5FFF and r4,r4,r5 stw r4,0(r3) -#endif +#endif /* * Cache must be enabled here for stack-in-cache trick. * This means we need to enable the BATS. @@ -303,13 +303,13 @@ in_flash: /* enable and invalidate the data cache */ /* bl l1dcache_enable */ - bl dcache_enable + bl dcache_enable sync #if 1 bl icache_enable #endif - + #ifdef CFG_INIT_RAM_LOCK bl lock_ram_in_cache sync @@ -330,7 +330,7 @@ in_flash: bl cpu_init_f sync -#ifdef RUN_DIAG +#ifdef RUN_DIAG /* Sri: Code to run the diagnostic automatically */ @@ -361,9 +361,9 @@ in_flash: /* Branch to diagnostic */ blr - -diag_done: -#endif + +diag_done: +#endif /* bl l2cache_enable*/ mr r3, r21 @@ -377,7 +377,7 @@ diag_done: .globl invalidate_bats invalidate_bats: - + /* invalidate BATs */ mtspr IBAT0U, r0 mtspr IBAT1U, r0 @@ -401,12 +401,12 @@ invalidate_bats: isync sync blr - - + + /* setup_bats - set them up to some initial state */ .globl setup_bats setup_bats: - + addis r0, r0, 0x0000 /* IBAT 0 */ @@ -553,7 +553,7 @@ setup_bats: mtspr DBAT7U, r3 isync -1: +1: addis r3, 0, 0x0000 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */ isync @@ -662,142 +662,140 @@ get_svr: blr -/*------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: in8 + * Description: Input 8 bits + */ .globl in8 in8: lbz r3,0x0000(r3) blr -/*------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: out8 + * Description: Output 8 bits + */ .globl out8 out8: stb r4,0x0000(r3) blr -/*------------------------------------------------------------------------------- */ -/* Function: out16 */ -/* Description: Output 16 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: out16 + * Description: Output 16 bits + */ .globl out16 out16: sth r4,0x0000(r3) blr -/*------------------------------------------------------------------------------- */ -/* Function: out16r */ -/* Description: Byte reverse and output 16 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: out16r + * Description: Byte reverse and output 16 bits + */ .globl out16r out16r: sthbrx r4,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: out32 + * Description: Output 32 bits + */ .globl out32 out32: stw r4,0x0000(r3) blr -/*------------------------------------------------------------------------------- */ -/* Function: out32r */ -/* Description: Byte reverse and output 32 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: out32r + * Description: Byte reverse and output 32 bits + */ .globl out32r out32r: stwbrx r4,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: in16 */ -/* Description: Input 16 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: in16 + * Description: Input 16 bits + */ .globl in16 in16: lhz r3,0x0000(r3) blr -/*------------------------------------------------------------------------------- */ -/* Function: in16r */ -/* Description: Input 16 bits and byte reverse */ -/*------------------------------------------------------------------------------- */ +/* + * Function: in16r + * Description: Input 16 bits and byte reverse + */ .globl in16r in16r: lhbrx r3,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: in32 + * Description: Input 32 bits + */ .globl in32 in32: lwz 3,0x0000(3) blr -/*------------------------------------------------------------------------------- */ -/* Function: in32r */ -/* Description: Input 32 bits and byte reverse */ -/*------------------------------------------------------------------------------- */ +/* + * Function: in32r + * Description: Input 32 bits and byte reverse + */ .globl in32r in32r: lwbrx r3,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ +/* + * Function: ppcDcbf + * Description: Data Cache block flush + * Input: r3 = effective address + * Output: none. + */ .globl ppcDcbf ppcDcbf: dcbf r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ +/* + * Function: ppcDcbi + * Description: Data Cache block Invalidate + * Input: r3 = effective address + * Output: none. + */ .globl ppcDcbi ppcDcbi: dcbi r0,r3 blr -/*-------------------------------------------------------------------------- +/* * Function: ppcDcbz * Description: Data Cache block zero. * Input: r3 = effective address * Output: none. - *-------------------------------------------------------------------------- */ - + */ .globl ppcDcbz ppcDcbz: dcbz r0,r3 blr -/*-------------------------------------------------------------------------- */ -/* Function: ppcSync */ -/* Description: Processor Synchronize */ -/* Input: none. */ -/* Output: none. */ -/*-------------------------------------------------------------------------- */ +/* + * Function: ppcSync + * Description: Processor Synchronize + * Input: none. + * Output: none. + */ .globl ppcSync ppcSync: sync blr - -/*-----------------------------------------------------------------------*/ + /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -1062,7 +1060,7 @@ enable_ext_addr: #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) .globl setup_ccsrbar -setup_ccsrbar: +setup_ccsrbar: /* Special sequence needed to update CCSRBAR itself */ lis r4, CFG_CCSRBAR_DEFAULT@h ori r4, r4, CFG_CCSRBAR_DEFAULT@l @@ -1081,10 +1079,10 @@ setup_ccsrbar: lis r3, CFG_CCSRBAR@h lwz r5, CFG_CCSRBAR@l(r3) isync - + blr #endif - + #ifdef CFG_INIT_RAM_LOCK lock_ram_in_cache: /* Allocate Initial RAM in data cache. @@ -1120,7 +1118,7 @@ lock_ram_in_cache: isync blr #endif - + .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ @@ -1146,7 +1144,7 @@ unlock_ram_in_cache: sync blr #endif -#if 0 +#if 0 /* Unlock the first way of the data cache */ mfspr r0, LDSTCR li r3,0x0080 @@ -1173,16 +1171,16 @@ unlock_ram_in_cache: * from Linux. We'll do some basic cpu init and then pass * it to the Linux Reset Vector. * Sri: Much of this initialization is not required. Linux - * rewrites the bats, and the sprs and also enables the L1 cache. + * rewrites the bats, and the sprs and also enables the L1 cache. */ #if (CONFIG_NUM_CPUS > 1) .globl secondary_cpu_setup -secondary_cpu_setup: +secondary_cpu_setup: /* Do only core setup on all cores except cpu0 */ bl invalidate_bats sync bl enable_ext_addr - + #ifdef CFG_L2 /* init the L2 cache */ addis r3, r0, L2_INIT@h @@ -1204,27 +1202,26 @@ secondary_cpu_setup: /* enable and invalidate the instruction cache*/ bl icache_enable sync - /* TBEN in HID0 */ mfspr r4, HID0 - oris r4, r4, 0x0400 + oris r4, r4, 0x0400 mtspr HID0, r4 sync isync - + /*SYNCBE|ABE in HID1*/ mfspr r4, HID1 - ori r4, r4, 0x0C00 + ori r4, r4, 0x0C00 mtspr HID1, r4 sync isync - + lis r3, CONFIG_LINUX_RESET_VEC@h ori r3, r3, CONFIG_LINUX_RESET_VEC@l mtlr r3 blr - - /* Never Returns, Running in Linux Now */ + + /* Never Returns, Running in Linux Now */ #endif diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index 8113dfb..8ea14e5 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -57,21 +57,22 @@ print_backtrace(unsigned long *sp) printf("Call backtrace: "); while (sp) { - if ((uint)sp > END_OF_MEM) + if ((uint) sp > END_OF_MEM) break; i = sp[1]; if (cnt++ % 7 == 0) printf("\n"); printf("%08lX ", i); - if (cnt > 32) break; + if (cnt > 32) + break; sp = (unsigned long *)*sp; } printf("\n"); } void -show_regs(struct pt_regs * regs) +show_regs(struct pt_regs *regs) { int i; @@ -80,21 +81,19 @@ show_regs(struct pt_regs * regs) regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); printf("MSR: %08lx EE: %01x PR: %01x FP:" " %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); + regs->msr, regs->msr & MSR_EE ? 1 : 0, + regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0, + regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0, + regs->msr & MSR_DR ? 1 : 0); printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) { printf("GPR%02d: ", i); } printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { + if ((i % 8) == 7) { printf("\n"); } } @@ -106,7 +105,7 @@ _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); + panic("Exception in kernel pc %lx signal %d", regs->nip, signr); } void @@ -124,25 +123,25 @@ MachineCheckException(struct pt_regs *regs) } #if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif printf("Machine check in kernel mode.\n"); printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): + printf("regs %p ", regs); + switch (regs->msr & 0x000F0000) { + case (0x80000000 >> 12): printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); + "with mmu off\n"); break; - case (0x80000000>>13): + case (0x80000000 >> 13): printf("Transfer error ack signal\n"); break; - case (0x80000000>>14): + case (0x80000000 >> 14): printf("Data parity signal\n"); break; - case (0x80000000>>15): + case (0x80000000 >> 15): printf("Address parity signal\n"); break; default: @@ -157,7 +156,7 @@ void AlignmentException(struct pt_regs *regs) { #if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif show_regs(regs); @@ -172,17 +171,17 @@ ProgramCheckException(struct pt_regs *regs) int i, j; #if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif show_regs(regs); - p = (unsigned char *) ((unsigned long)p & 0xFFFFFFE0); + p = (unsigned char *)((unsigned long)p & 0xFFFFFFE0); p -= 32; - for (i = 0; i < 256; i+=16) { - printf("%08x: ", (unsigned int)p+i); + for (i = 0; i < 256; i += 16) { + printf("%08x: ", (unsigned int)p + i); for (j = 0; j < 16; j++) { - printf("%02x ", p[i+j]); + printf("%02x ", p[i + j]); } printf("\n"); } @@ -195,7 +194,7 @@ void SoftEmuException(struct pt_regs *regs) { #if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif show_regs(regs); @@ -203,12 +202,11 @@ SoftEmuException(struct pt_regs *regs) panic("Software Emulation Exception"); } - void UnknownException(struct pt_regs *regs) { #if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", @@ -216,36 +214,13 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. +/* + * Probe an address by reading. + * If not present, return -1, + * otherwise return 0. */ int addr_probe(uint *addr) { -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif return 0; } - - - - - - |