diff options
| -rw-r--r-- | board/spc1920/hpi.c | 1 | ||||
| -rw-r--r-- | board/spc1920/spc1920.c | 14 | ||||
| -rw-r--r-- | include/configs/spc1920.h | 11 |
3 files changed, 17 insertions, 9 deletions
diff --git a/board/spc1920/hpi.c b/board/spc1920/hpi.c index 687c170..05dd8bd 100644 --- a/board/spc1920/hpi.c +++ b/board/spc1920/hpi.c @@ -40,7 +40,6 @@ #include "pld.h" #include "hpi.h" -#include "spc1920.h" /* led function */ #define _NOT_USED_ 0xFFFFFFFF diff --git a/board/spc1920/spc1920.c b/board/spc1920/spc1920.c index d0a6ff1..d69b915 100644 --- a/board/spc1920/spc1920.c +++ b/board/spc1920/spc1920.c @@ -220,10 +220,20 @@ int board_early_init_f(void) immap->im_ioport.iop_pdpar &= ~(0x0040); immap->im_ioport.iop_pddir |= 0x0040; immap->im_ioport.iop_pddat |= 0x0040; - #endif - /* Enable PD10 (COM2_EN) */ + /* + * Enable console on SMC1. This requires turning on + * the com2_en signal and SMC1_DISABLE + */ + + /* SMC1_DISABLE: PB17 */ + immap->im_cpm.cp_pbodr &= ~0x4000; + immap->im_cpm.cp_pbpar &= ~0x4000; + immap->im_cpm.cp_pbdir |= 0x4000; + immap->im_cpm.cp_pbdat &= ~0x4000; + + /* COM2_EN: PD10 */ immap->im_ioport.iop_pdpar &= ~0x0020; immap->im_ioport.iop_pddir &= ~0x4000; immap->im_ioport.iop_pddir |= 0x0020; diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h index c6b4d30..dcff8a6 100644 --- a/include/configs/spc1920.h +++ b/include/configs/spc1920.h @@ -51,12 +51,12 @@ #define CFG_8xx_CPUCLK_MIN 40000000 #define CFG_8xx_CPUCLK_MAX 133000000 -#define CFG_RESET_ADDRESS 0xf8000000 +#define CFG_RESET_ADDRESS 0xC0000000 #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_LAST_STAGE_INIT - -#if 1 +#if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ @@ -89,7 +89,6 @@ | CFG_CMD_JFFS2 \ | CFG_CMD_PING \ | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ | CFG_CMD_I2C \ | CFG_CMD_MII) /* & ~( CFG_CMD_NET)) */ @@ -248,7 +247,7 @@ *----------------------------------------------------------------------- * PCMCIA config., multi-function pin tri-state */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#define CFG_SIUMCR (SIUMCR_FRC) /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 @@ -393,7 +392,7 @@ #endif /* CONFIG_SPC1920_HPI_TEST */ /* - * PLD CS5 + * PLD CS5 */ #define CFG_SPC1920_PLD_BASE 0x80000000 #define CFG_PRELIM_OR5_AM 0xfff00000 |