summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--board/freescale/mpc8569mds/bcsr.c15
-rw-r--r--board/freescale/mpc8569mds/bcsr.h2
-rw-r--r--board/freescale/mpc8569mds/mpc8569mds.c96
-rw-r--r--include/configs/MPC8569MDS.h38
4 files changed, 144 insertions, 7 deletions
diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c
index 17c8478..a936edb 100644
--- a/board/freescale/mpc8569mds/bcsr.c
+++ b/board/freescale/mpc8569mds/bcsr.c
@@ -35,8 +35,9 @@ void disable_8569mds_flash_write()
clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
}
-void enable_8569mds_qe_mdio()
+void enable_8569mds_qe_uec()
{
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
@@ -45,6 +46,18 @@ void enable_8569mds_qe_mdio()
BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+ /* Set UCC1-4 working at RMII mode */
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
+ BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
+ BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+ BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+ BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
+#endif
}
void disable_8569mds_brd_eeprom_write_protect()
diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h
index 8efe9bd..e5d63c7 100644
--- a/board/freescale/mpc8569mds/bcsr.h
+++ b/board/freescale/mpc8569mds/bcsr.h
@@ -76,7 +76,7 @@
void enable_8569mds_flash_write(void);
void disable_8569mds_flash_write(void);
-void enable_8569mds_qe_mdio(void);
+void enable_8569mds_qe_uec(void);
void disable_8569mds_brd_eeprom_write_protect(void);
#endif /* __BCSR_H_ */
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 387ecad..1e7526a 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -47,6 +47,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
/* QE_MUX_MDIO */
{2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
/* UCC_1_RGMII */
{2, 11, 2, 0, 1}, /* CLK12 */
{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
@@ -107,6 +108,44 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
{2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+ /* UCC_1_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
+ {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
+
+ /* UCC_2_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
+ {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
+ {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
+ {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
+ {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
+ {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
+
+ /* UCC_3_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
+ {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
+ {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
+ {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
+ {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
+ {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
+
+ /* UCC_4_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
+ {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
+ {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
+ {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
+ {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
+ {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
+#endif
+
/* UART1 is muxed with QE PortF bit [9-12].*/
{5, 12, 2, 0, 3}, /* UART1_SIN */
{5, 9, 1, 0, 3}, /* UART1_SOUT */
@@ -128,7 +167,7 @@ int board_early_init_f (void)
enable_8569mds_flash_write();
#ifdef CONFIG_QE
- enable_8569mds_qe_mdio();
+ enable_8569mds_qe_uec();
#endif
#if CONFIG_SYS_I2C2_OFFSET
@@ -350,6 +389,61 @@ pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
+#if defined(CONFIG_SYS_UCC_RMII_MODE)
+ int nodeoff, off, err;
+ unsigned int val;
+ const u32 *ph;
+ const u32 *index;
+
+ /* fixup device tree for supporting rmii mode */
+ nodeoff = -1;
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
+ "ucc_geth")) >= 0) {
+ err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
+ "clk16");
+ if (err < 0) {
+ printf("WARNING: could not set tx-clock-name %s.\n",
+ fdt_strerror(err));
+ break;
+ }
+
+ err = fdt_setprop_string(blob, nodeoff, "phy-connection-type",
+ "rmii");
+ if (err < 0) {
+ printf("WARNING: could not set phy-connection-type "
+ "%s.\n", fdt_strerror(err));
+ break;
+ }
+
+ index = fdt_getprop(blob, nodeoff, "cell-index", 0);
+ if (index == NULL) {
+ printf("WARNING: could not get cell-index of ucc\n");
+ break;
+ }
+
+ ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
+ if (ph == NULL) {
+ printf("WARNING: could not get phy-handle of ucc\n");
+ break;
+ }
+
+ off = fdt_node_offset_by_phandle(blob, *ph);
+ if (off < 0) {
+ printf("WARNING: could not get phy node %s.\n",
+ fdt_strerror(err));
+ break;
+ }
+
+ val = 0x7 + *index; /* RMII phy address starts from 0x8 */
+
+ err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
+ if (err < 0) {
+ printf("WARNING: could not set reg for phy-handle "
+ "%s.\n", fdt_strerror(err));
+ break;
+ }
+ }
+#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCIE1
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 259cd57..c97ea2f 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -282,6 +282,8 @@ extern unsigned long get_clock_freq(void);
/*
* QE UEC ethernet configuration
*/
+#define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
+#undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
#define CONFIG_UEC_ETH
@@ -294,11 +296,18 @@ extern unsigned long get_clock_freq(void);
#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 7
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
-#endif
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
+#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH1 */
#define CONFIG_UEC_ETH2 /* GETH2 */
#define CONFIG_HAS_ETH1
@@ -306,11 +315,18 @@ extern unsigned long get_clock_freq(void);
#ifdef CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 1
#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
-#endif
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
+#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
+#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH2 */
#define CONFIG_UEC_ETH3 /* GETH3 */
#define CONFIG_HAS_ETH2
@@ -318,11 +334,18 @@ extern unsigned long get_clock_freq(void);
#ifdef CONFIG_UEC_ETH3
#define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC3_PHY_ADDR 2
#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID
-#endif
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
+#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
+#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH3 */
#define CONFIG_UEC_ETH4 /* GETH4 */
#define CONFIG_HAS_ETH3
@@ -330,11 +353,18 @@ extern unsigned long get_clock_freq(void);
#ifdef CONFIG_UEC_ETH4
#define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC4_PHY_ADDR 3
#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID
-#endif
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
+#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
+#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH4 */
#endif /* CONFIG_QE */
#if defined(CONFIG_PCI)
generated by cgit v1.1 at 2024-11-29 14:22:25 +0000