diff options
| -rw-r--r-- | cpu/mpc85xx/cpu_init.c | 2 | ||||
| -rw-r--r-- | cpu/mpc85xx/mp.c | 6 | ||||
| -rw-r--r-- | cpu/mpc85xx/spd_sdram.c | 2 |
3 files changed, 7 insertions, 3 deletions
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index fce0c48..e3240b5 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -272,7 +272,7 @@ int cpu_init_r(void) uint l2srbar; svr = get_svr(); - ver = SVR_VER(svr); + ver = SVR_SOC_VER(svr); asm("msync;isync"); cache_ctl = l2cache->l2ctl; diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 7b10fba..e733f7b 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -154,7 +154,7 @@ static void pq3_mp_up(unsigned long bootpg) while (timeout) { int i; for (i = 1; i < CONFIG_NR_CPUS; i++) { - if (table[i * NUM_BOOT_ENTRY]) + if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) cpu_up_mask |= (1 << i); }; @@ -165,6 +165,10 @@ static void pq3_mp_up(unsigned long bootpg) timeout--; } + if (timeout == 0) + printf("CPU up timeout. CPU up mask is %x should be %x\n", + cpu_up_mask, up); + /* enable time base at the platform */ if (whoami) devdisr |= MPC85xx_DEVDISR_TB1; diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index abc63c4..435458a 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -306,7 +306,7 @@ spd_sdram(void) * Adjust DDR II IO voltage biasing. * Only 8548 rev 1 needs the fix */ - if ((SVR_VER(get_svr()) == SVR_8548_E) && + if ((SVR_SOC_VER(get_svr()) == SVR_8548_E) && (SVR_MJREV(get_svr()) == 1) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |