diff options
| -rw-r--r-- | README | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 6 | ||||
| -rw-r--r-- | include/configs/mx6_common.h | 1 |
3 files changed, 8 insertions, 0 deletions
@@ -645,6 +645,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_773022 CONFIG_ARM_ERRATA_774769 CONFIG_ARM_ERRATA_794072 + CONFIG_ARM_ERRATA_845369 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index b180944..e3e8b7f 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -9,6 +9,7 @@ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> * Copyright (c) 2003 Kshitij <kshitij@ti.com> * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> + * Copyright (C) 2016 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -163,6 +164,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 21 @ set bit #21 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_845369 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 22 @ set bit #22 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif mov r5, lr @ Store my Caller mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index a228618..cf1e826 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -13,6 +13,7 @@ #define CONFIG_ARM_ERRATA_751472 #define CONFIG_ARM_ERRATA_794072 #define CONFIG_ARM_ERRATA_761320 +#define CONFIG_ARM_ERRATA_845369 #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 |