diff options
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index bd742bc..e95e19a 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -470,13 +470,24 @@ int arch_cpu_init(void) set_ahb_rate(132000000); } - if (is_cpu_type(MXC_CPU_MX6UL) && is_soc_rev(CHIP_REV_1_0)) { - /* - * According to the design team's requirement on i.MX6UL, - * the PMIC_STBY_REQ PAD should be configured as open - * drain 100K (0x0000b8a0). - */ - writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c); + if (is_cpu_type(MXC_CPU_MX6UL)) { + if (is_soc_rev(CHIP_REV_1_0)) { + /* + * According to the design team's requirement on i.MX6UL, + * the PMIC_STBY_REQ PAD should be configured as open + * drain 100K (0x0000b8a0). + */ + writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c); + } else { + /* + * From TO1.1, SNVS adds internal pull up control for POR_B, + * the register filed is GPBIT[1:0], after system boot up, + * it can be set to 2b'01 to disable internal pull up. + * It can save about 30uA power in SNVS mode. + */ + writel((readl(SNVS_LP_BASE_ADDR + 0x10) & (~0x1400)) | 0x400, + SNVS_LP_BASE_ADDR + 0x10); + } } /* Set perclk to source from OSC 24MHz */ |