diff options
1643 files changed, 38812 insertions, 8318 deletions
@@ -13,7 +13,11 @@ Andreas Bießmann <andreas.devel@googlemail.com> Aneesh V <aneesh@ti.com> Dirk Behme <dirk.behme@googlemail.com> Fabio Estevam <fabio.estevam@freescale.com> -Jagannadha Sutradharudu Teki <402jagan@gmail.com> +Jagan Teki <402jagan@gmail.com> +Jagan Teki <jaganna@gmail.com> +Jagan Teki <jaganna@xilinx.com> +Jagan Teki <jagannadh.teki@gmail.com> +Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com> Markus Klotzbuecher <mk@denx.de> Prabhakar Kushwaha <prabhakar@freescale.com> Rajeshwari Shinde <rajeshwari.s@samsung.com> diff --git a/MAINTAINERS b/MAINTAINERS index b3a45cc..5b3c93a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -112,12 +112,10 @@ M: Minkyu Kang <mk7.kang@samsung.com> S: Maintained T: git git://git.denx.de/u-boot-samsung.git F: arch/arm/cpu/arm920t/s3c24x0/ -F: arch/arm/cpu/armv7/exynos/ -F: arch/arm/cpu/armv7/s5pc1xx/ +F: arch/arm/mach-exynos/ +F: arch/arm/mach-s5pc1xx/ F: arch/arm/cpu/armv7/s5p-common/ -F: arch/arm/include/asm/arch-exynos/ F: arch/arm/include/asm/arch-s3c24x0/ -F: arch/arm/include/asm/arch-s5pc1xx/ ARM STM SPEAR M: Vipin Kumar <vipin.kumar@st.com> @@ -163,7 +161,7 @@ M: Masahiro Yamada <yamada.masahiro@socionext.com> S: Maintained T: git git://git.denx.de/u-boot-uniphier.git F: arch/arm/mach-uniphier/ -F: configs/ph1_*_defconfig +F: configs/uniphier_*_defconfig N: uniphier ARM ZYNQ @@ -5,7 +5,7 @@ VERSION = 2016 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* @@ -611,6 +611,9 @@ The following options need to be configured: CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS Number of controllers used for other than main memory. + CONFIG_SYS_FSL_HAS_DP_DDR + Defines the SoC has DP-DDR used for DPAA. + CONFIG_SYS_FSL_SEC_BE Defines the SEC controller register space as Big Endian @@ -2692,11 +2695,6 @@ CBFS (Coreboot Filesystem) support Enables the driver for SPI controller on SuperH. Currently only SH7757 is supported. - CONFIG_SPI_X - - Enables extended (16-bit) SPI EEPROM addressing. - (symmetrical to CONFIG_I2C_X) - CONFIG_SOFT_SPI Enables a software (bit-bang) SPI driver rather than @@ -3871,7 +3869,15 @@ Configuration Settings: Scratch address used by the alternate memory test You only need to set this if address zero isn't writeable -- CONFIG_SYS_MEM_TOP_HIDE (PPC only): +- CONFIG_SYS_MEM_RESERVE_SECURE + If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory + is substracted from total RAM and won't be reported to OS. + This memory can be used as secure memory. A variable + gd->secure_ram is used to track the location. In systems + the RAM base is not zero, or RAM is divided into banks, + this variable needs to be recalcuated to get the address. + +- CONFIG_SYS_MEM_TOP_HIDE: If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of RAM and won't get "touched" at all by U-Boot. By @@ -5050,8 +5056,8 @@ This firmware often needs to be loaded during U-Boot booting. - CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE Define minimum DDR size required for debug server image -- CONFIG_SYS_MEM_TOP_HIDE_MIN - Define minimum DDR size to be hided from top of the DDR memory +- CONFIG_SYS_MC_RSV_MEM_ALIGN + Define alignment of reserved memory MC requires Reproducible builds ------------------- diff --git a/arch/Kconfig b/arch/Kconfig index 25dcf4a..1709d40 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -40,6 +40,7 @@ config BLACKFIN config M68K bool "M68000 architecture" + select HAVE_PRIVATE_LIBGCC select HAVE_GENERIC_BOARD select SYS_GENERIC_BOARD @@ -97,6 +98,7 @@ config SH config SPARC bool "SPARC architecture" + select HAVE_GENERIC_BOARD select CREATE_ARCH_SYMLINK config X86 diff --git a/arch/arc/dts/axs10x.dts b/arch/arc/dts/axs10x.dts index 8fe1837..391d067 100644 --- a/arch/arc/dts/axs10x.dts +++ b/arch/arc/dts/axs10x.dts @@ -42,4 +42,16 @@ clock-names = "stmmaceth"; max-speed = <100>; }; + + ehci@0xe0040000 { + compatible = "generic-ehci"; + reg = < 0xe0040000 0x100 >; + interrupts = < 8 >; + }; + + ohci@0xe0060000 { + compatible = "generic-ohci"; + reg = < 0xe0060000 0x100 >; + interrupts = < 8 >; + }; }; diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6542c38..9bd6cf1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -516,14 +516,16 @@ config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" select CMD_USB select DM - select DM_GPIO select DM_ETH + select DM_GPIO + select DM_KEYBOARD select DM_SERIAL select DM_USB select OF_CONTROL select OF_SEPARATE select SPL_STACK_R if !MACH_SUN9I select SPL_SYS_MALLOC_SIMPLE if !MACH_SUN9I + select SYS_NS16550 select USB select USB_STORAGE select USB_KEYBOARD @@ -551,7 +553,9 @@ config ARCH_ZYNQ select OF_CONTROL select SPL_OF_CONTROL select DM + select DM_ETH select SPL_DM + select DM_MMC select DM_SPI select DM_SERIAL select DM_SPI_FLASH @@ -562,6 +566,8 @@ config ARCH_ZYNQMP select ARM64 select DM select OF_CONTROL + select DM_ETH + select DM_MMC select DM_SERIAL config TEGRA @@ -589,36 +595,46 @@ config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select ARM64 -config TARGET_LS2085A_EMU - bool "Support ls2085a_emu" +config TARGET_LS2080A_EMU + bool "Support ls2080a_emu" select ARM64 select ARMV8_MULTIENTRY + help + Support for Freescale LS2080A_EMU platform + The LS2080A Development System (EMULATOR) is a pre silicon + development platform that supports the QorIQ LS2080A + Layerscape Architecture processor. -config TARGET_LS2085A_SIMU - bool "Support ls2085a_simu" +config TARGET_LS2080A_SIMU + bool "Support ls2080a_simu" select ARM64 select ARMV8_MULTIENTRY + help + Support for Freescale LS2080A_SIMU platform + The LS2080A Development System (QDS) is a pre silicon + development platform that supports the QorIQ LS2080A + Layerscape Architecture processor. -config TARGET_LS2085AQDS - bool "Support ls2085aqds" +config TARGET_LS2080AQDS + bool "Support ls2080aqds" select ARM64 select ARMV8_MULTIENTRY select SUPPORT_SPL help - Support for Freescale LS2085AQDS platform - The LS2085A Development System (QDS) is a high-performance - development platform that supports the QorIQ LS2085A + Support for Freescale LS2080AQDS platform + The LS2080A Development System (QDS) is a high-performance + development platform that supports the QorIQ LS2080A Layerscape Architecture processor. -config TARGET_LS2085ARDB - bool "Support ls2085ardb" +config TARGET_LS2080ARDB + bool "Support ls2080ardb" select ARM64 select ARMV8_MULTIENTRY select SUPPORT_SPL help - Support for Freescale LS2085ARDB platform. - The LS2085A Reference design board (RDB) is a high-performance - development platform that supports the QorIQ LS2085A + Support for Freescale LS2080ARDB platform. + The LS2080A Reference design board (RDB) is a high-performance + development platform that supports the QorIQ LS2080A Layerscape Architecture processor. config TARGET_HIKEY @@ -640,6 +656,14 @@ config TARGET_LS1021ATWR select CPU_V7 select SUPPORT_SPL +config TARGET_LS1043AQDS + bool "Support ls1043aqds" + select ARM64 + select ARMV8_MULTIENTRY + select SUPPORT_SPL + help + Support for Freescale LS1043AQDS platform. + config TARGET_LS1043ARDB bool "Support ls1043ardb" select ARM64 @@ -674,6 +698,8 @@ config ARCH_UNIPHIER config TARGET_STM32F429_DISCOVERY bool "Support STM32F429 Discovery" select CPU_V7M + select DM + select DM_SERIAL config ARCH_ROCKCHIP bool "Support Rockchip SoCs" @@ -721,7 +747,7 @@ source "arch/arm/cpu/armv7/rmobile/Kconfig" source "arch/arm/mach-rockchip/Kconfig" -source "arch/arm/cpu/armv7/s5pc1xx/Kconfig" +source "arch/arm/mach-s5pc1xx/Kconfig" source "arch/arm/mach-socfpga/Kconfig" @@ -759,10 +785,11 @@ source "board/compulab/cm_t43/Kconfig" source "board/creative/xfi3/Kconfig" source "board/denx/m28evk/Kconfig" source "board/denx/m53evk/Kconfig" -source "board/freescale/ls2085a/Kconfig" -source "board/freescale/ls2085aqds/Kconfig" -source "board/freescale/ls2085ardb/Kconfig" +source "board/freescale/ls2080a/Kconfig" +source "board/freescale/ls2080aqds/Kconfig" +source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1021aqds/Kconfig" +source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/mx23evk/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 58f9bbb..18283d1 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -53,6 +53,7 @@ machine-$(CONFIG_ARMADA_XP) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x +machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_TEGRA) += tegra diff --git a/arch/arm/cpu/arm920t/ep93xx/led.c b/arch/arm/cpu/arm920t/ep93xx/led.c index 6144729..ecceb98 100644 --- a/arch/arm/cpu/arm920t/ep93xx/led.c +++ b/arch/arm/cpu/arm920t/ep93xx/led.c @@ -13,7 +13,7 @@ static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; static uint32_t gpio_pin[2] = {1 << STATUS_LED_GREEN, 1 << STATUS_LED_RED}; -inline void switch_LED_on(uint8_t led) +static inline void switch_LED_on(uint8_t led) { register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; @@ -21,7 +21,7 @@ inline void switch_LED_on(uint8_t led) saved_state[led] = STATUS_LED_ON; } -inline void switch_LED_off(uint8_t led) +static inline void switch_LED_off(uint8_t led) { register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index c8d1422..45f346c 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -49,7 +49,6 @@ obj-$(CONFIG_OMAP34XX) += omap3/ obj-$(CONFIG_OMAP44XX) += omap4/ obj-$(CONFIG_OMAP54XX) += omap5/ obj-$(CONFIG_RMOBILE) += rmobile/ -obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/ obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_VF610) += vf610/ diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index bd14326..466348f 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -38,11 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_OF_CONTROL) -/* - * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove - * the CONFIGs. At the same time, we should move this to the board files. - */ +#if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_platdata am33xx_serial[] = { { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK }, # ifdef CONFIG_SYS_NS16550_COM2 @@ -57,14 +53,14 @@ static const struct ns16550_platdata am33xx_serial[] = { }; U_BOOT_DEVICES(am33xx_uarts) = { - { "serial_omap", &am33xx_serial[0] }, + { "ns16550_serial", &am33xx_serial[0] }, # ifdef CONFIG_SYS_NS16550_COM2 - { "serial_omap", &am33xx_serial[1] }, + { "ns16550_serial", &am33xx_serial[1] }, # ifdef CONFIG_SYS_NS16550_COM3 - { "serial_omap", &am33xx_serial[2] }, - { "serial_omap", &am33xx_serial[3] }, - { "serial_omap", &am33xx_serial[4] }, - { "serial_omap", &am33xx_serial[5] }, + { "ns16550_serial", &am33xx_serial[2] }, + { "ns16550_serial", &am33xx_serial[3] }, + { "ns16550_serial", &am33xx_serial[4] }, + { "ns16550_serial", &am33xx_serial[5] }, # endif # endif }; @@ -273,12 +269,6 @@ void s_init(void) set_uart_mux_conf(); setup_clocks_for_console(); uart_soft_reset(); -#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT) - /* TODO: This does not work, gd is not available yet */ - gd->baudrate = CONFIG_BAUDRATE; - serial_init(); - gd->have_console = 1; -#endif #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) /* Enable RTC32K clock */ rtc32k_enable(); diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index b3fb0c4..888cf1f 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -164,6 +164,13 @@ void config_sdram(const struct emif_regs *regs, int nr) writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); + + /* Trigger initialization */ + writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); + /* Wait 1ms because of L3 timeout error */ + udelay(1000); + + /* Write proper sdram_ref_cref_ctrl value */ writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); } @@ -292,7 +299,9 @@ void config_ddr_phy(const struct emif_regs *regs, int nr) EMIF_REG_INITREF_DIS_MASK); #endif if (regs->zq_config) - writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl); + /* Set time between rising edge of DDR_RESET to rising + * edge of DDR_CKE to > 500us per memory spec. */ + writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2311468..0228300 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -8,6 +8,7 @@ obj-y += cpu.o obj-y += clock.o obj-y += timer.o obj-y += fsl_epu.o +obj-y += soc.o obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index df2e1b7..2f0df65 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -218,6 +218,14 @@ void enable_caches(void) } #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ + +uint get_svr(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + return in_be32(&gur->svr); +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { @@ -372,3 +380,13 @@ void reset_cpu(ulong addr) */ } } + +void arch_preboot_os(void) +{ + unsigned long ctrl; + + /* Disable PL1 Physical Timer */ + asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl)); + ctrl &= ~ARCH_TIMER_CTRL_ENABLE; + asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl)); +} diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c new file mode 100644 index 0000000..79ae883 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -0,0 +1,90 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/arch/immap_ls102xa.h> +#include <asm/arch/ls102xa_soc.h> + +unsigned int get_soc_major_rev(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr, major; + + svr = in_be32(&gur->svr); + major = SVR_MAJ(svr); + + return major; +} + +int arch_soc_init(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + unsigned int major; + +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + +#ifdef CONFIG_FSL_DCU_FB + out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); +#endif + + /* Configure Little endian for SAI, ASRC and SPDIF */ + out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); + + /* + * Enable snoop requests and DVM message requests for + * All the slave insterfaces. + */ + out_le32(&cci->slave[0].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + out_le32(&cci->slave[1].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + out_le32(&cci->slave[2].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + + major = get_soc_major_rev(); + if (major == SOC_MAJOR_VER_1_0) { + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override + * Register All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + + /* Workaround for the issue that DDR could not respond to + * barrier transaction which is generated by executing DSB/ISB + * instruction. Set CCI-400 control override register to + * terminate the barrier transaction. After DDR is initialized, + * allow barrier transaction to DDR again */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + } + + /* Enable all the snoop signal for various masters */ + out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR | + SCFG_SNPCNFGCR_DCU_RD_WR | + SCFG_SNPCNFGCR_SATA_RD_WR | + SCFG_SNPCNFGCR_USB3_RD_WR | + SCFG_SNPCNFGCR_DBG_RD_WR | + SCFG_SNPCNFGCR_EDMA_SNP); + + /* + * Memory controller require a register write before being enabled. + * Affects: DDR + * Register: EDDRTQCFG + * Description: Memory controller performance is not optimal with + * default internal target queue register values. + * Workaround: Write a value of 63b2_0042h to address: 157_020Ch. + */ + out_be32(&scfg->eddrtqcfg, 0x63b20042); + + return 0; +} diff --git a/arch/arm/cpu/armv7/ls102xa/timer.c b/arch/arm/cpu/armv7/ls102xa/timer.c index 11b17b2..e6a32ca 100644 --- a/arch/arm/cpu/armv7/ls102xa/timer.c +++ b/arch/arm/cpu/armv7/ls102xa/timer.c @@ -56,7 +56,8 @@ static inline unsigned long long us_to_tick(unsigned long long usec) int timer_init(void) { struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; - unsigned long ctrl, val, freq; + unsigned long ctrl, freq; + unsigned long long val; /* Enable System Counter */ writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr); diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 8e5d5c9..0456263 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -208,6 +208,7 @@ int board_mmc_init(bd_t *bis) break; case BOOT_DEVICE_MMC2: case BOOT_DEVICE_MMC2_2: + omap_mmc_init(0, 0, 0, -1, -1); omap_mmc_init(1, 0, 0, -1, -1); break; } diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 459d5d8..dfb0a3e 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -26,13 +26,18 @@ obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o +ifdef CONFIG_MACH_SUN8I_A83T +obj-y += clock_sun8i_a83t.o +else obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o +endif obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o obj-$(CONFIG_MACH_SUN6I) += tzpc.o obj-$(CONFIG_AXP152_POWER) += pmic_bus.o obj-$(CONFIG_AXP209_POWER) += pmic_bus.o obj-$(CONFIG_AXP221_POWER) += pmic_bus.o +obj-$(CONFIG_AXP818_POWER) += pmic_bus.o ifndef CONFIG_SPL_BUILD ifdef CONFIG_ARMV7_PSCI @@ -49,5 +54,7 @@ obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o +obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o +obj-$(CONFIG_MACH_SUN8I_H3) += dram_sun8i_h3.o obj-y += fel_utils.o endif diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 794b829..7dfb7f5 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -72,6 +72,14 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3) + sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); + sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) + sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 7c8eff9..7e6bd61 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -59,7 +59,7 @@ void clock_init_uart(void) /* open the clock for uart */ setbits_le32(&ccm->apb1_gate, - CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1)); + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX - 1)); } int clock_twi_onoff(int port, int state) @@ -67,16 +67,13 @@ int clock_twi_onoff(int port, int state) struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (port > 2) - return -1; - /* set the apb clock gate for twi */ if (state) setbits_le32(&ccm->apb1_gate, - CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port)); + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); else clrbits_le32(&ccm->apb1_gate, - CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port)); + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); return 0; } diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 3ab3b31..4501884 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -34,9 +34,11 @@ void clock_init_safe(void) clock_set_pll1(408000000); - writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); - writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); + while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) + ; + + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); @@ -75,9 +77,6 @@ int clock_twi_onoff(int port, int state) struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (port > 3) - return -1; - /* set the apb clock gate for twi */ if (state) setbits_le32(&ccm->apb2_gate, diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun8i_a83t.c b/arch/arm/cpu/armv7/sunxi/clock_sun8i_a83t.c new file mode 100644 index 0000000..3e8728f --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/clock_sun8i_a83t.c @@ -0,0 +1,136 @@ +/* + * A83 specific clock code + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/prcm.h> +#include <asm/arch/sys_proto.h> + +#ifdef CONFIG_SPL_BUILD +void clock_init_safe(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + clock_set_pll1(408000000); + /* enable pll_hsic, default is 480M */ + writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg); + writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg); + while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {} + + /* switch to default 24MHz before changing to hsic */ + writel(0x0, &ccm->cci400_cfg); + sdelay(50); + writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg); + sdelay(100); + + /* switch before changing pll6 */ + clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK, + AHB1_CLK_SRC_OSC24M); + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); + while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {} + + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); + writel(CCM_MBUS_RESET_RESET, &ccm->mbus_reset); + writel(MBUS_CLK_DEFAULT, &ccm->mbus_clk_cfg); + + /* timestamp */ + writel(1, 0x01720000); +} +#endif + +void clock_init_uart(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* uart clock source is apb2 */ + writel(APB2_CLK_SRC_OSC24M| + APB2_CLK_RATE_N_1| + APB2_CLK_RATE_M(1), + &ccm->apb2_div); + + /* open the clock for uart */ + setbits_le32(&ccm->apb2_gate, + CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); + + /* deassert uart reset */ + setbits_le32(&ccm->apb2_reset_cfg, + 1 << (APB2_RESET_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); +} + +#ifdef CONFIG_SPL_BUILD +void clock_set_pll1(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int p = 0; + + /* Switch to 24MHz clock while changing PLL1 */ + writel(AXI_DIV_2 << AXI0_DIV_SHIFT | + AXI_DIV_2 << AXI1_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << C0_CPUX_CLK_SRC_SHIFT | + CPU_CLK_SRC_OSC24M << C1_CPUX_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); + + /* clk = 24*n/p, p is ignored if clock is >288MHz */ + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 | + CCM_PLL1_CTRL_N(clk / 24000000), + &ccm->pll1_c0_cfg); + while (!(readl(&ccm->pll_stable_status) & 0x01)) {} + + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 | + CCM_PLL1_CTRL_N(clk / (24000000)), + &ccm->pll1_c1_cfg); + while (!(readl(&ccm->pll_stable_status) & 0x02)) {} + + /* Switch CPU to PLL1 */ + writel(AXI_DIV_2 << AXI0_DIV_SHIFT | + AXI_DIV_2 << AXI1_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << C0_CPUX_CLK_SRC_SHIFT | + CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); +} +#endif + +void clock_set_pll5(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + unsigned int div1 = 0, div2 = 0; + + /* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */ + writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD | + CCM_PLL5_CTRL_N(clk / (24000000)) | + div2 << CCM_PLL5_DIV2_SHIFT | + div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg); + + udelay(5500); +} + + +unsigned int clock_get_pll6(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + uint32_t rval = readl(&ccm->pll6_cfg); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); + int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> + CCM_PLL6_CTRL_DIV1_SHIFT) + 1; + int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> + CCM_PLL6_CTRL_DIV2_SHIFT) + 1; + return 24000000 * n / div1 / div2; +} diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index 05fef32..b9bc70c 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -69,8 +69,12 @@ int print_cpuinfo(void) puts("CPU: Allwinner A23 (SUN8I)\n"); #elif defined CONFIG_MACH_SUN8I_A33 puts("CPU: Allwinner A33 (SUN8I)\n"); +#elif defined CONFIG_MACH_SUN8I_H3 + puts("CPU: Allwinner H3 (SUN8I)\n"); #elif defined CONFIG_MACH_SUN9I puts("CPU: Allwinner A80 (SUN9I)\n"); +#elif defined CONFIG_MACH_SUN8I_A83T + puts("CPU: Allwinner A83T (SUN8I)\n"); #else #warning Please update cpu_info.c with correct CPU information puts("CPU: SUNXI Family\n"); diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c new file mode 100644 index 0000000..d757e40 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c @@ -0,0 +1,424 @@ +/* + * Sun8i a33 platform dram controller init. + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang <wangflord@allwinnertech.com> + * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> + * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/dram.h> +#include <asm/arch/prcm.h> + +#define DRAM_CLK_MUL 2 +#define DRAM_CLK_DIV 1 + +struct dram_para { + u8 cs1; + u8 seq; + u8 bank; + u8 rank; + u8 rows; + u8 bus_width; + u16 page_size; +}; + +static void mctl_set_cr(struct dram_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + + writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | + MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 | + (para->seq ? MCTL_CR_SEQUENCE : 0) | + ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | + MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | + MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), + &mctl_com->cr); +} + +static void auto_detect_dram_size(struct dram_para *para) +{ + u8 orig_rank = para->rank; + int rows, columns; + + /* Row detect */ + para->page_size = 512; + para->seq = 1; + para->rows = 16; + para->rank = 1; + mctl_set_cr(para); + for (rows = 11 ; rows < 16 ; rows++) { + if (mctl_mem_matches(1 << (rows + 9))) /* row-column */ + break; + } + + /* Column (page size) detect */ + para->rows = 11; + para->page_size = 8192; + mctl_set_cr(para); + for (columns = 9 ; columns < 13 ; columns++) { + if (mctl_mem_matches(1 << columns)) + break; + } + + para->seq = 0; + para->rank = orig_rank; + para->rows = rows; + para->page_size = 1 << columns; + mctl_set_cr(para); +} + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = + CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV; + + return (ctrl_freq * nanoseconds + 999) / 1000; +} + +static void auto_set_timing_para(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + u32 reg_val; + + u8 tccd = 2; + u8 tfaw = ns_to_t(50); + u8 trrd = max(ns_to_t(10), 4); + u8 trcd = ns_to_t(15); + u8 trc = ns_to_t(53); + u8 txp = max(ns_to_t(8), 3); + u8 twtr = max(ns_to_t(8), 4); + u8 trtp = max(ns_to_t(8), 4); + u8 twr = max(ns_to_t(15), 3); + u8 trp = ns_to_t(15); + u8 tras = ns_to_t(38); + + u16 trefi = ns_to_t(7800) / 32; + u16 trfc = ns_to_t(350); + + /* Fixed timing parameters */ + u8 tmrw = 0; + u8 tmrd = 4; + u8 tmod = 12; + u8 tcke = 3; + u8 tcksrx = 5; + u8 tcksre = 5; + u8 tckesr = 4; + u8 trasmax = 24; + u8 tcl = 6; /* CL 12 */ + u8 tcwl = 4; /* CWL 8 */ + u8 t_rdata_en = 4; + u8 wr_latency = 2; + + u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ + u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ + u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ + u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ + u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ + + /* Set work mode register */ + mctl_set_cr(para); + /* Set mode register */ + writel(MCTL_MR0, &mctl_ctl->mr0); + writel(MCTL_MR1, &mctl_ctl->mr1); + writel(MCTL_MR2, &mctl_ctl->mr2); + writel(MCTL_MR3, &mctl_ctl->mr3); + /* Set dram timing */ + reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); + writel(reg_val, &mctl_ctl->dramtmg0); + reg_val = (txp << 16) | (trtp << 8) | (trc << 0); + writel(reg_val, &mctl_ctl->dramtmg1); + reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); + writel(reg_val, &mctl_ctl->dramtmg2); + reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); + writel(reg_val, &mctl_ctl->dramtmg3); + reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); + writel(reg_val, &mctl_ctl->dramtmg4); + reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); + writel(reg_val, &mctl_ctl->dramtmg5); + /* Set two rank timing and exit self-refresh timing */ + reg_val = readl(&mctl_ctl->dramtmg8); + reg_val &= ~(0xff << 8); + reg_val &= ~(0xff << 0); + reg_val |= (0x33 << 8); + reg_val |= (0x8 << 0); + writel(reg_val, &mctl_ctl->dramtmg8); + /* Set phy interface time */ + reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) + | (wr_latency << 0); + /* PHY interface write latency and read latency configure */ + writel(reg_val, &mctl_ctl->pitmg0); + /* Set phy time PTR0-2 use default */ + writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3); + writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4); + /* Set refresh timing */ + reg_val = (trefi << 16) | (trfc << 0); + writel(reg_val, &mctl_ctl->rfshtmg); +} + +static void mctl_set_pir(u32 val) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + writel(val, &mctl_ctl->pir); + mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1); +} + +static void mctl_data_train_cfg(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + if (para->rank == 2) + clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24); + else + clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24); +} + +static int mctl_train_dram(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + mctl_data_train_cfg(para); + mctl_set_pir(0x5f3); + + return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0; +} + +static void set_master_priority(void) +{ + writel(0x00a0000d, MCTL_MASTER_CFG0(0)); + writel(0x00500064, MCTL_MASTER_CFG1(0)); + writel(0x07000009, MCTL_MASTER_CFG0(1)); + writel(0x00000600, MCTL_MASTER_CFG1(1)); + writel(0x01000009, MCTL_MASTER_CFG0(3)); + writel(0x00000064, MCTL_MASTER_CFG1(3)); + writel(0x08000009, MCTL_MASTER_CFG0(4)); + writel(0x00000640, MCTL_MASTER_CFG1(4)); + writel(0x20000308, MCTL_MASTER_CFG0(8)); + writel(0x00001000, MCTL_MASTER_CFG1(8)); + writel(0x02800009, MCTL_MASTER_CFG0(9)); + writel(0x00000100, MCTL_MASTER_CFG1(9)); + writel(0x01800009, MCTL_MASTER_CFG0(5)); + writel(0x00000100, MCTL_MASTER_CFG1(5)); + writel(0x01800009, MCTL_MASTER_CFG0(7)); + writel(0x00000100, MCTL_MASTER_CFG1(7)); + writel(0x00640009, MCTL_MASTER_CFG0(6)); + writel(0x00000032, MCTL_MASTER_CFG1(6)); + writel(0x0100000d, MCTL_MASTER_CFG0(2)); + writel(0x00500080, MCTL_MASTER_CFG1(2)); +} + +static int mctl_channel_init(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + u32 low_data_lines_status; /* Training status of datalines 0 - 7 */ + u32 high_data_lines_status; /* Training status of datalines 8 - 15 */ + u32 i, rval; + + auto_set_timing_para(para); + + /* Set dram master access priority */ + writel(0x000101a0, &mctl_com->bwcr); + /* set cpu high priority */ + writel(0x1, &mctl_com->mapr); + set_master_priority(); + udelay(250); + + /* Disable dram VTC */ + clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30); + clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26); + + writel(0x94be6fa3, MCTL_PROTECT); + udelay(100); + clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 26); + writel(0x0, MCTL_PROTECT); + udelay(100); + + + /* Set ODT */ + if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) + rval = 0x0; + else + rval = 0x2; + + for (i = 0 ; i < 11 ; i++) { + clrsetbits_le32(DATX0IOCR(i), (0x3 << 24) | (0x3 << 16), + rval << 24); + clrsetbits_le32(DATX1IOCR(i), (0x3 << 24) | (0x3 << 16), + rval << 24); + clrsetbits_le32(DATX2IOCR(i), (0x3 << 24) | (0x3 << 16), + rval << 24); + clrsetbits_le32(DATX3IOCR(i), (0x3 << 24) | (0x3 << 16), + rval << 24); + } + + for (i = 0; i < 31; i++) + clrsetbits_le32(CAIOCR(i), 0x3 << 26 | 0x3 << 16, 0x2 << 26); + + /* set PLL configuration */ + if (CONFIG_DRAM_CLK >= 480) + setbits_le32(&mctl_ctl->pllgcr, 0x1 << 19); + else + setbits_le32(&mctl_ctl->pllgcr, 0x3 << 19); + + /* Auto detect dram config, set 2 rank and 16bit bus-width */ + para->cs1 = 0; + para->rank = 2; + para->bus_width = 16; + mctl_set_cr(para); + + /* Open DQS gating */ + clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6)); + clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7)); + + if (readl(&mctl_com->cr) & 0x1) + writel(0x00000303, &mctl_ctl->odtmap); + else + writel(0x00000201, &mctl_ctl->odtmap); + + mctl_data_train_cfg(para); + /* ZQ calibration */ + clrsetbits_le32(ZQnPR(0), 0x000000ff, CONFIG_DRAM_ZQ & 0xff); + clrsetbits_le32(ZQnPR(1), 0x000000ff, (CONFIG_DRAM_ZQ >> 8) & 0xff); + /* CA calibration */ + mctl_set_pir(0x0201f3 | 0x1<<10); + + /* DQS gate training */ + if (mctl_train_dram(para) != 0) { + low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03; + high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03; + + if (low_data_lines_status == 0x3) + return -EIO; + + /* DRAM has only one rank */ + para->rank = 1; + mctl_set_cr(para); + + if (low_data_lines_status == high_data_lines_status) + goto done; /* 16 bit bus, 1 rank */ + + if (!(low_data_lines_status & high_data_lines_status)) { + /* Retry 16 bit bus-width with CS1 set */ + para->cs1 = 1; + mctl_set_cr(para); + if (mctl_train_dram(para) == 0) + goto done; + } + + /* Try 8 bit bus-width */ + writel(0x0, DXnGCR0(1)); /* Disable high DQ */ + para->cs1 = 0; + para->bus_width = 8; + mctl_set_cr(para); + if (mctl_train_dram(para) != 0) + return -EIO; + } +done: + /* Check the dramc status */ + mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); + + /* Close DQS gating */ + setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6); + + /* set PGCR3,CKE polarity */ + writel(0x00aa0060, &mctl_ctl->pgcr3); + /* Enable master access */ + writel(0xffffffff, &mctl_com->maer); + + return 0; +} + +static void mctl_sys_init(struct dram_para *para) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE); + clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); + clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); + clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); + clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31); + + clock_set_pll5(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL); + + clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK, + CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) | + CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD); + mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); + + setbits_le32(&ccm->ahb_reset0_cfg, 1 << 14); + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); + setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); + setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE); + + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); + setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); + setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE); + + /* Set dram master access priority */ + writel(0x0000e00f, &mctl_ctl->clken); /* normal */ + + udelay(250); +} + +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + struct dram_para para = { + .cs1 = 0, + .bank = 1, + .rank = 1, + .rows = 15, + .bus_width = 16, + .page_size = 2048, + }; + + setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8); + + writel(0, (SUNXI_PRCM_BASE + 0x1e8)); + udelay(10); + + mctl_sys_init(¶); + + if (mctl_channel_init(¶) != 0) + return 0; + + auto_detect_dram_size(¶); + + /* Enable master software clk */ + writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr); + + /* Set DRAM ODT MAP */ + if (para.rank == 2) + writel(0x00000303, &mctl_ctl->odtmap); + else + writel(0x00000201, &mctl_ctl->odtmap); + + return para.page_size * (para.bus_width / 8) * + (1 << (para.bank + para.rank + para.rows)); +} diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c new file mode 100644 index 0000000..2020d75 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c @@ -0,0 +1,469 @@ +/* + * sun8i H3 platform dram controller init + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang <wangflord@allwinnertech.com> + * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> + * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/dram.h> +#include <linux/kconfig.h> + +struct dram_para { + u32 read_delays; + u32 write_delays; + u16 page_size; + u8 bus_width; + u8 dual_rank; + u8 row_bits; +}; + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; + + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); +} + +static u32 bin_to_mgray(int val) +{ + static const u8 lookup_table[32] = { + 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, + 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, + 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d, + 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11, + }; + + return lookup_table[clamp(val, 0, 31)]; +} + +static int mgray_to_bin(u32 val) +{ + static const u8 lookup_table[32] = { + 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, + 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b, + 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b, + 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15, + }; + + return lookup_table[val & 0x1f]; +} + +static void mctl_phy_init(u32 val) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + writel(val | PIR_INIT, &mctl_ctl->pir); + mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1); +} + +static void mctl_dq_delay(u32 read, u32 write) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + int i, j; + u32 val; + + for (i = 0; i < 4; i++) { + val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) | + DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2); + + for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++) + writel(val, &mctl_ctl->datx[i].iocr[j]); + } + + clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26); + + for (i = 0; i < 4; i++) { + val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) | + DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf); + + writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]); + writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]); + } + + setbits_le32(&mctl_ctl->pgcr[0], 1 << 26); + + udelay(1); +} + +static void mctl_set_master_priority(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + + /* enable bandwidth limit windows and set windows size 1us */ + writel(0x00010190, &mctl_com->bwcr); + + /* set cpu high priority */ + writel(0x00000001, &mctl_com->mapr); + + writel(0x0200000d, &mctl_com->mcr[0][0]); + writel(0x00800100, &mctl_com->mcr[0][1]); + writel(0x06000009, &mctl_com->mcr[1][0]); + writel(0x01000400, &mctl_com->mcr[1][1]); + writel(0x0200000d, &mctl_com->mcr[2][0]); + writel(0x00600100, &mctl_com->mcr[2][1]); + writel(0x0100000d, &mctl_com->mcr[3][0]); + writel(0x00200080, &mctl_com->mcr[3][1]); + writel(0x07000009, &mctl_com->mcr[4][0]); + writel(0x01000640, &mctl_com->mcr[4][1]); + writel(0x0100000d, &mctl_com->mcr[5][0]); + writel(0x00200080, &mctl_com->mcr[5][1]); + writel(0x01000009, &mctl_com->mcr[6][0]); + writel(0x00400080, &mctl_com->mcr[6][1]); + writel(0x0100000d, &mctl_com->mcr[7][0]); + writel(0x00400080, &mctl_com->mcr[7][1]); + writel(0x0100000d, &mctl_com->mcr[8][0]); + writel(0x00400080, &mctl_com->mcr[8][1]); + writel(0x04000009, &mctl_com->mcr[9][0]); + writel(0x00400100, &mctl_com->mcr[9][1]); + writel(0x2000030d, &mctl_com->mcr[10][0]); + writel(0x04001800, &mctl_com->mcr[10][1]); + writel(0x04000009, &mctl_com->mcr[11][0]); + writel(0x00400120, &mctl_com->mcr[11][1]); +} + +static void mctl_set_timing_params(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u8 tccd = 2; + u8 tfaw = ns_to_t(50); + u8 trrd = max(ns_to_t(10), 4); + u8 trcd = ns_to_t(15); + u8 trc = ns_to_t(53); + u8 txp = max(ns_to_t(8), 3); + u8 twtr = max(ns_to_t(8), 4); + u8 trtp = max(ns_to_t(8), 4); + u8 twr = max(ns_to_t(15), 3); + u8 trp = ns_to_t(15); + u8 tras = ns_to_t(38); + u16 trefi = ns_to_t(7800) / 32; + u16 trfc = ns_to_t(350); + + u8 tmrw = 0; + u8 tmrd = 4; + u8 tmod = 12; + u8 tcke = 3; + u8 tcksrx = 5; + u8 tcksre = 5; + u8 tckesr = 4; + u8 trasmax = 24; + + u8 tcl = 6; /* CL 12 */ + u8 tcwl = 4; /* CWL 8 */ + u8 t_rdata_en = 4; + u8 wr_latency = 2; + + u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ + u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ + u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ + u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ + u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ + + /* set mode register */ + writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ + writel(0x40, &mctl_ctl->mr[1]); + writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ + writel(0x0, &mctl_ctl->mr[3]); + + /* set DRAM timing */ + writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | + DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), + &mctl_ctl->dramtmg[0]); + writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), + &mctl_ctl->dramtmg[1]); + writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | + DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), + &mctl_ctl->dramtmg[2]); + writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), + &mctl_ctl->dramtmg[3]); + writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | + DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); + writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | + DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), + &mctl_ctl->dramtmg[5]); + + /* set two rank timing */ + clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), + (0x66 << 8) | (0x10 << 0)); + + /* set PHY interface timing, write latency and read latency configure */ + writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | + (wr_latency << 0), &mctl_ctl->pitmg[0]); + + /* set PHY timing, PTR0-2 use default */ + writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); + writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); + + /* set refresh timing */ + writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); +} + +static void mctl_zq_calibration(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + int i; + u16 zq_val[6]; + u8 val; + + writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); + + for (i = 0; i < 6; i++) { + u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; + + writel((zq << 20) | (zq << 16) | (zq << 12) | + (zq << 8) | (zq << 4) | (zq << 0), + &mctl_ctl->zqcr); + + writel(PIR_CLRSR, &mctl_ctl->pir); + mctl_phy_init(PIR_ZCAL); + + zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff; + writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]); + + writel(PIR_CLRSR, &mctl_ctl->pir); + mctl_phy_init(PIR_ZCAL); + + val = readl(&mctl_ctl->zqdr[0]) >> 24; + zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8; + } + + writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); + writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); + writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); +} + +static void mctl_set_cr(struct dram_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + + writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED | + MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) | + (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | + MCTL_CR_PAGE_SIZE(para->page_size) | + MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr); +} + +static void mctl_sys_init(struct dram_para *para) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); + clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); + clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); + clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); + udelay(10); + + clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); + udelay(1000); + + clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false); + clrsetbits_le32(&ccm->dram_clk_cfg, + CCM_DRAMCLK_CFG_DIV_MASK | CCM_DRAMCLK_CFG_SRC_MASK, + CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5 | + CCM_DRAMCLK_CFG_UPD); + mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); + + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); + setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); + setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); + + setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); + udelay(10); + + writel(0xc00e, &mctl_ctl->clken); + udelay(500); +} + +static int mctl_channel_init(struct dram_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + unsigned int i; + + mctl_set_cr(para); + mctl_set_timing_params(para); + mctl_set_master_priority(); + + /* setting VTC, default disable all VT */ + clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f); + clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26); + + /* increase DFI_PHY_UPD clock */ + writel(PROTECT_MAGIC, &mctl_com->protect); + udelay(100); + clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16); + writel(0x0, &mctl_com->protect); + udelay(100); + + /* set dramc odt */ + for (i = 0; i < 4; i++) + clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) | + (0x1 << 1) | (0x3 << 2) | (0x3 << 12) | + (0x3 << 14), + IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2); + + /* AC PDR should always ON */ + setbits_le32(&mctl_ctl->aciocr, 0x1 << 1); + + /* set DQS auto gating PD mode */ + setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6); + + /* dx ddr_clk & hdr_clk dynamic mode */ + clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); + + /* dphy & aphy phase select 270 degree */ + clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), + (0x1 << 10) | (0x2 << 8)); + + /* set half DQ */ + if (para->bus_width != 32) { + writel(0x0, &mctl_ctl->datx[2].gcr); + writel(0x0, &mctl_ctl->datx[3].gcr); + } + + /* data training configuration */ + clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, + (para->dual_rank ? 0x3 : 0x1) << 24); + + + if (para->read_delays || para->write_delays) { + mctl_dq_delay(para->read_delays, para->write_delays); + udelay(50); + } + + mctl_zq_calibration(para); + + mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST | + PIR_DRAMINIT | PIR_QSGATE); + + /* detect ranks and bus width */ + if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) { + /* only one rank */ + if (((readl(&mctl_ctl->datx[0].gsr[0]) >> 24) & 0x2) || + ((readl(&mctl_ctl->datx[1].gsr[0]) >> 24) & 0x2)) { + clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24); + para->dual_rank = 0; + } + + /* only half DQ width */ + if (((readl(&mctl_ctl->datx[2].gsr[0]) >> 24) & 0x1) || + ((readl(&mctl_ctl->datx[3].gsr[0]) >> 24) & 0x1)) { + writel(0x0, &mctl_ctl->datx[2].gcr); + writel(0x0, &mctl_ctl->datx[3].gcr); + para->bus_width = 16; + } + + mctl_set_cr(para); + udelay(20); + + /* re-train */ + mctl_phy_init(PIR_QSGATE); + if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) + return 1; + } + + /* check the dramc status */ + mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); + + /* liuke added for refresh debug */ + setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); + udelay(10); + clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); + udelay(10); + + /* set PGCR3, CKE polarity */ + writel(0x00aa0060, &mctl_ctl->pgcr[3]); + + /* power down zq calibration module for power save */ + setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN); + + /* enable master access */ + writel(0xffffffff, &mctl_com->maer); + + return 0; +} + +static void mctl_auto_detect_dram_size(struct dram_para *para) +{ + /* detect row address bits */ + para->page_size = 512; + para->row_bits = 16; + mctl_set_cr(para); + + for (para->row_bits = 11; para->row_bits < 16; para->row_bits++) + if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size)) + break; + + /* detect page size */ + para->page_size = 8192; + mctl_set_cr(para); + + for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2) + if (mctl_mem_matches(para->page_size)) + break; +} + +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + struct dram_para para = { + .read_delays = 0x00007979, /* dram_tpr12 */ + .write_delays = 0x6aaa0000, /* dram_tpr11 */ + .dual_rank = 0, + .bus_width = 32, + .row_bits = 15, + .page_size = 4096, + }; + + mctl_sys_init(¶); + if (mctl_channel_init(¶)) + return 0; + + if (para.dual_rank) + writel(0x00000303, &mctl_ctl->odtmap); + else + writel(0x00000201, &mctl_ctl->odtmap); + udelay(1); + + /* odt delay */ + writel(0x0c000400, &mctl_ctl->odtcfg); + + /* clear credit value */ + setbits_le32(&mctl_com->cccr, 1 << 31); + udelay(10); + + mctl_auto_detect_dram_size(¶); + mctl_set_cr(¶); + + return (1 << (para.row_bits + 3)) * para.page_size * + (para.dual_rank ? 2 : 1); +} diff --git a/arch/arm/cpu/armv7/sunxi/pmic_bus.c b/arch/arm/cpu/armv7/sunxi/pmic_bus.c index 9e05127..5b81a8d 100644 --- a/arch/arm/cpu/armv7/sunxi/pmic_bus.c +++ b/arch/arm/cpu/armv7/sunxi/pmic_bus.c @@ -23,6 +23,7 @@ #define AXP221_CTRL_ADDR 0x3e #define AXP221_INIT_DATA 0x3e +/* AXP818 device and runtime addresses are same as AXP223 */ #define AXP223_DEVICE_ADDR 0x3a3 #define AXP223_RUNTIME_ADDR 0x2d @@ -35,7 +36,7 @@ int pmic_bus_init(void) if (!needs_init) return 0; -#ifdef CONFIG_AXP221_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I p2wi_init(); ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR, @@ -61,7 +62,7 @@ int pmic_bus_read(u8 reg, u8 *data) return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1); #elif defined CONFIG_AXP209_POWER return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); -#elif defined CONFIG_AXP221_POWER +#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I return p2wi_read(reg, data); # else @@ -76,7 +77,7 @@ int pmic_bus_write(u8 reg, u8 data) return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1); #elif defined CONFIG_AXP209_POWER return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); -#elif defined CONFIG_AXP221_POWER +#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I return p2wi_write(reg, data); # else diff --git a/arch/arm/cpu/armv7m/config.mk b/arch/arm/cpu/armv7m/config.mk index 0b31e44..4a53006 100644 --- a/arch/arm/cpu/armv7m/config.mk +++ b/arch/arm/cpu/armv7m/config.mk @@ -1,6 +1,6 @@ # # (C) Copyright 2015 -# Kamil Lulko, <rev13@wp.pl> +# Kamil Lulko, <kamil.lulko@gmail.com> # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c index d3ab862..58cde93 100644 --- a/arch/arm/cpu/armv7m/cpu.c +++ b/arch/arm/cpu/armv7m/cpu.c @@ -3,7 +3,7 @@ * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/cpu/armv7m/start.S b/arch/arm/cpu/armv7m/start.S index e05e984..49f2720 100644 --- a/arch/arm/cpu/armv7m/start.S +++ b/arch/arm/cpu/armv7m/start.S @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/cpu/armv7m/stm32f1/Makefile b/arch/arm/cpu/armv7m/stm32f1/Makefile index 4faf435..e2081db 100644 --- a/arch/arm/cpu/armv7m/stm32f1/Makefile +++ b/arch/arm/cpu/armv7m/stm32f1/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2015 -# Kamil Lulko, <rev13@wp.pl> +# Kamil Lulko, <kamil.lulko@gmail.com> # # Copyright 2015 ATS Advanced Telematics Systems GmbH # Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/cpu/armv7m/stm32f1/clock.c b/arch/arm/cpu/armv7m/stm32f1/clock.c index acad116..2820848 100644 --- a/arch/arm/cpu/armv7m/stm32f1/clock.c +++ b/arch/arm/cpu/armv7m/stm32f1/clock.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/cpu/armv7m/stm32f1/flash.c b/arch/arm/cpu/armv7m/stm32f1/flash.c index bb88f23..7d41f63 100644 --- a/arch/arm/cpu/armv7m/stm32f1/flash.c +++ b/arch/arm/cpu/armv7m/stm32f1/flash.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/cpu/armv7m/stm32f1/soc.c b/arch/arm/cpu/armv7m/stm32f1/soc.c index 8275ad7..4438621 100644 --- a/arch/arm/cpu/armv7m/stm32f1/soc.c +++ b/arch/arm/cpu/armv7m/stm32f1/soc.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/cpu/armv7m/stm32f1/timer.c b/arch/arm/cpu/armv7m/stm32f1/timer.c index c6292b5..6a26198 100644 --- a/arch/arm/cpu/armv7m/stm32f1/timer.c +++ b/arch/arm/cpu/armv7m/stm32f1/timer.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/cpu/armv7m/stm32f4/Makefile b/arch/arm/cpu/armv7m/stm32f4/Makefile index e982830..42d01db 100644 --- a/arch/arm/cpu/armv7m/stm32f4/Makefile +++ b/arch/arm/cpu/armv7m/stm32f4/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2015 -# Kamil Lulko, <rev13@wp.pl> +# Kamil Lulko, <kamil.lulko@gmail.com> # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/arch/arm/cpu/armv7m/stm32f4/clock.c b/arch/arm/cpu/armv7m/stm32f4/clock.c index d520a13..3deb17a 100644 --- a/arch/arm/cpu/armv7m/stm32f4/clock.c +++ b/arch/arm/cpu/armv7m/stm32f4/clock.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * (C) Copyright 2014 * STMicroelectronics diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/cpu/armv7m/stm32f4/flash.c index dd058bd..a379f47 100644 --- a/arch/arm/cpu/armv7m/stm32f4/flash.c +++ b/arch/arm/cpu/armv7m/stm32f4/flash.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/cpu/armv7m/stm32f4/soc.c b/arch/arm/cpu/armv7m/stm32f4/soc.c index 202a126..b5d06db 100644 --- a/arch/arm/cpu/armv7m/stm32f4/soc.c +++ b/arch/arm/cpu/armv7m/stm32f4/soc.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/cpu/armv7m/stm32f4/timer.c b/arch/arm/cpu/armv7m/stm32f4/timer.c index 102ae6d..1dee190 100644 --- a/arch/arm/cpu/armv7m/stm32f4/timer.c +++ b/arch/arm/cpu/armv7m/stm32f4/timer.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 1ece6a2..53bac3b 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -13,13 +13,13 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SYS_DCACHE_OFF inline void set_pgtable_section(u64 *page_table, u64 index, u64 section, - u64 memory_type, u64 share) + u64 memory_type, u64 attribute) { u64 value; value = section | PMD_TYPE_SECT | PMD_SECT_AF; value |= PMD_ATTRINDX(memory_type); - value |= share; + value |= attribute; page_table[index] = value; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 6fa08c8..cce7405 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -21,10 +21,14 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o endif endif +ifneq ($(CONFIG_LS2080A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o +endif + ifneq ($(CONFIG_LS2085A),) -obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o -else +obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o +endif + ifneq ($(CONFIG_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o endif -endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 index 03e18f6..f9323c1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 @@ -7,7 +7,7 @@ Freescale LayerScape with Chassis Generation 3 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, -for example LS2085A. +for example LS2080A. DDR Layout ============ @@ -152,7 +152,7 @@ u-boot command nand write <rcw image in memory> 0 <size of rcw image> To form the NAND image, build u-boot with NAND config, for example, -ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin. +ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin. The u-boot image should be written to match SRC_ADDR, in above example 0x20000. nand write <u-boot image in memory> 200000 <size of u-boot image> @@ -242,3 +242,84 @@ MMU Translation Tables | 0x81_0000_0000 | | 0x08_0080_0000 | ------------------ ------------------ ... ... + + +DPAA2 commands to manage Management Complex (MC) +------------------------------------------------ +DPAA2 commands has been introduced to manage Management Complex +(MC). These commands are used to start mc, aiop and apply DPL +from u-boot command prompt. + +Please note Management complex Firmware(MC), DPL and DPC are no +more deployed during u-boot boot-sequence. + +Commands: +a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex +b) fsl_mc apply DPL <DPL_addr> - Apply DPL file +c) fsl_mc start aiop <FW_addr> - Start AIOP + +How to use commands :- +1. Command sequence for u-boot ethernet: + a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex + b) DPMAC net-devices are now available for use + + Example- + Assumption: MC firmware, DPL and DPC dtb is already programmed + on NOR flash. + + => fsl_mc start mc 580300000 580800000 + => setenv ethact DPMAC1@xgmii + => ping $serverip + +2. Command sequence for Linux boot: + a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex + b) fsl_mc apply DPL <DPL_addr> - Apply DPL file + c) No DPMAC net-devices are available for use in u-boot + d) boot Linux + + Example- + Assumption: MC firmware, DPL and DPC dtb is already programmed + on NOR flash. + + => fsl_mc start mc 580300000 580800000 + => setenv ethact DPMAC1@xgmii + => tftp a0000000 kernel.itb + => fsl_mc apply dpl 580700000 + => bootm a0000000 + +3. Command sequence for AIOP boot: + a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex + b) fsl_mc start aiop <FW_addr> - Start AIOP + c) fsl_mc apply DPL <DPL_addr> - Apply DPL file + d) No DPMAC net-devices are availabe for use in u-boot + Please note actual AIOP start will happen during DPL parsing of + Management complex + + Example- + Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already + programmed on NOR flash. + + => fsl_mc start mc 580300000 580800000 + => fsl_mc start aiop 0x580900000 + => setenv ethact DPMAC1@xgmii + => fsl_mc apply dpl 580700000 + +Errata A009635 +--------------- +If the core runs at higher than x3 speed of the platform, there is +possiblity about sev instruction to getting missed by other cores. +This is because of SoC Run Control block may not able to sample +the EVENTI(Sev) signals. + +Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to +wake up A57 cores + +Errata workaround uses Env variable "a009635_interval_val". It uses decimal +value. +- Default value of env variable is platform clock (MHz) + +- User can modify default value by updating the env variable + setenv a009635_interval_val 600; saveenv; + It configure platform clock as 600 MHz + +- Env variable as 0 signifies no workaround diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 0cb0afa..6ea28ed 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -76,7 +76,7 @@ static int set_block_entry(const struct sys_mmu_table *list, index, block_addr, list->memory_type, - list->share); + list->attribute); block_addr += block_size; index++; } @@ -206,11 +206,65 @@ static inline void early_mmu_setup(void) set_sctlr(get_sctlr() | CR_M); } +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +/* + * Called from final mmu setup. The phys_addr is new, non-existing + * address. A new sub table is created @level2_table_secure to cover + * size of CONFIG_SYS_MEM_RESERVE_SECURE memory. + */ +static inline int final_secure_ddr(u64 *level0_table, + u64 *level2_table_secure, + phys_addr_t phys_addr) +{ + int ret = -EINVAL; + struct table_info table = {}; + struct sys_mmu_table ddr_entry = { + 0, 0, BLOCK_SIZE_L1, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS + }; + u64 index; + + /* Need to create a new table */ + ddr_entry.virt_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1); + ddr_entry.phys_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1); + ret = find_table(&ddr_entry, &table, level0_table); + if (ret) + return ret; + index = (ddr_entry.virt_addr - table.table_base) >> SECTION_SHIFT_L1; + set_pgtable_table(table.ptr, index, level2_table_secure); + table.ptr = level2_table_secure; + table.table_base = ddr_entry.virt_addr; + table.entry_size = BLOCK_SIZE_L2; + ret = set_block_entry(&ddr_entry, &table); + if (ret) { + printf("MMU error: could not fill non-secure ddr block entries\n"); + return ret; + } + ddr_entry.virt_addr = phys_addr; + ddr_entry.phys_addr = phys_addr; + ddr_entry.size = CONFIG_SYS_MEM_RESERVE_SECURE; + ddr_entry.attribute = PMD_SECT_OUTER_SHARE; + ret = find_table(&ddr_entry, &table, level0_table); + if (ret) { + printf("MMU error: could not find secure ddr table\n"); + return ret; + } + ret = set_block_entry(&ddr_entry, &table); + if (ret) + printf("MMU error: could not set secure ddr block entry\n"); + + return ret; +} +#endif + /* * The final tables look similar to early tables, but different in detail. * These tables are in DRAM. Sub tables are added to enable cache for * QBMan and OCRAM. * + * Put the MMU table in secure memory if gd->secure_ram is valid. + * OCRAM will be not used for this purpose so gd->secure_ram can't be 0. + * * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB. * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB. * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB. @@ -223,18 +277,40 @@ static inline void early_mmu_setup(void) */ static inline void final_mmu_setup(void) { - unsigned int el, i; + unsigned int el = current_el(); + unsigned int i; u64 *level0_table = (u64 *)gd->arch.tlb_addr; - u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000); - u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000); - u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000); -#ifdef CONFIG_FSL_LSCH3 - u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); -#elif defined(CONFIG_FSL_LSCH2) - u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); - u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000); + u64 *level1_table0; + u64 *level1_table1; + u64 *level2_table0; + u64 *level2_table1; +#ifdef CONFIG_FSL_LSCH2 + u64 *level2_table2; #endif - struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; + struct table_info table = {NULL, 0, BLOCK_SIZE_L0}; + +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + u64 *level2_table_secure; + + if (el == 3) { + /* + * Only use gd->secure_ram if the address is recalculated + * Align to 4KB for MMU table + */ + if (gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) + level0_table = (u64 *)(gd->secure_ram & ~0xfff); + else + printf("MMU warning: gd->secure_ram is not maintained, disabled.\n"); + } +#endif + level1_table0 = level0_table + 512; + level1_table1 = level1_table0 + 512; + level2_table0 = level1_table1 + 512; + level2_table1 = level2_table0 + 512; +#ifdef CONFIG_FSL_LSCH2 + level2_table2 = level2_table1 + 512; +#endif + table.ptr = level0_table; /* Invalidate all table entries */ memset(level0_table, 0, PGTABLE_SIZE); @@ -269,17 +345,34 @@ static inline void final_mmu_setup(void) &final_mmu_table[i]); } } + /* Set the secure memory to secure in MMU */ +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + if (el == 3 && gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { +#ifdef CONFIG_FSL_LSCH3 + level2_table_secure = level2_table1 + 512; +#elif defined(CONFIG_FSL_LSCH2) + level2_table_secure = level2_table2 + 512; +#endif + if (!final_secure_ddr(level0_table, + level2_table_secure, + gd->secure_ram & ~0x3)) { + gd->secure_ram |= MEM_RESERVE_SECURE_SECURED; + debug("Now MMU table is in secured memory at 0x%llx\n", + gd->secure_ram & ~0x3); + } else { + printf("MMU warning: Failed to secure DDR\n"); + } + } +#endif /* flush new MMU table */ - flush_dcache_range(gd->arch.tlb_addr, - gd->arch.tlb_addr + gd->arch.tlb_size); + flush_dcache_range((ulong)level0_table, + (ulong)level0_table + gd->arch.tlb_size); #ifdef CONFIG_SYS_DPAA_FMAN flush_dcache_all(); #endif /* point TTBR to the new table */ - el = current_el(); - set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL, MEMORY_ATTRIBUTES); /* @@ -438,7 +531,7 @@ int print_cpuinfo(void) #ifdef CONFIG_SYS_DPAA_FMAN printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); #endif -#ifdef CONFIG_FSL_LSCH3 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); #endif puts("\n"); @@ -484,7 +577,13 @@ int arch_early_init_r(void) { #ifdef CONFIG_MP int rv = 1; +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 + erratum_a009635(); +#endif + +#ifdef CONFIG_MP rv = fsl_layerscape_wake_seconday_cores(); if (rv) printf("Did not wake secondary cores\n"); @@ -537,3 +636,24 @@ void reset_cpu(ulong addr) val |= 0x02; scfg_out32(rstcr, val); } + +phys_size_t board_reserve_ram_top(phys_size_t ram_size) +{ + phys_size_t ram_top = ram_size; + +#ifdef CONFIG_SYS_MEM_TOP_HIDE +#error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function +#endif +/* Carve the Debug Server private DRAM block from the end of DRAM */ +#ifdef CONFIG_FSL_DEBUG_SERVER + ram_top -= debug_server_get_dram_block_size(); +#endif + +/* Carve the MC private DRAM block from the end of DRAM */ +#ifdef CONFIG_FSL_MC_ENET + ram_top -= mc_get_dram_block_size(); + ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1); +#endif + + return ram_top; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 47599c1..eafdd71 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -141,7 +141,7 @@ void append_mmu_masters(void *blob, const char *smmu_path, /* * The info below summarizes how streamID partitioning works - * for ls2085a and how it is conveyed to the OS via the device tree. + * for ls2080a and how it is conveyed to the OS via the device tree. * * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) * -all legacy devices get a unique ICID assigned and programmed in diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index f7178d1..fe3444a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -86,7 +86,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u32 cfg; int lane; - memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); + memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask; cfg >>= sd_prctl_shift; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 2ab8da6..be6acc6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -18,6 +18,11 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; #endif +#ifdef CONFIG_FSL_MC_ENET +int xfi_dpmac[XFI8 + 1]; +int sgmii_dpmac[SGMII16 + 1]; +#endif + int is_serdes_configured(enum srds_prtcl device) { int ret = 0; @@ -74,7 +79,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u32 cfg; int lane; - memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); + memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; cfg >>= sd_prctl_shift; @@ -116,9 +121,15 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, wriop_init_dpmac(sd, 12, (int)lane_prtcl); break; default: + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8) + wriop_init_dpmac(sd, + xfi_dpmac[lane_prtcl], + (int)lane_prtcl); + if (lane_prtcl >= SGMII1 && - lane_prtcl <= SGMII16) - wriop_init_dpmac(sd, lane + 1, + lane_prtcl <= SGMII16) + wriop_init_dpmac(sd, sgmii_dpmac[ + lane_prtcl], (int)lane_prtcl); break; } @@ -129,6 +140,16 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, void fsl_serdes_init(void) { +#ifdef CONFIG_FSL_MC_ENET + int i , j; + + for (i = XFI1, j = 1; i <= XFI8; i++, j++) + xfi_dpmac[i] = j; + + for (i = SGMII1, j = 1; i <= SGMII16; i++, j++) + sgmii_dpmac[i] = j; +#endif + #ifdef CONFIG_SYS_FSL_SRDS_1 serdes_init(FSL_SRDS_1, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 4054c3c..81cf470 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -11,6 +11,7 @@ #include <fsl_ifc.h> #include <asm/processor.h> #include <asm/io.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> #include <asm/arch/clock.h> #include <asm/arch/soc.h> #include "cpu.h" @@ -77,11 +78,15 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_systembus = sysclk; #ifdef CONFIG_DDR_CLK_FREQ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ; +#endif #else sys_info->freq_ddrbus = sysclk; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR sys_info->freq_ddrbus2 = sysclk; #endif +#endif sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & @@ -91,9 +96,11 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; +#endif for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { /* @@ -133,7 +140,9 @@ int get_clocks(void) gd->cpu_clk = sys_info.freq_processor[0]; gd->bus_clk = sys_info.freq_systembus; gd->mem_clk = sys_info.freq_ddrbus; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR gd->arch.mem2_clk = sys_info.freq_ddrbus2; +#endif #if defined(CONFIG_FSL_ESDHC) gd->arch.sdhc_clk = gd->bus_clk / 2; #endif /* defined(CONFIG_FSL_ESDHC) */ @@ -169,8 +178,10 @@ ulong get_ddr_freq(ulong ctrl_num) * DDR controller 0 & 1 are on memory complex 0 * DDR controler 2 is on memory complext 1 */ +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num >= 2) return gd->arch.mem2_clk; +#endif return gd->mem_clk; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index ea3114c..8ef4f1c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -28,7 +28,12 @@ static struct serdes_config serdes1_cfg_tbl[] = { SGMII1 } }, {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, +#ifdef CONFIG_LS2080A + {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } }, +#endif +#ifdef CONFIG_LS2085A {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, +#endif {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 0d600db..df7ffb8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -192,6 +192,12 @@ int cpu_release(int nr, int argc, char * const argv[]) (unsigned long)table + SPIN_TABLE_ELEM_SIZE); asm volatile("dsb st"); smp_kick_all_cpus(); /* only those with entry addr set will run */ + /* + * When the first release command runs, all cores are set to go. Those + * without a valid entry address will be trapped by "wfe". "sev" kicks + * them off to check the address again. When set, they continue to run. + */ + asm volatile("sev"); return 0; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 637853d..23d6b73 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -6,13 +6,93 @@ #include <common.h> #include <fsl_ifc.h> +#include <ahci.h> +#include <scsi.h> #include <asm/arch/soc.h> #include <asm/io.h> #include <asm/global_data.h> +#include <asm/arch-fsl-layerscape/config.h> DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_LS2085A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +/* + * This erratum requires setting a value to eddrtqcr1 to + * optimal the DDR performance. + */ +static void erratum_a008336(void) +{ + u32 *eddrtqcr1; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 +#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; + out_le32(eddrtqcr1, 0x63b30002); +#endif +#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; + out_le32(eddrtqcr1, 0x63b30002); +#endif +#endif +} + +/* + * This erratum requires a register write before being Memory + * controller 3 being enabled. + */ +static void erratum_a008514(void) +{ + u32 *eddrtqcr1; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 +#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; + out_le32(eddrtqcr1, 0x63b20002); +#endif +#endif +} +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 +#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" + +static unsigned long get_internval_val_mhz(void) +{ + char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); + /* + * interval is the number of platform cycles(MHz) between + * wake up events generated by EPU. + */ + ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); + + if (interval) + interval_mhz = simple_strtoul(interval, NULL, 10); + + return interval_mhz; +} + +void erratum_a009635(void) +{ + u32 val; + unsigned long interval_mhz = get_internval_val_mhz(); + + if (!interval_mhz) + return; + + val = in_le32(DCSR_CGACRE5); + writel(val | 0x00000200, DCSR_CGACRE5); + + val = in_le32(EPU_EPCMPR5); + writel(interval_mhz, EPU_EPCMPR5); + val = in_le32(EPU_EPCCR5); + writel(val | 0x82820000, EPU_EPCCR5); + val = in_le32(EPU_EPSMCR5); + writel(val | 0x002f0000, EPU_EPSMCR5); + val = in_le32(EPU_EPECR5); + writel(val | 0x20000000, EPU_EPECR5); + val = in_le32(EPU_EPGCR); + writel(val | 0x80000000, EPU_EPGCR); +} +#endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ + static void erratum_a008751(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A008751 @@ -75,29 +155,93 @@ void fsl_lsch3_early_init_f(void) erratum_rcw_src(); init_early_memctl_regs(); /* tighten IFC timing */ erratum_a009203(); + erratum_a008514(); + erratum_a008336(); } +#ifdef CONFIG_SCSI_AHCI_PLAT +int sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci; + + ccsr_ahci = (void *)CONFIG_SYS_SATA2; + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ccsr_ahci = (void *)CONFIG_SYS_SATA1; + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)CONFIG_SYS_SATA1); + scsi_scan(0); + + return 0; +} +#endif + #elif defined(CONFIG_LS1043A) +#ifdef CONFIG_SCSI_AHCI_PLAT +int sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; + + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)CONFIG_SYS_SATA); + scsi_scan(0); + + return 0; +} +#endif + +static void erratum_a009929(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009929 + struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; + u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); + + rstrqmr1 |= 0x00000400; + gur_out32(&gur->rstrqmr1, rstrqmr1); + writel(0x01000000, dcsr_cop_ccp); +#endif +} + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; #ifdef CONFIG_FSL_IFC init_early_memctl_regs(); /* tighten IFC timing */ #endif + /* Make SEC reads and writes snoopable */ + setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | + SCFG_SNPCNFGCR_SECWRSNP); + /* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A53 core cluster) */ out_le32(&cci->slave[4].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + + /* Erratum */ + erratum_a009929(); } #endif #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { +#ifdef CONFIG_SCSI_AHCI_PLAT + sata_init(); +#endif + return 0; } #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index ba551aa..f434c44 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -44,11 +44,9 @@ u32 spl_boot_mode(void) #ifdef CONFIG_SPL_BUILD void board_init_f(ulong dummy) { - /* Set global data pointer */ - gd = &gdata; /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); -#ifdef CONFIG_LS2085A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) arch_cpu_init(); #endif #ifdef CONFIG_FSL_IFC @@ -56,7 +54,7 @@ void board_init_f(ulong dummy) #endif board_early_init_f(); timer_init(); -#ifdef CONFIG_LS2085A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) env_init(); #endif get_clocks(); diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c index 8e60bae..8f47a82 100644 --- a/arch/arm/cpu/armv8/generic_timer.c +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -40,3 +40,14 @@ unsigned long timer_read_counter(void) #endif return cntpct; } + +unsigned long usec2ticks(unsigned long usec) +{ + ulong ticks; + if (usec < 1000) + ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000; + else + ticks = ((usec / 10) * (get_tbclk() / 100000)); + + return ticks; +} diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9542fff..0bcd316 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -21,7 +21,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5422-odroidxu3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-firefly.dtb \ - rk3288-jerry.dtb + rk3288-jerry.dtb \ + rk3036-sdk.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ @@ -80,15 +81,19 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_de0_nano_soc.dtb \ socfpga_cyclone5_sockit.dtb \ - socfpga_cyclone5_socrates.dtb + socfpga_cyclone5_socrates.dtb \ + socfpga_cyclone5_sr1500.dtb + dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ ls1021a-twr.dtb -dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \ - fsl-ls2085a-rdb.dtb +dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ + fsl-ls2080a-rdb.dtb +dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \ + fsl-ls1043a-rdb.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ @@ -120,6 +125,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a10s-r7-tv-dongle.dtb \ sun5i-a10s-wobo-i5.dtb \ sun5i-a13-ampe-a76.dtb \ + sun5i-a13-empire-electronix-d709.dtb \ sun5i-a13-hsg-h702.dtb \ sun5i-a13-inet-86vs.dtb \ sun5i-a13-inet-98v-rev2.dtb \ @@ -147,6 +153,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-cubietruck.dtb \ sun7i-a20-hummingbird.dtb \ sun7i-a20-i12-tvbox.dtb \ + sun7i-a20-lamobo-r1.dtb \ sun7i-a20-m3.dtb \ sun7i-a20-m5.dtb \ sun7i-a20-mk808c.dtb \ @@ -170,6 +177,11 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \ sun8i-a33-ga10h-v1.1.dtb \ sun8i-a33-q8-tablet.dtb \ sun8i-a33-sinlinx-sina33.dtb +dtb-$(CONFIG_MACH_SUN8I_A83T) += \ + sun8i-a83t-allwinner-h8homlet-v2.dtb +dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-plus.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi index 21fcc44..b26e21b 100644 --- a/arch/arm/dts/am33xx.dtsi +++ b/arch/arm/dts/am33xx.dtsi @@ -214,6 +214,7 @@ ti,hwmods = "uart1"; clock-frequency = <48000000>; reg = <0x44e09000 0x2000>; + reg-shift = <2>; interrupts = <72>; status = "disabled"; dmas = <&edma 26>, <&edma 27>; @@ -225,6 +226,7 @@ ti,hwmods = "uart2"; clock-frequency = <48000000>; reg = <0x48022000 0x2000>; + reg-shift = <2>; interrupts = <73>; status = "disabled"; dmas = <&edma 28>, <&edma 29>; @@ -236,6 +238,7 @@ ti,hwmods = "uart3"; clock-frequency = <48000000>; reg = <0x48024000 0x2000>; + reg-shift = <2>; interrupts = <74>; status = "disabled"; dmas = <&edma 30>, <&edma 31>; @@ -247,6 +250,7 @@ ti,hwmods = "uart4"; clock-frequency = <48000000>; reg = <0x481a6000 0x2000>; + reg-shift = <2>; interrupts = <44>; status = "disabled"; }; @@ -256,6 +260,7 @@ ti,hwmods = "uart5"; clock-frequency = <48000000>; reg = <0x481a8000 0x2000>; + reg-shift = <2>; interrupts = <45>; status = "disabled"; }; @@ -265,6 +270,7 @@ ti,hwmods = "uart6"; clock-frequency = <48000000>; reg = <0x481aa000 0x2000>; + reg-shift = <2>; interrupts = <46>; status = "disabled"; }; diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi index ade28c7..3fffe1e 100644 --- a/arch/arm/dts/am4372.dtsi +++ b/arch/arm/dts/am4372.dtsi @@ -152,6 +152,7 @@ uart0: serial@44e09000 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x44e09000 0x2000>; + reg-shift = <2>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart1"; }; @@ -159,6 +160,7 @@ uart1: serial@48022000 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x48022000 0x2000>; + reg-shift = <2>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; status = "disabled"; @@ -167,6 +169,7 @@ uart2: serial@48024000 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x48024000 0x2000>; + reg-shift = <2>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; status = "disabled"; @@ -175,6 +178,7 @@ uart3: serial@481a6000 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x481a6000 0x2000>; + reg-shift = <2>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; status = "disabled"; @@ -183,6 +187,7 @@ uart4: serial@481a8000 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x481a8000 0x2000>; + reg-shift = <2>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart5"; status = "disabled"; @@ -191,6 +196,7 @@ uart5: serial@481aa000 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x481aa000 0x2000>; + reg-shift = <2>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart6"; status = "disabled"; diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index 096f68b..e4daa99 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -14,6 +14,10 @@ model = "TI DRA742"; compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; + chosen { + stdout-path = &uart1; + }; + memory { device_type = "memory"; reg = <0x80000000 0x60000000>; /* 1536 MB */ diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index 8f1e25b..feb3708 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -399,6 +399,7 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; + reg-shift = <2>; interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart1"; clock-frequency = <48000000>; @@ -410,6 +411,7 @@ uart2: serial@4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; clock-frequency = <48000000>; @@ -421,6 +423,7 @@ uart3: serial@48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; clock-frequency = <48000000>; @@ -432,6 +435,7 @@ uart4: serial@4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; clock-frequency = <48000000>; @@ -443,6 +447,7 @@ uart5: serial@48066000 { compatible = "ti,omap4-uart"; reg = <0x48066000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart5"; clock-frequency = <48000000>; @@ -454,6 +459,7 @@ uart6: serial@48068000 { compatible = "ti,omap4-uart"; reg = <0x48068000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart6"; clock-frequency = <48000000>; @@ -465,6 +471,7 @@ uart7: serial@48420000 { compatible = "ti,omap4-uart"; reg = <0x48420000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart7"; clock-frequency = <48000000>; @@ -474,6 +481,7 @@ uart8: serial@48422000 { compatible = "ti,omap4-uart"; reg = <0x48422000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart8"; clock-frequency = <48000000>; @@ -483,6 +491,7 @@ uart9: serial@48424000 { compatible = "ti,omap4-uart"; reg = <0x48424000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart9"; clock-frequency = <48000000>; @@ -492,6 +501,7 @@ uart10: serial@4ae2b000 { compatible = "ti,omap4-uart"; reg = <0x4ae2b000 0x100>; + reg-shift = <2>; interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart10"; clock-frequency = <48000000>; diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts b/arch/arm/dts/fsl-ls1043a-qds.dts new file mode 100644 index 0000000..7435222 --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-qds.dts @@ -0,0 +1,124 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2015, Freescale Semiconductor + * + * Mingkai Hu <Mingkai.hu@freescale.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +/include/ "fsl-ls1043a.dtsi" + +/ { + model = "LS1043A QDS Board"; +}; + +&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "philips,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + /* IRQ10_B */ + interrupts = <0 150 0x4>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + eeprom@56 { + compatible = "at24,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "at24,24c512"; + reg = <0x57>; + }; + + adt7461a@4c { + compatible = "adt7461a"; + reg = <0x4c>; + }; + }; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000 + 0x2 0x0 0x0 0x7e800000 0x00010000 + 0x3 0x0 0x0 0x7fb00000 0x00000100>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@2,0 { + compatible = "fsl,ifc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1 0x0 0x10000>; + }; + + fpga: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + reg = <0x3 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 3 0 0x100>; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts new file mode 100644 index 0000000..16c5c89 --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-rdb.dts @@ -0,0 +1,103 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2015, Freescale Semiconductor + * + * Mingkai Hu <Mingkai.hu@freescale.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +/include/ "fsl-ls1043a.dtsi" + +/ { + model = "LS1043A RDB Board"; + + aliases { + spi1 = &dspi0; + }; + +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dspiflash: n25q12a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <1000000>; /* input clock */ + }; + +}; + +&i2c0 { + status = "okay"; + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + adt7461a@4c { + compatible = "adi,adt7461a"; + reg = <0x4c>; + }; + eeprom@56 { + compatible = "at24,24c512"; + reg = <0x52>; + }; + + eeprom@57 { + compatible = "at24,24c512"; + reg = <0x53>; + }; + + rtc@68 { + compatible = "pericom,pt7c4338"; + reg = <0x68>; + }; +}; + +&ifc { + status = "okay"; + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000 + 0x2 0x0 0x0 0x7e800000 0x00010000 + 0x3 0x0 0x0 0x7fb00000 0x00000100>; + + nor@0,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@1,0 { + compatible = "fsl,ifc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1 0x0 0x10000>; + }; + + cpld: board-control@2,0 { + compatible = "fsl,ls1043ardb-cpld"; + reg = <0x2 0x0 0x0000100>; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi new file mode 100644 index 0000000..85ea81e --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -0,0 +1,186 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2014-2015, Freescale Semiconductor + * + * Mingkai Hu <Mingkai.hu@freescale.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/include/ "skeleton64.dtsi" + +/ { + compatible = "fsl,ls1043a"; + interrupt-parent = <&gic>; + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&clockgen 1 0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + clocks = <&clockgen 1 0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + clocks = <&clockgen 1 0>; + }; + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + gic: interrupt-controller@1400000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0 0x1000>, /* GICD */ + <0x0 0x1402000 0 0x2000>, /* GICC */ + <0x0 0x1404000 0 0x2000>, /* GICH */ + <0x0 0x1406000 0 0x2000>; /* GICV */ + interrupts = <1 9 0xf08>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clockgen: clocking@1ee1000 { + compatible = "fsl,ls1043a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 64 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <6>; + big-endian; + status = "disabled"; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <0 65 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <6>; + big-endian; + status = "disabled"; + }; + + ifc: ifc@1530000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = <0 43 0x4>; + }; + + i2c0: i2c@2180000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <0 56 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c1: i2c@2190000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = <0 57 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c2: i2c@21a0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21a0000 0x0 0x10000>; + interrupts = <0 58 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c3: i2c@21b0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21b0000 0x0 0x10000>; + interrupts = <0 59 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + duart0: serial@21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0500 0x0 0x100>; + interrupts = <0 54 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart1: serial@21c0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0600 0x0 0x100>; + interrupts = <0 54 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart2: serial@21d0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0500 0x0 0x100>; + interrupts = <0 55 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart3: serial@21d0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0600 0x0 0x100>; + interrupts = <0 55 0x4>; + clocks = <&clockgen 4 0>; + }; + }; +}; diff --git a/arch/arm/dts/fsl-ls2085a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index 4477e54..547ec27 100644 --- a/arch/arm/dts/fsl-ls2085a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -1,5 +1,5 @@ /* - * Freescale ls2085a QDS board device tree source + * Freescale ls2080a QDS board device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. * @@ -8,11 +8,11 @@ /dts-v1/; -#include "fsl-ls2085a.dtsi" +#include "fsl-ls2080a.dtsi" / { - model = "Freescale Layerscape 2085a QDS Board"; - compatible = "fsl,ls2085a-qds", "fsl,ls2085a"; + model = "Freescale Layerscape 2080a QDS Board"; + compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; aliases { spi1 = &dspi; diff --git a/arch/arm/dts/fsl-ls2085a-rdb.dts b/arch/arm/dts/fsl-ls2080a-rdb.dts index 25278df..1a1813b 100644 --- a/arch/arm/dts/fsl-ls2085a-rdb.dts +++ b/arch/arm/dts/fsl-ls2080a-rdb.dts @@ -1,5 +1,5 @@ /* - * Freescale ls2085a RDB board device tree source + * Freescale ls2080a RDB board device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. * @@ -8,11 +8,11 @@ /dts-v1/; -#include "fsl-ls2085a.dtsi" +#include "fsl-ls2080a.dtsi" / { - model = "Freescale Layerscape 2085a RDB Board"; - compatible = "fsl,ls2085a-rdb", "fsl,ls2085a"; + model = "Freescale Layerscape 2080a RDB Board"; + compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; aliases { spi1 = &dspi; diff --git a/arch/arm/dts/fsl-ls2085a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 96404c5..a5c579c 100644 --- a/arch/arm/dts/fsl-ls2085a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -1,5 +1,5 @@ /* - * Freescale ls2085a SOC common device tree source + * Freescale ls2080a SOC common device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. * @@ -7,7 +7,7 @@ */ / { - compatible = "fsl,ls2085a"; + compatible = "fsl,ls2080a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts new file mode 100644 index 0000000..a83badb --- /dev/null +++ b/arch/arm/dts/rk3036-sdk.dts @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "rk3036.dtsi" + +/ { + model = "SDK-RK3036"; + compatible = "sdk,sdk-rk3036", "rockchip,rk3036"; + + chosen { + stdout-path = &uart2; + }; + + usb_control { + compatible = "rockchip,rk3036-usb-control"; + host_drv_gpio = <&gpio2 23 GPIO_ACTIVE_LOW>; + otg_drv_gpio = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; + + dr_mode = "host"; +}; diff --git a/arch/arm/dts/rk3036.dtsi b/arch/arm/dts/rk3036.dtsi new file mode 100644 index 0000000..ecf5416 --- /dev/null +++ b/arch/arm/dts/rk3036.dtsi @@ -0,0 +1,428 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3036-cru.h> +#include "skeleton.dtsi" + +/ { + compatible = "rockchip,rk3036"; + + interrupt-parent = <&gic>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + i2c1 = &i2c1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + mmc0 = &emmc; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3036-smp"; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + operating-points = < + /* KHz uV */ + 816000 1000000 + >; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + resets = <&cru SRST_CORE0>; + }; + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + resets = <&cru SRST_CORE1>; + }; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + arm,pl330-broken-no-flushp; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + }; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <24000000>; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3036-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>; + assigned-clock-rates = <594000000>; + }; + + uart0: serial@20060000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + }; + + uart1: serial@20064000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20064000 0x100>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + }; + + uart2: serial@20068000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20068000 0x100>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + }; + + pwm0: pwm@20050000 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050000 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm@20050010 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050010 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + sram: sram@10080000 { + compatible = "rockchip,rk3036-smp-sram", "mmio-sram"; + reg = <0x10080000 0x2000>; + }; + + gic: interrupt-controller@10139000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x10139000 0x1000>, + <0x1013a000 0x1000>, + <0x1013c000 0x2000>, + <0x1013e000 0x2000>; + interrupts = <GIC_PPI 9 0xf04>; + }; + + grf: syscon@20008000 { + compatible = "rockchip,rk3036-grf", "syscon"; + reg = <0x20008000 0x1000>; + }; + + usb_otg: usb@10180000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + g-use-dma; + status = "disabled"; + }; + + usb_host: usb@101c0000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x101c0000 0x40000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG1>; + clock-names = "otg"; + dr_mode = "host"; + status = "disabled"; + }; + + emmc: dwmmc@1021c000 { + compatible = "rockchip,rk3288-dw-mshc"; + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + dmas = <&pdma 12>; + dma-names = "rx-tx"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x1021c000 0x4000>; + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + disable-wp; + fifo-mode; + non-removable; + num-slots = <1>; + default-sample-phase = <158>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3036-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@2007c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2007c000 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emmc { + /* + * We run eMMC at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + emmc_clk: emmc-clk { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, + <1 25 RK_FUNC_2 &pcfg_pull_none>, + <1 26 RK_FUNC_2 &pcfg_pull_none>, + <1 27 RK_FUNC_2 &pcfg_pull_none>; + /* + <1 28 RK_FUNC_2 &pcfg_pull_up>, + <1 29 RK_FUNC_2 &pcfg_pull_up>, + <1 30 RK_FUNC_2 &pcfg_pull_up>, + <1 31 RK_FUNC_2 &pcfg_pull_up>; + */ + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, + <0 17 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, + <2 23 RK_FUNC_1 &pcfg_pull_none>; + }; + /* no rts / cts for uart1 */ + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, + <1 19 RK_FUNC_2 &pcfg_pull_none>; + }; + /* no rts / cts for uart2 */ + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <0 1 2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <0 27 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, + <0 3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; + + i2c1: i2c@20056000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0x20056000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 0f49709..ac367f8 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -324,6 +324,7 @@ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -337,6 +338,7 @@ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -350,6 +352,7 @@ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -362,6 +365,7 @@ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -375,6 +379,7 @@ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; diff --git a/arch/arm/dts/socfpga_arria5.dtsi b/arch/arm/dts/socfpga_arria5.dtsi index 5175f03..fa0bd7d 100644 --- a/arch/arm/dts/socfpga_arria5.dtsi +++ b/arch/arm/dts/socfpga_arria5.dtsi @@ -25,6 +25,8 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + drvsel = <3>; + smplsel = <0>; }; sysmgr@ffd08000 { diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 7d1836e..5933a40 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -25,6 +25,7 @@ * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; + udc0 = &usb1; }; regulator_3_3v: 3-3-v-regulator { diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi index de36209..040b236 100644 --- a/arch/arm/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -25,6 +25,8 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + drvsel = <3>; + smplsel = <0>; }; sysmgr@ffd08000 { diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts index b649c9a..dc09bed 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -16,6 +16,7 @@ aliases { ethernet0 = &gmac1; + udc0 = &usb1; }; memory { @@ -59,3 +60,7 @@ status = "okay"; u-boot,dm-pre-reloc; }; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts index e1e3d73..7d3f989 100644 --- a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts +++ b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts @@ -16,6 +16,7 @@ aliases { ethernet0 = &gmac0; + udc0 = &usb1; }; memory { @@ -51,3 +52,7 @@ bus-width = <8>; u-boot,dm-pre-reloc; }; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 9eb5a22..a202709 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -25,6 +25,7 @@ * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; + udc0 = &usb1; }; regulator_3_3v: 3-3-v-regulator { @@ -33,6 +34,10 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + soc { + u-boot,dm-pre-reloc; + }; }; &gmac1 { @@ -77,10 +82,6 @@ vqmmc-supply = <®ulator_3_3v>; }; -&usb1 { - status = "okay"; -}; - &qspi { status = "okay"; @@ -100,3 +101,7 @@ tslch-ns = <4>; }; }; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts index d7c41c8..e45c2ab 100644 --- a/arch/arm/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts @@ -14,9 +14,10 @@ bootargs = "console=ttyS0,115200"; }; - aliases { + aliases { ethernet0 = &gmac1; - }; + udc0 = &usb1; + }; memory { name = "memory"; @@ -90,3 +91,7 @@ tslch-ns = <4>; }; }; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 6782691..591d96c 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -14,16 +14,33 @@ bootargs = "console=ttyS0,115200"; }; + aliases { + udc0 = &usb1; + }; + memory { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; + + soc { + u-boot,dm-pre-reloc; + }; }; &gmac1 { status = "okay"; phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; }; &i2c0 { @@ -37,6 +54,7 @@ &mmc0 { status = "okay"; + u-boot,dm-pre-reloc; }; &qspi { @@ -58,3 +76,7 @@ tslch-ns = <4>; }; }; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts new file mode 100644 index 0000000..3729ca0 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "SoCFPGA Cyclone V SR1500"; + compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + /* + * This allows the ethaddr uboot environmnet variable + * contents to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + speed-mode = <0>; +}; + +&i2c1 { + status = "okay"; + speed-mode = <0>; +}; + +&mmc0 { + status = "okay"; + bus-width = <8>; + u-boot,dm-pre-reloc; +}; + +&uart0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + u-boot,dm-pre-reloc; + + flash0: n25q00@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00", "spi-flash"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; diff --git a/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts new file mode 100644 index 0000000..7fbb0b0 --- /dev/null +++ b/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts @@ -0,0 +1,241 @@ +/* + * Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sunxi-common-regulators.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "Empire Electronix D709 tablet"; + compatible = "empire-electronix,d709", "allwinner,sun5i-a13"; + + aliases { + serial0 = &uart1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + /* TODO: backlight uses axp gpio1 as enable pin */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <200000>; + }; + + button@400 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <400000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_inet98fv2>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ + cd-inverted; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; + + mmccard: mmccard@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + mmc0_cd_pin_inet98fv2: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins>; + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-pll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_usb0_vbus { + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb0_vbus_pin_a { + allwinner,pins = "PG12"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_ldo3>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/dts/sun7i-a20-lamobo-r1.dts new file mode 100644 index 0000000..975b0b2 --- /dev/null +++ b/arch/arm/dts/sun7i-a20-lamobo-r1.dts @@ -0,0 +1,297 @@ +/* + * Copyright 2015 Jelle de Jong <jelledejong@powercraft.nl> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Lamobo R1"; + compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + serial1 = &uart3; + serial2 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_lamobo_r1>; + + green { + label = "lamobo_r1:green:usr"; + gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_power_pin_lamobo_r1>; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + }; +}; + +&ahci_pwr_pin_a { + allwinner,pins = "PB3"; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; + operating-points = < + /* kHz uV */ + 960000 1400000 + 912000 1400000 + 864000 1350000 + 720000 1250000 + 528000 1150000 + 312000 1100000 + 144000 1050000 + >; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + mmc0_cd_pin_lamobo_r1: mmc0_cd_pin@0 { + allwinner,pins = "PH10"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + gmac_power_pin_lamobo_r1: gmac_power_pin@0 { + allwinner,pins = "PH23"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + led_pins_lamobo_r1: led_pins@0 { + allwinner,pins = "PH24"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +#include "axp209.dtsi" + +®_ahci_5v { + gpio = <&pio 1 3 0>; /* PB3 */ + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>, + <&spi0_cs0_pins_a>, + <&spi0_cs1_pins_a>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_b>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts new file mode 100644 index 0000000..342e1d3 --- /dev/null +++ b/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -0,0 +1,64 @@ +/* + * Copyright 2015 Vishnu Patekar + * Vishnu Patekar <vishnupatekar0510@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a83t.dtsi" + +/ { + model = "Allwinner A83T H8Homlet Proto Dev Board v2.0"; + compatible = "allwinner,h8homlet-v2", "allwinner,sun8i-a83t"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_b>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/arch/arm/dts/sun8i-a83t.dtsi new file mode 100644 index 0000000..245b819 --- /dev/null +++ b/arch/arm/dts/sun8i-a83t.dtsi @@ -0,0 +1,247 @@ +/* + * Copyright 2015 Vishnu Patekar + * + * Vishnu Patekar <vishnupatekar0510@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + + */ + +#include "skeleton.dtsi" + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + interrupt-parent = <&gic>; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + cpu@100 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x100>; + }; + + cpu@101 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x101>; + }; + cpu@102 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x102>; + }; + + cpu@103 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x103>; + }; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + pio: pinctrl@01c20800 { + compatible = "allwinner,sun8i-a83t-pinctrl"; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x01c20800 0x400>; + clocks = <&osc24M>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PH0", "PH1"; + allwinner,function = "i2c0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PH2", "PH3"; + allwinner,function = "i2c1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PH4", "PH5"; + allwinner,function = "i2c2"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + allwinner,function = "mmc1"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc2_8bit_pins: mmc2_8bit { + allwinner,pins = "PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", + "PC15"; + allwinner,function = "mmc2"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PF2", "PF4"; + allwinner,function = "uart0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart0_pins_b: uart0@1 { + allwinner,pins = "PB9", "PB10"; + allwinner,function = "uart0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts new file mode 100644 index 0000000..4b25dcc --- /dev/null +++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2015 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Xunlong Orange Pi PC"; + compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-plus.dts new file mode 100644 index 0000000..1cb6c66 --- /dev/null +++ b/arch/arm/dts/sun8i-h3-orangepi-plus.dts @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Xunlong Orange Pi Plus"; + compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_usb3_vbus: usb3-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_vbus_pin_a>; + regulator-name = "usb3-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&pio { + usb3_vbus_pin_a: usb3_vbus_pin@0 { + allwinner,pins = "PG11"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb1_vbus_pin_a { + allwinner,pins = "PG13"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb3_vbus-supply = <®_usb3_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi new file mode 100644 index 0000000..0faa38a --- /dev/null +++ b/arch/arm/dts/sun8i-h3.dtsi @@ -0,0 +1,595 @@ +/* + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pll1: clk@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + /* dummy clock until actually implemented */ + pll5: pll5_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "pll5"; + }; + + pll6: clk@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6", "pll6x2", "pll6d2"; + }; + + pll8: clk@01c20044 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20044 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll8", "pll8x2"; + }; + + cpu: cpu_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20050 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; + clock-output-names = "cpu"; + }; + + axi: axi_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-axi-clk"; + reg = <0x01c20050 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + ahb1: ahb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-ahb1-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; + clock-output-names = "ahb1"; + }; + + ahb2: ahb2_clk@01c2005c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-ahb2-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&ahb1>, <&pll6 2>; + clock-output-names = "ahb2"; + }; + + apb1: apb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb1>; + clock-output-names = "apb1"; + }; + + apb2: apb2_clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; + clock-output-names = "apb2"; + }; + + bus_gates: clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-h3-bus-gates-clk"; + reg = <0x01c20060 0x14>; + clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; + clock-names = "ahb1", "ahb2", "apb1", "apb2"; + clock-indices = <5>, <6>, <8>, + <9>, <10>, <13>, + <14>, <17>, <18>, + <19>, <20>, + <21>, <23>, + <24>, <25>, + <26>, <27>, + <28>, <29>, + <30>, <31>, <32>, + <35>, <36>, <37>, + <40>, <41>, <43>, + <44>, <52>, <53>, + <54>, <64>, + <65>, <69>, <72>, + <76>, <77>, <78>, + <96>, <97>, <98>, + <112>, <113>, + <114>, <115>, <116>, + <128>, <135>; + clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", + "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand", + "ahb1_sdram", "ahb2_gmac", "ahb1_ts", + "ahb1_hstimer", "ahb1_spi0", + "ahb1_spi1", "ahb1_otg", + "ahb1_otg_ehci0", "ahb1_ehic1", + "ahb1_ehic2", "ahb1_ehic3", + "ahb1_otg_ohci0", "ahb2_ohic1", + "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve", + "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint", + "ahb1_csi", "ahb1_tve", "ahb1_hdmi", + "ahb1_de", "ahb1_gpu", "ahb1_msgbox", + "ahb1_spinlock", "apb1_codec", + "apb1_spdif", "apb1_pio", "apb1_ths", + "apb1_i2s0", "apb1_i2s1", "apb1_i2s2", + "apb2_i2c0", "apb2_i2c1", "apb2_i2c2", + "apb2_uart0", "apb2_uart1", + "apb2_uart2", "apb2_uart3", "apb2_scr", + "ahb1_ephy", "ahb1_dbg"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; + clock-output-names = "mmc1", + "mmc1_output", + "mmc1_sample"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; + clock-output-names = "mmc2", + "mmc2_output", + "mmc2_sample"; + }; + + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun8i-h3-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", + "usb_phy2", "usb_phy3", + "usb_ohci0", "usb_ohci1", + "usb_ohci2", "usb_ohci3"; + }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5>; + clock-output-names = "mbus"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dma: dma-controller@01c02000 { + compatible = "allwinner,sun8i-h3-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 6>; + resets = <&bus_rst 6>; + #dma-cells = <1>; + }; + + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&bus_gates 8>, + <&mmc0_clk 0>, + <&mmc0_clk 1>, + <&mmc0_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&bus_rst 8>; + reset-names = "ahb"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&bus_gates 9>, + <&mmc1_clk 0>, + <&mmc1_clk 1>, + <&mmc1_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&bus_rst 9>; + reset-names = "ahb"; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&bus_gates 10>, + <&mmc2_clk 0>, + <&mmc2_clk 1>, + <&mmc2_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&bus_rst 10>; + reset-names = "ahb"; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbphy: phy@01c19400 { + compatible = "allwinner,sun8i-h3-usb-phy"; + reg = <0x01c19400 0x2c>, + <0x01c1a800 0x4>, + <0x01c1b800 0x4>, + <0x01c1c800 0x4>, + <0x01c1d800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2", + "pmu3"; + clocks = <&usb_clk 8>, + <&usb_clk 9>, + <&usb_clk 10>, + <&usb_clk 11>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb3_phy"; + resets = <&usb_clk 0>, + <&usb_clk 1>, + <&usb_clk 2>, + <&usb_clk 3>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset", + "usb3_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci1: usb@01c1b000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 25>, <&bus_gates 29>; + resets = <&bus_rst 25>, <&bus_rst 29>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@01c1b400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1b400 0x100>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 29>, <&bus_gates 25>, + <&usb_clk 17>; + resets = <&bus_rst 29>, <&bus_rst 25>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@01c1c000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 26>, <&bus_gates 30>; + resets = <&bus_rst 26>, <&bus_rst 30>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@01c1c400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 30>, <&bus_gates 26>, + <&usb_clk 18>; + resets = <&bus_rst 30>, <&bus_rst 26>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci3: usb@01c1d000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1d000 0x100>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 27>, <&bus_gates 31>; + resets = <&bus_rst 27>, <&bus_rst 31>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci3: usb@01c1d400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1d400 0x100>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 31>, <&bus_gates 27>, + <&usb_clk 19>; + resets = <&bus_rst 31>, <&bus_rst 27>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + + pio: pinctrl@01c20800 { + compatible = "allwinner,sun8i-h3-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 69>; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <2>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PA4", "PA5"; + allwinner,function = "uart0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_cd_pin: mmc0_cd_pin@0 { + allwinner,pins = "PF6"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + allwinner,function = "mmc1"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + }; + + bus_rst: reset@01c202c0 { + #reset-cells = <1>; + compatible = "allwinner,sun8i-h3-bus-reset"; + reg = <0x01c202c0 0x1c>; + }; + + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + + wdt0: watchdog@01c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 112>; + resets = <&bus_rst 144>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 113>; + resets = <&bus_rst 145>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 114>; + resets = <&bus_rst 146>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 115>; + resets = <&bus_rst 147>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + rtc: rtc@01f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi new file mode 100644 index 0000000..5d4b2cf --- /dev/null +++ b/arch/arm/dts/uniphier-common32.dtsi @@ -0,0 +1,105 @@ +/* + * Device Tree Source commonly used by UniPhier ARM SoCs + * + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/include/ "skeleton.dtsi" + +/ { + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + extbus: extbus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart_clk>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart_clk>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&uart_clk>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&uart_clk>; + }; + + system-bus-controller@58c00000 { + compatible = "socionext,uniphier-system-bus-controller"; + reg = <0x58c00000 0x400>, <0x59800000 0x2000>; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x104>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x104>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + pinctrl: pinctrl@5f801000 { + /* specify compatible in each SoC DTSI */ + reg = <0x5f801000 0xe00>; + }; + + nand: nand@68000000 { + compatible = "denali,denali-nand-dt"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + reg-names = "nand_data", "denali_reg"; + }; + }; +}; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts index 9d697c1..469bd05 100644 --- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts @@ -20,8 +20,7 @@ }; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &serial0; + stdout-path = "serial0:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi index 5f12e10..856c207 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ X11 */ -/include/ "skeleton.dtsi" +/include/ "uniphier-common32.dtsi" / { compatible = "socionext,ph1-ld4"; @@ -19,6 +19,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + next-level-cache = <&l2>; }; }; @@ -41,183 +42,117 @@ clock-frequency = <100000000>; }; }; +}; - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - extbus: extbus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - clock-frequency = <36864000>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - interrupts = <0 35 4>; - clocks = <&uart_clk>; - clock-frequency = <36864000>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - interrupts = <0 37 4>; - clocks = <&uart_clk>; - clock-frequency = <36864000>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - interrupts = <0 29 4>; - clocks = <&uart_clk>; - clock-frequency = <36864000>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - interrupts = <0 41 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - interrupts = <0 42 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(512 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 1>; - clocks = <&iobus_clk>; - clock-frequency = <400000>; - }; + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - interrupts = <0 44 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; - system-bus-controller-misc@59800000 { - compatible = "socionext,uniphier-system-bus-controller-misc", - "syscon"; - reg = <0x59800000 0x2000>; - }; + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; + }; - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - interrupts = <0 80 4>; - }; + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - interrupts = <0 81 4>; - }; + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + }; - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - interrupts = <0 82 4>; - }; + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + }; - pinctrl: pinctrl@5f801000 { - compatible = "socionext,ph1-ld4-pinctrl", - "syscon"; - reg = <0x5f801000 0xe00>; - }; + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + }; +}; - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; - clocks = <&arm_timer_clk>; - }; +&serial0 { + clock-frequency = <36864000>; +}; - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; - clocks = <&arm_timer_clk>; - }; +&serial1 { + clock-frequency = <36864000>; +}; - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - }; +&serial2 { + clock-frequency = <36864000>; +}; - nand: nand@68000000 { - compatible = "denali,denali-nand-dt"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - reg-names = "nand_data", "denali_reg"; - }; - }; +&serial3 { + interrupts = <0 29 4>; + clock-frequency = <36864000>; }; -/include/ "uniphier-pinctrl.dtsi" +&pinctrl { + compatible = "socionext,ph1-ld4-pinctrl", "syscon"; +}; diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts index ccadd81..e0a972f 100644 --- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts @@ -20,8 +20,7 @@ }; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &serial0; + stdout-path = "serial0:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts index a825069..02e74a7 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts @@ -20,8 +20,7 @@ }; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &serial0; + stdout-path = "serial0:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index a11b628..244ccf6 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ X11 */ -/include/ "skeleton.dtsi" +/include/ "uniphier-common32.dtsi" / { compatible = "socionext,ph1-pro4"; @@ -20,12 +20,14 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + next-level-cache = <&l2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + next-level-cache = <&l2>; }; }; @@ -48,216 +50,149 @@ clock-frequency = <50000000>; }; }; +}; - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - extbus: extbus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - clock-frequency = <73728000>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - interrupts = <0 35 4>; - clocks = <&uart_clk>; - clock-frequency = <73728000>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - interrupts = <0 37 4>; - clocks = <&uart_clk>; - clock-frequency = <73728000>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - interrupts = <0 29 4>; - clocks = <&uart_clk>; - clock-frequency = <73728000>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - interrupts = <0 41 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - interrupts = <0 42 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(768 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - interrupts = <0 44 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - /* i2c4 does not exist */ + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; + /* i2c4 does not exist */ - system-bus-controller-misc@59800000 { - compatible = "socionext,uniphier-system-bus-controller-misc", - "syscon"; - reg = <0x59800000 0x2000>; - }; + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; - usb2: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - interrupts = <0 80 4>; - }; + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; - usb3: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - interrupts = <0 81 4>; - }; + usb2: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + }; - usb0: usb@65a00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65a00000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - interrupts = <0 134 4>; - }; + usb3: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + }; - usb1: usb@65c00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65c00000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - interrupts = <0 137 4>; - }; + usb0: usb@65a00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65a00000 0x100>; + interrupts = <0 134 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + }; - pinctrl: pinctrl@5f801000 { - compatible = "socionext,ph1-pro4-pinctrl", - "syscon"; - reg = <0x5f801000 0xe00>; - }; + usb1: usb@65c00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65c00000 0x100>; + interrupts = <0 137 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + }; +}; - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&arm_timer_clk>; - }; +&serial0 { + clock-frequency = <73728000>; +}; - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x304>; - clocks = <&arm_timer_clk>; - }; +&serial1 { + clock-frequency = <73728000>; +}; - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - }; +&serial2 { + clock-frequency = <73728000>; +}; - nand: nand@68000000 { - compatible = "denali,denali-nand-dt"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - reg-names = "nand_data", "denali_reg"; - }; - }; +&serial3 { + clock-frequency = <73728000>; }; -/include/ "uniphier-pinctrl.dtsi" +&pinctrl { + compatible = "socionext,ph1-pro4-pinctrl", "syscon"; +}; diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts index 52dd1f9..d46e827 100644 --- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts +++ b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts @@ -19,8 +19,7 @@ }; chosen { - bootargs = "console=ttyS1,115200"; - stdout-path = &serial1; + stdout-path = "serial1:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi index 6f19bf8..0049106 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ X11 */ -/include/ "skeleton.dtsi" +/include/ "uniphier-common32.dtsi" / { compatible = "socionext,ph1-pro5"; @@ -20,12 +20,14 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + next-level-cache = <&l2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + next-level-cache = <&l2>; }; }; @@ -48,187 +50,143 @@ clock-frequency = <50000000>; }; }; +}; - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - extbus: extbus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - interrupts = <0 35 4>; - clocks = <&uart_clk>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - interrupts = <0 37 4>; - clocks = <&uart_clk>; - }; +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; + interrupts = <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + next-level-cache = <&l3>; + }; - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - interrupts = <0 177 4>; - clocks = <&uart_clk>; - }; + l3: l3-cache@500c8000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <256>; + cache-level = <3>; + }; - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - interrupts = <0 41 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - interrupts = <0 42 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - interrupts = <0 44 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - /* i2c4 does not exist */ - - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; + /* i2c4 does not exist */ - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; - system-bus-controller-misc@59800000 { - compatible = "socionext,uniphier-system-bus-controller-misc", - "syscon"; - reg = <0x59800000 0x2000>; - }; + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; - pinctrl: pinctrl@5f801000 { - compatible = "socionext,ph1-pro5-pinctrl", "syscon"; - reg = <0x5f801000 0xe00>; - }; + usb0: usb@65a00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65a00000 0x100>; + interrupts = <0 134 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + }; - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&arm_timer_clk>; - }; + usb1: usb@65c00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65c00000 0x100>; + interrupts = <0 137 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; + }; +}; - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x304>; - clocks = <&arm_timer_clk>; - }; +&serial0 { + clock-frequency = <73728000>; +}; - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - }; +&serial1 { + clock-frequency = <73728000>; +}; - usb0: usb@65a00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65a00000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - interrupts = <0 134 4>; - }; +&serial2 { + clock-frequency = <73728000>; +}; - usb1: usb@65c00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65c00000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; - interrupts = <0 137 4>; - }; - }; +&serial3 { + clock-frequency = <73728000>; }; -/include/ "uniphier-pinctrl.dtsi" +&pinctrl { + compatible = "socionext,ph1-pro5-pinctrl", "syscon"; +}; diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts index c760b6d..1f3aee9 100644 --- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts @@ -21,8 +21,7 @@ }; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &serial0; + stdout-path = "serial0:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts index 2cfcaff..b58bf07 100644 --- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts @@ -20,8 +20,7 @@ }; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &serial0; + stdout-path = "serial0:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi index 7d06f7e..cb28bc4 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ X11 */ -/include/ "skeleton.dtsi" +/include/ "uniphier-common32.dtsi" / { compatible = "socionext,ph1-sld8"; @@ -19,6 +19,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + next-level-cache = <&l2>; }; }; @@ -41,183 +42,117 @@ clock-frequency = <100000000>; }; }; +}; - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - extbus: extbus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - clock-frequency = <80000000>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - interrupts = <0 35 4>; - clocks = <&uart_clk>; - clock-frequency = <80000000>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - interrupts = <0 37 4>; - clocks = <&uart_clk>; - clock-frequency = <80000000>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - interrupts = <0 29 4>; - clocks = <&uart_clk>; - clock-frequency = <80000000>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - interrupts = <0 41 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - interrupts = <0 42 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(256 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 1>; - clocks = <&iobus_clk>; - clock-frequency = <400000>; - }; + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - interrupts = <0 44 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; - system-bus-controller-misc@59800000 { - compatible = "socionext,uniphier-system-bus-controller-misc", - "syscon"; - reg = <0x59800000 0x2000>; - }; + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; + }; - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - interrupts = <0 80 4>; - }; + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - interrupts = <0 81 4>; - }; + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + }; - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - interrupts = <0 82 4>; - }; + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + }; - pinctrl: pinctrl@5f801000 { - compatible = "socionext,ph1-sld8-pinctrl", - "syscon"; - reg = <0x5f801000 0xe00>; - }; + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + }; +}; - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; - clocks = <&arm_timer_clk>; - }; +&serial0 { + clock-frequency = <80000000>; +}; - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; - clocks = <&arm_timer_clk>; - }; +&serial1 { + clock-frequency = <80000000>; +}; - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - }; +&serial2 { + clock-frequency = <80000000>; +}; - nand: nand@68000000 { - compatible = "denali,denali-nand-dt"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - reg-names = "nand_data", "denali_reg"; - }; - }; +&serial3 { + interrupts = <0 29 4>; + clock-frequency = <80000000>; }; -/include/ "uniphier-pinctrl.dtsi" +&pinctrl { + compatible = "socionext,ph1-sld8-pinctrl", "syscon"; +}; diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi index b584213..b1691d0 100644 --- a/arch/arm/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/dts/uniphier-pinctrl.dtsi @@ -7,6 +7,11 @@ */ &pinctrl { + pinctrl_emmc: emmc_grp { + groups = "emmc", "emmc_dat8"; + function = "emmc"; + }; + pinctrl_i2c0: i2c0_grp { groups = "i2c0"; function = "i2c0"; @@ -27,6 +32,16 @@ function = "i2c3"; }; + pinctrl_sd: sd_grp { + groups = "sd"; + function = "sd"; + }; + + pinctrl_sd1: sd1_grp { + groups = "sd1"; + function = "sd1"; + }; + pinctrl_uart0: uart0_grp { groups = "uart0"; function = "uart0"; diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts index d0af8ac..a49215e 100644 --- a/arch/arm/dts/uniphier-proxstream2-gentil.dts +++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts @@ -19,8 +19,7 @@ }; chosen { - bootargs = "console=ttyS2,115200"; - stdout-path = &serial2; + stdout-path = "serial2:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts index 92d7404..63bd363 100644 --- a/arch/arm/dts/uniphier-proxstream2-vodka.dts +++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts @@ -19,8 +19,7 @@ }; chosen { - bootargs = "console=ttyS2,115200"; - stdout-path = &serial2; + stdout-path = "serial2:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi index cd0cf4e..3ba6a4a 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-proxstream2.dtsi @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ X11 */ -/include/ "skeleton.dtsi" +/include/ "uniphier-common32.dtsi" / { compatible = "socionext,proxstream2"; @@ -20,24 +20,28 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + next-level-cache = <&l2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + next-level-cache = <&l2>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + next-level-cache = <&l2>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + next-level-cache = <&l2>; }; }; @@ -60,200 +64,140 @@ clock-frequency = <50000000>; }; }; +}; - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - extbus: extbus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - clock-frequency = <88900000>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - interrupts = <0 35 4>; - clocks = <&uart_clk>; - clock-frequency = <88900000>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - interrupts = <0 37 4>; - clocks = <&uart_clk>; - clock-frequency = <88900000>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - interrupts = <0 177 4>; - clocks = <&uart_clk>; - clock-frequency = <88900000>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - interrupts = <0 41 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <(1280 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + }; - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - interrupts = <0 42 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - interrupts = <0 44 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + interrupts = <0 43 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - /* chip-internal connection for DMD */ - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - /* chip-internal connection for STM */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; + /* chip-internal connection for DMD */ + i2c4: i2c@58784000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58784000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; + /* chip-internal connection for STM */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; - system-bus-controller-misc@59800000 { - compatible = "socionext,uniphier-system-bus-controller-misc", - "syscon"; - reg = <0x59800000 0x2000>; - }; + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; - pinctrl: pinctrl@5f801000 { - compatible = "socionext,proxstream2-pinctrl", "syscon"; - reg = <0x5f801000 0xe00>; - }; + usb0: usb@65a00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65a00000 0x100>; + interrupts = <0 134 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; + }; - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0xf04>; - clocks = <&arm_timer_clk>; - }; + usb1: usb@65c00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65c00000 0x100>; + interrupts = <0 137 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; + }; +}; - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0xf04>; - clocks = <&arm_timer_clk>; - }; +&serial0 { + clock-frequency = <88900000>; +}; - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - }; +&serial1 { + clock-frequency = <88900000>; +}; - usb0: usb@65a00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65a00000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; - interrupts = <0 134 4>; - }; +&serial2 { + clock-frequency = <88900000>; +}; - usb1: usb@65c00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65c00000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; - interrupts = <0 137 4>; - }; - }; +&serial3 { + clock-frequency = <88900000>; }; -/include/ "uniphier-pinctrl.dtsi" +&pinctrl { + compatible = "socionext,proxstream2-pinctrl", "syscon"; +}; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index c417236..528cd27 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -18,6 +18,7 @@ i2c0 = &i2c0; serial0 = &uart1; spi0 = &qspi; + mmc0 = &sdhci0; }; memory { @@ -370,6 +371,7 @@ }; &sdhci0 { + u-boot,dm-pre-reloc; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; @@ -383,6 +385,7 @@ }; &qspi { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 5088cfe..1ba3a1c 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -18,6 +18,7 @@ i2c0 = &i2c0; serial0 = &uart1; spi0 = &qspi; + mmc0 = &sdhci0; }; memory { @@ -291,6 +292,7 @@ }; &sdhci0 { + u-boot,dm-pre-reloc; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 51d67d9..5ec59e2 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -17,6 +17,7 @@ ethernet0 = &gem0; serial0 = &uart1; spi0 = &qspi; + mmc0 = &sdhci0; }; memory { @@ -50,6 +51,7 @@ }; &sdhci0 { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index dcfc00e..fbbb891 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -16,6 +16,8 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; + mmc0 = &sdhci0; }; memory { @@ -28,6 +30,10 @@ stdout-path = "serial0:115200n8"; }; + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; }; &clkc { @@ -45,6 +51,7 @@ }; &sdhci0 { + u-boot,dm-pre-reloc; status = "okay"; }; @@ -52,3 +59,14 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 87bb937..49b113d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -17,10 +17,22 @@ #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 -#if defined(CONFIG_LS2085A) +/* + * Reserve secure memory + * To be aligned with MMU block size + */ +#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ + +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#ifdef CONFIG_LS2080A +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#endif +#ifdef CONFIG_LS2085A #define CONFIG_NUM_DDR_CONTROLLERS 3 +#define CONFIG_SYS_FSL_HAS_DP_DDR +#endif #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 #define CONFIG_SYS_FSL_SRDS_1 @@ -44,6 +56,7 @@ #define CONFIG_SYS_FSL_CCSR_SCFG_LE #define CONFIG_SYS_FSL_ESDHC_LE #define CONFIG_SYS_FSL_IFC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN @@ -60,6 +73,13 @@ #define CCI_MN_DVM_DOMAIN_CTL 0x200 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 +#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) +#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) +#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ +#define CCN_HN_F_SAM_NODEID_MASK 0x7f +#define CCN_HN_F_SAM_NODEID_DDR0 0x4 +#define CCN_HN_F_SAM_NODEID_DDR1 0xe + #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) @@ -84,11 +104,20 @@ #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) +#define DCSR_CGACRE5 0x700070914ULL +#define EPU_EPCMPR5 0x700060914ULL +#define EPU_EPCCR5 0x700060814ULL +#define EPU_EPSMCR5 0x700060228ULL +#define EPU_EPECR5 0x700060314ULL +#define EPU_EPCTR5 0x700060a14ULL +#define EPU_EPGCR 0x700060000ULL + #define CONFIG_SYS_FSL_ERRATUM_A008336 #define CONFIG_SYS_FSL_ERRATUM_A008511 #define CONFIG_SYS_FSL_ERRATUM_A008514 #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 +#define CONFIG_SYS_FSL_ERRATUM_A009635 #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -103,8 +132,8 @@ #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ #define CONFIG_SYS_FSL_DDR_BE -#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_CCSR_GUR_BE #define CONFIG_SYS_FSL_CCSR_SCFG_BE @@ -113,6 +142,7 @@ #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE +#define CONFIG_SYS_FSL_PEX_LUT_BE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -123,8 +153,8 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SNVS_LE -#define CONFIG_SYS_FSL_SEC_LE +#define CONFIG_SYS_FSL_SEC_MON_BE +#define CONFIG_SYS_FSL_SEC_BE #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SRK_LE #define CONFIG_KEY_REVOCATION @@ -136,6 +166,7 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A009929 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 2903996..e030430 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -8,8 +8,8 @@ #define _FSL_LAYERSCAPE_CPU_H static struct cpu_type cpu_type_list[] = { - CPU_TYPE_ENTRY(LS2085, LS2085, 8), CPU_TYPE_ENTRY(LS2080, LS2080, 8), + CPU_TYPE_ENTRY(LS2085, LS2085, 8), CPU_TYPE_ENTRY(LS2045, LS2045, 4), CPU_TYPE_ENTRY(LS1043, LS1043, 4), }; @@ -103,7 +103,7 @@ struct sys_mmu_table { u64 phys_addr; u64 size; u64 memory_type; - u64 share; + u64 attribute; }; struct table_info { @@ -115,7 +115,8 @@ struct table_info { static const struct sys_mmu_table early_mmu_table[] = { #ifdef CONFIG_FSL_LSCH3 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, /* For IFC Region #1, only the first 4MB is cache-enabled */ @@ -128,18 +129,27 @@ static const struct sys_mmu_table early_mmu_table[] = { { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, + /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, @@ -152,72 +162,95 @@ static const struct sys_mmu_table early_mmu_table[] = { static const struct sys_mmu_table final_mmu_table[] = { #ifdef CONFIG_FSL_LSCH3 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, - CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, - CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, - CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, /* For QBMAN portal, only the first 64MB is cache-enabled */ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN | PMD_SECT_NS }, { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, - MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, -#ifdef CONFIG_LS2085A + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, #endif { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, - CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, - CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, - CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, - CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, - CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE }, #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h index 4da73ab..099563e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h @@ -11,4 +11,5 @@ void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt); void append_mmu_masters(void *blob, const char *smmu_path, const char *master_name, u32 *stream_ids, int count); void fdt_fixup_smmu_pcie(void *blob); +void fdt_fixup_board_enet(void *fdt); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index e1043b5..d1fbde7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -9,7 +9,7 @@ #include <config.h> -#if defined(CONFIG_LS2085A) +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) enum srds_prtcl { NONE = 0, PCIE1, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d941437..21b803f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -11,7 +11,8 @@ #define CONFIG_SYS_IMMR 0x01000000 #define CONFIG_SYS_DCSRBAR 0x20000000 -#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) +#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) +#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) @@ -30,15 +31,15 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) +#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) +#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) #define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) -#define CONFIG_SYS_SNVS_ADDR (CONFIG_SYS_IMMR + 0xe90000) +#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 @@ -60,6 +61,10 @@ #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL +/* LUT registers */ +#define PCIE_LUT_BASE 0x10000 +#define PCIE_LUT_LCTRL0 0x7F8 +#define PCIE_LUT_DBG 0x7FC /* TZ Address Space Controller Definitions */ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 6a70d44..91f3ce8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -51,8 +51,8 @@ #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) -#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) +#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) /* TZ Address Space Controller Definitions */ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ @@ -69,6 +69,10 @@ #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) +/* SATA */ +#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) +#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) + /* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) @@ -78,6 +82,10 @@ #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL +/* LUT registers */ +#define PCIE_LUT_BASE 0x80000 +#define PCIE_LUT_LCTRL0 0x7F8 +#define PCIE_LUT_DBG 0x7FC /* Device Configuration */ #define DCFG_BASE 0x01e00000 @@ -115,7 +123,9 @@ struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; unsigned long freq_ddrbus; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR unsigned long freq_ddrbus2; +#endif unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h index 5c94530..954104b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h @@ -7,7 +7,7 @@ #ifndef __FSL_STREAM_ID_H #define __FSL_STREAM_ID_H -/* Stream IDs on ls2085a devices are not hardwired and are +/* Stream IDs on ls2080a devices are not hardwired and are * programmed by sw. There are a limited number of stream IDs * available, and the partitioning of them is scenario dependent. * This header defines the partitioning between legacy, PCI, @@ -17,7 +17,7 @@ * on the specific hardware config-- e.g. perhaps not all * PEX controllers are in use. * - * On LS2085 stream IDs are programmed in AMQ registers (32-bits) for + * On LS2080 stream IDs are programmed in AMQ registers (32-bits) for * each of the different bus masters. The relationship between * the AMQ registers and stream IDs is defined in the table below: * AMQ bit streamID bit diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 5ed456e..1565592 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -23,6 +23,14 @@ #define scfg_out32(a, v) out_be32(a, v) #endif +#ifdef CONFIG_SYS_FSL_PEX_LUT_LE +#define pex_lut_in32(a) in_le32(a) +#define pex_lut_out32(a, v) out_le32(a, v) +#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) +#define pex_lut_in32(a) in_be32(a) +#define pex_lut_out32(a, v) out_be32(a, v) +#endif + struct cpu_type { char name[15]; u32 soc_ver; @@ -43,6 +51,37 @@ struct cpu_type { #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +/* ahci port register default value */ +#define AHCI_PORT_PHY_1_CFG 0xa003fffe +#define AHCI_PORT_PHY_2_CFG 0x28184d1f +#define AHCI_PORT_PHY_3_CFG 0x0e081509 +#define AHCI_PORT_TRANS_CFG 0x08000029 + +/* AHCI (sata) register map */ +struct ccsr_ahci { + u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ + u32 pcfg; /* port config */ + u32 ppcfg; /* port phy1 config */ + u32 pp2c; /* port phy2 config */ + u32 pp3c; /* port phy3 config */ + u32 pp4c; /* port phy4 config */ + u32 pp5c; /* port phy5 config */ + u32 axicc; /* AXI cache control */ + u32 paxic; /* port AXI config */ + u32 axipc; /* AXI PROT control */ + u32 ptc; /* port Trans Config */ + u32 pts; /* port Trans Status */ + u32 plc; /* port link config */ + u32 plc1; /* port link config1 */ + u32 plc2; /* port link config2 */ + u32 pls; /* port link status */ + u32 pls1; /* port link status1 */ + u32 pcmdc; /* port CMD config */ + u32 ppcs; /* port phy control status */ + u32 pberr; /* port 0/1 BIST error */ + u32 cmds; /* port 0/1 CMD status error */ +}; + #ifdef CONFIG_FSL_LSCH3 void fsl_lsch3_early_init_f(void); #elif defined(CONFIG_FSL_LSCH2) @@ -50,4 +89,7 @@ void fsl_lsch2_early_init_f(void); #endif void cpu_name(char *name); +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 +void erratum_a009635(void); +#endif #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 845ba4f..d76514e 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -27,7 +27,6 @@ #endif #if defined(CONFIG_SYS_NS16550_SERIAL) -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 09ed980..89339fe 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -11,6 +11,8 @@ #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) #define IS_E_PROCESSOR(svr) (svr & 0x80000) +#define IS_SVR_REV(svr, maj, min) \ + ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) #define SOC_VER_SLS1020 0x00 #define SOC_VER_LS1020 0x10 @@ -31,7 +33,7 @@ #define RCWSR4_SRDS1_PRTCL_SHIFT 24 #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 -#define TIMER_COMP_VAL 0xffffffff +#define TIMER_COMP_VAL 0xffffffffffffffffull #define ARCH_TIMER_CTRL_ENABLE (1 << 0) #define SYS_COUNTER_CTRL_ENABLE (1 << 24) @@ -150,6 +152,12 @@ struct ccsr_gur { #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 #define SCFG_QSPI_CLKSEL 0xc0100000 +#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 +#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 +#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 +#define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000 +#define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 +#define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 #define SCFG_ENDIANCR_LE 0x80000000 /* Supplemental Configuration Unit */ @@ -222,7 +230,7 @@ struct ccsr_scfg { u32 scfgrevcr; u32 coresrencr; u32 pex2pmrdsr; - u32 ddrc1cr; + u32 eddrtqcfg; u32 ddrc2cr; u32 ddrc3cr; u32 ddrc4cr; @@ -422,4 +430,7 @@ struct ccsr_ahci { u32 pberr; /* port 0/1 BIST error */ u32 cmds; /* port 0/1 CMD status error */ }; + +uint get_svr(void); + #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h new file mode 100644 index 0000000..f10cb91 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -0,0 +1,12 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS102XA_SOC_H +#define __FSL_LS102XA_SOC_H + +unsigned int get_soc_major_rev(void); +int arch_soc_init(void); +#endif /* __FSL_LS102XA_SOC_H */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h new file mode 100644 index 0000000..7ecc8ee --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h @@ -0,0 +1,168 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RK3036_H +#define _ASM_ARCH_CRU_RK3036_H + +#include <common.h> + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (600 * 1000000) +#define GPLL_HZ (594 * 1000000) + +#define CORE_PERI_HZ 150000000 +#define CORE_ACLK_HZ 300000000 + +#define CPU_ACLK_HZ 150000000 +#define CPU_HCLK_HZ 300000000 +#define CPU_PCLK_HZ 300000000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +struct rk3036_cru { + struct rk3036_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + } pll[4]; + unsigned int cru_mode_con; + unsigned int cru_clksel_con[35]; + unsigned int cru_clkgate_con[11]; + unsigned int reserved; + unsigned int cru_glb_srst_fst_value; + unsigned int cru_glb_srst_snd_value; + unsigned int reserved1[2]; + unsigned int cru_softrst_con[9]; + unsigned int cru_misc_con; + unsigned int reserved2[2]; + unsigned int cru_glb_cnt_th; + unsigned int cru_sdmmc_con[2]; + unsigned int cru_sdio_con[2]; + unsigned int cru_emmc_con[2]; + unsigned int reserved3; + unsigned int cru_rst_st; + unsigned int reserved4[0x23]; + unsigned int cru_pll_mask_con; +}; +check_member(rk3036_cru, cru_pll_mask_con, 0x01f0); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLLCON0*/ + PLL_POSTDIV1_MASK = 7, + PLL_POSTDIV1_SHIFT = 12, + PLL_FBDIV_MASK = 0xfff, + PLL_FBDIV_SHIFT = 0, + + /* PLLCON1 */ + PLL_DSMPD_MASK = 1, + PLL_DSMPD_SHIFT = 12, + PLL_LOCK_STATUS_MASK = 1, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_POSTDIV2_MASK = 7, + PLL_POSTDIV2_SHIFT = 6, + PLL_REFDIV_MASK = 0x3f, + PLL_REFDIV_SHIFT = 0, + PLL_RST_SHIFT = 14, + + /* CRU_MODE */ + GPLL_MODE_MASK = 3, + GPLL_MODE_SHIFT = 12, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORM, + GPLL_MODE_DEEP, + DPLL_MODE_MASK = 1, + DPLL_MODE_SHIFT = 4, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORM, + APLL_MODE_MASK = 1, + APLL_MODE_SHIFT = 0, + APLL_MODE_SLOW = 0, + APLL_MODE_NORM, + + /* CRU_CLK_SEL0_CON */ + CPU_CLK_PLL_SEL_MASK = 3, + CPU_CLK_PLL_SEL_SHIFT = 14, + CPU_CLK_PLL_SEL_APLL = 0, + CPU_CLK_PLL_SEL_DPLL, + CPU_CLK_PLL_SEL_GPLL, + ACLK_CPU_DIV_MASK = 0x1f, + ACLK_CPU_DIV_SHIFT = 8, + CORE_CLK_PLL_SEL_MASK = 1, + CORE_CLK_PLL_SEL_SHIFT = 7, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL, + CORE_DIV_CON_MASK = 0x1f, + CORE_DIV_CON_SHIFT = 0, + + /* CRU_CLK_SEL1_CON */ + CPU_PCLK_DIV_MASK = 7, + CPU_PCLK_DIV_SHIFT = 12, + CPU_HCLK_DIV_MASK = 3, + CPU_HCLK_DIV_SHIFT = 8, + CORE_ACLK_DIV_MASK = 7, + CORE_ACLK_DIV_SHIFT = 4, + CORE_PERI_DIV_MASK = 0xf, + CORE_PERI_DIV_SHIFT = 0, + + /* CRU_CLKSEL10_CON */ + PERI_PLL_SEL_MASK = 3, + PERI_PLL_SEL_SHIFT = 14, + PERI_PLL_APLL = 0, + PERI_PLL_DPLL, + PERI_PLL_GPLL, + PERI_PCLK_DIV_MASK = 3, + PERI_PCLK_DIV_SHIFT = 12, + PERI_HCLK_DIV_MASK = 3, + PERI_HCLK_DIV_SHIFT = 8, + PERI_ACLK_DIV_MASK = 0x1f, + PERI_ACLK_DIV_SHIFT = 0, + + /* CRU_CLKSEL11_CON */ + SDIO_DIV_MASK = 0x7f, + SDIO_DIV_SHIFT = 8, + MMC0_DIV_MASK = 0x7f, + MMC0_DIV_SHIFT = 0, + + /* CRU_CLKSEL12_CON */ + EMMC_PLL_MASK = 3, + EMMC_PLL_SHIFT = 12, + EMMC_SEL_APLL = 0, + EMMC_SEL_DPLL, + EMMC_SEL_GPLL, + EMMC_SEL_24M, + SDIO_PLL_MASK = 3, + SDIO_PLL_SHIFT = 10, + SDIO_SEL_APLL = 0, + SDIO_SEL_DPLL, + SDIO_SEL_GPLL, + SDIO_SEL_24M, + MMC0_PLL_MASK = 3, + MMC0_PLL_SHIFT = 8, + MMC0_SEL_APLL = 0, + MMC0_SEL_DPLL, + MMC0_SEL_GPLL, + MMC0_SEL_24M, + EMMC_DIV_MASK = 0x7f, + EMMC_DIV_SHIFT = 0, + + /* CRU_SOFTRST5_CON */ + DDRCTRL_PSRST_SHIFT = 11, + DDRCTRL_SRST_SHIFT = 10, + DDRPHY_PSRST_SHIFT = 9, + DDRPHY_SRST_SHIFT = 8, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h new file mode 100644 index 0000000..72d133c --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h @@ -0,0 +1,493 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_RK3036_H +#define _ASM_ARCH_GRF_RK3036_H + +#include <common.h> + +struct rk3036_grf { + unsigned int reserved[0x2a]; + unsigned int gpio0a_iomux; + unsigned int gpio0b_iomux; + unsigned int gpio0c_iomux; + unsigned int gpio0d_iomux; + + unsigned int gpio1a_iomux; + unsigned int gpio1b_iomux; + unsigned int gpio1c_iomux; + unsigned int gpio1d_iomux; + + unsigned int gpio2a_iomux; + unsigned int gpio2b_iomux; + unsigned int gpio2c_iomux; + unsigned int gpio2d_iomux; + + unsigned int reserved2[0x0a]; + unsigned int gpiods; + unsigned int reserved3[0x05]; + unsigned int gpio0l_pull; + unsigned int gpio0h_pull; + unsigned int gpio1l_pull; + unsigned int gpio1h_pull; + unsigned int gpio2l_pull; + unsigned int gpio2h_pull; + unsigned int reserved4[4]; + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int soc_con2; + unsigned int soc_status0; + unsigned int reserved5; + unsigned int soc_con3; + unsigned int reserved6; + unsigned int dmac_con0; + unsigned int dmac_con1; + unsigned int dmac_con2; + unsigned int reserved7[5]; + unsigned int uoc0_con5; + unsigned int reserved8[4]; + unsigned int uoc1_con4; + unsigned int uoc1_con5; + unsigned int reserved9; + unsigned int ddrc_stat; + unsigned int uoc_con6; + unsigned int soc_status1; + unsigned int cpu_con0; + unsigned int cpu_con1; + unsigned int cpu_con2; + unsigned int cpu_con3; + unsigned int reserved10; + unsigned int reserved11; + unsigned int cpu_status0; + unsigned int cpu_status1; + unsigned int os_reg[8]; + unsigned int reserved12[6]; + unsigned int dll_con[4]; + unsigned int dll_status[4]; + unsigned int dfi_wrnum; + unsigned int dfi_rdnum; + unsigned int dfi_actnum; + unsigned int dfi_timerval; + unsigned int nfi_fifo[4]; + unsigned int reserved13[0x10]; + unsigned int usbphy0_con[8]; + unsigned int usbphy1_con[8]; + unsigned int reserved14[0x10]; + unsigned int chip_tag; + unsigned int sdmmc_det_cnt; +}; +check_member(rk3036_grf, sdmmc_det_cnt, 0x304); + +/* GRF_GPIO0A_IOMUX */ +enum { + GPIO0A3_SHIFT = 6, + GPIO0A3_MASK = 1, + GPIO0A3_GPIO = 0, + GPIO0A3_I2C1_SDA, + + GPIO0A2_SHIFT = 4, + GPIO0A2_MASK = 1, + GPIO0A2_GPIO = 0, + GPIO0A2_I2C1_SCL, + + GPIO0A1_SHIFT = 2, + GPIO0A1_MASK = 3, + GPIO0A1_GPIO = 0, + GPIO0A1_I2C0_SDA, + GPIO0A1_PWM2, + + GPIO0A0_SHIFT = 0, + GPIO0A0_MASK = 3, + GPIO0A0_GPIO = 0, + GPIO0A0_I2C0_SCL, + GPIO0A0_PWM1, + +}; + +/* GRF_GPIO0B_IOMUX */ +enum { + GPIO0B6_SHIFT = 12, + GPIO0B6_MASK = 3, + GPIO0B6_GPIO = 0, + GPIO0B6_MMC1_D3, + GPIO0B6_I2S1_SCLK, + + GPIO0B5_SHIFT = 10, + GPIO0B5_MASK = 3, + GPIO0B5_GPIO = 0, + GPIO0B5_MMC1_D2, + GPIO0B5_I2S1_SDI, + + GPIO0B4_SHIFT = 8, + GPIO0B4_MASK = 3, + GPIO0B4_GPIO = 0, + GPIO0B4_MMC1_D1, + GPIO0B4_I2S1_LRCKTX, + + GPIO0B3_SHIFT = 6, + GPIO0B3_MASK = 3, + GPIO0B3_GPIO = 0, + GPIO0B3_MMC1_D0, + GPIO0B3_I2S1_LRCKRX, + + GPIO0B1_SHIFT = 2, + GPIO0B1_MASK = 3, + GPIO0B1_GPIO = 0, + GPIO0B1_MMC1_CLKOUT, + GPIO0B1_I2S1_MCLK, + + GPIO0B0_SHIFT = 0, + GPIO0B0_MASK = 3, + GPIO0B0_GPIO = 0, + GPIO0B0_MMC1_CMD, + GPIO0B0_I2S1_SDO, +}; + +/* GRF_GPIO0C_IOMUX */ +enum { + GPIO0C4_SHIFT = 8, + GPIO0C4_MASK = 1, + GPIO0C4_GPIO = 0, + GPIO0C4_DRIVE_VBUS, + + GPIO0C3_SHIFT = 6, + GPIO0C3_MASK = 1, + GPIO0C3_GPIO = 0, + GPIO0C3_UART0_CTSN, + + GPIO0C2_SHIFT = 4, + GPIO0C2_MASK = 1, + GPIO0C2_GPIO = 0, + GPIO0C2_UART0_RTSN, + + GPIO0C1_SHIFT = 2, + GPIO0C1_MASK = 1, + GPIO0C1_GPIO = 0, + GPIO0C1_UART0_SIN, + + + GPIO0C0_SHIFT = 0, + GPIO0C0_MASK = 1, + GPIO0C0_GPIO = 0, + GPIO0C0_UART0_SOUT, +}; + +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 1, + GPIO0D4_GPIO = 0, + GPIO0D4_SPDIF, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 1, + GPIO0D3_GPIO = 0, + GPIO0D3_PWM3, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 1, + GPIO0D2_GPIO = 0, + GPIO0D2_PWM0, +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A5_SHIFT = 10, + GPIO1A5_MASK = 1, + GPIO1A5_GPIO = 0, + GPIO1A5_I2S_SDI, + + GPIO1A4_SHIFT = 8, + GPIO1A4_MASK = 1, + GPIO1A4_GPIO = 0, + GPIO1A4_I2S_SD0, + + GPIO1A3_SHIFT = 6, + GPIO1A3_MASK = 1, + GPIO1A3_GPIO = 0, + GPIO1A3_I2S_LRCKTX, + + GPIO1A2_SHIFT = 4, + GPIO1A2_MASK = 6, + GPIO1A2_GPIO = 0, + GPIO1A2_I2S_LRCKRX, + GPIO1A2_I2S_PWM1_0, + + GPIO1A1_SHIFT = 2, + GPIO1A1_MASK = 1, + GPIO1A1_GPIO = 0, + GPIO1A1_I2S_SCLK, + + GPIO1A0_SHIFT = 0, + GPIO1A0_MASK = 1, + GPIO1A0_GPIO = 0, + GPIO1A0_I2S_MCLK, + +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 1, + GPIO1B7_GPIO = 0, + GPIO1B7_MMC0_CMD, + + GPIO1B3_SHIFT = 6, + GPIO1B3_MASK = 1, + GPIO1B3_GPIO = 0, + GPIO1B3_HDMI_HPD, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 1, + GPIO1B2_GPIO = 0, + GPIO1B2_HDMI_SCL, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 1, + GPIO1B1_GPIO = 0, + GPIO1B1_HDMI_SDA, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 1, + GPIO1B0_GPIO = 0, + GPIO1B0_HDMI_CEC, +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3, + GPIO1C5_GPIO = 0, + GPIO1C5_MMC0_D3, + GPIO1C5_JTAG_TMS, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3, + GPIO1C4_GPIO = 0, + GPIO1C4_MMC0_D2, + GPIO1C4_JTAG_TCK, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3, + GPIO1C3_GPIO = 0, + GPIO1C3_MMC0_D1, + GPIO1C3_UART2_SOUT, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3, + GPIO1C2_GPIO = 0, + GPIO1C2_MMC0_D0, + GPIO1C2_UART2_SIN, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 1, + GPIO1C1_GPIO = 0, + GPIO1C1_MMC0_DETN, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 1, + GPIO1C0_GPIO = 0, + GPIO1C0_MMC0_CLKOUT, +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3, + GPIO1D7_GPIO = 0, + GPIO1D7_NAND_D7, + GPIO1D7_EMMC_D7, + GPIO1D7_SPI_CSN1, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 3, + GPIO1D6_GPIO = 0, + GPIO1D6_NAND_D6, + GPIO1D6_EMMC_D6, + GPIO1D6_SPI_CSN0, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3, + GPIO1D5_GPIO = 0, + GPIO1D5_NAND_D5, + GPIO1D5_EMMC_D5, + GPIO1D5_SPI_TXD, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3, + GPIO1D4_GPIO = 0, + GPIO1D4_NAND_D4, + GPIO1D4_EMMC_D4, + GPIO1D4_SPI_RXD, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3, + GPIO1D3_GPIO = 0, + GPIO1D3_NAND_D3, + GPIO1D3_EMMC_D3, + GPIO1D3_SFC_SIO3, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3, + GPIO1D2_GPIO = 0, + GPIO1D2_NAND_D2, + GPIO1D2_EMMC_D2, + GPIO1D2_SFC_SIO2, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3, + GPIO1D1_GPIO = 0, + GPIO1D1_NAND_D1, + GPIO1D1_EMMC_D1, + GPIO1D1_SFC_SIO1, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3, + GPIO1D0_GPIO = 0, + GPIO1D0_NAND_D0, + GPIO1D0_EMMC_D0, + GPIO1D0_SFC_SIO0, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 1, + GPIO2A7_GPIO = 0, + GPIO2A7_TESTCLK_OUT, + + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = 1, + GPIO2A6_GPIO = 0, + GPIO2A6_NAND_CS0, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3, + GPIO2A4_GPIO = 0, + GPIO2A4_NAND_RDY, + GPIO2A4_EMMC_CMD, + GPIO2A3_SFC_CLK, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3, + GPIO2A3_GPIO = 0, + GPIO2A3_NAND_RDN, + GPIO2A4_SFC_CSN1, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3, + GPIO2A2_GPIO = 0, + GPIO2A2_NAND_WRN, + GPIO2A4_SFC_CSN0, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3, + GPIO2A1_GPIO = 0, + GPIO2A1_NAND_CLE, + GPIO2A1_EMMC_CLKOUT, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3, + GPIO2A0_GPIO = 0, + GPIO2A0_NAND_ALE, + GPIO2A0_SPI_CLK, +}; + +/* GRF_GPIO2B_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 1, + GPIO2B7_GPIO = 0, + GPIO2B7_MAC_RXER, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 3, + GPIO2B6_GPIO = 0, + GPIO2B6_MAC_CLKOUT, + GPIO2B6_MAC_CLKIN, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 1, + GPIO2B5_GPIO = 0, + GPIO2B5_MAC_TXEN, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 1, + GPIO2B4_GPIO = 0, + GPIO2B4_MAC_MDIO, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 1, + GPIO2B2_GPIO = 0, + GPIO2B2_MAC_CRS, +}; + +/* GRF_GPIO2C_IOMUX */ +enum { + GPIO2C7_SHIFT = 14, + GPIO2C7_MASK = 3, + GPIO2C7_GPIO = 0, + GPIO2C7_UART1_SOUT, + GPIO2C7_TESTCLK_OUT1, + + GPIO2C6_SHIFT = 12, + GPIO2C6_MASK = 1, + GPIO2C6_GPIO = 0, + GPIO2C6_UART1_SIN, + + GPIO2C5_SHIFT = 10, + GPIO2C5_MASK = 1, + GPIO2C5_GPIO = 0, + GPIO2C5_I2C2_SCL, + + GPIO2C4_SHIFT = 8, + GPIO2C4_MASK = 1, + GPIO2C4_GPIO = 0, + GPIO2C4_I2C2_SDA, + + GPIO2C3_SHIFT = 6, + GPIO2C3_MASK = 1, + GPIO2C3_GPIO = 0, + GPIO2C3_MAC_TXD0, + + GPIO2C2_SHIFT = 4, + GPIO2C2_MASK = 1, + GPIO2C2_GPIO = 0, + GPIO2C2_MAC_TXD1, + + GPIO2C1_SHIFT = 2, + GPIO2C1_MASK = 1, + GPIO2C1_GPIO = 0, + GPIO2C1_MAC_RXD0, + + GPIO2C0_SHIFT = 0, + GPIO2C0_MASK = 1, + GPIO2C0_GPIO = 0, + GPIO2C0_MAC_RXD1, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D6_SHIFT = 12, + GPIO2D6_MASK = 1, + GPIO2D6_GPIO = 0, + GPIO2D6_I2S_SDO1, + + GPIO2D5_SHIFT = 10, + GPIO2D5_MASK = 1, + GPIO2D5_GPIO = 0, + GPIO2D5_I2S_SDO2, + + GPIO2D4_SHIFT = 8, + GPIO2D4_MASK = 1, + GPIO2D4_GPIO = 0, + GPIO2D4_I2S_SDO3, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 1, + GPIO2D1_GPIO = 0, + GPIO2D1_MAC_MDC, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h new file mode 100644 index 0000000..4ce2ba5 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h @@ -0,0 +1,341 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_SDRAM_RK3036_H +#define _ASM_ARCH_SDRAM_RK3036_H + +#include <common.h> + +struct rk3036_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[12]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 cmdtstaten; + u32 reserved1[3]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[4]; + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[3]; + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 reserved5[47]; + u32 dtuwactl; + u32 dturactl; + u32 dtucfg; + u32 dtuectl; + u32 dtuwd0; + u32 dtuwd1; + u32 dtuwd2; + u32 dtuwd3; + u32 dtuwdm; + u32 dturd0; + u32 dturd1; + u32 dturd2; + u32 dturd3; + u32 dtulfsrwd; + u32 dtulfsrrd; + u32 dtueaf; + u32 dfitctrldelay; + u32 dfiodtcfg; + u32 dfiodtcfg1; + u32 dfiodtrankmap; + u32 dfitphywrdata; + u32 dfitphywrlat; + u32 reserved7[2]; + u32 dfitrddataen; + u32 dfitphyrdlat; + u32 reserved8[2]; + u32 dfitphyupdtype0; + u32 dfitphyupdtype1; + u32 dfitphyupdtype2; + u32 dfitphyupdtype3; + u32 dfitctrlupdmin; + u32 dfitctrlupdmax; + u32 dfitctrlupddly; + u32 reserved9; + u32 dfiupdcfg; + u32 dfitrefmski; + u32 dfitctrlupdi; + u32 reserved10[4]; + u32 dfitrcfg0; + u32 dfitrstat0; + u32 dfitrwrlvlen; + u32 dfitrrdlvlen; + u32 dfitrrdlvlgateen; + u32 dfiststat0; + u32 dfistcfg0; + u32 dfistcfg1; + u32 reserved11; + u32 dfitdramclken; + u32 dfitdramclkdis; + u32 dfistcfg2; + u32 dfistparclr; + u32 dfistparlog; + u32 reserved12[3]; + u32 dfilpcfg0; + u32 reserved13[3]; + u32 dfitrwrlvlresp0; + u32 dfitrwrlvlresp1; + u32 dfitrwrlvlresp2; + u32 dfitrrdlvlresp0; + u32 dfitrrdlvlresp1; + u32 dfitrrdlvlresp2; + u32 dfitrwrlvldelay0; + u32 dfitrwrlvldelay1; + u32 dfitrwrlvldelay2; + u32 dfitrrdlvldelay0; + u32 dfitrrdlvldelay1; + u32 dfitrrdlvldelay2; + u32 dfitrrdlvlgatedelay0; + u32 dfitrrdlvlgatedelay1; + u32 dfitrrdlvlgatedelay2; + u32 dfitrcmd; + u32 reserved14[46]; + u32 ipvr; + u32 iptr; +}; +check_member(rk3036_ddr_pctl, iptr, 0x03fc); + +struct rk3036_ddr_phy { + u32 ddrphy_reg1; + u32 ddrphy_reg3; + u32 ddrphy_reg2; + u32 reserve[11]; + u32 ddrphy_reg4a; + u32 ddrphy_reg4b; + u32 reserve1[5]; + u32 ddrphy_reg16; + u32 reserve2; + u32 ddrphy_reg18; + u32 ddrphy_reg19; + u32 reserve3; + u32 ddrphy_reg21; + u32 reserve4; + u32 ddrphy_reg22; + u32 reserve5[3]; + u32 ddrphy_reg25; + u32 ddrphy_reg26; + u32 ddrphy_reg27; + u32 ddrphy_reg28; + u32 reserve6[17]; + u32 ddrphy_reg6; + u32 ddrphy_reg7; + u32 reserve7; + u32 ddrphy_reg8; + u32 ddrphy_reg0e4; + u32 reserve8[11]; + u32 ddrphy_reg9; + u32 ddrphy_reg10; + u32 reserve9; + u32 ddrphy_reg11; + u32 ddrphy_reg124; + u32 reserve10[38]; + u32 ddrphy_reg29; + u32 reserve11[40]; + u32 ddrphy_reg264; + u32 reserve12[18]; + u32 ddrphy_reg2a; + u32 reserve13[4]; + u32 ddrphy_reg30; + u32 ddrphy_reg31; + u32 ddrphy_reg32; + u32 ddrphy_reg33; + u32 ddrphy_reg34; + u32 ddrphy_reg35; + u32 ddrphy_reg36; + u32 ddrphy_reg37; + u32 ddrphy_reg38; + u32 ddrphy_reg39; + u32 ddrphy_reg40; + u32 ddrphy_reg41; + u32 ddrphy_reg42; + u32 ddrphy_reg43; + u32 ddrphy_reg44; + u32 ddrphy_reg45; + u32 ddrphy_reg46; + u32 ddrphy_reg47; + u32 ddrphy_reg48; + u32 ddrphy_reg49; + u32 ddrphy_reg50; + u32 ddrphy_reg51; + u32 ddrphy_reg52; + u32 ddrphy_reg53; + u32 reserve14; + u32 ddrphy_reg54; + u32 ddrphy_reg55; + u32 ddrphy_reg56; + u32 ddrphy_reg57; + u32 ddrphy_reg58; + u32 ddrphy_reg59; + u32 ddrphy_reg5a; + u32 ddrphy_reg5b; + u32 ddrphy_reg5c; + u32 ddrphy_reg5d; + u32 ddrphy_reg5e; + u32 reserve15[28]; + u32 ddrphy_reg5f; + u32 reserve16[6]; + u32 ddrphy_reg60; + u32 ddrphy_reg61; + u32 ddrphy_reg62; +}; +check_member(rk3036_ddr_phy, ddrphy_reg62, 0x03e8); + +struct rk3036_pctl_timing { + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; +}; + +struct rk3036_phy_timing { + u32 mr[4]; + u32 bl; + u32 cl_al; +}; + +typedef union { + u32 noc_timing; + struct { + u32 acttoact:6; + u32 rdtomiss:6; + u32 wrtomiss:6; + u32 burstlen:3; + u32 rdtowr:5; + u32 wrtord:5; + u32 bwratio:1; + }; +} rk3036_noc_timing; + +struct rk3036_ddr_timing { + u32 freq; + struct rk3036_pctl_timing pctl_timing; + struct rk3036_phy_timing phy_timing; + rk3036_noc_timing noc_timing; +}; + +struct rk3036_service_sys { + u32 id_coreid; + u32 id_revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; +}; + +struct rk3036_ddr_config { + /* + * 000: lpddr + * 001: ddr + * 010: ddr2 + * 011: ddr3 + * 100: lpddr2-s2 + * 101: lpddr2-s4 + * 110: lpddr3 + */ + u32 ddr_type; + u32 rank; + u32 cs0_row; + u32 cs1_row; + + /* 2: 4bank, 3: 8bank */ + u32 bank; + u32 col; + + /* bw(0: 8bit, 1: 16bit, 2: 32bit) */ + u32 bw; +}; + +/* rk3036 sdram initial */ +void sdram_init(void); + +/* get ddr die config, implement in specific board */ +void get_ddr_config(struct rk3036_ddr_config *config); + +/* get ddr size on board */ +size_t sdram_size(void); +#endif diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h new file mode 100644 index 0000000..1d044bb --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/timer.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_TIMER_H +#define __ASM_ARCH_TIMER_H + +struct rk_timer { + unsigned int timer_load_count0; + unsigned int timer_load_count1; + unsigned int timer_curr_value0; + unsigned int timer_curr_value1; + unsigned int timer_ctrl_reg; + unsigned int timer_int_status; +}; + +void rockchip_timer_init(void); +void rockchip_udelay(unsigned int usec); + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/uart.h b/arch/arm/include/asm/arch-rockchip/uart.h new file mode 100644 index 0000000..ea86ce6 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/uart.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_UART_H +#define __ASM_ARCH_UART_H +struct rk_uart { + unsigned int rbr; /* Receive buffer register. */ + unsigned int ier; /* Interrupt enable register. */ + unsigned int fcr; /* FIFO control register. */ + unsigned int lcr; /* Line control register. */ + unsigned int mcr; /* Modem control register. */ + unsigned int lsr; /* Line status register. */ + unsigned int msr; /* Modem status register. */ + unsigned int scr; + unsigned int reserved1[(0x30 - 0x20) / 4]; + unsigned int srbr[(0x70 - 0x30) / 4]; + unsigned int far; + unsigned int tfr; + unsigned int rfw; + unsigned int usr; + unsigned int tfl; + unsigned int rfl; + unsigned int srr; + unsigned int srts; + unsigned int sbcr; + unsigned int sdmam; + unsigned int sfe; + unsigned int srt; + unsigned int stet; + unsigned int htx; + unsigned int dmasa; + unsigned int reserver2[(0xf4 - 0xac) / 4]; + unsigned int cpr; + unsigned int ucv; + unsigned int ctr; +}; + +void rk_uart_init(void *base); +void print_hex(unsigned int n); +void print(char *s); +#endif diff --git a/arch/arm/include/asm/arch-stm32f1/gpio.h b/arch/arm/include/asm/arch-stm32f1/gpio.h index 6976e1f..8e8712f 100644 --- a/arch/arm/include/asm/arch-stm32f1/gpio.h +++ b/arch/arm/include/asm/arch-stm32f1/gpio.h @@ -3,7 +3,7 @@ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/include/asm/arch-stm32f1/stm32.h b/arch/arm/include/asm/arch-stm32f1/stm32.h index 686cb4f..4094a75 100644 --- a/arch/arm/include/asm/arch-stm32f1/stm32.h +++ b/arch/arm/include/asm/arch-stm32f1/stm32.h @@ -3,7 +3,7 @@ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/arch/arm/include/asm/arch-stm32f4/fmc.h b/arch/arm/include/asm/arch-stm32f4/fmc.h index 4ab3031..7dd5077 100644 --- a/arch/arm/include/asm/arch-stm32f4/fmc.h +++ b/arch/arm/include/asm/arch-stm32f4/fmc.h @@ -3,7 +3,7 @@ * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h index dd33b96..831c542 100644 --- a/arch/arm/include/asm/arch-stm32f4/gpio.h +++ b/arch/arm/include/asm/arch-stm32f4/gpio.h @@ -3,7 +3,7 @@ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index 7ca6dc3..6b64d03 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -3,7 +3,7 @@ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -106,6 +106,14 @@ struct stm32_flash_regs { #define STM32_FLASH_CR_SNB_OFFSET 3 #define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET) +/* + * Peripheral base addresses + */ +#define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000) +#define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400) +#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800) +#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400) + enum clock { CLOCK_CORE, CLOCK_AHB, diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 3e5d999..8ca58ae 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -15,7 +15,9 @@ #define CLK_GATE_CLOSE 0x0 /* clock control module regs definition */ -#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) +#if defined(CONFIG_MACH_SUN8I_A83T) +#include <asm/arch/clock_sun8i_a83t.h> +#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) #include <asm/arch/clock_sun6i.h> #elif defined(CONFIG_MACH_SUN9I) #include <asm/arch/clock_sun9i.h> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 9b7b90c..5c76275 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -201,6 +201,7 @@ struct sunxi_ccm_reg { #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) #define CCM_PLL6_CTRL_K_SHIFT 4 #define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) +#define CCM_PLL6_CTRL_LOCK (1 << 28) #define CCM_MIPI_PLL_CTRL_M_SHIFT 0 #define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT) @@ -219,7 +220,7 @@ struct sunxi_ccm_reg { #define CCM_PLL11_CTRL_UPD (0x1 << 30) #define CCM_PLL11_CTRL_EN (0x1 << 31) -#define AHB1_ABP1_DIV_DEFAULT 0x00002020 +#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ #define AXI_GATE_OFFSET_DRAM 0 @@ -282,6 +283,9 @@ struct sunxi_ccm_reg { #define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0) #define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) #define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8) +#define CCM_DRAMCLK_CFG_SRC_PLL5 (0x0 << 20) +#define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20) +#define CCM_DRAMCLK_CFG_SRC_MASK (0x3 << 20) #define CCM_DRAMCLK_CFG_UPD (0x1 << 16) #define CCM_DRAMCLK_CFG_RST (0x1 << 31) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h new file mode 100644 index 0000000..5f93d7f --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h @@ -0,0 +1,304 @@ +/* + * sun8i a83t clock register definitions + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> + * from sun6i.h + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CLOCK_SUN8I_A83T_H +#define _SUNXI_CLOCK_SUN8I_A83T_H + +struct sunxi_ccm_reg { + u32 pll1_c0_cfg; /* 0x00 c1cpu# pll control */ + u32 pll1_c1_cfg; /* 0x04 c1cpu# pll control */ + u32 pll2_cfg; /* 0x08 pll2 audio control */ + u32 reserved1; + u32 pll3_cfg; /* 0x10 pll3 video0 control */ + u32 reserved2; + u32 pll4_cfg; /* 0x18 pll4 ve control */ + u32 reserved3; + u32 pll5_cfg; /* 0x20 pll5 ddr control */ + u32 reserved4; + u32 pll6_cfg; /* 0x28 pll6 peripheral control */ + u32 reserved5[3]; /* 0x2c */ + u32 pll7_cfg; /* 0x38 pll7 gpu control */ + u32 reserved6[2]; /* 0x3c */ + u32 pll8_cfg; /* 0x44 pll8 hsic control */ + u32 pll9_cfg; /* 0x48 pll9 de control */ + u32 pll10_cfg; /* 0x4c pll10 video1 control */ + u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */ + u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */ + u32 apb2_div; /* 0x58 APB2 divide ratio */ + u32 ahb2_div; /* 0x5c AHB2 divide ratio */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb1_gate; /* 0x68 apb1 module clock gating 3 */ + u32 apb2_gate; /* 0x6c apb2 module clock gating 4 */ + u32 reserved7[2]; /* 0x70 */ + u32 cci400_cfg; /* 0x78 cci400 clock configuration A83T only */ + u32 reserved8; /* 0x7c */ + u32 nand0_clk_cfg; /* 0x80 nand clock control */ + u32 reserved9; /* 0x84 */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 reserved10; /* 0x98 */ + u32 ss_clk_cfg; /* 0x9c security system clock control */ + u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */ + u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */ + u32 reserved11[2]; /* 0xa8 */ + u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control */ + u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ + u32 i2s2_clk_cfg; /* 0xb8 I2S2 clock control */ + u32 tdm_clk_cfg; /* 0xbc TDM clock control */ + u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ + u32 reserved12[2]; /* 0xc4 */ + u32 usb_clk_cfg; /* 0xcc USB clock control */ + u32 reserved13[9]; /* 0xd0 */ + u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ + u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register */ + u32 mbus_reset; /* 0xfc MBUS reset control */ + u32 dram_clk_gate; /* 0x100 DRAM module gating */ + u32 reserved14[5]; /* 0x104 BE0 */ + u32 lcd0_clk_cfg; /* 0x118 LCD0 module clock */ + u32 lcd1_clk_cfg; /* 0x11c LCD1 module clock */ + u32 reserved15[4]; /* 0x120 */ + u32 mipi_csi_clk_cfg; /* 0x130 MIPI CSI module clock */ + u32 csi_clk_cfg; /* 0x134 CSI module clock */ + u32 reserved16; /* 0x138 */ + u32 ve_clk_cfg; /* 0x13c VE module clock */ + u32 reserved17; /* 0x140 */ + u32 avs_clk_cfg; /* 0x144 AVS module clock */ + u32 reserved18[2]; /* 0x148 */ + u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ + u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */ + u32 reserved19; /* 0x158 */ + u32 mbus_clk_cfg; /* 0x15c MBUS module clock */ + u32 reserved20[2]; /* 0x160 */ + u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */ + u32 reserved21[13]; /* 0x16c */ + u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */ + u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */ + u32 gpu_hyd_clk_cfg; /* 0x1a8 GPU HYD clock config */ + u32 reserved22[21]; /* 0x1ac */ + u32 pll_stable0; /* 0x200 PLL stable time 0 */ + u32 pll_stable1; /* 0x204 PLL stable time 1 */ + u32 reserved23; /* 0x208 */ + u32 pll_stable_status; /* 0x20c PLL stable status register */ + u32 reserved24[4]; /* 0x210 */ + u32 pll1_c0_bias_cfg; /* 0x220 PLL1 c0cpu# Bias config */ + u32 pll2_bias_cfg; /* 0x224 PLL2 audio Bias config */ + u32 pll3_bias_cfg; /* 0x228 PLL3 video Bias config */ + u32 pll4_bias_cfg; /* 0x22c PLL4 ve Bias config */ + u32 pll5_bias_cfg; /* 0x230 PLL5 ddr Bias config */ + u32 pll6_bias_cfg; /* 0x234 PLL6 periph Bias config */ + u32 pll1_c1_bias_cfg; /* 0x238 PLL1 c1cpu# Bias config */ + u32 pll8_bias_cfg; /* 0x23c PLL7 Bias config */ + u32 reserved25; /* 0x240 */ + u32 pll9_bias_cfg; /* 0x244 PLL9 hsic Bias config */ + u32 de_bias_cfg; /* 0x248 display engine Bias config */ + u32 video1_bias_cfg; /* 0x24c pll video1 bias register */ + u32 c0_tuning_cfg; /* 0x250 pll c0cpu# tuning register */ + u32 c1_tuning_cfg; /* 0x254 pll c1cpu# tuning register */ + u32 reserved26[11]; /* 0x258 */ + u32 pll2_pattern_cfg0; /* 0x284 PLL2 Pattern register 0 */ + u32 pll3_pattern_cfg0; /* 0x288 PLL3 Pattern register 0 */ + u32 reserved27; /* 0x28c */ + u32 pll5_pattern_cfg0; /* 0x290 PLL5 Pattern register 0*/ + u32 reserved28[4]; /* 0x294 */ + u32 pll2_pattern_cfg1; /* 0x2a4 PLL2 Pattern register 1 */ + u32 pll3_pattern_cfg1; /* 0x2a8 PLL3 Pattern register 1 */ + u32 reserved29; /* 0x2ac */ + u32 pll5_pattern_cfg1; /* 0x2b0 PLL5 Pattern register 1 */ + u32 reserved30[3]; /* 0x2b4 */ + u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ + u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ + u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */ + u32 reserved31; + u32 ahb_reset3_cfg; /* 0x2d0 AHB1 Reset 3 config */ + u32 reserved32; /* 0x2d4 */ + u32 apb2_reset_cfg; /* 0x2d8 BUS Reset 4 config */ +}; + +/* apb2 bit field */ +#define APB2_CLK_SRC_LOSC (0x0 << 24) +#define APB2_CLK_SRC_OSC24M (0x1 << 24) +#define APB2_CLK_SRC_PLL6 (0x2 << 24) +#define APB2_CLK_SRC_MASK (0x3 << 24) +#define APB2_CLK_RATE_N_1 (0x0 << 16) +#define APB2_CLK_RATE_N_2 (0x1 << 16) +#define APB2_CLK_RATE_N_4 (0x2 << 16) +#define APB2_CLK_RATE_N_8 (0x3 << 16) +#define APB2_CLK_RATE_N_MASK (3 << 16) +#define APB2_CLK_RATE_M(m) (((m)-1) << 0) +#define APB2_CLK_RATE_M_MASK (0x1f << 0) + +/* apb2 gate field */ +#define APB2_GATE_UART_SHIFT (16) +#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT) +#define APB2_GATE_TWI_SHIFT (0) +#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT) + +/* cpu_axi_cfg bits */ +#define AXI0_DIV_SHIFT 0 +#define AXI1_DIV_SHIFT 16 +#define C0_CPUX_CLK_SRC_SHIFT 12 +#define C1_CPUX_CLK_SRC_SHIFT 28 + +#define AXI_DIV_1 0 +#define AXI_DIV_2 1 +#define AXI_DIV_3 2 +#define AXI_DIV_4 3 +#define CPU_CLK_SRC_OSC24M 0 +#define CPU_CLK_SRC_PLL1 1 + +#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0xff) << 8) +#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16) +#define CCM_PLL1_CTRL_EN (0x1 << 31) +#define CMM_PLL1_CLOCK_TIME_2 (0x2 << 24) + +#define PLL8_CFG_DEFAULT 0x42800 +#define CCM_CCI400_CLK_SEL_HSIC (0x2<<24) + +#define CCM_PLL5_DIV1_SHIFT 16 +#define CCM_PLL5_DIV2_SHIFT 18 +#define CCM_PLL5_CTRL_N(n) (((n) - 1) << 8) +#define CCM_PLL5_CTRL_UPD (0x1 << 30) +#define CCM_PLL5_CTRL_EN (0x1 << 31) + +#define PLL6_CFG_DEFAULT 0x80001900 /* 600 MHz */ +#define CCM_PLL6_CTRL_N_SHIFT 8 +#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT) +#define CCM_PLL6_CTRL_DIV1_SHIFT 16 +#define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT) +#define CCM_PLL6_CTRL_DIV2_SHIFT 18 +#define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT) + +#define AHB1_ABP1_DIV_DEFAULT 0x00002190 +#define AHB1_CLK_SRC_MASK (0x3<<12) +#define AHB1_CLK_SRC_INTOSC (0x0<<12) +#define AHB1_CLK_SRC_OSC24M (0x1<<12) +#define AHB1_CLK_SRC_PLL6 (0x2<<12) + +#define AXI_GATE_OFFSET_DRAM 0 + +/* ahb_gate0 offsets */ +#define AHB_GATE_OFFSET_USB_OHCI1 30 +#define AHB_GATE_OFFSET_USB_OHCI0 29 +#define AHB_GATE_OFFSET_USB_EHCI1 27 +#define AHB_GATE_OFFSET_USB_EHCI0 26 +#define AHB_GATE_OFFSET_USB0 24 +#define AHB_GATE_OFFSET_SPI1 21 +#define AHB_GATE_OFFSET_SPI0 20 +#define AHB_GATE_OFFSET_HSTIMER 19 +#define AHB_GATE_OFFSET_EMAC 17 +#define AHB_GATE_OFFSET_MCTL 14 +#define AHB_GATE_OFFSET_GMAC 17 +#define AHB_GATE_OFFSET_NAND0 13 +#define AHB_GATE_OFFSET_MMC0 8 +#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) +#define AHB_GATE_OFFSET_DMA 6 +#define AHB_GATE_OFFSET_SS 5 + +/* ahb_gate1 offsets */ +#define AHB_GATE_OFFSET_DRC0 25 +#define AHB_GATE_OFFSET_DE_FE0 14 +#define AHB_GATE_OFFSET_DE_BE0 12 +#define AHB_GATE_OFFSET_HDMI 11 +#define AHB_GATE_OFFSET_LCD1 5 +#define AHB_GATE_OFFSET_LCD0 4 + +#define CCM_MMC_CTRL_M(x) ((x) - 1) +#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) +#define CCM_MMC_CTRL_N(x) ((x) << 16) +#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) +#define CCM_MMC_CTRL_PLL6 (0x1 << 24) +#define CCM_MMC_CTRL_ENABLE (0x1 << 31) + +#define CCM_USB_CTRL_PHY0_RST (0x1 << 0) +#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) +#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +/* There is no global phy clk gate on sun6i, define as 0 */ +#define CCM_USB_CTRL_PHYGATE 0 +#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) +#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) +#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) + +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) +#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) +#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) + +#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */ + +#define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) << 0) +#define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0) +#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) +#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8) +#define CCM_DRAMCLK_CFG_UPD (0x1 << 16) +#define CCM_DRAMCLK_CFG_RST (0x1 << 31) + +#define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */ +#define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */ +#define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16) + +#define CCM_MBUS_RESET_RESET (0x1 << 31) + +#define CCM_DRAM_GATE_OFFSET_DE_FE0 24 +#define CCM_DRAM_GATE_OFFSET_DE_FE1 25 +#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 +#define CCM_DRAM_GATE_OFFSET_DE_BE1 27 + + +#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6 / 2 */ + +#define MBUS_CLK_GATE (0x1 << 31) + +/* ahb_reset0 offsets */ +#define AHB_RESET_OFFSET_GMAC 17 +#define AHB_RESET_OFFSET_MCTL 14 +#define AHB_RESET_OFFSET_MMC3 11 +#define AHB_RESET_OFFSET_MMC2 10 +#define AHB_RESET_OFFSET_MMC1 9 +#define AHB_RESET_OFFSET_MMC0 8 +#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n)) +#define AHB_RESET_OFFSET_SS 5 + +/* ahb_reset1 offsets */ +#define AHB_RESET_OFFSET_SAT 26 +#define AHB_RESET_OFFSET_DRC0 25 +#define AHB_RESET_OFFSET_DE_FE0 14 +#define AHB_RESET_OFFSET_DE_BE0 12 +#define AHB_RESET_OFFSET_HDMI 11 +#define AHB_RESET_OFFSET_LCD1 5 +#define AHB_RESET_OFFSET_LCD0 4 + +/* ahb_reset2 offsets */ +#define AHB_RESET_OFFSET_LVDS 0 + +/* apb2 reset */ +#define APB2_RESET_UART_SHIFT (16) +#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) +#define APB2_RESET_TWI_SHIFT (0) +#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) + + +#ifndef __ASSEMBLY__ +void clock_set_pll1(unsigned int hz); +void clock_set_pll5(unsigned int clk); +unsigned int clock_get_pll6(void); +#endif + +#endif /* _SUNXI_CLOCK_SUN8I_A83T_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index 273f80f..675876f 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -22,6 +22,10 @@ #include <asm/arch/dram_sun8i_a23.h> #elif defined(CONFIG_MACH_SUN8I_A33) #include <asm/arch/dram_sun8i_a33.h> +#elif defined(CONFIG_MACH_SUN8I_A83T) +#include <asm/arch/dram_sun8i_a83t.h> +#elif defined(CONFIG_MACH_SUN8I_H3) +#include <asm/arch/dram_sun8i_h3.h> #else #include <asm/arch/dram_sun4i.h> #endif diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h new file mode 100644 index 0000000..2891b71 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h @@ -0,0 +1,201 @@ +/* + * Sun8i platform dram controller register and constant defines + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang <wangflord@allwinnertech.com> + * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> + * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_SUN8I_A83T_H +#define _SUNXI_DRAM_SUN8I_A83T_H + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 */ + u32 ccr; /* 0x04 controller configuration register */ + u32 dbgcr; /* 0x08 */ + u8 res0[0x4]; /* 0x0c */ + u32 mcr0_0; /* 0x10 */ + u32 mcr1_0; /* 0x14 */ + u32 mcr0_1; /* 0x18 */ + u32 mcr1_1; /* 0x1c */ + u32 mcr0_2; /* 0x20 */ + u32 mcr1_2; /* 0x24 */ + u32 mcr0_3; /* 0x28 */ + u32 mcr1_3; /* 0x2c */ + u32 mcr0_4; /* 0x30 */ + u32 mcr1_4; /* 0x34 */ + u32 mcr0_5; /* 0x38 */ + u32 mcr1_5; /* 0x3c */ + u32 mcr0_6; /* 0x40 */ + u32 mcr1_6; /* 0x44 */ + u32 mcr0_7; /* 0x48 */ + u32 mcr1_7; /* 0x4c */ + u32 mcr0_8; /* 0x50 */ + u32 mcr1_8; /* 0x54 */ + u32 mcr0_9; /* 0x58 */ + u32 mcr1_9; /* 0x5c */ + u32 mcr0_10; /* 0x60 */ + u32 mcr1_10; /* 0x64 */ + u32 mcr0_11; /* 0x68 */ + u32 mcr1_11; /* 0x6c */ + u32 mcr0_12; /* 0x70 */ + u32 mcr1_12; /* 0x74 */ + u32 mcr0_13; /* 0x78 */ + u32 mcr1_13; /* 0x7c */ + u32 mcr0_14; /* 0x80 */ + u32 mcr1_14; /* 0x84 */ + u32 mcr0_15; /* 0x88 */ + u32 mcr1_15; /* 0x8c */ + u32 bwcr; /* 0x90 */ + u32 maer; /* 0x94 */ + u32 mapr; /* 0x98 */ + u32 mcgcr; /* 0x9c */ + u32 bwctr; /* 0xa0 */ + u8 res2[0x8]; /* 0xa4 */ + u32 swoffr; /* 0xac */ + u8 res3[0x10]; /* 0xb0 */ + u32 swonr; /* 0xc0 */ + u8 res4[0x3c]; /* 0xc4 */ + u32 mdfscr; /* 0x100 */ + u32 mdfsmer; /* 0x104 */ +}; + +struct sunxi_mctl_ctl_reg { + u32 pir; /* 0x00 */ + u32 pwrctl; /* 0x04 */ + u32 mrctrl0; /* 0x08 */ + u32 clken; /* 0x0c */ + u32 pgsr0; /* 0x10 */ + u32 pgsr1; /* 0x14 */ + u32 statr; /* 0x18 */ + u8 res1[0x14]; /* 0x1c */ + u32 mr0; /* 0x30 */ + u32 mr1; /* 0x34 */ + u32 mr2; /* 0x38 */ + u32 mr3; /* 0x3c */ + u32 pllgcr; /* 0x40 */ + u32 ptr0; /* 0x44 */ + u32 ptr1; /* 0x48 */ + u32 ptr2; /* 0x4c */ + u32 ptr3; /* 0x50 */ + u32 ptr4; /* 0x54 */ + u32 dramtmg0; /* 0x58 dram timing parameters register 0 */ + u32 dramtmg1; /* 0x5c dram timing parameters register 1 */ + u32 dramtmg2; /* 0x60 dram timing parameters register 2 */ + u32 dramtmg3; /* 0x64 dram timing parameters register 3 */ + u32 dramtmg4; /* 0x68 dram timing parameters register 4 */ + u32 dramtmg5; /* 0x6c dram timing parameters register 5 */ + u32 dramtmg6; /* 0x70 dram timing parameters register 6 */ + u32 dramtmg7; /* 0x74 dram timing parameters register 7 */ + u32 dramtmg8; /* 0x78 dram timing parameters register 8 */ + u32 odtcfg; /* 0x7c */ + u32 pitmg0; /* 0x80 */ + u32 pitmg1; /* 0x84 */ + u8 res2[0x4]; /* 0x88 */ + u32 rfshctl0; /* 0x8c */ + u32 rfshtmg; /* 0x90 */ + u32 rfshctl1; /* 0x94 */ + u32 pwrtmg; /* 0x98 */ + u8 res3[0x20]; /* 0x9c */ + u32 dqsgmr; /* 0xbc */ + u32 dtcr; /* 0xc0 */ + u32 dtar0; /* 0xc4 */ + u32 dtar1; /* 0xc8 */ + u32 dtar2; /* 0xcc */ + u32 dtar3; /* 0xd0 */ + u32 dtdr0; /* 0xd4 */ + u32 dtdr1; /* 0xd8 */ + u32 dtmr0; /* 0xdc */ + u32 dtmr1; /* 0xe0 */ + u32 dtbmr; /* 0xe4 */ + u32 catr0; /* 0xe8 */ + u32 catr1; /* 0xec */ + u32 dtedr0; /* 0xf0 */ + u32 dtedr1; /* 0xf4 */ + u8 res4[0x8]; /* 0xf8 */ + u32 pgcr0; /* 0x100 */ + u32 pgcr1; /* 0x104 */ + u32 pgcr2; /* 0x108 */ + u32 pgcr3; /* 0x10c */ + u32 iovcr0; /* 0x110 */ + u32 iovcr1; /* 0x114 */ + u32 dqsdr; /* 0x118 */ + u32 dxccr; /* 0x11c */ + u32 odtmap; /* 0x120 */ + u32 zqctl0; /* 0x124 */ + u32 zqctl1; /* 0x128 */ + u8 res6[0x14]; /* 0x12c */ + u32 zqncr; /* 0x140 zq control register 0 */ + u32 zqnpr; /* 0x144 zq control register 1 */ + u32 zqndr; /* 0x148 zq control register 2 */ + u32 zqnsr; /* 0x14c zq status register 0 */ + u32 res7; /* 0x150 zq status register 1 */ + u8 res8[0x6c]; /* 0x154 */ + u32 sched; /* 0x1c0 */ + u32 perfhpr0; /* 0x1c4 */ + u32 perfhpr1; /* 0x1c8 */ + u32 perflpr0; /* 0x1cc */ + u32 perflpr1; /* 0x1d0 */ + u32 perfwr0; /* 0x1d4 */ + u32 perfwr1; /* 0x1d8 */ +}; + + +#define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x) +#define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x) +#define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x) + +#define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x) +#define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x) +#define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x) +#define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x) +#define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x) + +#define CAIOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000210 + 0x4 * (x)) +#define DXnMDLR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000300 + 0x80 * x) +#define DXMDLR0 (SUNXI_DRAM_CTL0_BASE + 0x00000300) +#define DXnLCDLR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000304 + 0x80 * x) +#define DXnLCDLR1(x) (SUNXI_DRAM_CTL0_BASE + 0x00000308 + 0x80 * x) +#define DXnLCDLR2(x) (SUNXI_DRAM_CTL0_BASE + 0x0000030c + 0x80 * x) +#define DATX0IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000310 + 0x4 * x) +#define DATX1IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000390 + 0x4 * x) +#define DATX2IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000410 + 0x4 * x) +#define DATX3IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000490 + 0x4 * x) +#define MX_UPD0 (SUNXI_DRAM_CTL0_BASE + 0x00000880) +#define MX_UPD2 (SUNXI_DRAM_CTL0_BASE + 0x00000888) + +#define MCTL_PROTECT (SUNXI_DRAM_COM_BASE + 0x800) +#define MCTL_MASTER_CFG0(x) (SUNXI_DRAM_COM_BASE + 0x10 + 0x8 * x) +#define MCTL_MASTER_CFG1(x) (SUNXI_DRAM_COM_BASE + 0x14 + 0x8 * x) + +/* + * DRAM common (sunxi_mctl_com_reg) register constants. + */ +#define MCTL_CR_RANK_MASK (3 << 0) +#define MCTL_CR_RANK(x) (((x) - 1) << 0) +#define MCTL_CR_BANK_MASK (3 << 2) +#define MCTL_CR_BANK(x) ((x) << 2) +#define MCTL_CR_ROW_MASK (0xf << 4) +#define MCTL_CR_ROW(x) (((x) - 1) << 4) +#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) +#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) +#define MCTL_CR_BUSW_MASK (7 << 12) +#define MCTL_CR_BUSW8 (0 << 12) +#define MCTL_CR_BUSW16 (1 << 12) +#define MCTL_CR_SEQUENCE (1 << 15) +#define MCTL_CR_DDR3 (3 << 16) +#define MCTL_CR_CHANNEL_MASK (1 << 19) +#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) +#define MCTL_CR_UNKNOWN (0x4 << 20) +#define MCTL_CR_CS1_CONTROL(x) ((x) << 24) + +/* DRAM control (sunxi_mctl_ctl_reg) register constants */ +#define MCTL_MR0 0x1c70 /* CL=11, WR=12 */ +#define MCTL_MR1 0x40 +#define MCTL_MR2 0x18 /* CWL=8 */ +#define MCTL_MR3 0x0 + +#endif /* _SUNXI_DRAM_SUN8I_A83T_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h new file mode 100644 index 0000000..d0f2b8a --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h @@ -0,0 +1,185 @@ +/* + * sun8i H3 platform dram controller register and constant defines + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang <wangflord@allwinnertech.com> + * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> + * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> + * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_SUN8I_H3_H +#define _SUNXI_DRAM_SUN8I_H3_H + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 control register */ + u8 res0[0xc]; /* 0x04 */ + u32 mcr[16][2]; /* 0x10 */ + u32 bwcr; /* 0x90 bandwidth control register */ + u32 maer; /* 0x94 master enable register */ + u32 mapr; /* 0x98 master priority register */ + u32 mcgcr; /* 0x9c */ + u32 cpu_bwcr; /* 0xa0 */ + u32 gpu_bwcr; /* 0xa4 */ + u32 ve_bwcr; /* 0xa8 */ + u32 disp_bwcr; /* 0xac */ + u32 other_bwcr; /* 0xb0 */ + u32 total_bwcr; /* 0xb4 */ + u8 res1[0x8]; /* 0xb8 */ + u32 swonr; /* 0xc0 */ + u32 swoffr; /* 0xc4 */ + u8 res2[0x8]; /* 0xc8 */ + u32 cccr; /* 0xd0 */ + u8 res3[0x72c]; /* 0xd4 */ + u32 protect; /* 0x800 */ +}; + +#define MCTL_CR_BL8 (0x4 << 20) + +#define MCTL_CR_1T (0x1 << 19) +#define MCTL_CR_2T (0x0 << 19) + +#define MCTL_CR_LPDDR3 (0x7 << 16) +#define MCTL_CR_LPDDR2 (0x6 << 16) +#define MCTL_CR_DDR3 (0x3 << 16) +#define MCTL_CR_DDR2 (0x2 << 16) + +#define MCTL_CR_SEQUENTIAL (0x1 << 15) +#define MCTL_CR_INTERLEAVED (0x0 << 15) + +#define MCTL_CR_32BIT (0x1 << 12) +#define MCTL_CR_16BIT (0x0 << 12) +#define MCTL_CR_BUS_WIDTH(x) ((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT) + +#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) +#define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4) +#define MCTL_CR_EIGHT_BANKS (0x1 << 2) +#define MCTL_CR_FOUR_BANKS (0x0 << 2) +#define MCTL_CR_DUAL_RANK (0x1 << 0) +#define MCTL_CR_SINGLE_RANK (0x0 << 0) + +#define PROTECT_MAGIC (0x94be6fa3) + +struct sunxi_mctl_ctl_reg { + u32 pir; /* 0x00 PHY initialization register */ + u32 pwrctl; /* 0x04 */ + u32 mrctrl; /* 0x08 */ + u32 clken; /* 0x0c */ + u32 pgsr[2]; /* 0x10 PHY general status registers */ + u32 statr; /* 0x18 */ + u8 res1[0x14]; /* 0x1c */ + u32 mr[4]; /* 0x30 mode registers */ + u32 pllgcr; /* 0x40 */ + u32 ptr[5]; /* 0x44 PHY timing registers */ + u32 dramtmg[9]; /* 0x58 DRAM timing registers */ + u32 odtcfg; /* 0x7c */ + u32 pitmg[2]; /* 0x80 PHY interface timing registers */ + u8 res2[0x4]; /* 0x88 */ + u32 rfshctl0; /* 0x8c */ + u32 rfshtmg; /* 0x90 refresh timing */ + u32 rfshctl1; /* 0x94 */ + u32 pwrtmg; /* 0x98 */ + u8 res3[0x20]; /* 0x9c */ + u32 dqsgmr; /* 0xbc */ + u32 dtcr; /* 0xc0 */ + u32 dtar[4]; /* 0xc4 */ + u32 dtdr[2]; /* 0xd4 */ + u32 dtmr[2]; /* 0xdc */ + u32 dtbmr; /* 0xe4 */ + u32 catr[2]; /* 0xe8 */ + u32 dtedr[2]; /* 0xf0 */ + u8 res4[0x8]; /* 0xf8 */ + u32 pgcr[4]; /* 0x100 PHY general configuration registers */ + u32 iovcr[2]; /* 0x110 */ + u32 dqsdr; /* 0x118 */ + u32 dxccr; /* 0x11c */ + u32 odtmap; /* 0x120 */ + u32 zqctl[2]; /* 0x124 */ + u8 res6[0x14]; /* 0x12c */ + u32 zqcr; /* 0x140 ZQ control register */ + u32 zqsr; /* 0x144 ZQ status register */ + u32 zqdr[3]; /* 0x148 ZQ data registers */ + u8 res7[0x6c]; /* 0x154 */ + u32 sched; /* 0x1c0 */ + u32 perfhpr[2]; /* 0x1c4 */ + u32 perflpr[2]; /* 0x1cc */ + u32 perfwr[2]; /* 0x1d4 */ + u8 res8[0x2c]; /* 0x1dc */ + u32 aciocr; /* 0x208 */ + u8 res9[0xf4]; /* 0x20c */ + struct { /* 0x300 DATX8 modules*/ + u32 mdlr; /* 0x00 */ + u32 lcdlr[3]; /* 0x04 */ + u32 iocr[11]; /* 0x10 IO configuration register */ + u32 bdlr6; /* 0x3c */ + u32 gtr; /* 0x40 */ + u32 gcr; /* 0x44 */ + u32 gsr[3]; /* 0x48 */ + u8 res0[0x2c]; /* 0x54 */ + } datx[4]; + u8 res10[0x388]; /* 0x500 */ + u32 upd2; /* 0x888 */ +}; + +#define PTR3_TDINIT1(x) ((x) << 20) +#define PTR3_TDINIT0(x) ((x) << 0) + +#define PTR4_TDINIT3(x) ((x) << 20) +#define PTR4_TDINIT2(x) ((x) << 0) + +#define DRAMTMG0_TWTP(x) ((x) << 24) +#define DRAMTMG0_TFAW(x) ((x) << 16) +#define DRAMTMG0_TRAS_MAX(x) ((x) << 8) +#define DRAMTMG0_TRAS(x) ((x) << 0) + +#define DRAMTMG1_TXP(x) ((x) << 16) +#define DRAMTMG1_TRTP(x) ((x) << 8) +#define DRAMTMG1_TRC(x) ((x) << 0) + +#define DRAMTMG2_TCWL(x) ((x) << 24) +#define DRAMTMG2_TCL(x) ((x) << 16) +#define DRAMTMG2_TRD2WR(x) ((x) << 8) +#define DRAMTMG2_TWR2RD(x) ((x) << 0) + +#define DRAMTMG3_TMRW(x) ((x) << 16) +#define DRAMTMG3_TMRD(x) ((x) << 12) +#define DRAMTMG3_TMOD(x) ((x) << 0) + +#define DRAMTMG4_TRCD(x) ((x) << 24) +#define DRAMTMG4_TCCD(x) ((x) << 16) +#define DRAMTMG4_TRRD(x) ((x) << 8) +#define DRAMTMG4_TRP(x) ((x) << 0) + +#define DRAMTMG5_TCKSRX(x) ((x) << 24) +#define DRAMTMG5_TCKSRE(x) ((x) << 16) +#define DRAMTMG5_TCKESR(x) ((x) << 8) +#define DRAMTMG5_TCKE(x) ((x) << 0) + +#define RFSHTMG_TREFI(x) ((x) << 16) +#define RFSHTMG_TRFC(x) ((x) << 0) + +#define PIR_CLRSR (0x1 << 27) /* clear status registers */ +#define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */ +#define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */ +#define PIR_DRAMRST (0x1 << 7) /* DRAM reset */ +#define PIR_PHYRST (0x1 << 6) /* PHY reset */ +#define PIR_DCAL (0x1 << 5) /* DDL calibration */ +#define PIR_PLLINIT (0x1 << 4) /* PLL initialization */ +#define PIR_ZCAL (0x1 << 1) /* ZQ calibration */ +#define PIR_INIT (0x1 << 0) /* PHY initialization trigger */ + +#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */ + +#define ZQCR_PWRDOWN (0x1 << 31) /* ZQ power down */ + +#define DATX_IOCR_DQ(x) (x) /* DQ0-7 IOCR index */ +#define DATX_IOCR_DM (8) /* DM IOCR index */ +#define DATX_IOCR_DQS (9) /* DQS IOCR index */ +#define DATX_IOCR_DQSN (10) /* DQSN IOCR index */ + +#define DATX_IOCR_WRITE_DELAY(x) ((x) << 8) +#define DATX_IOCR_READ_DELAY(x) ((x) << 0) + +#endif /* _SUNXI_DRAM_SUN8I_H3_H */ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 8382101..a2a9a38 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -147,6 +147,7 @@ enum sunxi_gpio_number { #define SUN7I_GPA_GMAC 5 #define SUN6I_GPA_SDC2 5 #define SUN6I_GPA_SDC3 4 +#define SUN8I_H3_GPA_UART0 2 #define SUN4I_GPB_TWI0 2 #define SUN4I_GPB_TWI1 2 @@ -157,6 +158,7 @@ enum sunxi_gpio_number { #define SUN5I_GPB_UART0 2 #define SUN8I_GPB_UART2 2 #define SUN8I_A33_GPB_UART0 3 +#define SUN8I_A83T_GPB_UART0 2 #define SUNXI_GPC_NAND 2 #define SUNXI_GPC_SDC2 3 diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 0f03c24..bbf89d9 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -8,9 +8,6 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H -#define ZYNQ_SERIAL_BASEADDR0 0xFF000000 -#define ZYNQ_SERIAL_BASEADDR1 0xFF001000 - #define ZYNQ_GEM_BASEADDR0 0xFF0B0000 #define ZYNQ_GEM_BASEADDR1 0xFF0C0000 #define ZYNQ_GEM_BASEADDR2 0xFF0D0000 @@ -22,9 +19,6 @@ #define ZYNQ_I2C_BASEADDR0 0xFF020000 #define ZYNQ_I2C_BASEADDR1 0xFF030000 -#define ZYNQ_SDHCI_BASEADDR0 0xFF160000 -#define ZYNQ_SDHCI_BASEADDR1 0xFF170000 - #define ZYNQMP_SATA_BASEADDR 0xFD0C0000 #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index f1e95a2..021626d 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -13,7 +13,6 @@ static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) { } -int zynq_sdhci_init(phys_addr_t regbase); int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h index d2aa1c4..200444d 100644 --- a/arch/arm/include/asm/armv7m.h +++ b/arch/arm/include/asm/armv7m.h @@ -3,7 +3,7 @@ * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index d8d9af4..2e2a3a8 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -119,7 +119,7 @@ void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type, - u64 share); + u64 attribute); void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr); diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index f2d4c3c..806302b 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -11,13 +11,17 @@ #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_DM #define CONFIG_RSA #define CONFIG_RSA_FREESCALE_EXP + #ifndef CONFIG_FSL_CAAM #define CONFIG_FSL_CAAM #endif +#ifndef CONFIG_DM +#define CONFIG_DM +#endif + #define CONFIG_KEY_REVOCATION #ifndef CONFIG_SYS_RAMBOOT /* The key used for verification of next level images diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 4e3ea55..bd27281 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -46,7 +46,7 @@ struct arch_global_data { u32 omap_boot_mode; u8 omap_ch_flags; #endif -#ifdef CONFIG_FSL_LSCH3 +#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR) unsigned long mem2_clk; #endif }; diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index ee56d74..a477cae 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -290,7 +290,10 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) s = getenv("machid"); if (s) { - strict_strtoul(s, 16, &machid); + if (strict_strtoul(s, 16, &machid) < 0) { + debug("strict_strtoul failed!\n"); + return; + } printf("Using machid 0x%lx from environment\n", machid); } diff --git a/arch/arm/lib/interrupts_m.c b/arch/arm/lib/interrupts_m.c index 89ce493..8a36c18 100644 --- a/arch/arm/lib/interrupts_m.c +++ b/arch/arm/lib/interrupts_m.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/lib/vectors_m.S b/arch/arm/lib/vectors_m.S index abc7f88..cf14a34 100644 --- a/arch/arm/lib/vectors_m.S +++ b/arch/arm/lib/vectors_m.S @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index fdaf328..c333647 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -71,6 +71,10 @@ config TARGET_AT91SAM9X5EK select CPU_ARM926EJS select SUPPORT_SPL +config TARGET_SAMA5D2_XPLAINED + bool "SAMA5D2 Xplained board" + select CPU_V7 + config TARGET_SAMA5D3_XPLAINED bool "SAMA5D3 Xplained board" select CPU_V7 @@ -123,6 +127,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig" source "board/atmel/at91sam9n12ek/Kconfig" source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" +source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" source "board/atmel/sama5d4_xplained/Kconfig" diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 30f2b49..5b89617 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -10,7 +10,7 @@ obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o -obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o +obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o obj-y += spl.o endif diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index f4f35a4..9538bc1 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -8,6 +8,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_SAMA5D2) += sama5d2_devices.o obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o obj-y += clock.o diff --git a/arch/arm/mach-at91/armv7/sama5d2_devices.c b/arch/arm/mach-at91/armv7/sama5d2_devices.c new file mode 100644 index 0000000..88f8f2c --- /dev/null +++ b/arch/arm/mach-at91/armv7/sama5d2_devices.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Wenyou Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> +#include <asm/arch/sama5d2.h> + +char *get_cpu_name() +{ + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_sama5d2()) { + switch (extension_id) { + case ARCH_EXID_SAMA5D21CU: + return "SAMA5D21"; + case ARCH_EXID_SAMA5D22CU: + return "SAMA5D22-CU"; + case ARCH_EXID_SAMA5D22CN: + return "SAMA5D22-CN"; + case ARCH_EXID_SAMA5D23CU: + return "SAMA5D23-CU"; + case ARCH_EXID_SAMA5D24CX: + return "SAMA5D24-CX"; + case ARCH_EXID_SAMA5D24CU: + return "SAMA5D24-CU"; + case ARCH_EXID_SAMA5D26CU: + return "SAMA5D26-CU"; + case ARCH_EXID_SAMA5D27CU: + return "SAMA5D27-CU"; + case ARCH_EXID_SAMA5D27CN: + return "SAMA5D27-CN"; + case ARCH_EXID_SAMA5D28CU: + return "SAMA5D28-CU"; + case ARCH_EXID_SAMA5D28CN: + return "SAMA5D28-CN"; + } + } + + return "Unknown CPU type"; +} + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +void at91_udp_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + + at91_periph_clk_enable(ATMEL_ID_UDPHS); +} +#endif diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c b/arch/arm/mach-at91/armv7/sama5d4_devices.c index 76301d6..ce33cd4 100644 --- a/arch/arm/mach-at91/armv7/sama5d4_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c @@ -10,7 +10,6 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> -#include <asm/arch/sama5_matrix.h> #include <asm/arch/sama5_sfr.h> #include <asm/arch/sama5d4.h> @@ -46,57 +45,3 @@ void at91_udp_hw_init(void) at91_periph_clk_enable(ATMEL_ID_UDPHS); } #endif - -#ifdef CONFIG_SPL_BUILD -void matrix_init(void) -{ - struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0; - struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1; - int i; - - /* Disable the write protect */ - writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr); - writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr); - - /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */ - for (i = 4; i <= 10; i++) { - writel(0x000f0f0f, &h64mx->ssr[i]); - writel(0x0000ffff, &h64mx->sassr[i]); - writel(0x0000000f, &h64mx->srtsr[i]); - } - - /* CS3 */ - writel(0x00c0c0c0, &h32mx->ssr[3]); - writel(0xff000000, &h32mx->sassr[3]); - writel(0xff000000, &h32mx->srtsr[3]); - - /* NFC SRAM */ - writel(0x00010101, &h32mx->ssr[4]); - writel(0x00000001, &h32mx->sassr[4]); - writel(0x00000001, &h32mx->srtsr[4]); - - /* Configure Programmable Security peripherals on matrix 64 */ - writel(readl(&h64mx->spselr[0]) | 0x00080000, &h64mx->spselr[0]); - writel(readl(&h64mx->spselr[1]) | 0x00180000, &h64mx->spselr[1]); - writel(readl(&h64mx->spselr[2]) | 0x00000008, &h64mx->spselr[2]); - - /* Configure Programmable Security peripherals on matrix 32 */ - writel(readl(&h32mx->spselr[0]) | 0xFFC00000, &h32mx->spselr[0]); - writel(readl(&h32mx->spselr[1]) | 0x60E3FFFF, &h32mx->spselr[1]); - - /* Enable the write protect */ - writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr); - writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr); -} - -void redirect_int_from_saic_to_aic(void) -{ - struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; - u32 key32; - - if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) { - key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY; - writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir); - } -} -#endif diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c new file mode 100644 index 0000000..2bccb84 --- /dev/null +++ b/arch/arm/mach-at91/atmel_sfr.c @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Wenyou Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sama5_sfr.h> + +void redirect_int_from_saic_to_aic(void) +{ + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + u32 key32; + + if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) { + key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY; + writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir); + } +} diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 5a51be6..3f50f77 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -78,7 +78,8 @@ typedef struct at91_pmc { #define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) #define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) #define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14) -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \ + defined(CONFIG_SAMA5D4) #define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18) #else #define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16) @@ -97,7 +98,8 @@ typedef struct at91_pmc { #define AT91_PMC_MCKR_CSS_PLLB 0x00000003 #define AT91_PMC_MCKR_CSS_MASK 0x00000003 -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ +#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \ + defined(CONFIG_SAMA5D4) || \ defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) #define AT91_PMC_MCKR_PRES_1 0x00000000 #define AT91_PMC_MCKR_PRES_2 0x00000010 @@ -127,10 +129,7 @@ typedef struct at91_pmc { #else #define AT91_PMC_MCKR_MDIV_1 0x00000000 #define AT91_PMC_MCKR_MDIV_2 0x00000100 -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ - defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) #define AT91_PMC_MCKR_MDIV_3 0x00000300 -#endif #define AT91_PMC_MCKR_MDIV_4 0x00000200 #define AT91_PMC_MCKR_MDIV_MASK 0x00000300 #endif diff --git a/arch/arm/mach-at91/include/mach/atmel_pio4.h b/arch/arm/mach-at91/include/mach/atmel_pio4.h new file mode 100644 index 0000000..8bb4b12 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/atmel_pio4.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2015 Atmel Corporation. + * Wenyou Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ATMEL_PIO4_H +#define __ATMEL_PIO4_H + +#ifndef __ASSEMBLY__ + +struct atmel_pio4_port { + u32 mskr; /* 0x00 PIO Mask Register */ + u32 cfgr; /* 0x04 PIO Configuration Register */ + u32 pdsr; /* 0x08 PIO Pin Data Status Register */ + u32 locksr; /* 0x0C PIO Lock Status Register */ + u32 sodr; /* 0x10 PIO Set Output Data Register */ + u32 codr; /* 0x14 PIO Clear Output Data Register */ + u32 odsr; /* 0x18 PIO Output Data Status Register */ + u32 reserved0; + u32 ier; /* 0x20 PIO Interrupt Enable Register */ + u32 idr; /* 0x24 PIO Interrupt Disable Register */ + u32 imr; /* 0x28 PIO Interrupt Mask Register */ + u32 isr; /* 0x2C PIO Interrupt Status Register */ + u32 reserved1[3]; + u32 iofr; /* 0x3C PIO I/O Freeze Register */ +}; + +#endif + +#define AT91_PIO_PORTA 0x0 +#define AT91_PIO_PORTB 0x1 +#define AT91_PIO_PORTC 0x2 +#define AT91_PIO_PORTD 0x3 + +int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value); +int atmel_pio4_get_pio_input(u32 port, u32 pin); + +#endif diff --git a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h index 38b5012..46a329b 100644 --- a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h +++ b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h @@ -31,7 +31,8 @@ static struct usba_ep_data usba_udc_ep[] = { EP("ep5", 5, 1024, 3, 1, 1), EP("ep6", 6, 1024, 3, 1, 1), }; -#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#elif defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \ + defined(CONFIG_SAMA5D4) static struct usba_ep_data usba_udc_ep[] = { EP("ep0", 0, 64, 1, 0, 0), EP("ep1", 1, 1024, 3, 1, 0), diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index ff6b71b..38abfda 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -23,6 +23,8 @@ # include <asm/arch/at91sam9g45.h> #elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5) # include <asm/arch/at91sam9x5.h> +#elif defined(CONFIG_SAMA5D2) +# include <asm/arch/sama5d2.h> #elif defined(CONFIG_SAMA5D3) # include <asm/arch/sama5d3.h> #elif defined(CONFIG_SAMA5D4) diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h index 3081d37..7b19a20 100644 --- a/arch/arm/mach-at91/include/mach/sama5_sfr.h +++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h @@ -32,7 +32,6 @@ struct atmel_sfr { #define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000 /* Bit field in AICREDIR */ -#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102 #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001 #endif diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h new file mode 100644 index 0000000..c85571c --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -0,0 +1,203 @@ +/* + * Chip-specific header file for the SAMA5D2 SoC + * + * Copyright (C) 2015 Atmel + * Wenyou Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SAMA5D2_H +#define __SAMA5D2_H + +/* + * definitions to be used in other places + */ +#define CONFIG_AT91FAMILY /* It's a member of AT91 */ + +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FIQ 0 /* FIQ Interrupt ID */ +/* 1 */ +#define ATMEL_ID_ARM 2 /* Performance Monitor Unit */ +#define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */ +#define ATMEL_ID_WDT 4 /* Watchdog Timer Interrupt */ +#define ATMEL_ID_GMAC 5 /* Ethernet MAC */ +#define ATMEL_ID_XDMAC0 6 /* DMA Controller 0 */ +#define ATMEL_ID_XDMAC1 7 /* DMA Controller 1 */ +#define ATMEL_ID_ICM 8 /* Integrity Check Monitor */ +#define ATMEL_ID_AES 9 /* Advanced Encryption Standard */ +#define ATMEL_ID_AESB 10 /* AES bridge */ +#define ATMEL_ID_TDES 11 /* Triple Data Encryption Standard */ +#define ATMEL_ID_SHA 12 /* SHA Signature */ +#define ATMEL_ID_MPDDRC 13 /* MPDDR Controller */ +#define ATMEL_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */ +#define ATMEL_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */ +#define ATMEL_ID_SECUMOD 16 /* Secure Module */ +#define ATMEL_ID_HSMC 17 /* Multi-bit ECC interrupt */ +#define ATMEL_ID_PIOA 18 /* Parallel I/O Controller A */ +#define ATMEL_ID_FLEXCOM0 19 /* FLEXCOM0 */ +#define ATMEL_ID_FLEXCOM1 20 /* FLEXCOM1 */ +#define ATMEL_ID_FLEXCOM2 21 /* FLEXCOM2 */ +#define ATMEL_ID_FLEXCOM3 22 /* FLEXCOM3 */ +#define ATMEL_ID_FLEXCOM4 23 /* FLEXCOM4 */ +#define ATMEL_ID_UART0 24 /* UART0 */ +#define ATMEL_ID_UART1 25 /* UART1 */ +#define ATMEL_ID_UART2 26 /* UART2 */ +#define ATMEL_ID_UART3 27 /* UART3 */ +#define ATMEL_ID_UART4 28 /* UART4 */ +#define ATMEL_ID_TWIHS0 29 /* Two-wire Interface 0 */ +#define ATMEL_ID_TWIHS1 30 /* Two-wire Interface 1 */ +#define ATMEL_ID_SDMMC0 31 /* Secure Data Memory Card Controller 0 */ +#define ATMEL_ID_SDMMC1 32 /* Secure Data Memory Card Controller 1 */ +#define ATMEL_ID_SPI0 33 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 34 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */ +#define ATMEL_ID_TC1 36 /* Timer Counter 1 (ch.3,4,5) */ +/* 37 */ +#define ATMEL_ID_PWM 38 /* PWMController0 (ch. 0,1,2,3) */ +/* 39 */ +#define ATMEL_ID_ADC 40 /* Touch Screen ADC Controller */ +#define ATMEL_ID_UHPHS 41 /* USB Host High Speed */ +#define ATMEL_ID_UDPHS 42 /* USB Device High Speed */ +#define ATMEL_ID_SSC0 43 /* Serial Synchronous Controller 0 */ +#define ATMEL_ID_SSC1 44 /* Serial Synchronous Controller 1 */ +#define ATMEL_ID_LCDC 45 /* LCD Controller */ +#define ATMEL_ID_ISI 46 /* Image Sensor Controller, for A5D2, named after ISC */ +#define ATMEL_ID_TRNG 47 /* True Random Number Generator */ +#define ATMEL_ID_PDMIC 48 /* PDM Interface Controller */ +#define ATMEL_ID_AIC_IRQ 49 /* IRQ Interrupt ID */ +#define ATMEL_ID_SFC 50 /* Fuse Controller */ +#define ATMEL_ID_SECURAM 51 /* Secure RAM */ +#define ATMEL_ID_QSPI0 52 /* QSPI0 */ +#define ATMEL_ID_QSPI1 53 /* QSPI1 */ +#define ATMEL_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */ +#define ATMEL_ID_I2SC1 55 /* Inter-IC Sound Controller 1 */ +#define ATMEL_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */ +#define ATMEL_ID_CAN1_INT0 57 /* MCAN 1 Interrupt0 */ +/* 58 */ +#define ATMEL_ID_CLASSD 59 /* Audio Class D Amplifier */ +#define ATMEL_ID_SFR 60 /* Special Function Register */ +#define ATMEL_ID_SAIC 61 /* Secured AIC */ +#define ATMEL_ID_AIC 62 /* Advanced Interrupt Controller */ +#define ATMEL_ID_L2CC 63 /* L2 Cache Controller */ +#define ATMEL_ID_CAN0_INT1 64 /* MCAN 0 Interrupt1 */ +#define ATMEL_ID_CAN1_INT1 65 /* MCAN 1 Interrupt1 */ +#define ATMEL_ID_GMAC_Q1 66 /* GMAC Queue 1 Interrupt */ +#define ATMEL_ID_GMAC_Q2 67 /* GMAC Queue 2 Interrupt */ +#define ATMEL_ID_PIOB 68 /* Parallel I/O Controller B */ +#define ATMEL_ID_PIOC 69 /* Parallel I/O Controller C */ +#define ATMEL_ID_PIOD 70 /* Parallel I/O Controller D */ +#define ATMEL_ID_SDMMC0_TIMER 71 /* Secure Data Memory Card Controller 0 (TIMER) */ +#define ATMEL_ID_SDMMC1_TIMER 72 /* Secure Data Memory Card Controller 1 (TIMER) */ +/* 73 */ +#define ATMEL_ID_SYS 74 /* System Controller Interrupt */ +#define ATMEL_ID_ACC 75 /* Analog Comparator */ +#define ATMEL_ID_RXLP 76 /* UART Low-Power */ +#define ATMEL_ID_SFRBU 77 /* Special Function Register BackUp */ +#define ATMEL_ID_CHIPID 78 /* Chip ID */ + +/* + * User Peripherals physical base addresses. + */ +#define ATMEL_BASE_LCDC 0xf0000000 +#define ATMEL_BASE_XDMAC1 0xf0004000 +#define ATMEL_BASE_MPDDRC 0xf000c000 +#define ATMEL_BASE_XDMAC0 0xf0010000 +#define ATMEL_BASE_PMC 0xf0014000 +#define ATMEL_BASE_QSPI0 0xf0020000 +#define ATMEL_BASE_QSPI1 0xf0024000 +#define ATMEL_BASE_SPI0 0xf8000000 +#define ATMEL_BASE_GMAC 0xf8008000 +#define ATMEL_BASE_TC0 0xf800c000 +#define ATMEL_BASE_TC1 0xf8010000 +#define ATMEL_BASE_HSMC 0xf8014000 +#define ATMEL_BASE_UART0 0xf801c000 +#define ATMEL_BASE_UART1 0xf8020000 +#define ATMEL_BASE_UART2 0xf8024000 +#define ATMEL_BASE_TWI0 0xf8028000 +#define ATMEL_BASE_SYSC 0xf8048000 +#define ATMEL_BASE_SPI1 0xfc000000 +#define ATMEL_BASE_UART3 0xfc008000 +#define ATMEL_BASE_UART4 0xfc00c000 +#define ATMEL_BASE_TWI1 0xfc028000 +#define ATMEL_BASE_UDPHS 0xfc02c000 + +#define ATMEL_BASE_PIOA 0xfc038000 + +#define ATMEL_CHIPID_CIDR 0xfc069000 +#define ATMEL_CHIPID_EXID 0xfc069004 + +/* + * Address Memory Space + */ +#define ATMEL_BASE_DDRCS 0x20000000 +#define ATMEL_BASE_QSPI0_AES_MEM 0x90000000 +#define ATMEL_BASE_QSPI1_AES_MEM 0x98000000 +#define ATMEL_BASE_SDMMC0 0xa0000000 +#define ATMEL_BASE_SDMMC1 0xb0000000 +#define ATMEL_BASE_QSPI0_MEM 0xd0000000 +#define ATMEL_BASE_QSPI1_MEM 0xd8000000 + +/* + * Internal Memories + */ +#define ATMEL_BASE_UDPHS_FIFO 0x00300000 /* USB Device HS controller */ +#define ATMEL_BASE_OHCI 0x00400000 /* USB Host controller (OHCI) */ +#define ATMEL_BASE_EHCI 0x00500000 /* USB Host controller (EHCI) */ + +/* + * SYSC Spawns + */ +#define ATMEL_BASE_RSTC ATMEL_BASE_SYSC +#define ATMEL_BASE_SHDWC (ATMEL_BASE_SYSC + 0x10) +#define ATMEL_BASE_PIT (ATMEL_BASE_SYSC + 0x30) +#define ATMEL_BASE_WDT (ATMEL_BASE_SYSC + 0x40) +#define ATMEL_BASE_SCKC (ATMEL_BASE_SYSC + 0x50) +#define ATMEL_BASE_RTC (ATMEL_BASE_SYSC + 0xb0) + +/* + * Other misc definitions + */ +#define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70) +#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500) + +#define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40) +#define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40) +#define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40) + +#define ATMEL_PIO_PORTS 4 +#define CPU_HAS_PCR +#define CPU_HAS_H32MXDIV + +/* SAMA5D2 series chip id definitions */ +#define ARCH_ID_SAMA5D2 0x8a5c08c0 +#define ARCH_EXID_SAMA5D21CU 0x0000005a +#define ARCH_EXID_SAMA5D22CU 0x00000059 +#define ARCH_EXID_SAMA5D22CN 0x00000069 +#define ARCH_EXID_SAMA5D23CU 0x00000058 +#define ARCH_EXID_SAMA5D24CX 0x00000004 +#define ARCH_EXID_SAMA5D24CU 0x00000014 +#define ARCH_EXID_SAMA5D26CU 0x00000012 +#define ARCH_EXID_SAMA5D27CU 0x00000011 +#define ARCH_EXID_SAMA5D27CN 0x00000021 +#define ARCH_EXID_SAMA5D28CU 0x00000010 +#define ARCH_EXID_SAMA5D28CN 0x00000020 + +#define cpu_is_sama5d2() (get_chip_id() == ARCH_ID_SAMA5D2) + +/* PIT Timer(PIT_PIIR) */ +#define CONFIG_SYS_TIMER_COUNTER 0xf804803c + +/* No PMECC Galois table in ROM */ +#define NO_GALOIS_TABLE_IN_ROM + +#ifndef __ASSEMBLY__ +unsigned int get_chip_id(void); +unsigned int get_extension_chip_id(void); +unsigned int has_lcdc(void); +char *get_cpu_name(void); +#endif + +#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h index 3da8aff..90085da 100644 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ b/arch/arm/mach-at91/include/mach/sama5d4.h @@ -179,6 +179,34 @@ #define CPU_HAS_PCR #define CPU_HAS_H32MXDIV +/* MATRIX0(H64MX) slave id definitions */ +#define H64MX_SLAVE_AXIMX_BRIDGE 0 /* Bridge from H64MX to AXIMX */ +#define H64MX_SLAVE_PERIPH_BRIDGE 1 /* H64MX Peripheral Bridge */ +#define H64MX_SLAVE_VDEC 2 /* Video Decoder */ +#define H64MX_SLAVE_DDRC_PORT0 3 /* DDR2 Port0-AESOTF */ +#define H64MX_SLAVE_DDRC_PORT1 4 /* DDR2 Port1 */ +#define H64MX_SLAVE_DDRC_PORT2 5 /* DDR2 Port2 */ +#define H64MX_SLAVE_DDRC_PORT3 6 /* DDR2 Port3 */ +#define H64MX_SLAVE_DDRC_PORT4 7 /* DDR2 Port4 */ +#define H64MX_SLAVE_DDRC_PORT5 8 /* DDR2 Port5 */ +#define H64MX_SLAVE_DDRC_PORT6 9 /* DDR2 Port6 */ +#define H64MX_SLAVE_DDRC_PORT7 10 /* DDR2 Port7 */ +#define H64MX_SLAVE_SRAM 11 /* Internal SRAM 128K */ +#define H64MX_SLAVE_H32MX_BRIDGE 12 /* Bridge from H64MX to H32MX */ + +/* MATRIX1(H32MX) slave id definitions */ +#define H32MX_SLAVE_H64MX_BRIDGE 0 /* Bridge from H32MX to H64MX */ +#define H32MX_SLAVE_PERIPH_BRIDGE0 1 /* H32MX Peripheral Bridge 0 */ +#define H32MX_SLAVE_PERIPH_BRIDGE1 2 /* H32MX Peripheral Bridge 1 */ +#define H32MX_SLAVE_EBI 3 /* External Bus Interface */ +#define H32MX_SLAVE_NFC_CMD 3 /* NFC command Register */ +#define H32MX_SLAVE_NFC_SRAM 4 /* NFC SRAM */ +#define H32MX_SLAVE_USB 5 /* USB Device & Host */ +#define H32MX_SLAVE_SMD 6 /* Soft Modem (SMD) */ + +/* AICREDIR Unlock Key */ +#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102 + /* sama5d4 series chip id definitions */ #define ARCH_ID_SAMA5D4 0x8a5c07c0 #define ARCH_EXID_SAMA5D41 0x00000001 diff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c new file mode 100644 index 0000000..57d7270 --- /dev/null +++ b/arch/arm/mach-at91/matrix.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Wenyou Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sama5_matrix.h> + +void matrix_init(void) +{ + struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0; + struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1; + int i; + + /* DDR port 1 ~ port 7 */ + for (i = H64MX_SLAVE_DDRC_PORT1; i <= H64MX_SLAVE_DDRC_PORT7; i++) { + writel(0x000f0f0f, &h64mx->ssr[i]); + writel(0x0000ffff, &h64mx->sassr[i]); + writel(0x0000000f, &h64mx->srtsr[i]); + } + + /* EBI CS3 (NANDFlash 128M) and NFC Command Registers(128M) */ + writel(0x00c0c0c0, &h32mx->ssr[H32MX_SLAVE_EBI]); + writel(0xff000000, &h32mx->sassr[H32MX_SLAVE_EBI]); + writel(0xff000000, &h32mx->srtsr[H32MX_SLAVE_EBI]); + + /* NFC SRAM */ + writel(0x00010101, &h32mx->ssr[H32MX_SLAVE_NFC_SRAM]); + writel(0x00000001, &h32mx->sassr[H32MX_SLAVE_NFC_SRAM]); + writel(0x00000001, &h32mx->srtsr[H32MX_SLAVE_NFC_SRAM]); +} diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index 9260ee2..af94dff 100644 --- a/arch/arm/mach-bcm283x/include/mach/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -125,34 +125,6 @@ struct bcm2835_mbox_tag_hdr { #define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002 -#ifdef CONFIG_BCM2836 -#define BCM2836_BOARD_REV_2_B 0x4 -#else -/* - * 0x2..0xf from: - * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/ - * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733 - * http://git.drogon.net/?p=wiringPi;a=blob_plain;f=wiringPi/wiringPi.c;hb=5edd177112c99416f68ba3e8c6c4db6ed942e796 - */ -#define BCM2835_BOARD_REV_B_I2C0_2 0x2 -#define BCM2835_BOARD_REV_B_I2C0_3 0x3 -#define BCM2835_BOARD_REV_B_I2C1_4 0x4 -#define BCM2835_BOARD_REV_B_I2C1_5 0x5 -#define BCM2835_BOARD_REV_B_I2C1_6 0x6 -#define BCM2835_BOARD_REV_A_7 0x7 -#define BCM2835_BOARD_REV_A_8 0x8 -#define BCM2835_BOARD_REV_A_9 0x9 -#define BCM2835_BOARD_REV_B_REV2_d 0xd -#define BCM2835_BOARD_REV_B_REV2_e 0xe -#define BCM2835_BOARD_REV_B_REV2_f 0xf -#define BCM2835_BOARD_REV_B_PLUS 0x10 -#define BCM2835_BOARD_REV_CM 0x11 -#define BCM2835_BOARD_REV_A_PLUS 0x12 -#define BCM2835_BOARD_REV_B_PLUS_13 0x13 -#define BCM2835_BOARD_REV_CM_14 0x14 -#define BCM2835_BOARD_REV_A_PLUS_15 0x15 -#endif - struct bcm2835_mbox_tag_get_board_rev { struct bcm2835_mbox_tag_hdr tag_hdr; union { diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index f7737bf..9205b1e 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -49,6 +49,9 @@ config TARGET_GOFLEXHOME config TARGET_NAS220 bool "BlackArmor NAS220" +config TARGET_NSA310S + bool "Zyxel NSA310S" + endchoice config SYS_SOC @@ -69,5 +72,6 @@ source "board/raidsonic/ib62x0/Kconfig" source "board/Seagate/dockstar/Kconfig" source "board/Seagate/goflexhome/Kconfig" source "board/Seagate/nas220/Kconfig" +source "board/zyxel/nsa310s/Kconfig" endif diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 9dde710..1d49cab 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -70,6 +70,8 @@ #define CONFIG_PHYLIB #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ #define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ +#define CONFIG_ARP_TIMEOUT 200 +#define CONFIG_NET_RETRY_COUNT 50 #endif /* CONFIG_CMD_NET */ /* diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index ab50f4e..d3bddb7 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -9,11 +9,19 @@ config ROCKCHIP_RK3288 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs. +config ROCKCHIP_RK3036 + bool "Support Rockchip RK3036" + help + The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 + including NEON and GPU, Mali-400 graphics, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. + config SYS_MALLOC_F default y -config SYS_MALLOC_F_LEN - default 0x800 +config SPL_SYS_MALLOC_SIMPLE + default y config SPL_DM default y @@ -33,9 +41,6 @@ config DM_I2C config DM_GPIO default y -config ROCKCHIP_SERIAL - default y - source "arch/arm/mach-rockchip/rk3288/Kconfig" - +source "arch/arm/mach-rockchip/rk3036/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 5a4e383..b703c3c 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -5,9 +5,13 @@ # ifdef CONFIG_SPL_BUILD -obj-y += board-spl.o +obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o else -obj-y += board.o +obj-$(CONFIG_ROCKCHIP_RK3288) += board.o endif -obj-y += common.o +obj-y += rk_timer.o +obj-y += rk_early_print.o +obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ +obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 688bc0f..f026abf 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -7,6 +7,7 @@ #include <common.h> #include <dm.h> #include <ram.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c new file mode 100644 index 0000000..3a1491c --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/grf_rk3036.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sdram_rk3036.h> +#include <asm/arch/timer.h> +#include <asm/arch/uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define GRF_BASE 0x20008000 +static struct rk3036_grf * const grf = (void *)GRF_BASE; + +#define DEBUG_UART_BASE 0x20068000 + +extern void back_to_bootrom(void); + +void board_init_f(ulong dummy) +{ +#ifdef EARLY_DEBUG + /* + * NOTE: sd card and debug uart use same iomux in rk3036, + * so if you enable uart, + * you can not boot from sdcard + */ + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C3_MASK << GPIO1C3_SHIFT | + GPIO1C2_MASK << GPIO1C2_SHIFT, + GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | + GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); + rk_uart_init((void *)DEBUG_UART_BASE); +#endif + rockchip_timer_init(); + sdram_init(); + + /* return to maskrom */ + back_to_bootrom(); +} + +/* Place Holders */ +void board_init_r(gd_t *id, ulong dest_addr) +{ + /* + * Function attribute is no-return + * This Function never executes + */ + while (1) + ; +} diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig new file mode 100644 index 0000000..cc03808 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -0,0 +1,21 @@ +if ROCKCHIP_RK3036 + +config TARGET_EVB_RK3036 + bool "EVB_RK3036" + +config TARGET_KYLIN_RK3036 + bool "KYLIN_RK3036" + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x400 + +config ROCKCHIP_COMMON + bool "Support rk common fuction" + +source "board/evb_rk3036/evb_rk3036/Kconfig" +source "board/kylin/kylin_rk3036/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile new file mode 100644 index 0000000..97d299d --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -0,0 +1,13 @@ +# +# (C) Copyright 2015 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_SPL_BUILD +obj-y += reset_rk3036.o +obj-y += syscon_rk3036.o +endif + +obj-y += sdram_rk3036.o +obj-y += save_boot_param.o diff --git a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c new file mode 100644 index 0000000..fefb568 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <reset.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3036.h> +#include <asm/arch/hardware.h> +#include <linux/err.h> + +int rk3036_reset_request(struct udevice *dev, enum reset_t type) +{ + struct rk3036_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case RESET_WARM: + writel(0xeca8, &cru->cru_glb_srst_snd_value); + break; + case RESET_COLD: + writel(0xfdb9, &cru->cru_glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct reset_ops rk3036_reset = { + .request = rk3036_reset_request, +}; + +U_BOOT_DRIVER(reset_rk3036) = { + .name = "rk3036_reset", + .id = UCLASS_RESET, + .ops = &rk3036_reset, +}; diff --git a/arch/arm/mach-rockchip/rk3036/save_boot_param.S b/arch/arm/mach-rockchip/rk3036/save_boot_param.S new file mode 100644 index 0000000..778ec83 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/save_boot_param.S @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> + +.globl SAVE_SP_ADDR +SAVE_SP_ADDR: + .word 0 + +/* + * void save_boot_params + * + * Save sp, lr, r1~r12 + */ +ENTRY(save_boot_params) + push {r1-r12, lr} + ldr r0, =SAVE_SP_ADDR + str sp, [r0] + b save_boot_params_ret @ back to my caller +ENDPROC(save_boot_params) + + +.globl back_to_bootrom +ENTRY(back_to_bootrom) + ldr r0, =SAVE_SP_ADDR + ldr sp, [r0] + mov r0, #0 + pop {r1-r12, pc} +ENDPROC(back_to_bootrom) diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c new file mode 100644 index 0000000..e3ca870 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -0,0 +1,768 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/io.h> +#include <asm/types.h> +#include <asm/arch/cru_rk3036.h> +#include <asm/arch/grf_rk3036.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sdram_rk3036.h> +#include <asm/arch/timer.h> +#include <asm/arch/uart.h> + +/* + * we can not fit the code to access the device tree in SPL + * (due to 4K SRAM size limits), so these are hard-coded + */ +#define CRU_BASE 0x20000000 +#define GRF_BASE 0x20008000 +#define DDR_PHY_BASE 0x2000a000 +#define DDR_PCTL_BASE 0x20004000 +#define CPU_AXI_BUS_BASE 0x10128000 + +struct rk3036_sdram_priv { + struct rk3036_cru *cru; + struct rk3036_grf *grf; + struct rk3036_ddr_phy *phy; + struct rk3036_ddr_pctl *pctl; + struct rk3036_service_sys *axi_bus; + + /* ddr die config */ + struct rk3036_ddr_config ddr_config; +}; + +/* use integer mode, 396MHz dpll setting + * refdiv, fbdiv, postdiv1, postdiv2 + */ +const struct pll_div dpll_init_cfg = {1, 66, 4, 1}; + +/* 396Mhz ddr timing */ +const struct rk3036_ddr_timing ddr_timing = {0x18c, + {0x18c, 0xc8, 0x1f4, 0x27, 0x4e, + 0x4, 0x8b, 0x06, 0x03, 0x0, 0x06, 0x05, 0x0f, 0x15, 0x06, 0x04, 0x04, + 0x06, 0x04, 0x200, 0x03, 0x0a, 0x40, 0x2710, 0x01, 0x05, 0x05, 0x03, + 0x0c, 0x28, 0x100, 0x0, 0x04, 0x0}, + {{0x420, 0x42, 0x0, 0x0}, 0x01, 0x60}, + {0x24717315} }; + +/* + * [7:6] bank(n:n bit bank) + * [5:4] row(13+n) + * [3] cs(0:1 cs, 1:2 cs) + * [2:1] bank(n:n bit bank) + * [0] col(10+n) + */ +const char ddr_cfg_2_rbc[] = { + ((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 1), + ((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 0), + ((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 0), + ((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 0), + ((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 1), + ((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 1), + ((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 1), + ((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 0), + ((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 1), + ((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 0), + ((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 1), + ((1 << 6) | (2 << 4) | (0 << 3) | (2 << 1) | 0), + ((3 << 6) | (2 << 4) | (0 << 3) | (0 << 1) | 1), + ((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 0), +}; + +/* DDRPHY REG */ +enum { + /* DDRPHY_REG1 */ + SOFT_RESET_MASK = 3, + SOFT_RESET_SHIFT = 2, + + /* DDRPHY_REG2 */ + MEMORY_SELECT_DDR3 = 0 << 6, + DQS_SQU_CAL_NORMAL_MODE = 0 << 1, + DQS_SQU_CAL_START = 1 << 0, + DQS_SQU_NO_CAL = 0 << 0, + + /* DDRPHY_REG2A */ + CMD_DLL_BYPASS = 1 << 4, + CMD_DLL_BYPASS_DISABLE = 0 << 4, + HIGH_8BIT_DLL_BYPASS = 1 << 3, + HIGH_8BIT_DLL_BYPASS_DISABLE = 0 << 3, + LOW_8BIT_DLL_BYPASS = 1 << 2, + LOW_8BIT_DLL_BYPASS_DISABLE = 0 << 2, + + /* DDRPHY_REG19 */ + CMD_FEEDBACK_ENABLE = 1 << 5, + CMD_SLAVE_DLL_INVERSE_MODE = 1 << 4, + CMD_SLAVE_DLL_NO_INVERSE_MODE = 0 << 4, + CMD_SLAVE_DLL_ENALBE = 1 << 3, + CMD_TX_SLAVE_DLL_DELAY_MASK = 7, + CMD_TX_SLAVE_DLL_DELAY_SHIFT = 0, + + /* DDRPHY_REG6 */ + LEFT_CHN_TX_DQ_PHASE_BYPASS_90 = 1 << 4, + LEFT_CHN_TX_DQ_PHASE_BYPASS_0 = 0 << 4, + LEFT_CHN_TX_DQ_DLL_ENABLE = 1 << 3, + LEFT_CHN_TX_DQ_DLL_DELAY_MASK = 7, + LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT = 0, + + /* DDRPHY_REG8 */ + LEFT_CHN_RX_DQS_DELAY_TAP_MASK = 3, + LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT = 0, + + /* DDRPHY_REG9 */ + RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 = 1 << 4, + RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 = 0 << 4, + RIGHT_CHN_TX_DQ_DLL_ENABLE = 1 << 3, + RIGHT_CHN_TX_DQ_DLL_DELAY_MASK = 7, + RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT = 0, + + /* DDRPHY_REG11 */ + RIGHT_CHN_RX_DQS_DELAY_TAP_MASK = 3, + RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT = 0, + + /* DDRPHY_REG62 */ + CAL_DONE_MASK = 3, + HIGH_8BIT_CAL_DONE = 1 << 1, + LOW_8BIT_CAL_DONE = 1 << 0, +}; + +/* PTCL */ +enum { + /* PCTL_DFISTCFG0 */ + DFI_INIT_START = 1 << 0, + DFI_DATA_BYTE_DISABLE_EN = 1 << 2, + + /* PCTL_DFISTCFG1 */ + DFI_DRAM_CLK_SR_EN = 1 << 0, + DFI_DRAM_CLK_DPD_EN = 1 << 1, + + /* PCTL_DFISTCFG2 */ + DFI_PARITY_INTR_EN = 1 << 0, + DFI_PARITY_EN = 1 << 1, + + /* PCTL_DFILPCFG0 */ + TLP_RESP_TIME_SHIFT = 16, + LP_SR_EN = 1 << 8, + LP_PD_EN = 1 << 0, + + /* PCTL_DFIODTCFG */ + RANK0_ODT_WRITE_SEL = 1 << 3, + RANK1_ODT_WRITE_SEL = 1 << 11, + + /* PCTL_DFIODTCFG1 */ + ODT_LEN_BL8_W_SHIFT = 16, + + /* PCTL_MCFG */ + TFAW_CFG_MASK = 3, + TFAW_CFG_SHIFT = 18, + PD_EXIT_SLOW_MODE = 0 << 17, + PD_ACTIVE_POWER_DOWN = 1 << 16, + PD_IDLE_MASK = 0xff, + PD_IDLE_SHIFT = 8, + MEM_BL4 = 0 << 0, + MEM_BL8 = 1 << 0, + + /* PCTL_MCFG1 */ + HW_EXIT_IDLE_EN_MASK = 1, + HW_EXIT_IDLE_EN_SHIFT = 31, + SR_IDLE_MASK = 0x1ff, + SR_IDLE_SHIFT = 0, + + /* PCTL_SCFG */ + HW_LOW_POWER_EN = 1 << 0, + + /* PCTL_POWCTL */ + POWER_UP_START = 1 << 0, + + /* PCTL_POWSTAT */ + POWER_UP_DONE = 1 << 0, + + /* PCTL_MCMD */ + START_CMD = 1 << 31, + BANK_ADDR_MASK = 7, + BANK_ADDR_SHIFT = 17, + CMD_ADDR_MASK = 0x1fff, + CMD_ADDR_SHIFT = 4, + DESELECT_CMD = 0, + PREA_CMD, + REF_CMD, + MRS_CMD, + ZQCS_CMD, + ZQCL_CMD, + RSTL_CMD, + MRR_CMD = 8, + + /* PCTL_STAT */ + INIT_MEM = 0, + CONFIG, + CONFIG_REQ, + ACCESS, + ACCESS_REQ, + LOW_POWER, + LOW_POWER_ENTRY_REQ, + LOW_POWER_EXIT_REQ, + PCTL_STAT_MASK = 7, + + /* PCTL_SCTL */ + INIT_STATE = 0, + CFG_STATE = 1, + GO_STATE = 2, + SLEEP_STATE = 3, + WAKEUP_STATE = 4, +}; + +/* GRF_SOC_CON2 */ +#define MSCH4_MAINDDR3 (1 << 7) +#define PHY_DRV_ODT_SET(n) ((n << 4) | n) +#define DDR3_DLL_RESET (1 << 8) + +/* CK pull up/down driver strength control */ +enum { + PHY_RON_DISABLE = 0, + PHY_RON_309OHM = 1, + PHY_RON_155OHM, + PHY_RON_103OHM = 3, + PHY_RON_63OHM = 5, + PHY_RON_45OHM = 7, + PHY_RON_77OHM, + PHY_RON_62OHM, + PHY_RON_52OHM, + PHY_RON_44OHM, + PHY_RON_39OHM, + PHY_RON_34OHM, + PHY_RON_31OHM, + PHY_RON_28OHM, +}; + +/* DQ pull up/down control */ +enum { + PHY_RTT_DISABLE = 0, + PHY_RTT_861OHM = 1, + PHY_RTT_431OHM, + PHY_RTT_287OHM, + PHY_RTT_216OHM, + PHY_RTT_172OHM, + PHY_RTT_145OHM, + PHY_RTT_124OHM, + PHY_RTT_215OHM, + PHY_RTT_144OHM = 0xa, + PHY_RTT_123OHM, + PHY_RTT_108OHM, + PHY_RTT_96OHM, + PHY_RTT_86OHM, + PHY_RTT_78OHM, +}; + +/* DQS squelch DLL delay */ +enum { + DQS_DLL_NO_DELAY = 0, + DQS_DLL_22P5_DELAY, + DQS_DLL_45_DELAY, + DQS_DLL_67P5_DELAY, + DQS_DLL_90_DELAY, + DQS_DLL_112P5_DELAY, + DQS_DLL_135_DELAY, + DQS_DLL_157P5_DELAY, +}; + +/* GRF_OS_REG1 */ +enum { + /* + * 000: lpddr + * 001: ddr + * 010: ddr2 + * 011: ddr3 + * 100: lpddr2-s2 + * 101: lpddr2-s4 + * 110: lpddr3 + */ + DDR_TYPE_MASK = 7, + DDR_TYPE_SHIFT = 13, + + /* 0: 1 chn, 1: 2 chn */ + DDR_CHN_CNT_SHIFT = 12, + + /* 0: 1 rank, 1: 2 rank */ + DDR_RANK_CNT_MASK = 1, + DDR_RANK_CNT_SHIFT = 11, + + /* + * 00: 9col + * 01: 10col + * 10: 11col + * 11: 12col + */ + DDR_COL_MASK = 3, + DDR_COL_SHIFT = 9, + + /* 0: 8 bank, 1: 4 bank*/ + DDR_BANK_MASK = 1, + DDR_BANK_SHIFT = 8, + + /* + * 00: 13 row + * 01: 14 row + * 10: 15 row + * 11: 16 row + */ + DDR_CS0_ROW_MASK = 3, + DDR_CS0_ROW_SHIFT = 6, + DDR_CS1_ROW_MASK = 3, + DDR_CS1_ROW_SHIFT = 4, + + /* + * 00: 32 bit + * 01: 16 bit + * 10: 8 bit + * rk3036 only support 16bit + */ + DDR_BW_MASK = 3, + DDR_BW_SHIFT = 2, + DDR_DIE_BW_MASK = 3, + DDR_DIE_BW_SHIFT = 0, +}; + +static void rkdclk_init(struct rk3036_sdram_priv *priv) +{ + struct rk3036_pll *pll = &priv->cru->pll[1]; + + /* pll enter slow-mode */ + rk_clrsetreg(&priv->cru->cru_mode_con, + DPLL_MODE_MASK << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW << DPLL_MODE_SHIFT); + + /* use integer mode */ + rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); + + rk_clrsetreg(&pll->con0, + PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK, + (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) | + dpll_init_cfg.fbdiv); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | + PLL_REFDIV_MASK << PLL_REFDIV_SHIFT, + (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | + dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT)); + + /* waiting for pll lock */ + while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) + rockchip_udelay(1); + + /* PLL enter normal-mode */ + rk_clrsetreg(&priv->cru->cru_mode_con, + DPLL_MODE_MASK << DPLL_MODE_SHIFT, + DPLL_MODE_NORM << DPLL_MODE_SHIFT); +} + +static void copy_to_reg(u32 *dest, const u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) { + writel(*src, dest); + src++; + dest++; + } +} + +void phy_pctrl_reset(struct rk3036_sdram_priv *priv) +{ + struct rk3036_ddr_phy *ddr_phy = priv->phy; + + rk_clrsetreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | + 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT | + 1 << DDRPHY_SRST_SHIFT, + 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT | + 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); + + rockchip_udelay(10); + + rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | + 1 << DDRPHY_SRST_SHIFT); + rockchip_udelay(10); + + rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | + 1 << DDRCTRL_SRST_SHIFT); + rockchip_udelay(10); + + clrsetbits_le32(&ddr_phy->ddrphy_reg1, + SOFT_RESET_MASK << SOFT_RESET_SHIFT, + 0 << SOFT_RESET_SHIFT); + rockchip_udelay(10); + clrsetbits_le32(&ddr_phy->ddrphy_reg1, + SOFT_RESET_MASK << SOFT_RESET_SHIFT, + 3 << SOFT_RESET_SHIFT); + + rockchip_udelay(1); +} + +void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq) +{ + struct rk3036_ddr_phy *ddr_phy = priv->phy; + + if (freq < ddr_timing.freq) { + writel(CMD_DLL_BYPASS | HIGH_8BIT_DLL_BYPASS | + LOW_8BIT_DLL_BYPASS, &ddr_phy->ddrphy_reg2a); + + writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_90 | + LEFT_CHN_TX_DQ_DLL_ENABLE | + (0 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) << + LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg6); + + writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 | + RIGHT_CHN_TX_DQ_DLL_ENABLE | + (0 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) << + RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT, + &ddr_phy->ddrphy_reg9); + } else { + writel(CMD_DLL_BYPASS_DISABLE | HIGH_8BIT_DLL_BYPASS_DISABLE | + LOW_8BIT_DLL_BYPASS_DISABLE, &ddr_phy->ddrphy_reg2a); + + writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_0 | + LEFT_CHN_TX_DQ_DLL_ENABLE | + (4 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) << + LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, + &ddr_phy->ddrphy_reg6); + + writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 | + RIGHT_CHN_TX_DQ_DLL_ENABLE | + (4 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) << + RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT, + &ddr_phy->ddrphy_reg9); + } + + writel(CMD_SLAVE_DLL_NO_INVERSE_MODE | CMD_SLAVE_DLL_ENALBE | + (0 & CMD_TX_SLAVE_DLL_DELAY_MASK) << + CMD_TX_SLAVE_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg19); + + /* 45 degree delay */ + writel((DQS_DLL_45_DELAY & LEFT_CHN_RX_DQS_DELAY_TAP_MASK) << + LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg8); + writel((DQS_DLL_45_DELAY & RIGHT_CHN_RX_DQS_DELAY_TAP_MASK) << + RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg11); +} + +static void send_command(struct rk3036_ddr_pctl *pctl, + u32 rank, u32 cmd, u32 arg) +{ + writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); + rockchip_udelay(1); + while (readl(&pctl->mcmd) & START_CMD) + ; +} + +static void memory_init(struct rk3036_sdram_priv *priv) +{ + struct rk3036_ddr_pctl *pctl = priv->pctl; + + send_command(pctl, 3, DESELECT_CMD, 0); + rockchip_udelay(1); + send_command(pctl, 3, PREA_CMD, 0); + send_command(pctl, 3, MRS_CMD, + (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | + (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << + CMD_ADDR_SHIFT); + + send_command(pctl, 3, MRS_CMD, + (0x03 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | + (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << + CMD_ADDR_SHIFT); + + send_command(pctl, 3, MRS_CMD, + (0x01 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | + (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << + CMD_ADDR_SHIFT); + + send_command(pctl, 3, MRS_CMD, + (0x00 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | + (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << + CMD_ADDR_SHIFT | DDR3_DLL_RESET); + + send_command(pctl, 3, ZQCL_CMD, 0); +} + +static void data_training(struct rk3036_sdram_priv *priv) +{ + struct rk3036_ddr_phy *ddr_phy = priv->phy; + struct rk3036_ddr_pctl *pctl = priv->pctl; + u32 value; + + /* disable auto refresh */ + value = readl(&pctl->trefi), + writel(0, &pctl->trefi); + + clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, + DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START); + + rockchip_udelay(1); + while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) != + (HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) { + ; + } + + clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, + DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_NO_CAL); + + /* + * since data training will take about 20us, so send some auto + * refresh(about 7.8us) to complement the lost time + */ + send_command(pctl, 3, REF_CMD, 0); + send_command(pctl, 3, REF_CMD, 0); + send_command(pctl, 3, REF_CMD, 0); + + writel(value, &pctl->trefi); +} + +static void move_to_config_state(struct rk3036_sdram_priv *priv) +{ + unsigned int state; + struct rk3036_ddr_pctl *pctl = priv->pctl; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MASK; + switch (state) { + case LOW_POWER: + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) + != ACCESS) + ; + /* + * If at low power state, need wakeup first, and then + * enter the config, so fallthrough + */ + case ACCESS: + /* fallthrough */ + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) + ; + break; + case CONFIG: + return; + default: + break; + } + } +} + +static void move_to_access_state(struct rk3036_sdram_priv *priv) +{ + unsigned int state; + struct rk3036_ddr_pctl *pctl = priv->pctl; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MASK; + switch (state) { + case LOW_POWER: + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) + ; + break; + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) + ; + /* fallthrough */ + case CONFIG: + writel(GO_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) + ; + break; + case ACCESS: + return; + default: + break; + } + } +} + +static void pctl_cfg(struct rk3036_sdram_priv *priv) +{ + struct rk3036_ddr_pctl *pctl = priv->pctl; + u32 burst_len; + u32 reg; + + writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1); + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, + &pctl->dfilpcfg0); + + writel(1, &pctl->dfitphyupdtype0); + writel(0x0d, &pctl->dfitphyrdlat); + + /* cs0 and cs1 write odt enable */ + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), + &pctl->dfiodtcfg); + + /* odt write length */ + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); + + /* phyupd and ctrlupd disabled */ + writel(0, &pctl->dfiupdcfg); + + if ((ddr_timing.noc_timing.burstlen << 1) == 4) + burst_len = MEM_BL4; + else + burst_len = MEM_BL8; + + copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, + sizeof(struct rk3036_pctl_timing)); + reg = readl(&pctl->tcl); + writel(reg - 3, &pctl->dfitrddataen); + reg = readl(&pctl->tcwl); + writel(reg - 1, &pctl->dfitphywrlat); + + writel(burst_len | (1 & TFAW_CFG_MASK) << TFAW_CFG_SHIFT | + PD_EXIT_SLOW_MODE | PD_ACTIVE_POWER_DOWN | + (0 & PD_IDLE_MASK) << PD_IDLE_SHIFT, + &pctl->mcfg); + + writel(RK_SETBITS(MSCH4_MAINDDR3), &priv->grf->soc_con2); + setbits_le32(&pctl->scfg, HW_LOW_POWER_EN); +} + +static void phy_cfg(struct rk3036_sdram_priv *priv) +{ + struct rk3036_ddr_phy *ddr_phy = priv->phy; + struct rk3036_service_sys *axi_bus = priv->axi_bus; + + writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); + writel(0x3f, &axi_bus->readlatency); + + writel(MEMORY_SELECT_DDR3 | DQS_SQU_CAL_NORMAL_MODE, + &ddr_phy->ddrphy_reg2); + + clrsetbits_le32(&ddr_phy->ddrphy_reg3, 1, ddr_timing.phy_timing.bl); + writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); + writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg16); + writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg22); + writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg25); + writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg26); + writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg27); + writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg28); +} + +void dram_cfg_rbc(struct rk3036_sdram_priv *priv) +{ + char noc_config; + int i = 0; + struct rk3036_ddr_config config = priv->ddr_config; + struct rk3036_service_sys *axi_bus = priv->axi_bus; + + move_to_config_state(priv); + + /* 2bit in BIT1, 2 */ + if (config.rank == 2) { + noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 | + 1 << 3 | (config.col - 10); + if (noc_config == ddr_cfg_2_rbc[9]) { + i = 9; + goto finish; + } else if (noc_config == ddr_cfg_2_rbc[10]) { + i = 10; + goto finish; + } + } + + noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 | + (config.col - 10); + + for (i = 0; i < sizeof(ddr_cfg_2_rbc); i++) { + if (noc_config == ddr_cfg_2_rbc[i]) + goto finish; + } + + /* bank: 1 bit in BIT6,7, 1bit in BIT1, 2 */ + noc_config = 1 << 6 | (config.cs0_row - 13) << 4 | + 2 << 1 | (config.col - 10); + if (noc_config == ddr_cfg_2_rbc[11]) { + i = 11; + goto finish; + } + + /* bank: 2bit in BIT6,7 */ + noc_config = (config.bank << 6) | (config.cs0_row - 13) << 4 | + (config.col - 10); + + if (noc_config == ddr_cfg_2_rbc[0]) + i = 0; + else if (noc_config == ddr_cfg_2_rbc[12]) + i = 12; + else if (noc_config == ddr_cfg_2_rbc[13]) + i = 13; +finish: + writel(i, &axi_bus->ddrconf); + move_to_access_state(priv); +} + +static void sdram_all_config(struct rk3036_sdram_priv *priv) +{ + u32 os_reg = 0; + u32 cs1_row = 0; + struct rk3036_ddr_config config = priv->ddr_config; + + if (config.rank > 1) + cs1_row = config.cs1_row - 13; + + os_reg = config.ddr_type << DDR_TYPE_SHIFT | + 0 << DDR_CHN_CNT_SHIFT | + (config.rank - 1) << DDR_RANK_CNT_SHIFT | + (config.col - 1) << DDR_COL_SHIFT | + (config.bank == 3 ? 0 : 1) << DDR_BANK_SHIFT | + (config.cs0_row - 13) << DDR_CS0_ROW_SHIFT | + cs1_row << DDR_CS1_ROW_SHIFT | + 1 << DDR_BW_SHIFT | config.bw << DDR_DIE_BW_SHIFT; + writel(os_reg, &priv->grf->os_reg[1]); +} + +size_t sdram_size(void) +{ + u32 size, os_reg, cs0_row, cs1_row, col, bank, rank; + struct rk3036_grf *grf = (void *)GRF_BASE; + + os_reg = readl(&grf->os_reg[1]); + + cs0_row = 13 + ((os_reg >> DDR_CS0_ROW_SHIFT) & DDR_CS0_ROW_MASK); + cs1_row = 13 + ((os_reg >> DDR_CS1_ROW_SHIFT) & DDR_CS1_ROW_MASK); + col = 9 + ((os_reg >> DDR_COL_SHIFT) & DDR_COL_MASK); + bank = 3 - ((os_reg >> DDR_BANK_SHIFT) & DDR_BANK_MASK); + rank = 1 + ((os_reg >> DDR_RANK_CNT_SHIFT) & DDR_RANK_CNT_MASK); + + /* row + col + bank + bw(rk3036 only support 16bit, so fix in 1) */ + size = 1 << (cs0_row + col + bank + 1); + + if (rank > 1) + size += size >> (cs0_row - cs1_row); + + return size; +} + +void sdram_init(void) +{ + struct rk3036_sdram_priv sdram_priv; + + sdram_priv.cru = (void *)CRU_BASE; + sdram_priv.grf = (void *)GRF_BASE; + sdram_priv.phy = (void *)DDR_PHY_BASE; + sdram_priv.pctl = (void *)DDR_PCTL_BASE; + sdram_priv.axi_bus = (void *)CPU_AXI_BUS_BASE; + + get_ddr_config(&sdram_priv.ddr_config); + sdram_all_config(&sdram_priv); + rkdclk_init(&sdram_priv); + phy_pctrl_reset(&sdram_priv); + phy_dll_bypass_set(&sdram_priv, ddr_timing.freq); + pctl_cfg(&sdram_priv); + phy_cfg(&sdram_priv); + writel(POWER_UP_START, &sdram_priv.pctl->powctl); + while (!(readl(&sdram_priv.pctl->powstat) & POWER_UP_DONE)) + ; + memory_init(&sdram_priv); + move_to_config_state(&sdram_priv); + data_training(&sdram_priv); + move_to_access_state(&sdram_priv); + dram_cfg_rbc(&sdram_priv); +} diff --git a/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c new file mode 100644 index 0000000..965afde --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rk3036_syscon_ids[] = { + { .compatible = "rockchip,rk3036-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3036) = { + .name = "rk3036_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3036_syscon_ids, +}; diff --git a/arch/arm/mach-rockchip/board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 28c3949..8199cad 100644 --- a/arch/arm/mach-rockchip/board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -18,6 +18,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/sdram.h> +#include <asm/arch/timer.h> #include <dm/pinctrl.h> #include <dm/root.h> #include <dm/test.h> @@ -110,24 +111,6 @@ static void configure_l2ctlr(void) write_l2ctlr(l2ctlr); } -struct rk3288_timer { - u32 timer_load_count0; - u32 timer_load_count1; - u32 timer_curr_value0; - u32 timer_curr_value1; - u32 timer_ctrl_reg; - u32 timer_int_status; -}; - -void init_timer(void) -{ - struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE; - - writel(0xffffffff, &timer7_ptr->timer_load_count0); - writel(0xffffffff, &timer7_ptr->timer_load_count1); - writel(1, &timer7_ptr->timer_ctrl_reg); -} - static int configure_emmc(struct udevice *pinctrl) { struct gpio_desc desc; @@ -197,7 +180,7 @@ void board_init_f(ulong dummy) hang(); } - init_timer(); + rockchip_timer_init(); configure_l2ctlr(); ret = uclass_get_device(UCLASS_CLK, 0, &dev); @@ -217,13 +200,6 @@ void board_init_f(ulong dummy) debug("DRAM init failed: %d\n", ret); return; } - - /* - * Now that DRAM is initialized setup base pointer for simple malloc - * into RAM. - */ - gd->malloc_base = CONFIG_SPL_STACK_R_ADDR; - gd->malloc_ptr = 0; } static int setup_led(void) diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 4d0f1b5..d0a7276 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -19,6 +19,9 @@ config TARGET_CHROMEBOOK_JERRY config SYS_SOC default "rockchip" +config SYS_MALLOC_F_LEN + default 0x0800 + source "board/google/chromebook_jerry/Kconfig" source "board/firefly/firefly-rk3288/Kconfig" diff --git a/arch/arm/mach-rockchip/rk_early_print.c b/arch/arm/mach-rockchip/rk_early_print.c new file mode 100644 index 0000000..a1c14b0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk_early_print.c @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <asm/arch/uart.h> +#include <common.h> + +static struct rk_uart *uart_ptr; + +static void uart_wrtie_byte(char byte) +{ + writel(byte, &uart_ptr->rbr); + while (!(readl(&uart_ptr->lsr) & 0x40)) + ; +} + +void print(char *s) +{ + while (*s) { + if (*s == '\n') + uart_wrtie_byte('\r'); + uart_wrtie_byte(*s); + s++; + } +} + +void print_hex(unsigned int n) +{ + int i; + int temp; + + uart_wrtie_byte('0'); + uart_wrtie_byte('x'); + + for (i = 8; i > 0; i--) { + temp = (n >> (i - 1) * 4) & 0x0f; + if (temp < 10) + uart_wrtie_byte((char)(temp + '0')); + else + uart_wrtie_byte((char)(temp - 10 + 'a')); + } + uart_wrtie_byte('\n'); + uart_wrtie_byte('\r'); +} + +/* + * TODO: since rk3036 only 4K sram to use in SPL, for saving space, + * we implement uart driver this way, we should convert this to use + * ns16550 driver in future, which support DEBUG_UART in the standard way + */ +void rk_uart_init(void *base) +{ + uart_ptr = (struct rk_uart *)base; + writel(0x83, &uart_ptr->lcr); + writel(0x0d, &uart_ptr->rbr); + writel(0x03, &uart_ptr->lcr); + + /* fifo enable, sfe is shadow register of FCR[0] */ + writel(0x01, &uart_ptr->sfe); +} diff --git a/arch/arm/mach-rockchip/rk_timer.c b/arch/arm/mach-rockchip/rk_timer.c new file mode 100644 index 0000000..ae5123d --- /dev/null +++ b/arch/arm/mach-rockchip/rk_timer.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/timer.h> +#include <asm/io.h> +#include <common.h> +#include <linux/types.h> + +struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE; + +static uint64_t rockchip_get_ticks(void) +{ + uint64_t timebase_h, timebase_l; + + timebase_l = readl(&timer_ptr->timer_curr_value0); + timebase_h = readl(&timer_ptr->timer_curr_value1); + + return timebase_h << 32 | timebase_l; +} + +static uint64_t usec_to_tick(unsigned int usec) +{ + uint64_t tick = usec; + tick *= CONFIG_SYS_TIMER_RATE / (1000 * 1000); + return tick; +} + +void rockchip_udelay(unsigned int usec) +{ + uint64_t tmp; + + /* get timestamp */ + tmp = rockchip_get_ticks() + usec_to_tick(usec); + + /* loop till event */ + while (rockchip_get_ticks() < tmp+1) + ; +} + +void rockchip_timer_init(void) +{ + writel(0xffffffff, &timer_ptr->timer_load_count0); + writel(0xffffffff, &timer_ptr->timer_load_count1); + writel(1, &timer_ptr->timer_ctrl_reg); +} diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/mach-s5pc1xx/Kconfig index 04acdaa..04acdaa 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig +++ b/arch/arm/mach-s5pc1xx/Kconfig diff --git a/arch/arm/cpu/armv7/s5pc1xx/Makefile b/arch/arm/mach-s5pc1xx/Makefile index 9f43ded..9f43ded 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Makefile +++ b/arch/arm/mach-s5pc1xx/Makefile diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.c b/arch/arm/mach-s5pc1xx/cache.c index 51af299..51af299 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/cache.c +++ b/arch/arm/mach-s5pc1xx/cache.c diff --git a/arch/arm/cpu/armv7/s5pc1xx/clock.c b/arch/arm/mach-s5pc1xx/clock.c index 3da0071..3da0071 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/clock.c +++ b/arch/arm/mach-s5pc1xx/clock.c diff --git a/arch/arm/include/asm/arch-s5pc1xx/clk.h b/arch/arm/mach-s5pc1xx/include/mach/clk.h index 6457ac7..6457ac7 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/clk.h +++ b/arch/arm/mach-s5pc1xx/include/mach/clk.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/clock.h b/arch/arm/mach-s5pc1xx/include/mach/clock.h index 858496a..858496a 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/clock.h +++ b/arch/arm/mach-s5pc1xx/include/mach/clock.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/mach-s5pc1xx/include/mach/cpu.h index 5ae5c87..5ae5c87 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h +++ b/arch/arm/mach-s5pc1xx/include/mach/cpu.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/mach-s5pc1xx/include/mach/gpio.h index 2de205e..2de205e 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/mach-s5pc1xx/include/mach/gpio.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/mach-s5pc1xx/include/mach/mmc.h index dd473c8..dd473c8 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h +++ b/arch/arm/mach-s5pc1xx/include/mach/mmc.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/periph.h b/arch/arm/mach-s5pc1xx/include/mach/periph.h index 5c1c3d4..5c1c3d4 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/periph.h +++ b/arch/arm/mach-s5pc1xx/include/mach/periph.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/pinmux.h b/arch/arm/mach-s5pc1xx/include/mach/pinmux.h index 0b91ef6..0b91ef6 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/pinmux.h +++ b/arch/arm/mach-s5pc1xx/include/mach/pinmux.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/power.h b/arch/arm/mach-s5pc1xx/include/mach/power.h index 8400cda..8400cda 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/power.h +++ b/arch/arm/mach-s5pc1xx/include/mach/power.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/pwm.h b/arch/arm/mach-s5pc1xx/include/mach/pwm.h index 7a33ed8..7a33ed8 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/pwm.h +++ b/arch/arm/mach-s5pc1xx/include/mach/pwm.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/sromc.h b/arch/arm/mach-s5pc1xx/include/mach/sromc.h index df1bf51..df1bf51 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/sromc.h +++ b/arch/arm/mach-s5pc1xx/include/mach/sromc.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h b/arch/arm/mach-s5pc1xx/include/mach/sys_proto.h index 647d6c4..647d6c4 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h +++ b/arch/arm/mach-s5pc1xx/include/mach/sys_proto.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/uart.h b/arch/arm/mach-s5pc1xx/include/mach/uart.h index 26db098..26db098 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/uart.h +++ b/arch/arm/mach-s5pc1xx/include/mach/uart.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/watchdog.h b/arch/arm/mach-s5pc1xx/include/mach/watchdog.h index 2f9746c..2f9746c 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/watchdog.h +++ b/arch/arm/mach-s5pc1xx/include/mach/watchdog.h diff --git a/arch/arm/cpu/armv7/s5pc1xx/reset.S b/arch/arm/mach-s5pc1xx/reset.S index bd74f2b..bd74f2b 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/reset.S +++ b/arch/arm/mach-s5pc1xx/reset.S diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index a413ea4..dea4ce5 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -2,9 +2,14 @@ if ARCH_SOCFPGA config TARGET_SOCFPGA_ARRIA5 bool + select TARGET_SOCFPGA_GEN5 config TARGET_SOCFPGA_CYCLONE5 bool + select TARGET_SOCFPGA_GEN5 + +config TARGET_SOCFPGA_GEN5 + bool choice prompt "Altera SOCFPGA board select" @@ -22,6 +27,14 @@ config TARGET_SOCFPGA_DENX_MCVEVK bool "DENX MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_SR1500 + bool "SR1500 (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + +config TARGET_SOCFPGA_EBV_SOCRATES + bool "EBV SoCrates (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + config TARGET_SOCFPGA_TERASIC_DE0_NANO bool "Terasic DE0-Nano-Atlas (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -38,11 +51,14 @@ config SYS_BOARD default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES + default "sr1500" if TARGET_SOCFPGA_SR1500 config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "denx" if TARGET_SOCFPGA_DENX_MCVEVK + default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT @@ -55,5 +71,7 @@ config SYS_CONFIG_NAME default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES + default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 endif diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 316b326..809cd47 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -8,11 +8,12 @@ # obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ - fpga_manager.o scan_manager.o + fpga_manager.o board.o + obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o # QTS-generated config file wrappers -obj-y += wrap_pll_config.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ wrap_sdram_config.o CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c new file mode 100644 index 0000000..a41d089 --- /dev/null +++ b/arch/arm/mach-socfpga/board.c @@ -0,0 +1,64 @@ +/* + * Altera SoCFPGA common board code + * + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/arch/reset_manager.h> +#include <asm/io.h> + +#include <usb.h> +#include <usb/dwc2_udc.h> + +DECLARE_GLOBAL_DATA_PTR; + +void s_init(void) {} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +#ifdef CONFIG_USB_GADGET +struct dwc2_plat_otg_data socfpga_otg_data = { + .usb_gusbcfg = 0x1417, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + int node[2], count; + fdt_addr_t addr; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", + COMPAT_ALTERA_SOCFPGA_DWC2USB, + node, 2); + if (count <= 0) /* No controller found. */ + return 0; + + addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); + if (addr == FDT_ADDR_T_NONE) { + printf("UDC Controller has no 'reg' property!\n"); + return -EINVAL; + } + + /* Patch the address from OF into the controller pdata. */ + socfpga_otg_data.regs_otg = addr; + + return dwc2_udc_probe(&socfpga_otg_data); +} + +int g_dnl_board_usb_cable_connected(void) +{ + return 1; +} +#endif diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h new file mode 100644 index 0000000..a7056d4 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_A10_BASE_HARDWARE_H_ +#define _SOCFPGA_A10_BASE_HARDWARE_H_ + +#define SOCFPGA_EMAC0_ADDRESS 0xff800000 +#define SOCFPGA_EMAC1_ADDRESS 0xff802000 +#define SOCFPGA_EMAC2_ADDRESS 0xff804000 +#define SOCFPGA_SDMMC_ADDRESS 0xff808000 +#define SOCFPGA_QSPIREGS_ADDRESS 0xff809000 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 +#define SOCFPGA_UART1_ADDRESS 0xffc02100 +#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xffcfa000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffcfe400 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xffd03000 +#define SOCFPGA_L4WD0_ADDRESS 0xffd00200 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd06000 +#define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS 0xffd07000 +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd07200 +#define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS 0xffd07300 +#define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS 0xffd07400 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 +#define SOCFPGA_MPUSCU_ADDRESS 0xffffc000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffff000 +#define SOCFPGA_I2C0_ADDRESS 0xffc02200 +#define SOCFPGA_I2C1_ADDRESS 0xffc02300 + +#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 + +#define SOCFPGA_SDR_ADDRESS 0xffcfb000 +#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400 +#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200 +#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300 +#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400 + +#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h index 6534283..6534283 100644 --- a/arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 666a2ef..2f070f2 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -25,6 +25,7 @@ struct socfpga_reset_manager { u32 per2_mod_reset; u32 brg_mod_reset; u32 misc_mod_reset; + u32 padding2[12]; u32 tstscratch; }; @@ -64,12 +65,13 @@ struct socfpga_reset_manager { */ #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_NAND RSTMGR_DEFINE(1, 4) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) -#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 8712f8e..c45edea 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -129,9 +129,13 @@ struct socfpga_system_manager { #define SYSMGR_FPGAINTF_NAND (1 << 4) #define SYSMGR_FPGAINTF_SDMMC (1 << 5) -/* FIXME: This is questionable macro. */ -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 +#else +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 +#endif + +#define SYSMGR_SDMMC_DRVSEL_SHIFT 0 /* EMAC Group Bit definitions */ #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index bbd31ef..9b43b92 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -54,14 +54,23 @@ void enable_caches(void) void v7_outer_cache_enable(void) { - /* disable the L2 cache */ - writel(0, &pl310->pl310_ctrl); + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | L310_AUX_CTRL_INST_PREFETCH_MASK | L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + +void v7_outer_cache_disable(void) +{ + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } /* @@ -130,17 +139,6 @@ int cpu_eth_init(bd_t *bis) } #endif -#ifdef CONFIG_DWMMC -/* - * Initializes MMC controllers. - * to override, implement board_mmc_init() - */ -int cpu_mmc_init(bd_t *bis) -{ - return socfpga_dwmmc_init(gd->fdt_blob); -} -#endif - struct { const char *mode; const char *name; @@ -361,6 +359,10 @@ int arch_early_init_r(void) socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); #endif +#ifdef CONFIG_NAND_DENALI + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); +#endif + return 0; } diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 775a827..98c16a0 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -40,6 +40,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ case 0x3: /* NAND Flash (3.0V) */ + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); return BOOT_DEVICE_NAND; case 0x4: /* SD/MMC External Transceiver (1.8V) */ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index de2454e..fbfb204 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -1,18 +1,29 @@ if TEGRA -config TEGRA_ARMV7_COMMON - bool "Tegra 32-bit" - select SUPPORT_SPL - select SPL - select OF_CONTROL - select CPU_V7 +config TEGRA_COMMON + bool "Tegra common options" select DM - select DM_SPI_FLASH - select DM_SERIAL - select DM_I2C - select DM_SPI select DM_GPIO + select DM_I2C select DM_KEYBOARD + select DM_PCI + select DM_PCI_COMPAT + select DM_SERIAL + select DM_SPI + select DM_SPI_FLASH + select OF_CONTROL + +config TEGRA_ARMV7_COMMON + bool "Tegra 32-bit common options" + select CPU_V7 + select SPL + select SUPPORT_SPL + select TEGRA_COMMON + +config TEGRA_ARMV8_COMMON + bool "Tegra 64-bit common options" + select ARM64 + select TEGRA_COMMON choice prompt "Tegra SoC select" @@ -36,14 +47,7 @@ config TEGRA124 config TEGRA210 bool "Tegra210 family" - select OF_CONTROL - select ARM64 - select DM - select DM_SPI_FLASH - select DM_SERIAL - select DM_I2C - select DM_SPI - select DM_GPIO + select TEGRA_ARMV8_COMMON endchoice diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index b00e4b5..3d1d26d 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -6,6 +6,8 @@ */ #include <common.h> +#include <dm.h> +#include <ns16550.h> #include <spl.h> #include <asm/io.h> #include <asm/arch/clock.h> @@ -212,6 +214,18 @@ void board_init_uart_f(void) setup_uarts(uart_ids); } +#if !CONFIG_IS_ENABLED(OF_CONTROL) +static struct ns16550_platdata ns16550_com1_pdata = { + .base = CONFIG_SYS_NS16550_COM1, + .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, +}; + +U_BOOT_DEVICE(ns16550_com1) = { + "ns16550_serial", &ns16550_com1_pdata +}; +#endif + #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) void enable_caches(void) { diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 8ba143d..a650abd 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -377,6 +377,10 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); +#ifdef CONFIG_PCI + gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; +#endif + #ifdef CONFIG_PHYS_64BIT if (gd->ram_size > SZ_2G) { gd->bd->bi_dram[1].start = 0x100000000; diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index b597a13..5b19f93 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -6,9 +6,8 @@ ifdef CONFIG_SPL_BUILD obj-y += lowlevel_init.o obj-y += init_page_table.o -obj-y += boards.o -obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ umc/ ddrphy/ +obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ dram/ obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ obj-$(CONFIG_DEBUG_LL) += debug_ll.o @@ -33,6 +32,7 @@ obj-y += pinctrl/ clk/ endif obj-y += timer.o +obj-y += boards.o obj-y += soc_info.o obj-y += boot-mode/ diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index a7530eb..c2a3261 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -6,6 +6,7 @@ #include <common.h> #include <spl.h> +#include <libfdt.h> #include <nand.h> #include <linux/io.h> #include <../drivers/mtd/nand/denali.h> @@ -25,6 +26,38 @@ static void nand_denali_wp_disable(void) #endif } +struct uniphier_fdt_file { + const char *compatible; + const char *file_name; +}; + +static const struct uniphier_fdt_file uniphier_fdt_files[] = { + { "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", }, + { "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", }, + { "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", }, + { "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", }, + { "socionext,ph1-pro5-4kbox", "uniphier-ph1-pro5-4kbox.dtb", }, + { "socionext,ph1-sld3-ref", "uniphier-ph1-sld3-ref.dtb", }, + { "socionext,ph1-sld8-ref", "uniphier-ph1-sld8-ref.dtb", }, + { "socionext,proxstream2-gentil", "uniphier-proxstream2-gentil.dtb", }, + { "socionext,proxstream2-vodka", "uniphier-proxstream2-vodka.dtb", }, +}; + +static void uniphier_set_fdt_file(void) +{ + DECLARE_GLOBAL_DATA_PTR; + int i; + + /* lookup DTB file name based on the compatible string */ + for (i = 0; i < ARRAY_SIZE(uniphier_fdt_files); i++) { + if (!fdt_node_check_compatible(gd->fdt_blob, 0, + uniphier_fdt_files[i].compatible)) { + setenv("fdt_file", uniphier_fdt_files[i].file_name); + return; + } + } +} + int board_late_init(void) { puts("MODE: "); @@ -48,5 +81,7 @@ int board_late_init(void) return -1; } + uniphier_set_fdt_file(); + return 0; } diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index 812c58f..d075a11 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -4,10 +4,13 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <common.h> #include <libfdt.h> #include <linux/kernel.h> #include <mach/init.h> +DECLARE_GLOBAL_DATA_PTR; + #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) static const struct uniphier_board_data ph1_sld3_data = { .dram_ch0_base = 0x80000000, @@ -71,8 +74,7 @@ static const struct uniphier_board_data ph1_pro5_data = { }; #endif -#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \ - defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) +#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) static const struct uniphier_board_data proxstream2_data = { .dram_ch0_base = 0x80000000, .dram_ch0_size = 0x40000000, @@ -83,6 +85,21 @@ static const struct uniphier_board_data proxstream2_data = { .dram_ch2_base = 0xe0000000, .dram_ch2_size = 0x20000000, .dram_ch2_width = 16, + .dram_freq = 2133, +}; +#endif + +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) +static const struct uniphier_board_data ph1_ld6b_data = { + .dram_ch0_base = 0x80000000, + .dram_ch0_size = 0x40000000, + .dram_ch0_width = 32, + .dram_ch1_base = 0xc0000000, + .dram_ch1_size = 0x20000000, + .dram_ch1_width = 32, + .dram_ch2_base = 0xe0000000, + .dram_ch2_size = 0x20000000, + .dram_ch2_width = 16, .dram_freq = 1866, }; #endif @@ -112,16 +129,16 @@ static const struct uniphier_board_id uniphier_boards[] = { { "socionext,proxstream2", &proxstream2_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) - { "socionext,ph1-ld6b", &proxstream2_data, }, + { "socionext,ph1-ld6b", &ph1_ld6b_data, }, #endif }; -const struct uniphier_board_data *uniphier_get_board_param(const void *fdt) +const struct uniphier_board_data *uniphier_get_board_param(void) { int i; for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) { - if (!fdt_node_check_compatible(fdt, 0, + if (!fdt_node_check_compatible(gd->fdt_blob, 0, uniphier_boards[i].compatible)) return uniphier_boards[i].param; } diff --git a/arch/arm/mach-uniphier/cmd_ddrphy.c b/arch/arm/mach-uniphier/cmd_ddrphy.c index dbbefd4..f9b79ab 100644 --- a/arch/arm/mach-uniphier/cmd_ddrphy.c +++ b/arch/arm/mach-uniphier/cmd_ddrphy.c @@ -50,7 +50,7 @@ static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx) printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff); } -void wbdl_dump(void) +static void wbdl_dump(void) { printf("\n--- Write Bit Delay Line ---\n"); printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n"); @@ -68,7 +68,7 @@ static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx) printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff); } -void rbdl_dump(void) +static void rbdl_dump(void) { printf("\n--- Read Bit Delay Line ---\n"); printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n"); @@ -91,7 +91,7 @@ static void __wld_dump(struct ddrphy_datx8 __iomem *dx) } } -void wld_dump(void) +static void wld_dump(void) { printf("\n--- Write Leveling Delay ---\n"); printf(" Rank0 Rank1 Rank2 Rank3\n"); @@ -113,7 +113,7 @@ static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx) } } -void dqsgd_dump(void) +static void dqsgd_dump(void) { printf("\n--- DQS Gating Delay ---\n"); printf(" Rank0 Rank1 Rank2 Rank3\n"); @@ -129,7 +129,7 @@ static void __mdl_dump(struct ddrphy_datx8 __iomem *dx) printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff); } -void mdl_dump(void) +static void mdl_dump(void) { printf("\n--- Master Delay Line ---\n"); printf(" IPRD TPRD MDLD\n"); @@ -141,7 +141,7 @@ void mdl_dump(void) { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \ p - (u32 *)phy, #x, p, readl(p)); } -void reg_dump(void) +static void reg_dump(void) { int ch, p; struct ddrphy __iomem *phy; diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c index 5d9ed84..935b209 100644 --- a/arch/arm/mach-uniphier/cpu_info.c +++ b/arch/arm/mach-uniphier/cpu_info.c @@ -43,13 +43,18 @@ int print_cpuinfo(void) case 0x2F: puts("PH1-LD6b (MN2WS0320)"); break; + case 0x31: + puts("PH1-sLD11 ()"); + break; + case 0x32: + puts("PH1-LD10 ()"); + break; default: printf("Unknown Processor ID (0x%x)\n", revision); return -1; } - if (model > 1) - printf(" model %d", model); + printf(" model %d", model); printf(" (rev. %d)\n", rev); diff --git a/arch/arm/mach-uniphier/ddrphy/Makefile b/arch/arm/mach-uniphier/ddrphy/Makefile deleted file mode 100644 index d0f4bd3..0000000 --- a/arch/arm/mach-uniphier/ddrphy/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ddrphy-training.o ddrphy-ph1-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ddrphy-training.o ddrphy-ph1-pro4.o -obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ddrphy-training.o ddrphy-ph1-sld8.o diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile new file mode 100644 index 0000000..d3a767b --- /dev/null +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o \ + ddrphy-training.o ddrphy-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o \ + ddrphy-training.o ddrphy-ph1-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o \ + ddrphy-training.o ddrphy-ph1-sld8.o diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c index 991d929..991d929 100644 --- a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c index bc47ba3..bc47ba3 100644 --- a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c index 39024a0..39024a0 100644 --- a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c b/arch/arm/mach-uniphier/dram/ddrphy-training.c index a98b814..4852f2d 100644 --- a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-training.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <linux/err.h> #include <linux/io.h> #include <mach/ddrphy-regs.h> @@ -32,8 +33,8 @@ void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank) /* Use Multi-Purpose Register for DQS gate training */ tmp |= DTCR_DTMPR; /* Specify the rank enabled for data-training */ - tmp &= ~DTCR_RNKEN_MASK; - tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK; + tmp &= ~DTCR_RANKEN_MASK; + tmp |= (1 << (DTCR_RANKEN_SHIFT + rank)) & DTCR_RANKEN_MASK; writel(tmp, p); } @@ -44,7 +45,7 @@ struct ddrphy_init_sequence { u32 err_flag; }; -static struct ddrphy_init_sequence init_sequence[] = { +static const struct ddrphy_init_sequence init_sequence[] = { { "DRAM Initialization", PIR_DRAMRST | PIR_DRAMINIT, @@ -117,7 +118,7 @@ int ddrphy_training(struct ddrphy __iomem *phy) if (--timeout < 0) { printf("%s: error: timeout during DDR training\n", __func__); - return -1; + return -ETIMEDOUT; } udelay(1); pgsr0 = readl(&phy->pgsr[0]); @@ -127,7 +128,7 @@ int ddrphy_training(struct ddrphy __iomem *phy) if (pgsr0 & init_sequence[i].err_flag) { printf("%s: error: %s failed\n", __func__, init_sequence[i].description); - return -1; + return -EIO; } } diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index 8124685..8124685 100644 --- a/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 8c9f057..8c9f057 100644 --- a/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index bc60a34..bc60a34 100644 --- a/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h index adcc972..03aedc2 100644 --- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h @@ -9,6 +9,7 @@ #ifndef ARCH_DDRPHY_REGS_H #define ARCH_DDRPHY_REGS_H +#include <linux/bitops.h> #include <linux/compiler.h> #ifndef __ASSEMBLY__ @@ -79,52 +80,52 @@ struct ddrphy { #endif /* __ASSEMBLY__ */ -#define PIR_INIT (1 << 0) /* Initialization Trigger */ -#define PIR_ZCAL (1 << 1) /* Impedance Calibration */ -#define PIR_PLLINIT (1 << 4) /* PLL Initialization */ -#define PIR_DCAL (1 << 5) /* DDL Calibration */ -#define PIR_PHYRST (1 << 6) /* PHY Reset */ -#define PIR_DRAMRST (1 << 7) /* DRAM Reset */ -#define PIR_DRAMINIT (1 << 8) /* DRAM Initialization */ -#define PIR_WL (1 << 9) /* Write Leveling */ -#define PIR_QSGATE (1 << 10) /* Read DQS Gate Training */ -#define PIR_WLADJ (1 << 11) /* Write Leveling Adjust */ -#define PIR_RDDSKW (1 << 12) /* Read Data Bit Deskew */ -#define PIR_WRDSKW (1 << 13) /* Write Data Bit Deskew */ -#define PIR_RDEYE (1 << 14) /* Read Data Eye Training */ -#define PIR_WREYE (1 << 15) /* Write Data Eye Training */ -#define PIR_LOCKBYP (1 << 28) /* PLL Lock Bypass */ -#define PIR_DCALBYP (1 << 29) /* DDL Calibration Bypass */ -#define PIR_ZCALBYP (1 << 30) /* Impedance Calib Bypass */ -#define PIR_INITBYP (1 << 31) /* Initialization Bypass */ - -#define PGSR0_IDONE (1 << 0) /* Initialization Done */ -#define PGSR0_PLDONE (1 << 1) /* PLL Lock Done */ -#define PGSR0_DCDONE (1 << 2) /* DDL Calibration Done */ -#define PGSR0_ZCDONE (1 << 3) /* Impedance Calibration Done */ -#define PGSR0_DIDONE (1 << 4) /* DRAM Initialization Done */ -#define PGSR0_WLDONE (1 << 5) /* Write Leveling Done */ -#define PGSR0_QSGDONE (1 << 6) /* DQS Gate Training Done */ -#define PGSR0_WLADONE (1 << 7) /* Write Leveling Adjust Done */ -#define PGSR0_RDDONE (1 << 8) /* Read Bit Deskew Done */ -#define PGSR0_WDDONE (1 << 9) /* Write Bit Deskew Done */ -#define PGSR0_REDONE (1 << 10) /* Read Eye Training Done */ -#define PGSR0_WEDONE (1 << 11) /* Write Eye Training Done */ -#define PGSR0_IERR (1 << 16) /* Initialization Error */ -#define PGSR0_PLERR (1 << 17) /* PLL Lock Error */ -#define PGSR0_DCERR (1 << 18) /* DDL Calibration Error */ -#define PGSR0_ZCERR (1 << 19) /* Impedance Calib Error */ -#define PGSR0_DIERR (1 << 20) /* DRAM Initialization Error */ -#define PGSR0_WLERR (1 << 21) /* Write Leveling Error */ -#define PGSR0_QSGERR (1 << 22) /* DQS Gate Training Error */ -#define PGSR0_WLAERR (1 << 23) /* Write Leveling Adj Error */ -#define PGSR0_RDERR (1 << 24) /* Read Bit Deskew Error */ -#define PGSR0_WDERR (1 << 25) /* Write Bit Deskew Error */ -#define PGSR0_REERR (1 << 26) /* Read Eye Training Error */ -#define PGSR0_WEERR (1 << 27) /* Write Eye Training Error */ +#define PIR_INIT BIT(0) /* Initialization Trigger */ +#define PIR_ZCAL BIT(1) /* Impedance Calibration */ +#define PIR_PLLINIT BIT(4) /* PLL Initialization */ +#define PIR_DCAL BIT(5) /* DDL Calibration */ +#define PIR_PHYRST BIT(6) /* PHY Reset */ +#define PIR_DRAMRST BIT(7) /* DRAM Reset */ +#define PIR_DRAMINIT BIT(8) /* DRAM Initialization */ +#define PIR_WL BIT(9) /* Write Leveling */ +#define PIR_QSGATE BIT(10) /* Read DQS Gate Training */ +#define PIR_WLADJ BIT(11) /* Write Leveling Adjust */ +#define PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */ +#define PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */ +#define PIR_RDEYE BIT(14) /* Read Data Eye Training */ +#define PIR_WREYE BIT(15) /* Write Data Eye Training */ +#define PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */ +#define PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */ +#define PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */ +#define PIR_INITBYP BIT(31) /* Initialization Bypass */ + +#define PGSR0_IDONE BIT(0) /* Initialization Done */ +#define PGSR0_PLDONE BIT(1) /* PLL Lock Done */ +#define PGSR0_DCDONE BIT(2) /* DDL Calibration Done */ +#define PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */ +#define PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */ +#define PGSR0_WLDONE BIT(5) /* Write Leveling Done */ +#define PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */ +#define PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */ +#define PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */ +#define PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */ +#define PGSR0_REDONE BIT(10) /* Read Eye Training Done */ +#define PGSR0_WEDONE BIT(11) /* Write Eye Training Done */ +#define PGSR0_IERR BIT(16) /* Initialization Error */ +#define PGSR0_PLERR BIT(17) /* PLL Lock Error */ +#define PGSR0_DCERR BIT(18) /* DDL Calibration Error */ +#define PGSR0_ZCERR BIT(19) /* Impedance Calib Error */ +#define PGSR0_DIERR BIT(20) /* DRAM Initialization Error */ +#define PGSR0_WLERR BIT(21) /* Write Leveling Error */ +#define PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */ +#define PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */ +#define PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */ +#define PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */ +#define PGSR0_REERR BIT(26) /* Read Eye Training Error */ +#define PGSR0_WEERR BIT(27) /* Write Eye Training Error */ #define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/ #define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT)) -#define PGSR0_APLOCK (1 << 31) /* AC PLL Lock */ +#define PGSR0_APLOCK BIT(31) /* AC PLL Lock */ #define DXCCR_DQSRES_OPEN (0 << 5) #define DXCCR_DQSRES_688_OHM (1 << 5) @@ -146,9 +147,9 @@ struct ddrphy { #define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */ #define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT)) -#define DTCR_DTMPR (1 << 6) /* Data Training using MPR */ -#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */ -#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT)) +#define DTCR_DTMPR BIT(6) /* Data Training using MPR */ +#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */ +#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT)) #define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ #define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT)) diff --git a/arch/arm/mach-uniphier/include/mach/init.h b/arch/arm/mach-uniphier/include/mach/init.h index 5108edd..27ae27d 100644 --- a/arch/arm/mach-uniphier/include/mach/init.h +++ b/arch/arm/mach-uniphier/include/mach/init.h @@ -20,7 +20,7 @@ struct uniphier_board_data { unsigned int dram_freq; }; -const struct uniphier_board_data *uniphier_get_board_param(const void *fdt); +const struct uniphier_board_data *uniphier_get_board_param(void); int ph1_sld3_init(const struct uniphier_board_data *bd); int ph1_ld4_init(const struct uniphier_board_data *bd); diff --git a/arch/arm/mach-uniphier/include/mach/soc_info.h b/arch/arm/mach-uniphier/include/mach/soc_info.h index 623e7ef..3cfd1e9 100644 --- a/arch/arm/mach-uniphier/include/mach/soc_info.h +++ b/arch/arm/mach-uniphier/include/mach/soc_info.h @@ -15,6 +15,8 @@ enum uniphier_soc_id { SOC_UNIPHIER_PH1_PRO5, SOC_UNIPHIER_PROXSTREAM2, SOC_UNIPHIER_PH1_LD6B, + SOC_UNIPHIER_PH1_SLD11, + SOC_UNIPHIER_PH1_LD10, SOC_UNIPHIER_UNKNOWN, }; @@ -25,7 +27,9 @@ enum uniphier_soc_id { IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \ - IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD11) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD10) #define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1) @@ -55,9 +59,18 @@ static inline enum uniphier_soc_id uniphier_get_soc_type(void) #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) return SOC_UNIPHIER_PH1_LD6B; #endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD11) + return SOC_UNIPHIER_PH1_SLD11; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD10) + return SOC_UNIPHIER_PH1_LD10; +#endif return SOC_UNIPHIER_UNKNOWN; } #endif +int uniphier_get_soc_model(void); +int uniphier_get_soc_revision(void); + #endif /* __MACH_SOC_INFO_H__ */ diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c index bbfc8e5..eda169e 100644 --- a/arch/arm/mach-uniphier/init/init.c +++ b/arch/arm/mach-uniphier/init/init.c @@ -9,13 +9,11 @@ #include <mach/init.h> #include <mach/soc_info.h> -DECLARE_GLOBAL_DATA_PTR; - void spl_board_init(void) { const struct uniphier_board_data *param; - param = uniphier_get_board_param(gd->fdt_blob); + param = uniphier_get_board_param(); if (!param) hang(); diff --git a/arch/arm/mach-uniphier/soc_info.c b/arch/arm/mach-uniphier/soc_info.c index 3e8e7f4..6cdeae6 100644 --- a/arch/arm/mach-uniphier/soc_info.c +++ b/arch/arm/mach-uniphier/soc_info.c @@ -51,6 +51,16 @@ enum uniphier_soc_id uniphier_get_soc_type(void) ret = SOC_UNIPHIER_PH1_LD6B; break; #endif +#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD11 + case 0x31: + ret = SOC_UNIPHIER_PH1_SLD11; + break; +#endif +#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD10 + case 0x32: + ret = SOC_UNIPHIER_PH1_LD10; + break; +#endif default: ret = SOC_UNIPHIER_UNKNOWN; break; @@ -59,3 +69,15 @@ enum uniphier_soc_id uniphier_get_soc_type(void) return ret; } #endif + +int uniphier_get_soc_model(void) +{ + return (readl(SG_REVISION) & SG_REVISION_MODEL_MASK) >> + SG_REVISION_MODEL_SHIFT; +} + +int uniphier_get_soc_revision(void) +{ + return (readl(SG_REVISION) & SG_REVISION_REV_MASK) >> + SG_REVISION_REV_SHIFT; +} diff --git a/arch/arm/mach-uniphier/umc/Makefile b/arch/arm/mach-uniphier/umc/Makefile deleted file mode 100644 index 89b2dec..0000000 --- a/arch/arm/mach-uniphier/umc/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o -obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index afe6cc3..d396a13 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -33,7 +33,6 @@ config TARGET_ZYNQ_ZC770 config TARGET_ZYNQ_ZYBO bool "Zynq Zybo Board" - select ZYNQ_CUSTOM_INIT endchoice diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h index 9a51d6b..830e1fe 100644 --- a/arch/arm/mach-zynq/include/mach/hardware.h +++ b/arch/arm/mach-zynq/include/mach/hardware.h @@ -7,15 +7,11 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H -#define ZYNQ_SERIAL_BASEADDR0 0xE0000000 -#define ZYNQ_SERIAL_BASEADDR1 0xE0001000 #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000 #define ZYNQ_SCU_BASEADDR 0xF8F00000 #define ZYNQ_GEM_BASEADDR0 0xE000B000 #define ZYNQ_GEM_BASEADDR1 0xE000C000 -#define ZYNQ_SDHCI_BASEADDR0 0xE0100000 -#define ZYNQ_SDHCI_BASEADDR1 0xE0101000 #define ZYNQ_I2C_BASEADDR0 0xE0004000 #define ZYNQ_I2C_BASEADDR1 0xE0005000 #define ZYNQ_SPI_BASEADDR0 0xE0006000 diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h index 9d50e24..882beab 100644 --- a/arch/arm/mach-zynq/include/mach/sys_proto.h +++ b/arch/arm/mach-zynq/include/mach/sys_proto.h @@ -20,9 +20,6 @@ extern void zynq_ddrc_init(void); extern unsigned int zynq_get_silicon_version(void); /* Driver extern functions */ -extern int zynq_sdhci_init(phys_addr_t regbase); -extern int zynq_sdhci_of_init(const void *blob); - extern void ps7_init(void); #endif /* _SYS_PROTO_H_ */ diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile index 73d40bd..dbca42c 100644 --- a/arch/m68k/lib/Makefile +++ b/arch/m68k/lib/Makefile @@ -5,6 +5,10 @@ # SPDX-License-Identifier: GPL-2.0+ # +## Build a couple of necessary functions into a private libgcc +## if the user asked for it +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += lshrdi3.o muldi3.o ashldi3.o + obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cache.o obj-y += interrupts.o diff --git a/arch/m68k/lib/ashldi3.c b/arch/m68k/lib/ashldi3.c new file mode 100644 index 0000000..be197da --- /dev/null +++ b/arch/m68k/lib/ashldi3.c @@ -0,0 +1,50 @@ +/* + * ashldi3.c extracted from gcc-2.7.2.3/libgcc2.c and + * gcc-2.7.2.3/longlong.h + * + * Copyright (C) 1989-2015 Free Software Foundation, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define BITS_PER_UNIT 8 + +typedef int SItype __attribute__ ((mode (SI))); +typedef unsigned int USItype __attribute__ ((mode (SI))); +typedef int DItype __attribute__ ((mode (DI))); +typedef int word_type __attribute__ ((mode (__word__))); + +struct DIstruct {SItype high, low;}; + +typedef union +{ + struct DIstruct s; + DItype ll; +} DIunion; + +DItype __ashldi3 (DItype u, word_type b) +{ + DIunion w; + word_type bm; + DIunion uu; + + if (b == 0) + return u; + + uu.ll = u; + + bm = (sizeof (SItype) * BITS_PER_UNIT) - b; + if (bm <= 0) + { + w.s.low = 0; + w.s.high = (USItype)uu.s.low << -bm; + } + else + { + USItype carries = (USItype)uu.s.low >> bm; + w.s.low = (USItype)uu.s.low << b; + w.s.high = ((USItype)uu.s.high << b) | carries; + } + + return w.ll; +}
\ No newline at end of file diff --git a/arch/m68k/lib/lshrdi3.c b/arch/m68k/lib/lshrdi3.c new file mode 100644 index 0000000..9052383 --- /dev/null +++ b/arch/m68k/lib/lshrdi3.c @@ -0,0 +1,50 @@ +/* + * lshrdi3.c extracted from gcc-2.7.2.3/libgcc2.c and + * gcc-2.7.2.3/longlong.h + * + * Copyright (C) 1989-2015 Free Software Foundation, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define BITS_PER_UNIT 8 + +typedef int SItype __attribute__ ((mode (SI))); +typedef unsigned int USItype __attribute__ ((mode (SI))); +typedef int DItype __attribute__ ((mode (DI))); +typedef int word_type __attribute__ ((mode (__word__))); + +struct DIstruct {SItype high, low;}; + +typedef union +{ + struct DIstruct s; + DItype ll; +} DIunion; + +DItype __lshrdi3 (DItype u, word_type b) +{ + DIunion w; + word_type bm; + DIunion uu; + + if (b == 0) + return u; + + uu.ll = u; + + bm = (sizeof (SItype) * BITS_PER_UNIT) - b; + if (bm <= 0) + { + w.s.high = 0; + w.s.low = (USItype)uu.s.high >> -bm; + } + else + { + USItype carries = (USItype)uu.s.high << bm; + w.s.high = (USItype)uu.s.high >> b; + w.s.low = ((USItype)uu.s.low >> b) | carries; + } + + return w.ll; +}
\ No newline at end of file diff --git a/arch/m68k/lib/muldi3.c b/arch/m68k/lib/muldi3.c new file mode 100644 index 0000000..d709c32 --- /dev/null +++ b/arch/m68k/lib/muldi3.c @@ -0,0 +1,71 @@ +/* + * muldi3.c extracted from gcc-2.7.2.3/libgcc2.c and + * gcc-2.7.2.3/longlong.h + * + * Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define SI_TYPE_SIZE 32 +#define __BITS4 (SI_TYPE_SIZE / 4) +#define __ll_B (1L << (SI_TYPE_SIZE / 2)) +#define __ll_lowpart(t) ((USItype) (t) % __ll_B) +#define __ll_highpart(t) ((USItype) (t) / __ll_B) + +#define umul_ppmm(w1, w0, u, v) \ + do { \ + USItype __x0, __x1, __x2, __x3; \ + USItype __ul, __vl, __uh, __vh; \ + \ + __ul = __ll_lowpart (u); \ + __uh = __ll_highpart (u); \ + __vl = __ll_lowpart (v); \ + __vh = __ll_highpart (v); \ + \ + __x0 = (USItype) __ul * __vl; \ + __x1 = (USItype) __ul * __vh; \ + __x2 = (USItype) __uh * __vl; \ + __x3 = (USItype) __uh * __vh; \ + \ + __x1 += __ll_highpart (__x0);/* this can't give carry */ \ + __x1 += __x2; /* but this indeed can */ \ + if (__x1 < __x2) /* did we get it? */ \ + __x3 += __ll_B; /* yes, add it in the proper pos. */ \ + \ + (w1) = __x3 + __ll_highpart (__x1); \ + (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \ + } while (0) + +#define __umulsidi3(u, v) \ + ({DIunion __w; \ + umul_ppmm (__w.s.high, __w.s.low, u, v); \ + __w.ll; }) + +typedef int SItype __attribute__ ((mode (SI))); +typedef unsigned int USItype __attribute__ ((mode (SI))); +typedef int DItype __attribute__ ((mode (DI))); +typedef int word_type __attribute__ ((mode (__word__))); + +struct DIstruct {SItype high, low;}; + +typedef union +{ + struct DIstruct s; + DItype ll; +} DIunion; + +DItype __muldi3 (DItype u, DItype v) +{ + DIunion w; + DIunion uu, vv; + + uu.ll = u, + vv.ll = v; + + w.ll = __umulsidi3 (uu.s.low, vv.s.low); + w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high + + (USItype) uu.s.high * (USItype) vv.s.low); + + return w.ll; +} diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 077b2a7..604f681 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -11,6 +11,8 @@ choice config TARGET_MICROBLAZE_GENERIC bool "Support microblaze-generic" select SUPPORT_SPL + select OF_CONTROL + select DM endchoice diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index f6d5cd3..be7f99c 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -21,6 +21,14 @@ int print_cpuinfo(void) } #endif /* CONFIG_DISPLAY_CPUINFO */ +#ifdef CONFIG_ALTERA_SYSID +int checkboard(void) +{ + display_sysid(); + return 0; +} +#endif + int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { disable_interrupts(); diff --git a/arch/nios2/dts/10m50_devboard.dts b/arch/nios2/dts/10m50_devboard.dts index e89dbb2..05eac30 100644 --- a/arch/nios2/dts/10m50_devboard.dts +++ b/arch/nios2/dts/10m50_devboard.dts @@ -262,6 +262,6 @@ chosen { bootargs = "debug console=ttyS0,115200"; - stdout-path = &uart_0; + stdout-path = &a_16550_uart_0; }; }; diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index b368562..a493556 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -7,7 +7,7 @@ #include <common.h> #include <command.h> #include <linux/compiler.h> -#include <asm/fsl_errata.h> +#include <fsl_errata.h> #include <asm/processor.h> #include <fsl_usb.h> #include "fsl_corenet_serdes.h" diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4cf8853..13a7d0f 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -19,7 +19,7 @@ #include <asm/io.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <asm/fsl_errata.h> +#include <fsl_errata.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h> diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index acb1353..9920839 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -11,7 +11,7 @@ #include <asm/processor.h> #include <asm/fsl_law.h> #include <asm/errno.h> -#include <asm/fsl_errata.h> +#include <fsl_errata.h> #include "fsl_corenet2_serdes.h" #ifdef CONFIG_SYS_FSL_SRDS_1 @@ -184,7 +184,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u32 cfg; int lane; - memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); + memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 struct ccsr_sfp_regs __iomem *sfp_regs = (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR); diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 945e771..efd3165 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -152,7 +152,7 @@ source "board/gdsys/405ex/Kconfig" source "board/gdsys/dlvision/Kconfig" source "board/gdsys/gdppc440etx/Kconfig" source "board/gdsys/intip/Kconfig" -source "board/lwmon5/Kconfig" +source "board/liebherr/lwmon5/Kconfig" source "board/mosaixtech/icon/Kconfig" source "board/mpl/mip405/Kconfig" source "board/mpl/pip405/Kconfig" diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 77d4040..3dd0557 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -1795,34 +1795,11 @@ ppc405ep_init: ..no_pllset: #endif /* CONFIG_BUBINGA */ -#ifdef CONFIG_TAIHU - mfdcr r4, CPC0_BOOT - andi. r5, r4, CPC0_BOOT_SEP@l - bne strap_1 /* serial eeprom present */ - addis r5,0,CPLD_REG0_ADDR@h - ori r5,r5,CPLD_REG0_ADDR@l - andi. r5, r5, 0x10 - bne _pci_66mhz -#endif /* CONFIG_TAIHU */ - addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ ori r3,r3,PLLMR0_DEFAULT@l /* */ addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ ori r4,r4,PLLMR1_DEFAULT@l /* */ -#ifdef CONFIG_TAIHU - b 1f -_pci_66mhz: - addis r3,0,PLLMR0_DEFAULT_PCI66@h - ori r3,r3,PLLMR0_DEFAULT_PCI66@l - addis r4,0,PLLMR1_DEFAULT_PCI66@h - ori r4,r4,PLLMR1_DEFAULT_PCI66@l - b 1f -strap_1: - mfdcr r3, CPC0_PLLMR0 - mfdcr r4, CPC0_PLLMR1 -#endif /* CONFIG_TAIHU */ - 1: b pll_write /* Write the CPC0_PLLMR with new value */ diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 65496d0..bb23756 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -104,4 +104,12 @@ /* All PPC boards must swap IDE bytes */ #define CONFIG_IDE_SWAP_IO +#if defined(CONFIG_DM_SERIAL) +/* + * TODO: Convert this to a clock driver exists that can give us the UART + * clock here. + */ +#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif + #endif /* _ASM_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7a5487b..674fac8 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -807,6 +807,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 +#define CONFIG_SYS_FSL_ERRATUM_A008378 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) @@ -854,6 +855,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 +#define CONFIG_SYS_FSL_ERRATUM_A008378 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 720ef93..d2addb4 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -179,6 +179,7 @@ timer { compatible = "sandbox,timer"; + clock-frequency = <1000000>; }; tpm { diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 04dc08f..1d1347b 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -12,6 +12,15 @@ config LEON3 bool select LEON +config SYS_SPARC_NWINDOWS + int "Number of SPARC register windows" + range 2 32 + default "8" + help + Specify the number of SPARC register windows implemented by this + processor. A SPARC implementation can have from 2 to 32 windows. + If unsure, choose 8. + choice prompt "Board select" optional diff --git a/arch/sparc/cpu/leon2/cpu.c b/arch/sparc/cpu/leon2/cpu.c index 380c397..d044c3a 100644 --- a/arch/sparc/cpu/leon2/cpu.c +++ b/arch/sparc/cpu/leon2/cpu.c @@ -1,7 +1,7 @@ /* CPU specific code for the LEON2 CPU * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com + * (C) Copyright 2007, 2015 + * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com * * SPDX-License-Identifier: GPL-2.0+ */ @@ -22,6 +22,16 @@ int checkcpu(void) return 0; } +#ifdef CONFIG_DISPLAY_CPUINFO + +int print_cpuinfo(void) +{ + printf("CPU: LEON2\n"); + return 0; +} + +#endif + /* ------------------------------------------------------------------------- */ void cpu_reset(void) diff --git a/arch/sparc/cpu/leon2/cpu_init.c b/arch/sparc/cpu/leon2/cpu_init.c index 6e07fe6..9dfb99c 100644 --- a/arch/sparc/cpu/leon2/cpu_init.c +++ b/arch/sparc/cpu/leon2/cpu_init.c @@ -1,8 +1,8 @@ /* Initializes CPU and basic hardware such as memory * controllers, IRQ controller and system timer 0. * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com + * (C) Copyright 2007, 2015 + * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,22 +10,12 @@ #include <common.h> #include <asm/asi.h> #include <asm/leon.h> +#include <asm/io.h> #include <config.h> -#define TIMER_BASE_CLK 1000000 -#define US_PER_TICK (1000000 / CONFIG_SYS_HZ) - DECLARE_GLOBAL_DATA_PTR; -/* reset CPU (jump to 0, without reset) */ -void start(void); - -struct { - gd_t gd_area; - bd_t bd; -} global_data; - /* * Breath some life into the CPU... * @@ -50,82 +40,56 @@ void cpu_init_f(void) /* cache */ - /* I/O port setup */ + /* I/O port setup */ #ifdef LEON2_IO_PORT_DIR - leon2->PIO_Direction = LEON2_IO_PORT_DIR; + leon2->PIO_Direction = LEON2_IO_PORT_DIR; #endif #ifdef LEON2_IO_PORT_DATA - leon2->PIO_Data = LEON2_IO_PORT_DATA; + leon2->PIO_Data = LEON2_IO_PORT_DATA; #endif #ifdef LEON2_IO_PORT_INT - leon2->PIO_Interrupt = LEON2_IO_PORT_INT; + leon2->PIO_Interrupt = LEON2_IO_PORT_INT; #else - leon2->PIO_Interrupt = 0; + leon2->PIO_Interrupt = 0; #endif + + /* disable timers */ + leon2->Timer_Control_1 = leon2->Timer_Control_2 = 0; } -void cpu_init_f2(void) +int arch_cpu_init(void) { + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; + gd->bus_clk = CONFIG_SYS_CLK_FREQ; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + return 0; } /* - * initialize higher level parts of CPU like time base and timers + * initialize higher level parts of CPU */ int cpu_init_r(void) { - LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; - - /* initialize prescaler common to all timers to 1MHz */ - leon2->Scaler_Counter = leon2->Scaler_Reload = - (((CONFIG_SYS_CLK_FREQ / 1000) + 500) / 1000) - 1; - - return (0); + return 0; } -/* Uses Timer 0 to get accurate - * pauses. Max 2 raised to 32 ticks - * +/* initiate and setup timer0 to configured HZ. Base clock is 1MHz. */ -void cpu_wait_ticks(unsigned long ticks) +int timer_init(void) { - unsigned long start = get_timer(0); - while (get_timer(start) < ticks) ; -} + LEON2_regs *leon2 = (LEON2_regs *)LEON2_PREGS; -/* initiate and setup timer0 interrupt to configured HZ. Base clock is 1MHz. - * Return irq number for timer int or a negative number for - * dealing with self - */ -int timer_interrupt_init_cpu(void) -{ - LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; + /* initialize prescaler common to all timers to 1MHz */ + leon2->Scaler_Counter = leon2->Scaler_Reload = + (((CONFIG_SYS_CLK_FREQ / 1000) + 500) / 1000) - 1; /* SYS_HZ ticks per second */ leon2->Timer_Counter_1 = 0; - leon2->Timer_Reload_1 = (TIMER_BASE_CLK / CONFIG_SYS_HZ) - 1; - leon2->Timer_Control_1 = - (LEON2_TIMER_CTRL_EN | LEON2_TIMER_CTRL_RS | LEON2_TIMER_CTRL_LD); - - return LEON2_TIMER1_IRQNO; -} - -ulong get_tbclk(void) -{ - return TIMER_BASE_CLK; -} + leon2->Timer_Reload_1 = (CONFIG_SYS_TIMER_RATE / CONFIG_SYS_HZ) - 1; + leon2->Timer_Control_1 = LEON2_TIMER_CTRL_EN | LEON2_TIMER_CTRL_RS | + LEON2_TIMER_CTRL_LD; -/* - * This function is intended for SHORT delays only. - */ -unsigned long cpu_usec2ticks(unsigned long usec) -{ - if (usec < US_PER_TICK) - return 1; - return usec / US_PER_TICK; -} - -unsigned long cpu_ticks2usec(unsigned long ticks) -{ - return ticks * US_PER_TICK; + CONFIG_SYS_TIMER_COUNTER = (void *)&leon2->Timer_Counter_1; + return 0; } diff --git a/arch/sparc/cpu/leon2/interrupts.c b/arch/sparc/cpu/leon2/interrupts.c index f78ec8a..602e4a6 100644 --- a/arch/sparc/cpu/leon2/interrupts.c +++ b/arch/sparc/cpu/leon2/interrupts.c @@ -118,20 +118,6 @@ int interrupt_init_cpu(void) /****************************************************************************/ -/* Handle Timer 0 IRQ */ -void timer_interrupt_cpu(void *arg) -{ - LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; - - leon2->Timer_Control_1 = - (LEON2_TIMER_CTRL_EN | LEON2_TIMER_CTRL_RS | LEON2_TIMER_CTRL_LD); - - /* nothing to do here */ - return; -} - -/****************************************************************************/ - /* * Install and free a interrupt handler. */ diff --git a/arch/sparc/cpu/leon2/prom.c b/arch/sparc/cpu/leon2/prom.c index cd2571f..7829e7a 100644 --- a/arch/sparc/cpu/leon2/prom.c +++ b/arch/sparc/cpu/leon2/prom.c @@ -25,6 +25,8 @@ extern struct linux_romvec *kernel_arg_promvec; #define PROM_TEXT __attribute__ ((__section__ (".prom.text"))) #define PROM_DATA __attribute__ ((__section__ (".prom.data"))) +void *__prom_start_reloc; /* relocated prom_start address */ + /* for __va */ extern int __prom_start; #define PAGE_OFFSET 0xf0000000 diff --git a/arch/sparc/cpu/leon2/serial.c b/arch/sparc/cpu/leon2/serial.c index 603364e..460abd1 100644 --- a/arch/sparc/cpu/leon2/serial.c +++ b/arch/sparc/cpu/leon2/serial.c @@ -120,7 +120,7 @@ static void leon2_serial_setbrg(void) if (!gd->baudrate) gd->baudrate = CONFIG_BAUDRATE; - scaler = leon2_serial_calc_scaler(CONFIG_SYS_CLK_FREQ, CONFIG_BAUDRATE); + scaler = leon2_serial_calc_scaler(CONFIG_SYS_CLK_FREQ, gd->baudrate); writel(scaler, &uart->UART_Scaler); } diff --git a/arch/sparc/cpu/leon2/start.S b/arch/sparc/cpu/leon2/start.S index 974de76..1b404da 100644 --- a/arch/sparc/cpu/leon2/start.S +++ b/arch/sparc/cpu/leon2/start.S @@ -1,6 +1,7 @@ /* This is where the SPARC/LEON3 starts - * Copyright (C) 2007, - * Daniel Hellstrom, daniel@gaisler.com + * + * Copyright (C) 2007, 2015 + * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com * * SPDX-License-Identifier: GPL-2.0+ */ @@ -12,7 +13,6 @@ #include <asm/psr.h> #include <asm/stack.h> #include <asm/leon.h> -#include <version.h> /* Entry for traps which jump to a programmer-specified trap handler. */ #define TRAPR(H) \ @@ -197,14 +197,6 @@ _trap_table: SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f4-f7 SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f8-fb SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! fc-ff -/* - * Version string - */ - - .data - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" .section ".text" .align 4 @@ -318,30 +310,62 @@ leon2_init_stackp: andn %fp, 0x0f, %fp sub %fp, 64, %sp +leon2_init_tbr: + set CONFIG_SYS_TEXT_BASE, %g2 + wr %g0, %g2, %tbr + nop + nop + nop + cpu_init_unreloc: call cpu_init_f nop +board_init_unreloc: + call board_init_f + clr %o0 ! boot_flags + +dead_unreloc: + ba dead_unreloc ! infinte loop + nop + +!------------------------------------------------------------------------------- + +/* void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM after + * relocating the monitor code. + * + * %o0 = Relocated stack pointer + * %o1 = Relocated global data pointer + * %o2 = Relocated text pointer + */ + .globl relocate_code + .type relocate_code, #function + .align 4 +relocate_code: + SPARC_PIC_THUNK_CALL(l7) + /* un relocated start address of monitor */ #define TEXT_START _text /* un relocated end address of monitor */ #define DATA_END __init_end - SPARC_PIC_THUNK_CALL(l7) reloc: SPARC_LOAD_ADDRESS(TEXT_START, l7, g2) SPARC_LOAD_ADDRESS(DATA_END, l7, g3) - set CONFIG_SYS_RELOC_MONITOR_BASE,%g4 -reloc_loop: - ldd [%g2],%l0 - ldd [%g2+8],%l2 - std %l0,[%g4] - std %l2,[%g4+8] - inc 16,%g2 - subcc %g3,%g2,%g0 - bne reloc_loop - inc 16,%g4 + mov %o2, %g4 ! relocation address + sub %g4, %g2, %g6 ! relocation offset + /* copy .text & .data to relocated address */ +10: ldd [%g2], %l0 + ldd [%g2+8], %l2 + std %l0, [%g4] + std %l2, [%g4+8] + inc 16, %g2 ! src += 16 + cmp %g2, %g3 + bcs 10b ! while (src < end) + inc 16, %g4 ! dst += 16 clr %l0 clr %l1 @@ -356,91 +380,93 @@ reloc_loop: * */ + /* clear bss area (the relocated) */ clr_bss: -/* clear bss area (the relocated) */ SPARC_LOAD_ADDRESS(__bss_start, l7, g2) SPARC_LOAD_ADDRESS(__bss_end, l7, g3) - sub %g3,%g2,%g3 + sub %g3,%g2,%g3 ! length of .bss area add %g3,%g4,%g3 + /* clearing 16byte a time ==> linker script need to align to 16 byte offset */ clr %g1 /* std %g0 uses g0 and g1 */ -/* clearing 16byte a time ==> linker script need to align to 16 byte offset */ -clr_bss_16: - std %g0,[%g4] - std %g0,[%g4+8] - inc 16,%g4 - cmp %g3,%g4 - bne clr_bss_16 +20: + std %g0, [%g4] + std %g0, [%g4+8] + inc 16, %g4 ! ptr += 16 + cmp %g4, %g3 + bcs 20b ! while (ptr < end) nop -/* add offsets to GOT table */ + /* add offsets to GOT table */ fixup_got: SPARC_LOAD_ADDRESS(__got_start, l7, g4) + add %g4, %g6, %g4 SPARC_LOAD_ADDRESS(__got_end, l7, g3) -/* - * new got offset = (old GOT-PTR (read with ld) - - * CONFIG_SYS_RELOC_MONITOR_BASE(from define) ) + - * Destination Address (from define) - */ - set CONFIG_SYS_RELOC_MONITOR_BASE,%g2 - SPARC_LOAD_ADDRESS(TEXT_START, l7, g1) - add %g4,%g2,%g4 - sub %g4,%g1,%g4 - add %g3,%g2,%g3 - sub %g3,%g1,%g3 - sub %g2,%g1,%g2 ! prepare register with (new base address) - - ! (old base address) -got_loop: - ld [%g4],%l0 ! load old GOT-PTR - add %l0,%g2,%l0 ! increase with (new base address) - - ! (old base) - st %l0,[%g4] - inc 4,%g4 - cmp %g3,%g4 - bne got_loop + add %g3, %g6, %g3 +30: ld [%g4], %l0 ! load old GOT-PTR +#ifdef CONFIG_RELOC_GOT_SKIP_NULL + cmp %l0, 0 + be 32f +#endif + add %l0, %g6, %l0 ! relocate GOT pointer + st %l0, [%g4] +32: inc 4, %g4 ! ptr += 4 + cmp %g4, %g3 + bcs 30b ! while (ptr < end) nop prom_relocate: SPARC_LOAD_ADDRESS(__prom_start, l7, g2) SPARC_LOAD_ADDRESS(__prom_end, l7, g3) - set CONFIG_SYS_PROM_OFFSET, %g4 - -prom_relocate_loop: - ldd [%g2],%l0 - ldd [%g2+8],%l2 - std %l0,[%g4] - std %l2,[%g4+8] - inc 16,%g2 - subcc %g3,%g2,%g0 - bne prom_relocate_loop - inc 16,%g4 + /* + * Calculated addres is stored in this variable by + * reserve_prom() function in common/board_f.c + */ + SPARC_LOAD_ADDRESS(__prom_start_reloc, l7, g4) + ld [%g4], %g4 + +40: ldd [%g2], %l0 + ldd [%g2+8], %l2 + std %l0, [%g4] + std %l2, [%g4+8] + inc 16, %g2 + cmp %g2, %g3 + bcs 40b + inc 16, %g4 + +! %o0 = stack pointer (relocated) +! %o1 = global data pointer (relocated) +! %o2 = text pointer (relocated) + +! %g6 = relocation offset +! %l7 = _GLOBAL_OFFSET_TABLE_ /* Trap table has been moved, lets tell CPU about * the new trap table address */ - - set CONFIG_SYS_RELOC_MONITOR_BASE, %g2 - wr %g0, %g2, %tbr - -/* call relocate*/ +update_trap_table_address: + wr %g0, %o2, %tbr + nop + nop nop -/* Call relocated init functions */ -jump: - SPARC_LOAD_ADDRESS(cpu_init_f2, l7, o1) - set CONFIG_SYS_RELOC_MONITOR_BASE,%o2 - add %o1,%o2,%o1 - sub %o1,%g1,%o1 - call %o1 - clr %o0 - SPARC_LOAD_ADDRESS(board_init_f, l7, o1) - set CONFIG_SYS_RELOC_MONITOR_BASE,%o2 - add %o1,%o2,%o1 - sub %o1,%g1,%o1 - call %o1 - clr %o0 +update_stack_pointers: + mov %o0, %fp + andn %fp, 0x0f, %fp ! align to 16 bytes + add %fp, -64, %fp ! make space for a window push + mov %fp, %sp ! setup stack pointer + +jump_board_init_r: + mov %o1, %o0 ! relocated global data pointer + mov %o2, %o1 ! relocated text pointer + SPARC_LOAD_ADDRESS(board_init_r, l7, o3) + add %o3, %g6, %o3 ! add relocation offset + call %o3 + nop dead: ta 0 ! if call returns... - nop + nop + +!------------------------------------------------------------------------------ /* Interrupt handler caller, * reg L7: interrupt number @@ -469,7 +495,11 @@ _irq_entry: RESTORE_ALL -!Window overflow trap handler. +!------------------------------------------------------------------------------ + +/* + * Window overflow trap handler. + */ .global _window_overflow _window_overflow: @@ -477,14 +507,12 @@ _window_overflow: mov %wim, %l3 ! Calculate next WIM mov %g1, %l7 srl %l3, 1, %g1 - sll %l3, (CONFIG_SYS_SPARC_NWINDOWS-1) , %l4 + sll %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l4 or %l4, %g1, %g1 save ! Get into window to be saved. mov %g1, %wim - nop; - nop; - nop + nop; nop; nop st %l0, [%sp + 0]; st %l1, [%sp + 4]; st %l2, [%sp + 8]; @@ -506,8 +534,9 @@ _window_overflow: jmp %l1 ! Re-execute save. rett %l2 -/* Window underflow trap handler. */ - +/* + * Window underflow trap handler. + */ .global _window_underflow _window_underflow: @@ -541,7 +570,7 @@ _window_underflow: jmp %l1 ! Re-execute restore. rett %l2 - retl +!------------------------------------------------------------------------------ _nmi_trap: nop diff --git a/arch/sparc/cpu/leon3/ambapp.c b/arch/sparc/cpu/leon3/ambapp.c index b8ac05f..47769cf 100644 --- a/arch/sparc/cpu/leon3/ambapp.c +++ b/arch/sparc/cpu/leon3/ambapp.c @@ -40,7 +40,7 @@ extern int ambapp_find_ahb(struct ambapp_bus *abus, unsigned int dev_vend, int index, int type, struct ambapp_find_ahb_info *result); /************ C ROUTINES USED BY U-BOOT AMBA CORE DRIVERS ************/ -struct ambapp_bus ambapp_plb; +struct ambapp_bus ambapp_plb __section(.data); void ambapp_bus_init( unsigned int ioarea, diff --git a/arch/sparc/cpu/leon3/cpu.c b/arch/sparc/cpu/leon3/cpu.c index 8ab3150..149e5c6 100644 --- a/arch/sparc/cpu/leon3/cpu.c +++ b/arch/sparc/cpu/leon3/cpu.c @@ -1,7 +1,7 @@ /* CPU specific code for the LEON3 CPU * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com + * (C) Copyright 2007, 2015 + * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com * * SPDX-License-Identifier: GPL-2.0+ */ @@ -13,18 +13,72 @@ #include <asm/io.h> #include <asm/processor.h> +#include <ambapp.h> DECLARE_GLOBAL_DATA_PTR; extern void _reset_reloc(void); +int leon_cpu_cnt = 1; +int leon_ver = 3; +unsigned int leon_cpu_freq = CONFIG_SYS_CLK_FREQ; + +int cpu_freq(void) +{ + ambapp_ahbdev dev; + + if (leon_ver == 3) { + ambapp_ahbmst_find(&ambapp_plb, VENDOR_GAISLER, + GAISLER_LEON3, 0, &dev); + } else { + ambapp_ahbmst_find(&ambapp_plb, VENDOR_GAISLER, + GAISLER_LEON4, 0, &dev); + } + + leon_cpu_freq = ambapp_bus_freq(&ambapp_plb, dev.ahb_bus_index); + + return 0; +} + int checkcpu(void) { + int cnt; + char str[4]; + /* check LEON version here */ - printf("CPU: LEON3\n"); + cnt = ambapp_ahbmst_count(&ambapp_plb, VENDOR_GAISLER, GAISLER_LEON3); + if (cnt <= 0) { + cnt = ambapp_ahbmst_count(&ambapp_plb, VENDOR_GAISLER, + GAISLER_LEON4); + if (cnt > 0) + leon_ver = 4; + } + + cpu_freq(); + + str[0] = '\0'; + if (cnt > 1) { + leon_cpu_cnt = cnt; + str[0] = '0' + cnt; + str[1] = 'x'; + str[2] = '\0'; + } + printf("CPU: %sLEON%d @ %dMHz\n", str, leon_ver, + leon_cpu_freq / 1000000); + return 0; } +#ifdef CONFIG_DISPLAY_CPUINFO + +int print_cpuinfo(void) +{ + printf("CPU: LEON3\n"); + return 0; +} + +#endif + /* ------------------------------------------------------------------------- */ void cpu_reset(void) diff --git a/arch/sparc/cpu/leon3/cpu_init.c b/arch/sparc/cpu/leon3/cpu_init.c index b140da3..f25388c 100644 --- a/arch/sparc/cpu/leon3/cpu_init.c +++ b/arch/sparc/cpu/leon3/cpu_init.c @@ -10,6 +10,7 @@ #include <common.h> #include <asm/asi.h> #include <asm/leon.h> +#include <asm/io.h> #include <ambapp.h> #include <grlib/irqmp.h> #include <grlib/gptimer.h> @@ -22,23 +23,14 @@ #define CONFIG_AMBAPP_IOAREA AMBA_DEFAULT_IOAREA #endif -#define TIMER_BASE_CLK 1000000 -#define US_PER_TICK (1000000 / CONFIG_SYS_HZ) +/* Select which TIMER that will become the time base */ +#ifndef CONFIG_SYS_GRLIB_GPTIMER_INDEX +#define CONFIG_SYS_GRLIB_GPTIMER_INDEX 0 +#endif DECLARE_GLOBAL_DATA_PTR; -/* reset CPU (jump to 0, without reset) */ -void start(void); - ambapp_dev_irqmp *irqmp = NULL; -ambapp_dev_gptimer *gptimer = NULL; -unsigned int gptimer_irq = 0; -int leon3_snooping_avail = 0; - -struct { - gd_t gd_area; - bd_t bd; -} global_data; /* * Breath some life into the CPU... @@ -56,19 +48,62 @@ void cpu_init_f(void) #endif } -/* Routine called from start.S, - * - * Run from FLASH/PROM: - * - memory controller has already been setup up, stack can be used - * - global variables available for read/writing - * - constants avaiable - */ -void cpu_init_f2(void) +/* If cache snooping is available in hardware the result will be set + * to 0x800000, otherwise 0. + */ +static unsigned int snoop_detect(void) { + unsigned int result; + asm("lda [%%g0] 2, %0" : "=r"(result)); + return result & 0x00800000; +} + +int arch_cpu_init(void) +{ + ambapp_apbdev apbdev; + int index; + + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; + gd->bus_clk = CONFIG_SYS_CLK_FREQ; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + gd->arch.snooping_available = snoop_detect(); + /* Initialize the AMBA Plug & Play bus structure, the bus * structure represents the AMBA bus that the CPU is located at. */ ambapp_bus_init(CONFIG_AMBAPP_IOAREA, CONFIG_SYS_CLK_FREQ, &ambapp_plb); + + /* Initialize/clear all the timers in the system. + */ + for (index = 0; ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER, + GAISLER_GPTIMER, index, &apbdev) == 1; index++) { + ambapp_dev_gptimer *timer; + unsigned int bus_freq; + int i, ntimers; + + timer = (ambapp_dev_gptimer *)apbdev.address; + + /* Different buses may have different frequency, the + * frequency of the bus tell in which frequency the timer + * prescaler operates. + */ + bus_freq = ambapp_bus_freq(&ambapp_plb, apbdev.ahb_bus_index); + + /* Initialize prescaler common to all timers to 1MHz */ + timer->scalar = timer->scalar_reload = + (((bus_freq / 1000) + 500) / 1000) - 1; + + /* Clear all timers */ + ntimers = timer->config & 0x7; + for (i = 0; i < ntimers; i++) { + timer->e[i].ctrl = GPTIMER_CTRL_IP; + timer->e[i].rld = 0; + timer->e[i].ctrl = GPTIMER_CTRL_LD; + } + } + + return 0; } /* @@ -77,9 +112,7 @@ void cpu_init_f2(void) int cpu_init_r(void) { ambapp_apbdev apbdev; - int index, cpu; - ambapp_dev_gptimer *timer = NULL; - unsigned int bus_freq; + int cpu; /* * Find AMBA APB IRQMP Controller, @@ -102,77 +135,41 @@ int cpu_init_r(void) irqmp->cpu_force[cpu] = 0; } - /* timer */ - index = 0; - while (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER, GAISLER_GPTIMER, - index, &apbdev) == 1) { - timer = (ambapp_dev_gptimer *)apbdev.address; - if (gptimer == NULL) { - gptimer = timer; - gptimer_irq = apbdev.irq; - } - - /* Different buses may have different frequency, the - * frequency of the bus tell in which frequency the timer - * prescaler operates. - */ - bus_freq = ambapp_bus_freq(&ambapp_plb, apbdev.ahb_bus_index); - - /* initialize prescaler common to all timers to 1MHz */ - timer->scalar = timer->scalar_reload = - (((bus_freq / 1000) + 500) / 1000) - 1; - - index++; - } - if (!gptimer) { - printf("%s: gptimer not found!\n", __func__); - return 1; - } return 0; } -/* Uses Timer 0 to get accurate - * pauses. Max 2 raised to 32 ticks - * - */ -void cpu_wait_ticks(unsigned long ticks) + ; +int timer_init(void) { - unsigned long start = get_timer(0); - while (get_timer(start) < ticks) ; -} + ambapp_dev_gptimer_element *tmr; + ambapp_dev_gptimer *gptimer; + ambapp_apbdev apbdev; + unsigned bus_freq; -/* initiate and setup timer0 interrupt to configured HZ. Base clock is 1MHz. - * Return irq number for timer int or a negative number for - * dealing with self - */ -int timer_interrupt_init_cpu(void) -{ - /* SYS_HZ ticks per second */ - gptimer->e[0].val = 0; - gptimer->e[0].rld = (TIMER_BASE_CLK / CONFIG_SYS_HZ) - 1; - gptimer->e[0].ctrl = - (GPTIMER_CTRL_EN | GPTIMER_CTRL_RS | - GPTIMER_CTRL_LD | GPTIMER_CTRL_IE); - - return gptimer_irq; -} + if (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER, GAISLER_GPTIMER, + CONFIG_SYS_GRLIB_GPTIMER_INDEX, &apbdev) != 1) { + panic("%s: gptimer not found!\n", __func__); + return -1; + } -ulong get_tbclk(void) -{ - return TIMER_BASE_CLK; -} + gptimer = (ambapp_dev_gptimer *) apbdev.address; -/* - * This function is intended for SHORT delays only. - */ -unsigned long cpu_usec2ticks(unsigned long usec) -{ - if (usec < US_PER_TICK) - return 1; - return usec / US_PER_TICK; -} + /* Different buses may have different frequency, the + * frequency of the bus tell in which frequency the timer + * prescaler operates. + */ + bus_freq = ambapp_bus_freq(&ambapp_plb, apbdev.ahb_bus_index); -unsigned long cpu_ticks2usec(unsigned long ticks) -{ - return ticks * US_PER_TICK; + /* initialize prescaler common to all timers to 1MHz */ + gptimer->scalar = gptimer->scalar_reload = + (((bus_freq / 1000) + 500) / 1000) - 1; + + tmr = (ambapp_dev_gptimer_element *)&gptimer->e[0]; + + tmr->val = 0; + tmr->rld = ~0; + tmr->ctrl = GPTIMER_CTRL_EN | GPTIMER_CTRL_RS | GPTIMER_CTRL_LD; + + CONFIG_SYS_TIMER_COUNTER = (void *)&tmr->val; + return 0; } diff --git a/arch/sparc/cpu/leon3/interrupts.c b/arch/sparc/cpu/leon3/interrupts.c index 2312b58..00c3288 100644 --- a/arch/sparc/cpu/leon3/interrupts.c +++ b/arch/sparc/cpu/leon3/interrupts.c @@ -124,17 +124,6 @@ int interrupt_init_cpu(void) /****************************************************************************/ -/* Handle Timer 0 IRQ */ -void timer_interrupt_cpu(void *arg) -{ - gptimer->e[0].ctrl = (GPTIMER_CTRL_EN | GPTIMER_CTRL_RS | - GPTIMER_CTRL_LD | GPTIMER_CTRL_IE); - /* nothing to do here */ - return; -} - -/****************************************************************************/ - /* * Install and free a interrupt handler. */ diff --git a/arch/sparc/cpu/leon3/prom.c b/arch/sparc/cpu/leon3/prom.c index c391be7..1f185b7 100644 --- a/arch/sparc/cpu/leon3/prom.c +++ b/arch/sparc/cpu/leon3/prom.c @@ -33,6 +33,8 @@ DECLARE_GLOBAL_DATA_PTR; ambapp_dev_gptimer *gptimer; +void *__prom_start_reloc; /* relocated prom_start address */ + /* for __va */ extern int __prom_start; #define PAGE_OFFSET 0xf0000000 diff --git a/arch/sparc/cpu/leon3/serial.c b/arch/sparc/cpu/leon3/serial.c index 66b3773..bc6e7a1 100644 --- a/arch/sparc/cpu/leon3/serial.c +++ b/arch/sparc/cpu/leon3/serial.c @@ -17,8 +17,18 @@ DECLARE_GLOBAL_DATA_PTR; /* Select which UART that will become u-boot console */ #ifndef CONFIG_SYS_GRLIB_APBUART_INDEX +/* Try to use CONFIG_CONS_INDEX, if available, it is numbered from 1 */ +#ifdef CONFIG_CONS_INDEX +#define CONFIG_SYS_GRLIB_APBUART_INDEX (CONFIG_CONS_INDEX - 1) +#else #define CONFIG_SYS_GRLIB_APBUART_INDEX 0 #endif +#endif + +static unsigned apbuart_calc_scaler(unsigned apbuart_freq, unsigned baud) +{ + return (((apbuart_freq * 10) / (baud * 8)) - 5) / 10; +} static int leon3_serial_init(void) { @@ -29,6 +39,7 @@ static int leon3_serial_init(void) /* find UART */ if (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER, GAISLER_APBUART, CONFIG_SYS_GRLIB_APBUART_INDEX, &apbdev) != 1) { + gd->flags &= ~GD_FLG_SERIAL_READY; panic("%s: apbuart not found!\n", __func__); return -1; /* didn't find hardware */ } @@ -36,8 +47,11 @@ static int leon3_serial_init(void) /* found apbuart, let's init .. */ uart = (ambapp_dev_apbuart *) apbdev.address; + /* APBUART Frequency is equal to bus frequency */ + gd->arch.uart_freq = ambapp_bus_freq(&ambapp_plb, apbdev.ahb_bus_index); + /* Set scaler / baud rate */ - tmp = (((CONFIG_SYS_CLK_FREQ*10) / (CONFIG_BAUDRATE*8)) - 5)/10; + tmp = apbuart_calc_scaler(gd->arch.uart_freq, CONFIG_BAUDRATE); writel(tmp, &uart->scaler); /* Let bit 11 be unchanged (debug bit for GRMON) */ @@ -122,7 +136,10 @@ static void leon3_serial_setbrg(void) if (!gd->baudrate) gd->baudrate = CONFIG_BAUDRATE; - scaler = (((CONFIG_SYS_CLK_FREQ*10) / (gd->baudrate*8)) - 5)/10; + if (!gd->arch.uart_freq) + gd->arch.uart_freq = CONFIG_SYS_CLK_FREQ; + + scaler = apbuart_calc_scaler(gd->arch.uart_freq, gd->baudrate); writel(scaler, &uart->scaler); } @@ -155,7 +172,7 @@ __weak struct serial_device *default_serial_console(void) static inline void _debug_uart_init(void) { ambapp_dev_apbuart *uart = (ambapp_dev_apbuart *)CONFIG_DEBUG_UART_BASE; - uart->scaler = (((CONFIG_DEBUG_UART_CLOCK*10) / (CONFIG_BAUDRATE*8)) - 5)/10; + uart->scaler = apbuart_calc_scaler(CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); uart->ctrl = APBUART_CTRL_RE | APBUART_CTRL_TE; } diff --git a/arch/sparc/cpu/leon3/start.S b/arch/sparc/cpu/leon3/start.S index 2031149..1527d72 100644 --- a/arch/sparc/cpu/leon3/start.S +++ b/arch/sparc/cpu/leon3/start.S @@ -1,6 +1,7 @@ /* This is where the SPARC/LEON3 starts - * Copyright (C) 2007, - * Daniel Hellstrom, daniel@gaisler.com + * + * Copyright (C) 2007, 2015 + * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com * * SPDX-License-Identifier: GPL-2.0+ */ @@ -12,7 +13,6 @@ #include <asm/psr.h> #include <asm/stack.h> #include <asm/leon.h> -#include <version.h> #include <ambapp.h> /* Default Plug&Play I/O area */ @@ -20,6 +20,11 @@ #define CONFIG_AMBAPP_IOAREA AMBA_DEFAULT_IOAREA #endif +/* Default number of SPARC register windows */ +#ifndef CONFIG_SYS_SPARC_NWINDOWS +#define CONFIG_SYS_SPARC_NWINDOWS 8 +#endif + /* Entry for traps which jump to a programmer-specified trap handler. */ #define TRAPR(H) \ wr %g0, 0xfe0, %psr; \ @@ -203,15 +208,6 @@ _trap_table: SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f4-f7 SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f8-fb SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! fc-ff -/* - * Version string - */ - - .data - .extern leon3_snooping_avail - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" .section ".text" .extern _nomem_amba_init, _nomem_memory_ctrl_init @@ -261,11 +257,18 @@ wiminit: set WIM_INIT, %g3 mov %g3, %wim -stackp: +stackinit: set CONFIG_SYS_INIT_SP_OFFSET, %fp andn %fp, 0x0f, %fp sub %fp, 64, %sp +tbrinit: + set CONFIG_SYS_TEXT_BASE, %g2 + wr %g0, %g2, %tbr + nop + nop + nop + /* Obtain the address of _GLOBAL_OFFSET_TABLE_ */ SPARC_PIC_THUNK_CALL(l7) @@ -302,25 +305,50 @@ cpu_init_unreloc: call cpu_init_f nop -/* un relocated start address of monitor */ -#define TEXT_START _text +board_init_unreloc: + call board_init_f + clr %o0 ! boot_flags -/* un relocated end address of monitor */ -#define DATA_END __init_end +dead_unreloc: + mov 1, %g1 ! For GRMON2 to exit normally. + ta 0 ! If board_init_f call returns.. (unlikely) + nop + nop + ba dead_unreloc ! infinte loop + nop + +!------------------------------------------------------------------------------- +/* void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM after + * relocating the monitor code. + * + * %o0 = Relocated stack pointer + * %o1 = Relocated global data pointer + * %o2 = Relocated text pointer + * + * %l7 = _GLOBAL_OFFSET_TABLE_ address + */ + .globl relocate_code + .type relocate_code, #function + .align 4 +relocate_code: + !SPARC_PIC_THUNK_CALL(l7) reloc: - SPARC_LOAD_ADDRESS(TEXT_START, l7, g2) - SPARC_LOAD_ADDRESS(DATA_END, l7, g3) - set CONFIG_SYS_RELOC_MONITOR_BASE,%g4 -reloc_loop: - ldd [%g2],%l0 - ldd [%g2+8],%l2 - std %l0,[%g4] - std %l2,[%g4+8] - inc 16,%g2 - subcc %g3,%g2,%g0 - bne reloc_loop - inc 16,%g4 + SPARC_LOAD_ADDRESS(_text, l7, g2) ! start address of monitor + SPARC_LOAD_ADDRESS(__init_end, l7, g3) ! end address of monitor + mov %o2, %g4 ! relocation address + sub %g4, %g2, %g6 ! relocation offset + /* copy .text & .data to relocated address */ +10: ldd [%g2], %l0 + ldd [%g2+8], %l2 + std %l0, [%g4] + std %l2, [%g4+8] + inc 16, %g2 ! src += 16 + cmp %g2, %g3 + bcs 10b ! while (src < end) + inc 16, %g4 ! dst += 16 clr %l0 clr %l1 @@ -335,106 +363,97 @@ reloc_loop: * */ + /* clear the relocated .bss area */ clr_bss: -/* clear bss area (the relocated) */ SPARC_LOAD_ADDRESS(__bss_start, l7, g2) SPARC_LOAD_ADDRESS(__bss_end, l7, g3) - sub %g3,%g2,%g3 + sub %g3,%g2,%g3 ! length of .bss area add %g3,%g4,%g3 + /* clearing 16byte a time ==> linker script need to align to 16 byte offset */ clr %g1 /* std %g0 uses g0 and g1 */ -/* clearing 16byte a time ==> linker script need to align to 16 byte offset */ -clr_bss_16: - std %g0,[%g4] - std %g0,[%g4+8] - inc 16,%g4 - cmp %g3,%g4 - bne clr_bss_16 +20: + std %g0, [%g4] + std %g0, [%g4+8] + inc 16, %g4 ! ptr += 16 + cmp %g4, %g3 + bcs 20b ! while (ptr < end) nop -/* add offsets to GOT table */ + /* add offsets to GOT table */ fixup_got: SPARC_LOAD_ADDRESS(__got_start, l7, g4) + add %g4, %g6, %g4 SPARC_LOAD_ADDRESS(__got_end, l7, g3) -/* - * new got offset = (old GOT-PTR (read with ld) - - * CONFIG_SYS_RELOC_MONITOR_BASE(from define) ) + - * Destination Address (from define) - */ - set CONFIG_SYS_RELOC_MONITOR_BASE,%g2 - SPARC_LOAD_ADDRESS(TEXT_START, l7, g1) - add %g4,%g2,%g4 - sub %g4,%g1,%g4 - add %g3,%g2,%g3 - sub %g3,%g1,%g3 - sub %g2,%g1,%g2 ! prepare register with (new base address) - - ! (old base address) -got_loop: - ld [%g4],%l0 ! load old GOT-PTR - add %l0,%g2,%l0 ! increase with (new base address) - - ! (old base) - st %l0,[%g4] - inc 4,%g4 - cmp %g3,%g4 - bne got_loop + add %g3, %g6, %g3 +30: ld [%g4], %l0 +#ifdef CONFIG_RELOC_GOT_SKIP_NULL + cmp %l0, 0 + be 32f +#endif + add %l0, %g6, %l0 ! relocate GOT pointer + st %l0, [%g4] +32: inc 4, %g4 ! ptr += 4 + cmp %g4, %g3 + bcs 30b ! while (ptr < end) nop prom_relocate: SPARC_LOAD_ADDRESS(__prom_start, l7, g2) SPARC_LOAD_ADDRESS(__prom_end, l7, g3) - set CONFIG_SYS_PROM_OFFSET, %g4 - -prom_relocate_loop: - ldd [%g2],%l0 - ldd [%g2+8],%l2 - std %l0,[%g4] - std %l2,[%g4+8] - inc 16,%g2 - subcc %g3,%g2,%g0 - bne prom_relocate_loop - inc 16,%g4 + /* + * Calculated addres is stored in this variable by + * reserve_prom() function in common/board_f.c + */ + SPARC_LOAD_ADDRESS(__prom_start_reloc, l7, g4) + ld [%g4], %g4 + +40: ldd [%g2], %l0 + ldd [%g2+8], %l2 + std %l0, [%g4] + std %l2, [%g4+8] + inc 16, %g2 + cmp %g2, %g3 + bcs 40b + inc 16, %g4 + +! %o0 = stack pointer (relocated) +! %o1 = global data pointer (relocated) +! %o2 = text pointer (relocated) + +! %g6 = relocation offset +! %l7 = _GLOBAL_OFFSET_TABLE_ /* Trap table has been moved, lets tell CPU about * the new trap table address */ - - set CONFIG_SYS_RELOC_MONITOR_BASE, %g2 - wr %g0, %g2, %tbr +update_trap_table_address: + wr %g0, %o2, %tbr nop nop nop -/* If CACHE snooping is available in hardware the - * variable leon3_snooping_avail will be set to - * 0x800000 else 0. - */ -snoop_detect: - sethi %hi(0x00800000), %o0 - lda [%g0] 2, %o1 - and %o0, %o1, %o0 - sethi %hi(leon3_snooping_avail+CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE), %o1 - st %o0, [%lo(leon3_snooping_avail+CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE)+%o1] - -/* call relocate*/ - nop -/* Call relocated init functions */ -jump: - SPARC_LOAD_ADDRESS(cpu_init_f2, l7, o1) - set CONFIG_SYS_RELOC_MONITOR_BASE,%o2 - add %o1,%o2,%o1 - sub %o1,%g1,%o1 - call %o1 - clr %o0 +update_stack_pointers: + mov %o0, %fp + andn %fp, 0x0f, %fp ! align to 16 bytes + add %fp, -64, %fp ! make space for a window push + mov %fp, %sp ! setup stack pointer + +jump_board_init_r: + mov %o1, %o0 ! relocated global data pointer + mov %o2, %o1 ! relocated text pointer + SPARC_LOAD_ADDRESS(board_init_r, l7, o3) + add %o3, %g6, %o3 ! add relocation offset + call %o3 + nop - SPARC_LOAD_ADDRESS(board_init_f, l7, o1) - set CONFIG_SYS_RELOC_MONITOR_BASE,%o2 - SPARC_LOAD_ADDRESS(TEXT_START, l7, g1) - add %o1,%o2,%o1 - sub %o1,%g1,%o1 - call %o1 - clr %o0 +dead: + mov 1, %g1 ! For GRMON2 to exit normally. + ta 0 ! if call returns.. (unlikely) + nop + b dead ! infinte loop + nop -dead: ta 0 ! if call returns... - nop +!------------------------------------------------------------------------------ /* Interrupt handler caller, * reg L7: interrupt number @@ -463,54 +482,56 @@ _irq_entry: RESTORE_ALL -!Window overflow trap handler. +!------------------------------------------------------------------------------ + +/* + * Window overflow trap handler + */ .global _window_overflow _window_overflow: mov %wim, %l3 ! Calculate next WIM - mov %g1, %l7 - srl %l3, 1, %g1 - sll %l3, (CONFIG_SYS_SPARC_NWINDOWS-1) , %l4 - or %l4, %g1, %g1 - + mov %g1, %l7 + srl %l3, 1, %g1 + sll %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l4 + or %g1, %l4, %g1 save ! Get into window to be saved. - mov %g1, %wim - nop; - nop; - nop - st %l0, [%sp + 0]; - st %l1, [%sp + 4]; - st %l2, [%sp + 8]; - st %l3, [%sp + 12]; - st %l4, [%sp + 16]; - st %l5, [%sp + 20]; - st %l6, [%sp + 24]; - st %l7, [%sp + 28]; - st %i0, [%sp + 32]; - st %i1, [%sp + 36]; - st %i2, [%sp + 40]; - st %i3, [%sp + 44]; - st %i4, [%sp + 48]; - st %i5, [%sp + 52]; - st %i6, [%sp + 56]; - st %i7, [%sp + 60]; + mov %g1, %wim + nop; nop; nop + st %l0, [%sp + 0] ! Save window to the stack + st %l1, [%sp + 4] + st %l2, [%sp + 8] + st %l3, [%sp + 12] + st %l4, [%sp + 16] + st %l5, [%sp + 20] + st %l6, [%sp + 24] + st %l7, [%sp + 28] + st %i0, [%sp + 32] + st %i1, [%sp + 36] + st %i2, [%sp + 40] + st %i3, [%sp + 44] + st %i4, [%sp + 48] + st %i5, [%sp + 52] + st %i6, [%sp + 56] + st %i7, [%sp + 60] restore ! Go back to trap window. - mov %l7, %g1 + mov %l7, %g1 jmp %l1 ! Re-execute save. - rett %l2 - -/* Window underflow trap handler. */ + rett %l2 +/* + * Window underflow trap handler + */ .global _window_underflow _window_underflow: - mov %wim, %l3 ! Calculate next WIM - sll %l3, 1, %l4 - srl %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l5 - or %l5, %l4, %l5 - mov %l5, %wim + mov %wim, %l3 ! Calculate next WIM + srl %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l5 + sll %l3, 1, %l4 + or %l5, %l4, %l5 + mov %l5, %wim nop; nop; nop restore ! Two restores to get into the restore ! window to restore @@ -533,9 +554,9 @@ _window_underflow: save ! Get back to the trap window. save jmp %l1 ! Re-execute restore. - rett %l2 + rett %l2 - retl +!------------------------------------------------------------------------------ _nmi_trap: nop diff --git a/arch/sparc/cpu/leon3/usb_uhci.c b/arch/sparc/cpu/leon3/usb_uhci.c index 1be84c6..242b83f 100644 --- a/arch/sparc/cpu/leon3/usb_uhci.c +++ b/arch/sparc/cpu/leon3/usb_uhci.c @@ -85,10 +85,11 @@ #include <usb.h> #include "usb_uhci.h" +DECLARE_GLOBAL_DATA_PTR; + #define USB_MAX_TEMP_TD 128 /* number of temporary TDs for bulk and control transfers */ #define USB_MAX_TEMP_INT_TD 32 /* number of temporary TDs for Interrupt transfers */ -extern int leon3_snooping_avail; /* #define out16r(address,data) (*(unsigned short *)(address) = \ (unsigned short)( \ @@ -573,7 +574,7 @@ void usb_check_skel(void) if (qh_cntrl.dev_ptr != 0) { /* it's a device assigned check if this caused IRQ */ dev = (struct usb_device *)qh_cntrl.dev_ptr; /* Flush cache now that hardware updated DATA and TDs/QHs */ - if (!leon3_snooping_avail) + if (!gd->arch.snooping_avail) sparc_dcache_flush_all(); usb_get_td_status(&tmp_td[0], dev); /* update status */ if (!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */ @@ -584,7 +585,7 @@ void usb_check_skel(void) if (qh_bulk.dev_ptr != 0) { /* it's a device assigned check if this caused IRQ */ dev = (struct usb_device *)qh_bulk.dev_ptr; /* Flush cache now that hardware updated DATA and TDs/QHs */ - if (!leon3_snooping_avail) + if (!gd->arch.snooping_avail) sparc_dcache_flush_all(); usb_get_td_status(&tmp_td[0], dev); /* update status */ if (!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */ diff --git a/arch/sparc/include/asm/config.h b/arch/sparc/include/asm/config.h index fd0b551..455fbc1 100644 --- a/arch/sparc/include/asm/config.h +++ b/arch/sparc/include/asm/config.h @@ -1,5 +1,6 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2015, + * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,9 +8,14 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_SYS_GENERIC_GLOBAL_DATA #define CONFIG_NEEDS_MANUAL_RELOC #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH +#define CONFIG_SYS_TIMER_RATE 1000000 /* 1MHz */ +#define CONFIG_SYS_TIMER_COUNTER gd->arch.timer +#define CONFIG_SYS_TIMER_COUNTS_DOWN + #endif diff --git a/arch/sparc/include/asm/global_data.h b/arch/sparc/include/asm/global_data.h index 0680a56..af38d17 100644 --- a/arch/sparc/include/asm/global_data.h +++ b/arch/sparc/include/asm/global_data.h @@ -2,8 +2,8 @@ * (C) Copyright 2002-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. + * (C) Copyright 2007, 2015 + * Daniel Hellstrom, Cobham, Gaisler, daniel@gaisler.com. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,7 +15,12 @@ /* Architecture-specific global data */ struct arch_global_data { + void *timer; void *uart; + unsigned int uart_freq; +#ifdef CONFIG_LEON3 + unsigned int snooping_available; +#endif }; #include <asm-generic/global_data.h> diff --git a/arch/sparc/include/asm/irq.h b/arch/sparc/include/asm/irq.h index 2faf7a0..5d0f756 100644 --- a/arch/sparc/include/asm/irq.h +++ b/arch/sparc/include/asm/irq.h @@ -32,4 +32,7 @@ extern int intLock(void); /* Sets the PIL to oldLevel */ extern void intUnlock(int oldLevel); +/* Return non-zero if interrupts are currently enabled */ +extern int interrupt_is_enabled(void); + #endif diff --git a/arch/sparc/include/asm/leon3.h b/arch/sparc/include/asm/leon3.h index 6ee1ea8..a9f32b9 100644 --- a/arch/sparc/include/asm/leon3.h +++ b/arch/sparc/include/asm/leon3.h @@ -19,4 +19,17 @@ * ctrl, memory controllers etc. */ + +#ifndef __ASSEMBLER__ +/* The frequency of the CPU */ +extern unsigned int leon_cpu_freq; + +/* Number of LEON processors in system */ +extern int leon_cpu_cnt; + +/* Ver/subversion of CPU */ +extern int leon_ver; + +#endif /* __ASSEMBLER__ */ + #endif diff --git a/arch/sparc/include/asm/u-boot.h b/arch/sparc/include/asm/u-boot.h index 5f12e58..9b9a71d 100644 --- a/arch/sparc/include/asm/u-boot.h +++ b/arch/sparc/include/asm/u-boot.h @@ -2,49 +2,23 @@ * (C) Copyright 2000 - 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2007, From asm-ppc/u-boot.h - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. + * (C) Copyright 2007, 2015 + * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com. * * SPDX-License-Identifier: GPL-2.0+ - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** */ #ifndef __U_BOOT_H__ #define __U_BOOT_H__ -/* - * Currently, this Board information is not passed to +/* Currently, this board information is not passed to * Linux kernel from U-Boot, but may be passed to other * Operating systems. This is because U-boot emulates * a SUN PROM loader (from Linux point of view). - * - * include/asm-sparc/u-boot.h */ - -#ifndef __ASSEMBLY__ - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ - unsigned long bi_intfreq; /* Internal Freq, in MHz */ - unsigned long bi_busfreq; /* Bus Freq, in MHz */ -} bd_t; - -#endif /* __ASSEMBLY__ */ +#include <asm-generic/u-boot.h> /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_SPARC -#endif /* __U_BOOT_H__ */ +#endif diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile index e69b9ba..6b7ad6d 100644 --- a/arch/sparc/lib/Makefile +++ b/arch/sparc/lib/Makefile @@ -1,9 +1,9 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2015 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # SPDX-License-Identifier: GPL-2.0+ # -obj-y = board.o cache.o interrupts.o time.o +obj-y = cache.o interrupts.o obj-$(CONFIG_CMD_BOOTM) += bootm.o diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c deleted file mode 100644 index 10475d1..0000000 --- a/arch/sparc/lib/board.c +++ /dev/null @@ -1,398 +0,0 @@ -/* SPARC Board initialization - * - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <console.h> -#include <malloc.h> -#include <stdio_dev.h> -#include <config.h> -#if defined(CONFIG_CMD_IDE) -#include <ide.h> -#endif -#ifdef CONFIG_STATUS_LED -#include <status_led.h> -#endif -#include <net.h> -#include <serial.h> -#include <version.h> -#if defined(CONFIG_POST) -#include <post.h> -#endif -#ifdef CONFIG_PS2KBD -#include <keyboard.h> -#endif -#ifdef CONFIG_CMD_AMBAPP -#include <ambapp.h> -#endif - -#ifdef CONFIG_BITBANGMII -#include <miiphy.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* Debug options -#define DEBUG_INIT_SEQUENCE -#define DEBUG_MEM_LAYOUT -#define DEBUG_COMMANDS -*/ - -extern void timer_interrupt_init(void); -extern int do_ambapp_print(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]); -extern int prom_init(void); - -#if defined(CONFIG__CMD_DOC) -void doc_init(void); -#endif - -#if !defined(CONFIG_SYS_NO_FLASH) -static char *failed = "*** failed ***\n"; -#endif - -#include <environment.h> - -ulong monitor_flash_len; - -/************************************************************************ - * Init Utilities * - ************************************************************************ - * Some of this code should be moved into the core functions, - * but let's get it working (again) first... - */ - -static int init_baudrate(void) -{ - gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); - return 0; -} - -/***********************************************************************/ - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ -typedef int (init_fnc_t) (void); - -#define WATCHDOG_RESET(x) - -/************************************************************************ - * Initialization sequence * - ************************************************************************ - */ - -init_fnc_t *init_sequence[] = { - -#if defined(CONFIG_BOARD_EARLY_INIT_F) - board_early_init_f, -#endif - serial_init, - - init_timebase, - -#if defined(CONFIG_CMD_AMBAPP) - ambapp_init_reloc, -#endif - - env_init, - - init_baudrate, - - console_init_f, - display_options, - - checkcpu, - checkboard, -#if defined(CONFIG_MISC_INIT_F) - misc_init_f, -#endif - -#ifdef CONFIG_POST - post_init_f, -#endif - - NULL, /* Terminate this list, - * beware: this list will be relocated - * which means that NULL will become - * NULL+RELOC_OFFSET. We simply make - * NULL be -RELOC_OFFSET instead. - */ -}; - -/************************************************************************ - * - * This is the SPARC board initialization routine, running from RAM. - * - ************************************************************************ - */ -#ifdef DEBUG_INIT_SEQUENCE -char *str_init_seq = "INIT_SEQ 00\n"; -char *str_init_seq_done = "\n\rInit sequence done...\r\n\r\n"; -#endif - -void board_init_f(ulong bootflag) -{ - bd_t *bd; - init_fnc_t **init_fnc_ptr; - int j; - -#ifndef CONFIG_SYS_NO_FLASH - ulong flash_size; -#endif - - gd = (gd_t *) (CONFIG_SYS_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset((void *)gd, 0, sizeof(gd_t)); - - gd->bd = (bd_t *) (gd + 1); /* At end of global data */ - gd->baudrate = CONFIG_BAUDRATE; - gd->cpu_clk = CONFIG_SYS_CLK_FREQ; - - bd = gd->bd; - bd->bi_memstart = CONFIG_SYS_RAM_BASE; - bd->bi_memsize = CONFIG_SYS_RAM_SIZE; - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; -#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE) - bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; - bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; -#endif - bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ - - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - gd->reloc_off = CONFIG_SYS_RELOC_MONITOR_BASE - CONFIG_SYS_MONITOR_BASE; - - for (init_fnc_ptr = init_sequence, j = 0; *init_fnc_ptr; - ++init_fnc_ptr, j++) { -#ifdef DEBUG_INIT_SEQUENCE - if (j > 9) - str_init_seq[9] = '0' + (j / 10); - str_init_seq[10] = '0' + (j - (j / 10) * 10); - serial_puts(str_init_seq); -#endif - if ((*init_fnc_ptr + gd->reloc_off) () != 0) { - hang(); - } - } -#ifdef DEBUG_INIT_SEQUENCE - serial_puts(str_init_seq_done); -#endif - - /* - * Now that we have DRAM mapped and working, we can - * relocate the code and continue running from DRAM. - * - * Reserve memory at end of RAM for (top down in that order): - * - kernel log buffer - * - protected RAM - * - LCD framebuffer - * - monitor code - * - board info struct - */ -#ifdef DEBUG_MEM_LAYOUT - printf("CONFIG_SYS_MONITOR_BASE: 0x%lx\n", CONFIG_SYS_MONITOR_BASE); - printf("CONFIG_ENV_ADDR: 0x%lx\n", CONFIG_ENV_ADDR); - printf("CONFIG_SYS_RELOC_MONITOR_BASE: 0x%lx (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE, - CONFIG_SYS_MONITOR_LEN); - printf("CONFIG_SYS_MALLOC_BASE: 0x%lx (%d)\n", CONFIG_SYS_MALLOC_BASE, - CONFIG_SYS_MALLOC_LEN); - printf("CONFIG_SYS_INIT_SP_OFFSET: 0x%lx (%d)\n", CONFIG_SYS_INIT_SP_OFFSET, - CONFIG_SYS_STACK_SIZE); - printf("CONFIG_SYS_PROM_OFFSET: 0x%lx (%d)\n", CONFIG_SYS_PROM_OFFSET, - CONFIG_SYS_PROM_SIZE); - printf("CONFIG_SYS_GBL_DATA_OFFSET: 0x%lx (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET, - GENERATED_GBL_DATA_SIZE); -#endif - -#ifdef CONFIG_POST - post_bootmode_init(); - post_run(NULL, POST_ROM | post_bootmode_get(0)); -#endif - -#if defined(CONFIG_NEEDS_MANUAL_RELOC) - /* - * We have to relocate the command table manually - */ - fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd), - ll_entry_count(cmd_tbl_t, cmd)); -#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ - -#if defined(CONFIG_CMD_AMBAPP) && defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP) - puts("AMBA:\n"); - do_ambapp_print(NULL, 0, 0, NULL); -#endif - - /* initialize higher level parts of CPU like time base and timers */ - cpu_init_r(); - - /* start timer */ - timer_interrupt_init(); - - /* - * Enable Interrupts before any calls to udelay, - * the flash driver may use udelay resulting in - * a hang if not timer0 IRQ is enabled. - */ - interrupt_init(); - - /* The Malloc area is immediately below the monitor copy in RAM */ - mem_malloc_init(CONFIG_SYS_MALLOC_BASE, - CONFIG_SYS_MALLOC_END - CONFIG_SYS_MALLOC_BASE); - -#if !defined(CONFIG_SYS_NO_FLASH) - puts("Flash: "); - - if ((flash_size = flash_init()) > 0) { -# ifdef CONFIG_SYS_FLASH_CHECKSUM - print_size(flash_size, ""); - /* - * Compute and print flash CRC if flashchecksum is set to 'y' - * - * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX - */ - if (getenv_yesno("flashchecksum") == 1) { - printf(" CRC: %08lX", - crc32(0, (const unsigned char *)CONFIG_SYS_FLASH_BASE, - flash_size) - ); - } - putc('\n'); -# else /* !CONFIG_SYS_FLASH_CHECKSUM */ - print_size(flash_size, "\n"); -# endif /* CONFIG_SYS_FLASH_CHECKSUM */ - } else { - puts(failed); - hang(); - } - - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; /* update start of FLASH memory */ - bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */ -#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE - bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */ -#else - bd->bi_flashoffset = 0; -#endif -#else /* CONFIG_SYS_NO_FLASH */ - bd->bi_flashsize = 0; - bd->bi_flashstart = 0; - bd->bi_flashoffset = 0; -#endif /* !CONFIG_SYS_NO_FLASH */ - -#ifdef CONFIG_SPI -# if !defined(CONFIG_ENV_IS_IN_EEPROM) - spi_init_f(); -# endif - spi_init_r(); -#endif - - /* relocate environment function pointers etc. */ - env_relocate(); - -#if defined(CONFIG_BOARD_LATE_INIT) - board_late_init(); -#endif - -#ifdef CONFIG_ID_EEPROM - mac_read_from_eeprom(); -#endif - -#if defined(CONFIG_PCI) - /* - * Do pci configuration - */ - pci_init(); -#endif - - /* Initialize stdio devices */ - stdio_init(); - - /* Initialize the jump table for applications */ - jumptable_init(); - - /* Initialize the console (after the relocation and devices init) */ - console_init_r(); - -#ifdef CONFIG_STATUS_LED - status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); -#endif - - udelay(20); - - /* Initialize from environment */ - load_addr = getenv_ulong("loadaddr", 16, load_addr); - - WATCHDOG_RESET(); - -#if defined(CONFIG_CMD_DOC) - WATCHDOG_RESET(); - puts("DOC: "); - doc_init(); -#endif - -#ifdef CONFIG_BITBANGMII - bb_miiphy_init(); -#endif -#if defined(CONFIG_CMD_NET) - WATCHDOG_RESET(); - puts("Net: "); - eth_initialize(); -#endif - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) - WATCHDOG_RESET(); - debug("Reset Ethernet PHY\n"); - reset_phy(); -#endif - -#ifdef CONFIG_POST - post_run(NULL, POST_RAM | post_bootmode_get(0)); -#endif - -#if defined(CONFIG_CMD_IDE) - WATCHDOG_RESET(); - puts("IDE: "); - ide_init(); -#endif /* CONFIG_CMD_IDE */ - -#ifdef CONFIG_LAST_STAGE_INIT - WATCHDOG_RESET(); - /* - * Some parts can be only initialized if all others (like - * Interrupts) are up and running (i.e. the PC-style ISA - * keyboard). - */ - last_stage_init(); -#endif - -#ifdef CONFIG_PS2KBD - puts("PS/2: "); - kbd_init(); -#endif - prom_init(); - - /* main_loop */ - for (;;) { - WATCHDOG_RESET(); - main_loop(); - } - -} - -/************************************************************************/ diff --git a/arch/sparc/lib/bootm.c b/arch/sparc/lib/bootm.c index 9e2b784..927a351 100644 --- a/arch/sparc/lib/bootm.c +++ b/arch/sparc/lib/bootm.c @@ -19,10 +19,6 @@ extern image_header_t header; extern void srmmu_init_cpu(unsigned int entry); extern void prepare_bootargs(char *bootargs); -#ifdef CONFIG_USB_UHCI -extern int usb_lowlevel_stop(int index); -#endif - /* sparc kernel argument (the ROM vector) */ struct linux_romvec *kernel_arg_promvec; @@ -111,10 +107,6 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t * im linux_hdr->linuxver_minor, linux_hdr->linuxver_revision); #endif -#ifdef CONFIG_USB_UHCI - usb_lowlevel_stop(); -#endif - /* set basic boot params in kernel header now that it has been * extracted and is writeable. */ diff --git a/arch/sparc/lib/interrupts.c b/arch/sparc/lib/interrupts.c index b7c3993..cb73d17 100644 --- a/arch/sparc/lib/interrupts.c +++ b/arch/sparc/lib/interrupts.c @@ -47,6 +47,13 @@ int disable_interrupts(void) return intLock(); } +int interrupt_is_enabled(void) +{ + if (get_pil() == 15) + return 0; + return 1; +} + int interrupt_init(void) { int ret; @@ -59,38 +66,3 @@ int interrupt_init(void) return ret; } - -/* timer interrupt/overflow counter */ -static volatile ulong timestamp = 0; - -/* regs can not be used here! regs is actually the pointer given in - * irq_install_handler - */ -void timer_interrupt(struct pt_regs *regs) -{ - /* call cpu specific function from $(CPU)/interrupts.c */ - timer_interrupt_cpu((void *)regs); - - timestamp++; -} - -ulong get_timer(ulong base) -{ - return (timestamp - base); -} - -void timer_interrupt_init(void) -{ - int irq; - - timestamp = 0; - - irq = timer_interrupt_init_cpu(); - - if (irq < 0) { - /* cpu specific code handled the interrupt registration it self */ - return; - } - /* register interrupt handler for timer */ - irq_install_handler(irq, (void (*)(void *))timer_interrupt, NULL); -} diff --git a/arch/sparc/lib/time.c b/arch/sparc/lib/time.c deleted file mode 100644 index 50a09ad..0000000 --- a/arch/sparc/lib/time.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -/* Implemented by SPARC CPUs */ -extern void cpu_wait_ticks(unsigned long ticks); -extern unsigned long cpu_usec2ticks(unsigned long usec); -extern unsigned long cpu_ticks2usec(unsigned long ticks); - -/* ------------------------------------------------------------------------- */ - -void wait_ticks(unsigned long ticks) -{ - cpu_wait_ticks(ticks); -} - -/* - * This function is intended for SHORT delays only. - */ -unsigned long usec2ticks(unsigned long usec) -{ - return cpu_usec2ticks(usec); -} - -/* ------------------------------------------------------------------------- */ - -/* - * We implement the delay by converting the delay (the number of - * microseconds to wait) into a number of time base ticks; then we - * watch the time base until it has incremented by that amount. - */ -void __udelay(unsigned long usec) -{ - ulong ticks = usec2ticks(usec); - - wait_ticks(ticks); -} - -/* ------------------------------------------------------------------------- */ - -unsigned long ticks2usec(unsigned long ticks) -{ - return cpu_ticks2usec(ticks); -} - -/* ------------------------------------------------------------------------- */ - -int init_timebase(void) -{ - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 14ab98e..7e7cb61 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -93,6 +93,9 @@ config SYS_X86_START16 depends on X86_RESET_VECTOR default 0xfffff800 +config DM_PCI_COMPAT + default y # Until we finish moving over to the new API + config BOARD_ROMSIZE_KB_512 bool config BOARD_ROMSIZE_KB_1024 @@ -279,26 +282,6 @@ config AP_STACK_SIZE the memory used by this initialisation process. Typically 4KB is enough space. -config TSC_CALIBRATION_BYPASS - bool "Bypass Time-Stamp Counter (TSC) calibration" - default n - help - By default U-Boot automatically calibrates Time-Stamp Counter (TSC) - running frequency via Model-Specific Register (MSR) and Programmable - Interval Timer (PIT). If the calibration does not work on your board, - select this option and provide a hardcoded TSC running frequency with - CONFIG_TSC_FREQ_IN_MHZ below. - - Normally this option should be turned on in a simulation environment - like qemu. - -config TSC_FREQ_IN_MHZ - int "Time-Stamp Counter (TSC) running frequency in MHz" - depends on TSC_CALIBRATION_BYPASS - default 1000 - help - The running frequency in MHz of Time-Stamp Counter (TSC). - config HAVE_VGA_BIOS bool "Add a VGA BIOS image" help diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index e797925..2ff2377 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -22,7 +22,6 @@ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ obj-$(CONFIG_SYS_COREBOOT) += coreboot/ obj-$(CONFIG_EFI_APP) += efi/ obj-$(CONFIG_QEMU) += qemu/ -obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index a009c14..9b30451 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -28,9 +28,6 @@ int arch_cpu_init(void) int ret; post_code(POST_CPU_INIT); -#ifdef CONFIG_SYS_X86_TSC_TIMER - timer_set_base(rdtsc()); -#endif ret = x86_cpu_init_f(); if (ret) diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c index 0edee6b..b382795 100644 --- a/arch/x86/cpu/coreboot/timestamp.c +++ b/arch/x86/cpu/coreboot/timestamp.c @@ -27,28 +27,6 @@ static struct timestamp_table *ts_table __attribute__((section(".data"))); void timestamp_init(void) { -#ifdef CONFIG_SYS_X86_TSC_TIMER - uint64_t base_time; -#endif - - ts_table = lib_sysinfo.tstamp_table; -#ifdef CONFIG_SYS_X86_TSC_TIMER - /* - * If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value - * of base_time in coreboot's timestamp table as our timer base, - * otherwise TSC counter value will be used. - * - * Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS, - * the value of base_time in the timestamp table is still zero, so - * we must exclude this case too (this is currently seen on booting - * coreboot in qemu) - */ - if (ts_table && ts_table->base_time) - base_time = ts_table->base_time; - else - base_time = rdtsc(); - timer_set_base(base_time); -#endif timestamp_add_now(TS_U_BOOT_INITTED); } diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 812c5e4..381d835 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -399,6 +399,11 @@ int x86_cpu_init_f(void) } } +#ifdef CONFIG_I8254_TIMER + /* Set up the i8254 timer if required */ + i8254_init(); +#endif + return 0; } @@ -641,24 +646,6 @@ int cpu_jump_to_64bit(ulong setup_base, ulong target) void show_boot_progress(int val) { -#if MIN_PORT80_KCLOCKS_DELAY - /* - * Scale the time counter reading to avoid using 64 bit arithmetics. - * Can't use get_timer() here becuase it could be not yet - * initialized or even implemented. - */ - if (!gd->arch.tsc_prev) { - gd->arch.tsc_base_kclocks = rdtsc() / 1000; - gd->arch.tsc_prev = 0; - } else { - uint32_t now; - - do { - now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; - } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); - gd->arch.tsc_prev = now; - } -#endif outb(val, POST_PORT); } diff --git a/arch/x86/cpu/efi/efi.c b/arch/x86/cpu/efi/efi.c index 75ba0d4..993ab8d 100644 --- a/arch/x86/cpu/efi/efi.c +++ b/arch/x86/cpu/efi/efi.c @@ -10,10 +10,6 @@ int arch_cpu_init(void) { -#ifdef CONFIG_SYS_X86_TSC_TIMER - timer_set_base(rdtsc()); -#endif - return 0; } diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 0e249a4..56abd8f 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -5,44 +5,13 @@ # # SPDX-License-Identifier: GPL-2.0 - -config NORTHBRIDGE_INTEL_SANDYBRIDGE - bool - select CACHE_MRC_BIN - select CPU_INTEL_MODEL_206AX - config NORTHBRIDGE_INTEL_IVYBRIDGE bool select CACHE_MRC_BIN - select CPU_INTEL_MODEL_306AX - -if NORTHBRIDGE_INTEL_SANDYBRIDGE - -config VGA_BIOS_ID - string - default "8086,0106" - -config CACHE_MRC_SIZE_KB - int - default 256 - -config DCACHE_RAM_BASE - hex - default 0xff7f0000 - -config DCACHE_RAM_SIZE - hex - default 0x10000 - -endif if NORTHBRIDGE_INTEL_IVYBRIDGE -config VGA_BIOS_ID - string - default "8086,0166" - -config EXTERNAL_MRC_BLOB +config CACHE_MRC_BIN bool default n @@ -58,10 +27,6 @@ config DCACHE_RAM_SIZE hex default 0x20000 -endif - -if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE - config HAVE_MRC bool "Add a System Agent binary" help @@ -80,25 +45,9 @@ config DCACHE_RAM_MRC_VAR_SIZE memory reference code. This should be set to 16KB (0x4000 hex) so that MRC has enough space to run. -config MRC_FILE - string "Intel System Agent path and filename" - depends on HAVE_MRC - default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE - default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE - help - The path and filename of the file to use as System Agent - binary. - config CPU_SPECIFIC_OPTIONS def_bool y select SMM_TSEG - select ARCH_BOOTBLOCK_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SSE2 - select UDELAY_LAPIC - select CPU_MICROCODE_IN_CBFS - select TSC_SYNC_MFENCE select HAVE_INTEL_ME select X86_RAMTEST @@ -124,20 +73,3 @@ config ENABLE_VMX slowly. endif - -config CPU_INTEL_SOCKET_RPGA989 - bool - -if CPU_INTEL_SOCKET_RPGA989 - -config SOCKET_SPECIFIC_OPTIONS # dummy - def_bool y - select MMX - select SSE - select CACHE_AS_RAM - -config CACHE_MRC_BIN - bool - default n - -endif diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 0e6512c..343bfb4 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -118,7 +118,6 @@ static void set_spi_speed(void) int arch_cpu_init(void) { post_code(POST_CPU_INIT); - timer_set_base(rdtsc()); return x86_cpu_init_f(); } @@ -299,16 +298,7 @@ int print_cpuinfo(void) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - debug("Resume from S3 detected.\n"); - boot_mode = PEI_BOOT_RESUME; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); -#else debug("Resume from S3 detected, but disabled.\n"); -#endif } else { /* * TODO: An indication of life might be possible here (e.g. diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 3efd3e8..af5d4a8 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -240,15 +240,6 @@ static void pch_rtc_init(pci_dev_t dev) } debug("rtc_failed = 0x%x\n", rtc_failed); -#if CONFIG_HAVE_ACPI_RESUME - /* Avoid clearing pending interrupts and resetting the RTC control - * register in the resume path because the Linux kernel relies on - * this to know if it should restart the RTC timerqueue if the wake - * was due to the RTC alarm. - */ - if (acpi_get_slp_type() == 3) - return; -#endif /* TODO: Handle power failure */ if (rtc_failed) printf("RTC power failed\n"); diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index e95e60e..e3d8c13 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -169,20 +169,4 @@ void northbridge_init(pci_dev_t dev) void northbridge_enable(pci_dev_t dev) { -#if CONFIG_HAVE_ACPI_RESUME - switch (x86_pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: - debug("Normal boot.\n"); - apci_set_slp_type(0); - break; - case 0xcafed00d: - debug("S3 Resume.\n"); - apci_set_slp_type(3); - break; - default: - debug("Unknown boot method, assuming normal.\n"); - apci_set_slp_type(0); - break; - } -#endif } diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig index fb775d7..4f98621 100644 --- a/arch/x86/cpu/qemu/Kconfig +++ b/arch/x86/cpu/qemu/Kconfig @@ -6,7 +6,6 @@ config QEMU bool - select TSC_CALIBRATION_BYPASS if QEMU diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 84fb082..1f93f72 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -64,9 +64,6 @@ int arch_cpu_init(void) int ret; post_code(POST_CPU_INIT); -#ifdef CONFIG_SYS_X86_TSC_TIMER - timer_set_base(rdtsc()); -#endif ret = x86_cpu_init_f(); if (ret) diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig index bc961ef..163caac 100644 --- a/arch/x86/cpu/quark/Kconfig +++ b/arch/x86/cpu/quark/Kconfig @@ -7,7 +7,6 @@ config INTEL_QUARK bool select HAVE_RMU - select TSC_CALIBRATION_BYPASS if INTEL_QUARK @@ -119,8 +118,4 @@ config SYS_CAR_SIZE Space in bytes in eSRAM used as Cache-As-ARM (CAR). Note this size must not exceed eSRAM's total size. -config TSC_FREQ_IN_MHZ - int - default 400 - endif diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index f737e19..c2bf497 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -233,9 +233,6 @@ int arch_cpu_init(void) int ret; post_code(POST_CPU_INIT); -#ifdef CONFIG_SYS_X86_TSC_TIMER - timer_set_base(rdtsc()); -#endif ret = x86_cpu_init_f(); if (ret) diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 933d189..fb81919 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -52,9 +52,6 @@ int arch_cpu_init(void) int ret; post_code(POST_CPU_INIT); -#ifdef CONFIG_SYS_X86_TSC_TIMER - timer_set_base(rdtsc()); -#endif ret = x86_cpu_init_f(); if (ret) diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index aa86387..d3380de 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -13,6 +13,7 @@ /include/ "keyboard.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "Intel Bayley Bay"; diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts index a6b5d0f..194f0eb 100644 --- a/arch/x86/dts/broadwell_som-6896.dts +++ b/arch/x86/dts/broadwell_som-6896.dts @@ -3,6 +3,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "Advantech SOM-6896"; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 7870bb1..c4469a9 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -4,6 +4,7 @@ /include/ "keyboard.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "Google Link"; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index 61e8f2f..4e2b517 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -3,6 +3,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "Google Panther"; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index eb8421c..84231b3 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -12,6 +12,7 @@ /include/ "serial.dtsi" /include/ "keyboard.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "Intel Crown Bay"; @@ -116,7 +117,7 @@ "pci8086,8811", "pciclass,070002", "pciclass,0700", - "x86-uart"; + "ns16550"; u-boot,dm-pre-reloc; reg = <0x00025100 0x0 0x0 0x0 0x0 0x01025110 0x0 0x0 0x0 0x0>; @@ -130,7 +131,7 @@ "pci8086,8812", "pciclass,070002", "pciclass,0700", - "x86-uart"; + "ns16550"; u-boot,dm-pre-reloc; reg = <0x00025200 0x0 0x0 0x0 0x0 0x01025210 0x0 0x0 0x0 0x0>; @@ -144,7 +145,7 @@ "pci8086,8813", "pciclass,070002", "pciclass,0700", - "x86-uart"; + "ns16550"; u-boot,dm-pre-reloc; reg = <0x00025300 0x0 0x0 0x0 0x0 0x01025310 0x0 0x0 0x0 0x0>; @@ -158,7 +159,7 @@ "pci8086,8814", "pciclass,070002", "pciclass,0700", - "x86-uart"; + "ns16550"; u-boot,dm-pre-reloc; reg = <0x00025400 0x0 0x0 0x0 0x0 0x01025410 0x0 0x0 0x0 0x0>; diff --git a/arch/x86/dts/efi.dts b/arch/x86/dts/efi.dts index 1f50428..6cd8116 100644 --- a/arch/x86/dts/efi.dts +++ b/arch/x86/dts/efi.dts @@ -7,6 +7,7 @@ /dts-v1/; /include/ "skeleton.dtsi" +/include/ "tsc_timer.dtsi" / { model = "EFI"; @@ -16,6 +17,10 @@ stdout-path = &serial; }; + tsc-timer { + clock-frequency = <1000000000>; + }; + serial: serial { compatible = "efi,uart"; }; diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index b49b1f5..55165e1 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -11,6 +11,7 @@ /include/ "skeleton.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "Intel Galileo"; @@ -28,6 +29,10 @@ stdout-path = &pciuart0; }; + tsc-timer { + clock-frequency = <400000000>; + }; + mrc { compatible = "intel,quark-mrc"; flags = <MRC_FLAG_SCRAMBLE_EN>; @@ -65,7 +70,7 @@ "pci8086,0936", "pciclass,070002", "pciclass,0700", - "x86-uart"; + "ns16550"; u-boot,dm-pre-reloc; reg = <0x0000a500 0x0 0x0 0x0 0x0 0x0200a510 0x0 0x0 0x0 0x0>; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index b03f987..bbfd6d4 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -12,6 +12,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "Intel Minnowboard Max"; diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 8da7e52..8a06229 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -12,6 +12,7 @@ /include/ "serial.dtsi" /include/ "keyboard.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "QEMU x86 (I440FX)"; @@ -44,6 +45,10 @@ }; }; + tsc-timer { + clock-frequency = <1000000000>; + }; + pci { compatible = "pci-x86"; #address-cells = <3>; diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index df30c89..0b685c8 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -22,6 +22,7 @@ /include/ "serial.dtsi" /include/ "keyboard.dtsi" /include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" / { model = "QEMU x86 (Q35)"; @@ -55,6 +56,10 @@ }; }; + tsc-timer { + clock-frequency = <1000000000>; + }; + pci { compatible = "pci-x86"; #address-cells = <3>; diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi index 6865eed..54c3faf 100644 --- a/arch/x86/dts/serial.dtsi +++ b/arch/x86/dts/serial.dtsi @@ -1,6 +1,6 @@ / { serial: serial { - compatible = "x86-uart"; + compatible = "ns16550"; reg = <0x3f8 8>; reg-shift = <0>; clock-frequency = <1843200>; diff --git a/arch/x86/dts/tsc_timer.dtsi b/arch/x86/dts/tsc_timer.dtsi new file mode 100644 index 0000000..4f5021d --- /dev/null +++ b/arch/x86/dts/tsc_timer.dtsi @@ -0,0 +1,6 @@ +/ { + tsc-timer { + compatible = "x86,tsc-timer"; + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 35148ab..0ca518c 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -54,9 +54,6 @@ struct arch_global_data { uint8_t x86_mask; uint32_t x86_device; uint64_t tsc_base; /* Initial value returned by rdtsc() */ - uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */ - uint32_t tsc_prev; /* For show_boot_progress() */ - uint32_t tsc_mhz; /* TSC frequency in MHz */ void *new_fdt; /* Relocated FDT */ uint32_t bist; /* Built-in self test value */ enum pei_boot_mode_t pei_boot_mode; diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index d676e2c..cd5ecb6 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -34,7 +34,6 @@ obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o obj-y += string.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o obj-y += tables.o -obj-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_CMD_ZBOOT) += zimage.o obj-$(CONFIG_HAVE_FSP) += fsp/ diff --git a/board/altera/arria5-socdk/socfpga.c b/board/altera/arria5-socdk/socfpga.c index a1dbc49..97fb902 100644 --- a/board/altera/arria5-socdk/socfpga.c +++ b/board/altera/arria5-socdk/socfpga.c @@ -3,83 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> -#include <asm/arch/reset_manager.h> -#include <asm/io.h> - -#include <usb.h> -#include <usb/s3c_udc.h> -#include <usb_mass_storage.h> - -#include <micrel.h> -#include <netdev.h> -#include <phy.h> - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -/* - * PHY configuration - */ -#ifdef CONFIG_PHY_MICREL_KSZ9021 -int board_phy_config(struct phy_device *phydev) -{ - int ret; - /* - * These skew settings for the KSZ9021 ethernet phy is required for ethernet - * to work reliably on most flavors of cyclone5 boards. - */ - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, - 0xf0f0); - if (ret) - return ret; - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} -#endif - -#ifdef CONFIG_USB_GADGET -struct s3c_plat_otg_data socfpga_otg_data = { - .regs_otg = CONFIG_USB_DWC2_REG_ADDR, - .usb_gusbcfg = 0x1417, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - return s3c_udc_probe(&socfpga_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - return 1; -} -#endif diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 33cf1fd..f1e6d2b 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -9,19 +9,19 @@ const u8 sys_mgr_init_table[] = { 3, /* EMACIO0 */ - 3, /* EMACIO1 */ - 3, /* EMACIO2 */ - 3, /* EMACIO3 */ - 3, /* EMACIO4 */ - 3, /* EMACIO5 */ - 3, /* EMACIO6 */ - 3, /* EMACIO7 */ - 3, /* EMACIO8 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ 3, /* EMACIO9 */ - 3, /* EMACIO10 */ - 3, /* EMACIO11 */ - 3, /* EMACIO12 */ - 3, /* EMACIO13 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ 0, /* EMACIO14 */ 0, /* EMACIO15 */ 0, /* EMACIO16 */ @@ -55,8 +55,8 @@ const u8 sys_mgr_init_table[] = { 0, /* GENERALIO12 */ 2, /* GENERALIO13 */ 2, /* GENERALIO14 */ - 0, /* GENERALIO15 */ - 0, /* GENERALIO16 */ + 3, /* GENERALIO15 */ + 3, /* GENERALIO16 */ 2, /* GENERALIO17 */ 2, /* GENERALIO18 */ 0, /* GENERALIO19 */ @@ -72,27 +72,27 @@ const u8 sys_mgr_init_table[] = { 0, /* GENERALIO29 */ 0, /* GENERALIO30 */ 0, /* GENERALIO31 */ - 0, /* MIXED1IO0 */ - 1, /* MIXED1IO1 */ - 1, /* MIXED1IO2 */ - 1, /* MIXED1IO3 */ - 1, /* MIXED1IO4 */ - 0, /* MIXED1IO5 */ - 0, /* MIXED1IO6 */ - 0, /* MIXED1IO7 */ - 1, /* MIXED1IO8 */ - 1, /* MIXED1IO9 */ - 1, /* MIXED1IO10 */ - 1, /* MIXED1IO11 */ - 0, /* MIXED1IO12 */ - 0, /* MIXED1IO13 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ 0, /* MIXED1IO14 */ - 1, /* MIXED1IO15 */ - 1, /* MIXED1IO16 */ - 1, /* MIXED1IO17 */ - 1, /* MIXED1IO18 */ - 0, /* MIXED1IO19 */ - 0, /* MIXED1IO20 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ 0, /* MIXED1IO21 */ 0, /* MIXED2IO0 */ 0, /* MIXED2IO1 */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 3d621ed..4abd2e0 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -14,7 +14,7 @@ #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 @@ -31,7 +31,7 @@ #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 diff --git a/board/altera/cyclone5-socdk/socfpga.c b/board/altera/cyclone5-socdk/socfpga.c index a1dbc49..97fb902 100644 --- a/board/altera/cyclone5-socdk/socfpga.c +++ b/board/altera/cyclone5-socdk/socfpga.c @@ -3,83 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> -#include <asm/arch/reset_manager.h> -#include <asm/io.h> - -#include <usb.h> -#include <usb/s3c_udc.h> -#include <usb_mass_storage.h> - -#include <micrel.h> -#include <netdev.h> -#include <phy.h> - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -/* - * PHY configuration - */ -#ifdef CONFIG_PHY_MICREL_KSZ9021 -int board_phy_config(struct phy_device *phydev) -{ - int ret; - /* - * These skew settings for the KSZ9021 ethernet phy is required for ethernet - * to work reliably on most flavors of cyclone5 boards. - */ - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, - 0xf0f0); - if (ret) - return ret; - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} -#endif - -#ifdef CONFIG_USB_GADGET -struct s3c_plat_otg_data socfpga_otg_data = { - .regs_otg = CONFIG_USB_DWC2_REG_ADDR, - .usb_gusbcfg = 0x1417, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - return s3c_udc_probe(&socfpga_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - return 1; -} -#endif diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile index a35db40..b4391a7 100644 --- a/board/armltd/vexpress64/Makefile +++ b/board/armltd/vexpress64/Makefile @@ -5,4 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := vexpress64.o pcie.o +obj-y := vexpress64.o +obj-$(CONFIG_TARGET_VEXPRESS64_JUNO) += pcie.o diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index 7b999e8..b3fb09c 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -87,7 +87,7 @@ void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH); writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM); - printf("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n", + debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n", src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr, ((u64)1) << window_size, trsl_param); } @@ -191,7 +191,5 @@ void xr3pci_init(void) void vexpress64_pcie_init(void) { -#ifdef CONFIG_TARGET_VEXPRESS64_JUNO xr3pci_init(); -#endif } diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index f4e8084..6efc8c1 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -28,6 +28,13 @@ U_BOOT_DEVICE(vexpress_serials) = { .platdata = &serial_platdata, }; +/* This function gets replaced by platforms supporting PCIe. + * The replacement function, eg. on Juno, initialises the PCIe bus. + */ +__weak void vexpress64_pcie_init(void) +{ +} + int board_init(void) { vexpress64_pcie_init(); @@ -44,8 +51,10 @@ void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +#ifdef PHYS_SDRAM_2 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +#endif } /* diff --git a/board/atmel/sama5d2_xplained/Kconfig b/board/atmel/sama5d2_xplained/Kconfig new file mode 100644 index 0000000..55712e9 --- /dev/null +++ b/board/atmel/sama5d2_xplained/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D2_XPLAINED + +config SYS_BOARD + default "sama5d2_xplained" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d2_xplained" + +endif diff --git a/board/atmel/sama5d2_xplained/MAINTAINERS b/board/atmel/sama5d2_xplained/MAINTAINERS new file mode 100644 index 0000000..ff9c86f --- /dev/null +++ b/board/atmel/sama5d2_xplained/MAINTAINERS @@ -0,0 +1,7 @@ +SAMA5D2 XPLAINED BOARD +M: Wenyou Yang <wenyou.yang@atmel.com> +S: Maintained +F: board/atmel/sama5d2_xplained/ +F: include/configs/sama5d2_xplained.h +F: configs/sama5d2_xplained_mmc_defconfig +F: configs/sama5d2_xplained_spiflash_defconfig diff --git a/board/atmel/sama5d2_xplained/Makefile b/board/atmel/sama5d2_xplained/Makefile new file mode 100644 index 0000000..420870b --- /dev/null +++ b/board/atmel/sama5d2_xplained/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2015 Atmel Corporation +# Wenyou Yang <wenyou.yang@atmel.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d2_xplained.o diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c new file mode 100644 index 0000000..0b3397f --- /dev/null +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -0,0 +1,283 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <atmel_hlcdc.h> +#include <lcd.h> +#include <mmc.h> +#include <net.h> +#include <netdev.h> +#include <spi.h> +#include <version.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_usba_udc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); +} + +static void board_spi0_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0); + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0); + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0); + + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); + + at91_periph_clk_enable(ATMEL_ID_SPI0); +} + +static void board_usb_hw_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1); +} + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 480, + .vl_row = 272, + .vl_clk = 9000000, + .vl_bpix = LCD_BPP, + .vl_tft = 1, + .vl_hsync_len = 41, + .vl_left_margin = 2, + .vl_right_margin = 2, + .vl_vsync_len = 11, + .vl_upper_margin = 2, + .vl_lower_margin = 2, + .mmio = ATMEL_BASE_LCDC, +}; + +/* No power up/down pin for the LCD pannel */ +void lcd_enable(void) { /* Empty! */ } +void lcd_disable(void) { /* Empty! */ } + +unsigned int has_lcdc(void) +{ + return 1; +} + +static void board_lcd_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 0, 0); /* LCDPCK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 1, 0); /* LCDDEN */ + + /* LCDDAT0 */ + /* LCDDAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */ + + /* LCDDAT8 */ + /* LCDDAT9 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */ + + /* LCDD16 */ + /* LCDD17 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */ + + at91_periph_clk_enable(ATMEL_ID_LCDC); +} + +#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{ + ulong dram_size; + int i; + char temp[32]; + + lcd_printf("%s\n", U_BOOT_VERSION); + lcd_printf("2015 ATMEL Corp\n"); + lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + + lcd_printf("%ld MB SDRAM\n", dram_size >> 20); +} +#endif /* CONFIG_LCD_INFO */ +#endif /* CONFIG_LCD */ + +static void board_gmac_hw_init(void) +{ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */ + + at91_periph_clk_enable(ATMEL_ID_GMAC); +} + +static void board_sdhci0_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SDMMC0_CK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SDMMC0_CMD */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SDMMC0_DAT0 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* SDMMC0_DAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* SDMMC0_DAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* SDMMC0_DAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 6, 0); /* SDMMC0_DAT4 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 7, 0); /* SDMMC0_DAT5 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 8, 0); /* SDMMC0_DAT6 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0); /* SDMMC0_DAT7 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0); /* SDMMC0_RSTN */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SDMMC0_VDDSEL */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC0); + at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0, + GCK_CSS_PLLA_CLK, 1); +} + +static void board_sdhci1_hw_init(void) +{ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 18, 0); /* SDMMC1_DAT0 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 19, 0); /* SDMMC1_DAT1 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 20, 0); /* SDMMC1_DAT2 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 21, 0); /* SDMMC1_DAT3 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 22, 0); /* SDMMC1_CK */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 27, 0); /* SDMMC1_RSTN */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 28, 0); /* SDMMC1_CMD */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 30, 0); /* SDMMC1_CD */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC1); + at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1, + GCK_CSS_PLLA_CLK, 1); +} + +int board_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_ATMEL_SDHCI0 + atmel_sdhci_init((void *)ATMEL_BASE_SDMMC0, ATMEL_ID_SDMMC0); +#endif +#ifdef CONFIG_ATMEL_SDHCI1 + atmel_sdhci_init((void *)ATMEL_BASE_SDMMC1, ATMEL_ID_SDMMC1); +#endif + + return 0; +} + +static void board_uart1_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */ + + at91_periph_clk_enable(ATMEL_ID_UART1); +} + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + + board_uart1_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_ATMEL_SPI + board_spi0_hw_init(); +#endif +#ifdef CONFIG_ATMEL_SDHCI +#ifdef CONFIG_ATMEL_SDHCI0 + board_sdhci0_hw_init(); +#endif +#ifdef CONFIG_ATMEL_SDHCI1 + board_sdhci1_hw_init(); +#endif +#endif +#ifdef CONFIG_MACB + board_gmac_hw_init(); +#endif +#ifdef CONFIG_LCD + board_lcd_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + board_usb_hw_init(); +#endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); +#endif + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + usba_udc_probe(&pdata); +#ifdef CONFIG_USB_ETH_RNDIS + usb_eth_initialize(bis); +#endif +#endif + + return rc; +} diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c index 20eb191..b3a4a41 100644 --- a/board/broadcom/bcm28155_ap/bcm28155_ap.c +++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c @@ -13,7 +13,7 @@ #include <asm/arch/sysmap.h> #include <usb.h> -#include <usb/s3c_udc.h> +#include <usb/dwc2_udc.h> #include <g_dnl.h> #define SECWATCHDOG_SDOGCR_OFFSET 0x00000000 @@ -95,14 +95,14 @@ int board_mmc_init(bd_t *bis) #endif #ifdef CONFIG_USB_GADGET -static struct s3c_plat_otg_data bcm_otg_data = { +static struct dwc2_plat_otg_data bcm_otg_data = { .regs_otg = HSOTG_BASE_ADDR }; int board_usb_init(int index, enum usb_init_type init) { - debug("%s: performing s3c_udc_probe\n", __func__); - return s3c_udc_probe(&bcm_otg_data); + debug("%s: performing dwc2_udc_probe\n", __func__); + return dwc2_udc_probe(&bcm_otg_data); } int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) diff --git a/board/corscience/tricorder/tricorder-eeprom.c b/board/corscience/tricorder/tricorder-eeprom.c index 1c74a0f..340a009 100644 --- a/board/corscience/tricorder/tricorder-eeprom.c +++ b/board/corscience/tricorder/tricorder-eeprom.c @@ -77,17 +77,13 @@ static int handle_eeprom_v1(struct tricorder_eeprom *eeprom) int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom) { -#ifdef CONFIG_SYS_EEPROM_BUS_NUM unsigned int bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); -#endif memset(eeprom, 0, TRICORDER_EEPROM_SIZE); i2c_read(addr, 0, 2, (unsigned char *)eeprom, TRICORDER_EEPROM_SIZE); -#ifdef CONFIG_SYS_EEPROM_BUS_NUM i2c_set_bus_num(bus); -#endif if (be32_to_cpu(eeprom->magic) != TRICORDER_EEPROM_MAGIC) { warn_wrong_value("magic", TRICORDER_EEPROM_MAGIC, @@ -138,9 +134,6 @@ int tricorder_eeprom_write(unsigned devaddr, const char *name, int ret; unsigned char *p; int i; -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - unsigned int bus; -#endif memset(eeprom, 0, TRICORDER_EEPROM_SIZE); memset(eeprom_verify, 0, TRICORDER_EEPROM_SIZE); @@ -172,33 +165,23 @@ int tricorder_eeprom_write(unsigned devaddr, const char *name, print_buffer(0, &eeprom, 1, sizeof(eeprom), 16); #endif -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); -#endif + eeprom_init(CONFIG_SYS_EEPROM_BUS_NUM); - /* do page write to the eeprom */ - for (i = 0, p = (unsigned char *)&eeprom; - i < sizeof(eeprom); - i += 32, p += 32) { - ret = i2c_write(devaddr, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - p, min(sizeof(eeprom) - i, 32)); - if (ret) - break; - udelay(5000); /* 5ms write cycle timing */ - } + ret = eeprom_write(devaddr, 0, (unsigned char *)&eeprom, + TRICORDER_EEPROM_SIZE); + if (ret) + printf("Tricorder: Could not write EEPROM content!\n"); - ret = i2c_read(devaddr, 0, 2, (unsigned char *)&eeprom_verify, + ret = eeprom_read(devaddr, 0, (unsigned char *)&eeprom_verify, TRICORDER_EEPROM_SIZE); + if (ret) + printf("Tricorder: Could not read EEPROM content!\n"); if (memcmp(&eeprom, &eeprom_verify, sizeof(eeprom)) != 0) { printf("Tricorder: Could not verify EEPROM content!\n"); ret = 1; } -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - i2c_set_bus_num(bus); -#endif return ret; } @@ -206,7 +189,7 @@ int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc == 3) { ulong dev_addr = simple_strtoul(argv[2], NULL, 16); - eeprom_init(); + if (strcmp(argv[1], "read") == 0) { int rcode; @@ -220,7 +203,6 @@ int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *version = argv[4]; char *serial = argv[5]; char *interface = NULL; - eeprom_init(); if (argc == 7) interface = argv[6]; diff --git a/board/denx/mcvevk/socfpga.c b/board/denx/mcvevk/socfpga.c index 1a23a7d..6be58f0 100644 --- a/board/denx/mcvevk/socfpga.c +++ b/board/denx/mcvevk/socfpga.c @@ -3,43 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> -#include <asm/arch/reset_manager.h> -#include <asm/io.h> - -#include <usb.h> -#include <usb/s3c_udc.h> -#include <usb_mass_storage.h> - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -#ifdef CONFIG_USB_GADGET -struct s3c_plat_otg_data socfpga_otg_data = { - .regs_otg = CONFIG_USB_DWC2_REG_ADDR, - .usb_gusbcfg = 0x1417, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - return s3c_udc_probe(&socfpga_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - return 1; -} -#endif diff --git a/board/ebv/socrates/MAINTAINERS b/board/ebv/socrates/MAINTAINERS new file mode 100644 index 0000000..e48236f --- /dev/null +++ b/board/ebv/socrates/MAINTAINERS @@ -0,0 +1,6 @@ +SOCRATES BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/ebv/socrates/ +F: include/configs/socfpga_socrates.h +F: configs/socfpga_socrates_defconfig diff --git a/board/ebv/socrates/Makefile b/board/ebv/socrates/Makefile new file mode 100644 index 0000000..86f9b78 --- /dev/null +++ b/board/ebv/socrates/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga.o diff --git a/board/ebv/socrates/qts/iocsr_config.h b/board/ebv/socrates/qts/iocsr_config.h new file mode 100644 index 0000000..f1bbe68 --- /dev/null +++ b/board/ebv/socrates/qts/iocsr_config.h @@ -0,0 +1,660 @@ +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00004824, + 0x01209000, + 0x82400000, + 0x00018004, + 0x00000000, + 0x00004000, + 0x00002412, + 0x00904800, + 0x41200000, + 0x80000002, + 0x00000904, + 0x00002000, + 0x00001209, + 0x00482400, + 0x20900000, + 0x40000001, + 0x00000482, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00009048, + 0x02412000, + 0x048000C0, + 0x00000009, + 0x00002412, + 0x00008000, + 0x00004824, + 0x01209000, + 0x82400000, + 0x00000004, + 0x00001209, + 0x00004000, + 0x00002412, + 0x00904800, + 0x41200000, + 0x80000002, + 0x00000904, + 0x00002000, + 0x06001209, + 0x00482400, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x80001000, + 0x00000904, + 0x00241200, + 0x90480000, + 0x20003000, + 0x00000241, + 0x00000800, + 0x00000000, + 0x00000000, + 0x48240000, + 0x90000000, + 0x00000120, + 0x00000400, + 0x00000000, + 0x00090480, + 0x00000003, + 0x00000000, + 0x00000000, + 0x90000200, + 0x00600120, + 0x00000000, + 0x12090000, + 0x24000600, + 0x00000048, + 0x48000100, + 0x00300090, + 0xC0024120, + 0x09048000, + 0x12000300, + 0x000C0024, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x30009048, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C002412, + 0x00008000, + 0x18004824, + 0x00000000, + 0x82400000, + 0x00018004, + 0x06001209, + 0x00004000, + 0x20002412, + 0x00904800, + 0x00000030, + 0x80000000, + 0x03000904, + 0x00002000, + 0x10001209, + 0x00482400, + 0x20900000, + 0x40010001, + 0x00000482, + 0x80001000, + 0x00000904, + 0x00000000, + 0x90480000, + 0x20008000, + 0x00C00241, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0CC20D80, + 0x0C3000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x20430000, + 0x0C003001, + 0x00C00481, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x90218000, + 0x86001800, + 0x00600240, + 0x80090218, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x4810C000, + 0x43000C00, + 0x00300120, + 0xC004810C, + 0x12043000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680A28, + 0x45034030, + 0x12481A01, + 0x80A280D0, + 0x34030C06, + 0x01A01450, + 0x280D0000, + 0x30C0680A, + 0x02490340, + 0xD000001A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x18000000, + 0x01800902, + 0x00240860, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x20430000, + 0x0C003001, + 0x00C00481, + 0x00000FF0, + 0x4810C000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x90218000, + 0x86001800, + 0x00600240, + 0x80090218, + 0x24086001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x4810C000, + 0x43000C00, + 0x00300120, + 0xC004810C, + 0x12043000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680A28, + 0x49034030, + 0x12481A02, + 0x80A280D0, + 0x34030C06, + 0x01A00040, + 0x280D0002, + 0x30C0680A, + 0x02490340, + 0xD00A281A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x18000000, + 0x01800902, + 0x00240860, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x2043090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x18864000, + 0x49247A06, + 0xF228A3D5, + 0xF6D1451E, + 0x0342E388, + 0x821A0000, + 0x0000D000, + 0x05140680, + 0xD949247A, + 0x1EF228A3, + 0x88F6D145, + 0x000352E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x86120800, + 0x00600240, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x18864000, + 0x49247A06, + 0xF3CF23D5, + 0xF4D1451E, + 0x034A9248, + 0x821A038E, + 0x0000D000, + 0x00000680, + 0xD949247A, + 0x1EF3CF23, + 0x88F4D145, + 0x000352E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x2043090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x18864000, + 0x49247A06, + 0xF228A3D9, + 0xF4D1451E, + 0x034A9248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD949247A, + 0x1EF228A3, + 0x88F4D145, + 0x000352E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x08864000, + 0x49247A02, + 0xF3CF23D9, + 0xF4D1451E, + 0x0342E388, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD949247A, + 0x1EF3CF23, + 0x88F4DE79, + 0x000342A2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/ebv/socrates/qts/pinmux_config.h b/board/ebv/socrates/qts/pinmux_config.h new file mode 100644 index 0000000..4bb654f --- /dev/null +++ b/board/ebv/socrates/qts/pinmux_config.h @@ -0,0 +1,219 @@ +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 3, /* GENERALIO9 */ + 3, /* GENERALIO10 */ + 3, /* GENERALIO11 */ + 3, /* GENERALIO12 */ + 2, /* GENERALIO13 */ + 2, /* GENERALIO14 */ + 1, /* GENERALIO15 */ + 1, /* GENERALIO16 */ + 1, /* GENERALIO17 */ + 1, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/ebv/socrates/qts/pll_config.h b/board/ebv/socrates/qts/pll_config.h new file mode 100644 index 0000000..c5aea9d --- /dev/null +++ b/board/ebv/socrates/qts/pll_config.h @@ -0,0 +1,85 @@ +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 +#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 50000000 +#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 +#define CONFIG_HPS_CLK_QSPI_HZ 400000000 +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 +#define CONFIG_HPS_CLK_CAN0_HZ 100000000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/ebv/socrates/qts/sdram_config.h b/board/ebv/socrates/qts/sdram_config.h new file mode 100644 index 0000000..cf9d1d3 --- /dev/null +++ b/board/ebv/socrates/qts/sdram_config.h @@ -0,0 +1,341 @@ +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 7 +#define CALIB_VFIFO_OFFSET 5 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 375 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 82 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 82 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080221, + 0x10080320, + 0x10090044, + 0x100a0008, + 0x100b0000, + 0x10380400, + 0x10080241, + 0x100802c0, + 0x100a0024, + 0x10090010, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/ebv/socrates/socfpga.c b/board/ebv/socrates/socfpga.c new file mode 100644 index 0000000..97fb902 --- /dev/null +++ b/board/ebv/socrates/socfpga.c @@ -0,0 +1,6 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> diff --git a/board/evb_rk3036/evb_rk3036/Kconfig b/board/evb_rk3036/evb_rk3036/Kconfig new file mode 100644 index 0000000..ae2a9eb --- /dev/null +++ b/board/evb_rk3036/evb_rk3036/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3036 + +config SYS_BOARD + default "evb_rk3036" + +config SYS_VENDOR + default "evb_rk3036" + +config SYS_CONFIG_NAME + default "evb_rk3036" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/evb_rk3036/evb_rk3036/MAINTAINERS b/board/evb_rk3036/evb_rk3036/MAINTAINERS new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/board/evb_rk3036/evb_rk3036/MAINTAINERS diff --git a/board/evb_rk3036/evb_rk3036/Makefile b/board/evb_rk3036/evb_rk3036/Makefile new file mode 100644 index 0000000..0403836 --- /dev/null +++ b/board/evb_rk3036/evb_rk3036/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb_rk3036.o diff --git a/board/evb_rk3036/evb_rk3036/evb_rk3036.c b/board/evb_rk3036/evb_rk3036/evb_rk3036.c new file mode 100644 index 0000000..f5758b1 --- /dev/null +++ b/board/evb_rk3036/evb_rk3036/evb_rk3036.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/uart.h> +#include <asm/arch/sdram_rk3036.h> + +DECLARE_GLOBAL_DATA_PTR; + +void get_ddr_config(struct rk3036_ddr_config *config) +{ + /* K4B4G1646Q config */ + config->ddr_type = 3; + config->rank = 2; + config->cs0_row = 15; + config->cs1_row = 15; + + /* 8bank */ + config->bank = 3; + config->col = 10; + + /* 16bit bw */ + config->bw = 1; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = sdram_size(); + + return 0; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c index 26cf517..b5025ab 100644 --- a/board/freescale/common/fman.c +++ b/board/freescale/common/fman.c @@ -52,6 +52,8 @@ int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, if (!ph) return -FDT_ERR_BADPHANDLE; + ph = cpu_to_fdt32(ph); + offset = fdt_node_offset_by_compat_reg(fdt, compat, addr); if (offset < 0) return offset; diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 73b6718..b510c71 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -15,7 +15,7 @@ #include <u-boot/rsa-mod-exp.h> #include <hash.h> #include <fsl_secboot_err.h> -#ifndef CONFIG_MPC85xx +#ifdef CONFIG_LS102XA #include <asm/arch/immap_ls102xa.h> #endif @@ -99,7 +99,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); - if (memcmp((u8 *)csf_hdr_addr, barker_code, ESBC_BARKER_LEN)) + if (memcmp((u8 *)(uintptr_t)csf_hdr_addr, + barker_code, ESBC_BARKER_LEN)) return -1; *csf_addr = csf_hdr_addr; @@ -117,7 +118,7 @@ static int get_ie_info_addr(u32 *ie_addr) if (get_csf_base_addr(&csf_addr, &flash_base_addr)) return -1; - hdr = (struct fsl_secboot_img_hdr *)csf_addr; + hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr; /* For SoC's with Trust Architecture v1 with corenet bus * the sg table field in CSF header has absolute address @@ -130,7 +131,7 @@ static int get_ie_info_addr(u32 *ie_addr) (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else - sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr + + sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr + (u32)hdr->psgtable); #endif @@ -379,8 +380,8 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img) #ifdef CONFIG_KEY_REVOCATION if (check_srk(img)) { ret = algo->hash_update(algo, ctx, - (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off), - img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1); + (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off), + img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1); srk = 1; } #endif @@ -438,8 +439,8 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) #ifdef CONFIG_KEY_REVOCATION if (check_srk(img)) { ret = algo->hash_update(algo, ctx, - (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off), - img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0); + (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off), + img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0); key_hash = 1; } #endif @@ -454,8 +455,13 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) return ret; /* Update hash for actual Image */ +#ifdef CONFIG_ESBC_ADDR_64BIT ret = algo->hash_update(algo, ctx, - (u8 *)img->hdr.pimg, img->hdr.img_size, 1); + (u8 *)(uintptr_t)img->hdr.pimg64, img->hdr.img_size, 1); +#else + ret = algo->hash_update(algo, ctx, + (u8 *)(uintptr_t)img->hdr.pimg, img->hdr.img_size, 1); +#endif if (ret) return ret; @@ -533,7 +539,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) { char buf[20]; struct fsl_secboot_img_hdr *hdr = &img->hdr; - void *esbc = (u8 *)img->ehdrloc; + void *esbc = (u8 *)(uintptr_t)img->ehdrloc; u8 *k, *s; #ifdef CONFIG_KEY_REVOCATION u32 ret; @@ -549,7 +555,11 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) return ERROR_ESBC_CLIENT_HEADER_BARKER; +#ifdef CONFIG_ESBC_ADDR_64BIT + sprintf(buf, "%llx", hdr->pimg64); +#else sprintf(buf, "%x", hdr->pimg); +#endif setenv("img_addr", buf); if (!hdr->img_size) @@ -594,7 +604,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) if (!key_found && check_ie(img)) { if (get_ie_info_addr(&img->ie_addr)) return ERROR_IE_TABLE_NOT_FOUND; - ie_info = (struct ie_key_info *)img->ie_addr; + ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; if (ie_info->num_keys == 0 || ie_info->num_keys > 32) return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; @@ -748,7 +758,7 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, hdr = &img->hdr; img->ehdrloc = addr; - esbc = (u8 *)img->ehdrloc; + esbc = (u8 *)(uintptr_t)img->ehdrloc; memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr)); diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 6b8af14..f1bed51 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -7,7 +7,12 @@ #include <common.h> #include <command.h> #include <i2c.h> +#include <asm/io.h> +#ifdef CONFIG_LS1043A +#include <asm/arch/immap_lsch2.h> +#else #include <asm/immap_85xx.h> +#endif #include "vid.h" DECLARE_GLOBAL_DATA_PTR; @@ -240,7 +245,11 @@ static int set_voltage_to_IR(int i2caddress, int vdd) * SoC before converting into an IR VID value */ vdd += board_vdd_drop_compensation(); +#ifdef CONFIG_LS1043A + vid = DIV_ROUND_UP(vdd - 265, 5); +#else vid = DIV_ROUND_UP(vdd - 245, 5); +#endif ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET, 1, (void *)&vid, sizeof(vid)); @@ -276,8 +285,12 @@ static int set_voltage(int i2caddress, int vdd) int adjust_vdd(ulong vdd_override) { int re_enable = disable_interrupts(); +#ifdef CONFIG_LS1043A + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#else ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif u32 fusesr; u8 vid; int vdd_target, vdd_current, vdd_last; @@ -352,12 +365,21 @@ int adjust_vdd(ulong vdd_override) * | T | | | | | * ------------------------------------------------------ */ +#ifdef CONFIG_LS1043A + vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; + if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { + vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & + FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; + } +#else vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) { vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & FSL_CORENET_DCFG_FUSESR_VID_MASK; } +#endif vdd_target = vdd[vid]; /* check override variable for overriding VDD */ diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d889ad5..be3358a 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -11,6 +11,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> +#include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_devdis.h> #include <asm/arch/ls102xa_sata.h> #include <hwconfig.h> @@ -140,17 +141,6 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -unsigned int get_soc_major_rev(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int svr, major; - - svr = in_be32(&gur->svr); - major = SVR_MAJ(svr); - - return major; -} - int select_i2c_ch_pca9547(u8 ch) { int ret; @@ -193,8 +183,6 @@ int board_mmc_init(bd_t *bis) int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major; #ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -205,40 +193,7 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif -#ifdef CONFIG_FSL_QSPI - out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); -#endif - -#ifdef CONFIG_FSL_DCU_FB - out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); -#endif - - /* Configure Little endian for SAI, ASRC and SPDIF */ - out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); - - /* - * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) - */ - out_le32(&cci->slave[4].snoop_ctrl, - CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override - * Register All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - - /* Workaround for the issue that DDR could not respond to - * barrier transaction which is generated by executing DSB/ISB - * instruction. Set CCI-400 control override register to - * terminate the barrier transaction. After DDR is initialized, - * allow barrier transaction to DDR again */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); - } + arch_soc_init(); #if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 4918c11..8eaff5f 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -12,6 +12,7 @@ #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> #include <asm/arch/ls102xa_devdis.h> +#include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_sata.h> #include <hwconfig.h> #include <mmc.h> @@ -138,17 +139,6 @@ int checkboard(void) return 0; } -unsigned int get_soc_major_rev(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int svr, major; - - svr = in_be32(&gur->svr); - major = SVR_MAJ(svr); - - return major; -} - void ddrmc_init(void) { struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; @@ -394,8 +384,6 @@ conflict: int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major; #ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -407,33 +395,7 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif -#ifdef CONFIG_FSL_DCU_FB - out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); -#endif - -#ifdef CONFIG_FSL_QSPI - out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); -#endif - - /* Configure Little endian for SAI, ASRC and SPDIF */ - out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); - - /* - * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) - */ - out_le32(&cci->slave[4].snoop_ctrl, - CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override - * Register All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - } + arch_soc_init(); #if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) { diff --git a/board/freescale/ls1043aqds/Kconfig b/board/freescale/ls1043aqds/Kconfig new file mode 100644 index 0000000..7e27f8f --- /dev/null +++ b/board/freescale/ls1043aqds/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1043AQDS + +config SYS_BOARD + default "ls1043aqds" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1043aqds" + +endif diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS new file mode 100644 index 0000000..0c7f648 --- /dev/null +++ b/board/freescale/ls1043aqds/MAINTAINERS @@ -0,0 +1,9 @@ +LS1043AQDS BOARD +M: Mingkai Hu <Mingkai.Hu@freescale.com> +S: Maintained +F: board/freescale/ls1043aqds/ +F: include/configs/ls1043aqds.h +F: configs/ls1043aqds_defconfig +F: configs/ls1043aqds_nor_ddr3_defconfig +F: configs/ls1043aqds_nand_defconfig +F: configs/ls1043aqds_sdcard_ifc_defconfig diff --git a/board/freescale/ls1043aqds/Makefile b/board/freescale/ls1043aqds/Makefile new file mode 100644 index 0000000..f727bfd --- /dev/null +++ b/board/freescale/ls1043aqds/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ddr.o +obj-y += eth.o +obj-y += ls1043aqds.o diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README new file mode 100644 index 0000000..6261a77 --- /dev/null +++ b/board/freescale/ls1043aqds/README @@ -0,0 +1,96 @@ +Overview +-------- +The LS1043A Development System (QDS) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1043A +LayerScape Architecture processor. The LS1043AQDS provides SW development +platform for the Freescale LS1043A processor series, with a complete +debugging environment. + +LS1043A SoC Overview +-------------------- +The LS1043A integrated multicore processor combines four ARM Cortex-A53 +processor cores with datapath acceleration optimized for L2/3 packet +processing, single pass security offload and robust traffic management +and quality of service. + +The LS1043A SoC includes the following function and features: + - Four 64-bit ARM Cortex-A53 CPUs + - 1 MB unified L2 Cache + - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving + support + - Data Path Acceleration Architecture (DPAA) incorporating acceleration the + the following functions: + - Packet parsing, classification, and distribution (FMan) + - Queue management for scheduling, packet sequencing, and congestion + management (QMan) + - Hardware buffer management for buffer allocation and de-allocation (BMan) + - Cryptography acceleration (SEC) + - Ethernet interfaces by FMan + - Up to 1 x XFI supporting 10G interface + - Up to 1 x QSGMII + - Up to 4 x SGMII supporting 1000Mbps + - Up to 2 x SGMII supporting 2500Mbps + - Up to 2 x RGMII supporting 1000Mbps + - High-speed peripheral interfaces + - Three PCIe 2.0 controllers, one supporting x4 operation + - One serial ATA (SATA 3.0) controllers + - Additional peripheral interfaces + - Three high-speed USB 3.0 controllers with integrated PHY + - Enhanced secure digital host controller (eSDXC/eMMC) + - Quad Serial Peripheral Interface (QSPI) Controller + - Serial peripheral interface (SPI) controller + - Four I2C controllers + - Two DUARTs + - Integrated flash controller supporting NAND and NOR flash + - QorIQ platform's trust architecture 2.1 + + LS1043AQDS board Overview + ----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - QSGMII + - SATA 3.0 + - XFI + - DDR Controller + - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s + -IFC/Local Bus + - One in-socket 128 MB NOR flash 16-bit data bus + - One 512 MB NAND flash with ECC support + - PromJet Port + - FPGA connection + - USB 3.0 + - Three high speed USB 3.0 ports + - First USB 3.0 port configured as Host with Type-A connector + - The other two USB 3.0 ports configured as OTG with micro-AB connector + - SDHC port connects directly to an adapter card slot, featuring: + - Optional clock feedback paths, and optional high-speed voltage translation assistance + - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC + - eMMC memory devices + - DSPI: Onboard support for three SPI flash memory devices + - 4 I2C controllers + - One SATA onboard connectors + - UART + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +Start Address End Address Description Size +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB + +Booting Options +--------------- +a) Promjet Boot +b) NOR boot +c) NAND boot +d) SD boot diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c new file mode 100644 index 0000000..42d9068 --- /dev/null +++ b/board/freescale/ls1043aqds/ddr.c @@ -0,0 +1,140 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#ifdef CONFIG_FSL_DEEP_SLEEP +#include <fsl_sleep.h> +#endif +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 3) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->cpo_override = pbsp->cpo_override; + popts->write_data_delay = + pbsp->write_data_delay; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + popts->bstopre = 0; /* enable auto precharge */ + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else + popts->cswl_override = DDR_CSWL_CS0; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + return fsl_ddr_sdram_size(); +#else + puts("Initializing DDR....using SPD\n"); + + dram_size = fsl_ddr_sdram(); +#endif + +#ifdef CONFIG_FSL_DEEP_SLEEP + fsl_dp_ddr_restore(); +#endif + + return dram_size; +} + +void dram_init_banksize(void) +{ + /* + * gd->secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif +} diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h new file mode 100644 index 0000000..8adb660 --- /dev/null +++ b/board/freescale/ls1043aqds/ddr.h @@ -0,0 +1,60 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo_override; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E0A,}, + {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, + {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,}, +#elif defined(CONFIG_SYS_FSL_DDR3) + {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, +#else +#error DDR type not defined +#endif + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +#endif diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c new file mode 100644 index 0000000..b7fc360 --- /dev/null +++ b/board/freescale/ls1043aqds/eth.c @@ -0,0 +1,492 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <netdev.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <fsl_dtsec.h> +#include <malloc.h> +#include <asm/arch/fsl_serdes.h> + +#include "../common/qixis.h" +#include "../common/fman.h" +#include "ls1043aqds_qixis.h" + +#define EMI_NONE 0xFF +#define EMI1_RGMII1 0 +#define EMI1_RGMII2 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT2 3 +#define EMI1_SLOT3 4 +#define EMI1_SLOT4 5 +#define EMI2 6 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { + "LS1043AQDS_MDIO_RGMII1", + "LS1043AQDS_MDIO_RGMII2", + "LS1043AQDS_MDIO_SLOT1", + "LS1043AQDS_MDIO_SLOT2", + "LS1043AQDS_MDIO_SLOT3", + "LS1043AQDS_MDIO_SLOT4", + "NULL", +}; + +/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ +static u8 lane_to_slot[] = {1, 2, 3, 4}; + +static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name; + + if (muxval > EMI2) + return NULL; + + name = ls1043aqds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct ls1043aqds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void ls1043aqds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + + if (muxval < 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct ls1043aqds_mdio *priv = bus->priv; + + ls1043aqds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct ls1043aqds_mdio *priv = bus->priv; + + ls1043aqds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, + regnum, value); +} + +static int ls1043aqds_mdio_reset(struct mii_dev *bus) +{ + struct ls1043aqds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int ls1043aqds_mdio_init(char *realbusname, u8 muxval) +{ + struct ls1043aqds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate ls1043aqds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate ls1043aqds private data\n"); + free(bus); + return -1; + } + + bus->read = ls1043aqds_mdio_read; + bus->write = ls1043aqds_mdio_write; + bus->reset = ls1043aqds_mdio_reset; + sprintf(bus->name, ls1043aqds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + struct fixed_link f_link; + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + if (port == FM1_DTSEC9) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_riser_s1_p1"); + } else if (port == FM1_DTSEC2) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_riser_s2_p1"); + } else if (port == FM1_DTSEC5) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_riser_s3_p1"); + } else if (port == FM1_DTSEC6) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_riser_s4_p1"); + } + } else if (fm_info_get_enet_if(port) == + PHY_INTERFACE_MODE_SGMII_2500) { + /* 2.5G SGMII interface */ + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 1000; + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for 2.5G SGMII */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "sgmii-2500"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { + switch (mdio_mux[port]) { + case EMI1_SLOT1: + switch (port) { + case FM1_DTSEC1: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s1_p1"); + break; + case FM1_DTSEC2: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s1_p2"); + break; + case FM1_DTSEC5: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s1_p3"); + break; + case FM1_DTSEC6: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s1_p4"); + break; + default: + break; + } + break; + case EMI1_SLOT2: + switch (port) { + case FM1_DTSEC1: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s2_p1"); + break; + case FM1_DTSEC2: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s2_p2"); + break; + case FM1_DTSEC5: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s2_p3"); + break; + case FM1_DTSEC6: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s2_p4"); + break; + default: + break; + } + break; + default: + break; + } + fdt_delprop(fdt, offset, "phy-connection-type"); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "qsgmii"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && + port == FM1_10GEC1) { + /* XFI interface */ + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for XFI */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + switch (mdio_mux[i]) { + case EMI1_SLOT1: + fdt_status_okay_by_alias(fdt, "emi1_slot1"); + break; + case EMI1_SLOT2: + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + break; + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + break; + case EMI1_SLOT4: + fdt_status_okay_by_alias(fdt, "emi1_slot4"); + break; + default: + break; + } + break; + case PHY_INTERFACE_MODE_XGMII: + break; + default: + break; + } + } +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + int i, idx, lane, slot, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + + switch (srds_s1) { + case 0x2555: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + break; + case 0x4555: + case 0x4558: + /* QSGMII on lane A, MAC 1/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC1, + QSGMII_CARD_PORT1_PHY_ADDR_S1); + fm_info_set_phy_address(FM1_DTSEC2, + QSGMII_CARD_PORT2_PHY_ADDR_S1); + fm_info_set_phy_address(FM1_DTSEC5, + QSGMII_CARD_PORT3_PHY_ADDR_S1); + fm_info_set_phy_address(FM1_DTSEC6, + QSGMII_CARD_PORT4_PHY_ADDR_S1); + break; + case 0x1355: + /* SGMII on lane B, MAC 2*/ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x2355: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + /* SGMII on lane B, MAC 2*/ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x3335: + /* SGMII on lane C, MAC 5 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + case 0x3355: + case 0x3358: + /* SGMII on lane B, MAC 2 */ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + case 0x3555: + case 0x3558: + /* SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x1455: + /* QSGMII on lane B, MAC 1/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC1, + QSGMII_CARD_PORT1_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC2, + QSGMII_CARD_PORT2_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC5, + QSGMII_CARD_PORT3_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC6, + QSGMII_CARD_PORT4_PHY_ADDR_S2); + break; + case 0x2455: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + /* QSGMII on lane B, MAC 1/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC1, + QSGMII_CARD_PORT1_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC2, + QSGMII_CARD_PORT2_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC5, + QSGMII_CARD_PORT3_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC6, + QSGMII_CARD_PORT4_PHY_ADDR_S2); + break; + case 0x2255: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + /* 2.5G SGMII on lane B, MAC 2 */ + fm_info_set_phy_address(FM1_DTSEC2, 2); + break; + case 0x3333: + /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC9, + SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, + SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, + SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, + SGMII_CARD_PORT1_PHY_ADDR); + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n", + srds_s1); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_QSGMII: + if (interface == PHY_INTERFACE_MODE_SGMII) { + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_2500_FM1_DTSEC1 + idx); + } else { + lane = serdes_get_first_lane(FSL_SRDS_1, + QSGMII_FM1_A); + } + + if (lane < 0) + break; + + slot = lane_to_slot[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + default: + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC3) + mdio_mux[i] = EMI1_RGMII1; + else if (i == FM1_DTSEC4) + mdio_mux[i] = EMI1_RGMII2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c new file mode 100644 index 0000000..d6696ca --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -0,0 +1,333 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <fdt_support.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/fdt.h> +#include <asm/arch/soc.h> +#include <ahci.h> +#include <hwconfig.h> +#include <mmc.h> +#include <scsi.h> +#include <fm_eth.h> +#include <fsl_csu.h> +#include <fsl_esdhc.h> +#include <fsl_ifc.h> +#include <spl.h> + +#include "../common/qixis.h" +#include "ls1043aqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +enum { + MUX_TYPE_GPIO, +}; + +/* LS1043AQDS serdes mux */ +#define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */ +#define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */ +#define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */ +#define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */ +#define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */ +#define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */ +#define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */ +#define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */ + +int checkboard(void) +{ + char buf[64]; +#ifndef CONFIG_SD_BOOT + u8 sw; +#endif + + puts("Board: LS1043AQDS, boot from "); + +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#else + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("PromJet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else if (sw == 0x15) + printf("IFCCard\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif + + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", + QIXIS_READ(id), QIXIS_READ(arch)); + + printf("FPGA: v%d (%s), build %d\n", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + + return 0; +} + +bool if_board_diff_clk(void) +{ + u8 diff_conf = QIXIS_READ(brdcfg[11]); + + return diff_conf & 0x40; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0f) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + if (if_board_diff_clk()) + return get_board_sys_clk(); + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + + return 66666666; +} + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +int dram_init(void) +{ + /* + * When resuming from deep sleep, the I2C channel may not be + * in the default channel. So, switch to the default channel + * before accessing DDR SPD. + */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + gd->ram_size = initdram(0); + + return 0; +} + +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel); +} + +void board_retimer_init(void) +{ + u8 reg; + + /* Retimer is connected to I2C1_CH7_CH5 */ + reg = I2C_MUX_CH7; + i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); + reg = I2C_MUX_CH5; + i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); + + /* Access to Control/Shared register */ + reg = 0x0; + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); + + /* Read device revision and ID */ + i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast. All writes target all channel register sets */ + reg = 0x0c; + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); + + /* Reset Channel Registers */ + i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); + reg |= 0x4; + i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); + + /* Enable override divider select and Enable Override Output Mux */ + i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); + reg |= 0x24; + i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); + + /* Select VCO Divider to full rate (000) */ + i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); + reg &= 0x8f; + i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); + + /* Selects active PFD MUX Input as Re-timed Data (001) */ + i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); + reg &= 0x3f; + reg |= 0x20; + i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x0; + i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); + reg = 0xb2; + i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); + reg = 0x90; + i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); + reg = 0xb3; + i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); + reg = 0xcd; + i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +#ifdef CONFIG_FSL_DEEP_SLEEP +/* determine if it is a warm boot */ +bool is_warm_boot(void) +{ +#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} +#endif + +int config_board_mux(int ctrl_type) +{ + u8 reg14; + + reg14 = QIXIS_READ(brdcfg[14]); + + switch (ctrl_type) { + case MUX_TYPE_GPIO: + reg14 = (reg14 & (~0x30)) | 0x20; + break; + default: + puts("Unsupported mux interface type\n"); + return -1; + } + + QIXIS_WRITE(brdcfg[14], reg14); + + return 0; +} + +int config_serdes_mux(void) +{ + return 0; +} + + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + if (hwconfig("gpio")) + config_board_mux(MUX_TYPE_GPIO); + + return 0; +} +#endif + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *) + CONFIG_SYS_CCI400_ADDR; + + /* Set CCI-400 control override register to enable barrier + * transaction */ + out_le32(&cci->ctrl_ord, + CCI400_CTRLORD_EN_BARRIER); + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + board_retimer_init(); + +#ifdef CONFIG_SYS_FSL_SERDES + config_serdes_mux(); +#endif + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif + return 0; +} +#endif + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} diff --git a/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg b/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg new file mode 100644 index 0000000..f072274 --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg @@ -0,0 +1,14 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Alt base register +09570158 00001000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#flush PBI data +096100c0 000fffff diff --git a/board/freescale/ls1043aqds/ls1043aqds_qixis.h b/board/freescale/ls1043aqds/ls1043aqds_qixis.h new file mode 100644 index 0000000..8783be8 --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_qixis.h @@ -0,0 +1,39 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1043AQDS_QIXIS_H__ +#define __LS1043AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1043AQDS */ + +/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 +#define QIXIS_SYSCLK_64 0x8 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +/* BRDCFG2 - SD clock*/ +#define QIXIS_SDCLK1_100 0x0 +#define QIXIS_SDCLK1_125 0x1 +#define QIXIS_SDCLK1_165 0x2 +#define QIXIS_SDCLK1_100_SP 0x3 + +#endif diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg new file mode 100644 index 0000000..d87058b --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol +08100010 0a000000 00000000 00000000 +14550002 80004012 e0106000 c1002000 +00000000 00000000 00000000 00038800 +00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg new file mode 100644 index 0000000..b6b5e0b --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +# Enable IFC; disable QSPI +08100010 0a000000 00000000 00000000 +14550002 80004012 60040000 c1002000 +00000000 00000000 00000000 00038800 +00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS index efca5bf..84ffb63 100644 --- a/board/freescale/ls1043ardb/MAINTAINERS +++ b/board/freescale/ls1043ardb/MAINTAINERS @@ -7,3 +7,8 @@ F: include/configs/ls1043ardb.h F: configs/ls1043ardb_defconfig F: configs/ls1043ardb_nand_defconfig F: configs/ls1043ardb_sdcard_defconfig + +LS1043A_SECURE_BOOT BOARD +M: Aneesh Bansal <aneesh.bansal@freescale.com> +S: Maintained +F: configs/ls1043ardb_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index b181579..11bc0f2 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -186,6 +186,28 @@ phys_size_t initdram(int board_type) void dram_init_banksize(void) { + /* + * gd->secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[1].start + + gd->secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } } diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 9032ed3..c8f723a 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -18,6 +18,8 @@ #include <fsl_csu.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> +#include <environment.h> +#include <fsl_sec.h> #include "cpld.h" DECLARE_GLOBAL_DATA_PTR; @@ -69,7 +71,23 @@ int dram_init(void) int board_early_init_f(void) { + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; + fsl_lsch2_early_init_f(); + +#ifdef CONFIG_HAS_FSL_XHCI_USB + out_be32(&scfg->rcwpmuxcr0, 0x3333); + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#endif + return 0; } @@ -107,13 +125,37 @@ int config_board_mux(void) int misc_init_r(void) { config_board_mux(); - +#ifdef CONFIG_SECURE_BOOT + /* In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif +#ifdef CONFIG_FSL_CAAM + return sec_init(); +#endif return 0; } #endif int ft_board_setup(void *blob, bd_t *bd) { + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg index 935ffc0..d87058b 100644 --- a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg +++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 01ee0100 # serdes protocol -0810000f 0c000000 00000000 00000000 -14550002 80004012 e0106000 61002000 +08100010 0a000000 00000000 00000000 +14550002 80004012 e0106000 c1002000 00000000 00000000 00000000 00038800 00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg index 28cd958..e2ee34b 100644 --- a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg +++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 01ee0100 # RCW -0810000f 0c000000 00000000 00000000 -14550002 80004012 60040000 61002000 +08100010 0a000000 00000000 00000000 +14550002 80004012 60040000 c1002000 00000000 00000000 00000000 00038800 00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls2085a/Kconfig b/board/freescale/ls2080a/Kconfig index 042f85b..0b938ff 100644 --- a/board/freescale/ls2085a/Kconfig +++ b/board/freescale/ls2080a/Kconfig @@ -1,7 +1,7 @@ -if TARGET_LS2085A_EMU +if TARGET_LS2080A_EMU config SYS_BOARD - default "ls2085a" + default "ls2080a" config SYS_VENDOR default "freescale" @@ -10,14 +10,14 @@ config SYS_SOC default "fsl-layerscape" config SYS_CONFIG_NAME - default "ls2085a_emu" + default "ls2080a_emu" endif -if TARGET_LS2085A_SIMU +if TARGET_LS2080A_SIMU config SYS_BOARD - default "ls2085a" + default "ls2080a" config SYS_VENDOR default "freescale" @@ -26,6 +26,6 @@ config SYS_SOC default "fsl-layerscape" config SYS_CONFIG_NAME - default "ls2085a_simu" + default "ls2080a_simu" endif diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS new file mode 100644 index 0000000..03ca168 --- /dev/null +++ b/board/freescale/ls2080a/MAINTAINERS @@ -0,0 +1,10 @@ +LS2080A BOARD +M: York Sun <yorksun@freescale.com> +S: Maintained +F: board/freescale/ls2080a/ +F: include/configs/ls2080a_emu.h +F: configs/ls2080a_emu_defconfig +F: include/configs/ls2080a_simu.h +F: configs/ls2080a_simu_defconfig +F: configs/ls2085a_emu_defconfig +F: configs/ls2085a_simu_defconfig diff --git a/board/freescale/ls2080a/Makefile b/board/freescale/ls2080a/Makefile new file mode 100644 index 0000000..47c7c74 --- /dev/null +++ b/board/freescale/ls2080a/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2014-15 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls2080a.o +obj-y += ddr.o diff --git a/board/freescale/ls2085a/README b/board/freescale/ls2080a/README index bc1d0bb..7e53f1f 100644 --- a/board/freescale/ls2085a/README +++ b/board/freescale/ls2080a/README @@ -1,4 +1,4 @@ -Freescale ls2085a_emu +Freescale ls2080a_emu This is a emulator target with limited peripherals. diff --git a/board/freescale/ls2085a/ddr.c b/board/freescale/ls2080a/ddr.c index 4884fa2..56c5d96 100644 --- a/board/freescale/ls2085a/ddr.c +++ b/board/freescale/ls2080a/ddr.c @@ -71,7 +71,7 @@ found: pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); - +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num == CONFIG_DP_DDR_CTRL) { /* force DDR bus width to 32 bits */ popts->data_bus_width = 1; @@ -79,6 +79,7 @@ found: popts->burst_length = DDR_BL8; popts->bstopre = 0; /* enable auto precharge */ } +#endif /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed @@ -174,14 +175,29 @@ void dram_init_banksize(void) phys_size_t dp_ddr_size; #endif + /* + * gd->secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[1].start + + gd->secure_ram - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif } else { gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif } #ifdef CONFIG_SYS_DP_DDR_BASE_PHY diff --git a/board/freescale/ls2085a/ddr.h b/board/freescale/ls2080a/ddr.h index 9958a68..9958a68 100644 --- a/board/freescale/ls2085a/ddr.h +++ b/board/freescale/ls2080a/ddr.h diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2080a/ls2080a.c index 27481e2..7bce8b0 100644 --- a/board/freescale/ls2085a/ls2085a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -41,11 +41,13 @@ void detail_board_ddr_info(void) puts("\nDDR "); print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); print_ddr_info(0); +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (gd->bd->bi_dram[2].size) { puts("\nDP-DDR "); print_size(gd->bd->bi_dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } +#endif } int dram_init(void) @@ -66,23 +68,6 @@ int arch_misc_init(void) } #endif -unsigned long get_dram_size_to_hide(void) -{ - unsigned long dram_to_hide = 0; - -/* Carve the Debug Server private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_DEBUG_SERVER - dram_to_hide += debug_server_get_dram_block_size(); -#endif - -/* Carve the MC private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_MC_ENET - dram_to_hide += mc_get_dram_block_size(); -#endif - - return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); -} - int board_eth_init(bd_t *bis) { int error = 0; diff --git a/board/freescale/ls2085aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig index 8d6acba..2f997e9 100644 --- a/board/freescale/ls2085aqds/Kconfig +++ b/board/freescale/ls2080aqds/Kconfig @@ -1,8 +1,8 @@ -if TARGET_LS2085AQDS +if TARGET_LS2080AQDS config SYS_BOARD - default "ls2085aqds" + default "ls2080aqds" config SYS_VENDOR default "freescale" @@ -11,6 +11,6 @@ config SYS_SOC default "fsl-layerscape" config SYS_CONFIG_NAME - default "ls2085aqds" + default "ls2080aqds" endif diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS new file mode 100644 index 0000000..6f99ad0 --- /dev/null +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -0,0 +1,10 @@ +LS2080A BOARD +M: Prabhakar Kushwaha <prabhakar@freescale.com> +S: Maintained +F: board/freescale/ls2080aqds/ +F: board/freescale/ls2080a/ls2080aqds.c +F: include/configs/ls2080aqds.h +F: configs/ls2080aqds_defconfig +F: configs/ls2080aqds_nand_defconfig +F: configs/ls2085aqds_defconfig +F: configs/ls2085aqds_nand_defconfig diff --git a/board/freescale/ls2085aqds/Makefile b/board/freescale/ls2080aqds/Makefile index da69a7d..e0da8a5 100644 --- a/board/freescale/ls2085aqds/Makefile +++ b/board/freescale/ls2080aqds/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ls2085aqds.o +obj-y += ls2080aqds.o obj-y += ddr.o obj-y += eth.o diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2080aqds/README index e4a6f69..375e97c 100644 --- a/board/freescale/ls2085aqds/README +++ b/board/freescale/ls2080aqds/README @@ -1,19 +1,19 @@ Overview -------- -The LS2085A Development System (QDS) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS2085A -Layerscape Architecture processor. The LS2085AQDS provides validation and -SW development platform for the Freescale LS2085A processor series, with +The LS2080A Development System (QDS) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS2080A +Layerscape Architecture processor. The LS2080AQDS provides validation and +SW development platform for the Freescale LS2080A processor series, with a complete debugging environment. -LS2085A SoC Overview +LS2080A SoC Overview ------------------ -The LS2085A integrated multicore processor combines eight ARM Cortex-A57 +The LS2080A integrated multicore processor combines eight ARM Cortex-A57 processor cores with high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. -The LS2085A SoC includes the following function and features: +The LS2080A SoC includes the following function and features: - Eight 64-bit ARM Cortex-A57 CPUs - 1 MB platform cache with ECC @@ -50,7 +50,7 @@ The LS2085A SoC includes the following function and features: - Service processor (SP) provides pre-boot initialization and secure-boot capabilities - LS2085AQDS board Overview + LS2080AQDS board Overview ----------------------- - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 @@ -172,7 +172,7 @@ Supported PHY addresses during SGMII: #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe -Mapping DPMACx to PHY during QSGMII +Mapping DPMACx to PHY during SGMII DPMAC1 -> PHY1-P0 DPMAC2 -> PHY2-P0 DPMAC3 -> PHY3-P0 diff --git a/board/freescale/ls2085aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index 8d71ae1..9fb5e11 100644 --- a/board/freescale/ls2085aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR u8 dq_mapping_0, dq_mapping_2, dq_mapping_3; +#endif const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; int slot; @@ -79,7 +81,7 @@ found: pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); - +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num == CONFIG_DP_DDR_CTRL) { /* force DDR bus width to 32 bits */ popts->data_bus_width = 1; @@ -114,6 +116,7 @@ found: pdimm[slot].dq_mapping[16] = 0; pdimm[slot].dq_mapping[17] = 0; } +#endif /* To work at higher than 1333MT/s */ popts->half_strength_driver_enable = 0; /* @@ -131,10 +134,18 @@ found: popts->zq_en = 1; if (ddr_freq < 2350) { - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | - DDR_CDR2_VREF_RANGE_2; + if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) { + /* four chip-selects */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm); + popts->twot_en = 1; /* enable 2T timing */ + } else { + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | + DDR_CDR2_VREF_RANGE_2; + } } else { popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_100ohm); @@ -164,14 +175,29 @@ void dram_init_banksize(void) phys_size_t dp_ddr_size; #endif + /* + * gd->secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[1].start + + gd->secure_ram - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif } else { gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif } #ifdef CONFIG_SYS_DP_DDR_BASE_PHY diff --git a/board/freescale/ls2085aqds/ddr.h b/board/freescale/ls2080aqds/ddr.h index b76ea61..b76ea61 100644 --- a/board/freescale/ls2085aqds/ddr.h +++ b/board/freescale/ls2080aqds/ddr.h diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2080aqds/eth.c index b8a2bf4..0637ecf 100644 --- a/board/freescale/ls2085aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -18,16 +18,16 @@ #include "../common/qixis.h" -#include "ls2085aqds_qixis.h" +#include "ls2080aqds_qixis.h" #ifdef CONFIG_FSL_MC_ENET - /* - In LS2085A there are only 16 SERDES lanes, spread across 2 SERDES banks. + /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks. * Bank 1 -> Lanes A, B, C, D, E, F, G, H * Bank 2 -> Lanes A,B, C, D, E, F, G, H */ - /* Mapping of 16 SERDES lanes to LS2085A QDS board slots. A value of '0' here + /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here * means that the mapping must be determined dynamically, or that the lane * maps to something other than a board slot. */ @@ -74,16 +74,16 @@ static int sgmii_riser_phy_addr[] = { #define SFP_TX 0 static const char * const mdio_names[] = { - "LS2085A_QDS_MDIO0", - "LS2085A_QDS_MDIO1", - "LS2085A_QDS_MDIO2", - "LS2085A_QDS_MDIO3", - "LS2085A_QDS_MDIO4", - "LS2085A_QDS_MDIO5", + "LS2080A_QDS_MDIO0", + "LS2080A_QDS_MDIO1", + "LS2080A_QDS_MDIO2", + "LS2080A_QDS_MDIO3", + "LS2080A_QDS_MDIO4", + "LS2080A_QDS_MDIO5", DEFAULT_WRIOP_MDIO2_NAME, }; -struct ls2085a_qds_mdio { +struct ls2080a_qds_mdio { u8 muxval; struct mii_dev *realbus; }; @@ -95,7 +95,7 @@ static void sgmii_configure_repeater(int serdes_port) int i, j, ret; int dpmac_id = 0, dpmac, mii_bus = 0; unsigned short value; - char dev[2][20] = {"LS2085A_QDS_MDIO0", "LS2085A_QDS_MDIO3"}; + char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"}; uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60}; uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; @@ -222,7 +222,7 @@ static void qsgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; - const char *dev = "LS2085A_QDS_MDIO0"; + const char *dev = "LS2080A_QDS_MDIO0"; int ret = 0; unsigned short value; @@ -318,7 +318,7 @@ error: return; } -static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval) +static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval) { return mdio_names[muxval]; } @@ -326,7 +326,7 @@ static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval) struct mii_dev *mii_dev_for_muxval(u8 muxval) { struct mii_dev *bus; - const char *name = ls2085a_qds_mdio_name_for_muxval(muxval); + const char *name = ls2080a_qds_mdio_name_for_muxval(muxval); if (!name) { printf("No bus for muxval %x\n", muxval); @@ -343,7 +343,7 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval) return bus; } -static void ls2085a_qds_enable_SFP_TX(u8 muxval) +static void ls2080a_qds_enable_SFP_TX(u8 muxval) { u8 brdcfg9; @@ -353,7 +353,7 @@ static void ls2085a_qds_enable_SFP_TX(u8 muxval) QIXIS_WRITE(brdcfg[9], brdcfg9); } -static void ls2085a_qds_mux_mdio(u8 muxval) +static void ls2080a_qds_mux_mdio(u8 muxval) { u8 brdcfg4; @@ -365,54 +365,54 @@ static void ls2085a_qds_mux_mdio(u8 muxval) } } -static int ls2085a_qds_mdio_read(struct mii_dev *bus, int addr, +static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr, int devad, int regnum) { - struct ls2085a_qds_mdio *priv = bus->priv; + struct ls2080a_qds_mdio *priv = bus->priv; - ls2085a_qds_mux_mdio(priv->muxval); + ls2080a_qds_mux_mdio(priv->muxval); return priv->realbus->read(priv->realbus, addr, devad, regnum); } -static int ls2085a_qds_mdio_write(struct mii_dev *bus, int addr, int devad, +static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad, int regnum, u16 value) { - struct ls2085a_qds_mdio *priv = bus->priv; + struct ls2080a_qds_mdio *priv = bus->priv; - ls2085a_qds_mux_mdio(priv->muxval); + ls2080a_qds_mux_mdio(priv->muxval); return priv->realbus->write(priv->realbus, addr, devad, regnum, value); } -static int ls2085a_qds_mdio_reset(struct mii_dev *bus) +static int ls2080a_qds_mdio_reset(struct mii_dev *bus) { - struct ls2085a_qds_mdio *priv = bus->priv; + struct ls2080a_qds_mdio *priv = bus->priv; return priv->realbus->reset(priv->realbus); } -static int ls2085a_qds_mdio_init(char *realbusname, u8 muxval) +static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval) { - struct ls2085a_qds_mdio *pmdio; + struct ls2080a_qds_mdio *pmdio; struct mii_dev *bus = mdio_alloc(); if (!bus) { - printf("Failed to allocate ls2085a_qds MDIO bus\n"); + printf("Failed to allocate ls2080a_qds MDIO bus\n"); return -1; } pmdio = malloc(sizeof(*pmdio)); if (!pmdio) { - printf("Failed to allocate ls2085a_qds private data\n"); + printf("Failed to allocate ls2080a_qds private data\n"); free(bus); return -1; } - bus->read = ls2085a_qds_mdio_read; - bus->write = ls2085a_qds_mdio_write; - bus->reset = ls2085a_qds_mdio_reset; - sprintf(bus->name, ls2085a_qds_mdio_name_for_muxval(muxval)); + bus->read = ls2080a_qds_mdio_read; + bus->write = ls2080a_qds_mdio_write; + bus->reset = ls2080a_qds_mdio_reset; + sprintf(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); @@ -474,8 +474,8 @@ static void initialize_dpmac_to_slot(void) serdes1_prtcl); break; default: - printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", - serdes1_prtcl); + printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", + __func__, serdes1_prtcl); break; } @@ -505,13 +505,13 @@ static void initialize_dpmac_to_slot(void) } break; default: - printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", - serdes2_prtcl); + printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", + __func__ , serdes2_prtcl); break; } } -void ls2085a_handle_phy_interface_sgmii(int dpmac_id) +void ls2080a_handle_phy_interface_sgmii(int dpmac_id) { int lane, slot; struct mii_dev *bus; @@ -580,8 +580,8 @@ void ls2085a_handle_phy_interface_sgmii(int dpmac_id) } break; default: - printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", - serdes1_prtcl); + printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", + __func__ , serdes1_prtcl); break; } @@ -626,13 +626,13 @@ serdes2: } break; default: - printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", - serdes2_prtcl); + printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", + __func__, serdes2_prtcl); break; } } -void ls2085a_handle_phy_interface_qsgmii(int dpmac_id) +void ls2080a_handle_phy_interface_qsgmii(int dpmac_id) { int lane = 0, slot; struct mii_dev *bus; @@ -706,7 +706,7 @@ void ls2085a_handle_phy_interface_qsgmii(int dpmac_id) qsgmii_configure_repeater(dpmac_id); } -void ls2085a_handle_phy_interface_xsgmii(int i) +void ls2080a_handle_phy_interface_xsgmii(int i) { struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & @@ -725,7 +725,7 @@ void ls2085a_handle_phy_interface_xsgmii(int i) * error. */ wriop_set_phy_address(i, i + 4); - ls2085a_qds_enable_SFP_TX(SFP_TX); + ls2080a_qds_enable_SFP_TX(SFP_TX); break; default: @@ -778,25 +778,25 @@ int board_eth_init(bd_t *bis) fm_memac_mdio_init(bis, memac_mdio1_info); /* Register the muxing front-ends to the MDIO buses */ - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2); for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { switch (wriop_get_enet_if(i)) { case PHY_INTERFACE_MODE_QSGMII: - ls2085a_handle_phy_interface_qsgmii(i); + ls2080a_handle_phy_interface_qsgmii(i); break; case PHY_INTERFACE_MODE_SGMII: - ls2085a_handle_phy_interface_sgmii(i); + ls2080a_handle_phy_interface_sgmii(i); break; case PHY_INTERFACE_MODE_XGMII: - ls2085a_handle_phy_interface_xsgmii(i); + ls2080a_handle_phy_interface_xsgmii(i); break; default: break; diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index b02d6e8..aa256a2 100644 --- a/board/freescale/ls2085aqds/ls2085aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -21,7 +21,7 @@ #include <hwconfig.h> #include "../common/qixis.h" -#include "ls2085aqds_qixis.h" +#include "ls2080aqds_qixis.h" #define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a @@ -226,11 +226,13 @@ void detail_board_ddr_info(void) puts("\nDDR "); print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); print_ddr_info(0); +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (gd->bd->bi_dram[2].size) { puts("\nDP-DDR "); print_size(gd->bd->bi_dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } +#endif } int dram_init(void) @@ -251,23 +253,6 @@ int arch_misc_init(void) } #endif -unsigned long get_dram_size_to_hide(void) -{ - unsigned long dram_to_hide = 0; - -/* Carve the Debug Server private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_DEBUG_SERVER - dram_to_hide += debug_server_get_dram_block_size(); -#endif - -/* Carve the MC private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_MC_ENET - dram_to_hide += mc_get_dram_block_size(); -#endif - - return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); -} - #ifdef CONFIG_FSL_MC_ENET void fdt_fixup_board_enet(void *fdt) { @@ -294,6 +279,7 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { + int err; u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; @@ -309,7 +295,9 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); - fsl_mc_ldpaa_exit(bd); + err = fsl_mc_ldpaa_exit(bd); + if (err) + return err; #endif return 0; diff --git a/board/freescale/ls2085aqds/ls2085aqds_qixis.h b/board/freescale/ls2080aqds/ls2080aqds_qixis.h index e281e5f..e281e5f 100644 --- a/board/freescale/ls2085aqds/ls2085aqds_qixis.h +++ b/board/freescale/ls2080aqds/ls2080aqds_qixis.h diff --git a/board/freescale/ls2085ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig index cb40db9..fe02575 100644 --- a/board/freescale/ls2085ardb/Kconfig +++ b/board/freescale/ls2080ardb/Kconfig @@ -1,8 +1,8 @@ -if TARGET_LS2085ARDB +if TARGET_LS2080ARDB config SYS_BOARD - default "ls2085ardb" + default "ls2080ardb" config SYS_VENDOR default "freescale" @@ -11,6 +11,6 @@ config SYS_SOC default "fsl-layerscape" config SYS_CONFIG_NAME - default "ls2085ardb" + default "ls2080ardb" endif diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS new file mode 100644 index 0000000..c9f3459 --- /dev/null +++ b/board/freescale/ls2080ardb/MAINTAINERS @@ -0,0 +1,10 @@ +LS2080A BOARD +M: Prabhakar Kushwaha <prabhakar@freescale.com> +S: Maintained +F: board/freescale/ls2080ardb/ +F: board/freescale/ls2080a/ls2080ardb.c +F: include/configs/ls2080ardb.h +F: configs/ls2080ardb_defconfig +F: configs/ls2080ardb_nand_defconfig +F: configs/ls2085ardb_defconfig +F: configs/ls2085ardb_nand_defconfig diff --git a/board/freescale/ls2085ardb/Makefile b/board/freescale/ls2080ardb/Makefile index de383cc..6a52167 100644 --- a/board/freescale/ls2085ardb/Makefile +++ b/board/freescale/ls2080ardb/Makefile @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ls2085ardb.o eth_ls2085rdb.o +obj-y += ls2080ardb.o eth_ls2080rdb.o obj-y += ddr.o diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2080ardb/README index 2f18243..7fc2569 100644 --- a/board/freescale/ls2085ardb/README +++ b/board/freescale/ls2080ardb/README @@ -1,17 +1,17 @@ Overview -------- -The LS2085A Reference Design (RDB) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS2085A +The LS2080A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS2080A Layerscape Architecture processor. -LS2085A SoC Overview +LS2080A SoC Overview ------------------ -The LS2085A integrated multicore processor combines eight ARM Cortex-A57 +The LS2080A integrated multicore processor combines eight ARM Cortex-A57 processor cores with high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. -The LS2085A SoC includes the following function and features: +The LS2080A SoC includes the following function and features: - Eight 64-bit ARM Cortex-A57 CPUs - 1 MB platform cache with ECC @@ -48,7 +48,7 @@ The LS2085A SoC includes the following function and features: - Service processor (SP) provides pre-boot initialization and secure-boot capabilities - LS2085ARDB board Overview + LS2080ARDB board Overview ----------------------- - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index 8d71ae1..6c19173 100644 --- a/board/freescale/ls2085ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR u8 dq_mapping_0, dq_mapping_2, dq_mapping_3; +#endif const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; int slot; @@ -79,7 +81,7 @@ found: pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); - +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num == CONFIG_DP_DDR_CTRL) { /* force DDR bus width to 32 bits */ popts->data_bus_width = 1; @@ -114,6 +116,7 @@ found: pdimm[slot].dq_mapping[16] = 0; pdimm[slot].dq_mapping[17] = 0; } +#endif /* To work at higher than 1333MT/s */ popts->half_strength_driver_enable = 0; /* @@ -131,10 +134,18 @@ found: popts->zq_en = 1; if (ddr_freq < 2350) { - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | - DDR_CDR2_VREF_RANGE_2; + if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) { + /* four chip-selects */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm); + popts->twot_en = 1; /* enable 2T timing */ + } else { + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | + DDR_CDR2_VREF_RANGE_2; + } } else { popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_100ohm); @@ -164,14 +175,29 @@ void dram_init_banksize(void) phys_size_t dp_ddr_size; #endif + /* + * gd->secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[1].start + + gd->secure_ram - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif } else { gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif } #ifdef CONFIG_SYS_DP_DDR_BASE_PHY diff --git a/board/freescale/ls2085ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h index bda9d4a..bda9d4a 100644 --- a/board/freescale/ls2085ardb/ddr.h +++ b/board/freescale/ls2080ardb/ddr.h diff --git a/board/freescale/ls2085ardb/eth_ls2085rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index d578757..db50e4e 100644 --- a/board/freescale/ls2085ardb/eth_ls2085rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -97,7 +97,7 @@ int board_eth_init(bd_t *bis) break; default: - printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n", + printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n", srds_s1); break; } diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 18953b8..c63b639 100644 --- a/board/freescale/ls2085ardb/ls2085ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -20,7 +20,7 @@ #include <asm/arch/soc.h> #include "../common/qixis.h" -#include "ls2085ardb_qixis.h" +#include "ls2080ardb_qixis.h" #define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a @@ -192,11 +192,13 @@ void detail_board_ddr_info(void) puts("\nDDR "); print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); print_ddr_info(0); +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (gd->bd->bi_dram[2].size) { puts("\nDP-DDR "); print_size(gd->bd->bi_dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } +#endif } int dram_init(void) @@ -217,23 +219,6 @@ int arch_misc_init(void) } #endif -unsigned long get_dram_size_to_hide(void) -{ - unsigned long dram_to_hide = 0; - -/* Carve the Debug Server private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_DEBUG_SERVER - dram_to_hide += debug_server_get_dram_block_size(); -#endif - -/* Carve the MC private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_MC_ENET - dram_to_hide += mc_get_dram_block_size(); -#endif - - return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); -} - #ifdef CONFIG_FSL_MC_ENET void fdt_fixup_board_enet(void *fdt) { @@ -260,6 +245,7 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { + int err; u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; @@ -275,7 +261,9 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); - fsl_mc_ldpaa_exit(bd); + err = fsl_mc_ldpaa_exit(bd); + if (err) + return err; #endif return 0; diff --git a/board/freescale/ls2085ardb/ls2085ardb_qixis.h b/board/freescale/ls2080ardb/ls2080ardb_qixis.h index cb60c00..cb60c00 100644 --- a/board/freescale/ls2085ardb/ls2085ardb_qixis.h +++ b/board/freescale/ls2080ardb/ls2080ardb_qixis.h diff --git a/board/freescale/ls2085a/MAINTAINERS b/board/freescale/ls2085a/MAINTAINERS deleted file mode 100644 index 90b4e47..0000000 --- a/board/freescale/ls2085a/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -LS2085A BOARD -M: York Sun <yorksun@freescale.com> -S: Maintained -F: board/freescale/ls2085a/ -F: include/configs/ls2085a_emu.h -F: configs/ls2085a_emu_defconfig -F: include/configs/ls2085a_simu.h -F: configs/ls2085a_simu_defconfig diff --git a/board/freescale/ls2085a/Makefile b/board/freescale/ls2085a/Makefile deleted file mode 100644 index 701b35c..0000000 --- a/board/freescale/ls2085a/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2014 Freescale Semiconductor -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ls2085a.o -obj-y += ddr.o diff --git a/board/freescale/ls2085aqds/MAINTAINERS b/board/freescale/ls2085aqds/MAINTAINERS deleted file mode 100644 index fbed672..0000000 --- a/board/freescale/ls2085aqds/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -LS2085A BOARD -M: Prabhakar Kushwaha <prabhakar@freescale.com> -S: Maintained -F: board/freescale/ls2085aqds/ -F: board/freescale/ls2085a/ls2085aqds.c -F: include/configs/ls2085aqds.h -F: configs/ls2085aqds_defconfig -F: configs/ls2085aqds_nand_defconfig diff --git a/board/freescale/ls2085ardb/MAINTAINERS b/board/freescale/ls2085ardb/MAINTAINERS deleted file mode 100644 index d5cce40..0000000 --- a/board/freescale/ls2085ardb/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -LS2085A BOARD -M: Prabhakar Kushwaha <prabhakar@freescale.com> -S: Maintained -F: board/freescale/ls2085ardb/ -F: board/freescale/ls2085a/ls2085ardb.c -F: include/configs/ls2085ardb.h -F: configs/ls2085ardb_defconfig -F: configs/ls2085ardb_nand_defconfig diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 6c863da..f8ae973 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -44,6 +44,9 @@ DECLARE_GLOBAL_DATA_PTR; #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ PAD_CTL_DSE_3P3V_49OHM) +#define QSPI_PAD_CTRL \ + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + #ifdef CONFIG_SYS_I2C_MXC #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1 for PMIC */ @@ -455,6 +458,29 @@ int board_phy_config(struct phy_device *phydev) } #endif +#ifdef CONFIG_FSL_QSPI +static iomux_v3_cfg_t const quadspi_pads[] = { + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), +}; + +int board_qspi_init(void) +{ + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, + ARRAY_SIZE(quadspi_pads)); + + /* Set the clock */ + set_clk_qspi(); + + return 0; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -481,6 +507,10 @@ int board_init(void) setup_lcd(); #endif +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + return 0; } diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index d3644a9..6b13939 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -18,10 +18,7 @@ config SYS_TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR - select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SOUTHBRIDGE_INTEL_C216 - select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_8192 config PCIE_ECAM_BASE diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index d56d903..ae96d23 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -19,10 +19,7 @@ config SYS_TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR - select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SOUTHBRIDGE_INTEL_C216 - select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_8192 config SYS_CAR_ADDR diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 044c6d5..57b89e0 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -40,7 +40,7 @@ static const struct ns16550_platdata igep_serial = { }; U_BOOT_DEVICE(igep_uart) = { - "serial_omap", + "ns16550_serial", &igep_serial }; diff --git a/board/kylin/kylin_rk3036/Kconfig b/board/kylin/kylin_rk3036/Kconfig new file mode 100644 index 0000000..5d75c1f --- /dev/null +++ b/board/kylin/kylin_rk3036/Kconfig @@ -0,0 +1,15 @@ +if TARGET_KYLIN_RK3036 + +config SYS_BOARD + default "kylin_rk3036" + +config SYS_VENDOR + default "kylin" + +config SYS_CONFIG_NAME + default "kylin_rk3036" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/kylin/kylin_rk3036/MAINTAINERS b/board/kylin/kylin_rk3036/MAINTAINERS new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/board/kylin/kylin_rk3036/MAINTAINERS diff --git a/board/kylin/kylin_rk3036/Makefile b/board/kylin/kylin_rk3036/Makefile new file mode 100644 index 0000000..0663270 --- /dev/null +++ b/board/kylin/kylin_rk3036/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += kylin_rk3036.o diff --git a/board/kylin/kylin_rk3036/kylin_rk3036.c b/board/kylin/kylin_rk3036/kylin_rk3036.c new file mode 100644 index 0000000..40d6b52 --- /dev/null +++ b/board/kylin/kylin_rk3036/kylin_rk3036.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/uart.h> +#include <asm/arch/sdram_rk3036.h> + +DECLARE_GLOBAL_DATA_PTR; + +void get_ddr_config(struct rk3036_ddr_config *config) +{ + /* K4B4G1646Q config */ + config->ddr_type = 3; + config->rank = 1; + config->cs0_row = 15; + config->cs1_row = 15; + + /* 8bank */ + config->bank = 3; + config->col = 10; + + /* 16bit bw */ + config->bw = 1; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = sdram_size(); + + return 0; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/board/lge/sniper/sniper.c b/board/lge/sniper/sniper.c index 4eff01a..c818c9d 100644 --- a/board/lge/sniper/sniper.c +++ b/board/lge/sniper/sniper.c @@ -35,7 +35,7 @@ static const struct ns16550_platdata serial_omap_platdata = { }; U_BOOT_DEVICE(sniper_serial) = { - .name = "serial_omap", + .name = "ns16550_serial", .platdata = &serial_omap_platdata }; diff --git a/board/lwmon5/Kconfig b/board/liebherr/lwmon5/Kconfig index 7b8c605..7f1bb40 100644 --- a/board/lwmon5/Kconfig +++ b/board/liebherr/lwmon5/Kconfig @@ -3,6 +3,9 @@ if TARGET_LWMON5 config SYS_BOARD default "lwmon5" +config SYS_VENDOR + default "liebherr" + config SYS_CONFIG_NAME default "lwmon5" diff --git a/board/lwmon5/MAINTAINERS b/board/liebherr/lwmon5/MAINTAINERS index 3ea1888..df45730 100644 --- a/board/lwmon5/MAINTAINERS +++ b/board/liebherr/lwmon5/MAINTAINERS @@ -1,6 +1,6 @@ LWMON5 BOARD M: Stefan Roese <sr@denx.de> S: Maintained -F: board/lwmon5/ +F: board/liebherr/lwmon5/ F: include/configs/lwmon5.h F: configs/lwmon5_defconfig diff --git a/board/lwmon5/Makefile b/board/liebherr/lwmon5/Makefile index 02478ca..02478ca 100644 --- a/board/lwmon5/Makefile +++ b/board/liebherr/lwmon5/Makefile diff --git a/board/lwmon5/config.mk b/board/liebherr/lwmon5/config.mk index d0348e8..d0348e8 100644 --- a/board/lwmon5/config.mk +++ b/board/liebherr/lwmon5/config.mk diff --git a/board/lwmon5/init.S b/board/liebherr/lwmon5/init.S index e5207c2..e5207c2 100644 --- a/board/lwmon5/init.S +++ b/board/liebherr/lwmon5/init.S diff --git a/board/lwmon5/kbd.c b/board/liebherr/lwmon5/kbd.c index d6c0a20..d6c0a20 100644 --- a/board/lwmon5/kbd.c +++ b/board/liebherr/lwmon5/kbd.c diff --git a/board/lwmon5/lwmon5.c b/board/liebherr/lwmon5/lwmon5.c index 8ad6712..8ad6712 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/liebherr/lwmon5/lwmon5.c diff --git a/board/lwmon5/sdram.c b/board/liebherr/lwmon5/sdram.c index bcb3449..bcb3449 100644 --- a/board/lwmon5/sdram.c +++ b/board/liebherr/lwmon5/sdram.c diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index babb0dc..fb89921 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -43,7 +43,7 @@ static const struct ns16550_platdata omap3logic_serial = { }; U_BOOT_DEVICE(omap3logic_uart) = { - "serial_omap", + "ns16550_serial", &omap3logic_serial }; diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 0a3b55b..4040114 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -50,7 +50,7 @@ static const struct ns16550_platdata zoom1_serial = { }; U_BOOT_DEVICE(zoom1_uart) = { - "serial_omap", + "ns16550_serial", &zoom1_serial }; diff --git a/board/overo/overo.c b/board/overo/overo.c index 20cbec2..a38b959 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -74,7 +74,7 @@ static const struct ns16550_platdata overo_serial = { }; U_BOOT_DEVICE(overo_uart) = { - "serial_omap", + "ns16550_serial", &overo_serial }; diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c index b97a09a..21793e8 100644 --- a/board/quipos/cairo/cairo.c +++ b/board/quipos/cairo/cairo.c @@ -97,7 +97,7 @@ static const struct ns16550_platdata cairo_serial = { }; U_BOOT_DEVICE(cairo_uart) = { - "serial_omap", + "ns16550_serial", &cairo_serial }; diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 6451d1d..4b80d7b 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -74,117 +74,132 @@ struct msg_get_clock_rate { u32 end_tag; }; -/* See comments in mbox.h for data source */ -static const struct { +/* + * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/ + * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733 + * http://git.drogon.net/?p=wiringPi;a=blob;f=wiringPi/wiringPi.c;h=503151f61014418b9c42f4476a6086f75cd4e64b;hb=refs/heads/master#l922 + */ +struct rpi_model { const char *name; const char *fdtfile; bool has_onboard_eth; -} models[] = { - [0] = { - "Unknown model", +}; + +static const struct rpi_model rpi_model_unknown = { + "Unknown model", #ifdef CONFIG_BCM2836 - "bcm2836-rpi-other.dtb", + "bcm2836-rpi-other.dtb", #else - "bcm2835-rpi-other.dtb", + "bcm2835-rpi-other.dtb", #endif - false, - }, -#ifdef CONFIG_BCM2836 - [BCM2836_BOARD_REV_2_B] = { + false, +}; + +static const struct rpi_model rpi_models_new_scheme[] = { + [0x4] = { "2 Model B", "bcm2836-rpi-2-b.dtb", true, }, -#else - [BCM2835_BOARD_REV_B_I2C0_2] = { + [0x9] = { + "Zero", + "bcm2835-rpi-zero.dtb", + false, + }, +}; + +static const struct rpi_model rpi_models_old_scheme[] = { + [0x2] = { "Model B (no P5)", "bcm2835-rpi-b-i2c0.dtb", true, }, - [BCM2835_BOARD_REV_B_I2C0_3] = { + [0x3] = { "Model B (no P5)", "bcm2835-rpi-b-i2c0.dtb", true, }, - [BCM2835_BOARD_REV_B_I2C1_4] = { + [0x4] = { "Model B", "bcm2835-rpi-b.dtb", true, }, - [BCM2835_BOARD_REV_B_I2C1_5] = { + [0x5] = { "Model B", "bcm2835-rpi-b.dtb", true, }, - [BCM2835_BOARD_REV_B_I2C1_6] = { + [0x6] = { "Model B", "bcm2835-rpi-b.dtb", true, }, - [BCM2835_BOARD_REV_A_7] = { + [0x7] = { "Model A", "bcm2835-rpi-a.dtb", false, }, - [BCM2835_BOARD_REV_A_8] = { + [0x8] = { "Model A", "bcm2835-rpi-a.dtb", false, }, - [BCM2835_BOARD_REV_A_9] = { + [0x9] = { "Model A", "bcm2835-rpi-a.dtb", false, }, - [BCM2835_BOARD_REV_B_REV2_d] = { + [0xd] = { "Model B rev2", "bcm2835-rpi-b-rev2.dtb", true, }, - [BCM2835_BOARD_REV_B_REV2_e] = { + [0xe] = { "Model B rev2", "bcm2835-rpi-b-rev2.dtb", true, }, - [BCM2835_BOARD_REV_B_REV2_f] = { + [0xf] = { "Model B rev2", "bcm2835-rpi-b-rev2.dtb", true, }, - [BCM2835_BOARD_REV_B_PLUS] = { + [0x10] = { "Model B+", "bcm2835-rpi-b-plus.dtb", true, }, - [BCM2835_BOARD_REV_CM] = { + [0x11] = { "Compute Module", "bcm2835-rpi-cm.dtb", false, }, - [BCM2835_BOARD_REV_A_PLUS] = { + [0x12] = { "Model A+", "bcm2835-rpi-a-plus.dtb", false, }, - [BCM2835_BOARD_REV_B_PLUS_13] = { + [0x13] = { "Model B+", "bcm2835-rpi-b-plus.dtb", true, }, - [BCM2835_BOARD_REV_CM_14] = { + [0x14] = { "Compute Module", "bcm2835-rpi-cm.dtb", false, }, - [BCM2835_BOARD_REV_A_PLUS_15] = { + [0x15] = { "Model A+", "bcm2835-rpi-a-plus.dtb", false, }, -#endif }; -u32 rpi_board_rev = 0; +static uint32_t revision; +static uint32_t rev_scheme; +static uint32_t rev_type; +static const struct rpi_model *model; int dram_init(void) { @@ -212,7 +227,7 @@ static void set_fdtfile(void) if (getenv("fdtfile")) return; - fdtfile = models[rpi_board_rev].fdtfile; + fdtfile = model->fdtfile; setenv("fdtfile", fdtfile); } @@ -221,7 +236,7 @@ static void set_usbethaddr(void) ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1); int ret; - if (!models[rpi_board_rev].has_onboard_eth) + if (!model->has_onboard_eth) return; if (getenv("usbethaddr")) @@ -245,10 +260,16 @@ static void set_usbethaddr(void) #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG static void set_board_info(void) { - char str_rev[11]; - sprintf(str_rev, "0x%X", rpi_board_rev); - setenv("board_rev", str_rev); - setenv("board_name", models[rpi_board_rev].name); + char s[11]; + + snprintf(s, sizeof(s), "0x%X", revision); + setenv("board_revision", s); + snprintf(s, sizeof(s), "%d", rev_scheme); + setenv("board_rev_scheme", s); + /* Can't rename this to board_rev_type since it's an ABI for scripts */ + snprintf(s, sizeof(s), "0x%X", rev_type); + setenv("board_rev", s); + setenv("board_name", model->name); } #endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */ @@ -290,7 +311,8 @@ static void get_board_rev(void) { ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1); int ret; - const char *name; + const struct rpi_model *models; + uint32_t models_count; BCM2835_MBOX_INIT_HDR(msg); BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV); @@ -313,23 +335,29 @@ static void get_board_rev(void) * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=98367&start=250 * http://www.raspberrypi.org/forums/viewtopic.php?f=31&t=20594 */ - rpi_board_rev = msg->get_board_rev.body.resp.rev; - if (rpi_board_rev & 0x800000) - rpi_board_rev = (rpi_board_rev >> 4) & 0xff; - else - rpi_board_rev &= 0xff; - if (rpi_board_rev >= ARRAY_SIZE(models)) { - printf("RPI: Board rev %u outside known range\n", - rpi_board_rev); - rpi_board_rev = 0; + revision = msg->get_board_rev.body.resp.rev; + if (revision & 0x800000) { + rev_scheme = 1; + rev_type = (revision >> 4) & 0xff; + models = rpi_models_new_scheme; + models_count = ARRAY_SIZE(rpi_models_new_scheme); + } else { + rev_scheme = 0; + rev_type = revision & 0xff; + models = rpi_models_old_scheme; + models_count = ARRAY_SIZE(rpi_models_old_scheme); } - if (!models[rpi_board_rev].name) { - printf("RPI: Board rev %u unknown\n", rpi_board_rev); - rpi_board_rev = 0; + if (rev_type >= models_count) { + printf("RPI: Board rev 0x%x outside known range\n", rev_type); + model = &rpi_model_unknown; + } else if (!models[rev_type].name) { + printf("RPI: Board rev 0x%x unknown\n", rev_type); + model = &rpi_model_unknown; + } else { + model = &models[rev_type]; } - name = models[rpi_board_rev].name; - printf("RPI %s\n", name); + printf("RPI %s (0x%x)\n", model->name, revision); } int board_init(void) diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index d943d63..1600568 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -10,7 +10,7 @@ #include <asm/gpio.h> #include <asm/arch/mmc.h> #include <power/pmic.h> -#include <usb/s3c_udc.h> +#include <usb/dwc2_udc.h> #include <asm/arch/cpu.h> #include <power/max8998_pmic.h> #include <samsung/misc.h> @@ -183,7 +183,7 @@ static int s5pc1xx_phy_control(int on) return 0; } -struct s3c_plat_otg_data s5pc110_otg_data = { +struct dwc2_plat_otg_data s5pc110_otg_data = { .phy_control = s5pc1xx_phy_control, .regs_phy = S5PC110_PHY_BASE, .regs_otg = S5PC110_OTG_BASE, @@ -193,7 +193,7 @@ struct s3c_plat_otg_data s5pc110_otg_data = { int board_usb_init(int index, enum usb_init_type init) { debug("USB_udc_probe\n"); - return s3c_udc_probe(&s5pc110_otg_data); + return dwc2_udc_probe(&s5pc110_otg_data); } #endif diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 36d493d..b4cb332 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -19,7 +19,7 @@ #include <errno.h> #include <mmc.h> #include <usb.h> -#include <usb/s3c_udc.h> +#include <usb/dwc2_udc.h> #include <samsung/misc.h> #include "setup.h" @@ -452,7 +452,7 @@ static int s5pc210_phy_control(int on) return regulator_set_mode(dev, OPMODE_LPM); } -struct s3c_plat_otg_data s5pc210_otg_data = { +struct dwc2_plat_otg_data s5pc210_otg_data = { .phy_control = s5pc210_phy_control, .regs_phy = EXYNOS4X12_USBPHY_BASE, .regs_otg = EXYNOS4X12_USBOTG_BASE, @@ -510,6 +510,6 @@ int board_usb_init(int index, enum usb_init_type init) } #endif debug("USB_udc_probe\n"); - return s3c_udc_probe(&s5pc210_otg_data); + return dwc2_udc_probe(&s5pc210_otg_data); } #endif diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index e163e45..54d01ec 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -18,7 +18,7 @@ #include <asm/arch/watchdog.h> #include <asm/arch/power.h> #include <power/pmic.h> -#include <usb/s3c_udc.h> +#include <usb/dwc2_udc.h> #include <power/max8997_pmic.h> #include <power/max8997_muic.h> #include <power/battery.h> @@ -41,7 +41,7 @@ u32 get_board_rev(void) #endif static void check_hw_revision(void); -struct s3c_plat_otg_data s5pc210_otg_data; +struct dwc2_plat_otg_data s5pc210_otg_data; int exynos_init(void) { @@ -419,7 +419,7 @@ static int s5pc210_phy_control(int on) return 0; } -struct s3c_plat_otg_data s5pc210_otg_data = { +struct dwc2_plat_otg_data s5pc210_otg_data = { .phy_control = s5pc210_phy_control, .regs_phy = EXYNOS4_USBPHY_BASE, .regs_otg = EXYNOS4_USBOTG_BASE, @@ -430,7 +430,7 @@ struct s3c_plat_otg_data s5pc210_otg_data = { int board_usb_init(int index, enum usb_init_type init) { debug("USB_udc_probe\n"); - return s3c_udc_probe(&s5pc210_otg_data); + return dwc2_udc_probe(&s5pc210_otg_data); } int g_dnl_board_usb_cable_connected(void) diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index a737749..7b28ae8 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -21,7 +21,7 @@ #include <libtizen.h> #include <errno.h> #include <usb.h> -#include <usb/s3c_udc.h> +#include <usb/dwc2_udc.h> #include <usb_mass_storage.h> DECLARE_GLOBAL_DATA_PTR; @@ -303,7 +303,7 @@ static int s5pc210_phy_control(int on) return 0; } -struct s3c_plat_otg_data s5pc210_otg_data = { +struct dwc2_plat_otg_data s5pc210_otg_data = { .phy_control = s5pc210_phy_control, .regs_phy = EXYNOS4X12_USBPHY_BASE, .regs_otg = EXYNOS4X12_USBOTG_BASE, @@ -314,7 +314,7 @@ struct s3c_plat_otg_data s5pc210_otg_data = { int board_usb_init(int index, enum usb_init_type init) { debug("USB_udc_probe\n"); - return s3c_udc_probe(&s5pc210_otg_data); + return dwc2_udc_probe(&s5pc210_otg_data); } int g_dnl_board_usb_cable_connected(void) diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index df46713..c25b486 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -17,7 +17,7 @@ #include <ld9040.h> #include <power/pmic.h> #include <usb.h> -#include <usb/s3c_udc.h> +#include <usb/dwc2_udc.h> #include <asm/arch/cpu.h> #include <power/max8998_pmic.h> #include <libtizen.h> @@ -179,7 +179,7 @@ static int s5pc210_phy_control(int on) return 0; } -struct s3c_plat_otg_data s5pc210_otg_data = { +struct dwc2_plat_otg_data s5pc210_otg_data = { .phy_control = s5pc210_phy_control, .regs_phy = EXYNOS4_USBPHY_BASE, .regs_otg = EXYNOS4_USBOTG_BASE, @@ -191,7 +191,7 @@ struct s3c_plat_otg_data s5pc210_otg_data = { int board_usb_init(int index, enum usb_init_type init) { debug("USB_udc_probe\n"); - return s3c_udc_probe(&s5pc210_otg_data); + return dwc2_udc_probe(&s5pc210_otg_data); } int exynos_early_init_f(void) diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c index 4882314..988c12a 100644 --- a/board/siemens/draco/board.c +++ b/board/siemens/draco/board.c @@ -196,11 +196,6 @@ struct ctrl_ioregs draco_ddr3_ioregs = { config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data, &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0); - - /* For Samsung 2Gbit RAM we need this delay otherwise config fails after - * soft reset. - */ - udelay(2000); } static void spl_siemens_board_init(void) diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index fc0918f..858a9ca 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -48,9 +48,6 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_ETH_DESIGNWARE) u32 interface = PHY_INTERFACE_MODE_MII; -#if defined(CONFIG_DW_AUTONEG) - interface = PHY_INTERFACE_MODE_GMII; -#endif if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif diff --git a/board/sr1500/MAINTAINERS b/board/sr1500/MAINTAINERS new file mode 100644 index 0000000..ed013a8 --- /dev/null +++ b/board/sr1500/MAINTAINERS @@ -0,0 +1,6 @@ +SOCFPGA SR1500 BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/sr1500/ +F: include/configs/socfpga_sr1500.h +F: configs/socfpga_sr1500_defconfig diff --git a/board/sr1500/Makefile b/board/sr1500/Makefile new file mode 100644 index 0000000..eae7ad0 --- /dev/null +++ b/board/sr1500/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga.o diff --git a/board/sr1500/qts/iocsr_config.h b/board/sr1500/qts/iocsr_config.h new file mode 100644 index 0000000..aa1e65c --- /dev/null +++ b/board/sr1500/qts/iocsr_config.h @@ -0,0 +1,660 @@ +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00100000, + 0x40000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x000E0180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00020000, + 0x00004000, + 0x000700C0, + 0x1C030000, + 0x0C000000, + 0x00000070, + 0x0001C030, + 0x00002000, + 0x00018060, + 0x0E018000, + 0x06000000, + 0x00000038, + 0x0000E018, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x001C0300, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x000000E0, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x1C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00001806, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x000C0300, + 0x700C0000, + 0x0FF00000, + 0x00000000, + 0x000700C0, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x200300C0, + 0x0C030000, + 0x0C000000, + 0x00000070, + 0x0001C030, + 0x00002000, + 0x10018060, + 0x0E018000, + 0x06000000, + 0x00010018, + 0x0000E018, + 0x00001000, + 0x0001C030, + 0x04000000, + 0x03000000, + 0x0000800C, + 0x00C0300C, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C420D80, + 0x0C3000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x20430000, + 0x0C003001, + 0x00C00481, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x90218000, + 0x86001800, + 0x00600240, + 0x80090218, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x4810C000, + 0x43000C00, + 0x00300120, + 0xC004810C, + 0x12043000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x45034071, + 0x0A281A01, + 0x806180D0, + 0x34071C06, + 0x01A034D0, + 0x180D0000, + 0x71C06806, + 0x01450340, + 0xD000001A, + 0x0680E380, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x18000000, + 0x01800902, + 0x00240860, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x20430000, + 0x0C003001, + 0x00C00481, + 0x00000FF0, + 0x4810C000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x90218000, + 0x86001800, + 0x00600240, + 0x80090218, + 0x24086001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x4810C000, + 0x43000C00, + 0x00300120, + 0xC004810C, + 0x12043000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x45034071, + 0x0A281A01, + 0x80E380D0, + 0x34071C06, + 0x01A00040, + 0x180D0002, + 0x71C06806, + 0x01450340, + 0xD00A281A, + 0x06806180, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x18000000, + 0x01800902, + 0x00240860, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x2043090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xCB2CA3DD, + 0xF5D5551E, + 0x034AD348, + 0x821A0000, + 0x0000D000, + 0x030C0680, + 0xDD59647A, + 0x1ECB2CA3, + 0x48F5D555, + 0x00035AD3, + 0x00080000, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000010, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00808000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x86120800, + 0x00600240, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xCB2CA3DD, + 0xF5D9651E, + 0x035AB2C8, + 0x821A0041, + 0x0000D000, + 0x00000680, + 0xDD59647A, + 0x1ECB2CA3, + 0x48F5D965, + 0x00035AD3, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000010, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820004, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00808000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x2043090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010000, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00202000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xCB2CA3D5, + 0xF6D9651E, + 0x035AB2C8, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDD59647A, + 0x1ECB2CA3, + 0x48F5D965, + 0x00034AD3, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x00000000, + 0x00000010, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820004, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00800000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020000, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00001000, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0xCB2CA3D5, + 0xF6D9651E, + 0x034AD348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1ECB2CA3, + 0x48F6D965, + 0x00034A92, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x00000000, + 0x00000010, + 0x0080C000, + 0x41000000, + 0x00000002, + 0x00820004, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00004000, + 0x00010000, + 0x40002080, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000008, + 0x00000020, + 0x00008000, + 0x20001040, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/sr1500/qts/pinmux_config.h b/board/sr1500/qts/pinmux_config.h new file mode 100644 index 0000000..45e390d --- /dev/null +++ b/board/sr1500/qts/pinmux_config.h @@ -0,0 +1,219 @@ +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 0, /* GENERALIO15 */ + 0, /* GENERALIO16 */ + 0, /* GENERALIO17 */ + 0, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 0, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 0, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 0, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 0, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 0, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 0, /* GPLMUX40 */ + 0, /* GPLMUX41 */ + 0, /* GPLMUX42 */ + 0, /* GPLMUX43 */ + 0, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 0, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 0, /* GPLMUX53 */ + 0, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 0, /* GPLMUX57 */ + 0, /* GPLMUX58 */ + 0, /* GPLMUX59 */ + 0, /* GPLMUX60 */ + 0, /* GPLMUX61 */ + 0, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/sr1500/qts/pll_config.h b/board/sr1500/qts/pll_config.h new file mode 100644 index 0000000..359e7ad --- /dev/null +++ b/board/sr1500/qts/pll_config.h @@ -0,0 +1,85 @@ +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 +#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 50000000 +#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 +#define CONFIG_HPS_CLK_QSPI_HZ 400000000 +#define CONFIG_HPS_CLK_SPIM_HZ 12500000 +#define CONFIG_HPS_CLK_CAN0_HZ 12500000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h new file mode 100644 index 0000000..edbaf89 --- /dev/null +++ b/board/sr1500/qts/sdram_config.h @@ -0,0 +1,341 @@ +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 7 +#define CALIB_VFIFO_OFFSET 5 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 99 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 99 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080421, + 0x10080520, + 0x10090044, + 0x100a0008, + 0x100b0000, + 0x10380400, + 0x10080441, + 0x100804c0, + 0x100a0024, + 0x10090010, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/sr1500/socfpga.c b/board/sr1500/socfpga.c new file mode 100644 index 0000000..617dffa --- /dev/null +++ b/board/sr1500/socfpga.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/reset_manager.h> +#include <asm/gpio.h> +#include <asm/io.h> + +int board_early_init_f(void) +{ + int ret; + + /* Reset the Marvell PHY 88E1510 */ + ret = gpio_request(63, "PHY reset"); + if (ret) + return ret; + + gpio_direction_output(63, 0); + mdelay(1); + gpio_set_value(63, 1); + mdelay(10); + + return 0; +} diff --git a/board/st/stm32f429-discovery/MAINTAINERS b/board/st/stm32f429-discovery/MAINTAINERS index 641f26a..fdb62e9 100644 --- a/board/st/stm32f429-discovery/MAINTAINERS +++ b/board/st/stm32f429-discovery/MAINTAINERS @@ -1,5 +1,5 @@ STM32F429-DISCOVERY BOARD -M: Kamil Lulko <rev13@wp.pl> +M: Kamil Lulko <kamil.lulko@gmail.com> S: Maintained F: board/st/stm32f429-discovery/ F: include/configs/stm32f429-discovery.h diff --git a/board/st/stm32f429-discovery/Makefile b/board/st/stm32f429-discovery/Makefile index 7e764e3..d94059d 100644 --- a/board/st/stm32f429-discovery/Makefile +++ b/board/st/stm32f429-discovery/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2015 -# Kamil Lulko, <rev13@wp.pl> +# Kamil Lulko, <kamil.lulko@gmail.com> # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/board/st/stm32f429-discovery/led.c b/board/st/stm32f429-discovery/led.c index 306e550..ee22009 100644 --- a/board/st/stm32f429-discovery/led.c +++ b/board/st/stm32f429-discovery/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index f418186..8bc2d9e 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -6,7 +6,7 @@ * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -17,6 +17,8 @@ #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> #include <asm/arch/fmc.h> +#include <dm/platdata.h> +#include <dm/platform_data/serial_stm32.h> DECLARE_GLOBAL_DATA_PTR; @@ -263,6 +265,15 @@ int dram_init(void) return rv; } +static const struct stm32_serial_platdata serial_platdata = { + .base = (struct stm32_usart *)STM32_USART1_BASE, +}; + +U_BOOT_DEVICE(stm32_serials) = { + .name = "serial_stm32", + .platdata = &serial_platdata, +}; + u32 get_board_rev(void) { return 0; diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index f6f2a60..9d67847 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -68,6 +68,18 @@ config MACH_SUN8I_A33 select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT +config MACH_SUN8I_H3 + bool "sun8i (Allwinner H3)" + select CPU_V7 + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + +config MACH_SUN8I_A83T + bool "sun8i (Allwinner A83T)" + select CPU_V7 + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + config MACH_SUN9I bool "sun9i (Allwinner A80)" select CPU_V7 @@ -78,7 +90,7 @@ endchoice # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" config MACH_SUN8I bool - default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 + default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T config DRAM_CLK @@ -367,6 +379,7 @@ config AXP_GPIO config VIDEO boolean "Enable graphical uboot console on HDMI, LCD or VGA" + depends on !MACH_SUN8I_A83T default y ---help--- Say Y here to add support for using a cfb console on the HDMI, LCD diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 96c4f3a..131c341 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -25,6 +25,7 @@ F: configs/A13-OLinuXinoM_defconfig F: configs/Auxtek-T003_defconfig F: configs/Auxtek-T004_defconfig F: configs/CHIP_defconfig +F: configs/Empire_electronix_d709_defconfig F: configs/inet98v_rev2_defconfig F: configs/mk802_a10s_defconfig F: configs/q8_a13_tablet_defconfig @@ -50,6 +51,8 @@ F: configs/Wits_Pro_A20_DKT_defconfig F: include/configs/sun8i.h F: configs/ga10h_v1_1_defconfig F: configs/gt90h_v4_defconfig +F: configs/orangepi_pc_defconfig +F: configs/orangepi_plus_defconfig F: configs/q8_a23_tablet_800x480_defconfig F: configs/q8_a33_tablet_800x480_defconfig F: configs/q8_a33_tablet_1024x600_defconfig @@ -99,6 +102,11 @@ M: Priit Laes <plaes@plaes.org> S: Maintained F: configs/sunxi_Gemei_G9_defconfig +H8HOMLET PROTO A83T BOARD +M: VishnuPatekar <vishnupatekar0510@gmail.com> +S: Maintained +F: configs/h8_homlet_v2_defconfig + HUMMINGBIRD-A31 BOARD M: Chen-Yu Tsai <wens@csie.org> S: Maintained @@ -119,6 +127,11 @@ M: Michal Suchanek <hramrach@gmail.com> S: Maintained F: configs/iNet_86VS_defconfig +LAMOBO-R1 BOARD +M: Jelle de Jong <jelledejong@powercraft.nl> +S: Maintained +F: configs/Lamobo_R1_defconfig + LINKSPRITE-PCDUINO BOARD M: Zoltan Herpai <wigyori@uid0.hu> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 6ac398c..386e2e0 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -430,26 +430,29 @@ void sunxi_board_init(void) int power_failed = 0; unsigned long ramsize; -#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER +#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ + defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER power_failed = axp_init(); -#ifdef CONFIG_AXP221_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); #endif power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); -#ifndef CONFIG_AXP209_POWER +#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); #endif -#ifdef CONFIG_AXP221_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); #endif #ifdef CONFIG_AXP221_POWER power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); #endif +#ifndef CONFIG_AXP818_POWER power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); -#ifndef CONFIG_AXP152_POWER +#endif +#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP818_POWER) power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); #endif #ifdef CONFIG_AXP209_POWER diff --git a/board/terasic/de0-nano-soc/socfpga.c b/board/terasic/de0-nano-soc/socfpga.c index 85700b0..97fb902 100644 --- a/board/terasic/de0-nano-soc/socfpga.c +++ b/board/terasic/de0-nano-soc/socfpga.c @@ -3,70 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> - -#include <micrel.h> -#include <netdev.h> -#include <phy.h> - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -/* - * PHY configuration - */ -#ifdef CONFIG_PHY_MICREL_KSZ9031 -int board_phy_config(struct phy_device *phydev) -{ - int ret; - /* - * These skew settings for the KSZ9021 ethernet phy is required for ethernet - * to work reliably on most flavors of cyclone5 boards. - */ - ret = ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - 0x70); - if (ret) - return ret; - - ret = ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - 0x7777); - if (ret) - return ret; - - ret = ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - 0); - if (ret) - return ret; - - ret = ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - 0x03FC); - if (ret) - return ret; - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} -#endif diff --git a/board/terasic/sockit/socfpga.c b/board/terasic/sockit/socfpga.c index a1dbc49..97fb902 100644 --- a/board/terasic/sockit/socfpga.c +++ b/board/terasic/sockit/socfpga.c @@ -3,83 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> -#include <asm/arch/reset_manager.h> -#include <asm/io.h> - -#include <usb.h> -#include <usb/s3c_udc.h> -#include <usb_mass_storage.h> - -#include <micrel.h> -#include <netdev.h> -#include <phy.h> - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -/* - * PHY configuration - */ -#ifdef CONFIG_PHY_MICREL_KSZ9021 -int board_phy_config(struct phy_device *phydev) -{ - int ret; - /* - * These skew settings for the KSZ9021 ethernet phy is required for ethernet - * to work reliably on most flavors of cyclone5 boards. - */ - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, - 0xf0f0); - if (ret) - return ret; - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} -#endif - -#ifdef CONFIG_USB_GADGET -struct s3c_plat_otg_data socfpga_otg_data = { - .regs_otg = CONFIG_USB_DWC2_REG_ADDR, - .usb_gusbcfg = 0x1417, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - return s3c_udc_probe(&socfpga_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - return 1; -} -#endif diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h index 23f22a0..3c007b7 100644 --- a/board/ti/am57xx/mux_data.h +++ b/board/ti/am57xx/mux_data.h @@ -255,10 +255,10 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */ {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */ {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */ - {WAKEUP0, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup0.Wakeup0 */ - {WAKEUP1, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup1.Wakeup1 */ - {WAKEUP2, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup2.Wakeup2 */ - {WAKEUP3, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup3.Wakeup3 */ + {WAKEUP0, (M0 | PULL_UP)}, /* Wakeup0.Wakeup0 */ + {WAKEUP1, (M0)}, /* Wakeup1.Wakeup1 */ + {WAKEUP2, (M0)}, /* Wakeup2.Wakeup2 */ + {WAKEUP3, (M0 | PULL_UP)}, /* Wakeup3.Wakeup3 */ {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */ {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */ {RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */ diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 56e3cfe..ff317ef 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -79,7 +79,7 @@ static const struct ns16550_platdata beagle_serial = { }; U_BOOT_DEVICE(beagle_uart) = { - "serial_omap", + "ns16550_serial", &beagle_serial }; diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index bf40144..1bfb362 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -372,7 +372,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { {I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */ {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */ {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */ - {WAKEUP2, (M14 | PIN_OUTPUT)}, /* Wakeup2.gpio1_2 */ + {WAKEUP2, (M14)}, /* Wakeup2.gpio1_2 */ }; #ifdef CONFIG_IODELAY_RECALIBRATION diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index a61cc14..1a447c7 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -52,7 +52,7 @@ static const struct ns16550_platdata devkit8000_serial = { }; U_BOOT_DEVICE(devkit8000_uart) = { - "serial_omap", + "ns16550_serial", &devkit8000_serial }; diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 0c8bd7d..dfa6293 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -69,6 +69,7 @@ int dram_init(void) int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_XILINX_GPIO if (reset_pin != -1) gpio_direction_output(reset_pin, 1); @@ -77,7 +78,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_XILINX_TB_WATCHDOG hw_watchdog_disable(); #endif - +#endif puts ("Reseting board\n"); __asm__ __volatile__ (" mts rmsr, r0;" \ "bra r0"); @@ -122,40 +123,5 @@ int board_eth_init(bd_t *bis) txpp, rxpp); #endif -#ifdef CONFIG_XILINX_LL_TEMAC -# ifdef XILINX_LLTEMAC_BASEADDR -# ifdef XILINX_LLTEMAC_FIFO_BASEADDR - ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, - XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR); -# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR -# if XILINX_LLTEMAC_SDMA_USE_DCR == 1 - ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, - XILINX_LL_TEMAC_M_SDMA_DCR, - XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); -# else - ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, - XILINX_LL_TEMAC_M_SDMA_PLB, - XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); -# endif -# endif -# endif -# ifdef XILINX_LLTEMAC_BASEADDR1 -# ifdef XILINX_LLTEMAC_FIFO_BASEADDR1 - ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, - XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1); -# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1 -# if XILINX_LLTEMAC_SDMA_USE_DCR == 1 - ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, - XILINX_LL_TEMAC_M_SDMA_DCR, - XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1); -# else - ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, - XILINX_LL_TEMAC_M_SDMA_PLB, - XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1); -# endif -# endif -# endif -#endif - return ret; } diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index d6d0d67..8ba146c 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -56,12 +56,6 @@ /* Ethernet controller is Ethernet_MAC */ #define XILINX_EMACLITE_BASEADDR 0x40C00000 -/* LL_TEMAC Ethernet controller */ -#define XILINX_LLTEMAC_BASEADDR 0x44000000 -#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180 -#define XILINX_LLTEMAC_BASEADDR1 0x44200000 -#define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000 - /* Watchdog IP is wxi_timebase_wdt_0 */ #define XILINX_WATCHDOG_BASEADDR 0x50000000 #define XILINX_WATCHDOG_IRQ 1 diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 88047ec..eab9303 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -12,6 +12,7 @@ hw-platform-$(CONFIG_TARGET_ZYNQ_ZED) := zed_hw_platform hw-platform-$(CONFIG_TARGET_ZYNQ_MICROZED) := MicroZed_hw_platform hw-platform-$(CONFIG_TARGET_ZYNQ_ZC702) := ZC702_hw_platform hw-platform-$(CONFIG_TARGET_ZYNQ_ZC706) := ZC706_hw_platform +hw-platform-$(CONFIG_TARGET_ZYNQ_ZYBO) := zybo_hw_platform # If you want to use customized ps7_init_gpl.c/h, # enable CONFIG_ZYNQ_CUSTOM_INIT and put them into custom_hw_platform/. # This line must be placed at the bottom of the list because diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 237f2c2..414f530 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -119,39 +119,9 @@ int board_eth_init(bd_t *bis) ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, txpp, rxpp); #endif - -#if defined(CONFIG_ZYNQ_GEM) -# if defined(CONFIG_ZYNQ_GEM0) - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, - CONFIG_ZYNQ_GEM_PHY_ADDR0, - CONFIG_ZYNQ_GEM_EMIO0); -# endif -# if defined(CONFIG_ZYNQ_GEM1) - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, - CONFIG_ZYNQ_GEM_PHY_ADDR1, - CONFIG_ZYNQ_GEM_EMIO1); -# endif -#endif return ret; } -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bd) -{ - int ret = 0; - -#if defined(CONFIG_ZYNQ_SDHCI) -# if defined(CONFIG_ZYNQ_SDHCI0) - ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); -# endif -# if defined(CONFIG_ZYNQ_SDHCI1) - ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); -# endif -#endif - return ret; -} -#endif - int dram_init(void) { #if CONFIG_IS_ENABLED(OF_CONTROL) diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c new file mode 100644 index 0000000..2c0feca --- /dev/null +++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c @@ -0,0 +1,11948 @@ +/* + * Copyright (c) Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: PLL SLCR REGISTERS */ + /* .. .. START: ARM PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x177 */ + /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x1a */ + /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. ARM_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. SRCSEL = 0x0 */ + /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. .. DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */ + /* .. .. .. CPU_6OR4XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. .. CPU_3OR2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */ + /* .. .. .. CPU_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. .. CPU_1XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. .. CPU_PERI_CLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + /* .. .. FINISH: ARM PLL INIT */ + /* .. .. START: DDR PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1db */ + /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x15 */ + /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. DDR_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. DDR_3XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. DDR_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */ + /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */ + /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + /* .. .. FINISH: DDR PLL INIT */ + /* .. .. START: IO PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1f4 */ + /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x14 */ + /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. IO_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. FINISH: IO PLL INIT */ + /* .. FINISH: PLL SLCR REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_clock_init_data_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: CLOCK CONTROL SLCR REGISTERS */ + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000128[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. DIVISOR0 = 0x34 */ + /* .. ==> 0XF8000128[13:8] = 0x00000034U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */ + /* .. DIVISOR1 = 0x2 */ + /* .. ==> 0XF8000128[25:20] = 0x00000002U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000138[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000138[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000140[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000140[6:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. DIVISOR = 0x8 */ + /* .. ==> 0XF8000140[13:8] = 0x00000008U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */ + /* .. DIVISOR1 = 0x1 */ + /* .. ==> 0XF8000140[25:20] = 0x00000001U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF800014C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF800014C[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x5 */ + /* .. ==> 0XF800014C[13:8] = 0x00000005U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. */ + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + /* .. CLKACT0 = 0x1 */ + /* .. ==> 0XF8000150[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. CLKACT1 = 0x0 */ + /* .. ==> 0XF8000150[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000150[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000150[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U), + /* .. CLKACT0 = 0x0 */ + /* .. ==> 0XF8000154[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. CLKACT1 = 0x1 */ + /* .. ==> 0XF8000154[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000154[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000154[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + /* .. .. START: TRACE CLOCK */ + /* .. .. FINISH: TRACE CLOCK */ + /* .. .. CLKACT = 0x1 */ + /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR = 0x5 */ + /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), + /* .. .. SRCSEL = 0x3 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ + /* .. .. DIVISOR0 = 0x6 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), + /* .. .. SRCSEL = 0x2 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ + /* .. .. DIVISOR0 = 0x35 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ + /* .. .. DIVISOR1 = 0x2 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + /* .. .. CLK_621_TRUE = 0x1 */ + /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + /* .. .. DMA_CPU_2XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. USB0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. USB1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. GEM0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */ + /* .. .. GEM1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. SDI0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */ + /* .. .. SDI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. SPI0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. SPI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. CAN0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. CAN1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. I2C0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */ + /* .. .. I2C1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. UART0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. UART1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. GPIO_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */ + /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */ + /* .. .. SMC_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU), + /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */ + /* .. START: THIS SHOULD BE BLANK */ + /* .. FINISH: THIS SHOULD BE BLANK */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + /* START: top */ + /* .. START: DDR INITIALIZATION */ + /* .. .. START: LOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + /* .. .. FINISH: LOCK DDR */ + /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */ + /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */ + /* .. .. reserved_reg_ddrc_active_ranks = 0x1 */ + /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */ + /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */ + /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000107FU), + /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */ + /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */ + /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */ + /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */ + /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */ + /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */ + /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */ + /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_w_xact_run_length = 0x8 */ + /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */ + /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */ + /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */ + /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + /* .. .. reg_ddrc_t_rc = 0x1a */ + /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */ + /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */ + /* .. .. reg_ddrc_t_rfc_min = 0x54 */ + /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */ + /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */ + /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */ + /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */ + /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU), + /* .. .. reg_ddrc_wr2pre = 0x12 */ + /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */ + /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */ + /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_t_faw = 0x15 */ + /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */ + /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */ + /* .. .. reg_ddrc_t_ras_max = 0x23 */ + /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */ + /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */ + /* .. .. reg_ddrc_t_ras_min = 0x13 */ + /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */ + /* .. .. reg_ddrc_t_cke = 0x4 */ + /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U), + /* .. .. reg_ddrc_write_latency = 0x5 */ + /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_rd2wr = 0x7 */ + /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */ + /* .. .. reg_ddrc_wr2rd = 0xe */ + /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */ + /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */ + /* .. .. reg_ddrc_t_xp = 0x4 */ + /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */ + /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */ + /* .. .. reg_ddrc_pad_pd = 0x0 */ + /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd2pre = 0x4 */ + /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */ + /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */ + /* .. .. reg_ddrc_t_rcd = 0x7 */ + /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U), + /* .. .. reg_ddrc_t_ccd = 0x4 */ + /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */ + /* .. .. reg_ddrc_t_rrd = 0x6 */ + /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_refresh_margin = 0x2 */ + /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_rp = 0x7 */ + /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */ + /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */ + /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */ + /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_mobile = 0x0 */ + /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 */ + /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_read_latency = 0x7 */ + /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */ + /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */ + /* .. .. reg_ddrc_dis_pad_pd = 0x0 */ + /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U), + /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */ + /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_prefer_write = 0x0 */ + /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_wr = 0x0 */ + /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_addr = 0x0 */ + /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_data = 0x0 */ + /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */ + /* .. .. ddrc_reg_mr_wr_busy = 0x0 */ + /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_type = 0x0 */ + /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */ + /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + /* .. .. reg_ddrc_final_wait_x32 = 0x7 */ + /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */ + /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */ + /* .. .. reg_ddrc_t_mrd = 0x4 */ + /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + /* .. .. reg_ddrc_emr2 = 0x8 */ + /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */ + /* .. .. reg_ddrc_emr3 = 0x0 */ + /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U), + /* .. .. reg_ddrc_mr = 0x930 */ + /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */ + /* .. .. reg_ddrc_emr = 0x4 */ + /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U), + /* .. .. reg_ddrc_burst_rdwr = 0x4 */ + /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ + /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ + /* .. .. reg_ddrc_burstchop = 0x0 */ + /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ + /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_dq = 0x0 */ + /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */ + /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */ + /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */ + /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */ + /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */ + /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */ + /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */ + /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */ + /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */ + /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */ + /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */ + /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */ + /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */ + /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */ + /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */ + /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */ + /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */ + /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */ + /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */ + /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */ + /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */ + /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */ + /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */ + /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U), + /* .. .. reg_phy_rd_local_odt = 0x0 */ + /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */ + /* .. .. reg_phy_idle_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */ + /* .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */ + /* .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + /* .. .. reg_phy_rd_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_wr_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */ + /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */ + /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */ + /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_fixed_re = 0x1 */ + /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */ + /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */ + /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_phy_clk_stall_level = 0x0 */ + /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + /* .. .. reg_ddrc_dis_dll_calib = 0x0 */ + /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + /* .. .. reg_ddrc_rd_odt_delay = 0x3 */ + /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */ + /* .. .. reg_ddrc_wr_odt_delay = 0x0 */ + /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd_odt_hold = 0x0 */ + /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_hold = 0x5 */ + /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + /* .. .. reg_ddrc_pageclose = 0x0 */ + /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_lpr_num_entries = 0x1f */ + /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */ + /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */ + /* .. .. reg_ddrc_auto_pre_en = 0x0 */ + /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_ddrc_refresh_update_level = 0x0 */ + /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_wc = 0x0 */ + /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */ + /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_ddrc_selfref_en = 0x0 */ + /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */ + /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */ + /* .. .. reg_arb_go2critical_en = 0x1 */ + /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + /* .. .. reg_ddrc_wrlvl_ww = 0x41 */ + /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */ + /* .. .. reg_ddrc_rdlvl_rr = 0x41 */ + /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */ + /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */ + /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U), + /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */ + /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */ + /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */ + /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */ + /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */ + /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */ + /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */ + /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */ + /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */ + /* .. .. reg_ddrc_t_cksre = 0x6 */ + /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_t_cksrx = 0x6 */ + /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_t_ckesr = 0x4 */ + /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + /* .. .. reg_ddrc_t_ckpde = 0x2 */ + /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_ckpdx = 0x2 */ + /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */ + /* .. .. reg_ddrc_t_ckdpde = 0x2 */ + /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_ckdpdx = 0x2 */ + /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */ + /* .. .. reg_ddrc_t_ckcsx = 0x3 */ + /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + /* .. .. reg_ddrc_dis_auto_zq = 0x0 */ + /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_ddr3 = 0x1 */ + /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_mod = 0x200 */ + /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */ + /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */ + /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */ + /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */ + /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */ + /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + /* .. .. t_zq_short_interval_x1024 = 0xc845 */ + /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */ + /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */ + /* .. .. dram_rstn_x1024 = 0x67 */ + /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */ + /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), + /* .. .. deeppowerdown_en = 0x0 */ + /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. deeppowerdown_to_x1024 = 0xff */ + /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */ + /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + /* .. .. dfi_wrlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */ + /* .. .. dfi_rdlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */ + /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */ + /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */ + /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + /* .. .. reg_ddrc_skip_ocd = 0x1 */ + /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */ + /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */ + /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */ + /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */ + /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */ + /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U), + /* .. .. START: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U), + /* .. .. FINISH: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + /* .. .. CORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */ + /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + /* .. .. STAT_NUM_CORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */ + /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + /* .. .. reg_ddrc_ecc_mode = 0x0 */ + /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_scrub = 0x1 */ + /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + /* .. .. reg_phy_dif_on = 0x0 */ + /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_dif_off = 0x0 */ + /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */ + /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */ + /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */ + /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */ + /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */ + /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */ + /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */ + /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */ + /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */ + /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */ + /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */ + /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */ + /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U), + /* .. .. reg_phy_bl2 = 0x0 */ + /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_at_spd_atpg = 0x0 */ + /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_enable = 0x0 */ + /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_force_err = 0x0 */ + /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_mode = 0x0 */ + /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. .. reg_phy_invert_clkout = 0x1 */ + /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. .. reg_phy_sel_logic = 0x0 */ + /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */ + /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */ + /* .. .. reg_phy_ctrl_slave_force = 0x0 */ + /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */ + /* .. .. reg_phy_lpddr = 0x0 */ + /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. .. reg_phy_cmd_latency = 0x0 */ + /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + /* .. .. reg_phy_wr_rl_delay = 0x2 */ + /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */ + /* .. .. reg_phy_rd_rl_delay = 0x4 */ + /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */ + /* .. .. reg_phy_dll_lock_diff = 0xf */ + /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */ + /* .. .. reg_phy_use_wr_level = 0x1 */ + /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */ + /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */ + /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */ + /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_dis_calib_rst = 0x0 */ + /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U), + /* .. .. reg_arb_page_addr_mask = 0x0 */ + /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_ddrc_lpddr2 = 0x0 */ + /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_derate_enable = 0x0 */ + /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr4_margin = 0x0 */ + /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + /* .. .. reg_ddrc_mr4_read_interval = 0x0 */ + /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */ + /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */ + /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */ + /* .. .. reg_ddrc_t_mrw = 0x5 */ + /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */ + /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */ + /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */ + /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */ + /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), + /* .. .. START: POLL ON DCI STATUS */ + /* .. .. DONE = 1 */ + /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */ + /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + /* .. .. FINISH: POLL ON DCI STATUS */ + /* .. .. START: UNLOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0x1 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + /* .. .. FINISH: UNLOCK DDR */ + /* .. .. START: CHECK DDR STATUS */ + /* .. .. ddrc_reg_operating_mode = 1 */ + /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + /* .. .. FINISH: CHECK DDR STATUS */ + /* .. FINISH: DDR INITIALIZATION */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_mio_init_data_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: OCM REMAPPING */ + /* .. VREF_EN = 0x1 */ + /* .. ==> 0XF8000B00[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. VREF_SEL = 0x0 */ + /* .. ==> 0XF8000B00[6:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B00, 0x00000071U, 0x00000001U), + /* .. FINISH: OCM REMAPPING */ + /* .. START: DDRIOB SETTINGS */ + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B40[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B40[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B40[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCI_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B40[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B40[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B44[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B44[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B44[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCI_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B44[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B44[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B48[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B48[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B48[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B48[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCI_TYPE = 0x3 */ + /* .. ==> 0XF8000B48[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B48[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B48[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCI_TYPE = 0x3 */ + /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B50[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B50[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B50[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B50[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCI_TYPE = 0x3 */ + /* .. ==> 0XF8000B50[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B50[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B50[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B54[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B54[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B54[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B54[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCI_TYPE = 0x3 */ + /* .. ==> 0XF8000B54[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B54[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B54[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B58[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B58[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B58[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCI_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B58[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B58[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + /* .. reserved_DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. reserved_DRIVE_N = 0xc */ + /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. reserved_SLEW_P = 0x3 */ + /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */ + /* .. reserved_SLEW_N = 0x3 */ + /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */ + /* .. reserved_GTL = 0x0 */ + /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. reserved_RTERM = 0x0 */ + /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + /* .. reserved_DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. reserved_DRIVE_N = 0xc */ + /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. reserved_SLEW_P = 0x6 */ + /* .. ==> 0XF8000B60[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. reserved_SLEW_N = 0x1f */ + /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. reserved_GTL = 0x0 */ + /* .. ==> 0XF8000B60[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. reserved_RTERM = 0x0 */ + /* .. ==> 0XF8000B60[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + /* .. reserved_DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. reserved_DRIVE_N = 0xc */ + /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. reserved_SLEW_P = 0x6 */ + /* .. ==> 0XF8000B64[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. reserved_SLEW_N = 0x1f */ + /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. reserved_GTL = 0x0 */ + /* .. ==> 0XF8000B64[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. reserved_RTERM = 0x0 */ + /* .. ==> 0XF8000B64[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + /* .. reserved_DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. reserved_DRIVE_N = 0xc */ + /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. reserved_SLEW_P = 0x6 */ + /* .. ==> 0XF8000B68[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. reserved_SLEW_N = 0x1f */ + /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. reserved_GTL = 0x0 */ + /* .. ==> 0XF8000B68[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. reserved_RTERM = 0x0 */ + /* .. ==> 0XF8000B68[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + /* .. VREF_INT_EN = 0x0 */ + /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. VREF_SEL = 0x0 */ + /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */ + /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */ + /* .. VREF_EXT_EN = 0x3 */ + /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. reserved_VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. REFIO_EN = 0x1 */ + /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. reserved_REFIO_TEST = 0x0 */ + /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */ + /* .. reserved_REFIO_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. reserved_DRST_B_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. reserved_CKE_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */ + /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + /* .. .. START: ASSERT RESET */ + /* .. .. RESET = 1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + /* .. .. FINISH: ASSERT RESET */ + /* .. .. START: DEASSERT RESET */ + /* .. .. RESET = 0 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reserved_VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + /* .. .. FINISH: DEASSERT RESET */ + /* .. .. RESET = 0x1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. ENABLE = 0x1 */ + /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. reserved_VRP_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reserved_VRN_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reserved_VRP_OUT = 0x0 */ + /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reserved_VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. NREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. .. NREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */ + /* .. .. NREF_OPT4 = 0x1 */ + /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */ + /* .. .. PREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[15:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ + /* .. .. PREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */ + /* .. .. UPDATE_CONTROL = 0x0 */ + /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. reserved_INIT_COMPLETE = 0x0 */ + /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. reserved_TST_CLK = 0x0 */ + /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. reserved_TST_HLN = 0x0 */ + /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. reserved_TST_HLP = 0x0 */ + /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. reserved_TST_RST = 0x0 */ + /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reserved_INT_DCI_EN = 0x0 */ + /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + /* .. FINISH: DDRIOB SETTINGS */ + /* .. START: MIO PROGRAMMING */ + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000704[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000704[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000704[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000704[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000704[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000704[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000704[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000704[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000704[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000708[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000708[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000708[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000708[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000708[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000708[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000708[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000708[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000708[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800070C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800070C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800070C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800070C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800070C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800070C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800070C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800070C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800070C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000710[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000710[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000710[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000710[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000710[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000710[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000710[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000710[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000710[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000714[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000714[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000714[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000714[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000714[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000714[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000714[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000714[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000714[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000718[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000718[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000718[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000718[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000718[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000718[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000718[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000718[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000718[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000740[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000740[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000740[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000740[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000740[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000740[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000740[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000740[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000740[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000744[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000744[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000744[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000744[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000744[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000744[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000744[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000744[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000744[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000748[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000748[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000748[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000748[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000748[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000748[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000748[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000748[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000748[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800074C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800074C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800074C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800074C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800074C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800074C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800074C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800074C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF800074C[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000750[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000750[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000750[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000750[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000750[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000750[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000750[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000750[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000750[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000754[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000754[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000754[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000754[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000754[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000754[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000754[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000754[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000754[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000758[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000758[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000758[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000758[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000758[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000758[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000758[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000758[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000758[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800075C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800075C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800075C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800075C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800075C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800075C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800075C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800075C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800075C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000760[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000760[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000760[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000760[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000760[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000760[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000760[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000760[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000760[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000764[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000764[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000764[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000764[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000764[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000764[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000764[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000764[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000764[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000768[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000768[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000768[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000768[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000768[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000768[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000768[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000768[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000768[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800076C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800076C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800076C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800076C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800076C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800076C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800076C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800076C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800076C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000770[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000770[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000770[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000770[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000770[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000770[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000770[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000770[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000770[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000774[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000774[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000774[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000774[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000774[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000774[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000774[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000774[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000774[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000778[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000778[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000778[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000778[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000778[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000778[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000778[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000778[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000778[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800077C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800077C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800077C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800077C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800077C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800077C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800077C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800077C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800077C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000780[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000780[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000780[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000780[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000780[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000780[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000780[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000780[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000780[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000784[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000784[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000784[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000784[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000784[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000784[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000784[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000784[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000784[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000788[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000788[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000788[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000788[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000788[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000788[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000788[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000788[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000788[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800078C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800078C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800078C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800078C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800078C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800078C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800078C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800078C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800078C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000790[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000790[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000790[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000790[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000790[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000790[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000790[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000790[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000790[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000794[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000794[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000794[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000794[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000794[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000794[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000794[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000794[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000794[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000798[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000798[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000798[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000798[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000798[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000798[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000798[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000798[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000798[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800079C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800079C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800079C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800079C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800079C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800079C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800079C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800079C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800079C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A8[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A8[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007AC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007AC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007AC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007AC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007AC[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007AC[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007AC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007AC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007AC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007BC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007BC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007BC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007BC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C0[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007C4[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C4[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), + /* .. SDIO0_WP_SEL = 55 */ + /* .. ==> 0XF8000830[5:0] = 0x00000037U */ + /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */ + /* .. SDIO0_CD_SEL = 47 */ + /* .. ==> 0XF8000830[21:16] = 0x0000002FU */ + /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U), + /* .. FINISH: MIO PROGRAMMING */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* .. START: SRAM/NOR SET OPMODE */ + /* .. FINISH: SRAM/NOR SET OPMODE */ + /* .. START: UART REGISTERS */ + /* .. BDIV = 0x6 */ + /* .. ==> 0XE0001034[7:0] = 0x00000006U */ + /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ + /* .. */ + EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), + /* .. CD = 0x3e */ + /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. */ + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + /* .. STPBRK = 0x0 */ + /* .. ==> 0XE0001000[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. STTBRK = 0x0 */ + /* .. ==> 0XE0001000[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. RSTTO = 0x0 */ + /* .. ==> 0XE0001000[6:6] = 0x00000000U */ + /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. TXDIS = 0x0 */ + /* .. ==> 0XE0001000[5:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. TXEN = 0x1 */ + /* .. ==> 0XE0001000[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. RXDIS = 0x0 */ + /* .. ==> 0XE0001000[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. RXEN = 0x1 */ + /* .. ==> 0XE0001000[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. TXRES = 0x1 */ + /* .. ==> 0XE0001000[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. RXRES = 0x1 */ + /* .. ==> 0XE0001000[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. */ + EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), + /* .. CHMODE = 0x0 */ + /* .. ==> 0XE0001004[9:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ + /* .. NBSTOP = 0x0 */ + /* .. ==> 0XE0001004[7:6] = 0x00000000U */ + /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. PAR = 0x4 */ + /* .. ==> 0XE0001004[5:3] = 0x00000004U */ + /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ + /* .. CHRL = 0x0 */ + /* .. ==> 0XE0001004[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. CLKS = 0x0 */ + /* .. ==> 0XE0001004[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), + /* .. FINISH: UART REGISTERS */ + /* .. START: TPIU WIDTH IN CASE OF EMIO */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0XC5ACCE55 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. .. START: TRACE CURRENT PORT SIZE */ + /* .. .. a = 2 */ + /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), + /* .. .. FINISH: TRACE CURRENT PORT SIZE */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0X0 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ + /* .. START: QSPI REGISTERS */ + /* .. Holdb_dr = 1 */ + /* .. ==> 0XE000D000[19:19] = 0x00000001U */ + /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. */ + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + /* .. FINISH: QSPI REGISTERS */ + /* .. START: PL POWER ON RESET REGISTERS */ + /* .. PCFG_POR_CNT_4K = 0 */ + /* .. ==> 0XF8007000[29:29] = 0x00000000U */ + /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + /* .. FINISH: PL POWER ON RESET REGISTERS */ + /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */ + /* .. .. START: NAND SET CYCLE */ + /* .. .. FINISH: NAND SET CYCLE */ + /* .. .. START: OPMODE */ + /* .. .. FINISH: OPMODE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: SRAM/NOR CS0 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS0 BASE ADDRESS */ + /* .. .. FINISH: NOR CS0 BASE ADDRESS */ + /* .. .. START: SRAM/NOR CS1 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS1 BASE ADDRESS */ + /* .. .. FINISH: NOR CS1 BASE ADDRESS */ + /* .. .. START: USB RESET */ + /* .. .. .. START: USB0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB0 RESET */ + /* .. .. .. START: USB1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB1 RESET */ + /* .. .. FINISH: USB RESET */ + /* .. .. START: ENET RESET */ + /* .. .. .. START: ENET0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET0 RESET */ + /* .. .. .. START: ENET1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET1 RESET */ + /* .. .. FINISH: ENET RESET */ + /* .. .. START: I2C RESET */ + /* .. .. .. START: I2C0 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C0 RESET */ + /* .. .. .. START: I2C1 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C1 RESET */ + /* .. .. FINISH: I2C RESET */ + /* .. .. START: NOR CHIP SELECT */ + /* .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. FINISH: NOR CHIP SELECT */ + /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_post_config_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: ENABLING LEVEL SHIFTER */ + /* .. USER_LVL_INP_EN_0 = 1 */ + /* .. ==> 0XF8000900[3:3] = 0x00000001U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. USER_LVL_OUT_EN_0 = 1 */ + /* .. ==> 0XF8000900[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. USER_LVL_INP_EN_1 = 1 */ + /* .. ==> 0XF8000900[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. USER_LVL_OUT_EN_1 = 1 */ + /* .. ==> 0XF8000900[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. */ + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + /* .. FINISH: ENABLING LEVEL SHIFTER */ + /* .. START: TPIU WIDTH IN CASE OF EMIO */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0XC5ACCE55 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. .. START: TRACE CURRENT PORT SIZE */ + /* .. .. a = 2 */ + /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), + /* .. .. FINISH: TRACE CURRENT PORT SIZE */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0X0 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ + /* .. START: FPGA RESETS TO 0 */ + /* .. reserved_3 = 0 */ + /* .. ==> 0XF8000240[31:25] = 0x00000000U */ + /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */ + /* .. reserved_FPGA_ACP_RST = 0 */ + /* .. ==> 0XF8000240[24:24] = 0x00000000U */ + /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. reserved_FPGA_AXDS3_RST = 0 */ + /* .. ==> 0XF8000240[23:23] = 0x00000000U */ + /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. reserved_FPGA_AXDS2_RST = 0 */ + /* .. ==> 0XF8000240[22:22] = 0x00000000U */ + /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. reserved_FPGA_AXDS1_RST = 0 */ + /* .. ==> 0XF8000240[21:21] = 0x00000000U */ + /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. reserved_FPGA_AXDS0_RST = 0 */ + /* .. ==> 0XF8000240[20:20] = 0x00000000U */ + /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. reserved_2 = 0 */ + /* .. ==> 0XF8000240[19:18] = 0x00000000U */ + /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. reserved_FSSW1_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[17:17] = 0x00000000U */ + /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. reserved_FSSW0_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[16:16] = 0x00000000U */ + /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. reserved_1 = 0 */ + /* .. ==> 0XF8000240[15:14] = 0x00000000U */ + /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ + /* .. reserved_FPGA_FMSW1_RST = 0 */ + /* .. ==> 0XF8000240[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. reserved_FPGA_FMSW0_RST = 0 */ + /* .. ==> 0XF8000240[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. reserved_FPGA_DMA3_RST = 0 */ + /* .. ==> 0XF8000240[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. reserved_FPGA_DMA2_RST = 0 */ + /* .. ==> 0XF8000240[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. reserved_FPGA_DMA1_RST = 0 */ + /* .. ==> 0XF8000240[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. reserved_FPGA_DMA0_RST = 0 */ + /* .. ==> 0XF8000240[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. reserved = 0 */ + /* .. ==> 0XF8000240[7:4] = 0x00000000U */ + /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. FPGA3_OUT_RST = 0 */ + /* .. ==> 0XF8000240[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. FPGA2_OUT_RST = 0 */ + /* .. ==> 0XF8000240[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. FPGA1_OUT_RST = 0 */ + /* .. ==> 0XF8000240[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. FPGA0_OUT_RST = 0 */ + /* .. ==> 0XF8000240[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + /* .. FINISH: FPGA RESETS TO 0 */ + /* .. START: AFI REGISTERS */ + /* .. .. START: AFI0 REGISTERS */ + /* .. .. FINISH: AFI0 REGISTERS */ + /* .. .. START: AFI1 REGISTERS */ + /* .. .. FINISH: AFI1 REGISTERS */ + /* .. .. START: AFI2 REGISTERS */ + /* .. .. FINISH: AFI2 REGISTERS */ + /* .. .. START: AFI3 REGISTERS */ + /* .. .. FINISH: AFI3 REGISTERS */ + /* .. FINISH: AFI REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_debug_3_0[] = { + /* START: top */ + /* .. START: CROSS TRIGGER CONFIGURATIONS */ + /* .. .. START: UNLOCKING CTI REGISTERS */ + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: UNLOCKING CTI REGISTERS */ + /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_pll_init_data_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: PLL SLCR REGISTERS */ + /* .. .. START: ARM PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x177 */ + /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x1a */ + /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. ARM_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. SRCSEL = 0x0 */ + /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. .. DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */ + /* .. .. .. CPU_6OR4XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. .. CPU_3OR2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */ + /* .. .. .. CPU_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. .. CPU_1XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. .. CPU_PERI_CLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + /* .. .. FINISH: ARM PLL INIT */ + /* .. .. START: DDR PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1db */ + /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x15 */ + /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. DDR_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. DDR_3XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. DDR_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */ + /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */ + /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + /* .. .. FINISH: DDR PLL INIT */ + /* .. .. START: IO PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1f4 */ + /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x14 */ + /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. IO_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. FINISH: IO PLL INIT */ + /* .. FINISH: PLL SLCR REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_clock_init_data_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: CLOCK CONTROL SLCR REGISTERS */ + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000128[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. DIVISOR0 = 0x34 */ + /* .. ==> 0XF8000128[13:8] = 0x00000034U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */ + /* .. DIVISOR1 = 0x2 */ + /* .. ==> 0XF8000128[25:20] = 0x00000002U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000138[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000138[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000140[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000140[6:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. DIVISOR = 0x8 */ + /* .. ==> 0XF8000140[13:8] = 0x00000008U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */ + /* .. DIVISOR1 = 0x1 */ + /* .. ==> 0XF8000140[25:20] = 0x00000001U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF800014C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF800014C[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x5 */ + /* .. ==> 0XF800014C[13:8] = 0x00000005U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. */ + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + /* .. CLKACT0 = 0x1 */ + /* .. ==> 0XF8000150[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. CLKACT1 = 0x0 */ + /* .. ==> 0XF8000150[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000150[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000150[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U), + /* .. CLKACT0 = 0x0 */ + /* .. ==> 0XF8000154[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. CLKACT1 = 0x1 */ + /* .. ==> 0XF8000154[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000154[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000154[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + /* .. .. START: TRACE CLOCK */ + /* .. .. FINISH: TRACE CLOCK */ + /* .. .. CLKACT = 0x1 */ + /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR = 0x5 */ + /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), + /* .. .. SRCSEL = 0x3 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ + /* .. .. DIVISOR0 = 0x6 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), + /* .. .. SRCSEL = 0x2 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ + /* .. .. DIVISOR0 = 0x35 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ + /* .. .. DIVISOR1 = 0x2 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + /* .. .. CLK_621_TRUE = 0x1 */ + /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + /* .. .. DMA_CPU_2XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. USB0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. USB1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. GEM0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */ + /* .. .. GEM1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. SDI0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */ + /* .. .. SDI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. SPI0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. SPI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. CAN0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. CAN1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. I2C0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */ + /* .. .. I2C1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. UART0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. UART1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. GPIO_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */ + /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */ + /* .. .. SMC_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU), + /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */ + /* .. START: THIS SHOULD BE BLANK */ + /* .. FINISH: THIS SHOULD BE BLANK */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + /* START: top */ + /* .. START: DDR INITIALIZATION */ + /* .. .. START: LOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + /* .. .. FINISH: LOCK DDR */ + /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */ + /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */ + /* .. .. reg_ddrc_active_ranks = 0x1 */ + /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */ + /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */ + /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_block = 0x1 */ + /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */ + /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */ + /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */ + /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */ + /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU), + /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */ + /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */ + /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */ + /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */ + /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */ + /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */ + /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */ + /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_w_xact_run_length = 0x8 */ + /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */ + /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */ + /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */ + /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + /* .. .. reg_ddrc_t_rc = 0x1a */ + /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */ + /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */ + /* .. .. reg_ddrc_t_rfc_min = 0x54 */ + /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */ + /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */ + /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */ + /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */ + /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU), + /* .. .. reg_ddrc_wr2pre = 0x12 */ + /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */ + /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */ + /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_t_faw = 0x15 */ + /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */ + /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */ + /* .. .. reg_ddrc_t_ras_max = 0x23 */ + /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */ + /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */ + /* .. .. reg_ddrc_t_ras_min = 0x13 */ + /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */ + /* .. .. reg_ddrc_t_cke = 0x4 */ + /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U), + /* .. .. reg_ddrc_write_latency = 0x5 */ + /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_rd2wr = 0x7 */ + /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */ + /* .. .. reg_ddrc_wr2rd = 0xe */ + /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */ + /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */ + /* .. .. reg_ddrc_t_xp = 0x4 */ + /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */ + /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */ + /* .. .. reg_ddrc_pad_pd = 0x0 */ + /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd2pre = 0x4 */ + /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */ + /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */ + /* .. .. reg_ddrc_t_rcd = 0x7 */ + /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U), + /* .. .. reg_ddrc_t_ccd = 0x4 */ + /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */ + /* .. .. reg_ddrc_t_rrd = 0x6 */ + /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_refresh_margin = 0x2 */ + /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_rp = 0x7 */ + /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */ + /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */ + /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */ + /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_sdram = 0x1 */ + /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_mobile = 0x0 */ + /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_clock_stop_en = 0x0 */ + /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_read_latency = 0x7 */ + /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */ + /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */ + /* .. .. reg_ddrc_dis_pad_pd = 0x0 */ + /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_loopback = 0x0 */ + /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */ + /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U), + /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */ + /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_prefer_write = 0x0 */ + /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_max_rank_rd = 0xf */ + /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */ + /* .. .. reg_ddrc_mr_wr = 0x0 */ + /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_addr = 0x0 */ + /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_data = 0x0 */ + /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */ + /* .. .. ddrc_reg_mr_wr_busy = 0x0 */ + /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_type = 0x0 */ + /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */ + /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU), + /* .. .. reg_ddrc_final_wait_x32 = 0x7 */ + /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */ + /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */ + /* .. .. reg_ddrc_t_mrd = 0x4 */ + /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + /* .. .. reg_ddrc_emr2 = 0x8 */ + /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */ + /* .. .. reg_ddrc_emr3 = 0x0 */ + /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U), + /* .. .. reg_ddrc_mr = 0x930 */ + /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */ + /* .. .. reg_ddrc_emr = 0x4 */ + /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U), + /* .. .. reg_ddrc_burst_rdwr = 0x4 */ + /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ + /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ + /* .. .. reg_ddrc_burstchop = 0x0 */ + /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ + /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_dq = 0x0 */ + /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_debug_mode = 0x0 */ + /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_level_start = 0x0 */ + /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_level_start = 0x0 */ + /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_phy_dq0_wait_t = 0x0 */ + /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U), + /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */ + /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */ + /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */ + /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */ + /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */ + /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */ + /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */ + /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */ + /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */ + /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */ + /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */ + /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */ + /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */ + /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */ + /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */ + /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */ + /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */ + /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */ + /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */ + /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */ + /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */ + /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */ + /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */ + /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U), + /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */ + /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */ + /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */ + /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. .. reg_phy_rd_local_odt = 0x0 */ + /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */ + /* .. .. reg_phy_idle_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */ + /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */ + /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */ + /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U), + /* .. .. reg_phy_rd_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_wr_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */ + /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */ + /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */ + /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_fixed_re = 0x1 */ + /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */ + /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */ + /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_phy_clk_stall_level = 0x0 */ + /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */ + /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */ + /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */ + /* .. .. reg_ddrc_dis_dll_calib = 0x0 */ + /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U), + /* .. .. reg_ddrc_rd_odt_delay = 0x3 */ + /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */ + /* .. .. reg_ddrc_wr_odt_delay = 0x0 */ + /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd_odt_hold = 0x0 */ + /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_hold = 0x5 */ + /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + /* .. .. reg_ddrc_pageclose = 0x0 */ + /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_lpr_num_entries = 0x1f */ + /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */ + /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */ + /* .. .. reg_ddrc_auto_pre_en = 0x0 */ + /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_ddrc_refresh_update_level = 0x0 */ + /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_wc = 0x0 */ + /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */ + /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_ddrc_selfref_en = 0x0 */ + /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */ + /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */ + /* .. .. reg_arb_go2critical_en = 0x1 */ + /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + /* .. .. reg_ddrc_wrlvl_ww = 0x41 */ + /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */ + /* .. .. reg_ddrc_rdlvl_rr = 0x41 */ + /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */ + /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */ + /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U), + /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */ + /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */ + /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */ + /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */ + /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */ + /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */ + /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */ + /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */ + /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */ + /* .. .. reg_ddrc_t_cksre = 0x6 */ + /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_t_cksrx = 0x6 */ + /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_t_ckesr = 0x4 */ + /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + /* .. .. reg_ddrc_t_ckpde = 0x2 */ + /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_ckpdx = 0x2 */ + /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */ + /* .. .. reg_ddrc_t_ckdpde = 0x2 */ + /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_ckdpdx = 0x2 */ + /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */ + /* .. .. reg_ddrc_t_ckcsx = 0x3 */ + /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + /* .. .. refresh_timer0_start_value_x32 = 0x0 */ + /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */ + /* .. .. refresh_timer1_start_value_x32 = 0x8 */ + /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U), + /* .. .. reg_ddrc_dis_auto_zq = 0x0 */ + /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_ddr3 = 0x1 */ + /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_mod = 0x200 */ + /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */ + /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */ + /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */ + /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */ + /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */ + /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + /* .. .. t_zq_short_interval_x1024 = 0xc845 */ + /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */ + /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */ + /* .. .. dram_rstn_x1024 = 0x67 */ + /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */ + /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), + /* .. .. deeppowerdown_en = 0x0 */ + /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. deeppowerdown_to_x1024 = 0xff */ + /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */ + /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + /* .. .. dfi_wrlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */ + /* .. .. dfi_rdlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */ + /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */ + /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */ + /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + /* .. .. reg_ddrc_2t_delay = 0x0 */ + /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */ + /* .. .. reg_ddrc_skip_ocd = 0x1 */ + /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */ + /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U), + /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */ + /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */ + /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */ + /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */ + /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */ + /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U), + /* .. .. START: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U), + /* .. .. FINISH: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + /* .. .. CORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */ + /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + /* .. .. STAT_NUM_CORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */ + /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + /* .. .. reg_ddrc_ecc_mode = 0x0 */ + /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_scrub = 0x1 */ + /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + /* .. .. reg_phy_dif_on = 0x0 */ + /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_dif_off = 0x0 */ + /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */ + /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */ + /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */ + /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */ + /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */ + /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */ + /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */ + /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */ + /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */ + /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */ + /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */ + /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */ + /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U), + /* .. .. reg_phy_loopback = 0x0 */ + /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_phy_bl2 = 0x0 */ + /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_at_spd_atpg = 0x0 */ + /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_enable = 0x0 */ + /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_force_err = 0x0 */ + /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_mode = 0x0 */ + /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. .. reg_phy_invert_clkout = 0x1 */ + /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */ + /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_phy_sel_logic = 0x0 */ + /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */ + /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */ + /* .. .. reg_phy_ctrl_slave_force = 0x0 */ + /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_rank0_delays = 0x1 */ + /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. reg_phy_lpddr = 0x0 */ + /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. .. reg_phy_cmd_latency = 0x0 */ + /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. reg_phy_int_lpbk = 0x0 */ + /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */ + /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U), + /* .. .. reg_phy_wr_rl_delay = 0x2 */ + /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */ + /* .. .. reg_phy_rd_rl_delay = 0x4 */ + /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */ + /* .. .. reg_phy_dll_lock_diff = 0xf */ + /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */ + /* .. .. reg_phy_use_wr_level = 0x1 */ + /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */ + /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */ + /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */ + /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_dis_calib_rst = 0x0 */ + /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U), + /* .. .. reg_arb_page_addr_mask = 0x0 */ + /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_ddrc_lpddr2 = 0x0 */ + /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_per_bank_refresh = 0x0 */ + /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_derate_enable = 0x0 */ + /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr4_margin = 0x0 */ + /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U), + /* .. .. reg_ddrc_mr4_read_interval = 0x0 */ + /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */ + /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */ + /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */ + /* .. .. reg_ddrc_t_mrw = 0x5 */ + /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */ + /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */ + /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */ + /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */ + /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), + /* .. .. START: POLL ON DCI STATUS */ + /* .. .. DONE = 1 */ + /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */ + /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + /* .. .. FINISH: POLL ON DCI STATUS */ + /* .. .. START: UNLOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0x1 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + /* .. .. FINISH: UNLOCK DDR */ + /* .. .. START: CHECK DDR STATUS */ + /* .. .. ddrc_reg_operating_mode = 1 */ + /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + /* .. .. FINISH: CHECK DDR STATUS */ + /* .. FINISH: DDR INITIALIZATION */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_mio_init_data_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: OCM REMAPPING */ + /* .. VREF_EN = 0x1 */ + /* .. ==> 0XF8000B00[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. CLK_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. SRSTN_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U), + /* .. FINISH: OCM REMAPPING */ + /* .. START: DDRIOB SETTINGS */ + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B40[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B40[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B40[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B40[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B40[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B44[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B44[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B44[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B44[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B44[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B48[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B48[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B48[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B48[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B48[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B48[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B48[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B50[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B50[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B50[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B50[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B50[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B50[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B50[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B54[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B54[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B54[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B54[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B54[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B54[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B54[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B58[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B58[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B58[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B58[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B58[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x3 */ + /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */ + /* .. SLEW_N = 0x3 */ + /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B60[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B60[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B60[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B64[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B64[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B64[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B68[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B68[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B68[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + /* .. VREF_INT_EN = 0x0 */ + /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. VREF_SEL = 0x0 */ + /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */ + /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */ + /* .. VREF_EXT_EN = 0x3 */ + /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. REFIO_EN = 0x1 */ + /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. REFIO_TEST = 0x0 */ + /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */ + /* .. REFIO_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DRST_B_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. CKE_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */ + /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + /* .. .. START: ASSERT RESET */ + /* .. .. RESET = 1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U), + /* .. .. FINISH: ASSERT RESET */ + /* .. .. START: DEASSERT RESET */ + /* .. .. RESET = 0 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + /* .. .. FINISH: DEASSERT RESET */ + /* .. .. RESET = 0x1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. ENABLE = 0x1 */ + /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. VRP_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. VRN_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. VRP_OUT = 0x0 */ + /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. NREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. .. NREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */ + /* .. .. NREF_OPT4 = 0x1 */ + /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */ + /* .. .. PREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */ + /* .. .. PREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */ + /* .. .. UPDATE_CONTROL = 0x0 */ + /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. INIT_COMPLETE = 0x0 */ + /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. TST_CLK = 0x0 */ + /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. TST_HLN = 0x0 */ + /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. TST_HLP = 0x0 */ + /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. TST_RST = 0x0 */ + /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. INT_DCI_EN = 0x0 */ + /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U), + /* .. FINISH: DDRIOB SETTINGS */ + /* .. START: MIO PROGRAMMING */ + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000704[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000704[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000704[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000704[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000704[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000704[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000704[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000704[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000704[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000708[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000708[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000708[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000708[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000708[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000708[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000708[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000708[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000708[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800070C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800070C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800070C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800070C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800070C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800070C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800070C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800070C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800070C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000710[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000710[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000710[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000710[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000710[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000710[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000710[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000710[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000710[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000714[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000714[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000714[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000714[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000714[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000714[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000714[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000714[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000714[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000718[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000718[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000718[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000718[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000718[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000718[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000718[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000718[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000718[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000740[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000740[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000740[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000740[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000740[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000740[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000740[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000740[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000740[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000744[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000744[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000744[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000744[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000744[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000744[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000744[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000744[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000744[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000748[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000748[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000748[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000748[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000748[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000748[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000748[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000748[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000748[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800074C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800074C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800074C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800074C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800074C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800074C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800074C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800074C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF800074C[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000750[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000750[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000750[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000750[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000750[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000750[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000750[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000750[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000750[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000754[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000754[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000754[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000754[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000754[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000754[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000754[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000754[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000754[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000758[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000758[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000758[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000758[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000758[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000758[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000758[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000758[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000758[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800075C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800075C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800075C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800075C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800075C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800075C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800075C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800075C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800075C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000760[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000760[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000760[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000760[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000760[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000760[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000760[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000760[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000760[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000764[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000764[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000764[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000764[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000764[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000764[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000764[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000764[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000764[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000768[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000768[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000768[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000768[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000768[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000768[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000768[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000768[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000768[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800076C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800076C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800076C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800076C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800076C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800076C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800076C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800076C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800076C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000770[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000770[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000770[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000770[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000770[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000770[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000770[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000770[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000770[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000774[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000774[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000774[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000774[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000774[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000774[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000774[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000774[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000774[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000778[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000778[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000778[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000778[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000778[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000778[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000778[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000778[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000778[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800077C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800077C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800077C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800077C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800077C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800077C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800077C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800077C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800077C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000780[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000780[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000780[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000780[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000780[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000780[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000780[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000780[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000780[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000784[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000784[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000784[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000784[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000784[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000784[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000784[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000784[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000784[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000788[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000788[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000788[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000788[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000788[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000788[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000788[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000788[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000788[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800078C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800078C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800078C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800078C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800078C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800078C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800078C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800078C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800078C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000790[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000790[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000790[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000790[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000790[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000790[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000790[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000790[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000790[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000794[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000794[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000794[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000794[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000794[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000794[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000794[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000794[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000794[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000798[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000798[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000798[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000798[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000798[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000798[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000798[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000798[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000798[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800079C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800079C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800079C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800079C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800079C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800079C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800079C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800079C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800079C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A8[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A8[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007AC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007AC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007AC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007AC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007AC[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007AC[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007AC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007AC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007AC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007BC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007BC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007BC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007BC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C0[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007C4[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C4[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), + /* .. SDIO0_WP_SEL = 55 */ + /* .. ==> 0XF8000830[5:0] = 0x00000037U */ + /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */ + /* .. SDIO0_CD_SEL = 47 */ + /* .. ==> 0XF8000830[21:16] = 0x0000002FU */ + /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U), + /* .. FINISH: MIO PROGRAMMING */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* .. START: SRAM/NOR SET OPMODE */ + /* .. FINISH: SRAM/NOR SET OPMODE */ + /* .. START: UART REGISTERS */ + /* .. BDIV = 0x6 */ + /* .. ==> 0XE0001034[7:0] = 0x00000006U */ + /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ + /* .. */ + EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), + /* .. CD = 0x3e */ + /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. */ + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + /* .. STPBRK = 0x0 */ + /* .. ==> 0XE0001000[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. STTBRK = 0x0 */ + /* .. ==> 0XE0001000[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. RSTTO = 0x0 */ + /* .. ==> 0XE0001000[6:6] = 0x00000000U */ + /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. TXDIS = 0x0 */ + /* .. ==> 0XE0001000[5:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. TXEN = 0x1 */ + /* .. ==> 0XE0001000[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. RXDIS = 0x0 */ + /* .. ==> 0XE0001000[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. RXEN = 0x1 */ + /* .. ==> 0XE0001000[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. TXRES = 0x1 */ + /* .. ==> 0XE0001000[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. RXRES = 0x1 */ + /* .. ==> 0XE0001000[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. */ + EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), + /* .. IRMODE = 0x0 */ + /* .. ==> 0XE0001004[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. UCLKEN = 0x0 */ + /* .. ==> 0XE0001004[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. CHMODE = 0x0 */ + /* .. ==> 0XE0001004[9:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ + /* .. NBSTOP = 0x0 */ + /* .. ==> 0XE0001004[7:6] = 0x00000000U */ + /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. PAR = 0x4 */ + /* .. ==> 0XE0001004[5:3] = 0x00000004U */ + /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ + /* .. CHRL = 0x0 */ + /* .. ==> 0XE0001004[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. CLKS = 0x0 */ + /* .. ==> 0XE0001004[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), + /* .. FINISH: UART REGISTERS */ + /* .. START: TPIU WIDTH IN CASE OF EMIO */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0XC5ACCE55 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. .. START: TRACE CURRENT PORT SIZE */ + /* .. .. a = 2 */ + /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), + /* .. .. FINISH: TRACE CURRENT PORT SIZE */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0X0 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ + /* .. START: QSPI REGISTERS */ + /* .. Holdb_dr = 1 */ + /* .. ==> 0XE000D000[19:19] = 0x00000001U */ + /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. */ + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + /* .. FINISH: QSPI REGISTERS */ + /* .. START: PL POWER ON RESET REGISTERS */ + /* .. PCFG_POR_CNT_4K = 0 */ + /* .. ==> 0XF8007000[29:29] = 0x00000000U */ + /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + /* .. FINISH: PL POWER ON RESET REGISTERS */ + /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */ + /* .. .. START: NAND SET CYCLE */ + /* .. .. FINISH: NAND SET CYCLE */ + /* .. .. START: OPMODE */ + /* .. .. FINISH: OPMODE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: SRAM/NOR CS0 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS0 BASE ADDRESS */ + /* .. .. FINISH: NOR CS0 BASE ADDRESS */ + /* .. .. START: SRAM/NOR CS1 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS1 BASE ADDRESS */ + /* .. .. FINISH: NOR CS1 BASE ADDRESS */ + /* .. .. START: USB RESET */ + /* .. .. .. START: USB0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB0 RESET */ + /* .. .. .. START: USB1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB1 RESET */ + /* .. .. FINISH: USB RESET */ + /* .. .. START: ENET RESET */ + /* .. .. .. START: ENET0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET0 RESET */ + /* .. .. .. START: ENET1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET1 RESET */ + /* .. .. FINISH: ENET RESET */ + /* .. .. START: I2C RESET */ + /* .. .. .. START: I2C0 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C0 RESET */ + /* .. .. .. START: I2C1 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C1 RESET */ + /* .. .. FINISH: I2C RESET */ + /* .. .. START: NOR CHIP SELECT */ + /* .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. FINISH: NOR CHIP SELECT */ + /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_post_config_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: ENABLING LEVEL SHIFTER */ + /* .. USER_INP_ICT_EN_0 = 3 */ + /* .. ==> 0XF8000900[1:0] = 0x00000003U */ + /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */ + /* .. USER_INP_ICT_EN_1 = 3 */ + /* .. ==> 0XF8000900[3:2] = 0x00000003U */ + /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */ + /* .. */ + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + /* .. FINISH: ENABLING LEVEL SHIFTER */ + /* .. START: TPIU WIDTH IN CASE OF EMIO */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0XC5ACCE55 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. .. START: TRACE CURRENT PORT SIZE */ + /* .. .. a = 2 */ + /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), + /* .. .. FINISH: TRACE CURRENT PORT SIZE */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0X0 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ + /* .. START: FPGA RESETS TO 0 */ + /* .. reserved_3 = 0 */ + /* .. ==> 0XF8000240[31:25] = 0x00000000U */ + /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */ + /* .. FPGA_ACP_RST = 0 */ + /* .. ==> 0XF8000240[24:24] = 0x00000000U */ + /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. FPGA_AXDS3_RST = 0 */ + /* .. ==> 0XF8000240[23:23] = 0x00000000U */ + /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. FPGA_AXDS2_RST = 0 */ + /* .. ==> 0XF8000240[22:22] = 0x00000000U */ + /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. FPGA_AXDS1_RST = 0 */ + /* .. ==> 0XF8000240[21:21] = 0x00000000U */ + /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. FPGA_AXDS0_RST = 0 */ + /* .. ==> 0XF8000240[20:20] = 0x00000000U */ + /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. reserved_2 = 0 */ + /* .. ==> 0XF8000240[19:18] = 0x00000000U */ + /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. FSSW1_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[17:17] = 0x00000000U */ + /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. FSSW0_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[16:16] = 0x00000000U */ + /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. reserved_1 = 0 */ + /* .. ==> 0XF8000240[15:14] = 0x00000000U */ + /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ + /* .. FPGA_FMSW1_RST = 0 */ + /* .. ==> 0XF8000240[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. FPGA_FMSW0_RST = 0 */ + /* .. ==> 0XF8000240[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. FPGA_DMA3_RST = 0 */ + /* .. ==> 0XF8000240[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. FPGA_DMA2_RST = 0 */ + /* .. ==> 0XF8000240[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. FPGA_DMA1_RST = 0 */ + /* .. ==> 0XF8000240[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. FPGA_DMA0_RST = 0 */ + /* .. ==> 0XF8000240[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. reserved = 0 */ + /* .. ==> 0XF8000240[7:4] = 0x00000000U */ + /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. FPGA3_OUT_RST = 0 */ + /* .. ==> 0XF8000240[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. FPGA2_OUT_RST = 0 */ + /* .. ==> 0XF8000240[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. FPGA1_OUT_RST = 0 */ + /* .. ==> 0XF8000240[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. FPGA0_OUT_RST = 0 */ + /* .. ==> 0XF8000240[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + /* .. FINISH: FPGA RESETS TO 0 */ + /* .. START: AFI REGISTERS */ + /* .. .. START: AFI0 REGISTERS */ + /* .. .. FINISH: AFI0 REGISTERS */ + /* .. .. START: AFI1 REGISTERS */ + /* .. .. FINISH: AFI1 REGISTERS */ + /* .. .. START: AFI2 REGISTERS */ + /* .. .. FINISH: AFI2 REGISTERS */ + /* .. .. START: AFI3 REGISTERS */ + /* .. .. FINISH: AFI3 REGISTERS */ + /* .. FINISH: AFI REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_debug_2_0[] = { + /* START: top */ + /* .. START: CROSS TRIGGER CONFIGURATIONS */ + /* .. .. START: UNLOCKING CTI REGISTERS */ + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: UNLOCKING CTI REGISTERS */ + /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_pll_init_data_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: PLL SLCR REGISTERS */ + /* .. .. START: ARM PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x177 */ + /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x1a */ + /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. ARM_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. SRCSEL = 0x0 */ + /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. .. DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */ + /* .. .. .. CPU_6OR4XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. .. CPU_3OR2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */ + /* .. .. .. CPU_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. .. CPU_1XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. .. CPU_PERI_CLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + /* .. .. FINISH: ARM PLL INIT */ + /* .. .. START: DDR PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1db */ + /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x15 */ + /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. DDR_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. DDR_3XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. DDR_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */ + /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */ + /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + /* .. .. FINISH: DDR PLL INIT */ + /* .. .. START: IO PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1f4 */ + /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x14 */ + /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. IO_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. FINISH: IO PLL INIT */ + /* .. FINISH: PLL SLCR REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_clock_init_data_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: CLOCK CONTROL SLCR REGISTERS */ + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000128[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. DIVISOR0 = 0x34 */ + /* .. ==> 0XF8000128[13:8] = 0x00000034U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */ + /* .. DIVISOR1 = 0x2 */ + /* .. ==> 0XF8000128[25:20] = 0x00000002U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000138[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000138[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000140[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000140[6:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. DIVISOR = 0x8 */ + /* .. ==> 0XF8000140[13:8] = 0x00000008U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */ + /* .. DIVISOR1 = 0x1 */ + /* .. ==> 0XF8000140[25:20] = 0x00000001U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF800014C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF800014C[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x5 */ + /* .. ==> 0XF800014C[13:8] = 0x00000005U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. */ + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + /* .. CLKACT0 = 0x1 */ + /* .. ==> 0XF8000150[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. CLKACT1 = 0x0 */ + /* .. ==> 0XF8000150[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000150[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000150[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U), + /* .. CLKACT0 = 0x0 */ + /* .. ==> 0XF8000154[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. CLKACT1 = 0x1 */ + /* .. ==> 0XF8000154[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000154[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000154[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + /* .. .. START: TRACE CLOCK */ + /* .. .. FINISH: TRACE CLOCK */ + /* .. .. CLKACT = 0x1 */ + /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR = 0x5 */ + /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), + /* .. .. SRCSEL = 0x3 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ + /* .. .. DIVISOR0 = 0x6 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), + /* .. .. SRCSEL = 0x2 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ + /* .. .. DIVISOR0 = 0x35 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ + /* .. .. DIVISOR1 = 0x2 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + /* .. .. CLK_621_TRUE = 0x1 */ + /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + /* .. .. DMA_CPU_2XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. USB0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. USB1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. GEM0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */ + /* .. .. GEM1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. SDI0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */ + /* .. .. SDI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. SPI0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. SPI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. CAN0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. CAN1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. I2C0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */ + /* .. .. I2C1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. UART0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. UART1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. GPIO_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */ + /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */ + /* .. .. SMC_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU), + /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */ + /* .. START: THIS SHOULD BE BLANK */ + /* .. FINISH: THIS SHOULD BE BLANK */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + /* START: top */ + /* .. START: DDR INITIALIZATION */ + /* .. .. START: LOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + /* .. .. FINISH: LOCK DDR */ + /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */ + /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */ + /* .. .. reg_ddrc_active_ranks = 0x1 */ + /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */ + /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */ + /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_block = 0x1 */ + /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */ + /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */ + /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */ + /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */ + /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU), + /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */ + /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */ + /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */ + /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */ + /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */ + /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */ + /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */ + /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_w_xact_run_length = 0x8 */ + /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */ + /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */ + /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */ + /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + /* .. .. reg_ddrc_t_rc = 0x1a */ + /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */ + /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */ + /* .. .. reg_ddrc_t_rfc_min = 0x54 */ + /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */ + /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */ + /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */ + /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */ + /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU), + /* .. .. reg_ddrc_wr2pre = 0x12 */ + /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */ + /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */ + /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_t_faw = 0x15 */ + /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */ + /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */ + /* .. .. reg_ddrc_t_ras_max = 0x23 */ + /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */ + /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */ + /* .. .. reg_ddrc_t_ras_min = 0x13 */ + /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */ + /* .. .. reg_ddrc_t_cke = 0x4 */ + /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U), + /* .. .. reg_ddrc_write_latency = 0x5 */ + /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_rd2wr = 0x7 */ + /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */ + /* .. .. reg_ddrc_wr2rd = 0xe */ + /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */ + /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */ + /* .. .. reg_ddrc_t_xp = 0x4 */ + /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */ + /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */ + /* .. .. reg_ddrc_pad_pd = 0x0 */ + /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd2pre = 0x4 */ + /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */ + /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */ + /* .. .. reg_ddrc_t_rcd = 0x7 */ + /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U), + /* .. .. reg_ddrc_t_ccd = 0x4 */ + /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */ + /* .. .. reg_ddrc_t_rrd = 0x6 */ + /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_refresh_margin = 0x2 */ + /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_rp = 0x7 */ + /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */ + /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */ + /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */ + /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_sdram = 0x1 */ + /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_mobile = 0x0 */ + /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_clock_stop_en = 0x0 */ + /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_read_latency = 0x7 */ + /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */ + /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */ + /* .. .. reg_ddrc_dis_pad_pd = 0x0 */ + /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_loopback = 0x0 */ + /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */ + /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U), + /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */ + /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_prefer_write = 0x0 */ + /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_max_rank_rd = 0xf */ + /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */ + /* .. .. reg_ddrc_mr_wr = 0x0 */ + /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_addr = 0x0 */ + /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_data = 0x0 */ + /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */ + /* .. .. ddrc_reg_mr_wr_busy = 0x0 */ + /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_type = 0x0 */ + /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */ + /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU), + /* .. .. reg_ddrc_final_wait_x32 = 0x7 */ + /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */ + /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */ + /* .. .. reg_ddrc_t_mrd = 0x4 */ + /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + /* .. .. reg_ddrc_emr2 = 0x8 */ + /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */ + /* .. .. reg_ddrc_emr3 = 0x0 */ + /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U), + /* .. .. reg_ddrc_mr = 0x930 */ + /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */ + /* .. .. reg_ddrc_emr = 0x4 */ + /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U), + /* .. .. reg_ddrc_burst_rdwr = 0x4 */ + /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ + /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ + /* .. .. reg_ddrc_burstchop = 0x0 */ + /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ + /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_dq = 0x0 */ + /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_debug_mode = 0x0 */ + /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_level_start = 0x0 */ + /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_level_start = 0x0 */ + /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_phy_dq0_wait_t = 0x0 */ + /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U), + /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */ + /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */ + /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */ + /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */ + /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */ + /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */ + /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */ + /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */ + /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */ + /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */ + /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */ + /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */ + /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */ + /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */ + /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */ + /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */ + /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */ + /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */ + /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */ + /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */ + /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */ + /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */ + /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */ + /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U), + /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */ + /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */ + /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */ + /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. .. reg_phy_rd_local_odt = 0x0 */ + /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */ + /* .. .. reg_phy_idle_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */ + /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */ + /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */ + /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U), + /* .. .. reg_phy_rd_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_wr_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */ + /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */ + /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */ + /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_fixed_re = 0x1 */ + /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */ + /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */ + /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_phy_clk_stall_level = 0x0 */ + /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */ + /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */ + /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */ + /* .. .. reg_ddrc_dis_dll_calib = 0x0 */ + /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U), + /* .. .. reg_ddrc_rd_odt_delay = 0x3 */ + /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */ + /* .. .. reg_ddrc_wr_odt_delay = 0x0 */ + /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd_odt_hold = 0x0 */ + /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_hold = 0x5 */ + /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + /* .. .. reg_ddrc_pageclose = 0x0 */ + /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_lpr_num_entries = 0x1f */ + /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */ + /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */ + /* .. .. reg_ddrc_auto_pre_en = 0x0 */ + /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_ddrc_refresh_update_level = 0x0 */ + /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_wc = 0x0 */ + /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */ + /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_ddrc_selfref_en = 0x0 */ + /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */ + /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */ + /* .. .. reg_arb_go2critical_en = 0x1 */ + /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + /* .. .. reg_ddrc_wrlvl_ww = 0x41 */ + /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */ + /* .. .. reg_ddrc_rdlvl_rr = 0x41 */ + /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */ + /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */ + /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U), + /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */ + /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */ + /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */ + /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + /* .. .. refresh_timer0_start_value_x32 = 0x0 */ + /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */ + /* .. .. refresh_timer1_start_value_x32 = 0x8 */ + /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U), + /* .. .. reg_ddrc_dis_auto_zq = 0x0 */ + /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_ddr3 = 0x1 */ + /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_mod = 0x200 */ + /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */ + /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */ + /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */ + /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */ + /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */ + /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + /* .. .. t_zq_short_interval_x1024 = 0xc845 */ + /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */ + /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */ + /* .. .. dram_rstn_x1024 = 0x67 */ + /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */ + /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), + /* .. .. deeppowerdown_en = 0x0 */ + /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. deeppowerdown_to_x1024 = 0xff */ + /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */ + /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + /* .. .. dfi_wrlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */ + /* .. .. dfi_rdlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */ + /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */ + /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */ + /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + /* .. .. reg_ddrc_2t_delay = 0x0 */ + /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */ + /* .. .. reg_ddrc_skip_ocd = 0x1 */ + /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */ + /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U), + /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */ + /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */ + /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */ + /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */ + /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */ + /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U), + /* .. .. START: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U), + /* .. .. FINISH: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + /* .. .. CORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */ + /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + /* .. .. STAT_NUM_CORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */ + /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + /* .. .. reg_ddrc_ecc_mode = 0x0 */ + /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_scrub = 0x1 */ + /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + /* .. .. reg_phy_dif_on = 0x0 */ + /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_dif_off = 0x0 */ + /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */ + /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */ + /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */ + /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */ + /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */ + /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */ + /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */ + /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */ + /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */ + /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */ + /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */ + /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */ + /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U), + /* .. .. reg_phy_loopback = 0x0 */ + /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_phy_bl2 = 0x0 */ + /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_at_spd_atpg = 0x0 */ + /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_enable = 0x0 */ + /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_force_err = 0x0 */ + /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_mode = 0x0 */ + /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. .. reg_phy_invert_clkout = 0x1 */ + /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */ + /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_phy_sel_logic = 0x0 */ + /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */ + /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */ + /* .. .. reg_phy_ctrl_slave_force = 0x0 */ + /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_rank0_delays = 0x1 */ + /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. reg_phy_lpddr = 0x0 */ + /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. .. reg_phy_cmd_latency = 0x0 */ + /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. reg_phy_int_lpbk = 0x0 */ + /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */ + /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U), + /* .. .. reg_phy_wr_rl_delay = 0x2 */ + /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */ + /* .. .. reg_phy_rd_rl_delay = 0x4 */ + /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */ + /* .. .. reg_phy_dll_lock_diff = 0xf */ + /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */ + /* .. .. reg_phy_use_wr_level = 0x1 */ + /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */ + /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */ + /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */ + /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_dis_calib_rst = 0x0 */ + /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U), + /* .. .. reg_arb_page_addr_mask = 0x0 */ + /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_ddrc_lpddr2 = 0x0 */ + /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_per_bank_refresh = 0x0 */ + /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_derate_enable = 0x0 */ + /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr4_margin = 0x0 */ + /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U), + /* .. .. reg_ddrc_mr4_read_interval = 0x0 */ + /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */ + /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */ + /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */ + /* .. .. reg_ddrc_t_mrw = 0x5 */ + /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */ + /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */ + /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */ + /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */ + /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), + /* .. .. START: POLL ON DCI STATUS */ + /* .. .. DONE = 1 */ + /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */ + /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + /* .. .. FINISH: POLL ON DCI STATUS */ + /* .. .. START: UNLOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0x1 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + /* .. .. FINISH: UNLOCK DDR */ + /* .. .. START: CHECK DDR STATUS */ + /* .. .. ddrc_reg_operating_mode = 1 */ + /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + /* .. .. FINISH: CHECK DDR STATUS */ + /* .. FINISH: DDR INITIALIZATION */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_mio_init_data_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: OCM REMAPPING */ + /* .. VREF_EN = 0x1 */ + /* .. ==> 0XF8000B00[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. CLK_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. SRSTN_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U), + /* .. FINISH: OCM REMAPPING */ + /* .. START: DDRIOB SETTINGS */ + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B40[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B40[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B40[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B40[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B40[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B44[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B44[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B44[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B44[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B44[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B48[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B48[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B48[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B48[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B48[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B48[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B48[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B50[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B50[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B50[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B50[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B50[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B50[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B50[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B54[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B54[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B54[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B54[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B54[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B54[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B54[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B58[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B58[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B58[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B58[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B58[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x3 */ + /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */ + /* .. SLEW_N = 0x3 */ + /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B60[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B60[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B60[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B64[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B64[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B64[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B68[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B68[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B68[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + /* .. VREF_INT_EN = 0x0 */ + /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. VREF_SEL = 0x0 */ + /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */ + /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */ + /* .. VREF_EXT_EN = 0x3 */ + /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. REFIO_EN = 0x1 */ + /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. REFIO_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DRST_B_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. CKE_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */ + /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U), + /* .. .. START: ASSERT RESET */ + /* .. .. RESET = 1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U), + /* .. .. FINISH: ASSERT RESET */ + /* .. .. START: DEASSERT RESET */ + /* .. .. RESET = 0 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + /* .. .. FINISH: DEASSERT RESET */ + /* .. .. RESET = 0x1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. ENABLE = 0x1 */ + /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. VRP_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. VRN_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. VRP_OUT = 0x0 */ + /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. NREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. .. NREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */ + /* .. .. NREF_OPT4 = 0x1 */ + /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */ + /* .. .. PREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */ + /* .. .. PREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */ + /* .. .. UPDATE_CONTROL = 0x0 */ + /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. INIT_COMPLETE = 0x0 */ + /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. TST_CLK = 0x0 */ + /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. TST_HLN = 0x0 */ + /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. TST_HLP = 0x0 */ + /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. TST_RST = 0x0 */ + /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. INT_DCI_EN = 0x0 */ + /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U), + /* .. FINISH: DDRIOB SETTINGS */ + /* .. START: MIO PROGRAMMING */ + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000704[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000704[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000704[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000704[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000704[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000704[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000704[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000704[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000704[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000708[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000708[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000708[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000708[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000708[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000708[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000708[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000708[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000708[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800070C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800070C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800070C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800070C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800070C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800070C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800070C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800070C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800070C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000710[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000710[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000710[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000710[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000710[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000710[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000710[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000710[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000710[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000714[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000714[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000714[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000714[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000714[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000714[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000714[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000714[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000714[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000718[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000718[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000718[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000718[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000718[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000718[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000718[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000718[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000718[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000740[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000740[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000740[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000740[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000740[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000740[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000740[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000740[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000740[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000744[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000744[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000744[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000744[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000744[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000744[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000744[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000744[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000744[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000748[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000748[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000748[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000748[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000748[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000748[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000748[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000748[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000748[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800074C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800074C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800074C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800074C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800074C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800074C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800074C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800074C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF800074C[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000750[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000750[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000750[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000750[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000750[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000750[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000750[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000750[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000750[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000754[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000754[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000754[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000754[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000754[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000754[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000754[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000754[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000754[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000758[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000758[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000758[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000758[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000758[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000758[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000758[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000758[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000758[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800075C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800075C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800075C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800075C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800075C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800075C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800075C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800075C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800075C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000760[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000760[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000760[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000760[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000760[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000760[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000760[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000760[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000760[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000764[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000764[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000764[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000764[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000764[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000764[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000764[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000764[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000764[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000768[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000768[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000768[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000768[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000768[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000768[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000768[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000768[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000768[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800076C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800076C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800076C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800076C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800076C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800076C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800076C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800076C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800076C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000770[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000770[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000770[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000770[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000770[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000770[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000770[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000770[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000770[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000774[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000774[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000774[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000774[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000774[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000774[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000774[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000774[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000774[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000778[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000778[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000778[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000778[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000778[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000778[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000778[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000778[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000778[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800077C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800077C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800077C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800077C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800077C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800077C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800077C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800077C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800077C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000780[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000780[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000780[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000780[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000780[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000780[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000780[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000780[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000780[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000784[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000784[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000784[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000784[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000784[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000784[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000784[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000784[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000784[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000788[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000788[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000788[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000788[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000788[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000788[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000788[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000788[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000788[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800078C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800078C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800078C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800078C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800078C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800078C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800078C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800078C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800078C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000790[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000790[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000790[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000790[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000790[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000790[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000790[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000790[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000790[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000794[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000794[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000794[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000794[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000794[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000794[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000794[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000794[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000794[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000798[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000798[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000798[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000798[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000798[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000798[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000798[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000798[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000798[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800079C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800079C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800079C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800079C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800079C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800079C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800079C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800079C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800079C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A8[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A8[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007AC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007AC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007AC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007AC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007AC[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007AC[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007AC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007AC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007AC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007BC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007BC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007BC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007BC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C0[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007C4[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C4[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), + /* .. SDIO0_WP_SEL = 55 */ + /* .. ==> 0XF8000830[5:0] = 0x00000037U */ + /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */ + /* .. SDIO0_CD_SEL = 47 */ + /* .. ==> 0XF8000830[21:16] = 0x0000002FU */ + /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U), + /* .. FINISH: MIO PROGRAMMING */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* .. START: SRAM/NOR SET OPMODE */ + /* .. FINISH: SRAM/NOR SET OPMODE */ + /* .. START: UART REGISTERS */ + /* .. BDIV = 0x6 */ + /* .. ==> 0XE0001034[7:0] = 0x00000006U */ + /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ + /* .. */ + EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), + /* .. CD = 0x3e */ + /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. */ + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + /* .. STPBRK = 0x0 */ + /* .. ==> 0XE0001000[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. STTBRK = 0x0 */ + /* .. ==> 0XE0001000[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. RSTTO = 0x0 */ + /* .. ==> 0XE0001000[6:6] = 0x00000000U */ + /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. TXDIS = 0x0 */ + /* .. ==> 0XE0001000[5:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. TXEN = 0x1 */ + /* .. ==> 0XE0001000[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. RXDIS = 0x0 */ + /* .. ==> 0XE0001000[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. RXEN = 0x1 */ + /* .. ==> 0XE0001000[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. TXRES = 0x1 */ + /* .. ==> 0XE0001000[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. RXRES = 0x1 */ + /* .. ==> 0XE0001000[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. */ + EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), + /* .. IRMODE = 0x0 */ + /* .. ==> 0XE0001004[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. UCLKEN = 0x0 */ + /* .. ==> 0XE0001004[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. CHMODE = 0x0 */ + /* .. ==> 0XE0001004[9:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ + /* .. NBSTOP = 0x0 */ + /* .. ==> 0XE0001004[7:6] = 0x00000000U */ + /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. PAR = 0x4 */ + /* .. ==> 0XE0001004[5:3] = 0x00000004U */ + /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ + /* .. CHRL = 0x0 */ + /* .. ==> 0XE0001004[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. CLKS = 0x0 */ + /* .. ==> 0XE0001004[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), + /* .. FINISH: UART REGISTERS */ + /* .. START: TPIU WIDTH IN CASE OF EMIO */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0XC5ACCE55 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. .. START: TRACE CURRENT PORT SIZE */ + /* .. .. a = 2 */ + /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), + /* .. .. FINISH: TRACE CURRENT PORT SIZE */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0X0 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ + /* .. START: QSPI REGISTERS */ + /* .. Holdb_dr = 1 */ + /* .. ==> 0XE000D000[19:19] = 0x00000001U */ + /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. */ + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + /* .. FINISH: QSPI REGISTERS */ + /* .. START: PL POWER ON RESET REGISTERS */ + /* .. PCFG_POR_CNT_4K = 0 */ + /* .. ==> 0XF8007000[29:29] = 0x00000000U */ + /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + /* .. FINISH: PL POWER ON RESET REGISTERS */ + /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */ + /* .. .. START: NAND SET CYCLE */ + /* .. .. FINISH: NAND SET CYCLE */ + /* .. .. START: OPMODE */ + /* .. .. FINISH: OPMODE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: SRAM/NOR CS0 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS0 BASE ADDRESS */ + /* .. .. FINISH: NOR CS0 BASE ADDRESS */ + /* .. .. START: SRAM/NOR CS1 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS1 BASE ADDRESS */ + /* .. .. FINISH: NOR CS1 BASE ADDRESS */ + /* .. .. START: USB RESET */ + /* .. .. .. START: USB0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB0 RESET */ + /* .. .. .. START: USB1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB1 RESET */ + /* .. .. FINISH: USB RESET */ + /* .. .. START: ENET RESET */ + /* .. .. .. START: ENET0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET0 RESET */ + /* .. .. .. START: ENET1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET1 RESET */ + /* .. .. FINISH: ENET RESET */ + /* .. .. START: I2C RESET */ + /* .. .. .. START: I2C0 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C0 RESET */ + /* .. .. .. START: I2C1 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C1 RESET */ + /* .. .. FINISH: I2C RESET */ + /* .. .. START: NOR CHIP SELECT */ + /* .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. FINISH: NOR CHIP SELECT */ + /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_post_config_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: ENABLING LEVEL SHIFTER */ + /* .. USER_INP_ICT_EN_0 = 3 */ + /* .. ==> 0XF8000900[1:0] = 0x00000003U */ + /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */ + /* .. USER_INP_ICT_EN_1 = 3 */ + /* .. ==> 0XF8000900[3:2] = 0x00000003U */ + /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */ + /* .. */ + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + /* .. FINISH: ENABLING LEVEL SHIFTER */ + /* .. START: TPIU WIDTH IN CASE OF EMIO */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0XC5ACCE55 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. .. START: TRACE CURRENT PORT SIZE */ + /* .. .. a = 2 */ + /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), + /* .. .. FINISH: TRACE CURRENT PORT SIZE */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0X0 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ + /* .. START: FPGA RESETS TO 0 */ + /* .. reserved_3 = 0 */ + /* .. ==> 0XF8000240[31:25] = 0x00000000U */ + /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */ + /* .. FPGA_ACP_RST = 0 */ + /* .. ==> 0XF8000240[24:24] = 0x00000000U */ + /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. FPGA_AXDS3_RST = 0 */ + /* .. ==> 0XF8000240[23:23] = 0x00000000U */ + /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. FPGA_AXDS2_RST = 0 */ + /* .. ==> 0XF8000240[22:22] = 0x00000000U */ + /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. FPGA_AXDS1_RST = 0 */ + /* .. ==> 0XF8000240[21:21] = 0x00000000U */ + /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. FPGA_AXDS0_RST = 0 */ + /* .. ==> 0XF8000240[20:20] = 0x00000000U */ + /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. reserved_2 = 0 */ + /* .. ==> 0XF8000240[19:18] = 0x00000000U */ + /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. FSSW1_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[17:17] = 0x00000000U */ + /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. FSSW0_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[16:16] = 0x00000000U */ + /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. reserved_1 = 0 */ + /* .. ==> 0XF8000240[15:14] = 0x00000000U */ + /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ + /* .. FPGA_FMSW1_RST = 0 */ + /* .. ==> 0XF8000240[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. FPGA_FMSW0_RST = 0 */ + /* .. ==> 0XF8000240[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. FPGA_DMA3_RST = 0 */ + /* .. ==> 0XF8000240[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. FPGA_DMA2_RST = 0 */ + /* .. ==> 0XF8000240[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. FPGA_DMA1_RST = 0 */ + /* .. ==> 0XF8000240[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. FPGA_DMA0_RST = 0 */ + /* .. ==> 0XF8000240[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. reserved = 0 */ + /* .. ==> 0XF8000240[7:4] = 0x00000000U */ + /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. FPGA3_OUT_RST = 0 */ + /* .. ==> 0XF8000240[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. FPGA2_OUT_RST = 0 */ + /* .. ==> 0XF8000240[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. FPGA1_OUT_RST = 0 */ + /* .. ==> 0XF8000240[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. FPGA0_OUT_RST = 0 */ + /* .. ==> 0XF8000240[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + /* .. FINISH: FPGA RESETS TO 0 */ + /* .. START: AFI REGISTERS */ + /* .. .. START: AFI0 REGISTERS */ + /* .. .. FINISH: AFI0 REGISTERS */ + /* .. .. START: AFI1 REGISTERS */ + /* .. .. FINISH: AFI1 REGISTERS */ + /* .. .. START: AFI2 REGISTERS */ + /* .. .. FINISH: AFI2 REGISTERS */ + /* .. .. START: AFI3 REGISTERS */ + /* .. .. FINISH: AFI3 REGISTERS */ + /* .. FINISH: AFI REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_debug_1_0[] = { + /* START: top */ + /* .. START: CROSS TRIGGER CONFIGURATIONS */ + /* .. .. START: UNLOCKING CTI REGISTERS */ + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: UNLOCKING CTI REGISTERS */ + /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char *getPS7MessageInfo(unsigned key) +{ + char *err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: + err_msg = "PS7 initialization successful"; + break; + case PS7_INIT_CORRUPT: + err_msg = "PS7 init Data Corrupted"; + break; + case PS7_INIT_TIMEOUT: + err_msg = "PS7 init mask poll timeout"; + break; + case PS7_POLL_FAILED_DDR_INIT: + err_msg = "Mask Poll failed for DDR Init"; + break; + case PS7_POLL_FAILED_DMA: + err_msg = "Mask Poll failed for PLL Init"; + break; + case PS7_POLL_FAILED_PLL: + err_msg = "Mask Poll failed for DMA done bit"; + break; + default: + err_msg = "Undefined error status"; + break; + } + + return err_msg; +} + +unsigned long ps7GetSiliconVersion(void) +{ + /* Read PS version from MCTRL register [31:28] */ + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long *)0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write(unsigned long add, unsigned long mask, unsigned long val) +{ + unsigned long *addr = (unsigned long *)add; + *addr = (val & mask) | (*addr & ~mask); +} + +int mask_poll(unsigned long add, unsigned long mask) +{ + volatile unsigned long *addr = (volatile unsigned long *)add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) + return -1; + i++; + } + return 1; +} + +unsigned long mask_read(unsigned long add, unsigned long mask) +{ + unsigned long *addr = (unsigned long *)add; + unsigned long val = (*addr & mask); + return val; +} + +int ps7_config(unsigned long *ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; /* current instruction .. */ + unsigned long args[16]; /* no opcode has so many args ... */ + int numargs; /* number of arguments of this instruction */ + int j; /* general purpose index */ + + volatile unsigned long *addr; /* some variable to make code readable */ + unsigned long val, mask; /* some variable to make code readable */ + + int finish = -1; /* loop while this is negative ! */ + int i = 0; /* Timeout variable */ + + while (finish < 0) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for (j = 0; j < numargs; j++) + args[j] = ptr[j + 1]; + ptr += numargs + 1; + + switch (opcode) { + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long *)args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long *)args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long *)args[0]; + mask = args[1]; + val = args[2]; + *addr = (val & mask) | (*addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long *)args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long *)args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) + ; + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int ps7_post_config(void) +{ + /* Get the PS_VERSION on run time */ + unsigned long si_ver = ps7GetSiliconVersion(); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config(ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config(ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } else { + ret = ps7_config(ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } + return PS7_INIT_SUCCESS; +} + +int ps7_debug(void) +{ + /* Get the PS_VERSION on run time */ + unsigned long si_ver = ps7GetSiliconVersion(); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config(ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config(ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } else { + ret = ps7_config(ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } + return PS7_INIT_SUCCESS; +} + +int ps7_init(void) +{ + /* Get the PS_VERSION on run time */ + unsigned long si_ver = ps7GetSiliconVersion(); + int ret; + /*int pcw_ver = 0; */ + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + /*pcw_ver = 1; */ + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + /*pcw_ver = 2; */ + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + /*pcw_ver = 3; */ + } + + /* MIO init */ + ret = ps7_config(ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + /* PLL init */ + ret = ps7_config(ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + /* Clock init */ + ret = ps7_config(ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + /* DDR init */ + ret = ps7_config(ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + /* Peripherals init */ + ret = ps7_config(ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + return PS7_INIT_SUCCESS; +} + +/* For delay calculation using global timer */ + +/* start timer */ +void perf_start_clock(void) +{ + *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | /* Timer Enable */ + (1 << 3) | /* Auto-increment */ + (0 << 8) /* Pre-scale */ + ); +} + +/* stop timer and reset timer count regs */ +void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + /* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */ + return APU_FREQ * delay / (2 * 1000); +} + +/* stop timer */ +void perf_disable_clock(void) +{ + *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer(void) +{ + perf_reset_clock(); + perf_start_clock(); +} diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h new file mode 100644 index 0000000..62b8a58 --- /dev/null +++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*typedef unsigned int u32; */ + +/** do we need to make this name more unique ? **/ +/*extern u32 ps7_init_data[]; */ +extern unsigned long *ps7_ddr_init_data; +extern unsigned long *ps7_mio_init_data; +extern unsigned long *ps7_pll_init_data; +extern unsigned long *ps7_clock_init_data; +extern unsigned long *ps7_peripherals_init_data; + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0) +#define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr +#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val +#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val +#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask +#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */ +#define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */ +#define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */ +#define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */ +#define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */ +#define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */ + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 650000000 +#define DDR_FREQ 525000000 +#define DCI_FREQ 10096154 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 50000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 108333336 +#define WDT_FREQ 108333336 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 100000000 +#define FPGA1_FREQ 175000000 +#define FPGA2_FREQ 12264151 +#define FPGA3_FREQ 100000000 + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config(unsigned long *); +int ps7_init(void); +int ps7_post_config(void); +int ps7_debug(void); +char *getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(void); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index d105bb4..2cf4712 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -65,53 +65,6 @@ void scsi_init(void) } #endif -int board_eth_init(bd_t *bis) -{ - u32 ret = 0; - -#if defined(CONFIG_ZYNQ_GEM) -# if defined(CONFIG_ZYNQ_GEM0) - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, - CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); -# endif -# if defined(CONFIG_ZYNQ_GEM1) - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, - CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); -# endif -# if defined(CONFIG_ZYNQ_GEM2) - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2, - CONFIG_ZYNQ_GEM_PHY_ADDR2, 0); -# endif -# if defined(CONFIG_ZYNQ_GEM3) - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3, - CONFIG_ZYNQ_GEM_PHY_ADDR3, 0); -# endif -#endif - return ret; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bd) -{ - int ret = 0; - - u32 ver = zynqmp_get_silicon_version(); - - if (ver != ZYNQMP_CSU_VERSION_VELOCE) { -#if defined(CONFIG_ZYNQ_SDHCI) -# if defined(CONFIG_ZYNQ_SDHCI0) - ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); -# endif -# if defined(CONFIG_ZYNQ_SDHCI1) - ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); -# endif -#endif - } - - return ret; -} -#endif - int board_late_init(void) { u32 reg = 0; diff --git a/board/zyxel/nsa310s/Kconfig b/board/zyxel/nsa310s/Kconfig new file mode 100644 index 0000000..77e734d --- /dev/null +++ b/board/zyxel/nsa310s/Kconfig @@ -0,0 +1,20 @@ +# +# Copyright (C) 2015 +# Gerald Kerma <dreagle@doukki.net> +# Tony Dinh <mibodhi@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if TARGET_NSA310S + +config SYS_BOARD + default "nsa310s" + +config SYS_VENDOR + default "zyxel" + +config SYS_CONFIG_NAME + default "nsa310s" + +endif diff --git a/board/zyxel/nsa310s/MAINTAINERS b/board/zyxel/nsa310s/MAINTAINERS new file mode 100644 index 0000000..d153758 --- /dev/null +++ b/board/zyxel/nsa310s/MAINTAINERS @@ -0,0 +1,8 @@ +NSA310S BOARD +M: Gerald Kerma <dreagle@doukki.net> +M: Tony Dinh <mibodhi@gmail.com> +M: Luka Perkov <luka.perkov@sartura.hr> +S: Maintained +F: board/zyxel/nsa310s/ +F: include/configs/nsa310s.h +F: configs/nsa310s_defconfig diff --git a/board/zyxel/nsa310s/Makefile b/board/zyxel/nsa310s/Makefile new file mode 100644 index 0000000..43cdb86 --- /dev/null +++ b/board/zyxel/nsa310s/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2015 +# Gerald Kerma <dreagle@doukki.net> +# Tony Dinh <mibodhi@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := nsa310s.o diff --git a/board/zyxel/nsa310s/kwbimage.cfg b/board/zyxel/nsa310s/kwbimage.cfg new file mode 100644 index 0000000..e8f4b8a --- /dev/null +++ b/board/zyxel/nsa310s/kwbimage.cfg @@ -0,0 +1,43 @@ +# +# Copyright (C) 2015 +# Gerald Kerma <dreagle@doukki.net> +# Tony Dinh <mibodhi@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer to doc/README.kwbimage for more details about how-to +# configure and create kirkwood boot images. +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +DATA 0xFFD01400 0x43010c30 +DATA 0xFFD01404 0x39543000 +DATA 0xFFD01408 0x22125451 +DATA 0xFFD0140C 0x00000833 +DATA 0xFFD01410 0x0000000C +DATA 0xFFD01414 0x00000000 +DATA 0xFFD01418 0x00000000 +DATA 0xFFD0141C 0x00000652 +DATA 0xFFD01420 0x00000004 +DATA 0xFFD01424 0x0000F17F +DATA 0xFFD01428 0x00085520 +DATA 0xFFD0147c 0x00008552 +DATA 0xFFD01504 0x0FFFFFF1 +DATA 0xFFD01508 0x10000000 +DATA 0xFFD0150C 0x00000000 +DATA 0xFFD01514 0x00000000 +DATA 0xFFD0151C 0x00000000 +DATA 0xFFD01494 0x00010000 +DATA 0xFFD01498 0x00000000 +DATA 0xFFD0149C 0x0000E403 +DATA 0xFFD01480 0x00000001 +DATA 0xFFD20134 0x66666666 +DATA 0xFFD20138 0x66666666 +DATA 0x0 0x0 diff --git a/board/zyxel/nsa310s/nsa310s.c b/board/zyxel/nsa310s/nsa310s.c new file mode 100644 index 0000000..aab33cf --- /dev/null +++ b/board/zyxel/nsa310s/nsa310s.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2015 + * Gerald Kerma <dreagle@doukki.net> + * Tony Dinh <mibodhi@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include <asm/io.h> +#include "nsa310s.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH, + NSA310S_OE_LOW, NSA310S_OE_HIGH); + + /* (all LEDs & power off active high) */ + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, + MPP13_GPIO, + MPP14_GPIO, + MPP15_GPIO, + MPP16_GPIO, + MPP17_GPIO, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ + u16 reg; + u16 phyaddr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* read PHY dev address */ + if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) { + printf("could not read PHY dev address\n"); + return; + } + + /* set RGMII delay */ + miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG); + miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, ®); + reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL); + miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg); + miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0); + + /* reset PHY */ + if (miiphy_reset(name, phyaddr)) + return; + + /* + * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318) + * and has an MCU attached to the LED[2] via tristate interrupt + */ + + /* switch to LED register page */ + miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG); + /* read out LED polarity register */ + miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, ®); + /* clear 4, set 5 - LED2 low, tri-state */ + reg &= ~(MV88E1318_LED2_4); + reg |= (MV88E1318_LED2_5); + /* write back LED polarity register */ + miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg); + /* jump back to page 0, per the PHY chip documenation. */ + miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0); + + /* set PHY back to auto-negotiation mode */ + miiphy_write(name, phyaddr, 0x4, 0x1e1); + miiphy_write(name, phyaddr, 0x9, 0x300); + /* downshift */ + miiphy_write(name, phyaddr, 0x10, 0x3860); + miiphy_write(name, phyaddr, 0x0, 0x9140); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/zyxel/nsa310s/nsa310s.h b/board/zyxel/nsa310s/nsa310s.h new file mode 100644 index 0000000..1ea1105 --- /dev/null +++ b/board/zyxel/nsa310s/nsa310s.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2015 + * Gerald Kerma <dreagle@doukki.net> + * Tony Dinh <mibodhi@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __NSA310S_H +#define __NSA310S_H + +/* low GPIO's */ +#define HDD1_GREEN_LED (1 << 16) +#define HDD1_RED_LED (1 << 13) +#define USB_GREEN_LED (1 << 15) +#define USB_POWER (1 << 21) +#define SYS_GREEN_LED (1 << 28) +#define SYS_ORANGE_LED (1 << 29) + +#define COPY_GREEN_LED (1 << 22) +#define COPY_RED_LED (1 << 23) + +#define PIN_USB_GREEN_LED 15 +#define PIN_USB_POWER 21 + +#define NSA310S_OE_LOW (~(0)) +#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER) + +/* high GPIO's */ +#define HDD2_GREEN_LED (1 << 2) +#define HDD2_POWER (1 << 1) + +#define NSA310S_OE_HIGH (~(0)) +#define NSA310S_VAL_HIGH (HDD2_POWER) + +/* PHY related */ +#define MV88E1318_PGADR_REG 22 +#define MV88E1318_MAC_CTRL_PG 2 +#define MV88E1318_MAC_CTRL_REG 21 +#define MV88E1318_RGMII_TX_CTRL (1 << 4) +#define MV88E1318_RGMII_RX_CTRL (1 << 5) +#define MV88E1318_LED_PG 3 +#define MV88E1318_LED_POL_REG 17 +#define MV88E1318_LED2_4 (1 << 4) +#define MV88E1318_LED2_5 (1 << 5) + +#endif /* __NSA310S_H */ diff --git a/common/Makefile b/common/Makefile index d8dc892..2a1d9f8 100644 --- a/common/Makefile +++ b/common/Makefile @@ -227,6 +227,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o +obj-$(CONFIG_SPL_OF_TRANSLATE) += fdt_support.o ifdef CONFIG_SPL_USB_HOST_SUPPORT obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o obj-$(CONFIG_USB_STORAGE) += usb_storage.o diff --git a/common/board_f.c b/common/board_f.c index b035c90..8094ac4 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -317,6 +317,15 @@ __weak ulong board_get_usable_ram_top(ulong total_size) return gd->ram_top; } +__weak phys_size_t board_reserve_ram_top(phys_size_t ram_size) +{ +#ifdef CONFIG_SYS_MEM_TOP_HIDE + return ram_size - CONFIG_SYS_MEM_TOP_HIDE; +#else + return ram_size; +#endif +} + static int setup_dest_addr(void) { debug("Monitor len: %08lX\n", gd->mon_len); @@ -324,19 +333,26 @@ static int setup_dest_addr(void) * Ram is setup, size stored in gd !! */ debug("Ram size: %08lX\n", (ulong)gd->ram_size); -#if defined(CONFIG_SYS_MEM_TOP_HIDE) +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + /* Reserve memory for secure MMU tables, and/or security monitor */ + gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + /* + * Record secure memory location. Need recalcuate if memory splits + * into banks, or the ram base is not zero. + */ + gd->secure_ram = gd->ram_size; +#endif /* * Subtract specified amount of memory to hide so that it won't * get "touched" at all by U-Boot. By fixing up gd->ram_size * the Linux kernel should now get passed the now "corrected" - * memory size and won't touch it either. This should work - * for arch/ppc and arch/powerpc. Only Linux board ports in - * arch/powerpc with bootwrapper support, that recalculate the - * memory size from the SDRAM controller setup will have to - * get fixed. + * memory size and won't touch it either. This has been used + * by arch/powerpc exclusively. Now ARMv8 takes advantage of + * thie mechanism. If memory is split into banks, addresses + * need to be calculated. */ - gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; -#endif + gd->ram_size = board_reserve_ram_top(gd->ram_size); + #ifdef CONFIG_SYS_SDRAM_BASE gd->ram_top = CONFIG_SYS_SDRAM_BASE; #endif @@ -357,6 +373,20 @@ static int setup_dest_addr(void) return 0; } +#if defined(CONFIG_SPARC) +static int reserve_prom(void) +{ + /* defined in arch/sparc/cpu/leon?/prom.c */ + extern void *__prom_start_reloc; + int size = 8192; /* page table = 2k, prom = 6k */ + gd->relocaddr -= size; + __prom_start_reloc = map_sysmem(gd->relocaddr + 2048, size - 2048); + debug("Reserving %dk for PROM and page table at %08lx\n", size, + gd->relocaddr); + return 0; +} +#endif + #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) static int reserve_logbuffer(void) { @@ -510,6 +540,7 @@ static int reserve_global_data(void) static int reserve_fdt(void) { +#ifndef CONFIG_OF_EMBED /* * If the device tree is sitting immediately above our image then we * must relocate it. If it is embedded in the data section, then it @@ -523,6 +554,7 @@ static int reserve_fdt(void) debug("Reserving %lu Bytes for FDT at: %08lx\n", gd->fdt_size, gd->start_addr_sp); } +#endif return 0; } @@ -660,12 +692,14 @@ static int setup_dram_config(void) static int reloc_fdt(void) { +#ifndef CONFIG_OF_EMBED if (gd->flags & GD_FLG_SKIP_RELOC) return 0; if (gd->new_fdt) { memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); gd->fdt_blob = gd->new_fdt; } +#endif return 0; } @@ -807,8 +841,9 @@ static init_fnc_t init_sequence_f[] = { /* TODO: can we rename this to timer_init()? */ init_timebase, #endif -#if defined(CONFIG_X86) || defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \ - defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) +#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \ + defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \ + defined(CONFIG_SPARC) timer_init, /* initialize timer */ #endif #ifdef CONFIG_SYS_ALLOC_DPRAM @@ -908,6 +943,9 @@ static init_fnc_t init_sequence_f[] = { /* Blackfin u-boot monitor should be on top of the ram */ reserve_uboot, #endif +#if defined(CONFIG_SPARC) + reserve_prom, +#endif #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) reserve_logbuffer, #endif diff --git a/common/board_r.c b/common/board_r.c index f7118e8..75ee43e 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -15,6 +15,7 @@ #if defined(CONFIG_CMD_BEDBUG) #include <bedbug/type.h> #endif +#include <command.h> #include <console.h> #ifdef CONFIG_HAS_DATAFLASH #include <dataflash.h> @@ -66,6 +67,10 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_SPARC) +extern int prom_init(void); +#endif + ulong monitor_flash_len; __weak int board_flash_wp_on(void) @@ -109,7 +114,6 @@ static int initr_reloc(void) { /* tell others: relocation done */ gd->flags |= GD_FLG_RELOC | GD_FLG_FULL_MALLOC_INIT; - bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r"); return 0; } @@ -165,6 +169,14 @@ static int initr_reloc_global_data(void) */ gd->env_addr += gd->relocaddr - CONFIG_SYS_MONITOR_BASE; #endif +#ifdef CONFIG_OF_EMBED + /* + * The fdt_blob needs to be moved to new relocation address + * incase of FDT blob is embedded with in image + */ + gd->fdt_blob += gd->reloc_off; +#endif + return 0; } @@ -310,6 +322,14 @@ static int initr_dm(void) } #endif +static int initr_bootstage(void) +{ + /* We cannot do this before initr_dm() */ + bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r"); + + return 0; +} + __weak int power_init_board(void) { return 0; @@ -748,6 +768,7 @@ init_fnc_t init_sequence_r[] = { #ifdef CONFIG_DM initr_dm, #endif + initr_bootstage, #if defined(CONFIG_ARM) || defined(CONFIG_NDS32) board_init, /* Setup chipselects */ #endif @@ -805,7 +826,8 @@ init_fnc_t init_sequence_r[] = { initr_flash, #endif INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86) +#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86) || \ + defined(CONFIG_SPARC) /* initialize higher level parts of CPU like time base and timers */ cpu_init_r, #endif @@ -925,6 +947,9 @@ init_fnc_t init_sequence_r[] = { #ifdef CONFIG_PS2KBD initr_kbd, #endif +#if defined(CONFIG_SPARC) + prom_init, +#endif run_main_loop, }; diff --git a/common/bootm_os.c b/common/bootm_os.c index 72477f0..cb83f4a 100644 --- a/common/bootm_os.c +++ b/common/bootm_os.c @@ -288,6 +288,8 @@ void do_bootvx_fdt(bootm_headers_t *images) if (ret) return; + fdt_fixup_ethernet(*of_flat_tree); + ret = fdt_add_subnode(*of_flat_tree, 0, "chosen"); if ((ret >= 0 || ret == -FDT_ERR_EXISTS)) { bootline = getenv("bootargs"); diff --git a/common/cli_hush.c b/common/cli_hush.c index a7cac4f..2fbfdbe 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -2162,7 +2162,7 @@ int set_local_var(const char *s, int flg_export) * NAME=VALUE format. So the first order of business is to * split 's' on the '=' into 'name' and 'value' */ value = strchr(name, '='); - if (value == NULL && ++value == NULL) { + if (value == NULL || *(value + 1) == 0) { free(name); return -1; } @@ -2471,11 +2471,16 @@ static int done_word(o_string *dest, struct p_context *ctx) } argc = ++child->argc; child->argv = realloc(child->argv, (argc+1)*sizeof(*child->argv)); - if (child->argv == NULL) return 1; + if (child->argv == NULL) { + free(str); + return 1; + } child->argv_nonnull = realloc(child->argv_nonnull, (argc+1)*sizeof(*child->argv_nonnull)); - if (child->argv_nonnull == NULL) + if (child->argv_nonnull == NULL) { + free(str); return 1; + } child->argv[argc-1]=str; child->argv_nonnull[argc-1] = dest->nonnull; child->argv[argc]=NULL; @@ -3503,9 +3508,9 @@ static char *insert_var_value_sub(char *inp, int tag_subst) char *p, *p1, *res_str = NULL; while ((p = strchr(inp, SPECIAL_VAR_SYMBOL))) { - /* check the beginning of the string for normal charachters */ + /* check the beginning of the string for normal characters */ if (p != inp) { - /* copy any charachters to the result string */ + /* copy any characters to the result string */ len = p - inp; res_str = xrealloc(res_str, (res_str_len + len)); strncpy((res_str + res_str_len), inp, len); diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index adda55a..deed6d8 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -382,6 +382,12 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, print_num("-> size", bd->bi_dram[i].size); } +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + if (gd->secure_ram & MEM_RESERVE_SECURE_SECURED) { + print_num("Secure ram", + gd->secure_ram & MEM_RESERVE_SECURE_ADDR_MASK); + } +#endif #if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH) print_eths(); #endif diff --git a/common/cmd_blob.c b/common/cmd_blob.c index d3f22a1..ac8b268 100644 --- a/common/cmd_blob.c +++ b/common/cmd_blob.c @@ -73,9 +73,9 @@ static int do_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) len = simple_strtoul(argv[4], NULL, 16); key_addr = simple_strtoul(argv[5], NULL, 16); - km_ptr = (uint8_t *)key_addr; - src_ptr = (uint8_t *)src_addr; - dst_ptr = (uint8_t *)dst_addr; + km_ptr = (uint8_t *)(uintptr_t)key_addr; + src_ptr = (uint8_t *)(uintptr_t)src_addr; + dst_ptr = (uint8_t *)(uintptr_t)dst_addr; if (enc) ret = blob_encap(km_ptr, src_ptr, dst_ptr, len); diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c index e9904cd..571240a 100644 --- a/common/cmd_eeprom.c +++ b/common/cmd_eeprom.c @@ -25,404 +25,241 @@ #include <command.h> #include <i2c.h> -extern void eeprom_init (void); -extern int eeprom_read (unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt); -extern int eeprom_write (unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt); -#if defined(CONFIG_SYS_EEPROM_WREN) -extern int eeprom_write_enable (unsigned dev_addr, int state); +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 50000 #endif - -#if defined(CONFIG_SYS_EEPROM_X40430) - /* Maximum number of times to poll for acknowledge after write */ -#define MAX_ACKNOWLEDGE_POLLS 10 +#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 0 #endif -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_CMD_EEPROM) -static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - const char *const fmt = - "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... "; - -#if defined(CONFIG_SYS_I2C_MULTI_EEPROMS) - if (argc == 6) { - ulong dev_addr = simple_strtoul (argv[2], NULL, 16); - ulong addr = simple_strtoul (argv[3], NULL, 16); - ulong off = simple_strtoul (argv[4], NULL, 16); - ulong cnt = simple_strtoul (argv[5], NULL, 16); -#else - if (argc == 5) { - ulong dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR; - ulong addr = simple_strtoul (argv[2], NULL, 16); - ulong off = simple_strtoul (argv[3], NULL, 16); - ulong cnt = simple_strtoul (argv[4], NULL, 16); -#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */ - -# if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C) - eeprom_init (); -# endif /* !CONFIG_SPI */ - - if (strcmp (argv[1], "read") == 0) { - int rcode; - - printf (fmt, dev_addr, argv[1], addr, off, cnt); - - rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt); - - puts ("done\n"); - return rcode; - } else if (strcmp (argv[1], "write") == 0) { - int rcode; - - printf (fmt, dev_addr, argv[1], addr, off, cnt); - - rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt); - - puts ("done\n"); - return rcode; - } - } - - return CMD_RET_USAGE; -} +#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_BITS +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 8 #endif -/*----------------------------------------------------------------------- - * +#define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS) +#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1)) + +/* * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM. * * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is * 0x00000nxx for EEPROM address selectors and page number at n. */ - #if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C) -#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1 || CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2 +#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || \ + (CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1) || \ + (CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2) #error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2 #endif #endif -int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt) +__weak int eeprom_write_enable(unsigned dev_addr, int state) { - unsigned end = offset + cnt; - unsigned blk_off; - int rcode = 0; + return 0; +} - /* Read data until done or would cross a page boundary. - * We must write the address again when changing pages - * because the next page may be in a different device. - */ - while (offset < end) { - unsigned alen, len; -#if !defined(CONFIG_SYS_I2C_FRAM) - unsigned maxlen; +void eeprom_init(int bus) +{ + /* SPI EEPROM */ +#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) + spi_init_f(); #endif -#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X) - uchar addr[2]; + /* I2C EEPROM */ +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) +#if defined(CONFIG_SYS_I2C) + if (bus >= 0) + i2c_set_bus_num(bus); +#endif + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif +} - blk_off = offset & 0xFF; /* block offset */ +static int eeprom_addr(unsigned dev_addr, unsigned offset, uchar *addr) +{ + unsigned blk_off; + int alen; - addr[0] = offset >> 8; /* block number */ - addr[1] = blk_off; /* block offset */ - alen = 2; + blk_off = offset & 0xff; /* block offset */ +#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 + addr[0] = offset >> 8; /* block number */ + addr[1] = blk_off; /* block offset */ + alen = 2; #else - uchar addr[3]; - - blk_off = offset & 0xFF; /* block offset */ - - addr[0] = offset >> 16; /* block number */ - addr[1] = offset >> 8; /* upper address octet */ - addr[2] = blk_off; /* lower address octet */ - alen = 3; -#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */ - - addr[0] |= dev_addr; /* insert device address */ + addr[0] = offset >> 16; /* block number */ + addr[1] = offset >> 8; /* upper address octet */ + addr[2] = blk_off; /* lower address octet */ + alen = 3; +#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN */ - len = end - offset; + addr[0] |= dev_addr; /* insert device address */ - /* - * For a FRAM device there is no limit on the number of the - * bytes that can be ccessed with the single read or write - * operation. - */ -#if !defined(CONFIG_SYS_I2C_FRAM) - maxlen = 0x100 - blk_off; - if (maxlen > I2C_RXTX_LEN) - maxlen = I2C_RXTX_LEN; - if (len > maxlen) - len = maxlen; -#endif - -#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) - spi_read (addr, alen, buffer, len); -#else -#if defined(CONFIG_SYS_I2C_EEPROM_BUS) - i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS); -#endif - if (i2c_read(addr[0], offset, alen - 1, buffer, len)) - rcode = 1; -#endif - buffer += len; - offset += len; - } - - return rcode; + return alen; } -/*----------------------------------------------------------------------- - * - * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is - * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM. - * - * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is - * 0x00000nxx for EEPROM address selectors and page number at n. - */ - -int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt) +static int eeprom_len(unsigned offset, unsigned end) { - unsigned end = offset + cnt; - unsigned blk_off; - int rcode = 0; - -#if defined(CONFIG_SYS_EEPROM_X40430) - uchar contr_r_addr[2]; - uchar addr_void[2]; - uchar contr_reg[2]; - uchar ctrl_reg_v; - int i; -#endif + unsigned len = end - offset; -#if defined(CONFIG_SYS_EEPROM_WREN) - eeprom_write_enable (dev_addr,1); -#endif - /* Write data until done or would cross a write page boundary. - * We must write the address again when changing pages - * because the address counter only increments within a page. + /* + * For a FRAM device there is no limit on the number of the + * bytes that can be ccessed with the single read or write + * operation. */ - - while (offset < end) { - unsigned alen, len; #if !defined(CONFIG_SYS_I2C_FRAM) - unsigned maxlen; -#endif + unsigned blk_off = offset & 0xff; + unsigned maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off); -#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X) - uchar addr[2]; + if (maxlen > I2C_RXTX_LEN) + maxlen = I2C_RXTX_LEN; - blk_off = offset & 0xFF; /* block offset */ - - addr[0] = offset >> 8; /* block number */ - addr[1] = blk_off; /* block offset */ - alen = 2; -#else - uchar addr[3]; + if (len > maxlen) + len = maxlen; +#endif - blk_off = offset & 0xFF; /* block offset */ + return len; +} - addr[0] = offset >> 16; /* block number */ - addr[1] = offset >> 8; /* upper address octet */ - addr[2] = blk_off; /* lower address octet */ - alen = 3; -#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */ +static int eeprom_rw_block(unsigned offset, uchar *addr, unsigned alen, + uchar *buffer, unsigned len, bool read) +{ + int ret = 0; - addr[0] |= dev_addr; /* insert device address */ + /* SPI */ +#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) + if (read) + spi_read(addr, alen, buffer, len); + else + spi_write(addr, alen, buffer, len); +#else /* I2C */ - len = end - offset; +#if defined(CONFIG_SYS_I2C_EEPROM_BUS) + i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS); +#endif - /* - * For a FRAM device there is no limit on the number of the - * bytes that can be accessed with the single read or write - * operation. - */ -#if !defined(CONFIG_SYS_I2C_FRAM) + if (read) + ret = i2c_read(addr[0], offset, alen - 1, buffer, len); + else + ret = i2c_write(addr[0], offset, alen - 1, buffer, len); -#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_BITS) + if (ret) + ret = 1; +#endif + return ret; +} -#define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS) -#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1)) +static int eeprom_rw(unsigned dev_addr, unsigned offset, uchar *buffer, + unsigned cnt, bool read) +{ + unsigned end = offset + cnt; + unsigned alen, len; + int rcode = 0; + uchar addr[3]; - maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off); -#else - maxlen = 0x100 - blk_off; -#endif - if (maxlen > I2C_RXTX_LEN) - maxlen = I2C_RXTX_LEN; + while (offset < end) { + alen = eeprom_addr(dev_addr, offset, addr); - if (len > maxlen) - len = maxlen; -#endif + len = eeprom_len(offset, end); -#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) - spi_write (addr, alen, buffer, len); -#else -#if defined(CONFIG_SYS_EEPROM_X40430) - /* Get the value of the control register. - * Set current address (internal pointer in the x40430) - * to 0x1ff. - */ - contr_r_addr[0] = 9; - contr_r_addr[1] = 0xff; - addr_void[0] = 0; - addr_void[1] = addr[1]; -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR - contr_r_addr[0] |= CONFIG_SYS_I2C_EEPROM_ADDR; - addr_void[0] |= CONFIG_SYS_I2C_EEPROM_ADDR; -#endif - contr_reg[0] = 0xff; - if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) { - rcode = 1; - } - ctrl_reg_v = contr_reg[0]; - - /* Are any of the eeprom blocks write protected? - */ - if (ctrl_reg_v & 0x18) { - ctrl_reg_v &= ~0x18; /* reset block protect bits */ - ctrl_reg_v |= 0x02; /* set write enable latch */ - ctrl_reg_v &= ~0x04; /* clear RWEL */ - - /* Set write enable latch. - */ - contr_reg[0] = 0x02; - if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) { - rcode = 1; - } - - /* Set register write enable latch. - */ - contr_reg[0] = 0x06; - if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) { - rcode = 1; - } - - /* Modify ctrl register. - */ - contr_reg[0] = ctrl_reg_v; - if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) { - rcode = 1; - } - - /* The write (above) is an operation on NV memory. - * These can take some time (~5ms), and the device - * will not respond to further I2C messages till - * it's completed the write. - * So poll device for an I2C acknowledge. - * When we get one we know we can continue with other - * operations. - */ - contr_reg[0] = 0; - for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) { - if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0) - break; /* got ack */ -#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS) - udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); -#endif - } - if (i == MAX_ACKNOWLEDGE_POLLS) { - puts ("EEPROM poll acknowledge failed\n"); - rcode = 1; - } - } - - /* Is the write enable latch on?. - */ - else if (!(ctrl_reg_v & 0x02)) { - /* Set write enable latch. - */ - contr_reg[0] = 0x02; - if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) { - rcode = 1; - } - } - /* Write is enabled ... now write eeprom value. - */ -#endif -#if defined(CONFIG_SYS_I2C_EEPROM_BUS) - i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS); -#endif - if (i2c_write(addr[0], offset, alen - 1, buffer, len)) - rcode = 1; + rcode = eeprom_rw_block(offset, addr, alen, buffer, len, read); -#endif buffer += len; offset += len; -#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS) - udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); -#endif + if (!read) + udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); } -#if defined(CONFIG_SYS_EEPROM_WREN) - eeprom_write_enable (dev_addr,0); -#endif + return rcode; } -#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C) -int -eeprom_probe (unsigned dev_addr, unsigned offset) +int eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt) { - unsigned char chip; - - /* Probe the chip address + /* + * Read data until done or would cross a page boundary. + * We must write the address again when changing pages + * because the next page may be in a different device. */ -#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X) - chip = offset >> 8; /* block number */ -#else - chip = offset >> 16; /* block number */ -#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */ + return eeprom_rw(dev_addr, offset, buffer, cnt, 1); +} + +int eeprom_write(unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt) +{ + int ret; + + eeprom_write_enable(dev_addr, 1); - chip |= dev_addr; /* insert device address */ + /* + * Write data until done or would cross a write page boundary. + * We must write the address again when changing pages + * because the address counter only increments within a page. + */ + ret = eeprom_rw(dev_addr, offset, buffer, cnt, 0); - return (i2c_probe (chip)); + eeprom_write_enable(dev_addr, 0); + return ret; } -#endif -/*----------------------------------------------------------------------- - * Set default values - */ -#ifndef CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SPEED 50000 +static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const char *const fmt = + "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... "; + char * const *args = &argv[2]; + int rcode; + ulong dev_addr, addr, off, cnt; + int bus_addr; + + switch (argc) { +#ifdef CONFIG_SYS_DEF_EEPROM_ADDR + case 5: + bus_addr = -1; + dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR; + break; #endif + case 6: + bus_addr = -1; + dev_addr = simple_strtoul(*args++, NULL, 16); + break; + case 7: + bus_addr = simple_strtoul(*args++, NULL, 16); + dev_addr = simple_strtoul(*args++, NULL, 16); + break; + default: + return CMD_RET_USAGE; + } -void eeprom_init (void) -{ + addr = simple_strtoul(*args++, NULL, 16); + off = simple_strtoul(*args++, NULL, 16); + cnt = simple_strtoul(*args++, NULL, 16); -#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) - spi_init_f (); -#endif -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif -} + eeprom_init(bus_addr); -/*----------------------------------------------------------------------- - */ + if (strcmp(argv[1], "read") == 0) { + printf(fmt, dev_addr, argv[1], addr, off, cnt); + + rcode = eeprom_read(dev_addr, off, (uchar *)addr, cnt); + + puts("done\n"); + return rcode; + } else if (strcmp(argv[1], "write") == 0) { + printf(fmt, dev_addr, argv[1], addr, off, cnt); -/***************************************************/ + rcode = eeprom_write(dev_addr, off, (uchar *)addr, cnt); -#if defined(CONFIG_CMD_EEPROM) + puts("done\n"); + return rcode; + } + + return CMD_RET_USAGE; +} -#ifdef CONFIG_SYS_I2C_MULTI_EEPROMS U_BOOT_CMD( - eeprom, 6, 1, do_eeprom, + eeprom, 7, 1, do_eeprom, "EEPROM sub-system", - "read devaddr addr off cnt\n" - "eeprom write devaddr addr off cnt\n" + "read <bus> <devaddr> addr off cnt\n" + "eeprom write <bus> <devaddr> addr off cnt\n" " - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'" ) -#else /* One EEPROM */ -U_BOOT_CMD( - eeprom, 5, 1, do_eeprom, - "EEPROM sub-system", - "read addr off cnt\n" - "eeprom write addr off cnt\n" - " - read/write `cnt' bytes at EEPROM offset `off'" -) -#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */ - -#endif diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c index e3c0297..d94d553 100644 --- a/common/cmd_gpt.c +++ b/common/cmd_gpt.c @@ -1,6 +1,9 @@ /* * cmd_gpt.c -- GPT (GUID Partition Table) handling command * + * Copyright (C) 2015 + * Lukasz Majewski <l.majewski@majess.pl> + * * Copyright (C) 2012 Samsung Electronics * author: Lukasz Majewski <l.majewski@samsung.com> * author: Piotr Wilczek <p.wilczek@samsung.com> @@ -15,6 +18,7 @@ #include <exports.h> #include <linux/ctype.h> #include <div64.h> +#include <memalign.h> #ifndef CONFIG_PARTITION_UUIDS #error CONFIG_PARTITION_UUIDS must be enabled for CONFIG_CMD_GPT to be enabled @@ -118,6 +122,40 @@ static char *extract_val(const char *str, const char *key) } /** + * found_key(): Found key without value in parameter list (comma separated). + * + * @param str - pointer to string with key + * @param key - pointer to the key to search for + * + * @return - true on found key + */ +static bool found_key(const char *str, const char *key) +{ + char *k; + char *s, *strcopy; + bool result = false; + + strcopy = strdup(str); + if (!strcopy) + return NULL; + + s = strcopy; + while (s) { + k = strsep(&s, ","); + if (!k) + break; + if (strcmp(k, key) == 0) { + result = true; + break; + } + } + + free(strcopy); + + return result; +} + +/** * set_gpt_info(): Fill partition information from string * function allocates memory, remember to free! * @@ -271,6 +309,10 @@ static int set_gpt_info(block_dev_desc_t *dev_desc, parts[i].start = lldiv(start_ll, dev_desc->blksz); free(val); } + + /* bootable */ + if (found_key(tok, "bootable")) + parts[i].bootable = 1; } *parts_count = p_count; @@ -293,9 +335,6 @@ static int gpt_default(block_dev_desc_t *blk_dev_desc, const char *str_part) u8 part_count = 0; disk_partition_t *partitions = NULL; - if (!str_part) - return -1; - /* fill partitions */ ret = set_gpt_info(blk_dev_desc, str_part, &str_disk_guid, &partitions, &part_count); @@ -317,6 +356,43 @@ static int gpt_default(block_dev_desc_t *blk_dev_desc, const char *str_part) return ret; } +static int gpt_verify(block_dev_desc_t *blk_dev_desc, const char *str_part) +{ + ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, + blk_dev_desc->blksz); + disk_partition_t *partitions = NULL; + gpt_entry *gpt_pte = NULL; + char *str_disk_guid; + u8 part_count = 0; + int ret = 0; + + /* fill partitions */ + ret = set_gpt_info(blk_dev_desc, str_part, + &str_disk_guid, &partitions, &part_count); + if (ret) { + if (ret == -1) { + printf("No partition list provided - only basic check\n"); + ret = gpt_verify_headers(blk_dev_desc, gpt_head, + &gpt_pte); + goto out; + } + if (ret == -2) + printf("Missing disk guid\n"); + if ((ret == -3) || (ret == -4)) + printf("Partition list incomplete\n"); + return -1; + } + + /* Check partition layout with provided pattern */ + ret = gpt_verify_partitions(blk_dev_desc, partitions, part_count, + gpt_head, &gpt_pte); + free(str_disk_guid); + free(partitions); + out: + free(gpt_pte); + return ret; +} + /** * do_gpt(): Perform GPT operations * @@ -332,45 +408,49 @@ static int do_gpt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int ret = CMD_RET_SUCCESS; int dev = 0; char *ep; - block_dev_desc_t *blk_dev_desc; + block_dev_desc_t *blk_dev_desc = NULL; - if (argc < 5) + if (argc < 4 || argc > 5) return CMD_RET_USAGE; - /* command: 'write' */ - if ((strcmp(argv[1], "write") == 0) && (argc == 5)) { - dev = (int)simple_strtoul(argv[3], &ep, 10); - if (!ep || ep[0] != '\0') { - printf("'%s' is not a number\n", argv[3]); - return CMD_RET_USAGE; - } - blk_dev_desc = get_dev(argv[2], dev); - if (!blk_dev_desc) { - printf("%s: %s dev %d NOT available\n", - __func__, argv[2], dev); - return CMD_RET_FAILURE; - } - - puts("Writing GPT: "); + dev = (int)simple_strtoul(argv[3], &ep, 10); + if (!ep || ep[0] != '\0') { + printf("'%s' is not a number\n", argv[3]); + return CMD_RET_USAGE; + } + blk_dev_desc = get_dev(argv[2], dev); + if (!blk_dev_desc) { + printf("%s: %s dev %d NOT available\n", + __func__, argv[2], dev); + return CMD_RET_FAILURE; + } + if ((strcmp(argv[1], "write") == 0) && (argc == 5)) { + printf("Writing GPT: "); ret = gpt_default(blk_dev_desc, argv[4]); - if (!ret) { - puts("success!\n"); - return CMD_RET_SUCCESS; - } else { - puts("error!\n"); - return CMD_RET_FAILURE; - } + } else if ((strcmp(argv[1], "verify") == 0)) { + ret = gpt_verify(blk_dev_desc, argv[4]); + printf("Verify GPT: "); } else { return CMD_RET_USAGE; } - return ret; + + if (ret) { + printf("error!\n"); + return CMD_RET_FAILURE; + } + + printf("success!\n"); + return CMD_RET_SUCCESS; } U_BOOT_CMD(gpt, CONFIG_SYS_MAXARGS, 1, do_gpt, "GUID Partition Table", "<command> <interface> <dev> <partitions_list>\n" - " - GUID partition table restoration\n" - " Restore GPT information on a device connected\n" + " - GUID partition table restoration and validity check\n" + " Restore or verify GPT information on a device connected\n" " to interface\n" + " Example usage:\n" + " gpt write mmc 0 $partitions\n" + " gpt verify mmc 0 $partitions\n" ); diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 3d0de81..552c875 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -1944,11 +1944,15 @@ static cmd_tbl_t cmd_i2c_sub[] = { U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""), }; -#ifdef CONFIG_NEEDS_MANUAL_RELOC -void i2c_reloc(void) { - fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub)); +static __maybe_unused void i2c_reloc(void) +{ + static int relocated; + + if (!relocated) { + fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub)); + relocated = 1; + }; } -#endif /** * do_i2c() - Handle the "i2c" command-line command @@ -1964,6 +1968,10 @@ static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { cmd_tbl_t *c; +#ifdef CONFIG_NEEDS_MANUAL_RELOC + i2c_reloc(); +#endif + if (argc < 2) return CMD_RET_USAGE; diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index dfc1ec8..a6b7313 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -747,7 +747,7 @@ static int do_mmc_rst_func(cmd_tbl_t *cmdtp, int flag, dev = simple_strtoul(argv[1], NULL, 10); enable = simple_strtoul(argv[2], NULL, 10); - if (enable > 2 || enable < 0) { + if (enable > 2) { puts("Invalid RST_n_ENABLE value\n"); return CMD_RET_USAGE; } diff --git a/common/cmd_part.c b/common/cmd_part.c index b860624..5599509 100644 --- a/common/cmd_part.c +++ b/common/cmd_part.c @@ -100,7 +100,7 @@ static int do_part_list(int argc, char * const argv[]) if (bootable && !info.bootable) continue; - sprintf(t, "%s%d", str[0] ? " " : "", p); + sprintf(t, "%s%x", str[0] ? " " : "", p); strcat(str, t); } setenv(var, str); diff --git a/common/cmd_pci.c b/common/cmd_pci.c index 802e433..4e0951f 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -18,103 +18,278 @@ #include <cli.h> #include <command.h> #include <console.h> +#include <dm.h> #include <asm/processor.h> #include <asm/io.h> #include <pci.h> -/* - * Follows routines for the output of infos about devices on PCI bus. - */ +struct pci_reg_info { + const char *name; + enum pci_size_t size; + u8 offset; +}; -void pci_header_show(pci_dev_t dev); -void pci_header_show_brief(pci_dev_t dev); +static int pci_byte_size(enum pci_size_t size) +{ + switch (size) { + case PCI_SIZE_8: + return 1; + case PCI_SIZE_16: + return 2; + case PCI_SIZE_32: + default: + return 4; + } +} -/* - * Subroutine: pciinfo - * - * Description: Show information about devices on PCI bus. - * Depending on the define CONFIG_SYS_SHORT_PCI_LISTING - * the output will be more or less exhaustive. - * - * Inputs: bus_no the number of the bus to be scanned. - * - * Return: None +static int pci_field_width(enum pci_size_t size) +{ + return pci_byte_size(size) * 2; +} + +#ifdef CONFIG_DM_PCI +static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs) +{ + for (; regs->name; regs++) { + unsigned long val; + + dm_pci_read_config(dev, regs->offset, &val, regs->size); + printf(" %s =%*s%#.*lx\n", regs->name, + (int)(28 - strlen(regs->name)), "", + pci_field_width(regs->size), val); + } +} +#else +static unsigned long pci_read_config(pci_dev_t dev, int offset, + enum pci_size_t size) +{ + u32 val32; + u16 val16; + u8 val8; + + switch (size) { + case PCI_SIZE_8: + pci_read_config_byte(dev, offset, &val8); + return val8; + case PCI_SIZE_16: + pci_read_config_word(dev, offset, &val16); + return val16; + case PCI_SIZE_32: + default: + pci_read_config_dword(dev, offset, &val32); + return val32; + } +} + +static void pci_show_regs(pci_dev_t dev, struct pci_reg_info *regs) +{ + for (; regs->name; regs++) { + printf(" %s =%*s%#.*lx\n", regs->name, + (int)(28 - strlen(regs->name)), "", + pci_field_width(regs->size), + pci_read_config(dev, regs->offset, regs->size)); + } +} +#endif + +static struct pci_reg_info regs_start[] = { + { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID }, + { "device ID", PCI_SIZE_16, PCI_DEVICE_ID }, + { "command register ID", PCI_SIZE_16, PCI_COMMAND }, + { "status register", PCI_SIZE_16, PCI_STATUS }, + { "revision ID", PCI_SIZE_8, PCI_REVISION_ID }, + {}, +}; + +static struct pci_reg_info regs_rest[] = { + { "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE }, + { "programming interface", PCI_SIZE_8, PCI_CLASS_PROG }, + { "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE }, + { "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER }, + { "header type", PCI_SIZE_8, PCI_HEADER_TYPE }, + { "BIST", PCI_SIZE_8, PCI_BIST }, + { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 }, + {}, +}; + +static struct pci_reg_info regs_normal[] = { + { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 }, + { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 }, + { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 }, + { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 }, + { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 }, + { "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS }, + { "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID }, + { "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID }, + { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS }, + { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE }, + { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN }, + { "min Grant", PCI_SIZE_8, PCI_MIN_GNT }, + { "max Latency", PCI_SIZE_8, PCI_MAX_LAT }, + {}, +}; + +static struct pci_reg_info regs_bridge[] = { + { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 }, + { "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS }, + { "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS }, + { "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS }, + { "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER }, + { "IO base", PCI_SIZE_8, PCI_IO_BASE }, + { "IO limit", PCI_SIZE_8, PCI_IO_LIMIT }, + { "secondary status", PCI_SIZE_16, PCI_SEC_STATUS }, + { "memory base", PCI_SIZE_16, PCI_MEMORY_BASE }, + { "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT }, + { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE }, + { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT }, + { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 }, + { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 }, + { "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 }, + { "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 }, + { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 }, + { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE }, + { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN }, + { "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL }, + {}, +}; + +static struct pci_reg_info regs_cardbus[] = { + { "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST }, + { "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS }, + { "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS }, + { "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS }, + { "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS }, + { "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER }, + { "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 }, + { "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 }, + { "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 }, + { "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 }, + { "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 }, + { "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI }, + { "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 }, + { "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI }, + { "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 }, + { "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI }, + { "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 }, + { "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI }, + { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE }, + { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN }, + { "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL }, + { "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID }, + { "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID }, + { "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE }, + {}, +}; + +/** + * pci_header_show() - Show the header of the specified PCI device. * + * @dev: Bus+Device+Function number */ -void pciinfo(int BusNum, int ShortPCIListing) +#ifdef CONFIG_DM_PCI +void pci_header_show(struct udevice *dev) +#else +void pci_header_show(pci_dev_t dev) +#endif { - struct pci_controller *hose = pci_bus_to_hose(BusNum); - int Device; - int Function; - unsigned char HeaderType; - unsigned short VendorID; - pci_dev_t dev; - int ret; +#ifdef CONFIG_DM_PCI + unsigned long class, header_type; - if (!hose) - return; + dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8); + dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8); +#else + u8 class, header_type; + + pci_read_config_byte(dev, PCI_CLASS_CODE, &class); + pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type); +#endif + pci_show_regs(dev, regs_start); + printf(" class code = 0x%.2x (%s)\n", (int)class, + pci_class_str(class)); + pci_show_regs(dev, regs_rest); + + switch (header_type & 0x03) { + case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */ + pci_show_regs(dev, regs_normal); + break; + case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */ + pci_show_regs(dev, regs_bridge); + break; + case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */ + pci_show_regs(dev, regs_cardbus); + break; + + default: + printf("unknown header\n"); + break; + } +} - printf("Scanning PCI devices on bus %d\n", BusNum); +void pciinfo_header(int busnum, bool short_listing) +{ + printf("Scanning PCI devices on bus %d\n", busnum); - if (ShortPCIListing) { + if (short_listing) { printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n"); printf("_____________________________________________________________\n"); } +} - for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) { - HeaderType = 0; - VendorID = 0; - for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) { - /* - * If this is not a multi-function device, we skip the rest. - */ - if (Function && !(HeaderType & 0x80)) - break; - - dev = PCI_BDF(BusNum, Device, Function); - - if (pci_skip_dev(hose, dev)) - continue; +#ifdef CONFIG_DM_PCI +/** + * pci_header_show_brief() - Show the short-form PCI device header + * + * Reads and prints the header of the specified PCI device in short form. + * + * @dev: PCI device to show + */ +static void pci_header_show_brief(struct udevice *dev) +{ + ulong vendor, device; + ulong class, subclass; - ret = pci_read_config_word(dev, PCI_VENDOR_ID, - &VendorID); - if (ret) - goto error; - if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) - continue; + dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16); + dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16); + dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8); + dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8); - if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType); + printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n", + vendor, device, + pci_class_str(class), subclass); +} - if (ShortPCIListing) - { - printf("%02x.%02x.%02x ", BusNum, Device, Function); - pci_header_show_brief(dev); - } - else - { - printf("\nFound PCI device %02x.%02x.%02x:\n", - BusNum, Device, Function); - pci_header_show(dev); - } +static void pciinfo(struct udevice *bus, bool short_listing) +{ + struct udevice *dev; + + pciinfo_header(bus->seq, short_listing); + + for (device_find_first_child(bus, &dev); + dev; + device_find_next_child(&dev)) { + struct pci_child_platdata *pplat; + + pplat = dev_get_parent_platdata(dev); + if (short_listing) { + printf("%02x.%02x.%02x ", bus->seq, + PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn)); + pci_header_show_brief(dev); + } else { + printf("\nFound PCI device %02x.%02x.%02x:\n", bus->seq, + PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn)); + pci_header_show(dev); } } - - return; -error: - printf("Cannot read bus configuration: %d\n", ret); } +#else -/* - * Subroutine: pci_header_show_brief - * - * Description: Reads and prints the header of the - * specified PCI device in short form. +/** + * pci_header_show_brief() - Show the short-form PCI device header * - * Inputs: dev Bus+Device+Function number - * - * Return: None + * Reads and prints the header of the specified PCI device in short form. * + * @dev: Bus+Device+Function number */ void pci_header_show_brief(pci_dev_t dev) { @@ -131,128 +306,85 @@ void pci_header_show_brief(pci_dev_t dev) pci_class_str(class), subclass); } -/* - * Subroutine: PCI_Header_Show +/** + * pciinfo() - Show a list of devices on the PCI bus * - * Description: Reads the header of the specified PCI device. - * - * Inputs: BusDevFunc Bus+Device+Function number - * - * Return: None + * Show information about devices on PCI bus. Depending on @short_pci_listing + * the output will be more or less exhaustive. * + * @bus_num: The number of the bus to be scanned + * @short_pci_listing: true to use short form, showing only a brief header + * for each device */ -void pci_header_show(pci_dev_t dev) +void pciinfo(int bus_num, int short_pci_listing) { - u8 _byte, header_type; - u16 _word; - u32 _dword; - -#define PRINT(msg, type, reg) \ - pci_read_config_##type(dev, reg, &_##type); \ - printf(msg, _##type) - -#define PRINT2(msg, type, reg, func) \ - pci_read_config_##type(dev, reg, &_##type); \ - printf(msg, _##type, func(_##type)) + struct pci_controller *hose = pci_bus_to_hose(bus_num); + int device; + int function; + unsigned char header_type; + unsigned short vendor_id; + pci_dev_t dev; + int ret; - pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type); + if (!hose) + return; - PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID); - PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID); - PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND); - PRINT (" status register = 0x%.4x\n", word, PCI_STATUS); - PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID); - PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE, - pci_class_str); - PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE); - PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG); - PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE); - PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER); - PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE); - PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST); - PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0); + pciinfo_header(bus_num, short_pci_listing); - switch (header_type & 0x03) { - case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */ - PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1); - PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2); - PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3); - PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4); - PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5); - PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS); - PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID); - PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID); - PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS); - PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); - PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); - PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT); - PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT); - break; + for (device = 0; device < PCI_MAX_PCI_DEVICES; device++) { + header_type = 0; + vendor_id = 0; + for (function = 0; function < PCI_MAX_PCI_FUNCTIONS; + function++) { + /* + * If this is not a multi-function device, we skip + * the rest. + */ + if (function && !(header_type & 0x80)) + break; - case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */ + dev = PCI_BDF(bus_num, device, function); - PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1); - PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS); - PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS); - PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS); - PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER); - PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE); - PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT); - PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS); - PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE); - PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT); - PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE); - PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT); - PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32); - PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32); - PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16); - PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16); - PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1); - PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); - PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); - PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL); - break; + if (pci_skip_dev(hose, dev)) + continue; - case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */ + ret = pci_read_config_word(dev, PCI_VENDOR_ID, + &vendor_id); + if (ret) + goto error; + if ((vendor_id == 0xFFFF) || (vendor_id == 0x0000)) + continue; - PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST); - PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS); - PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS); - PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS); - PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS); - PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER); - PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0); - PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0); - PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1); - PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1); - PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0); - PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI); - PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0); - PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI); - PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1); - PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI); - PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1); - PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI); - PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); - PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); - PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL); - PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID); - PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID); - PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE); - break; + if (!function) { + pci_read_config_byte(dev, PCI_HEADER_TYPE, + &header_type); + } - default: - printf("unknown header\n"); - break; - } + if (short_pci_listing) { + printf("%02x.%02x.%02x ", bus_num, device, + function); + pci_header_show_brief(dev); + } else { + printf("\nFound PCI device %02x.%02x.%02x:\n", + bus_num, device, function); + pci_header_show(dev); + } + } + } -#undef PRINT -#undef PRINT2 + return; +error: + printf("Cannot read bus configuration: %d\n", ret); } +#endif -/* Convert the "bus.device.function" identifier into a number. +/** + * get_pci_dev() - Convert the "bus.device.function" identifier into a number + * + * @name: Device string in the form "bus.device.function" where each is in hex + * @return encoded pci_dev_t or -1 if the string was invalid */ -static pci_dev_t get_pci_dev(char* name) +static pci_dev_t get_pci_dev(char *name) { char cnum[12]; int len, i, iold, n; @@ -273,41 +405,44 @@ static pci_dev_t get_pci_dev(char* name) if (n == 0) n = 1; bdfs[n] = simple_strtoul(cnum, NULL, 16); + return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]); } -static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length) +#ifdef CONFIG_DM_PCI +static int pci_cfg_display(struct udevice *dev, ulong addr, + enum pci_size_t size, ulong length) +#else +static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size, + ulong length) +#endif { #define DISP_LINE_LEN 16 ulong i, nbytes, linebytes; + int byte_size; int rc = 0; + byte_size = pci_byte_size(size); if (length == 0) - length = 0x40 / size; /* Standard PCI configuration space */ + length = 0x40 / byte_size; /* Standard PCI config space */ /* Print the lines. * once, and all accesses are with the specified bus width. */ - nbytes = length * size; + nbytes = length * byte_size; do { - uint val4; - ushort val2; - u_char val1; - printf("%08lx:", addr); - linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes; - for (i=0; i<linebytes; i+= size) { - if (size == 4) { - pci_read_config_dword(bdf, addr, &val4); - printf(" %08x", val4); - } else if (size == 2) { - pci_read_config_word(bdf, addr, &val2); - printf(" %04x", val2); - } else { - pci_read_config_byte(bdf, addr, &val1); - printf(" %02x", val1); - } - addr += size; + linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; + for (i = 0; i < linebytes; i += byte_size) { + unsigned long val; + +#ifdef CONFIG_DM_PCI + dm_pci_read_config(dev, addr, &val, size); +#else + val = pci_read_config(bdf, addr, size); +#endif + printf(" %0*lx", pci_field_width(size), val); + addr += byte_size; } printf("\n"); nbytes -= linebytes; @@ -320,6 +455,7 @@ static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length) return (rc); } +#ifndef CONFIG_DM_PCI static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value) { if (size == 4) { @@ -335,33 +471,31 @@ static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value) } return 0; } +#endif -static int -pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag) +#ifdef CONFIG_DM_PCI +static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size, + ulong value, int incrflag) +#else +static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value, + int incrflag) +#endif { ulong i; int nbytes; - uint val4; - ushort val2; - u_char val1; + ulong val; /* Print the address, followed by value. Then accept input for * the next value. A non-converted value exits. */ do { printf("%08lx:", addr); - if (size == 4) { - pci_read_config_dword(bdf, addr, &val4); - printf(" %08x", val4); - } - else if (size == 2) { - pci_read_config_word(bdf, addr, &val2); - printf(" %04x", val2); - } - else { - pci_read_config_byte(bdf, addr, &val1); - printf(" %02x", val1); - } +#ifdef CONFIG_DM_PCI + dm_pci_read_config(dev, addr, &val, size); +#else + val = pci_read_config(bdf, addr, size); +#endif + printf(" %0*lx", pci_field_width(size), val); nbytes = cli_readline(" ? "); if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) { @@ -387,7 +521,11 @@ pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag /* good enough to not time out */ bootretry_reset_cmd_timeout(); - pci_cfg_write (bdf, addr, size, i); +#ifdef CONFIG_DM_PCI + dm_pci_write_config(dev, addr, i, size); +#else + pci_cfg_write(bdf, addr, size, i); +#endif if (incrflag) addr += size; } @@ -407,9 +545,17 @@ pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag */ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - ulong addr = 0, value = 0, size = 0; + ulong addr = 0, value = 0, cmd_size = 0; + enum pci_size_t size = PCI_SIZE_32; +#ifdef CONFIG_DM_PCI + struct udevice *dev, *bus; +#else + pci_dev_t dev; +#endif + int busnum = 0; pci_dev_t bdf = 0; char cmd = 's'; + int ret = 0; if (argc > 1) cmd = argv[1][0]; @@ -420,7 +566,8 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) case 'm': /* modify */ case 'w': /* write */ /* Check for a size specification. */ - size = cmd_get_data_size(argv[1], 4); + cmd_size = cmd_get_data_size(argv[1], 4); + size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1; if (argc > 3) addr = simple_strtoul(argv[3], NULL, 16); if (argc > 4) @@ -437,45 +584,77 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif default: /* scan bus */ value = 1; /* short listing */ - bdf = 0; /* bus number */ if (argc > 1) { if (argv[argc-1][0] == 'l') { value = 0; argc--; } if (argc > 1) - bdf = simple_strtoul(argv[1], NULL, 16); + busnum = simple_strtoul(argv[1], NULL, 16); + } +#ifdef CONFIG_DM_PCI + ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus); + if (ret) { + printf("No such bus\n"); + return CMD_RET_FAILURE; } - pciinfo(bdf, value); + pciinfo(bus, value); +#else + pciinfo(busnum, value); +#endif return 0; } +#ifdef CONFIG_DM_PCI + ret = pci_bus_find_bdf(bdf, &dev); + if (ret) { + printf("No such device\n"); + return CMD_RET_FAILURE; + } +#else + dev = bdf; +#endif + switch (argv[1][0]) { case 'h': /* header */ - pci_header_show(bdf); - return 0; + pci_header_show(dev); + break; case 'd': /* display */ - return pci_cfg_display(bdf, addr, size, value); + return pci_cfg_display(dev, addr, size, value); #ifdef CONFIG_CMD_PCI_ENUM case 'e': +# ifdef CONFIG_DM_PCI + printf("This command is not yet supported with driver model\n"); +# else pci_init(); - return 0; +# endif + break; #endif case 'n': /* next */ if (argc < 4) goto usage; - return pci_cfg_modify(bdf, addr, size, value, 0); + ret = pci_cfg_modify(dev, addr, size, value, 0); + break; case 'm': /* modify */ if (argc < 4) goto usage; - return pci_cfg_modify(bdf, addr, size, value, 1); + ret = pci_cfg_modify(dev, addr, size, value, 1); + break; case 'w': /* write */ if (argc < 5) goto usage; - return pci_cfg_write(bdf, addr, size, value); +#ifdef CONFIG_DM_PCI + ret = dm_pci_write_config(dev, addr, value, size); +#else + ret = pci_cfg_write(dev, addr, size, value); +#endif + break; + default: + ret = CMD_RET_USAGE; + break; } - return 1; + return ret; usage: return CMD_RET_USAGE; } diff --git a/common/console.c b/common/console.c index b3f126c..bc37b6d 100644 --- a/common/console.c +++ b/common/console.c @@ -558,45 +558,6 @@ void puts(const char *s) } } -int printf(const char *fmt, ...) -{ - va_list args; - uint i; - char printbuffer[CONFIG_SYS_PBSIZE]; - - va_start(args, fmt); - - /* For this to work, printbuffer must be larger than - * anything we ever want to print. - */ - i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args); - va_end(args); - - /* Print the string */ - puts(printbuffer); - return i; -} - -int vprintf(const char *fmt, va_list args) -{ - uint i; - char printbuffer[CONFIG_SYS_PBSIZE]; - -#if defined(CONFIG_PRE_CONSOLE_BUFFER) && !defined(CONFIG_SANDBOX) - if (!gd->have_console) - return 0; -#endif - - /* For this to work, printbuffer must be larger than - * anything we ever want to print. - */ - i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args); - - /* Print the string */ - puts(printbuffer); - return i; -} - #ifdef CONFIG_CONSOLE_RECORD int console_record_init(void) { diff --git a/common/env_eeprom.c b/common/env_eeprom.c index eea169d..72b1373 100644 --- a/common/env_eeprom.c +++ b/common/env_eeprom.c @@ -91,7 +91,7 @@ void env_relocate_spec(void) uchar rdbuf[64], flags[2]; int i, crc_ok[2] = {0, 0}; - eeprom_init(); /* prepare for EEPROM read/write */ + eeprom_init(-1); /* prepare for EEPROM read/write */ off_env[0] = CONFIG_ENV_OFFSET; off_env[1] = CONFIG_ENV_OFFSET_REDUND; @@ -154,7 +154,7 @@ void env_relocate_spec(void) ulong crc, len, new; uchar rdbuf[64]; - eeprom_init(); /* prepare for EEPROM read/write */ + eeprom_init(-1); /* prepare for EEPROM read/write */ /* read old CRC */ eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, diff --git a/common/fdt_support.c b/common/fdt_support.c index a7ff2df..66464db 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -16,6 +16,7 @@ #include <libfdt.h> #include <fdt_support.h> #include <exports.h> +#include <fdtdec.h> /** * fdt_getprop_u32_default_node - Return a node's property or a default @@ -950,7 +951,7 @@ void fdt_del_node_and_alias(void *blob, const char *alias) /* Max address size we deal with */ #define OF_MAX_ADDR_CELLS 4 -#define OF_BAD_ADDR ((u64)-1) +#define OF_BAD_ADDR FDT_ADDR_T_NONE #define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \ (ns) > 0) diff --git a/common/image-fdt.c b/common/image-fdt.c index 5180a03..5e4e5bd 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -326,7 +326,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, if (load == image_start || load == image_data) { - fdt_blob = (char *)image_data; + fdt_addr = load; break; } diff --git a/common/miiphyutil.c b/common/miiphyutil.c index e499b58..7e41957 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -114,6 +114,8 @@ void miiphy_register(const char *name, if (new_dev == NULL || ldev == NULL) { printf("miiphy_register: cannot allocate memory for '%s'\n", name); + free(ldev); + mdio_free(new_dev); return; } @@ -159,7 +161,7 @@ void mdio_free(struct mii_dev *bus) int mdio_register(struct mii_dev *bus) { - if (!bus || !bus->name || !bus->read || !bus->write) + if (!bus || !bus->read || !bus->write) return -1; /* check if we have unique name */ diff --git a/common/spl/spl.c b/common/spl/spl.c index 7a393dc..6e6dee7 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -452,7 +452,7 @@ ulong spl_relocate_stack_gd(void) #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) { if (!(gd->flags & GD_FLG_SPL_INIT)) - panic("spl_init must be called before heap reloc"); + panic_str("spl_init must be called before heap reloc"); ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN; gd->malloc_base = ptr; diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index b3c2c64..c1c29c0 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -23,12 +23,13 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector) unsigned long count; u32 image_size_sectors; struct image_header *header; + int dev_num = mmc->block_dev.dev; header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - sizeof(struct image_header)); /* read image header to find the image size & load address */ - count = mmc->block_dev.block_read(0, sector, 1, header); + count = mmc->block_dev.block_read(dev_num, sector, 1, header); debug("read sector %lx, count=%lu\n", sector, count); if (count == 0) goto end; @@ -45,7 +46,7 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector) mmc->read_bl_len; /* Read the header too to avoid extra memcpy */ - count = mmc->block_dev.block_read(0, sector, image_size_sectors, + count = mmc->block_dev.block_read(dev_num, sector, image_size_sectors, (void *)(ulong)spl_image.load_addr); debug("read %x sectors to %x\n", image_size_sectors, spl_image.load_addr); @@ -78,10 +79,11 @@ int spl_mmc_get_device_index(u32 boot_device) return -ENODEV; } -#ifdef CONFIG_DM_MMC -static int spl_mmc_find_device(struct mmc **mmc, u32 boot_device) +static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device) { +#ifdef CONFIG_DM_MMC struct udevice *dev; +#endif int err, mmc_dev; mmc_dev = spl_mmc_get_device_index(boot_device); @@ -96,47 +98,23 @@ static int spl_mmc_find_device(struct mmc **mmc, u32 boot_device) return err; } +#ifdef CONFIG_DM_MMC err = uclass_get_device(UCLASS_MMC, mmc_dev, &dev); - if (err) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: could not find mmc device. error: %d\n", err); -#endif - return err; - } - - *mmc = NULL; - *mmc = mmc_get_mmc_dev(dev); - return *mmc != NULL ? 0 : -ENODEV; -} + if (!err) + *mmcp = mmc_get_mmc_dev(dev); #else -static int spl_mmc_find_device(struct mmc **mmc, u32 boot_device) -{ - int err, mmc_dev; - - mmc_dev = spl_mmc_get_device_index(boot_device); - if (mmc_dev < 0) - return mmc_dev; - - err = mmc_initialize(gd->bd); + *mmcp = find_mmc_device(mmc_dev); + err = *mmcp ? 0 : -ENODEV; +#endif if (err) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: could not initialize mmc. error: %d\n", err); + printf("spl: could not find mmc device. error: %d\n", err); #endif return err; } - /* We register only one device. So, the dev id is always 0 */ - *mmc = find_mmc_device(mmc_dev); - if (!*mmc) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - puts("spl: mmc device not found\n"); -#endif - return -ENODEV; - } - return 0; } -#endif #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION static int mmc_load_image_raw_partition(struct mmc *mmc, int partition) @@ -172,7 +150,8 @@ static int mmc_load_image_raw_os(struct mmc *mmc) { unsigned long count; - count = mmc->block_dev.block_read(0, + count = mmc->block_dev.block_read( + mmc->block_dev.dev, CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS, (void *) CONFIG_SYS_SPL_ARGS_ADDR); @@ -248,7 +227,7 @@ int spl_mmc_do_fs_boot(struct mmc *mmc) int spl_mmc_load_image(u32 boot_device) { - struct mmc *mmc; + struct mmc *mmc = NULL; u32 boot_mode; int err = 0; __maybe_unused int part; diff --git a/common/usb.c b/common/usb.c index 700bfc3..9f67cc1 100644 --- a/common/usb.c +++ b/common/usb.c @@ -566,13 +566,12 @@ static int usb_get_descriptor(struct usb_device *dev, unsigned char type, } /********************************************************************** - * gets configuration cfgno and store it in the buffer + * gets len of configuration cfgno */ -int usb_get_configuration_no(struct usb_device *dev, - unsigned char *buffer, int cfgno) +int usb_get_configuration_len(struct usb_device *dev, int cfgno) { int result; - unsigned int length; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, 9); struct usb_config_descriptor *config; config = (struct usb_config_descriptor *)&buffer[0]; @@ -586,17 +585,23 @@ int usb_get_configuration_no(struct usb_device *dev, "(expected %i, got %i)\n", 9, result); return -EIO; } - length = le16_to_cpu(config->wTotalLength); + return le16_to_cpu(config->wTotalLength); +} - if (length > USB_BUFSIZ) { - printf("%s: failed to get descriptor - too long: %d\n", - __func__, length); - return -EIO; - } +/********************************************************************** + * gets configuration cfgno and store it in the buffer + */ +int usb_get_configuration_no(struct usb_device *dev, int cfgno, + unsigned char *buffer, int length) +{ + int result; + struct usb_config_descriptor *config; + config = (struct usb_config_descriptor *)&buffer[0]; result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, length); - debug("get_conf_no %d Result %d, wLength %d\n", cfgno, result, length); - config->wTotalLength = length; /* validated, with CPU byte order */ + debug("get_conf_no %d Result %d, wLength %d\n", cfgno, result, + le16_to_cpu(config->wTotalLength)); + config->wTotalLength = result; /* validated, with CPU byte order */ return result; } @@ -1070,7 +1075,7 @@ static int usb_prepare_device(struct usb_device *dev, int addr, bool do_read, int usb_select_config(struct usb_device *dev) { - ALLOC_CACHE_ALIGN_BUFFER(unsigned char, tmpbuf, USB_BUFSIZ); + unsigned char *tmpbuf = 0; int err; err = get_descriptor_len(dev, USB_DT_DEVICE_SIZE, USB_DT_DEVICE_SIZE); @@ -1084,14 +1089,23 @@ int usb_select_config(struct usb_device *dev) le16_to_cpus(&dev->descriptor.bcdDevice); /* only support for one config for now */ - err = usb_get_configuration_no(dev, tmpbuf, 0); + err = usb_get_configuration_len(dev, 0); + if (err >= 0) { + tmpbuf = (unsigned char *)malloc_cache_aligned(err); + if (!tmpbuf) + err = -ENOMEM; + else + err = usb_get_configuration_no(dev, 0, tmpbuf, err); + } if (err < 0) { printf("usb_new_device: Cannot read configuration, " \ "skipping device %04x:%04x\n", dev->descriptor.idVendor, dev->descriptor.idProduct); + free(tmpbuf); return err; } usb_parse_config(dev, tmpbuf, 0); + free(tmpbuf); usb_set_maxpacket(dev); /* * we set the default configuration here @@ -1200,4 +1214,60 @@ bool usb_device_has_child_on_port(struct usb_device *parent, int port) #endif } +#ifdef CONFIG_DM_USB +void usb_find_usb2_hub_address_port(struct usb_device *udev, + uint8_t *hub_address, uint8_t *hub_port) +{ + struct udevice *parent; + struct usb_device *uparent, *ttdev; + + /* + * When called from usb-uclass.c: usb_scan_device() udev->dev points + * to the parent udevice, not the actual udevice belonging to the + * udev as the device is not instantiated yet. So when searching + * for the first usb-2 parent start with udev->dev not + * udev->dev->parent . + */ + ttdev = udev; + parent = udev->dev; + uparent = dev_get_parent_priv(parent); + + while (uparent->speed != USB_SPEED_HIGH) { + struct udevice *dev = parent; + + if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) { + printf("Error: Cannot find high speed parent of usb-1 device\n"); + *hub_address = 0; + *hub_port = 0; + return; + } + + ttdev = dev_get_parent_priv(dev); + parent = dev->parent; + uparent = dev_get_parent_priv(parent); + } + *hub_address = uparent->devnum; + *hub_port = ttdev->portnr; +} +#else +void usb_find_usb2_hub_address_port(struct usb_device *udev, + uint8_t *hub_address, uint8_t *hub_port) +{ + /* Find out the nearest parent which is high speed */ + while (udev->parent->parent != NULL) + if (udev->parent->speed != USB_SPEED_HIGH) { + udev = udev->parent; + } else { + *hub_address = udev->parent->devnum; + *hub_port = udev->portnr; + return; + } + + printf("Error: Cannot find high speed parent of usb-1 device\n"); + *hub_address = 0; + *hub_port = 0; +} +#endif + + /* EOF */ diff --git a/common/usb_kbd.c b/common/usb_kbd.c index 069fbd2..9617a48 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -476,6 +476,9 @@ static int usb_kbd_probe_dev(struct usb_device *dev, unsigned int ifnum) USB_KBD_BOOT_REPORT_SIZE, data->new, data->intinterval); if (!data->intq) { +#elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP) + if (usb_get_report(dev, iface->desc.bInterfaceNumber, + 1, 0, data->new, USB_KBD_BOOT_REPORT_SIZE) < 0) { #else if (usb_submit_int_msg(dev, data->intpipe, data->new, data->intpktsize, data->intinterval) < 0) { diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig index 1919502..a0d29a0 100644 --- a/configs/10m50_defconfig +++ b/configs/10m50_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="10m50_devboard" CONFIG_DM_SERIAL=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard" +CONFIG_FIT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_BOOTD is not set @@ -22,6 +23,6 @@ CONFIG_MTD=y CONFIG_ALTERA_QSPI=y CONFIG_DM_ETH=y CONFIG_ALTERA_TSE=y -CONFIG_ALTERA_UART=y +CONFIG_SYS_NS16550=y CONFIG_TIMER=y CONFIG_ALTERA_TIMER=y diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig index 8bc13f3..9d249c7 100644 --- a/configs/3c120_defconfig +++ b/configs/3c120_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="3c120_devboard" CONFIG_DM_SERIAL=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard" +CONFIG_FIT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_BOOTD is not set diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 0357803..11691a2 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -12,8 +12,6 @@ CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_USB_MUSB_SUNXI=y -CONFIG_USB_MUSB_GADGET=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -23,3 +21,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2" # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index f616388..001d31b 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -3,6 +3,9 @@ CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=480 CONFIG_MMC0_CD_PIN="PH1" +CONFIG_MMC3_CD_PIN="PH0" +CONFIG_MMC3_PINS="PH" +CONFIG_MMC_SUNXI_SLOT_EXTRA=3 CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb" diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig index 986eda6..e50833a 100644 --- a/configs/B4420QDS_NAND_defconfig +++ b/configs/B4420QDS_NAND_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_B4860QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig index 5c6a319..b53a1cf 100644 --- a/configs/B4420QDS_SPIFLASH_defconfig +++ b/configs/B4420QDS_SPIFLASH_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig index 8568f7d..8308b95 100644 --- a/configs/B4420QDS_defconfig +++ b/configs/B4420QDS_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig index a48ada4..a8f05db 100644 --- a/configs/B4860QDS_NAND_defconfig +++ b/configs/B4860QDS_NAND_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_B4860QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig index 60ff218..1a61dc3 100644 --- a/configs/B4860QDS_SECURE_BOOT_defconfig +++ b/configs/B4860QDS_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig index 7e8449e..0875ee7 100644 --- a/configs/B4860QDS_SPIFLASH_defconfig +++ b/configs/B4860QDS_SPIFLASH_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig index 5e3fd50..11db5bc 100644 --- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig @@ -5,5 +5,8 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig index d5c7545..54ceec7 100644 --- a/configs/B4860QDS_defconfig +++ b/configs/B4860QDS_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig index 90aa865..5e0e09b 100644 --- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig +++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig @@ -6,3 +6,6 @@ CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig index 9cd68f0..4f666f1 100644 --- a/configs/BSC9131RDB_NAND_defconfig +++ b/configs/BSC9131RDB_NAND_defconfig @@ -6,3 +6,6 @@ CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig index d90d7a0..ca90c83 100644 --- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig +++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig @@ -5,3 +5,6 @@ CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig index 4ba8d62..2902a68 100644 --- a/configs/BSC9131RDB_SPIFLASH_defconfig +++ b/configs/BSC9131RDB_SPIFLASH_defconfig @@ -5,3 +5,6 @@ CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig index b123f9e..15e3862 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig index 0da87b3..48f1c3c 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_BSC9132QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig index d8ad344..b909789 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig index 738c490..06b411d 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_BSC9132QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig index c468137..6f37d36 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig index 31a5223..4993dc9 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig index 726c8ff..d69047e 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig index ff4e4b4..f9129ca 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig index 61725cd..d11e9e3 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig index 484857a..4c22ce6 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig index c4a772a..f350c34 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig index fcada6d..1862f0c 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig index 9282e0e..5173a5b 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig index f6ad1e9..a1a5cd3 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig index f3c5702..14ed190 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig index 7f3554d..6e5fbaf 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig index fd26cea..bef3771 100644 --- a/configs/C29XPCIE_NAND_defconfig +++ b/configs/C29XPCIE_NAND_defconfig @@ -5,5 +5,9 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig index bcc2701..110e597 100644 --- a/configs/C29XPCIE_NOR_SECBOOT_defconfig +++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig @@ -3,5 +3,9 @@ CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig index 2f151fa..de0beb6 100644 --- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig +++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig @@ -3,5 +3,9 @@ CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig index 8057f9c..d2d9262 100644 --- a/configs/C29XPCIE_SPIFLASH_defconfig +++ b/configs/C29XPCIE_SPIFLASH_defconfig @@ -3,5 +3,9 @@ CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig index 11610d5..373db16 100644 --- a/configs/C29XPCIE_defconfig +++ b/configs/C29XPCIE_defconfig @@ -3,5 +3,9 @@ CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/CPCI2DP_defconfig b/configs/CPCI2DP_defconfig index 9f98014..1c821ba 100644 --- a/configs/CPCI2DP_defconfig +++ b/configs/CPCI2DP_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_CPCI2DP=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/CPCI4052_defconfig b/configs/CPCI4052_defconfig index c4fac41..ba4a13e 100644 --- a/configs/CPCI4052_defconfig +++ b/configs/CPCI4052_defconfig @@ -5,3 +5,4 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index 4f4f6d4..8cbaea6 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -3,6 +3,9 @@ CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 CONFIG_MMC0_CD_PIN="PH1" +CONFIG_USB0_VBUS_PIN="PH17" +CONFIG_USB0_VBUS_DET="PH22" +CONFIG_USB0_ID_DET="PH19" CONFIG_VIDEO_VGA=y CONFIG_GMAC_TX_DELAY=1 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck" @@ -15,8 +18,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)" CONFIG_CMD_GPIO=y CONFIG_ETH_DESIGNWARE=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB0_ID_DET="PH19" -CONFIG_USB0_VBUS_DET="PH22" -CONFIG_USB0_VBUS_PIN="PH17" -CONFIG_USB_MUSB_SUNXI=y CONFIG_USB_MUSB_GADGET=y diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig index 280e417..e4deda9 100644 --- a/configs/Cyrus_P5020_defconfig +++ b/configs/Cyrus_P5020_defconfig @@ -7,3 +7,5 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020" # CONFIG_CMD_FLASH is not set CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig index d34c05b..026d37a 100644 --- a/configs/Cyrus_P5040_defconfig +++ b/configs/Cyrus_P5040_defconfig @@ -7,3 +7,5 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040" # CONFIG_CMD_FLASH is not set CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig new file mode 100644 index 0000000..5973fbf --- /dev/null +++ b/configs/Empire_electronix_d709_defconfig @@ -0,0 +1,24 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_CLK=432 +CONFIG_DRAM_EMR1=0 +CONFIG_MMC0_CD_PIN="PG0" +CONFIG_USB0_VBUS_PIN="PG12" +CONFIG_USB0_VBUS_DET="PG1" +CONFIG_USB0_ID_DET="PG2" +CONFIG_AXP_GPIO=y +# CONFIG_VIDEO_HDMI is not set +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_POWER="AXP0-0" +CONFIG_VIDEO_LCD_BL_EN="AXP0-1" +CONFIG_VIDEO_LCD_BL_PWM="PB2" +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_USB_MUSB_HOST=y diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig new file mode 100644 index 0000000..d460c32 --- /dev/null +++ b/configs/Lamobo_R1_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN7I=y +CONFIG_DRAM_CLK=432 +CONFIG_MMC0_CD_PIN="PH10" +CONFIG_GMAC_TX_DELAY=4 +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUNXI_GPB(3)" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_USB_EHCI_HCD=y diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig index ccb8823..b2ad88a 100644 --- a/configs/M52277EVB_defconfig +++ b/configs/M52277EVB_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig index 1ee9c8b..ea39356 100644 --- a/configs/M52277EVB_stmicro_defconfig +++ b/configs/M52277EVB_stmicro_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000" # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig index bc47ed6..7c22abe 100644 --- a/configs/M54418TWR_defconfig +++ b/configs/M54418TWR_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig index 949be9a..373845b 100644 --- a/configs/M54418TWR_nand_mii_defconfig +++ b/configs/M54418TWR_nand_mii_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig index 4035ea9..08c45b2 100644 --- a/configs/M54418TWR_nand_rmii_defconfig +++ b/configs/M54418TWR_nand_rmii_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig index d89a587..c5bf10e 100644 --- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig +++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig index cd383c2..9e81827 100644 --- a/configs/M54418TWR_serial_mii_defconfig +++ b/configs/M54418TWR_serial_mii_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig index bc47ed6..7c22abe 100644 --- a/configs/M54418TWR_serial_rmii_defconfig +++ b/configs/M54418TWR_serial_rmii_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig index 2115263..3b96dfb 100644 --- a/configs/M54451EVB_defconfig +++ b/configs/M54451EVB_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig index 9b69415..21a2687 100644 --- a/configs/M54451EVB_stmicro_defconfig +++ b/configs/M54451EVB_stmicro_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_I # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig index e82d0bd..e810273 100644 --- a/configs/M54455EVB_a66_defconfig +++ b/configs/M54455EVB_a66_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKS # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig index 20bf103..3d9cb12 100644 --- a/configs/M54455EVB_defconfig +++ b/configs/M54455EVB_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig index bc7d707..b5cbfdc 100644 --- a/configs/M54455EVB_i66_defconfig +++ b/configs/M54455EVB_i66_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKS # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig index cb5b4bd..8ed05a6 100644 --- a/configs/M54455EVB_intel_defconfig +++ b/configs/M54455EVB_intel_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKS # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig index a79f949..0a64580 100644 --- a/configs/M54455EVB_stm33_defconfig +++ b/configs/M54455EVB_stm33_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_I # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/MIP405T_defconfig b/configs/MIP405T_defconfig index 22b82b1..799a1b6 100644 --- a/configs/MIP405T_defconfig +++ b/configs/MIP405T_defconfig @@ -3,3 +3,4 @@ CONFIG_4xx=y CONFIG_TARGET_MIP405=y CONFIG_SYS_EXTRA_OPTIONS="MIP405T" # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MIP405_defconfig b/configs/MIP405_defconfig index f25cf51..3a012e7 100644 --- a/configs/MIP405_defconfig +++ b/configs/MIP405_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_MIP405=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index cb98324..2aec6d9 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC8308RDB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index ec8d7b6..d736191 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_MPC8313ERDB=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index ed498de..583fde8 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_MPC8313ERDB=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index ed0b105..7faa2fe 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -5,3 +5,4 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index 4dfb715..bb4a35d 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -5,3 +5,4 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index e618381..3d9dede 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC8315ERDB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 762ad5b..337a0dd 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC8323ERDB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index b4b3724..cd29b89 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 9a2f338..071fe08 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1" # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 66e4269..789c8b1 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1" # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index 467f220..7f5c55a 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE" # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index 3e24ab1..2ea5868 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 6a907cf..f4d1d45 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 1a85eea..445beb6 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_MPC8349ITX=y CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000" CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> " # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 9aabd6a..c260a46 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_MPC8349ITX=y CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000" CONFIG_SYS_PROMPT="MPC8349E-mITX> " # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index a5309de..5b234c6 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_MPC8349ITX=y CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX" CONFIG_SYS_PROMPT="MPC8349E-mITX> " # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 2e472a7..972e0f8 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XEMDS=y CONFIG_SYS_EXTRA_OPTIONS="PCI" # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index 21b4506..9ddddde 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XEMDS=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 126d0d2..c77fe0c 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XERDB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig index 6604004..fdea51d 100644 --- a/configs/MPC8536DS_36BIT_defconfig +++ b/configs/MPC8536DS_36BIT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8536DS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig index d1bad84..a7492fd 100644 --- a/configs/MPC8536DS_SDCARD_defconfig +++ b/configs/MPC8536DS_SDCARD_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8536DS=y CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig index ad0ae69..e2a4226 100644 --- a/configs/MPC8536DS_SPIFLASH_defconfig +++ b/configs/MPC8536DS_SPIFLASH_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8536DS=y CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig index 2e9ae63..c07b84a 100644 --- a/configs/MPC8536DS_defconfig +++ b/configs/MPC8536DS_defconfig @@ -2,5 +2,8 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8536DS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/MPC8540ADS_defconfig b/configs/MPC8540ADS_defconfig index 41af349..1239ba8 100644 --- a/configs/MPC8540ADS_defconfig +++ b/configs/MPC8540ADS_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8540ADS=y +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig index bc9c246..0c5cc13 100644 --- a/configs/MPC8541CDS_defconfig +++ b/configs/MPC8541CDS_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8541CDS=y +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig index 55478ab..3ae3a3d 100644 --- a/configs/MPC8541CDS_legacy_defconfig +++ b/configs/MPC8541CDS_legacy_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8541CDS=y CONFIG_SYS_EXTRA_OPTIONS="LEGACY" +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig index ab0c79b..e4e2f9c 100644 --- a/configs/MPC8544DS_defconfig +++ b/configs/MPC8544DS_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8544DS=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 11d67ef..5e635e0 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_MPC8548CDS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT" CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 6a9ce6a..ac2c090 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8548CDS=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 381947f..3e1ecd7 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_MPC8548CDS=y CONFIG_SYS_EXTRA_OPTIONS="LEGACY" CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig index 3bdbb0c..9a7c16e 100644 --- a/configs/MPC8555CDS_defconfig +++ b/configs/MPC8555CDS_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8555CDS=y +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig index 8e53ee0..eb6382c 100644 --- a/configs/MPC8555CDS_legacy_defconfig +++ b/configs/MPC8555CDS_legacy_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8555CDS=y CONFIG_SYS_EXTRA_OPTIONS="LEGACY" +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig index ac0ec8c..36b5c3b 100644 --- a/configs/MPC8568MDS_defconfig +++ b/configs/MPC8568MDS_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8568MDS=y +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig index 719ca84..186126b 100644 --- a/configs/MPC8569MDS_ATM_defconfig +++ b/configs/MPC8569MDS_ATM_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_MPC8569MDS=y CONFIG_SYS_EXTRA_OPTIONS="ATM" CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig index bb1a4fb..bfb51d2 100644 --- a/configs/MPC8569MDS_defconfig +++ b/configs/MPC8569MDS_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8569MDS=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig index 5c76524..878404b 100644 --- a/configs/MPC8572DS_36BIT_defconfig +++ b/configs/MPC8572DS_36BIT_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_MPC8572DS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT" CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig index 2f69b14..8b42ea3 100644 --- a/configs/MPC8572DS_defconfig +++ b/configs/MPC8572DS_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8572DS=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig index f0e1370..bdde5d0 100644 --- a/configs/MPC8610HPCD_defconfig +++ b/configs/MPC8610HPCD_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC86xx=y CONFIG_TARGET_MPC8610HPCD=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig index 0aee7ea..46f8077 100644 --- a/configs/MPC8641HPCN_36BIT_defconfig +++ b/configs/MPC8641HPCN_36BIT_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC86xx=y CONFIG_TARGET_MPC8641HPCN=y CONFIG_SYS_EXTRA_OPTIONS="PHYS_64BIT" # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig index 2bee038..25056d6 100644 --- a/configs/MPC8641HPCN_defconfig +++ b/configs/MPC8641HPCN_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC86xx=y CONFIG_TARGET_MPC8641HPCN=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index 5689cff..806fb64 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -9,4 +9,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y +CONFIG_SUNXI_NO_PMIC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig index 407f0fb..c533f97 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 737921c..8c0f763 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig index a34436e..c09e73e 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index c6cc9b5..32580d8 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index d32ca80..d656b21 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig index 56cc3c6..7d31491 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index da56dfb..981d4db 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig index fec2697..d49b5a7 100644 --- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index e45a541..f638ff2 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig index 64ed63a..8a4793d 100644 --- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index fe4c8b5..f00c54f 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 3d41cb0..384d0e7 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig index 6afce00..751cc54 100644 --- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index faab1ac..fc4afce 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig index a76affd..40e2f26 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 64963b6..6321123 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig index ea68ffb..982f829 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 0a5403d..521a3d4 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index f7e9050..ac6ee07 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig index b92c3f3..2363aec 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index ae9309a..875e4d5 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig index 9b9a8a2..51286af 100644 --- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 60b3417..47e249c 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig index 17b9941..aa68725 100644 --- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index f3b3b22..c07fa85 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 5d9607c..7a431b5 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig index c88b433..d3d9e49 100644 --- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index b390406..256bdf4 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig index 7714ac6..ef36139 100644 --- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT" CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig index 29a520b..0cbe477 100644 --- a/configs/P1020MBG-PC_36BIT_defconfig +++ b/configs/P1020MBG-PC_36BIT_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT" CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig index c0a0745..4771767 100644 --- a/configs/P1020MBG-PC_SDCARD_defconfig +++ b/configs/P1020MBG-PC_SDCARD_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD" CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig index bc408b7..9c25cfc 100644 --- a/configs/P1020MBG-PC_defconfig +++ b/configs/P1020MBG-PC_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1020MBG" CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index b7d1d2e..0ecaaff 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 6b55479..32d3606 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 78db491..da260a7 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index df9dbc9..3fad0b9 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index c54b31a..09616da 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 3c08d4f..4ed2f7c 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 708d5c4..3a26800 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index b7c624f..734824e 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 82492c0..c45b2a8 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index e694d5b..bdfc29e 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 3cf0b8a..4ebcfea 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 6ddf70c..3c97423 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig index b29fcc4..27259c3 100644 --- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD" CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig index 63b6471..ace09b0 100644 --- a/configs/P1020UTM-PC_36BIT_defconfig +++ b/configs/P1020UTM-PC_36BIT_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT" CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig index 650ffe5..42e6d1c 100644 --- a/configs/P1020UTM-PC_SDCARD_defconfig +++ b/configs/P1020UTM-PC_SDCARD_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD" CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig index 56ca99c..9a5a04f 100644 --- a/configs/P1020UTM-PC_defconfig +++ b/configs/P1020UTM-PC_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1020UTM" CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig index d246c7b..d6ec2ad 100644 --- a/configs/P1021RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig index 1bf813f..9414eab 100644 --- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig index d5c8bd2..429d249 100644 --- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig index a9510dc..236d67a 100644 --- a/configs/P1021RDB-PC_36BIT_defconfig +++ b/configs/P1021RDB-PC_36BIT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig index a7de239..e1410b6 100644 --- a/configs/P1021RDB-PC_NAND_defconfig +++ b/configs/P1021RDB-PC_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig index faf36fe..8950dcd 100644 --- a/configs/P1021RDB-PC_SDCARD_defconfig +++ b/configs/P1021RDB-PC_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig index cc9320f..8760a60 100644 --- a/configs/P1021RDB-PC_SPIFLASH_defconfig +++ b/configs/P1021RDB-PC_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig index 9ac36f7..fd52fcf 100644 --- a/configs/P1021RDB-PC_defconfig +++ b/configs/P1021RDB-PC_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig index c093ccf..a57ab4a 100644 --- a/configs/P1022DS_36BIT_NAND_defconfig +++ b/configs/P1022DS_36BIT_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig index 342870d..0e68138 100644 --- a/configs/P1022DS_36BIT_SDCARD_defconfig +++ b/configs/P1022DS_36BIT_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1022DS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig index 40db7b5..130b7cf 100644 --- a/configs/P1022DS_36BIT_SPIFLASH_defconfig +++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1022DS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig index d6f2ee4..5646062 100644 --- a/configs/P1022DS_36BIT_defconfig +++ b/configs/P1022DS_36BIT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1022DS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig index 22e354c..ef08a9e 100644 --- a/configs/P1022DS_NAND_defconfig +++ b/configs/P1022DS_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig index 25ec334..8ff94af 100644 --- a/configs/P1022DS_SDCARD_defconfig +++ b/configs/P1022DS_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1022DS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig index 0227f35..ecc48cc 100644 --- a/configs/P1022DS_SPIFLASH_defconfig +++ b/configs/P1022DS_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1022DS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig index 427c64b..40c6621 100644 --- a/configs/P1022DS_defconfig +++ b/configs/P1022DS_defconfig @@ -2,5 +2,8 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1022DS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig index ab8f6bb..2478f30 100644 --- a/configs/P1023RDB_defconfig +++ b/configs/P1023RDB_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1023RDB=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig index ab32765..3f96330 100644 --- a/configs/P1024RDB_36BIT_defconfig +++ b/configs/P1024RDB_36BIT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig index 1b4f31c..05c06b6 100644 --- a/configs/P1024RDB_NAND_defconfig +++ b/configs/P1024RDB_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig index d647f8a..ad081e5 100644 --- a/configs/P1024RDB_SDCARD_defconfig +++ b/configs/P1024RDB_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig index b5790e1..12158de 100644 --- a/configs/P1024RDB_SPIFLASH_defconfig +++ b/configs/P1024RDB_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig index 5dd1cbc..3d13da9 100644 --- a/configs/P1024RDB_defconfig +++ b/configs/P1024RDB_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig index 509f116..453c057 100644 --- a/configs/P1025RDB_36BIT_defconfig +++ b/configs/P1025RDB_36BIT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig index 6369e39..1c5e06a 100644 --- a/configs/P1025RDB_NAND_defconfig +++ b/configs/P1025RDB_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig index a3cc80a..fc01fe6 100644 --- a/configs/P1025RDB_SDCARD_defconfig +++ b/configs/P1025RDB_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig index b5d56f7..0a37298 100644 --- a/configs/P1025RDB_SPIFLASH_defconfig +++ b/configs/P1025RDB_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig index 05c347e..fe21544 100644 --- a/configs/P1025RDB_defconfig +++ b/configs/P1025RDB_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index e86ff8c..578bfc5 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index d97c6bc..19c795a 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 8c15726..bdc5e43 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index b93ce08..b9d4a47 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 3184f5e..ea9f830 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -5,5 +5,8 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 4328967..997887d 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 55cb86c..e547ea4 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index b5496fc..fdad880 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index a3e8f9c..540b79d 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index dc022a1..e879d94 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig index 3fccb2b..114fc32 100644 --- a/configs/P2041RDB_SECURE_BOOT_defconfig +++ b/configs/P2041RDB_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index f748ba3..6feec40 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig index 4d62252..45ba154 100644 --- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig @@ -5,5 +5,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 9dba9a6..9a455ef 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -2,5 +2,8 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig index 6e4b88e..783089b 100644 --- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index d075e8f..d8fa407 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index 5f1c198..385bcc8 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig index 307f6d7..5d463a2 100644 --- a/configs/P3041DS_SECURE_BOOT_defconfig +++ b/configs/P3041DS_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 6112639..2c52861 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig index 24a79ce..6925f99 100644 --- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig @@ -5,5 +5,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index 0fed50f..b41254d 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -2,5 +2,8 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 74a1452..4a0a65d 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig index 0dd1f32..92e1c1d 100644 --- a/configs/P4080DS_SECURE_BOOT_defconfig +++ b/configs/P4080DS_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index b7bfc38..c503a70 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig index 766db5e..f9b877b 100644 --- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig @@ -5,5 +5,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index b0a6bdf..319f1c7 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -2,5 +2,8 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig index c89ec85..46b78bc 100644 --- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig index 64ba6e9..259371c 100644 --- a/configs/P5020DS_NAND_defconfig +++ b/configs/P5020DS_NAND_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig index 796e9a1..2da6f48 100644 --- a/configs/P5020DS_SDCARD_defconfig +++ b/configs/P5020DS_SDCARD_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig index 27ae488..aeb7949 100644 --- a/configs/P5020DS_SECURE_BOOT_defconfig +++ b/configs/P5020DS_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig index 65cc600..ae06e9c 100644 --- a/configs/P5020DS_SPIFLASH_defconfig +++ b/configs/P5020DS_SPIFLASH_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig index 65e9d2f..53a279e 100644 --- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig @@ -5,5 +5,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig index bd06987..e133570 100644 --- a/configs/P5020DS_defconfig +++ b/configs/P5020DS_defconfig @@ -2,5 +2,8 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig index 3027031..063e0f7 100644 --- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index b2f5cda..2c5f058 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index 950df55..d78bea0 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig index d0bc383..ca1c87c 100644 --- a/configs/P5040DS_SECURE_BOOT_defconfig +++ b/configs/P5040DS_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 0dbc3eb..4c403b6 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index 5da5a3c..4c01789 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -2,5 +2,8 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/PIP405_defconfig b/configs/PIP405_defconfig index ced7d1a..046a5d8 100644 --- a/configs/PIP405_defconfig +++ b/configs/PIP405_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_PIP405=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/PLU405_defconfig b/configs/PLU405_defconfig index a691e24..546376f 100644 --- a/configs/PLU405_defconfig +++ b/configs/PLU405_defconfig @@ -5,3 +5,4 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/PMC405DE_defconfig b/configs/PMC405DE_defconfig index 37b2d23..53fccf5 100644 --- a/configs/PMC405DE_defconfig +++ b/configs/PMC405DE_defconfig @@ -5,3 +5,4 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/PMC440_defconfig b/configs/PMC440_defconfig index 96ff54c..984497a 100644 --- a/configs/PMC440_defconfig +++ b/configs/PMC440_defconfig @@ -5,3 +5,4 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig index 836bde4..4fe6af8 100644 --- a/configs/T1023RDB_NAND_defconfig +++ b/configs/T1023RDB_NAND_defconfig @@ -6,5 +6,8 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig index 7bc7f54..84febc5 100644 --- a/configs/T1023RDB_SDCARD_defconfig +++ b/configs/T1023RDB_SDCARD_defconfig @@ -6,5 +6,8 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig index 6a3ccca..8e355be 100644 --- a/configs/T1023RDB_SECURE_BOOT_defconfig +++ b/configs/T1023RDB_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig index 83b14a8..b72fc86 100644 --- a/configs/T1023RDB_SPIFLASH_defconfig +++ b/configs/T1023RDB_SPIFLASH_defconfig @@ -6,5 +6,8 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig index c4b72d4..eb5d4ef 100644 --- a/configs/T1023RDB_defconfig +++ b/configs/T1023RDB_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig index f69c49d..5a30ab4 100644 --- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig @@ -3,5 +3,10 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XQDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig index 174fbca..39dc0a6 100644 --- a/configs/T1024QDS_DDR4_defconfig +++ b/configs/T1024QDS_DDR4_defconfig @@ -3,3 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XQDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig index caedd39..4425bb2 100644 --- a/configs/T1024QDS_NAND_defconfig +++ b/configs/T1024QDS_NAND_defconfig @@ -4,5 +4,10 @@ CONFIG_TARGET_T102XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig index 844d9a5..97e32ca 100644 --- a/configs/T1024QDS_SDCARD_defconfig +++ b/configs/T1024QDS_SDCARD_defconfig @@ -4,5 +4,10 @@ CONFIG_TARGET_T102XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig index 9f80de0..aa5dcde 100644 --- a/configs/T1024QDS_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_SECURE_BOOT_defconfig @@ -3,5 +3,10 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XQDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig index dc5a460..beaac8b 100644 --- a/configs/T1024QDS_SPIFLASH_defconfig +++ b/configs/T1024QDS_SPIFLASH_defconfig @@ -4,5 +4,10 @@ CONFIG_TARGET_T102XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig index 74138c7..7bb2ea6 100644 --- a/configs/T1024QDS_defconfig +++ b/configs/T1024QDS_defconfig @@ -3,5 +3,10 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XQDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 7ae0433..065e168 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T102XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 3a664f8..ae4f8cf 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T102XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig index 8f4378b..e24c91b 100644 --- a/configs/T1024RDB_SECURE_BOOT_defconfig +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 36f2208..91aad61 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T102XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index fba47c2..d43ec06 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig index 0af8c8d..e96c984 100644 --- a/configs/T1040D4RDB_NAND_defconfig +++ b/configs/T1040D4RDB_NAND_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig index dc9ee34..e90d39d 100644 --- a/configs/T1040D4RDB_SDCARD_defconfig +++ b/configs/T1040D4RDB_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig index 6a891a6..17f7585 100644 --- a/configs/T1040D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig index 4628576..0191a63 100644 --- a/configs/T1040D4RDB_SPIFLASH_defconfig +++ b/configs/T1040D4RDB_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig index 6adc196..6feecb3 100644 --- a/configs/T1040D4RDB_defconfig +++ b/configs/T1040D4RDB_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig index 8c4320b..52b67c8 100644 --- a/configs/T1040QDS_DDR4_defconfig +++ b/configs/T1040QDS_DDR4_defconfig @@ -3,5 +3,10 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T1040QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig index 607c280..d98b87a 100644 --- a/configs/T1040QDS_SECURE_BOOT_defconfig +++ b/configs/T1040QDS_SECURE_BOOT_defconfig @@ -3,5 +3,10 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T1040QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig index 1f200f9..56eb500 100644 --- a/configs/T1040QDS_defconfig +++ b/configs/T1040QDS_defconfig @@ -3,5 +3,10 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T1040QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig index 146448d..74f22d2 100644 --- a/configs/T1040RDB_NAND_defconfig +++ b/configs/T1040RDB_NAND_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig index f363067..a0f9f2d 100644 --- a/configs/T1040RDB_SDCARD_defconfig +++ b/configs/T1040RDB_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig index 55d2a5e..7b19069 100644 --- a/configs/T1040RDB_SECURE_BOOT_defconfig +++ b/configs/T1040RDB_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig index c6fd93a..3305e49 100644 --- a/configs/T1040RDB_SPIFLASH_defconfig +++ b/configs/T1040RDB_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig index 810d1d8..8b7816d 100644 --- a/configs/T1040RDB_defconfig +++ b/configs/T1040RDB_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index c06e335..8c77cda 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index b86554a..0a3b0f8 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig index 8130f7c..f856f7d 100644 --- a/configs/T1042D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index ca7243a..307de29 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 4e44c89..1549200 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig index ff0052a..fb229df 100644 --- a/configs/T1042RDB_PI_NAND_defconfig +++ b/configs/T1042RDB_PI_NAND_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig index c19bd8b..3743a1f 100644 --- a/configs/T1042RDB_PI_SDCARD_defconfig +++ b/configs/T1042RDB_PI_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig index fbce984..ce3e54e 100644 --- a/configs/T1042RDB_PI_SPIFLASH_defconfig +++ b/configs/T1042RDB_PI_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig index 6353543..18d3967 100644 --- a/configs/T1042RDB_PI_defconfig +++ b/configs/T1042RDB_PI_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig index 39121ca..cdcfccf 100644 --- a/configs/T1042RDB_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig index e5888e3..2a11421 100644 --- a/configs/T1042RDB_defconfig +++ b/configs/T1042RDB_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 3610370..13f40b4 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -4,5 +4,10 @@ CONFIG_TARGET_T208XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 37cb6b7..a72830e 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -4,5 +4,10 @@ CONFIG_TARGET_T208XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 0f27b07..6a50147 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -3,5 +3,10 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 85a3689..dc66fd3 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -4,5 +4,10 @@ CONFIG_TARGET_T208XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 8f276fa..ca842a4 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -5,5 +5,10 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index c681528..3d2be66 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -3,5 +3,10 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index ab4a7be..e2eead4 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T208XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 5d0f43a..fc61d1a 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T208XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig index 43a76bc..fe4a439 100644 --- a/configs/T2080RDB_SECURE_BOOT_defconfig +++ b/configs/T2080RDB_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T208XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 1b230b1..4fbaf65 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T208XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig index af1a232..95720ee 100644 --- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig @@ -5,5 +5,8 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index cbd1220..bc2fc92 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T208XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig index 9ef946b..57f327c 100644 --- a/configs/T2081QDS_NAND_defconfig +++ b/configs/T2081QDS_NAND_defconfig @@ -4,5 +4,10 @@ CONFIG_TARGET_T208XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig index 8728f2d..74a134e 100644 --- a/configs/T2081QDS_SDCARD_defconfig +++ b/configs/T2081QDS_SDCARD_defconfig @@ -4,5 +4,10 @@ CONFIG_TARGET_T208XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig index 95c37dc..85d48c3 100644 --- a/configs/T2081QDS_SPIFLASH_defconfig +++ b/configs/T2081QDS_SPIFLASH_defconfig @@ -4,5 +4,10 @@ CONFIG_TARGET_T208XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig index 1b0ac47..70f87d7 100644 --- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig @@ -5,5 +5,10 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig index 8f3bcf6..23ed67c 100644 --- a/configs/T2081QDS_defconfig +++ b/configs/T2081QDS_defconfig @@ -3,5 +3,10 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig index 3a35060..bf88846 100644 --- a/configs/T4160QDS_NAND_defconfig +++ b/configs/T4160QDS_NAND_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T4240QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig index ef7135e..dcb9ac8 100644 --- a/configs/T4160QDS_SDCARD_defconfig +++ b/configs/T4160QDS_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T4240QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig index d08f98c..42e6508 100644 --- a/configs/T4160QDS_SECURE_BOOT_defconfig +++ b/configs/T4160QDS_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig index e44af1e..d87eb23 100644 --- a/configs/T4160QDS_defconfig +++ b/configs/T4160QDS_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig index 1cc929f..708374b 100644 --- a/configs/T4160RDB_defconfig +++ b/configs/T4160RDB_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T4240RDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig index 31e1f53..4ee998b 100644 --- a/configs/T4240QDS_NAND_defconfig +++ b/configs/T4240QDS_NAND_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T4240QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig index a464136..6a3320a 100644 --- a/configs/T4240QDS_SDCARD_defconfig +++ b/configs/T4240QDS_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T4240QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig index 094f305..861ac5c 100644 --- a/configs/T4240QDS_SECURE_BOOT_defconfig +++ b/configs/T4240QDS_SECURE_BOOT_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig index 60afd9e..0adca74 100644 --- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig @@ -5,5 +5,8 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig index 7fe54bf..7d8e826 100644 --- a/configs/T4240QDS_defconfig +++ b/configs/T4240QDS_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 0d0d26c..009ec04 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -4,5 +4,8 @@ CONFIG_TARGET_T4240RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 01221b0..217471a 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -3,5 +3,8 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T4240RDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index c980d95..f88beef 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_TQM834X=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig index e6d34e8..2b0a2ab 100644 --- a/configs/TWR-P1025_defconfig +++ b/configs/TWR-P1025_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_TWR=y CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025" CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/UCP1020_SPIFLASH_defconfig b/configs/UCP1020_SPIFLASH_defconfig index d06e5fa..a075bcc 100644 --- a/configs/UCP1020_SPIFLASH_defconfig +++ b/configs/UCP1020_SPIFLASH_defconfig @@ -7,5 +7,10 @@ CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n" CONFIG_AUTOBOOT_STOP_STR="\x1b" CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig index 043e617..c8da464 100644 --- a/configs/UCP1020_defconfig +++ b/configs/UCP1020_defconfig @@ -7,5 +7,10 @@ CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n" CONFIG_AUTOBOOT_STOP_STR="\x1b" CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/VOM405_defconfig b/configs/VOM405_defconfig index ba3ade0..53ac1bf 100644 --- a/configs/VOM405_defconfig +++ b/configs/VOM405_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_VOM405=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/acadia_defconfig b/configs/acadia_defconfig index 26221ce..51efe06 100644 --- a/configs/acadia_defconfig +++ b/configs/acadia_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_ACADIA=y +CONFIG_SYS_NS16550=y diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig index 4216cd7..87be263 100644 --- a/configs/adp-ag101p_defconfig +++ b/configs/adp-ag101p_defconfig @@ -2,3 +2,4 @@ CONFIG_NDS32=y CONFIG_TARGET_ADP_AG101P=y CONFIG_SYS_PROMPT="NDS32 # " # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/alt_defconfig b/configs/alt_defconfig index 479b4a5..aaf6a99 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -19,3 +19,4 @@ CONFIG_TARGET_ALT=y CONFIG_SH_SDHI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index a0d4328..91bb63f 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -10,3 +10,4 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig index c5c7b5d..3030a95 100644 --- a/configs/am335x_boneblack_defconfig +++ b/configs/am335x_boneblack_defconfig @@ -10,3 +10,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_DFU_TFTP=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index e93f6ac..ad40b07 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -15,4 +15,6 @@ CONFIG_CMD_GPIO=y CONFIG_OF_CONTROL=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y +CONFIG_SYS_NS16550=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 0fa3720..27cb881 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -9,3 +9,5 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig index 5d89104..bde7b8a 100644 --- a/configs/am335x_evm_nor_defconfig +++ b/configs/am335x_evm_nor_defconfig @@ -9,3 +9,5 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig index ffc0b09..94dfb5a 100644 --- a/configs/am335x_evm_norboot_defconfig +++ b/configs/am335x_evm_norboot_defconfig @@ -6,3 +6,5 @@ CONFIG_NOR_BOOT=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index de4f586..9757142 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -9,3 +9,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig index 496b709..0329948 100644 --- a/configs/am335x_evm_usbspl_defconfig +++ b/configs/am335x_evm_usbspl_defconfig @@ -9,3 +9,5 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig index f5cd48c..74d9ffb 100644 --- a/configs/am335x_gp_evm_defconfig +++ b/configs/am335x_gp_evm_defconfig @@ -12,5 +12,7 @@ CONFIG_CMD_GPIO=y CONFIG_OF_CONTROL=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y +CONFIG_SYS_NS16550=y CONFIG_RSA=y diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig index 6175aba..8f6bf02 100644 --- a/configs/am335x_igep0033_defconfig +++ b/configs/am335x_igep0033_defconfig @@ -7,3 +7,4 @@ CONFIG_SPL_STACK_R=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index e810fdc..d6cd92e 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig index 48a184f..72172cf 100644 --- a/configs/am3517_crane_defconfig +++ b/configs/am3517_crane_defconfig @@ -10,3 +10,4 @@ CONFIG_SYS_PROMPT="AM3517_CRANE # " # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 8857b9f..cde84fe 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -9,3 +9,4 @@ CONFIG_SYS_PROMPT="AM3517_EVM # " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig index f69e97e..7155c98 100644 --- a/configs/am437x_gp_evm_defconfig +++ b/configs/am437x_gp_evm_defconfig @@ -15,3 +15,6 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y +CONFIG_TI_QSPI=y diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig index 1a0b518..a9b6f52 100644 --- a/configs/am437x_sk_evm_defconfig +++ b/configs/am437x_sk_evm_defconfig @@ -15,3 +15,6 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y +CONFIG_TI_QSPI=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 49a617f..1ba1c8b 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -8,3 +8,6 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y +CONFIG_TI_QSPI=y diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig index 9eb9972..ff2acf0 100644 --- a/configs/am43xx_evm_ethboot_defconfig +++ b/configs/am43xx_evm_ethboot_defconfig @@ -7,3 +7,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_ETH_SUPPORT" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y +CONFIG_TI_QSPI=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index f6a24cc..095f4d0 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -6,3 +6,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y +CONFIG_TI_QSPI=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index a5f2b9f..be99599 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -7,3 +7,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y +CONFIG_TI_QSPI=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 8d6fd1e..c5e4670 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -18,3 +18,4 @@ CONFIG_DM=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SYS_NS16550=y diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig index eb402b8..e351be4 100644 --- a/configs/am57xx_evm_nodt_defconfig +++ b/configs/am57xx_evm_nodt_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index e882883..f939bdb 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -13,6 +13,8 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_NFS is not set CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_PCI_TEGRA=y +CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/arches_defconfig b/configs/arches_defconfig index 9084a3a..245e6fa 100644 --- a/configs/arches_defconfig +++ b/configs/arches_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_CANYONLANDS=y CONFIG_ARCHES=y CONFIG_DEFAULT_DEVICE_TREE="arches" CONFIG_OF_CONTROL=y +CONFIG_SYS_NS16550=y diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index acce983..b83e7ea 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig index 45e63ed..cdad556 100644 --- a/configs/aristainetos2b_defconfig +++ b/configs/aristainetos2b_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig index 5e9f220..15fc3a9 100644 --- a/configs/aristainetos_defconfig +++ b/configs/aristainetos_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig index c606244..812122f 100644 --- a/configs/aspenite_defconfig +++ b/configs/aspenite_defconfig @@ -5,3 +5,4 @@ CONFIG_TARGET_ASPENITE=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index 7c2af16..6f2390b 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index 3aa3cb1..ec16f34 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -9,3 +9,4 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index b01fdc1..655c574 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -9,3 +9,4 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index 998f11d..43b32d1 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -9,3 +9,4 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index 78b73cf..29fdf31 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -9,3 +9,4 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index d1a8c6c..004ee25 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -10,3 +10,4 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 51b7e05..c574422 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -10,3 +10,4 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/atngw100_defconfig b/configs/atngw100_defconfig index 5b01c18..7ef4677 100644 --- a/configs/atngw100_defconfig +++ b/configs/atngw100_defconfig @@ -11,3 +11,4 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/atngw100mkii_defconfig b/configs/atngw100mkii_defconfig index 48ea9ba..b552421 100644 --- a/configs/atngw100mkii_defconfig +++ b/configs/atngw100mkii_defconfig @@ -10,3 +10,4 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index 78fcb76..38bb9ab 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -11,3 +11,4 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM" # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 8e5d2e5..a541d9d 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="axs10x" CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y @@ -18,4 +19,10 @@ CONFIG_DM=y CONFIG_CLK=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index cbd63fe..a208a27 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="axs10x" CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y @@ -17,4 +18,9 @@ CONFIG_DM=y CONFIG_CLK=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/bamboo_defconfig b/configs/bamboo_defconfig index 1d66807..6ecdbcc 100644 --- a/configs/bamboo_defconfig +++ b/configs/bamboo_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_BAMBOO=y +CONFIG_SYS_NS16550=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index a36a501..f462e05 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -21,10 +21,16 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_CPU=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO_VESA=y diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig index ce1e805..4b1bc49 100644 --- a/configs/bcm11130_defconfig +++ b/configs/bcm11130_defconfig @@ -7,3 +7,4 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig index a0b5b01..2e7aff9 100644 --- a/configs/bcm11130_nand_defconfig +++ b/configs/bcm11130_nand_defconfig @@ -7,3 +7,4 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig index 38ed8da..7ec0d30 100644 --- a/configs/bcm28155_ap_defconfig +++ b/configs/bcm28155_ap_defconfig @@ -6,3 +6,4 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig index d7e27ea..47eb31d 100644 --- a/configs/bcm28155_w1d_defconfig +++ b/configs/bcm28155_w1d_defconfig @@ -7,3 +7,4 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig index 4a7e1bc..58c0ff6 100644 --- a/configs/bcm911360_entphn-ns_defconfig +++ b/configs/bcm911360_entphn-ns_defconfig @@ -4,3 +4,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig index a0d291c..2589cb1 100644 --- a/configs/bcm911360_entphn_defconfig +++ b/configs/bcm911360_entphn_defconfig @@ -4,3 +4,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig index df88a57..ba430e6 100644 --- a/configs/bcm911360k_defconfig +++ b/configs/bcm911360k_defconfig @@ -4,3 +4,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig index d9105a6..14db5a1 100644 --- a/configs/bcm958300k-ns_defconfig +++ b/configs/bcm958300k-ns_defconfig @@ -4,3 +4,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig index df88a57..ba430e6 100644 --- a/configs/bcm958300k_defconfig +++ b/configs/bcm958300k_defconfig @@ -4,3 +4,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig index df88a57..ba430e6 100644 --- a/configs/bcm958305k_defconfig +++ b/configs/bcm958305k_defconfig @@ -4,3 +4,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig index 2272462..3bf0b0e 100644 --- a/configs/bcm958622hr_defconfig +++ b/configs/bcm958622hr_defconfig @@ -4,3 +4,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig index 45c0c29..8add08d 100644 --- a/configs/beaver_defconfig +++ b/configs/beaver_defconfig @@ -13,6 +13,10 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PCI_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_TEGRA20_SLINK=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/bf518f-ezbrd_defconfig b/configs/bf518f-ezbrd_defconfig index 430fc7c..a8eab8c 100644 --- a/configs/bf518f-ezbrd_defconfig +++ b/configs/bf518f-ezbrd_defconfig @@ -4,4 +4,6 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf525-ucr2_defconfig b/configs/bf525-ucr2_defconfig index 6406f20..15a8f1f 100644 --- a/configs/bf525-ucr2_defconfig +++ b/configs/bf525-ucr2_defconfig @@ -6,3 +6,4 @@ CONFIG_TARGET_BF525_UCR2=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y diff --git a/configs/bf526-ezbrd_defconfig b/configs/bf526-ezbrd_defconfig index 6a652a0..a5f4b73 100644 --- a/configs/bf526-ezbrd_defconfig +++ b/configs/bf526-ezbrd_defconfig @@ -4,3 +4,4 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y diff --git a/configs/bf527-ad7160-eval_defconfig b/configs/bf527-ad7160-eval_defconfig index 3b9e374..4751df4 100644 --- a/configs/bf527-ad7160-eval_defconfig +++ b/configs/bf527-ad7160-eval_defconfig @@ -6,4 +6,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig index 53679ca..356ab64 100644 --- a/configs/bf527-ezkit-v2_defconfig +++ b/configs/bf527-ezkit-v2_defconfig @@ -4,4 +4,5 @@ CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_LIB_RAND=y diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig index 8752267..c1b139c 100644 --- a/configs/bf527-ezkit_defconfig +++ b/configs/bf527-ezkit_defconfig @@ -2,5 +2,6 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF527_EZKIT=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +# CONFIG_NET_TFTP_VARS is not set CONFIG_SPI_FLASH=y -CONFIG_NET_TFTP_VARS=n +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/bf527-sdp_defconfig b/configs/bf527-sdp_defconfig index f422f42..383f62e 100644 --- a/configs/bf527-sdp_defconfig +++ b/configs/bf527-sdp_defconfig @@ -6,4 +6,11 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/bf537-minotaur_defconfig b/configs/bf537-minotaur_defconfig index f71af52..bf3d79f 100644 --- a/configs/bf537-minotaur_defconfig +++ b/configs/bf537-minotaur_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_PROMPT="minotaur> " # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/bf537-pnav_defconfig b/configs/bf537-pnav_defconfig index 88a3ef1..e737561 100644 --- a/configs/bf537-pnav_defconfig +++ b/configs/bf537-pnav_defconfig @@ -4,3 +4,4 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/bf537-srv1_defconfig b/configs/bf537-srv1_defconfig index 3db7400..ba80e63 100644 --- a/configs/bf537-srv1_defconfig +++ b/configs/bf537-srv1_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_PROMPT="srv1> " # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/bf537-stamp_defconfig b/configs/bf537-stamp_defconfig index 1b3d313..34c774c 100644 --- a/configs/bf537-stamp_defconfig +++ b/configs/bf537-stamp_defconfig @@ -4,3 +4,10 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig index 2825754..eca4c85 100644 --- a/configs/bf548-ezkit_defconfig +++ b/configs/bf548-ezkit_defconfig @@ -3,5 +3,6 @@ CONFIG_TARGET_BF548_EZKIT=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y CONFIG_LIB_RAND=y diff --git a/configs/bf561-acvilon_defconfig b/configs/bf561-acvilon_defconfig index cb813ea..4a25d2e 100644 --- a/configs/bf561-acvilon_defconfig +++ b/configs/bf561-acvilon_defconfig @@ -6,5 +6,6 @@ CONFIG_SYS_PROMPT="Acvilon> " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y CONFIG_LIB_RAND=y diff --git a/configs/bf609-ezkit_defconfig b/configs/bf609-ezkit_defconfig index 4f9b272..642ca87 100644 --- a/configs/bf609-ezkit_defconfig +++ b/configs/bf609-ezkit_defconfig @@ -3,6 +3,13 @@ CONFIG_TARGET_BF609_EZKIT=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y CONFIG_LIB_RAND=y diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig index 2cb8831..620d621 100644 --- a/configs/bg0900_defconfig +++ b/configs/bg0900_defconfig @@ -6,3 +6,4 @@ CONFIG_SPL=y CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig index 75549d3..d807ea5 100644 --- a/configs/birdland_bav335a_defconfig +++ b/configs/birdland_bav335a_defconfig @@ -8,3 +8,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig index 11ee51a..2ed64f6 100644 --- a/configs/birdland_bav335b_defconfig +++ b/configs/birdland_bav335b_defconfig @@ -8,3 +8,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/blackstamp_defconfig b/configs/blackstamp_defconfig index 762eef3..944145a 100644 --- a/configs/blackstamp_defconfig +++ b/configs/blackstamp_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_BLACKSTAMP=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/blackvme_defconfig b/configs/blackvme_defconfig index 53f4a0d..41b5a23 100644 --- a/configs/blackvme_defconfig +++ b/configs/blackvme_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_BLACKVME=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/br4_defconfig b/configs/br4_defconfig index 272b96e..effba78 100644 --- a/configs/br4_defconfig +++ b/configs/br4_defconfig @@ -6,5 +6,6 @@ CONFIG_SYS_PROMPT="br4>" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y CONFIG_LIB_RAND=y diff --git a/configs/bubinga_defconfig b/configs/bubinga_defconfig index 65ea4d1..1423dc5 100644 --- a/configs/bubinga_defconfig +++ b/configs/bubinga_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_BUBINGA=y +CONFIG_SYS_NS16550=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 343432c..a353aa1 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CADDY2" # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig index 356f549..3844bd4 100644 --- a/configs/cairo_defconfig +++ b/configs/cairo_defconfig @@ -9,3 +9,4 @@ CONFIG_SYS_PROMPT="Cairo # " # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_NET is not set +CONFIG_SYS_NS16550=y diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig index 6dd5b52..374023e 100644 --- a/configs/calimain_defconfig +++ b/configs/calimain_defconfig @@ -6,3 +6,4 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR="\x0b" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig index 44d4fbd..ad7e927 100644 --- a/configs/canyonlands_defconfig +++ b/configs/canyonlands_defconfig @@ -5,3 +5,4 @@ CONFIG_CANYONLANDS=y CONFIG_DEFAULT_DEVICE_TREE="canyonlands" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y +CONFIG_SYS_NS16550=y diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig index c454ffe..c9f565a 100644 --- a/configs/cardhu_defconfig +++ b/configs/cardhu_defconfig @@ -13,6 +13,10 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PCI_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_TEGRA20_SLINK=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index e07a6e4..da47707 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_CHROMEBOOK_JERRY=y CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry" CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set @@ -12,11 +13,13 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_SPL_SYSCON=y CONFIG_LED=y CONFIG_SPL_LED=y CONFIG_LED_GPIO=y @@ -33,10 +36,10 @@ CONFIG_REGULATOR_ACT8846=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART=y -CONFIG_DEBUG_UART_NS16550=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index d68fa41..dbfbb97 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -21,13 +21,18 @@ CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y CONFIG_DEBUG_UART=y -CONFIG_DEBUG_UART_NS16550=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y CONFIG_TPM_TIS_LPC=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index 52336d5..ed4428f 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -20,8 +20,14 @@ CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y CONFIG_TPM_TIS_LPC=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig index f0bfd6f..df16a61 100644 --- a/configs/cm_t335_defconfig +++ b/configs/cm_t335_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_PROMPT="CM-T335 # " # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig index a0cf5d8..1d9af56 100644 --- a/configs/cm_t3517_defconfig +++ b/configs/cm_t3517_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_PROMPT="CM-T3517 # " # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig index 1df085d..1e1591f 100644 --- a/configs/cm_t35_defconfig +++ b/configs/cm_t35_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_PROMPT="CM-T3x # " # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 2432049..6044ae9 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -9,3 +9,4 @@ CONFIG_CMD_USB=y CONFIG_CMD_GPIO=y # CONFIG_CMD_NFS is not set CONFIG_DM=y +CONFIG_SYS_NS16550=y diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig index aa5c755..ccf3807 100644 --- a/configs/cm_t54_defconfig +++ b/configs/cm_t54_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_PROMPT="CM-T54 # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index 5ef21eb..982cee4 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -11,6 +11,7 @@ CONFIG_SYS_PROMPT="Colibri T20 # " # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index 0338363..6dda271 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -11,6 +11,7 @@ CONFIG_SYS_PROMPT="Colibri T30 # " # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig index ae72e33..3df602f 100644 --- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig +++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig @@ -7,5 +7,8 @@ CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD,DEVELOP" CONFIG_CMD_TPM=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y CONFIG_TPM_AUTH_SESSIONS=y CONFIG_TPM=y diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig index 67a185e..c30dfae 100644 --- a/configs/controlcenterd_36BIT_SDCARD_defconfig +++ b/configs/controlcenterd_36BIT_SDCARD_defconfig @@ -7,5 +7,8 @@ CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD" CONFIG_CMD_TPM=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y CONFIG_TPM_AUTH_SESSIONS=y CONFIG_TPM=y diff --git a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig index 14c012e..59072cc 100644 --- a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig +++ b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig @@ -8,5 +8,6 @@ CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP" # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TPM=y CONFIG_DM=y +CONFIG_SYS_NS16550=y CONFIG_TPM_AUTH_SESSIONS=y CONFIG_TPM=y diff --git a/configs/controlcenterd_TRAILBLAZER_defconfig b/configs/controlcenterd_TRAILBLAZER_defconfig index de3b3dd..b1e3a80 100644 --- a/configs/controlcenterd_TRAILBLAZER_defconfig +++ b/configs/controlcenterd_TRAILBLAZER_defconfig @@ -8,5 +8,6 @@ CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH" # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TPM=y CONFIG_DM=y +CONFIG_SYS_NS16550=y CONFIG_TPM_AUTH_SESSIONS=y CONFIG_TPM=y diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig index 5c4260f..cd2be18 100644 --- a/configs/coreboot-x86_defconfig +++ b/configs/coreboot-x86_defconfig @@ -1,7 +1,6 @@ CONFIG_X86=y CONFIG_VENDOR_COREBOOT=y CONFIG_TARGET_COREBOOT=y -CONFIG_TSC_CALIBRATION_BYPASS=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set @@ -13,10 +12,15 @@ CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y CONFIG_OF_CONTROL=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_TIMER=y CONFIG_TPM_TIS_LPC=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 3f9b20a..932d9ec 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -19,11 +19,18 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_CPU=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_PCH_GBE=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO_VESA=y diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index d5f783f..c962a61 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -6,3 +6,5 @@ CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig index ffdabab..c253c38 100644 --- a/configs/da850_am18xxevm_defconfig +++ b/configs/da850_am18xxevm_defconfig @@ -7,3 +7,6 @@ CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 3f2c3c8..75f4eb6 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -8,3 +8,6 @@ CONFIG_SYS_PROMPT="U-Boot > " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 6b0bde2..d8c002f 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -5,3 +5,6 @@ CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT" CONFIG_SYS_PROMPT="U-Boot > " # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index f0b3193..dc5077d 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -13,6 +13,8 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index 6f612d9..cdcd34c 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -8,6 +8,9 @@ CONFIG_SPL=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 258e4d6..4c4329d 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -9,6 +9,9 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_NAND_PXA3XX=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/devconcenter_defconfig b/configs/devconcenter_defconfig index ecf766e..f75bb62 100644 --- a/configs/devconcenter_defconfig +++ b/configs/devconcenter_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_INTIP=y CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER" +CONFIG_SYS_NS16550=y diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index 88cf299..64a0fb0 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -6,3 +6,4 @@ CONFIG_SPL=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_DM=y +CONFIG_SYS_NS16550=y diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index 60ead72..d782f45 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -7,3 +7,4 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig index 04037ba..fe15a4a 100644 --- a/configs/dlvision-10g_defconfig +++ b/configs/dlvision-10g_defconfig @@ -5,3 +5,4 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_ELF is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/dlvision_defconfig b/configs/dlvision_defconfig index 97bdd51..b011cb1 100644 --- a/configs/dlvision_defconfig +++ b/configs/dlvision_defconfig @@ -3,3 +3,4 @@ CONFIG_4xx=y CONFIG_TARGET_DLVISION=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index c56dc5b..1c4e502 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_DNS325=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index 819cf1f..43e6423 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_PROMPT="DockStar> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig index 34393c0..3205bd5 100644 --- a/configs/dra72_evm_defconfig +++ b/configs/dra72_evm_defconfig @@ -17,3 +17,6 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SYS_NS16550=y +CONFIG_TI_QSPI=y diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig index e69ba1a..394edbe 100644 --- a/configs/dra74_evm_defconfig +++ b/configs/dra74_evm_defconfig @@ -15,3 +15,7 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_TI_QSPI=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index fa48505..1be2f5b 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -11,3 +11,6 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SYS_NS16550=y +CONFIG_TI_QSPI=y diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig index f9acfe5..4370b96 100644 --- a/configs/dra7xx_evm_qspiboot_defconfig +++ b/configs/dra7xx_evm_qspiboot_defconfig @@ -11,3 +11,6 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SYS_NS16550=y +CONFIG_TI_QSPI=y diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig index 3965660..204483a 100644 --- a/configs/dra7xx_evm_uart3_defconfig +++ b/configs/dra7xx_evm_uart3_defconfig @@ -12,3 +12,6 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SYS_NS16550=y +CONFIG_TI_QSPI=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index 3338f94..f7174e6 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -10,3 +10,5 @@ CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index ec2a749..966fa9e 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -1,12 +1,14 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_DREAMPLUG=y +CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_SPI_FLASH=y -CONFIG_HUSH_PARSER=y CONFIG_CMD_DHCP=y -CONFIG_CMD_SF=y CONFIG_CMD_PING=y -CONFIG_CMD_USB=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig index f833704..81d089e 100644 --- a/configs/duovero_defconfig +++ b/configs/duovero_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_PROMPT="duovero # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig index 2d5c673..db2d159 100644 --- a/configs/e2220-1170_defconfig +++ b/configs/e2220-1170_defconfig @@ -11,6 +11,8 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig index f38d29c..6fe19c7 100644 --- a/configs/ea20_defconfig +++ b/configs/ea20_defconfig @@ -7,3 +7,5 @@ CONFIG_SYS_PROMPT="ea20 > " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig index 5b1c8dc..9ca47e6 100644 --- a/configs/eco5pk_defconfig +++ b/configs/eco5pk_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_PROMPT="ECO5-PK # " # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig index d2c3f22..6ed785f 100644 --- a/configs/edminiv2_defconfig +++ b/configs/edminiv2_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_EDMINIV2=y CONFIG_SPL=y CONFIG_SYS_PROMPT="EDMiniV2> " # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig index fa53e4a..943ef07 100644 --- a/configs/efi-x86_defconfig +++ b/configs/efi-x86_defconfig @@ -2,7 +2,6 @@ CONFIG_X86=y CONFIG_VENDOR_EFI=y CONFIG_DEFAULT_DEVICE_TREE="efi" CONFIG_TARGET_EFI=y -CONFIG_TSC_CALIBRATION_BYPASS=y # CONFIG_CMD_BOOTM is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_NET is not set @@ -13,5 +12,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEBUG_EFI_CONSOLE=y CONFIG_DEBUG_UART_BASE=0 CONFIG_DEBUG_UART_CLOCK=0 +CONFIG_ICH_SPI=y # CONFIG_X86_SERIAL is not set +CONFIG_TIMER=y CONFIG_EFI=y diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig index 2645d90..04d8611 100644 --- a/configs/ethernut5_defconfig +++ b/configs/ethernut5_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FPGA is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig new file mode 100644 index 0000000..2e915ff --- /dev/null +++ b/configs/evb-rk3036_defconfig @@ -0,0 +1,26 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ROCKCHIP_RK3036=y +CONFIG_TARGET_EVB_RK3036=y +CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CLK=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_RESET=y +CONFIG_LED=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_ROCKCHIP_DWMMC=y +CONFIG_ROCKCHIP_3036_PINCTRL=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_RAM=y +CONFIG_DM_MMC=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 6f42377..be4ca88 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_FIREFLY_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly" CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set @@ -12,11 +13,13 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_SPL_SYSCON=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_RESET=y @@ -34,10 +37,11 @@ CONFIG_REGULATOR_ACT8846=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART=y -CONFIG_DEBUG_UART_NS16550=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/fx12mm_defconfig b/configs/fx12mm_defconfig index da5df04..c714d0d 100644 --- a/configs/fx12mm_defconfig +++ b/configs/fx12mm_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_PROMPT="FX12MM:/# " # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/fx12mm_flash_defconfig b/configs/fx12mm_flash_defconfig index 60eee67..ac38412 100644 --- a/configs/fx12mm_flash_defconfig +++ b/configs/fx12mm_flash_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFF # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 725b37e..0604aa7 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -15,10 +15,16 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/gdppc440etx_defconfig b/configs/gdppc440etx_defconfig index 2dfebbb..9b06cb6 100644 --- a/configs/gdppc440etx_defconfig +++ b/configs/gdppc440etx_defconfig @@ -3,3 +3,4 @@ CONFIG_4xx=y CONFIG_TARGET_GDPPC440ETX=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_SYS_NS16550=y diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig index d318f82..61444ff 100644 --- a/configs/glacier_defconfig +++ b/configs/glacier_defconfig @@ -5,3 +5,4 @@ CONFIG_GLACIER=y CONFIG_DEFAULT_DEVICE_TREE="glacier" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y +CONFIG_SYS_NS16550=y diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig index 98bcaf4..11d7da2 100644 --- a/configs/glacier_ramboot_defconfig +++ b/configs/glacier_ramboot_defconfig @@ -6,3 +6,4 @@ CONFIG_DEFAULT_DEVICE_TREE="glacier" CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds" CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y +CONFIG_SYS_NS16550=y diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index 3f4cd1d..779daf6 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_PROMPT="GoFlexHome> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index b0dfa90..01aa817 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -19,3 +19,4 @@ CONFIG_TARGET_GOSE=y CONFIG_SH_SDHI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig index ab3f760..d2c5e6a 100644 --- a/configs/gplugd_defconfig +++ b/configs/gplugd_defconfig @@ -5,3 +5,6 @@ CONFIG_TARGET_GPLUGD=y # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index b7f79a3..7e20dbb 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -1,11 +1,12 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_GURUPLUG=y +CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_NAND=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_HUSH_PARSER=y CONFIG_CMD_DHCP=y -CONFIG_CMD_NAND=y CONFIG_CMD_PING=y -CONFIG_CMD_USB=y +CONFIG_SYS_NS16550=y diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig new file mode 100644 index 0000000..dc2809a --- /dev/null +++ b/configs/h8_homlet_v2_defconfig @@ -0,0 +1,24 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A83T=y +CONFIG_DRAM_CLK=480 +CONFIG_DRAM_ZQ=15355 +CONFIG_DRAM_ODT_EN=y +#CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +#CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +CONFIG_AXP_GPIO=y +#CONFIG_USB_MUSB_HOST=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_AXP_DCDC1_VOLT=3000 +CONFIG_AXP_DCDC2_VOLT=900 +CONFIG_AXP_DCDC3_VOLT=900 +CONFIG_AXP_DCDC4_VOLT=0 +CONFIG_AXP_DCDC5_VOLT=1500 +CONFIG_AXP_ALDO2_VOLT=0 +CONFIG_AXP_ALDO3_VOLT=0 +CONFIG_AXP_DLDO4_VOLT=0 diff --git a/configs/haleakala_defconfig b/configs/haleakala_defconfig index 81e3398..234bbea 100644 --- a/configs/haleakala_defconfig +++ b/configs/haleakala_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_KILAUEA=y CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA" +CONFIG_SYS_NS16550=y diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index 87ddd84..a3f73cc 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="Tegra20 (Harmony) # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 6b2b5d3..f6c531f 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_HRCON=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index a059dd9..aad015a 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -1,5 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH" - CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_HRCON=y +CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH" +CONFIG_SYS_NS16550=y diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 19cbfd5..a229f46 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -1,12 +1,13 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_IB62X0=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ib62x0 => " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_NAND=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_HUSH_PARSER=y CONFIG_CMD_DHCP=y -CONFIG_CMD_NAND=y CONFIG_CMD_PING=y -CONFIG_CMD_USB=y +CONFIG_SYS_NS16550=y diff --git a/configs/icon_defconfig b/configs/icon_defconfig index 771a093..36fd884 100644 --- a/configs/icon_defconfig +++ b/configs/icon_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_ICON=y +CONFIG_SYS_NS16550=y diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index af1c1fc..3b4d37e 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_PROMPT="iconnect => " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 821c6fa..deafa38 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -8,3 +8,4 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n" CONFIG_AUTOBOOT_DELAY_STR="ids" # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig index b2ce2ad..b9e6711 100644 --- a/configs/igep0020_defconfig +++ b/configs/igep0020_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/igep0020_nand_defconfig b/configs/igep0020_nand_defconfig index 6574c3f..011ebac 100644 --- a/configs/igep0020_nand_defconfig +++ b/configs/igep0020_nand_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig index 726ff12..63ce633 100644 --- a/configs/igep0030_defconfig +++ b/configs/igep0030_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/igep0030_nand_defconfig b/configs/igep0030_nand_defconfig index 54f1ff8..dce7e06 100644 --- a/configs/igep0030_nand_defconfig +++ b/configs/igep0030_nand_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig index cebf1c6..ba160ef 100644 --- a/configs/igep0032_defconfig +++ b/configs/igep0032_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index f314059..2d03974 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -6,3 +6,5 @@ CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y diff --git a/configs/intip_defconfig b/configs/intip_defconfig index 898f544..7893f64 100644 --- a/configs/intip_defconfig +++ b/configs/intip_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_INTIP=y CONFIG_SYS_EXTRA_OPTIONS="INTIB" CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_SYS_NS16550=y diff --git a/configs/io64_defconfig b/configs/io64_defconfig index 52829da..b433cdd 100644 --- a/configs/io64_defconfig +++ b/configs/io64_defconfig @@ -3,3 +3,4 @@ CONFIG_4xx=y CONFIG_TARGET_IO64=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_SYS_NS16550=y diff --git a/configs/io_defconfig b/configs/io_defconfig index 7b71805..17c9c9d 100644 --- a/configs/io_defconfig +++ b/configs/io_defconfig @@ -5,3 +5,4 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_ELF is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig index 63f0c37..a6532d1 100644 --- a/configs/iocon_defconfig +++ b/configs/iocon_defconfig @@ -1,7 +1,9 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_IOCON=y +CONFIG_FIT=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_ELF is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/ip04_defconfig b/configs/ip04_defconfig index 847a25d..e2aa906 100644 --- a/configs/ip04_defconfig +++ b/configs/ip04_defconfig @@ -6,4 +6,6 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y diff --git a/configs/ipam390_defconfig b/configs/ipam390_defconfig index a353beb..b02b496 100644 --- a/configs/ipam390_defconfig +++ b/configs/ipam390_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_PROMPT="U-Boot > " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index bd60d15..efc4aee 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -13,6 +13,9 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PCI_TEGRA=y +CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index c0d8210..9fb9dac 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -11,3 +11,5 @@ CONFIG_SYS_PROMPT="K2E EVM # " CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 4e747ae..7bdf7a4 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -10,3 +10,5 @@ CONFIG_SPL=y CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index d5a4ef2..940d483 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -11,3 +11,5 @@ CONFIG_SYS_PROMPT="K2HK EVM # " CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 47fcad3..1b21ed0 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -11,3 +11,5 @@ CONFIG_SYS_PROMPT="K2L EVM # " CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/katmai_defconfig b/configs/katmai_defconfig index 8492314..a2c4294 100644 --- a/configs/katmai_defconfig +++ b/configs/katmai_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_KATMAI=y +CONFIG_SYS_NS16550=y diff --git a/configs/kilauea_defconfig b/configs/kilauea_defconfig index 0054cc6..5c77b0c 100644 --- a/configs/kilauea_defconfig +++ b/configs/kilauea_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_KILAUEA=y CONFIG_SYS_EXTRA_OPTIONS="KILAUEA" +CONFIG_SYS_NS16550=y diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig index b903f6e..d2625e5 100644 --- a/configs/km_kirkwood_128m16_defconfig +++ b/configs/km_kirkwood_128m16_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig index 7fc1112..4db809e 100644 --- a/configs/km_kirkwood_defconfig +++ b/configs/km_kirkwood_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig index a310fb7..98b1c10 100644 --- a/configs/km_kirkwood_pci_defconfig +++ b/configs/km_kirkwood_pci_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig index 519b39d..b4371ff 100644 --- a/configs/kmcoge4_defconfig +++ b/configs/kmcoge4_defconfig @@ -5,5 +5,9 @@ CONFIG_SYS_EXTRA_OPTIONS="KMCOGE4" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index a8b5275..6623162 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_KM8360=y CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE" +CONFIG_SYS_NS16550=y diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig index 95c61f1..0b4fee1 100644 --- a/configs/kmcoge5un_defconfig +++ b/configs/kmcoge5un_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 3374ab0..98c4cc9 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_KM8360=y CONFIG_SYS_EXTRA_OPTIONS="KMETER1" +CONFIG_SYS_NS16550=y diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig index f948b2b..bf55746 100644 --- a/configs/kmlion1_defconfig +++ b/configs/kmlion1_defconfig @@ -5,5 +5,9 @@ CONFIG_SYS_EXTRA_OPTIONS="KMLION1" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig index 158fe39..13a3187 100644 --- a/configs/kmnusa_defconfig +++ b/configs/kmnusa_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 11c53b5..6d7896e 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2" +CONFIG_SYS_NS16550=y diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig index d754ac0..0f4c51b 100644 --- a/configs/kmsugp1_defconfig +++ b/configs/kmsugp1_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index fd4bb9a..6cc721b 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5" +CONFIG_SYS_NS16550=y diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig index 5f56925..0c27f17 100644 --- a/configs/kmsuv31_defconfig +++ b/configs/kmsuv31_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index aee9886..6acf420 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -1,4 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_SUVD3=y +CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" +CONFIG_SYS_NS16550=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 5cffd53..a4427ac 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -1,4 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="KMTEPR2" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y +CONFIG_SYS_EXTRA_OPTIONS="KMTEPR2" +CONFIG_SYS_NS16550=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 512d12c..c2ee6be 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_SUVD3=y CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" +CONFIG_SYS_NS16550=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index 848aa55..fc8a567 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -19,3 +19,4 @@ CONFIG_TARGET_KOELSCH=y CONFIG_SH_SDHI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/kwb_defconfig b/configs/kwb_defconfig index 0f56bfa..10d39eb 100644 --- a/configs/kwb_defconfig +++ b/configs/kwb_defconfig @@ -19,3 +19,4 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig new file mode 100644 index 0000000..60cdebf --- /dev/null +++ b/configs/kylin-rk3036_defconfig @@ -0,0 +1,26 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ROCKCHIP_RK3036=y +CONFIG_TARGET_KYLIN_RK3036=y +CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CLK=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_RESET=y +CONFIG_LED=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_ROCKCHIP_DWMMC=y +CONFIG_ROCKCHIP_3036_PINCTRL=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_RAM=y +CONFIG_DM_MMC=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index a43aca3..77f1fb3 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -19,3 +19,4 @@ CONFIG_TARGET_LAGER=y CONFIG_SH_SDHI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 940da92..2f16339 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -4,3 +4,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 613fc28..fe84419 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 97d08f1..025a8f2 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -4,3 +4,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index af76fa0..6878df4 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -3,3 +3,4 @@ CONFIG_TARGET_LS1021AQDS=y # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 44c7f50..0f740fd 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -8,5 +8,9 @@ CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y diff --git a/configs/ls1021aqds_sdcard_defconfig b/configs/ls1021aqds_sdcard_defconfig index 0fb637e..3249b48 100644 --- a/configs/ls1021aqds_sdcard_defconfig +++ b/configs/ls1021aqds_sdcard_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 0d2c9a0..bf19c33 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -4,3 +4,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 0a4b3ea..aa874fd 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -3,3 +3,4 @@ CONFIG_TARGET_LS1021ATWR=y # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 5bb52bb..0c71df6 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -8,5 +8,10 @@ CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 2136ab2..f6d4b4a 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -4,3 +4,4 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 9f2d27d..2b4ebd9 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -7,5 +7,10 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig new file mode 100644 index 0000000..60fb0ad --- /dev/null +++ b/configs/ls1043aqds_defconfig @@ -0,0 +1,6 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_SYS_NS16550=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds" +CONFIG_OF_CONTROL=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig new file mode 100644 index 0000000..e9d5afd --- /dev/null +++ b/configs/ls1043aqds_nand_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig new file mode 100644 index 0000000..5221ddb --- /dev/null +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig new file mode 100644 index 0000000..6765d3d --- /dev/null +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig new file mode 100644 index 0000000..d9d6c97 --- /dev/null +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -0,0 +1,9 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043ARDB=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, SECURE_BOOT" +CONFIG_SYS_NS16550=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y
\ No newline at end of file diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index a476360..8622ce7 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -1,3 +1,9 @@ CONFIG_ARM=y CONFIG_TARGET_LS1043ARDB=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_NS16550=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 784ea20..c4f5f60 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -2,3 +2,9 @@ CONFIG_ARM=y CONFIG_TARGET_LS1043ARDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4" +CONFIG_SYS_NS16550=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 4b94e93..6c7eda3 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -2,3 +2,9 @@ CONFIG_ARM=y CONFIG_TARGET_LS1043ARDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4" +CONFIG_SYS_NS16550=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig new file mode 100644 index 0000000..d58d2d0 --- /dev/null +++ b/configs/ls2080a_emu_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080A_EMU=y +CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A" +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_MISC is not set +CONFIG_SYS_NS16550=y diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig new file mode 100644 index 0000000..4c19b89 --- /dev/null +++ b/configs/ls2080a_simu_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080A_SIMU=y +CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A" +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_MISC is not set +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig new file mode 100644 index 0000000..6ac09ce --- /dev/null +++ b/configs/ls2080aqds_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig new file mode 100644 index 0000000..b7d64f6 --- /dev/null +++ b/configs/ls2080aqds_nand_defconfig @@ -0,0 +1,9 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" +# CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig new file mode 100644 index 0000000..1b30114 --- /dev/null +++ b/configs/ls2080ardb_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080ARDB=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig new file mode 100644 index 0000000..daed2e3 --- /dev/null +++ b/configs/ls2080ardb_nand_defconfig @@ -0,0 +1,9 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080ARDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" +# CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls2085a_emu_defconfig b/configs/ls2085a_emu_defconfig index 9c82e17..1c20a27 100644 --- a/configs/ls2085a_emu_defconfig +++ b/configs/ls2085a_emu_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y -CONFIG_TARGET_LS2085A_EMU=y -CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4" +CONFIG_TARGET_LS2080A_EMU=y +CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2085A" # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set @@ -12,3 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_SYS_NS16550=y diff --git a/configs/ls2085a_simu_defconfig b/configs/ls2085a_simu_defconfig index 9d04218..38905ce 100644 --- a/configs/ls2085a_simu_defconfig +++ b/configs/ls2085a_simu_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y -CONFIG_TARGET_LS2085A_SIMU=y -CONFIG_SYS_EXTRA_OPTIONS="SIMU" +CONFIG_TARGET_LS2080A_SIMU=y +CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2085A" # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set @@ -13,3 +13,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SIMU" # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls2085aqds_defconfig b/configs/ls2085aqds_defconfig index 78b121d..b4a1d8c 100644 --- a/configs/ls2085aqds_defconfig +++ b/configs/ls2085aqds_defconfig @@ -1,14 +1,15 @@ CONFIG_ARM=y -CONFIG_TARGET_LS2085AQDS=y +CONFIG_TARGET_LS2080AQDS=y # CONFIG_SYS_MALLOC_F is not set CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-qds" -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2085aqds_nand_defconfig b/configs/ls2085aqds_nand_defconfig index ce2a81c..b6bc7c6 100644 --- a/configs/ls2085aqds_nand_defconfig +++ b/configs/ls2085aqds_nand_defconfig @@ -1,8 +1,9 @@ CONFIG_ARM=y -CONFIG_TARGET_LS2085AQDS=y +CONFIG_TARGET_LS2080AQDS=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A" # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls2085ardb_defconfig b/configs/ls2085ardb_defconfig index d0f16f2..0f514ca 100644 --- a/configs/ls2085ardb_defconfig +++ b/configs/ls2085ardb_defconfig @@ -1,14 +1,15 @@ CONFIG_ARM=y -CONFIG_TARGET_LS2085ARDB=y +CONFIG_TARGET_LS2080ARDB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-rdb" -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2085ardb_nand_defconfig b/configs/ls2085ardb_nand_defconfig index 25a6f71..593b8ca 100644 --- a/configs/ls2085ardb_nand_defconfig +++ b/configs/ls2085ardb_nand_defconfig @@ -1,8 +1,9 @@ CONFIG_ARM=y -CONFIG_TARGET_LS2085ARDB=y +CONFIG_TARGET_LS2080ARDB=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A" # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index a086de8..7264c2d 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -7,3 +7,5 @@ CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2" # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index 7d48abd..62acb40 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -7,3 +7,5 @@ CONFIG_SYS_EXTRA_OPTIONS="LSXHL" # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/luan_defconfig b/configs/luan_defconfig index d42b4a9..7babe26 100644 --- a/configs/luan_defconfig +++ b/configs/luan_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_LUAN=y +CONFIG_SYS_NS16550=y diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig index 0a6da68..5cbca3b 100644 --- a/configs/lwmon5_defconfig +++ b/configs/lwmon5_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_LWMON5=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig index 9e8508c..9da42eb 100644 --- a/configs/m28evk_defconfig +++ b/configs/m28evk_defconfig @@ -5,3 +5,4 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/makalu_defconfig b/configs/makalu_defconfig index ed9b82d..1b71638 100644 --- a/configs/makalu_defconfig +++ b/configs/makalu_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_MAKALU=y +CONFIG_SYS_NS16550=y diff --git a/configs/malta_defconfig b/configs/malta_defconfig index 3056c48..2ebd58b 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -5,4 +5,5 @@ CONFIG_TARGET_MALTA=y # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index 858a852..d24d217 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -6,4 +6,5 @@ CONFIG_SYS_LITTLE_ENDIAN=y # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index a353e85..8495800 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -7,4 +7,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX CONFIG_CMD_GPIO=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_DM_THERMAL=y diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index d49def1..921c6c4 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -8,3 +8,7 @@ CONFIG_SPL=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig index 1d82c40..1e204d5 100644 --- a/configs/mcx_defconfig +++ b/configs/mcx_defconfig @@ -9,3 +9,4 @@ CONFIG_SYS_PROMPT="mcx # " # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index 631159a..6c9e41a 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig index cd5f358..965972a 100644 --- a/configs/mgcoge3un_defconfig +++ b/configs/mgcoge3un_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 1fe2e0f..54aa3ef 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -1,9 +1,9 @@ CONFIG_MICROBLAZE=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_TARGET_MICROBLAZE_GENERIC=y CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" CONFIG_SPL=y CONFIG_SYS_PROMPT="U-Boot-mONStR> " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set -CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 02d43a3..864fd1b 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -20,13 +20,19 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_CPU=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y CONFIG_DEBUG_UART=y -CONFIG_DEBUG_UART_NS16550=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO_VESA=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index 8c67eab..c31d948 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_MPC8308_P1M=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig index 38fb331..a0153e4 100644 --- a/configs/mt_ventoux_defconfig +++ b/configs/mt_ventoux_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_PROMPT="mt_ventoux => " # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig index 1cb26d7..dcabd7b 100644 --- a/configs/mx28evk_auart_console_defconfig +++ b/configs/mx28evk_auart_console_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_M # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index 3c8ea76..d7f0706 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig index bd86917..f4ace44 100644 --- a/configs/mx28evk_nand_defconfig +++ b/configs/mx28evk_nand_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig index d1d8ed7..976ebc2 100644 --- a/configs/mx28evk_spi_defconfig +++ b/configs/mx28evk_spi_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig index 9dea2d2..40d82ca 100644 --- a/configs/mx6dlsabreauto_defconfig +++ b/configs/mx6dlsabreauto_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig index 68f6676..b2cf924 100644 --- a/configs/mx6dlsabresd_defconfig +++ b/configs/mx6dlsabresd_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig index 3e9506a..c44cd8f 100644 --- a/configs/mx6qpsabreauto_defconfig +++ b/configs/mx6qpsabreauto_defconfig @@ -4,3 +4,4 @@ CONFIG_TARGET_MX6QSABREAUTO=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q" CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig index 11d7670..67b9e10 100644 --- a/configs/mx6qsabreauto_defconfig +++ b/configs/mx6qsabreauto_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg, # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 119f63e..8736e31 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -7,4 +7,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX CONFIG_CMD_GPIO=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_DM_THERMAL=y diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig index 7d141d3..63187b3 100644 --- a/configs/mx6qsabresd_defconfig +++ b/configs/mx6qsabresd_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128 # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig index 7a48075..d047309 100644 --- a/configs/mx6sabresd_spl_defconfig +++ b/configs/mx6sabresd_spl_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index d7305b0..5eca5e9 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -8,4 +8,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_THERMAL=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 60aa057..caf0335 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -8,4 +8,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_THERMAL=y diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index b5b289a..2603927 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -6,4 +6,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL" CONFIG_CMD_GPIO=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_THERMAL=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index 6748a6e..eae74a0 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_PROMPT="nas220> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/neo_defconfig b/configs/neo_defconfig index 1ef57ad..a500b5f 100644 --- a/configs/neo_defconfig +++ b/configs/neo_defconfig @@ -3,3 +3,4 @@ CONFIG_4xx=y CONFIG_TARGET_NEO=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index 09df520..87f4f92 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -6,3 +6,5 @@ CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 862a9ae..2e2ee35 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -6,3 +6,5 @@ CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index 1829995..d336ef3 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -6,3 +6,5 @@ CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index 35cb154..667da1b 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -6,3 +6,5 @@ CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index a13452b..949f680 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -6,3 +6,5 @@ CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SYS_NS16550=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index c9aca46..281292d 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 5b1c06c..5ae77e3 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,M # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 9938328..e5c7824 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg, # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index 430b34d..e2a1242 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index 0f49397..3d38c08 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg, # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index c21ba2a..9b44758 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index 21959a6..d7eb39a 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -12,3 +12,4 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig new file mode 100644 index 0000000..6b3f28a --- /dev/null +++ b/configs/nsa310s_defconfig @@ -0,0 +1,13 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_NSA310S=y +CONFIG_SYS_NS16550=y +CONFIG_SYS_PROMPT="nsa310s => " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PING=y +CONFIG_CMD_USB=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index dac8d3a..7fc1bde 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -19,6 +19,8 @@ CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index 7535a17..988f99d 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_SYS_NS16550=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index 168b9a8..89fdf80 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_PROMPT="OMAP3_EVM # " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/omap3_evm_quick_mmc_defconfig b/configs/omap3_evm_quick_mmc_defconfig index 1b6aa7c..1af2b45 100644 --- a/configs/omap3_evm_quick_mmc_defconfig +++ b/configs/omap3_evm_quick_mmc_defconfig @@ -24,3 +24,4 @@ CONFIG_SYS_PROMPT="OMAP3_EVM # " # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_SYS_NS16550=y diff --git a/configs/omap3_evm_quick_nand_defconfig b/configs/omap3_evm_quick_nand_defconfig index 48c2bb1..b53a9c2 100644 --- a/configs/omap3_evm_quick_nand_defconfig +++ b/configs/omap3_evm_quick_nand_defconfig @@ -24,3 +24,4 @@ CONFIG_SYS_PROMPT="OMAP3_EVM # " # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_SYS_NS16550=y diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig index f22b50e..04b3215 100644 --- a/configs/omap3_ha_defconfig +++ b/configs/omap3_ha_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index ab03285..0ff510e 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_PROMPT="OMAP Logic # " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y +CONFIG_SYS_NS16550=y diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig index 51304fd..4c2a17d 100644 --- a/configs/omap3_overo_defconfig +++ b/configs/omap3_overo_defconfig @@ -10,3 +10,4 @@ CONFIG_SYS_PROMPT="Overo # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig index 9b24544..badfde6 100644 --- a/configs/omap3_pandora_defconfig +++ b/configs/omap3_pandora_defconfig @@ -10,3 +10,4 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/omap3_zoom1_defconfig b/configs/omap3_zoom1_defconfig index ccc1170..639000c 100644 --- a/configs/omap3_zoom1_defconfig +++ b/configs/omap3_zoom1_defconfig @@ -7,3 +7,4 @@ CONFIG_TARGET_OMAP3_ZOOM1=y # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig index ce6e8d9..332ed66 100644 --- a/configs/omap4_panda_defconfig +++ b/configs/omap4_panda_defconfig @@ -7,3 +7,4 @@ CONFIG_SPL=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig index 2947508..023ee41 100644 --- a/configs/omap4_sdp4430_defconfig +++ b/configs/omap4_sdp4430_defconfig @@ -8,3 +8,4 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index d136e2c..ba5d9ca 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -6,3 +6,4 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 8aa410d..7c2d6c8 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -7,3 +7,6 @@ CONFIG_SYS_PROMPT="U-Boot > " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 1686139..ea7861d 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index c342315..886698b 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index 530ba4d..4989319 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/openrisc-generic_defconfig b/configs/openrisc-generic_defconfig index 54cd832..47ed8df 100644 --- a/configs/openrisc-generic_defconfig +++ b/configs/openrisc-generic_defconfig @@ -3,3 +3,4 @@ CONFIG_TARGET_OPENRISC_GENERIC=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig new file mode 100644 index 0000000..358caa5 --- /dev/null +++ b/configs/orangepi_pc_defconfig @@ -0,0 +1,14 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=624 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y +# CONFIG_VIDEO is not set +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig new file mode 100644 index 0000000..003a9c6 --- /dev/null +++ b/configs/orangepi_plus_defconfig @@ -0,0 +1,14 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=672 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y +# CONFIG_VIDEO is not set +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig index 6023fa7..a1ecf06 100644 --- a/configs/ot1200_defconfig +++ b/configs/ot1200_defconfig @@ -6,3 +6,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg, # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig index 0c8b44a..5d44d7d 100644 --- a/configs/ot1200_spl_defconfig +++ b/configs/ot1200_spl_defconfig @@ -7,3 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index 07bc339..a7315ce 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -12,6 +12,8 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index b56181c..c41f322 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -12,6 +12,9 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y +CONFIG_PCI_TEGRA=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index eb38077..e6de2da 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -12,6 +12,8 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index 3d6840e..9d7350a 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig index b8739cd..ce7c4bb 100644 --- a/configs/pcm051_rev1_defconfig +++ b/configs/pcm051_rev1_defconfig @@ -7,3 +7,5 @@ CONFIG_SYS_EXTRA_OPTIONS="REV1" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index 3a47313..7c2dee4 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -7,3 +7,5 @@ CONFIG_SYS_EXTRA_OPTIONS="REV3" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index 08ccfc3..65c6044 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -21,6 +21,8 @@ CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PMIC=y CONFIG_PMIC_TPS65090=y CONFIG_DM_REGULATOR=y @@ -30,6 +32,7 @@ CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y CONFIG_SOUND_MAX98095=y CONFIG_SOUND_WM8994=y +CONFIG_EXYNOS_SPI=y CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index 938ee68..272988f 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -21,6 +21,8 @@ CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PMIC=y CONFIG_PMIC_TPS65090=y CONFIG_DM_REGULATOR=y @@ -30,6 +32,7 @@ CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y CONFIG_SOUND_MAX98095=y CONFIG_SOUND_WM8994=y +CONFIG_EXYNOS_SPI=y CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig index 3350b6f..00a3dac 100644 --- a/configs/pengwyn_defconfig +++ b/configs/pengwyn_defconfig @@ -5,3 +5,4 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig index a038020..62bb80a 100644 --- a/configs/pepper_defconfig +++ b/configs/pepper_defconfig @@ -6,3 +6,4 @@ CONFIG_SYS_PROMPT="pepper# " # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig deleted file mode 100644 index 4474ec3..0000000 --- a/configs/ph1_sld8_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_UNIPHIER=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_ARCH_UNIPHIER_PH1_SLD8=y -CONFIG_MICRO_SUPPORT_CARD=y -CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref" -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -# CONFIG_CMD_FPGA is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_PING=y -CONFIG_CMD_TIME=y -# CONFIG_CMD_MISC is not set -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_SIMPLE_BUS=y -CONFIG_NAND_DENALI=y -CONFIG_SYS_NAND_DENALI_64BIT=y -CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 -CONFIG_SPL_NAND_DENALI=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_UNIPHIER_SERIAL=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig index d19f14f..c2c4638 100644 --- a/configs/plutux_defconfig +++ b/configs/plutux_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="Tegra20 (Plutux) # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index 234833b..1a31256 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_PROMPT="PogoE02> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/porter_defconfig b/configs/porter_defconfig index b7c99de..44f2387 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -19,3 +19,4 @@ CONFIG_TARGET_PORTER=y CONFIG_SH_SDHI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/portl2_defconfig b/configs/portl2_defconfig index 3ff9ebb..0efc4c6 100644 --- a/configs/portl2_defconfig +++ b/configs/portl2_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="KM_PORTL2" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/pr1_defconfig b/configs/pr1_defconfig index f3029dc..c813502 100644 --- a/configs/pr1_defconfig +++ b/configs/pr1_defconfig @@ -6,5 +6,6 @@ CONFIG_SYS_PROMPT="pr1>" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y CONFIG_LIB_RAND=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 75c6f64..02984ed 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -10,3 +10,5 @@ CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index b05c722..d28532c 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -5,3 +5,4 @@ CONFIG_TARGET_QEMU_PPCE500=y # CONFIG_CMD_FLASH is not set CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 366ccc4..8c86931 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -15,10 +15,15 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_CPU=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO_VESA=y diff --git a/configs/qemu_mips64_defconfig b/configs/qemu_mips64_defconfig index 4187430..2bc92a5 100644 --- a/configs/qemu_mips64_defconfig +++ b/configs/qemu_mips64_defconfig @@ -4,4 +4,5 @@ CONFIG_CPU_MIPS64_R1=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/qemu_mips64el_defconfig b/configs/qemu_mips64el_defconfig index c8bcbb7..d8a9c71 100644 --- a/configs/qemu_mips64el_defconfig +++ b/configs/qemu_mips64el_defconfig @@ -5,4 +5,5 @@ CONFIG_CPU_MIPS64_R1=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/qemu_mips_defconfig b/configs/qemu_mips_defconfig index 337ecea..e855906 100644 --- a/configs/qemu_mips_defconfig +++ b/configs/qemu_mips_defconfig @@ -3,4 +3,5 @@ CONFIG_TARGET_QEMU_MIPS=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/qemu_mipsel_defconfig b/configs/qemu_mipsel_defconfig index bfb3bcc..d851075 100644 --- a/configs/qemu_mipsel_defconfig +++ b/configs/qemu_mipsel_defconfig @@ -4,4 +4,5 @@ CONFIG_SYS_LITTLE_ENDIAN=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/rainier_defconfig b/configs/rainier_defconfig index 1713592..cffc355 100644 --- a/configs/rainier_defconfig +++ b/configs/rainier_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_SEQUOIA=y CONFIG_SYS_EXTRA_OPTIONS="RAINIER" +CONFIG_SYS_NS16550=y diff --git a/configs/rainier_ramboot_defconfig b/configs/rainier_ramboot_defconfig index ba22d9d..9766835 100644 --- a/configs/rainier_ramboot_defconfig +++ b/configs/rainier_ramboot_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_SEQUOIA=y CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds" +CONFIG_SYS_NS16550=y diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index f0e622d..a1403fb 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -10,3 +10,5 @@ CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/redwood_defconfig b/configs/redwood_defconfig index ad87d0e..3b7cebb 100644 --- a/configs/redwood_defconfig +++ b/configs/redwood_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_REDWOOD=y +CONFIG_SYS_NS16550=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index bdd9173..3cf82c3 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -7,4 +7,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg, CONFIG_CMD_GPIO=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y CONFIG_DM_THERMAL=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index ba73dc3..4c1fd4b 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -10,3 +10,5 @@ CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig new file mode 100644 index 0000000..c1dcbef --- /dev/null +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D2_XPLAINED=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_SPI_FLASH=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig new file mode 100644 index 0000000..0271e8e --- /dev/null +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D2_XPLAINED=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_SPI_FLASH=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index e953d0a..644b150 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FPGA is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index 832b9eb..1e42880 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FPGA is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index bcfc65b..724b55b 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH" # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FPGA is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 42d302c..3daac36 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -9,3 +9,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index d27f572..e3517e8 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -9,3 +9,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index e5d026a..1cdb9bc 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -9,3 +9,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index 82fa9d4..a75705a 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -9,3 +9,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index a333e06..346a890 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -9,3 +9,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index fc6dbb0..efba861 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -9,3 +9,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 0178674..731fc25 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -22,7 +22,9 @@ CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 CONFIG_OF_CONTROL=y CONFIG_OF_HOSTFILE=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y CONFIG_DEVRES=y CONFIG_ADC=y CONFIG_ADC_SANDBOX=y @@ -39,8 +41,17 @@ CONFIG_RESET=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH_SANDBOX=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index c03a807..068b1b6 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M" # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 030c2d6..9939155 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M" # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 01392aa..f1e356d 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig index b6e8766..bf1f0a5 100644 --- a/configs/sbc8548_PCI_33_PCIE_defconfig +++ b/configs/sbc8548_PCI_33_PCIE_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC85xx=y CONFIG_TARGET_SBC8548=y CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE" # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig index f3c4ced..789333e 100644 --- a/configs/sbc8548_PCI_33_defconfig +++ b/configs/sbc8548_PCI_33_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC85xx=y CONFIG_TARGET_SBC8548=y CONFIG_SYS_EXTRA_OPTIONS="PCI,33" # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig index bb0ad95..e0f3752 100644 --- a/configs/sbc8548_PCI_66_PCIE_defconfig +++ b/configs/sbc8548_PCI_66_PCIE_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC85xx=y CONFIG_TARGET_SBC8548=y CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE" # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig index d601416..132e66d 100644 --- a/configs/sbc8548_PCI_66_defconfig +++ b/configs/sbc8548_PCI_66_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC85xx=y CONFIG_TARGET_SBC8548=y CONFIG_SYS_EXTRA_OPTIONS="PCI,66" # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig index 3e3b507..b8d9d5a 100644 --- a/configs/sbc8548_defconfig +++ b/configs/sbc8548_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_SBC8548=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig index b67c7c0..a37b18e 100644 --- a/configs/sbc8641d_defconfig +++ b/configs/sbc8641d_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC86xx=y CONFIG_TARGET_SBC8641D=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index bcce38c..ad16a10 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sequoia_defconfig b/configs/sequoia_defconfig index bbaec61..39190a3 100644 --- a/configs/sequoia_defconfig +++ b/configs/sequoia_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_SEQUOIA=y CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA" +CONFIG_SYS_NS16550=y diff --git a/configs/sequoia_ramboot_defconfig b/configs/sequoia_ramboot_defconfig index 5b2c6f4..b86b230 100644 --- a/configs/sequoia_ramboot_defconfig +++ b/configs/sequoia_ramboot_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_SEQUOIA=y CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds" +CONFIG_SYS_NS16550=y diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig index b748e37..4c8883b 100644 --- a/configs/sh7752evb_defconfig +++ b/configs/sh7752evb_defconfig @@ -18,4 +18,6 @@ CONFIG_TARGET_SH7752EVB=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_MISC is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig index 7bac054..9992cff 100644 --- a/configs/sh7753evb_defconfig +++ b/configs/sh7753evb_defconfig @@ -17,4 +17,6 @@ CONFIG_TARGET_SH7753EVB=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_MISC is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig index 1a253dc..54d6436 100644 --- a/configs/sh7757lcr_defconfig +++ b/configs/sh7757lcr_defconfig @@ -18,4 +18,5 @@ CONFIG_TARGET_SH7757LCR=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_MISC is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 5a37eea..9b41460 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -1,11 +1,12 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_SHEEVAPLUG=y +CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_NAND=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_HUSH_PARSER=y CONFIG_CMD_DHCP=y -CONFIG_CMD_NAND=y CONFIG_CMD_PING=y -CONFIG_CMD_USB=y +CONFIG_SYS_NS16550=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 5afcde3..836beff 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -19,3 +19,4 @@ CONFIG_TARGET_SILK=y CONFIG_SH_SDHI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig index 17b2a35..b0dec29 100644 --- a/configs/smdk5250_defconfig +++ b/configs/smdk5250_defconfig @@ -13,6 +13,8 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_DM_I2C_COMPAT=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_MAX77686=y CONFIG_DM_REGULATOR=y @@ -22,6 +24,7 @@ CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y CONFIG_SOUND_MAX98095=y CONFIG_SOUND_WM8994=y +CONFIG_EXYNOS_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO_BRIDGE=y diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig index 9d58ac1..50148fc 100644 --- a/configs/smdk5420_defconfig +++ b/configs/smdk5420_defconfig @@ -10,8 +10,11 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_DM_I2C_COMPAT=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_EXYNOS_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_VIDEO_BRIDGE=y diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig index 7afaa49..0474deb 100644 --- a/configs/sniper_defconfig +++ b/configs/sniper_defconfig @@ -6,5 +6,6 @@ CONFIG_SYS_PROMPT="Sniper # " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_MUSB_GADGET=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index 41441a8..3d8081b 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -22,6 +22,8 @@ CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_MAX77686=y CONFIG_PMIC_S5M8767=y @@ -39,6 +41,7 @@ CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y CONFIG_SOUND_MAX98095=y CONFIG_SOUND_WM8994=y +CONFIG_EXYNOS_SPI=y CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index a1245e2..68d12df 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -11,7 +11,17 @@ CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_SPL_SIMPLE_BUS=y CONFIG_DWAPB_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y +CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 74ce232..accee92 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -11,7 +11,17 @@ CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_SPL_SIMPLE_BUS=y CONFIG_DWAPB_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y +CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 5837e98..65c1197 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -15,3 +15,9 @@ CONFIG_SPL_SIMPLE_BUS=y CONFIG_DWAPB_GPIO=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 455ea95..c98d4a1 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -15,3 +15,9 @@ CONFIG_SPL_SIMPLE_BUS=y CONFIG_DWAPB_GPIO=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 4ab373f..b4f41a9 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -14,6 +14,14 @@ CONFIG_CMD_GPIO=y CONFIG_SPL_SIMPLE_BUS=y CONFIG_DWAPB_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 07b8447..fe940f9 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_DM=y CONFIG_DM_GPIO=y -CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y +CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" CONFIG_SPL=y @@ -11,7 +11,16 @@ CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_SPL_SIMPLE_BUS=y CONFIG_DWAPB_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig new file mode 100644 index 0000000..3d98a63 --- /dev/null +++ b/configs/socfpga_sr1500_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_DM=y +CONFIG_DM_GPIO=y +CONFIG_TARGET_SOCFPGA_SR1500=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x00800000 +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_SPL_SIMPLE_BUS=y +CONFIG_DWAPB_GPIO=y +CONFIG_SPI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_DM_MMC=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 37af82e..19cc388 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -3,3 +3,4 @@ CONFIG_MPC85xx=y CONFIG_TARGET_SOCRATES=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/spring_defconfig b/configs/spring_defconfig index 0f44ce8..11cb6e3 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -22,6 +22,8 @@ CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_MAX77686=y CONFIG_PMIC_S5M8767=y @@ -39,6 +41,7 @@ CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y CONFIG_SOUND_MAX98095=y CONFIG_SOUND_WM8994=y +CONFIG_EXYNOS_SPI=y CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index fcfc5c1..d353495 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -19,3 +19,4 @@ CONFIG_TARGET_STOUT=y CONFIG_SH_SDHI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 74ef69e..59fdc7b 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -1,7 +1,8 @@ -CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON" CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index fc0a823..a0584b8 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -1,7 +1,8 @@ -CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU" CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU" CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 60de787..cce8818 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -11,5 +11,8 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y +CONFIG_CADENCE_QSPI=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index e477b0e..b0b8390 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_SUVD3=y CONFIG_SYS_EXTRA_OPTIONS="SUVD3" +CONFIG_SYS_NS16550=y diff --git a/configs/sycamore_defconfig b/configs/sycamore_defconfig index 844e67f..29b3d2b 100644 --- a/configs/sycamore_defconfig +++ b/configs/sycamore_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_WALNUT=y +CONFIG_SYS_NS16550=y diff --git a/configs/t3corp_defconfig b/configs/t3corp_defconfig index c61508a..75eeda6 100644 --- a/configs/t3corp_defconfig +++ b/configs/t3corp_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_T3CORP=y +CONFIG_SYS_NS16550=y diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig index b2977f3..af4292b 100644 --- a/configs/tao3530_defconfig +++ b/configs/tao3530_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_PROMPT="TAO-3530 # " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index ec1566f..d59912c 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -12,3 +12,4 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig index ca34bbb..27ea43f 100644 --- a/configs/tb100_defconfig +++ b/configs/tb100_defconfig @@ -14,4 +14,5 @@ CONFIG_OF_EMBED=y CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig index 7a8d687..3d10fd0 100644 --- a/configs/tec-ng_defconfig +++ b/configs/tec-ng_defconfig @@ -13,6 +13,9 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y +CONFIG_TEGRA20_SLINK=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/tec_defconfig b/configs/tec_defconfig index a4d5ac6..ea3c369 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="Tegra20 (TEC) # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index 70420f0..13aade6 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -10,3 +10,5 @@ CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig index 781e270..0c9a9d1 100644 --- a/configs/ti814x_evm_defconfig +++ b/configs/ti814x_evm_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_PROMPT="U-Boot# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig index 294d775..78f11f5 100644 --- a/configs/ti816x_evm_defconfig +++ b/configs/ti816x_evm_defconfig @@ -5,3 +5,4 @@ CONFIG_SYS_PROMPT="u-boot/ti816x# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig index 827b5be..cdc51c0 100644 --- a/configs/tqma6q_mba6_mmc_defconfig +++ b/configs/tqma6q_mba6_mmc_defconfig @@ -5,3 +5,4 @@ CONFIG_TARGET_TQMA6=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig index 9bfb539..1408be3 100644 --- a/configs/tqma6q_mba6_spi_defconfig +++ b/configs/tqma6q_mba6_spi_defconfig @@ -6,3 +6,4 @@ CONFIG_TQMA6X_SPI_BOOT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig index 9b8ae93..4e5428b 100644 --- a/configs/tqma6s_mba6_mmc_defconfig +++ b/configs/tqma6s_mba6_mmc_defconfig @@ -6,3 +6,4 @@ CONFIG_TQMA6S=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig index c1d06ec..04740ec 100644 --- a/configs/tqma6s_mba6_spi_defconfig +++ b/configs/tqma6s_mba6_spi_defconfig @@ -7,3 +7,4 @@ CONFIG_TQMA6X_SPI_BOOT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig index bc30837..c32ef86 100644 --- a/configs/tricorder_defconfig +++ b/configs/tricorder_defconfig @@ -10,3 +10,4 @@ CONFIG_SYS_PROMPT="OMAP3 Tricorder # " # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig index 4619fc9..1cf3928 100644 --- a/configs/tricorder_flash_defconfig +++ b/configs/tricorder_flash_defconfig @@ -10,3 +10,4 @@ CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig index be65652..e34faa3 100644 --- a/configs/trimslice_defconfig +++ b/configs/trimslice_defconfig @@ -13,6 +13,10 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PCI_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_TEGRA20_SFLASH=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/tseries_mmc_defconfig b/configs/tseries_mmc_defconfig index 9b096ed..7518774 100644 --- a/configs/tseries_mmc_defconfig +++ b/configs/tseries_mmc_defconfig @@ -16,3 +16,4 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/tseries_nand_defconfig b/configs/tseries_nand_defconfig index ffce135..65d514a 100644 --- a/configs/tseries_nand_defconfig +++ b/configs/tseries_nand_defconfig @@ -16,3 +16,4 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y diff --git a/configs/tseries_spi_defconfig b/configs/tseries_spi_defconfig index 6703b17..11e4e6b 100644 --- a/configs/tseries_spi_defconfig +++ b/configs/tseries_spi_defconfig @@ -17,3 +17,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index d4a422c..1030dc7 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y CONFIG_SYS_EXTRA_OPTIONS="TUGE1" +CONFIG_SYS_NS16550=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index c8db21a..7675fb3 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y CONFIG_SYS_EXTRA_OPTIONS="TUXX1" +CONFIG_SYS_NS16550=y diff --git a/configs/twister_defconfig b/configs/twister_defconfig index ec85267..e721edb 100644 --- a/configs/twister_defconfig +++ b/configs/twister_defconfig @@ -7,3 +7,4 @@ CONFIG_SYS_PROMPT="twister => " # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/ph1_ld4_defconfig b/configs/uniphier_ld4_sld8_defconfig index 2ddd1eb..ee3cbad 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ARCH_UNIPHIER_PH1_LD4=y +CONFIG_ARCH_UNIPHIER_PH1_SLD8=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" diff --git a/configs/ph1_pro4_defconfig b/configs/uniphier_pro4_defconfig index 2361db6..2361db6 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/uniphier_pro4_defconfig diff --git a/configs/ph1_pro5_defconfig b/configs/uniphier_pro5_defconfig index be0d7b5..be0d7b5 100644 --- a/configs/ph1_pro5_defconfig +++ b/configs/uniphier_pro5_defconfig diff --git a/configs/ph1_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig index bbcb344..f8cb794 100644 --- a/configs/ph1_ld6b_defconfig +++ b/configs/uniphier_pxs2_ld6b_defconfig @@ -1,10 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ARCH_UNIPHIER_PROXSTREAM2=y CONFIG_ARCH_UNIPHIER_PH1_LD6B=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld6b-ref" +CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka" CONFIG_HUSH_PARSER=y # CONFIG_CMD_XIMG is not set # CONFIG_CMD_ENV_EXISTS is not set diff --git a/configs/ph1_sld3_defconfig b/configs/uniphier_sld3_defconfig index 4b871d0..4b871d0 100644 --- a/configs/ph1_sld3_defconfig +++ b/configs/uniphier_sld3_defconfig diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig index 0c30ae9..4b0b5b4 100644 --- a/configs/vct_platinum_defconfig +++ b/configs/vct_platinum_defconfig @@ -3,4 +3,5 @@ CONFIG_TARGET_VCT=y CONFIG_VCT_PLATINUM=y CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig index e26c2f6..62d8878 100644 --- a/configs/vct_platinum_onenand_defconfig +++ b/configs/vct_platinum_onenand_defconfig @@ -6,4 +6,5 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_platinum_onenand_small_defconfig b/configs/vct_platinum_onenand_small_defconfig index 47985cd..7b379be 100644 --- a/configs/vct_platinum_onenand_small_defconfig +++ b/configs/vct_platinum_onenand_small_defconfig @@ -18,4 +18,5 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_platinum_small_defconfig b/configs/vct_platinum_small_defconfig index f85d3f7..78d215d 100644 --- a/configs/vct_platinum_small_defconfig +++ b/configs/vct_platinum_small_defconfig @@ -15,4 +15,5 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_platinumavc_defconfig b/configs/vct_platinumavc_defconfig index 103434c..92a3027 100644 --- a/configs/vct_platinumavc_defconfig +++ b/configs/vct_platinumavc_defconfig @@ -5,4 +5,5 @@ CONFIG_SYS_PROMPT="VCT# " # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_platinumavc_onenand_defconfig b/configs/vct_platinumavc_onenand_defconfig index e387b82..87767bd 100644 --- a/configs/vct_platinumavc_onenand_defconfig +++ b/configs/vct_platinumavc_onenand_defconfig @@ -8,4 +8,5 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_platinumavc_onenand_small_defconfig b/configs/vct_platinumavc_onenand_small_defconfig index 77dd414..be70588 100644 --- a/configs/vct_platinumavc_onenand_small_defconfig +++ b/configs/vct_platinumavc_onenand_small_defconfig @@ -18,4 +18,5 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_platinumavc_small_defconfig b/configs/vct_platinumavc_small_defconfig index 8fe82fc..b7e0a78 100644 --- a/configs/vct_platinumavc_small_defconfig +++ b/configs/vct_platinumavc_small_defconfig @@ -15,4 +15,5 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig index 2ae4975..7ca6e34 100644 --- a/configs/vct_premium_defconfig +++ b/configs/vct_premium_defconfig @@ -3,4 +3,5 @@ CONFIG_TARGET_VCT=y CONFIG_VCT_PREMIUM=y CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig index 9768dbc..88555d9 100644 --- a/configs/vct_premium_onenand_defconfig +++ b/configs/vct_premium_onenand_defconfig @@ -6,4 +6,5 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_premium_onenand_small_defconfig b/configs/vct_premium_onenand_small_defconfig index ac6f422..a3a93b8 100644 --- a/configs/vct_premium_onenand_small_defconfig +++ b/configs/vct_premium_onenand_small_defconfig @@ -18,4 +18,5 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vct_premium_small_defconfig b/configs/vct_premium_small_defconfig index 3297434..fddc04d 100644 --- a/configs/vct_premium_small_defconfig +++ b/configs/vct_premium_small_defconfig @@ -15,4 +15,5 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_SYS_NS16550=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 627bb3c..5a8ba8e 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_VE8313=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index a93c139..05f6bc4 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -13,6 +13,8 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index 01dad0e..3423f24 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="Tegra20 (Ventana) # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig index 72d405f..cad4466 100644 --- a/configs/vexpress_aemv8a_dram_defconfig +++ b/configs/vexpress_aemv8a_dram_defconfig @@ -10,7 +10,6 @@ CONFIG_SYS_PROMPT="VExpress64# " # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_ENV_EXISTS is not set # CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index a082d27..e899b90 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -10,7 +10,6 @@ CONFIG_SYS_PROMPT="VExpress64# " # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_ENV_EXISTS is not set # CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 117a154..7a91da3 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC83xx=y CONFIG_TARGET_VME8349=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/walnut_defconfig b/configs/walnut_defconfig index 844e67f..29b3d2b 100644 --- a/configs/walnut_defconfig +++ b/configs/walnut_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_WALNUT=y +CONFIG_SYS_NS16550=y diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig index 995cf36..9fa9664 100644 --- a/configs/whistler_defconfig +++ b/configs/whistler_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="Tegra20 (Whistler) # " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 1c22eaf..1cad3a2 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -7,3 +7,4 @@ CONFIG_SPL=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_DM=y +CONFIG_SYS_NS16550=y diff --git a/configs/x600_defconfig b/configs/x600_defconfig index a1b2e33..71dc7dc 100644 --- a/configs/x600_defconfig +++ b/configs/x600_defconfig @@ -9,3 +9,4 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y +CONFIG_USE_TINY_PRINTF=y diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 79304c1..dd2a9ed 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_ZYNQMP=y CONFIG_ZYNQMP_USB=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set @@ -22,4 +24,5 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ZYNQ_GEM=y # CONFIG_REGEX is not set diff --git a/configs/xpedite1000_defconfig b/configs/xpedite1000_defconfig index 73d5ff2..3bccacb 100644 --- a/configs/xpedite1000_defconfig +++ b/configs/xpedite1000_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_XPEDITE1000=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig index 45d0ae1..07c4642 100644 --- a/configs/xpedite517x_defconfig +++ b/configs/xpedite517x_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC86xx=y CONFIG_TARGET_XPEDITE517X=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig index 797c166..6a25b47 100644 --- a/configs/xpedite520x_defconfig +++ b/configs/xpedite520x_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_XPEDITE520X=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig index 2db7f65..611f1b1 100644 --- a/configs/xpedite537x_defconfig +++ b/configs/xpedite537x_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_XPEDITE537X=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig index 2740957..8f6b433 100644 --- a/configs/xpedite550x_defconfig +++ b/configs/xpedite550x_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_XPEDITE550X=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/configs/yellowstone_defconfig b/configs/yellowstone_defconfig index 7b1a630..7f4144c 100644 --- a/configs/yellowstone_defconfig +++ b/configs/yellowstone_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_YOSEMITE=y CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE" +CONFIG_SYS_NS16550=y diff --git a/configs/yosemite_defconfig b/configs/yosemite_defconfig index 00ec425..cd852c2 100644 --- a/configs/yosemite_defconfig +++ b/configs/yosemite_defconfig @@ -2,3 +2,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_YOSEMITE=y CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE" +CONFIG_SYS_NS16550=y diff --git a/configs/yucca_defconfig b/configs/yucca_defconfig index 6c8e20a..c3e7a7a 100644 --- a/configs/yucca_defconfig +++ b/configs/yucca_defconfig @@ -1,3 +1,4 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_YUCCA=y +CONFIG_SYS_NS16550=y diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 6cbf8ac..e577c93 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -12,4 +12,8 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ZYNQ_GEM=y CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index 600ca8b..7d52d8e 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -8,3 +8,4 @@ CONFIG_SPL=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ZYNQ_GEM=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 2b51deb..9d1b40d 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -11,4 +11,12 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xe0001000 +CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 0bc53a8..bba91df 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -12,4 +12,8 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ZYNQ_GEM=y CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 17833e7..96f0a79 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -13,4 +13,10 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SPI=y CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 49dd025..b0c535e 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -12,3 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ZYNQ_GEM=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index d505943..7fb03eb 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -10,3 +10,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ZYNQ_GEM=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index c2ae2ab..6766512 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -12,3 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ZYNQ_GEM=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 15efb19..058bb05 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -12,4 +12,8 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_ZYNQ_GEM=y CONFIG_ZYNQ_QSPI=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 1227b7a..231483e 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -11,7 +11,11 @@ CONFIG_FIT_SIGNATURE=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xe0001000 CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_ZYNQ_QSPI=y diff --git a/disk/part_efi.c b/disk/part_efi.c index ea9c615..b1e0155 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -493,6 +493,9 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e, memset(&gpt_e[i].attributes, 0, sizeof(gpt_entry_attributes)); + if (partitions[i].bootable) + gpt_e[i].attributes.fields.legacy_bios_bootable = 1; + /* partition name */ efiname_len = sizeof(gpt_e[i].partition_name) / sizeof(efi_char16_t); @@ -578,6 +581,116 @@ err: return ret; } +static void gpt_convert_efi_name_to_char(char *s, efi_char16_t *es, int n) +{ + char *ess = (char *)es; + int i, j; + + memset(s, '\0', n); + + for (i = 0, j = 0; j < n; i += 2, j++) { + s[j] = ess[i]; + if (!ess[i]) + return; + } +} + +int gpt_verify_headers(block_dev_desc_t *dev_desc, gpt_header *gpt_head, + gpt_entry **gpt_pte) +{ + /* + * This function validates AND + * fills in the GPT header and PTE + */ + if (is_gpt_valid(dev_desc, + GPT_PRIMARY_PARTITION_TABLE_LBA, + gpt_head, gpt_pte) != 1) { + printf("%s: *** ERROR: Invalid GPT ***\n", + __func__); + return -1; + } + if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), + gpt_head, gpt_pte) != 1) { + printf("%s: *** ERROR: Invalid Backup GPT ***\n", + __func__); + return -1; + } + + return 0; +} + +int gpt_verify_partitions(block_dev_desc_t *dev_desc, + disk_partition_t *partitions, int parts, + gpt_header *gpt_head, gpt_entry **gpt_pte) +{ + char efi_str[PARTNAME_SZ + 1]; + u64 gpt_part_size; + gpt_entry *gpt_e; + int ret, i; + + ret = gpt_verify_headers(dev_desc, gpt_head, gpt_pte); + if (ret) + return ret; + + gpt_e = *gpt_pte; + + for (i = 0; i < parts; i++) { + if (i == gpt_head->num_partition_entries) { + error("More partitions than allowed!\n"); + return -1; + } + + /* Check if GPT and ENV partition names match */ + gpt_convert_efi_name_to_char(efi_str, gpt_e[i].partition_name, + PARTNAME_SZ + 1); + + debug("%s: part: %2d name - GPT: %16s, ENV: %16s ", + __func__, i, efi_str, partitions[i].name); + + if (strncmp(efi_str, (char *)partitions[i].name, + sizeof(partitions->name))) { + error("Partition name: %s does not match %s!\n", + efi_str, (char *)partitions[i].name); + return -1; + } + + /* Check if GPT and ENV sizes match */ + gpt_part_size = le64_to_cpu(gpt_e[i].ending_lba) - + le64_to_cpu(gpt_e[i].starting_lba) + 1; + debug("size(LBA) - GPT: %8llu, ENV: %8llu ", + gpt_part_size, (u64) partitions[i].size); + + if (le64_to_cpu(gpt_part_size) != partitions[i].size) { + error("Partition %s size: %llu does not match %llu!\n", + efi_str, gpt_part_size, (u64) partitions[i].size); + return -1; + } + + /* + * Start address is optional - check only if provided + * in '$partition' variable + */ + if (!partitions[i].start) { + debug("\n"); + continue; + } + + /* Check if GPT and ENV start LBAs match */ + debug("start LBA - GPT: %8llu, ENV: %8llu\n", + le64_to_cpu(gpt_e[i].starting_lba), + (u64) partitions[i].start); + + if (le64_to_cpu(gpt_e[i].starting_lba) != partitions[i].start) { + error("Partition %s start: %llu does not match %llu!\n", + efi_str, le64_to_cpu(gpt_e[i].starting_lba), + (u64) partitions[i].start); + return -1; + } + } + + return 0; +} + int is_valid_gpt_buf(block_dev_desc_t *dev_desc, void *buf) { gpt_header *gpt_h; diff --git a/doc/README.fsl-trustzone-components b/doc/README.fsl-trustzone-components index a3afd1f..e122346 100644 --- a/doc/README.fsl-trustzone-components +++ b/doc/README.fsl-trustzone-components @@ -1,4 +1,4 @@ -Freescale ARM64 SoCs like LS2085A have ARM TrustZone components like +Freescale ARM64 SoCs like LS2080A have ARM TrustZone components like TZPC-BP147 (TrustZone Protection Controller) and TZASC-400 (TrustZone Address Space Controller). @@ -7,7 +7,7 @@ is left to a root-of-trust security software layer (running in EL3 privilege mode), but still some configurations of these peripherals might be required while the bootloader is executing in EL3 privilege mode. The following sections define how to turn on these features for -LS2085A like SoCs. +LS2080A like SoCs. TZPC-BP147 (TrustZone Protection Controller) ============================================ diff --git a/doc/README.gpt b/doc/README.gpt index 35902ce..a6f6de6 100644 --- a/doc/README.gpt +++ b/doc/README.gpt @@ -142,6 +142,10 @@ of the Primary. Attribute flags: Bit 0 - System partition + Bit 1 - Hide from EFI + Bit 2 - Legacy BIOS bootable + Bit 48-63 - Defined and used by the individual partition type + For Basic data partition : Bit 60 - Read-only Bit 62 - Hidden Bit 63 - Not mount @@ -161,16 +165,51 @@ To restore GUID partition table one needs to: The fields 'name' and 'size' are mandatory for every partition. The field 'start' is optional. + If field 'size' of the last partition is 0, the partiton is extended + up to the end of the device. + The fields 'uuid' and 'uuid_disk' are optional if CONFIG_RANDOM_UUID is enabled. A random uuid will be used if omitted or they point to an empty/ non-existent environment variable. The environment variable will be set to the generated UUID. + The field 'bootable' is optional, it is used to mark the GPT partition + bootable (set attribute flags "Legacy BIOS bootable"). + "name=u-boot,size=60MiB;name=boot,size=60Mib,bootable;name=rootfs,size=0" + It can be used to locate bootable disks with command + "part list <interface> <dev> -bootable <varname>", + please check out doc/README.distro for use. + 2. Define 'CONFIG_EFI_PARTITION' and 'CONFIG_CMD_GPT' -2. From u-boot prompt type: +3. From u-boot prompt type: gpt write mmc 0 $partitions +Checking (validating) GPT partitions in U-Boot: +=============================================== + +Procedure is the same as above. The only change is at point 3. + +At u-boot prompt one needs to write: + gpt verify mmc 0 [$partitions] + +where [$partitions] is an optional parameter. + +When it is not provided, only basic checks based on CRC32 calculation for GPT +header and PTEs are performed. +When provided, additionally partition data - name, size and starting +offset (last two in LBA) - are compared with data defined in '$partitions' +environment variable. + +After running this command, return code is set to 0 if no errors found in +on non-volatile medium stored GPT. + +Following line can be used to assess if GPT verification has succeed: + +U-BOOT> gpt verify mmc 0 $partitions +U-BOOT> if test $? = 0; then echo "GPT OK"; else echo "GPT ERR"; fi + + Partition type GUID: ==================== diff --git a/doc/README.nand b/doc/README.nand index 0ff5633..545d88c 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -94,7 +94,7 @@ Configuration Options: address of u-boot MTD partition in NAND. CONFIG_CMD_NAND - Enables NAND support and commmands. + Enables NAND support and commands. CONFIG_CMD_NAND_TORTURE Enables the torture command (see description of this command below). diff --git a/doc/README.rockchip b/doc/README.rockchip index 87ce9d2..b455f6f 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -42,6 +42,10 @@ At present three RK3288 boards are supported: - Radxa Rock 2 - also uses firefly-rk3288 configuration - Haier Chromebook - use chromebook_jerry configuration +one RK3036 board is support: + + - EVB RK3036 - use evb-rk3036_defconfig configuration + For example: CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig all @@ -67,7 +71,7 @@ Connect your board's OTG port to your computer. To create a suitable image and write it to the board: - ./firefly-rk3288/tools/mkimage -T rkimage -d \ + ./firefly-rk3288/tools/mkimage -n rk3288 -T rkimage -d \ ./firefly-rk3288/spl/u-boot-spl-dtb.bin out && \ cat out | openssl rc4 -K 7c4e0304550509072d2c7b38170d1711 | rkflashtool l @@ -90,7 +94,7 @@ Booting from an SD card To write an image that boots from an SD card (assumed to be /dev/sdc): - ./firefly-rk3288/tools/mkimage -T rksd -d \ + ./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \ firefly-rk3288/spl/u-boot-spl-dtb.bin out && \ sudo dd if=out of=/dev/sdc seek=64 && \ sudo dd if=firefly-rk3288/u-boot-dtb.img of=/dev/sdc seek=256 @@ -118,13 +122,20 @@ something like: Err: serial@ff690000 => +For evb_rk3036 board: + ./evb-rk3036/tools/mkimage -n rk3036 -T rksd -d evb-rk3036/spl/u-boot-spl.bin out && \ + cat evb-rk3036/u-boot-dtb.bin >> out && \ + sudo dd if=out of=/dev/sdc seek=64 + +Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, the + debug uart must be disabled Booting from SPI ================ To write an image that boots from SPI flash (e.g. for the Haier Chromebook): - ./chromebook_jerry/tools/mkimage -T rkspi -d chromebook_jerry/spl/u-boot-spl-dtb.bin out + ./chromebook_jerry/tools/mkimage -n rk3036 -T rkspi -d chromebook_jerry/spl/u-boot-spl-dtb.bin out dd if=spl.bin of=out.bin bs=128K conv=sync cat chromebook_jerry/u-boot-dtb.img out.bin dd if=out.bin of=out.bin.pad bs=4M conv=sync diff --git a/doc/README.uniphier b/doc/README.uniphier index 57b947b..f0f5346 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -28,34 +28,38 @@ Tested toolchains Compile the source ------------------ -PH1-sLD3: - $ make ph1_sld3_defconfig +PH1-sLD3 reference board: + $ make uniphier_sld3_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- -PH1-LD4: - $ make ph1_ld4_defconfig +PH1-LD4 reference board: + $ make uniphier_ld4_sld8_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- -PH1-Pro4: - $ make ph1_pro4_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- +PH1-sLD8 reference board: + $ make uniphier_ld4_sld8_defconfig + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-sld8-ref -PH1-sLD8: - $ make ph1_sld8_defconfig +PH1-Pro4 reference board: + $ make uniphier_pro4_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- -PH1-Pro5: - $ make ph1_pro5_defconfig +PH1-Pro5 4KBOX Board: + $ make uniphier_pro5_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- -ProXstream2: - $ make pxs2_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- +ProXstream2 Gentil board: + $ make uniphier_pxs2_ld6b_defconfig + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-proxstream2-gentil -PH1-LD6b: - $ make ph1_ld6b_defconfig +ProXstream2 Vodka board: + $ make uniphier_pxs2_ld6b_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- +PH1-LD6b reference board: + $ make uniphier_pxs2_ld6b_defconfig + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld6b-ref + You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-" to use your favorite compiler. diff --git a/doc/README.update b/doc/README.update index eab124c..d37f2c4 100644 --- a/doc/README.update +++ b/doc/README.update @@ -51,7 +51,7 @@ the mkimage tool. dtc tool with support for binary includes, e.g. in version to be prepared. Refer to the doc/uImage.FIT/ directory for more details on FIT images. -This mechanism can be also triggered by the commmand "fitupd". +This mechanism can be also triggered by the command "fitupd". If an optional, non-zero address is provided as argument, the TFTP transfer is skipped and the image at this address is used. The fitupd command is enabled by CONFIG_CMD_FITUPD. diff --git a/doc/driver-model/serial-howto.txt b/doc/driver-model/serial-howto.txt index 60483a4..4706d56 100644 --- a/doc/driver-model/serial-howto.txt +++ b/doc/driver-model/serial-howto.txt @@ -4,8 +4,6 @@ How to port a serial driver to driver model About 16 of 33 serial drivers have been converted as at September 2015. It is time for maintainers to start converting over the remaining serial drivers: - altera_jtag_uart.c - altera_uart.c arm_dcc.c lpc32xx_hsuart.c mcfuart.c @@ -18,7 +16,6 @@ is time for maintainers to start converting over the remaining serial drivers: serial_pxa.c serial_s3c24x0.c serial_sa1100.c - serial_stm32.c serial_xuartlite.c usbtty.c diff --git a/doc/git-mailrc b/doc/git-mailrc index 85bac75..ced7085 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -20,7 +20,6 @@ alias angelo_ts Angelo Dureghello <angelo@sysam.it> alias bmeng Bin Meng <bmeng.cn@gmail.com> alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com> alias galak Kumar Gala <galak@kernel.crashing.org> -alias gruss Graeme Russ <graeme.russ@gmail.com> alias hs Heiko Schocher <hs@denx.de> alias ijc Ian Campbell <ijc+uboot@hellion.org.uk> alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org> @@ -112,7 +111,7 @@ alias sparc uboot, Francois Retief <fgretief@spaceteq.co.za> alias superh uboot, iwamatsu alias sh superh -alias x86 uboot, sjg, gruss, bmeng +alias x86 uboot, sjg, bmeng # Subsystem aliases alias dm uboot, sjg diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 1ad638e..5efa821 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -818,7 +818,7 @@ static int ata_scsiop_read_capacity10(ccb *pccb) if (!ataid[pccb->target]) { printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " "\tNo ATA info!\n" - "\tPlease run SCSI commmand INQUIRY firstly!\n"); + "\tPlease run SCSI command INQUIRY first!\n"); return -EPERM; } @@ -847,7 +847,7 @@ static int ata_scsiop_read_capacity16(ccb *pccb) if (!ataid[pccb->target]) { printf("scsi_ahci: SCSI READ CAPACITY16 command failure. " "\tNo ATA info!\n" - "\tPlease run SCSI commmand INQUIRY firstly!\n"); + "\tPlease run SCSI command INQUIRY first!\n"); return -EPERM; } diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index 208a0ae..e000ebf 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -398,7 +398,7 @@ static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis debug("attribute = %08x\n\r", val32); cmd_hdr->attribute = cpu_to_le32(val32); - /* Make sure cmd desc and cmd slot valid before commmand issue */ + /* Make sure cmd desc and cmd slot valid before command issue */ sync(); /* PMP*/ diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 008ec10..4a6a4a8 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -6,5 +6,6 @@ # obj-$(CONFIG_CLK) += clk-uclass.o +obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c new file mode 100644 index 0000000..6c802b6 --- /dev/null +++ b/drivers/clk/clk_rk3036.c @@ -0,0 +1,414 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3036.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <dm/lists.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3036_clk_plat { + enum rk_clk_id clk_id; +}; + +struct rk3036_clk_priv { + struct rk3036_cru *cru; + ulong rate; +}; + +enum { + VCO_MAX_HZ = 2400U * 1000000, + VCO_MIN_HZ = 600 * 1000000, + OUTPUT_MAX_HZ = 2400U * 1000000, + OUTPUT_MIN_HZ = 24 * 1000000, +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ + .refdiv = _refdiv,\ + .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ + _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ + OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ + #hz "Hz cannot be hit with PLL "\ + "divisors on line " __stringify(__LINE__)); + +/* use interge mode*/ +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); + +static inline unsigned int log2(unsigned int value) +{ + return fls(value) - 1; +} + +static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div) +{ + int pll_id = rk_pll_id(clk_id); + struct rk3036_pll *pll = &cru->pll[pll_id]; + + /* All PLLs have same VCO and output frequency range restrictions. */ + uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; + uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; + + debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\ + vco=%u Hz, output=%u Hz\n", + pll, div->fbdiv, div->refdiv, div->postdiv1, + div->postdiv2, vco_hz, output_hz); + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); + + /* use interger mode */ + rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); + + rk_clrsetreg(&pll->con0, + PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK, + (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | + PLL_REFDIV_MASK << PLL_REFDIV_SHIFT, + (div->postdiv2 << PLL_POSTDIV2_SHIFT | + div->refdiv << PLL_REFDIV_SHIFT)); + + /* waiting for pll lock */ + while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) + udelay(1); + + return 0; +} + +static void rkclk_init(struct rk3036_cru *cru) +{ + u32 aclk_div; + u32 hclk_div; + u32 pclk_div; + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK << GPLL_MODE_SHIFT | + APLL_MODE_MASK << APLL_MODE_SHIFT, + GPLL_MODE_SLOW << GPLL_MODE_SHIFT | + APLL_MODE_SLOW << APLL_MODE_SHIFT); + + /* init pll */ + rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); + + /* + * select apll as core clock pll source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + * core hz : apll = 1:1 + */ + aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; + assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); + + pclk_div = APLL_HZ / CORE_PERI_HZ - 1; + assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); + + rk_clrsetreg(&cru->cru_clksel_con[0], + CORE_CLK_PLL_SEL_MASK << CORE_CLK_PLL_SEL_SHIFT | + CORE_DIV_CON_MASK << CORE_DIV_CON_SHIFT, + CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | + 0 << CORE_DIV_CON_SHIFT); + + rk_clrsetreg(&cru->cru_clksel_con[1], + CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT | + CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT, + aclk_div << CORE_ACLK_DIV_SHIFT | + pclk_div << CORE_PERI_DIV_SHIFT); + + /* + * select apll as cpu clock pll source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = APLL_HZ / CPU_ACLK_HZ - 1; + assert((aclk_div + 1) * CPU_ACLK_HZ == APLL_HZ && aclk_div < 0x1f); + + pclk_div = APLL_HZ / CPU_PCLK_HZ - 1; + assert((pclk_div + 1) * CPU_PCLK_HZ == APLL_HZ && pclk_div < 0x7); + + hclk_div = APLL_HZ / CPU_HCLK_HZ - 1; + assert((hclk_div + 1) * CPU_HCLK_HZ == APLL_HZ && hclk_div < 0x3); + + rk_clrsetreg(&cru->cru_clksel_con[0], + CPU_CLK_PLL_SEL_MASK << CPU_CLK_PLL_SEL_SHIFT | + ACLK_CPU_DIV_MASK << ACLK_CPU_DIV_SHIFT, + CPU_CLK_PLL_SEL_APLL << CPU_CLK_PLL_SEL_SHIFT | + aclk_div << ACLK_CPU_DIV_SHIFT); + + rk_clrsetreg(&cru->cru_clksel_con[1], + CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT | + CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT, + pclk_div << CPU_PCLK_DIV_SHIFT | + hclk_div << CPU_HCLK_DIV_SHIFT); + + /* + * select gpll as peri clock pll source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ); + assert((1 << hclk_div) * PERI_HCLK_HZ == + PERI_ACLK_HZ && (pclk_div < 0x4)); + + pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ); + assert((1 << pclk_div) * PERI_PCLK_HZ == + PERI_ACLK_HZ && pclk_div < 0x8); + + rk_clrsetreg(&cru->cru_clksel_con[10], + PERI_PLL_SEL_MASK << PERI_PLL_SEL_SHIFT | + PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | + PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | + PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, + PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | + pclk_div << PERI_PCLK_DIV_SHIFT | + hclk_div << PERI_HCLK_DIV_SHIFT | + aclk_div << PERI_ACLK_DIV_SHIFT); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK << GPLL_MODE_SHIFT | + APLL_MODE_MASK << APLL_MODE_SHIFT, + GPLL_MODE_NORM << GPLL_MODE_SHIFT | + APLL_MODE_NORM << APLL_MODE_SHIFT); +} + +/* Get pll rate by id */ +static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, + enum rk_clk_id clk_id) +{ + uint32_t refdiv, fbdiv, postdiv1, postdiv2; + uint32_t con; + int pll_id = rk_pll_id(clk_id); + struct rk3036_pll *pll = &cru->pll[pll_id]; + static u8 clk_shift[CLK_COUNT] = { + 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, + GPLL_MODE_SHIFT, 0xff + }; + static u8 clk_mask[CLK_COUNT] = { + 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, + GPLL_MODE_MASK, 0xff + }; + uint shift; + uint mask; + + con = readl(&cru->cru_mode_con); + shift = clk_shift[clk_id]; + mask = clk_mask[clk_id]; + + switch ((con >> shift) & mask) { + case GPLL_MODE_SLOW: + return OSC_HZ; + case GPLL_MODE_NORM: + + /* normal mode */ + con = readl(&pll->con0); + postdiv1 = (con >> PLL_POSTDIV1_SHIFT) & PLL_POSTDIV1_MASK; + fbdiv = (con >> PLL_FBDIV_SHIFT) & PLL_FBDIV_MASK; + con = readl(&pll->con1); + postdiv2 = (con >> PLL_POSTDIV2_SHIFT) & PLL_POSTDIV2_MASK; + refdiv = (con >> PLL_REFDIV_SHIFT) & PLL_REFDIV_MASK; + return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; + case GPLL_MODE_DEEP: + default: + return 32768; + } +} + +static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, + enum periph_id periph) +{ + uint src_rate; + uint div, mux; + u32 con; + + switch (periph) { + case PERIPH_ID_EMMC: + con = readl(&cru->cru_clksel_con[12]); + mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK; + div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; + break; + case PERIPH_ID_SDCARD: + con = readl(&cru->cru_clksel_con[12]); + mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK; + div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; + break; + default: + return -EINVAL; + } + + src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; + return DIV_TO_RATE(src_rate, div); +} + +static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, + enum periph_id periph, uint freq) +{ + int src_clk_div; + int mux; + + debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); + + /* mmc clock auto divide 2 in internal */ + src_clk_div = (clk_general_rate / 2 + freq - 1) / freq; + + if (src_clk_div > 0x7f) { + src_clk_div = (OSC_HZ / 2 + freq - 1) / freq; + mux = EMMC_SEL_24M; + } else { + mux = EMMC_SEL_GPLL; + } + + switch (periph) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&cru->cru_clksel_con[12], + EMMC_PLL_MASK << EMMC_PLL_SHIFT | + EMMC_DIV_MASK << EMMC_DIV_SHIFT, + mux << EMMC_PLL_SHIFT | + (src_clk_div - 1) << EMMC_DIV_SHIFT); + break; + case PERIPH_ID_SDCARD: + rk_clrsetreg(&cru->cru_clksel_con[11], + MMC0_PLL_MASK << MMC0_PLL_SHIFT | + MMC0_DIV_MASK << MMC0_DIV_SHIFT, + mux << MMC0_PLL_SHIFT | + (src_clk_div - 1) << MMC0_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rockchip_mmc_get_clk(cru, clk_general_rate, periph); +} + +static ulong rk3036_clk_get_rate(struct udevice *dev) +{ + struct rk3036_clk_plat *plat = dev_get_platdata(dev); + struct rk3036_clk_priv *priv = dev_get_priv(dev); + + debug("%s\n", dev->name); + return rkclk_pll_get_rate(priv->cru, plat->clk_id); +} + +static ulong rk3036_clk_set_rate(struct udevice *dev, ulong rate) +{ + debug("%s\n", dev->name); + + return 0; +} + +ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong rate) +{ + struct rk3036_clk_priv *priv = dev_get_priv(dev); + ulong new_rate; + + switch (periph) { + case PERIPH_ID_EMMC: + new_rate = rockchip_mmc_set_clk(priv->cru, clk_get_rate(dev), + periph, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static struct clk_ops rk3036_clk_ops = { + .get_rate = rk3036_clk_get_rate, + .set_rate = rk3036_clk_set_rate, + .set_periph_rate = rk3036_set_periph_rate, +}; + +static int rk3036_clk_probe(struct udevice *dev) +{ + struct rk3036_clk_plat *plat = dev_get_platdata(dev); + struct rk3036_clk_priv *priv = dev_get_priv(dev); + + if (plat->clk_id != CLK_OSC) { + struct rk3036_clk_priv *parent_priv = dev_get_priv(dev->parent); + + priv->cru = parent_priv->cru; + return 0; + } + priv->cru = (struct rk3036_cru *)dev_get_addr(dev); + rkclk_init(priv->cru); + + return 0; +} + +static const char *const clk_name[] = { + "osc", + "apll", + "dpll", + "cpll", + "gpll", + "mpll", +}; + +static int rk3036_clk_bind(struct udevice *dev) +{ + struct rk3036_clk_plat *plat = dev_get_platdata(dev); + int pll, ret; + + /* We only need to set up the root clock */ + if (dev->of_offset == -1) { + plat->clk_id = CLK_OSC; + return 0; + } + + /* Create devices for P main clocks */ + for (pll = 1; pll < CLK_COUNT; pll++) { + struct udevice *child; + struct rk3036_clk_plat *cplat; + + debug("%s %s\n", __func__, clk_name[pll]); + ret = device_bind_driver(dev, "clk_rk3036", clk_name[pll], + &child); + if (ret) + return ret; + + cplat = dev_get_platdata(child); + cplat->clk_id = pll; + } + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rk3036_reset", "reset", &dev); + if (ret) + debug("Warning: No RK3036 reset driver: ret=%d\n", ret); + + return 0; +} + +static const struct udevice_id rk3036_clk_ids[] = { + { .compatible = "rockchip,rk3036-cru" }, + { } +}; + +U_BOOT_DRIVER(clk_rk3036) = { + .name = "clk_rk3036", + .id = UCLASS_CLK, + .of_match = rk3036_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk3036_clk_priv), + .platdata_auto_alloc_size = sizeof(struct rk3036_clk_plat), + .ops = &rk3036_clk_ops, + .bind = rk3036_clk_bind, + .probe = rk3036_clk_probe, +}; diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 15681df..f332480 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -72,6 +72,16 @@ config REGMAP support any bus type (I2C, SPI) but so far this only supports direct memory access. +config SPL_REGMAP + bool "Support register maps in SPL" + depends on DM + help + Hardware peripherals tend to have one or more sets of registers + which can be accessed to control the hardware. A register map + models this with a simple read/write interface. It can in principle + support any bus type (I2C, SPI) but so far this only supports + direct memory access. + config SYSCON bool "Support system controllers" depends on REGMAP @@ -81,6 +91,15 @@ config SYSCON by this uclass, including accessing registers via regmap and assigning a unique number to each. +config SPL_SYSCON + bool "Support system controllers in SPL" + depends on REGMAP + help + Many SoCs have a number of system controllers which are dealt with + as a group by a single driver. Some common functionality is provided + by this uclass, including accessing registers via regmap and + assigning a unique number to each. + config DEVRES bool "Managed device resources" depends on DM @@ -115,7 +134,7 @@ config SIMPLE_BUS config SPL_SIMPLE_BUS bool "Support simple-bus driver in SPL" depends on SPL_DM && SPL_OF_CONTROL - default n + default y help Supports the 'simple-bus' driver, which is used on some systems in SPL. @@ -136,7 +155,7 @@ config OF_TRANSLATE smaller in size than fdt_translate_address(). config SPL_OF_TRANSLATE - bool "Translate addresses using fdt_translate_address" + bool "Translate addresses using fdt_translate_address in SPL" depends on SPL_DM && SPL_OF_CONTROL default n help diff --git a/drivers/core/Makefile b/drivers/core/Makefile index f19f67d..07adb61 100644 --- a/drivers/core/Makefile +++ b/drivers/core/Makefile @@ -9,5 +9,5 @@ obj-$(CONFIG_DEVRES) += devres.o obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE) += device-remove.o obj-$(CONFIG_$(SPL_)SIMPLE_BUS) += simple-bus.o obj-$(CONFIG_DM) += dump.o -obj-$(CONFIG_REGMAP) += regmap.o -obj-$(CONFIG_SYSCON) += syscon-uclass.o +obj-$(CONFIG_$(SPL_)REGMAP) += regmap.o +obj-$(CONFIG_$(SPL_)SYSCON) += syscon-uclass.o diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index f63eacb..b553e3c 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -470,17 +470,13 @@ static void kick_trng(int ent_delay) sec_out32(&rng->rtfreqmin, ent_delay >> 2); /* disable maximum frequency count */ sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE); - /* read the control register */ - val = sec_in32(&rng->rtmctl); /* * select raw sampling in both entropy shifter * and statistical checker */ - sec_setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC); + sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC); /* put RNG4 into run mode */ - sec_clrbits32(&val, RTMCTL_PRGM); - /* write back the control register */ - sec_out32(&rng->rtmctl, val); + sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM); } static int rng_init(void) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 8543679..0bfcd34 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -317,7 +317,24 @@ static void set_timing_cfg_0(const unsigned int ctrl_num, /* for faster clock, need more time for data setup */ trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2; - twrt_mclk = 1; + + /* + * for single quad-rank DIMM and two-slot DIMMs + * to avoid ODT overlap + */ + switch (avoid_odt_overlap(dimm_params)) { + case 2: + twrt_mclk = 2; + twwt_mclk = 2; + trrt_mclk = 2; + break; + default: + twrt_mclk = 1; + twwt_mclk = 1; + trrt_mclk = 0; + break; + } + act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); pre_pd_exit_mclk = act_pd_exit_mclk; /* @@ -1117,10 +1134,18 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */ unsigned short esdmode5; /* Extended SDRAM mode 5 */ int rtt_park = 0; - + bool four_cs = false; + +#if CONFIG_CHIP_SELECTS_PER_CTRL == 4 + if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) && + (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) && + (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) && + (ddr->cs[3].config & SDRAM_CS_CONFIG_EN)) + four_cs = true; +#endif if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) { esdmode5 = 0x00000500; /* Data mask enable, RTT_PARK CS0 */ - rtt_park = 1; + rtt_park = four_cs ? 0 : 1; } else { esdmode5 = 0x00000400; /* Data mask enabled */ } @@ -1130,7 +1155,10 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, | ((esdmode5 & 0xffff) << 0) ); - /* only mode_9 use 0x500, others use 0x400 */ + /* Normally only the first enabled CS use 0x500, others use 0x400 + * But when four chip-selects are all enabled, all mode registers + * need 0x500 to park. + */ debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9); if (unq_mrs_en) { /* unique mode registers are supported */ @@ -1138,7 +1166,7 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, if (!rtt_park && (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) { esdmode5 |= 0x00000500; /* RTT_PARK */ - rtt_park = 1; + rtt_park = four_cs ? 0 : 1; } else { esdmode5 = 0x00000400; } @@ -1186,6 +1214,9 @@ static void set_ddr_sdram_mode_10(const unsigned int ctrl_num, esdmode6 = ((tccdl_min - 4) & 0x7) << 10; + if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) + esdmode6 |= 1 << 6; /* Range 2 */ + ddr->ddr_sdram_mode_10 = (0 | ((esdmode6 & 0xffff) << 16) | ((esdmode7 & 0xffff) << 0) @@ -1808,6 +1839,7 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ unsigned int rrt = 0; /* Read-to-read turnaround for same CS */ unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ + unsigned int trwt_mclk = 0; /* ext_rwt */ unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) @@ -1821,17 +1853,21 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, wwt = 2; /* BL/2 + 2 clocks */ } #endif - #ifdef CONFIG_SYS_FSL_DDR4 dll_lock = 2; /* tDLLK = 1024 clocks */ #elif defined(CONFIG_SYS_FSL_DDR3) dll_lock = 1; /* tDLLK = 512 clocks from spec */ #endif + + if (popts->trwt_override) + trwt_mclk = popts->trwt; + ddr->timing_cfg_4 = (0 | ((rwt & 0xf) << 28) | ((wrt & 0xf) << 24) | ((rrt & 0xf) << 20) | ((wwt & 0xf) << 16) + | ((trwt_mclk & 0xc) << 12) | (dll_lock & 0x3) ); debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 49e4688..3fca5c2 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -10,6 +10,7 @@ #include <asm/processor.h> #include <fsl_immap.h> #include <fsl_ddr.h> +#include <fsl_errata.h> #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) @@ -48,12 +49,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 temp_sdram_cfg; u32 total_gb_size_per_controller; int timeout; -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ - defined(CONFIG_SYS_FSL_ERRATUM_A008514) - u32 *eddrtqcr1; -#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 u32 temp32, mr6; + u32 vref_seq1[3] = {0x80, 0x96, 0x16}; /* for range 1 */ + u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */ + u32 *vref_seq = vref_seq1; #endif #ifdef CONFIG_FSL_DDR_BIST u32 mtcr, err_detect, err_sbe; @@ -66,36 +66,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, switch (ctrl_num) { case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ - defined(CONFIG_SYS_FSL_ERRATUM_A008514) - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; -#endif break; #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) case 1: ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ - defined(CONFIG_SYS_FSL_ERRATUM_A008514) - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; -#endif break; #endif #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) case 2: ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ - defined(CONFIG_SYS_FSL_ERRATUM_A008514) - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; -#endif break; #endif #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) case 3: ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ - defined(CONFIG_SYS_FSL_ERRATUM_A008514) - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800; -#endif break; #endif default: @@ -106,20 +90,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (step == 2) goto step2; -#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 -#ifdef CONFIG_LS2085A - /* A008336 only applies to general DDR controllers */ - if ((ctrl_num == 0) || (ctrl_num == 1)) -#endif - ddr_out32(eddrtqcr1, 0x63b30002); -#endif -#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 -#ifdef CONFIG_LS2085A - /* A008514 only applies to DP-DDR controler */ - if (ctrl_num == 2) -#endif - ddr_out32(eddrtqcr1, 0x63b20002); -#endif if (regs->ddr_eor) ddr_out32(&ddr->eor, regs->ddr_eor); @@ -235,9 +205,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, /* Erratum applies when accumulated ECC is used, or DBI is enabled */ #define IS_ACC_ECC_EN(v) ((v) & 0x4) #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) - if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || - IS_DBI(regs->ddr_sdram_cfg_3)) - ddr_setbits32(ddr->debug[28], 0x9 << 20); + if (has_erratum_a008378()) { + if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || + IS_DBI(regs->ddr_sdram_cfg_3)) + ddr_setbits32(&ddr->debug[28], 0x9 << 20); + } #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 @@ -307,16 +279,21 @@ step2: /* This erraum only applies to verion 5.2.0 */ if (fsl_ddr_get_version(ctrl_num) == 0x50200) { /* Wait for idle */ - timeout = 200; + timeout = 40; while (!(ddr_in32(&ddr->debug[1]) & 0x2) && (timeout > 0)) { - udelay(100); + udelay(1000); timeout--; } if (timeout <= 0) { printf("Controler %d timeout, debug_2 = %x\n", ctrl_num, ddr_in32(&ddr->debug[1])); } + + /* The vref setting sequence is different for range 2 */ + if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) + vref_seq = vref_seq2; + /* Set VREF */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) @@ -327,17 +304,17 @@ step2: MD_CNTL_CS_SEL(i) | MD_CNTL_MD_SEL(6) | 0x00200000; - temp32 = mr6 | 0xc0; + temp32 = mr6 | vref_seq[0]; set_wait_for_bits_clear(&ddr->sdram_md_cntl, temp32, MD_CNTL_MD_EN); udelay(1); debug("MR6 = 0x%08x\n", temp32); - temp32 = mr6 | 0xf0; + temp32 = mr6 | vref_seq[1]; set_wait_for_bits_clear(&ddr->sdram_md_cntl, temp32, MD_CNTL_MD_EN); udelay(1); debug("MR6 = 0x%08x\n", temp32); - temp32 = mr6 | 0x70; + temp32 = mr6 | vref_seq[2]; set_wait_for_bits_clear(&ddr->sdram_md_cntl, temp32, MD_CNTL_MD_EN); udelay(1); @@ -347,10 +324,10 @@ step2: ddr_out32(&ddr->debug[28], 0); /* Enable deskew */ ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */ /* wait for idle */ - timeout = 200; + timeout = 40; while (!(ddr_in32(&ddr->debug[1]) & 0x2) && (timeout > 0)) { - udelay(100); + udelay(1000); timeout--; } if (timeout <= 0) { @@ -423,16 +400,16 @@ step2: if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) { puts("Running BIST test. This will take a while..."); cs0_config = ddr_in32(&ddr->cs0_config); + cs0_bnds = ddr_in32(&ddr->cs0_bnds); + cs1_bnds = ddr_in32(&ddr->cs1_bnds); + cs2_bnds = ddr_in32(&ddr->cs2_bnds); + cs3_bnds = ddr_in32(&ddr->cs3_bnds); if (cs0_config & CTLR_INTLV_MASK) { - cs0_bnds = ddr_in32(&cs0_bnds); - cs1_bnds = ddr_in32(&cs1_bnds); - cs2_bnds = ddr_in32(&cs2_bnds); - cs3_bnds = ddr_in32(&cs3_bnds); /* set bnds to non-interleaving */ - ddr_out32(&cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1); - ddr_out32(&cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1); - ddr_out32(&cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1); - ddr_out32(&cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1); + ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1); + ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1); + ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1); + ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1); } ddr_out32(&ddr->mtp1, BIST_PATTERN1); ddr_out32(&ddr->mtp2, BIST_PATTERN1); @@ -469,10 +446,10 @@ step2: if (cs0_config & CTLR_INTLV_MASK) { /* restore bnds registers */ - ddr_out32(&cs0_bnds, cs0_bnds); - ddr_out32(&cs1_bnds, cs1_bnds); - ddr_out32(&cs2_bnds, cs2_bnds); - ddr_out32(&cs3_bnds, cs3_bnds); + ddr_out32(&ddr->cs0_bnds, cs0_bnds); + ddr_out32(&ddr->cs1_bnds, cs1_bnds); + ddr_out32(&ddr->cs2_bnds, cs2_bnds); + ddr_out32(&ddr->cs3_bnds, cs3_bnds); } } #endif diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 72ec1be..c686632 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -813,6 +813,7 @@ phys_size_t fsl_ddr_sdram(void) info.board_need_mem_reset = board_need_mem_reset; info.board_mem_reset = board_assert_mem_reset; info.board_mem_de_reset = board_deassert_mem_reset; + remove_unused_controllers(&info); return __fsl_ddr_sdram(&info); } diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 3c09c64..791d644 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -29,7 +29,240 @@ struct dynamic_odt { unsigned int odt_rtt_wr; }; -#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) +#ifdef CONFIG_SYS_FSL_DDR4 +/* Quad rank is not verified yet due availability. + * Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option + */ +static const struct dynamic_odt single_Q[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS_AND_OTHER_DIMM, + DDR4_RTT_34_OHM, /* unverified */ + DDR4_RTT_120_OHM + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR4_RTT_OFF, + DDR4_RTT_120_OHM + }, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS_AND_OTHER_DIMM, + DDR4_RTT_34_OHM, + DDR4_RTT_120_OHM + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, /* tied high */ + DDR4_RTT_OFF, + DDR4_RTT_120_OHM + } +}; + +static const struct dynamic_odt single_D[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR4_RTT_40_OHM, + DDR4_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR4_RTT_OFF, + DDR4_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt single_S[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR4_RTT_40_OHM, + DDR4_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0}, +}; + +static const struct dynamic_odt dual_DD[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR4_RTT_120_OHM, + DDR4_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR4_RTT_34_OHM, + DDR4_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR4_RTT_120_OHM, + DDR4_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR4_RTT_34_OHM, + DDR4_RTT_OFF + } +}; + +static const struct dynamic_odt dual_DS[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR4_RTT_120_OHM, + DDR4_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR4_RTT_34_OHM, + DDR4_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR4_RTT_34_OHM, + DDR4_RTT_120_OHM + }, + {0, 0, 0, 0} +}; +static const struct dynamic_odt dual_SD[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR4_RTT_34_OHM, + DDR4_RTT_120_OHM + }, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR4_RTT_120_OHM, + DDR4_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR4_RTT_34_OHM, + DDR4_RTT_OFF + } +}; + +static const struct dynamic_odt dual_SS[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR4_RTT_34_OHM, + DDR4_RTT_120_OHM + }, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR4_RTT_34_OHM, + DDR4_RTT_120_OHM + }, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt dual_D0[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR4_RTT_40_OHM, + DDR4_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR4_RTT_OFF, + DDR4_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt dual_0D[4] = { + {0, 0, 0, 0}, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR4_RTT_40_OHM, + DDR4_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR4_RTT_OFF, + DDR4_RTT_OFF + } +}; + +static const struct dynamic_odt dual_S0[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR4_RTT_40_OHM, + DDR4_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0} + +}; + +static const struct dynamic_odt dual_0S[4] = { + {0, 0, 0, 0}, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR4_RTT_40_OHM, + DDR4_RTT_OFF + }, + {0, 0, 0, 0} + +}; + +static const struct dynamic_odt odt_unknown[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR4_RTT_120_OHM, + DDR4_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR4_RTT_120_OHM, + DDR4_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR4_RTT_120_OHM, + DDR4_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR4_RTT_120_OHM, + DDR4_RTT_OFF + } +}; +#elif defined(CONFIG_SYS_FSL_DDR3) static const struct dynamic_odt single_Q[4] = { { /* cs0 */ FSL_DDR_ODT_NEVER, @@ -259,7 +492,7 @@ static const struct dynamic_odt odt_unknown[4] = { DDR3_RTT_OFF } }; -#else /* CONFIG_SYS_FSL_DDR3 || CONFIG_SYS_FSL_DDR4 */ +#else /* CONFIG_SYS_FSL_DDR3 */ static const struct dynamic_odt single_Q[4] = { {0, 0, 0, 0}, {0, 0, 0, 0}, diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index ce55aea..1a49b28 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -385,3 +385,43 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]); } #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */ + +void remove_unused_controllers(fsl_ddr_info_t *info) +{ +#ifdef CONFIG_FSL_LSCH3 + int i; + u64 nodeid; + void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL); + bool ddr0_used = false; + bool ddr1_used = false; + + for (i = 0; i < 8; i++) { + nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK; + if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) { + ddr0_used = true; + } else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) { + ddr1_used = true; + } else { + printf("Unknown nodeid in HN-F SAM control: 0x%llx\n", + nodeid); + } + hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE); + } + if (!ddr0_used && !ddr1_used) { + printf("Invalid configuration in HN-F SAM control\n"); + return; + } + + if (!ddr0_used && info->first_ctrl == 0) { + info->first_ctrl = 1; + info->num_ctrls = 1; + debug("First DDR controller disabled\n"); + return; + } + + if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) { + info->num_ctrls = 1; + debug("Second DDR controller disabled\n"); + } +#endif +} diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 9e49471..e60e9fd 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -28,6 +28,17 @@ config DWAPB_GPIO help Support for the Designware APB GPIO driver. +config ATMEL_PIO4 + bool "ATMEL PIO4 driver" + depends on DM + default n + help + Say yes here to support the Atmel PIO4 driver. + The PIO4 is new version of Atmel PIO controller, which manages + up to 128 fully programmable input/output lines. Each I/O line + may be dedicated as a general purpose I/O or be assigned to + a function of an embedded peripheral. + config LPC32XX_GPIO bool "LPC32XX GPIO driver" depends on DM diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index c58aa4d..fb4fd25 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -12,6 +12,7 @@ endif obj-$(CONFIG_DM_GPIO) += gpio-uclass.o obj-$(CONFIG_AT91_GPIO) += at91_gpio.o +obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o obj-$(CONFIG_KONA_GPIO) += kona_gpio.o diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c new file mode 100644 index 0000000..d71f525 --- /dev/null +++ b/drivers/gpio/atmel_pio4.c @@ -0,0 +1,296 @@ +/* + * Atmel PIO4 device driver + * + * Copyright (C) 2015 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <asm/arch/hardware.h> +#include <mach/gpio.h> +#include <mach/atmel_pio4.h> + +#define ATMEL_PIO4_PINS_PER_BANK 32 + +/* + * Register Field Definitions + */ +#define ATMEL_PIO4_CFGR_FUNC (0x7 << 0) +#define ATMEL_PIO4_CFGR_FUNC_GPIO (0x0 << 0) +#define ATMEL_PIO4_CFGR_FUNC_PERIPH_A (0x1 << 0) +#define ATMEL_PIO4_CFGR_FUNC_PERIPH_B (0x2 << 0) +#define ATMEL_PIO4_CFGR_FUNC_PERIPH_C (0x3 << 0) +#define ATMEL_PIO4_CFGR_FUNC_PERIPH_D (0x4 << 0) +#define ATMEL_PIO4_CFGR_FUNC_PERIPH_E (0x5 << 0) +#define ATMEL_PIO4_CFGR_FUNC_PERIPH_F (0x6 << 0) +#define ATMEL_PIO4_CFGR_FUNC_PERIPH_G (0x7 << 0) +#define ATMEL_PIO4_CFGR_DIR (0x1 << 8) +#define ATMEL_PIO4_CFGR_PUEN (0x1 << 9) +#define ATMEL_PIO4_CFGR_PDEN (0x1 << 10) +#define ATMEL_PIO4_CFGR_IFEN (0x1 << 12) +#define ATMEL_PIO4_CFGR_IFSCEN (0x1 << 13) +#define ATMEL_PIO4_CFGR_OPD (0x1 << 14) +#define ATMEL_PIO4_CFGR_SCHMITT (0x1 << 15) +#define ATMEL_PIO4_CFGR_DRVSTR (0x3 << 16) +#define ATMEL_PIO4_CFGR_DRVSTR_LOW0 (0x0 << 16) +#define ATMEL_PIO4_CFGR_DRVSTR_LOW1 (0x1 << 16) +#define ATMEL_PIO4_CFGR_DRVSTR_MEDIUM (0x2 << 16) +#define ATMEL_PIO4_CFGR_DRVSTR_HIGH (0x3 << 16) +#define ATMEL_PIO4_CFGR_EVTSEL (0x7 << 24) +#define ATMEL_PIO4_CFGR_EVTSEL_FALLING (0x0 << 24) +#define ATMEL_PIO4_CFGR_EVTSEL_RISING (0x1 << 24) +#define ATMEL_PIO4_CFGR_EVTSEL_BOTH (0x2 << 24) +#define ATMEL_PIO4_CFGR_EVTSEL_LOW (0x3 << 24) +#define ATMEL_PIO4_CFGR_EVTSEL_HIGH (0x4 << 24) +#define ATMEL_PIO4_CFGR_PCFS (0x1 << 29) +#define ATMEL_PIO4_CFGR_ICFS (0x1 << 30) + +static struct atmel_pio4_port *atmel_pio4_port_base(u32 port) +{ + struct atmel_pio4_port *base = NULL; + + switch (port) { + case AT91_PIO_PORTA: + base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA; + break; + case AT91_PIO_PORTB: + base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB; + break; + case AT91_PIO_PORTC: + base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC; + break; + case AT91_PIO_PORTD: + base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD; + break; + default: + printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n", + port); + break; + } + + return base; +} + +static int atmel_pio4_config_io_func(u32 port, u32 pin, + u32 func, u32 use_pullup) +{ + struct atmel_pio4_port *port_base; + u32 reg, mask; + + if (pin >= ATMEL_PIO4_PINS_PER_BANK) + return -ENODEV; + + port_base = atmel_pio4_port_base(port); + if (!port_base) + return -ENODEV; + + mask = 1 << pin; + reg = func; + reg |= use_pullup ? ATMEL_PIO4_CFGR_PUEN : 0; + + writel(mask, &port_base->mskr); + writel(reg, &port_base->cfgr); + + return 0; +} + +int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_GPIO, + use_pullup); +} + +int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_PERIPH_A, + use_pullup); +} + +int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_PERIPH_B, + use_pullup); +} + +int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_PERIPH_C, + use_pullup); +} + +int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_PERIPH_D, + use_pullup); +} + +int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_PERIPH_E, + use_pullup); +} + +int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_PERIPH_F, + use_pullup); +} + +int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_PERIPH_G, + use_pullup); +} + +int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value) +{ + struct atmel_pio4_port *port_base; + u32 reg, mask; + + if (pin >= ATMEL_PIO4_PINS_PER_BANK) + return -ENODEV; + + port_base = atmel_pio4_port_base(port); + if (!port_base) + return -ENODEV; + + mask = 0x01 << pin; + reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR; + + writel(mask, &port_base->mskr); + writel(reg, &port_base->cfgr); + + if (value) + writel(mask, &port_base->sodr); + else + writel(mask, &port_base->codr); + + return 0; +} + +int atmel_pio4_get_pio_input(u32 port, u32 pin) +{ + struct atmel_pio4_port *port_base; + u32 reg, mask; + + if (pin >= ATMEL_PIO4_PINS_PER_BANK) + return -ENODEV; + + port_base = atmel_pio4_port_base(port); + if (!port_base) + return -ENODEV; + + mask = 0x01 << pin; + reg = ATMEL_PIO4_CFGR_FUNC_GPIO; + + writel(mask, &port_base->mskr); + writel(reg, &port_base->cfgr); + + return (readl(&port_base->pdsr) & mask) ? 1 : 0; +} + +#ifdef CONFIG_DM_GPIO +static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset) +{ + struct at91_port_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; + u32 mask = 0x01 << offset; + u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO; + + writel(mask, &port_base->mskr); + writel(reg, &port_base->cfgr); + + return 0; +} + +static int atmel_pio4_direction_output(struct udevice *dev, + unsigned offset, int value) +{ + struct at91_port_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; + u32 mask = 0x01 << offset; + u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR; + + writel(mask, &port_base->mskr); + writel(reg, &port_base->cfgr); + + if (value) + writel(mask, &port_base->sodr); + else + writel(mask, &port_base->codr); + + return 0; +} + +static int atmel_pio4_get_value(struct udevice *dev, unsigned offset) +{ + struct at91_port_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; + u32 mask = 0x01 << offset; + + return (readl(&port_base->pdsr) & mask) ? 1 : 0; +} + +static int atmel_pio4_set_value(struct udevice *dev, + unsigned offset, int value) +{ + struct at91_port_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; + u32 mask = 0x01 << offset; + + if (value) + writel(mask, &port_base->sodr); + else + writel(mask, &port_base->codr); + + return 0; +} + +static int atmel_pio4_get_function(struct udevice *dev, unsigned offset) +{ + struct at91_port_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; + u32 mask = 0x01 << offset; + + writel(mask, &port_base->mskr); + + return (readl(&port_base->cfgr) & + ATMEL_PIO4_CFGR_DIR) ? GPIOF_OUTPUT : GPIOF_INPUT; +} + +static const struct dm_gpio_ops atmel_pio4_ops = { + .direction_input = atmel_pio4_direction_input, + .direction_output = atmel_pio4_direction_output, + .get_value = atmel_pio4_get_value, + .set_value = atmel_pio4_set_value, + .get_function = atmel_pio4_get_function, +}; + +static int atmel_pio4_probe(struct udevice *dev) +{ + struct at91_port_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->bank_name = plat->bank_name; + uc_priv->gpio_count = ATMEL_PIO4_PINS_PER_BANK; + + return 0; +} + +U_BOOT_DRIVER(gpio_atmel_pio4) = { + .name = "gpio_atmel_pio4", + .id = UCLASS_GPIO, + .ops = &atmel_pio4_ops, + .probe = atmel_pio4_probe, +}; +#endif diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c index d7a194e..75a84e1 100644 --- a/drivers/gpio/stm32_gpio.c +++ b/drivers/gpio/stm32_gpio.c @@ -3,7 +3,7 @@ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * Copyright 2015 ATS Advanced Telematics Systems GmbH * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 32198bd..811ad9b 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -40,4 +40,4 @@ obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o -obj-y += muxes/ +obj-$(CONFIG_I2C_MUX) += muxes/ diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index bd3e078..913093d 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -1,5 +1,5 @@ config I2C_MUX - bool "Suport I2C multiplexers" + bool "Support I2C multiplexers" depends on DM_I2C help This enables I2C buses to be multiplexed, so that you can select @@ -8,10 +8,10 @@ config I2C_MUX using a suitable I2C MUX driver. config I2C_ARB_GPIO_CHALLENGE - bool "GPIO-based I2C arbitration" - depends on I2C_MUX - help - If you say yes to this option, support will be included for an - I2C multimaster arbitration scheme using GPIOs and a challenge & - response mechanism where masters have to claim the bus by asserting - a GPIO. + bool "GPIO-based I2C arbitration" + depends on I2C_MUX + help + If you say yes to this option, support will be included for an + I2C multimaster arbitration scheme using GPIOs and a challenge & + response mechanism where masters have to claim the bus by asserting + a GPIO. diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4375abc..909e3ca 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -94,6 +94,81 @@ static void dwmci_prepare_data(struct dwmci_host *host, dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); } +static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) +{ + int ret = 0; + u32 timeout = 240000; + u32 mask, size, i, len = 0; + u32 *buf = NULL; + ulong start = get_timer(0); + u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> + RX_WMARK_SHIFT) + 1) * 2; + + size = data->blocksize * data->blocks / 4; + if (data->flags == MMC_DATA_READ) + buf = (unsigned int *)data->dest; + else + buf = (unsigned int *)data->src; + + for (;;) { + mask = dwmci_readl(host, DWMCI_RINTSTS); + /* Error during data transfer. */ + if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { + debug("%s: DATA ERROR!\n", __func__); + ret = -EINVAL; + break; + } + + if (host->fifo_mode && size) { + if (data->flags == MMC_DATA_READ) { + if ((dwmci_readl(host, DWMCI_RINTSTS) && + DWMCI_INTMSK_RXDR)) { + len = dwmci_readl(host, DWMCI_STATUS); + len = (len >> DWMCI_FIFO_SHIFT) & + DWMCI_FIFO_MASK; + for (i = 0; i < len; i++) + *buf++ = + dwmci_readl(host, DWMCI_DATA); + dwmci_writel(host, DWMCI_RINTSTS, + DWMCI_INTMSK_RXDR); + } + } else { + if ((dwmci_readl(host, DWMCI_RINTSTS) && + DWMCI_INTMSK_TXDR)) { + len = dwmci_readl(host, DWMCI_STATUS); + len = fifo_depth - ((len >> + DWMCI_FIFO_SHIFT) & + DWMCI_FIFO_MASK); + for (i = 0; i < len; i++) + dwmci_writel(host, DWMCI_DATA, + *buf++); + dwmci_writel(host, DWMCI_RINTSTS, + DWMCI_INTMSK_TXDR); + } + } + size = size > len ? (size - len) : 0; + } + + /* Data arrived correctly. */ + if (mask & DWMCI_INTMSK_DTO) { + ret = 0; + break; + } + + /* Check for timeout. */ + if (get_timer(start) > timeout) { + debug("%s: Timeout waiting for data!\n", + __func__); + ret = TIMEOUT; + break; + } + } + + dwmci_writel(host, DWMCI_RINTSTS, mask); + + return ret; +} + static int dwmci_set_transfer_mode(struct dwmci_host *host, struct mmc_data *data) { @@ -129,17 +204,24 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); if (data) { - if (data->flags == MMC_DATA_READ) { - bounce_buffer_start(&bbstate, (void*)data->dest, - data->blocksize * - data->blocks, GEN_BB_WRITE); + if (host->fifo_mode) { + dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); + dwmci_writel(host, DWMCI_BYTCNT, + data->blocksize * data->blocks); + dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); } else { - bounce_buffer_start(&bbstate, (void*)data->src, - data->blocksize * - data->blocks, GEN_BB_READ); + if (data->flags == MMC_DATA_READ) { + bounce_buffer_start(&bbstate, (void*)data->dest, + data->blocksize * + data->blocks, GEN_BB_WRITE); + } else { + bounce_buffer_start(&bbstate, (void*)data->src, + data->blocksize * + data->blocks, GEN_BB_READ); + } + dwmci_prepare_data(host, data, cur_idmac, + bbstate.bounce_buffer); } - dwmci_prepare_data(host, data, cur_idmac, - bbstate.bounce_buffer); } dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); @@ -213,39 +295,15 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } if (data) { - start = get_timer(0); - timeout = 240000; - for (;;) { - mask = dwmci_readl(host, DWMCI_RINTSTS); - /* Error during data transfer. */ - if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { - debug("%s: DATA ERROR!\n", __func__); - ret = -EINVAL; - break; - } - - /* Data arrived correctly. */ - if (mask & DWMCI_INTMSK_DTO) { - ret = 0; - break; - } - - /* Check for timeout. */ - if (get_timer(start) > timeout) { - debug("%s: Timeout waiting for data!\n", - __func__); - ret = TIMEOUT; - break; - } + ret = dwmci_data_transfer(host, data); + + /* only dma mode need it */ + if (!host->fifo_mode) { + ctrl = dwmci_readl(host, DWMCI_CTRL); + ctrl &= ~(DWMCI_DMA_EN); + dwmci_writel(host, DWMCI_CTRL, ctrl); + bounce_buffer_stop(&bbstate); } - - dwmci_writel(host, DWMCI_RINTSTS, mask); - - ctrl = dwmci_readl(host, DWMCI_CTRL); - ctrl &= ~(DWMCI_DMA_EN); - dwmci_writel(host, DWMCI_CTRL, ctrl); - - bounce_buffer_stop(&bbstate); } udelay(100); diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 2a58702..3a34028 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1469,7 +1469,9 @@ static int mmc_startup(struct mmc *mmc) mmc->block_dev.blksz = mmc->read_bl_len; mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz); mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) +#if !defined(CONFIG_SPL_BUILD) || \ + (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ + !defined(CONFIG_USE_TINY_PRINTF)) sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x", mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), (mmc->cid[3] >> 16) & 0xffff); diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index f11c8e0..aeaec6c 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -50,8 +50,9 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; host->priv = dev; - /* TODO(sjg@chromium.org): Remove the need for this hack */ - host->dev_index = (ulong)host->ioaddr == 0xff0f0000 ? 0 : 1; + /* use non-removeable as sdcard and emmc as judgement */ + if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable")) + host->dev_index = 1; return 0; } @@ -63,6 +64,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev) struct dwmci_host *host = &priv->host; u32 minmax[2]; int ret; + int fifo_depth; priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); if (IS_ERR(priv->grf)) @@ -71,10 +73,22 @@ static int rockchip_dwmmc_probe(struct udevice *dev) if (ret) return ret; - ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, - "clock-freq-min-max", minmax, 2); - if (!ret) - ret = add_dwmci(host, minmax[1], minmax[0]); + if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, + "clock-freq-min-max", minmax, 2)) + return -EINVAL; + + fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "fifo-depth", 0); + if (fifo_depth < 0) + return -EINVAL; + + host->fifoth_val = MSIZE(0x2) | + RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); + + if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "fifo-mode")) + host->fifo_mode = true; + + ret = add_dwmci(host, minmax[1], minmax[0]); if (ret) return ret; diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 8076761..43a7e7e 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -5,36 +5,44 @@ */ #include <common.h> -#include <malloc.h> -#include <fdtdec.h> -#include <libfdt.h> -#include <dwmmc.h> -#include <errno.h> -#include <asm/arch/dwmmc.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/dwmmc.h> #include <asm/arch/system_manager.h> +#include <dm.h> +#include <dwmmc.h> +#include <errno.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <linux/err.h> +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_clock_manager *clock_manager_base = (void *)SOCFPGA_CLKMGR_ADDRESS; static const struct socfpga_system_manager *system_manager_base = (void *)SOCFPGA_SYSMGR_ADDRESS; +/* socfpga implmentation specific driver private data */ +struct dwmci_socfpga_priv_data { + struct dwmci_host host; + unsigned int drvsel; + unsigned int smplsel; +}; + static void socfpga_dwmci_clksel(struct dwmci_host *host) { - unsigned int drvsel; - unsigned int smplsel; + struct dwmci_socfpga_priv_data *priv = host->priv; + u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | + ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT); /* Disable SDMMC clock. */ clrbits_le32(&clock_manager_base->per_pll.en, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); - /* Configures drv_sel and smpl_sel */ - drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL; - smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL; - - debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel); - writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel), - &system_manager_base->sdmmcgrp_ctrl); + debug("%s: drvsel %d smplsel %d\n", __func__, + priv->drvsel, priv->smplsel); + writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl); debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, readl(&system_manager_base->sdmmcgrp_ctrl)); @@ -44,87 +52,77 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); } -static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx) +static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev) { /* FIXME: probe from DT eventually too/ */ const unsigned long clk = cm_get_mmc_controller_clk_hz(); - struct dwmci_host *host; - fdt_addr_t reg_base; - int bus_width, fifo_depth; + struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + int fifo_depth; if (clk == 0) { - printf("DWMMC%d: MMC clock is zero!", idx); + printf("DWMMC: MMC clock is zero!"); return -EINVAL; } - /* Get the register address from the device node */ - reg_base = fdtdec_get_addr(blob, node, "reg"); - if (!reg_base) { - printf("DWMMC%d: Can't get base address\n", idx); - return -EINVAL; - } - - /* Get the bus width from the device node */ - bus_width = fdtdec_get_int(blob, node, "bus-width", 0); - if (bus_width <= 0) { - printf("DWMMC%d: Can't get bus-width\n", idx); - return -EINVAL; - } - - fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0); + fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "fifo-depth", 0); if (fifo_depth < 0) { - printf("DWMMC%d: Can't get FIFO depth\n", idx); + printf("DWMMC: Can't get FIFO depth\n"); return -EINVAL; } - /* Allocate the host */ - host = calloc(1, sizeof(*host)); - if (!host) - return -ENOMEM; - - host->name = "SOCFPGA DWMMC"; - host->ioaddr = (void *)reg_base; - host->buswidth = bus_width; + host->name = dev->name; + host->ioaddr = (void *)dev_get_addr(dev); + host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "bus-width", 4); host->clksel = socfpga_dwmci_clksel; - host->dev_index = idx; + + /* + * TODO(sjg@chromium.org): Remove the need for this hack. + * We only have one dwmmc block on gen5 SoCFPGA. + */ + host->dev_index = 0; /* Fixed clock divide by 4 which due to the SDMMC wrapper */ host->bus_hz = clk; host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); + priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "drvsel", 3); + priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "smplsel", 0); + host->priv = priv; - return add_dwmci(host, host->bus_hz, 400000); -} - -static int socfpga_dwmci_process_node(const void *blob, int nodes[], - int count) -{ - int i, node, ret; - - for (i = 0; i < count; i++) { - node = nodes[i]; - if (node <= 0) - continue; - - ret = socfpga_dwmci_of_probe(blob, node, i); - if (ret) { - printf("%s: failed to decode dev %d\n", __func__, i); - return ret; - } - } return 0; } -int socfpga_dwmmc_init(const void *blob) +static int socfpga_dwmmc_probe(struct udevice *dev) { - int nodes[2]; /* Max. two controllers. */ - int ret, count; + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + int ret; - count = fdtdec_find_aliases_for_id(blob, "mmc", - COMPAT_ALTERA_SOCFPGA_DWMMC, - nodes, ARRAY_SIZE(nodes)); + ret = add_dwmci(host, host->bus_hz, 400000); + if (ret) + return ret; - ret = socfpga_dwmci_process_node(blob, nodes, count); + upriv->mmc = host->mmc; - return ret; + return 0; } + +static const struct udevice_id socfpga_dwmmc_ids[] = { + { .compatible = "altr,socfpga-dw-mshc" }, + { } +}; + +U_BOOT_DRIVER(socfpga_dwmmc_drv) = { + .name = "socfpga_dwmmc", + .id = UCLASS_MMC, + .of_match = socfpga_dwmmc_ids, + .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata, + .probe = socfpga_dwmmc_probe, + .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data), +}; diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index e169b77..4fe3da9 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013 Inc. + * (C) Copyright 2013 - 2015 Xilinx, Inc. * * Xilinx Zynq SD Host Controller Interface * @@ -7,55 +7,48 @@ */ #include <common.h> +#include <dm.h> #include <fdtdec.h> #include <libfdt.h> #include <malloc.h> #include <sdhci.h> -#include <asm/arch/sys_proto.h> -int zynq_sdhci_init(phys_addr_t regbase) +static int arasan_sdhci_probe(struct udevice *dev) { - struct sdhci_host *host = NULL; + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct sdhci_host *host = dev_get_priv(dev); - host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); - if (!host) { - printf("zynq_sdhci_init: sdhci_host malloc fail\n"); - return 1; - } - - host->name = "zynq_sdhci"; - host->ioaddr = (void *)regbase; host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; host->version = sdhci_readw(host, SDHCI_HOST_VERSION); - add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, 52000000 >> 9); + add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, 0); + + upriv->mmc = host->mmc; + return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) -int zynq_sdhci_of_init(const void *blob) +static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) { - int offset = 0; - u32 ret = 0; - phys_addr_t reg; - - debug("ZYNQ SDHCI: Initialization\n"); - - do { - offset = fdt_node_offset_by_compatible(blob, offset, - "arasan,sdhci-8.9a"); - if (offset != -1) { - reg = fdtdec_get_addr(blob, offset, "reg"); - if (reg != FDT_ADDR_T_NONE) { - ret |= zynq_sdhci_init(reg); - } else { - debug("ZYNQ SDHCI: Can't get base address\n"); - return -1; - } - } - } while (offset != -1); - - return ret; + struct sdhci_host *host = dev_get_priv(dev); + + host->name = (char *)dev->name; + host->ioaddr = (void *)dev_get_addr(dev); + + return 0; } -#endif + +static const struct udevice_id arasan_sdhci_ids[] = { + { .compatible = "arasan,sdhci-8.9a" }, + { } +}; + +U_BOOT_DRIVER(arasan_sdhci_drv) = { + .name = "arasan_sdhci", + .id = UCLASS_MMC, + .of_match = arasan_sdhci_ids, + .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, + .probe = arasan_sdhci_probe, + .priv_auto_alloc_size = sizeof(struct sdhci_host), +}; diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c index 50c6e0e..a9148a7 100644 --- a/drivers/mtd/altera_qspi.c +++ b/drivers/mtd/altera_qspi.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <console.h> #include <dm.h> #include <errno.h> #include <fdt_support.h> @@ -14,6 +15,14 @@ DECLARE_GLOBAL_DATA_PTR; +/* The STATUS register */ +#define QUADSPI_SR_BP0 BIT(2) +#define QUADSPI_SR_BP1 BIT(3) +#define QUADSPI_SR_BP2 BIT(4) +#define QUADSPI_SR_BP2_0 GENMASK(4, 2) +#define QUADSPI_SR_BP3 BIT(6) +#define QUADSPI_SR_TB BIT(5) + /* * The QUADSPI_MEM_OP register is used to do memory protect and erase operations */ @@ -44,12 +53,32 @@ struct altera_qspi_platdata { unsigned long size; }; +static uint flash_verbose; flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */ +static void altera_qspi_get_locked_range(struct mtd_info *mtd, loff_t *ofs, + uint64_t *len); + void flash_print_info(flash_info_t *info) { + struct mtd_info *mtd = info->mtd; + loff_t ofs; + u64 len; + printf("Altera QSPI flash Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + altera_qspi_get_locked_range(mtd, &ofs, &len); + printf(" %08lX +%lX", info->start[0], info->size); + if (len) { + printf(", protected %08llX +%llX", + info->start[0] + ofs, len); + } + putc('\n'); +} + +void flash_set_verbose(uint v) +{ + flash_verbose = v; } int flash_erase(flash_info_t *info, int s_first, int s_last) @@ -59,12 +88,16 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) int ret; memset(&instr, 0, sizeof(instr)); + instr.mtd = mtd; instr.addr = mtd->erasesize * s_first; instr.len = mtd->erasesize * (s_last + 1 - s_first); + flash_set_verbose(1); ret = mtd_erase(mtd, &instr); + flash_set_verbose(0); if (ret) - return ERR_NOT_ERASED; + return ERR_PROTECTED; + puts(" done\n"); return 0; } @@ -80,7 +113,7 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) ret = mtd_write(mtd, to, cnt, &retlen, src); if (ret) - return ERR_NOT_ERASED; + return ERR_PROTECTED; return 0; } @@ -108,23 +141,49 @@ static int altera_qspi_erase(struct mtd_info *mtd, struct erase_info *instr) size_t end = addr + len; u32 sect; u32 stat; + u32 *flash, *last; instr->state = MTD_ERASING; addr &= ~(mtd->erasesize - 1); /* get lower aligned address */ while (addr < end) { - sect = addr / mtd->erasesize; - sect <<= 8; - sect |= QUADSPI_MEM_OP_SECTOR_ERASE; - debug("erase %08x\n", sect); - writel(sect, ®s->mem_op); - stat = readl(®s->isr); - if (stat & QUADSPI_ISR_ILLEGAL_ERASE) { - /* erase failed, sector might be protected */ - debug("erase %08x fail %x\n", sect, stat); - writel(stat, ®s->isr); /* clear isr */ + if (ctrlc()) { + if (flash_verbose) + putc('\n'); + instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN; instr->state = MTD_ERASE_FAILED; + mtd_erase_callback(instr); return -EIO; } + flash = pdata->base + addr; + last = pdata->base + addr + mtd->erasesize; + /* skip erase if sector is blank */ + while (flash < last) { + if (readl(flash) != 0xffffffff) + break; + flash++; + } + if (flash < last) { + sect = addr / mtd->erasesize; + sect <<= 8; + sect |= QUADSPI_MEM_OP_SECTOR_ERASE; + debug("erase %08x\n", sect); + writel(sect, ®s->mem_op); + stat = readl(®s->isr); + if (stat & QUADSPI_ISR_ILLEGAL_ERASE) { + /* erase failed, sector might be protected */ + debug("erase %08x fail %x\n", sect, stat); + writel(stat, ®s->isr); /* clear isr */ + instr->fail_addr = addr; + instr->state = MTD_ERASE_FAILED; + mtd_erase_callback(instr); + return -EIO; + } + if (flash_verbose) + putc('.'); + } else { + if (flash_verbose) + putc(','); + } addr += mtd->erasesize; } instr->state = MTD_ERASE_DONE; @@ -171,6 +230,77 @@ static void altera_qspi_sync(struct mtd_info *mtd) { } +static void altera_qspi_get_locked_range(struct mtd_info *mtd, loff_t *ofs, + uint64_t *len) +{ + struct udevice *dev = mtd->dev; + struct altera_qspi_platdata *pdata = dev_get_platdata(dev); + struct altera_qspi_regs *regs = pdata->regs; + int shift0 = ffs(QUADSPI_SR_BP2_0) - 1; + int shift3 = ffs(QUADSPI_SR_BP3) - 1 - 3; + u32 stat = readl(®s->rd_status); + unsigned pow = ((stat & QUADSPI_SR_BP2_0) >> shift0) | + ((stat & QUADSPI_SR_BP3) >> shift3); + + *ofs = 0; + *len = 0; + if (pow) { + *len = mtd->erasesize << (pow - 1); + if (*len > mtd->size) + *len = mtd->size; + if (!(stat & QUADSPI_SR_TB)) + *ofs = mtd->size - *len; + } +} + +static int altera_qspi_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) +{ + struct udevice *dev = mtd->dev; + struct altera_qspi_platdata *pdata = dev_get_platdata(dev); + struct altera_qspi_regs *regs = pdata->regs; + u32 sector_start, sector_end; + u32 num_sectors; + u32 mem_op; + u32 sr_bp; + u32 sr_tb; + + num_sectors = mtd->size / mtd->erasesize; + sector_start = ofs / mtd->erasesize; + sector_end = (ofs + len) / mtd->erasesize; + + if (sector_start >= num_sectors / 2) { + sr_bp = fls(num_sectors - 1 - sector_start) + 1; + sr_tb = 0; + } else if (sector_end < num_sectors / 2) { + sr_bp = fls(sector_end) + 1; + sr_tb = 1; + } else { + sr_bp = 15; + sr_tb = 0; + } + + mem_op = (sr_tb << 12) | (sr_bp << 8); + mem_op |= QUADSPI_MEM_OP_SECTOR_PROTECT; + debug("lock %08x\n", mem_op); + writel(mem_op, ®s->mem_op); + + return 0; +} + +static int altera_qspi_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) +{ + struct udevice *dev = mtd->dev; + struct altera_qspi_platdata *pdata = dev_get_platdata(dev); + struct altera_qspi_regs *regs = pdata->regs; + u32 mem_op; + + mem_op = QUADSPI_MEM_OP_SECTOR_PROTECT; + debug("unlock %08x\n", mem_op); + writel(mem_op, ®s->mem_op); + + return 0; +} + static int altera_qspi_probe(struct udevice *dev) { struct altera_qspi_platdata *pdata = dev_get_platdata(dev); @@ -196,6 +326,8 @@ static int altera_qspi_probe(struct udevice *dev) mtd->_read = altera_qspi_read; mtd->_write = altera_qspi_write; mtd->_sync = altera_qspi_sync; + mtd->_lock = altera_qspi_lock; + mtd->_unlock = altera_qspi_unlock; mtd->numeraseregions = 0; mtd->erasesize = 0x10000; if (add_mtd_device(mtd)) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 1565a9a..f65b499 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -451,7 +451,7 @@ static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info, } /** - * NOTE: it is a must to set ND_RUN firstly, then write + * NOTE: it is a must to set ND_RUN first, then write * command buffer, otherwise, it does not work. * We enable all the interrupt at the same time, and * let pxa3xx_nand_irq to handle all logic. diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index cf4e7e1..c665836 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -12,11 +12,7 @@ obj-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o endif -#ifndef CONFIG_DM_SPI -obj-$(CONFIG_SPI_FLASH) += sf_probe.o -#endif -obj-$(CONFIG_CMD_SF) += sf.o -obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o +obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o sf_params.o sf.o obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 85c8a89..ed5c391 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -44,13 +44,10 @@ enum { #endif SECT_32K = 1 << 1, E_FSR = 1 << 2, - SST_BP = 1 << 3, - SST_WP = 1 << 4, - WR_QPP = 1 << 5, + SST_WR = 1 << 3, + WR_QPP = 1 << 4, }; -#define SST_WR (SST_BP | SST_WP) - enum spi_nor_option_flags { SNOR_F_SST_WR = (1 << 0), SNOR_F_USE_FSR = (1 << 1), @@ -66,6 +63,7 @@ enum spi_nor_option_flags { #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 #define SPI_FLASH_CFI_MFR_SST 0xbf #define SPI_FLASH_CFI_MFR_WINBOND 0xef +#define SPI_FLASH_CFI_MFR_ATMEL 0x1f /* Erase commands */ #define CMD_ERASE_4K 0x20 @@ -171,12 +169,6 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, /* Flash erase(sectors) operation, support all possible erase commands */ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); -/* Read the status register */ -int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs); - -/* Program the status register */ -int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws); - /* Lock stmicro spi flash region */ int stm_lock(struct spi_flash *flash, u32 ofs, size_t len); @@ -186,12 +178,6 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len); /* Check if a stmicro spi flash region is completely locked */ int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len); -/* Read the config register */ -int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc); - -/* Program the config register */ -int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc); - /* Enable writing on the SPI flash */ static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) { @@ -205,12 +191,6 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) } /* - * Send the read status command to the device and wait for the wip - * (write-in-progress) bit to clear itself. - */ -int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout); - -/* * Used for spi_flash write operation * - SPI claim * - spi_flash_cmd_write_enable @@ -245,4 +225,16 @@ int spi_flash_mtd_register(struct spi_flash *flash); void spi_flash_mtd_unregister(void); #endif +/** + * spi_flash_scan - scan the SPI FLASH + * @flash: the spi flash structure + * + * The drivers can use this fuction to scan the SPI FLASH. + * In the scanning, it will try to get all the necessary information to + * fill the spi_flash{}. + * + * Return: 0 for success, others for failure. + */ +int spi_flash_scan(struct spi_flash *flash); + #endif /* _SF_INTERNAL_H_ */ diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index a619182..0cafc29 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -11,327 +11,21 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <fdtdec.h> #include <malloc.h> -#include <mapmem.h> #include <spi.h> #include <spi_flash.h> -#include <asm/io.h> #include "sf_internal.h" -DECLARE_GLOBAL_DATA_PTR; - -/* Read commands array */ -static u8 spi_read_cmds_array[] = { - CMD_READ_ARRAY_SLOW, - CMD_READ_ARRAY_FAST, - CMD_READ_DUAL_OUTPUT_FAST, - CMD_READ_DUAL_IO_FAST, - CMD_READ_QUAD_OUTPUT_FAST, - CMD_READ_QUAD_IO_FAST, -}; - -#ifdef CONFIG_SPI_FLASH_MACRONIX -static int spi_flash_set_qeb_mxic(struct spi_flash *flash) -{ - u8 qeb_status; - int ret; - - ret = spi_flash_cmd_read_status(flash, &qeb_status); - if (ret < 0) - return ret; - - if (qeb_status & STATUS_QEB_MXIC) { - debug("SF: mxic: QEB is already set\n"); - } else { - ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC); - if (ret < 0) - return ret; - } - - return ret; -} -#endif - -#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) -static int spi_flash_set_qeb_winspan(struct spi_flash *flash) -{ - u8 qeb_status; - int ret; - - ret = spi_flash_cmd_read_config(flash, &qeb_status); - if (ret < 0) - return ret; - - if (qeb_status & STATUS_QEB_WINSPAN) { - debug("SF: winspan: QEB is already set\n"); - } else { - ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN); - if (ret < 0) - return ret; - } - - return ret; -} -#endif - -static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0) -{ - switch (idcode0) { -#ifdef CONFIG_SPI_FLASH_MACRONIX - case SPI_FLASH_CFI_MFR_MACRONIX: - return spi_flash_set_qeb_mxic(flash); -#endif -#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) - case SPI_FLASH_CFI_MFR_SPANSION: - case SPI_FLASH_CFI_MFR_WINBOND: - return spi_flash_set_qeb_winspan(flash); -#endif -#ifdef CONFIG_SPI_FLASH_STMICRO - case SPI_FLASH_CFI_MFR_STMICRO: - debug("SF: QEB is volatile for %02x flash\n", idcode0); - return 0; -#endif - default: - printf("SF: Need set QEB func for %02x flash\n", idcode0); - return -1; - } -} - -#ifdef CONFIG_SPI_FLASH_BAR -static int spi_flash_read_bank(struct spi_flash *flash, u8 idcode0) -{ - u8 curr_bank = 0; - int ret; - - if (flash->size <= SPI_FLASH_16MB_BOUN) - goto bank_end; - - switch (idcode0) { - case SPI_FLASH_CFI_MFR_SPANSION: - flash->bank_read_cmd = CMD_BANKADDR_BRRD; - flash->bank_write_cmd = CMD_BANKADDR_BRWR; - default: - flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; - flash->bank_write_cmd = CMD_EXTNADDR_WREAR; - } - - ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1, - &curr_bank, 1); - if (ret) { - debug("SF: fail to read bank addr register\n"); - return ret; - } - -bank_end: - flash->bank_curr = curr_bank; - return 0; -} -#endif - -static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, - struct spi_flash *flash) -{ - const struct spi_flash_params *params; - u8 cmd; - u16 jedec = idcode[1] << 8 | idcode[2]; - u16 ext_jedec = idcode[3] << 8 | idcode[4]; - - /* Validate params from spi_flash_params table */ - params = spi_flash_params_table; - for (; params->name != NULL; params++) { - if ((params->jedec >> 16) == idcode[0]) { - if ((params->jedec & 0xFFFF) == jedec) { - if (params->ext_jedec == 0) - break; - else if (params->ext_jedec == ext_jedec) - break; - } - } - } - - if (!params->name) { - printf("SF: Unsupported flash IDs: "); - printf("manuf %02x, jedec %04x, ext_jedec %04x\n", - idcode[0], jedec, ext_jedec); - return -EPROTONOSUPPORT; - } - - /* Assign spi data */ - flash->spi = spi; - flash->name = params->name; - flash->memory_map = spi->memory_map; - flash->dual_flash = flash->spi->option; - - /* Assign spi flash flags */ - if (params->flags & SST_WR) - flash->flags |= SNOR_F_SST_WR; - - /* Assign spi_flash ops */ -#ifndef CONFIG_DM_SPI_FLASH - flash->write = spi_flash_cmd_write_ops; -#if defined(CONFIG_SPI_FLASH_SST) - if (flash->flags & SNOR_F_SST_WR) { - if (flash->spi->op_mode_tx & SPI_OPM_TX_BP) - flash->write = sst_write_bp; - else - flash->write = sst_write_wp; - } -#endif - flash->erase = spi_flash_cmd_erase_ops; - flash->read = spi_flash_cmd_read_ops; -#endif - - /* lock hooks are flash specific - assign them based on idcode0 */ - switch (idcode[0]) { -#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) - case SPI_FLASH_CFI_MFR_STMICRO: - case SPI_FLASH_CFI_MFR_SST: - flash->flash_lock = stm_lock; - flash->flash_unlock = stm_unlock; - flash->flash_is_locked = stm_is_locked; -#endif - break; - default: - debug("SF: Lock ops not supported for %02x flash\n", idcode[0]); - } - - /* Compute the flash size */ - flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; - /* - * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the - * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with - * the 0x4d00 Extended JEDEC code have 512b pages. All of the others - * have 256b pages. - */ - if (ext_jedec == 0x4d00) { - if ((jedec == 0x0215) || (jedec == 0x216)) - flash->page_size = 256; - else - flash->page_size = 512; - } else { - flash->page_size = 256; - } - flash->page_size <<= flash->shift; - flash->sector_size = params->sector_size << flash->shift; - flash->size = flash->sector_size * params->nr_sectors << flash->shift; -#ifdef CONFIG_SF_DUAL_FLASH - if (flash->dual_flash & SF_DUAL_STACKED_FLASH) - flash->size <<= 1; -#endif - - /* Compute erase sector and command */ - if (params->flags & SECT_4K) { - flash->erase_cmd = CMD_ERASE_4K; - flash->erase_size = 4096 << flash->shift; - } else if (params->flags & SECT_32K) { - flash->erase_cmd = CMD_ERASE_32K; - flash->erase_size = 32768 << flash->shift; - } else { - flash->erase_cmd = CMD_ERASE_64K; - flash->erase_size = flash->sector_size; - } - - /* Now erase size becomes valid sector size */ - flash->sector_size = flash->erase_size; - - /* Look for the fastest read cmd */ - cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx); - if (cmd) { - cmd = spi_read_cmds_array[cmd - 1]; - flash->read_cmd = cmd; - } else { - /* Go for default supported read cmd */ - flash->read_cmd = CMD_READ_ARRAY_FAST; - } - - /* Not require to look for fastest only two write cmds yet */ - if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP) - flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; - else - /* Go for default supported write cmd */ - flash->write_cmd = CMD_PAGE_PROGRAM; - - /* Read dummy_byte: dummy byte is determined based on the - * dummy cycles of a particular command. - * Fast commands - dummy_byte = dummy_cycles/8 - * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8 - * For I/O commands except cmd[0] everything goes on no.of lines - * based on particular command but incase of fast commands except - * data all go on single line irrespective of command. - */ - switch (flash->read_cmd) { - case CMD_READ_QUAD_IO_FAST: - flash->dummy_byte = 2; - break; - case CMD_READ_ARRAY_SLOW: - flash->dummy_byte = 0; - break; - default: - flash->dummy_byte = 1; - } - -#ifdef CONFIG_SPI_FLASH_STMICRO - if (params->flags & E_FSR) - flash->flags |= SNOR_F_USE_FSR; -#endif - - /* Configure the BAR - discover bank cmds and read current bank */ -#ifdef CONFIG_SPI_FLASH_BAR - int ret = spi_flash_read_bank(flash, idcode[0]); - if (ret < 0) - return ret; -#endif - - /* Flash powers up read-only, so clear BP# bits */ -#if defined(CONFIG_SPI_FLASH_ATMEL) || \ - defined(CONFIG_SPI_FLASH_MACRONIX) || \ - defined(CONFIG_SPI_FLASH_SST) - spi_flash_cmd_write_status(flash, 0); -#endif - - return 0; -} - -#if CONFIG_IS_ENABLED(OF_CONTROL) -int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) -{ - fdt_addr_t addr; - fdt_size_t size; - int node; - - /* If there is no node, do nothing */ - node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); - if (node < 0) - return 0; - - addr = fdtdec_get_addr_size(blob, node, "memory-map", &size); - if (addr == FDT_ADDR_T_NONE) { - debug("%s: Cannot decode address\n", __func__); - return 0; - } - - if (flash->size != size) { - debug("%s: Memory map must cover entire device\n", __func__); - return -1; - } - flash->memory_map = map_sysmem(addr, size); - - return 0; -} -#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ - /** * spi_flash_probe_slave() - Probe for a SPI flash device on a bus * - * @spi: Bus to probe * @flashp: Pointer to place to put flash info, which may be NULL if the * space should be allocated */ -int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash) +static int spi_flash_probe_slave(struct spi_flash *flash) { - u8 idcode[5]; + struct spi_slave *spi = flash->spi; int ret; /* Setup spi_slave */ @@ -347,59 +41,12 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash) return ret; } - /* Read the ID codes */ - ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); + ret = spi_flash_scan(flash); if (ret) { - printf("SF: Failed to get idcodes\n"); - goto err_read_id; - } - -#ifdef DEBUG - printf("SF: Got idcodes\n"); - print_buffer(0, idcode, 1, sizeof(idcode), 0); -#endif - - if (spi_flash_validate_params(spi, idcode, flash)) { ret = -EINVAL; goto err_read_id; } - /* Set the quad enable bit - only for quad commands */ - if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || - (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || - (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { - if (spi_flash_set_qeb(flash, idcode[0])) { - debug("SF: Fail to set QEB for %02x\n", idcode[0]); - ret = -EINVAL; - goto err_read_id; - } - } - -#if CONFIG_IS_ENABLED(OF_CONTROL) - if (spi_flash_decode_fdt(gd->fdt_blob, flash)) { - debug("SF: FDT decode error\n"); - ret = -EINVAL; - goto err_read_id; - } -#endif -#ifndef CONFIG_SPL_BUILD - printf("SF: Detected %s with page size ", flash->name); - print_size(flash->page_size, ", erase size "); - print_size(flash->erase_size, ", total "); - print_size(flash->size, ""); - if (flash->memory_map) - printf(", mapped at %p", flash->memory_map); - puts("\n"); -#endif -#ifndef CONFIG_SPI_FLASH_BAR - if (((flash->dual_flash == SF_SINGLE_FLASH) && - (flash->size > SPI_FLASH_16MB_BOUN)) || - ((flash->dual_flash > SF_SINGLE_FLASH) && - (flash->size > SPI_FLASH_16MB_BOUN << 1))) { - puts("SF: Warning - Only lower 16MiB accessible,"); - puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); - } -#endif #ifdef CONFIG_SPI_FLASH_MTD ret = spi_flash_mtd_register(flash); #endif @@ -410,7 +57,7 @@ err_read_id: } #ifndef CONFIG_DM_SPI_FLASH -struct spi_flash *spi_flash_probe_tail(struct spi_slave *bus) +static struct spi_flash *spi_flash_probe_tail(struct spi_slave *bus) { struct spi_flash *flash; @@ -421,7 +68,8 @@ struct spi_flash *spi_flash_probe_tail(struct spi_slave *bus) return NULL; } - if (spi_flash_probe_slave(bus, flash)) { + flash->spi = bus; + if (spi_flash_probe_slave(flash)) { spi_free_slave(bus); free(flash); return NULL; @@ -473,7 +121,7 @@ static int spi_flash_std_read(struct udevice *dev, u32 offset, size_t len, return spi_flash_cmd_read_ops(flash, offset, len, buf); } -int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len, +static int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len, const void *buf) { struct spi_flash *flash = dev_get_uclass_priv(dev); @@ -490,14 +138,14 @@ int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len, return spi_flash_cmd_write_ops(flash, offset, len, buf); } -int spi_flash_std_erase(struct udevice *dev, u32 offset, size_t len) +static int spi_flash_std_erase(struct udevice *dev, u32 offset, size_t len) { struct spi_flash *flash = dev_get_uclass_priv(dev); return spi_flash_cmd_erase_ops(flash, offset, len); } -int spi_flash_std_probe(struct udevice *dev) +static int spi_flash_std_probe(struct udevice *dev) { struct spi_slave *slave = dev_get_parent_priv(dev); struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); @@ -505,8 +153,9 @@ int spi_flash_std_probe(struct udevice *dev) flash = dev_get_uclass_priv(dev); flash->dev = dev; + flash->spi = slave; debug("%s: slave=%p, cs=%d\n", __func__, slave, plat->cs); - return spi_flash_probe_slave(slave, flash); + return spi_flash_probe_slave(flash); } static const struct dm_spi_flash_ops spi_flash_std_ops = { diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/spi_flash.c index 3a56d7f..7ffa136 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/spi_flash.c @@ -1,9 +1,10 @@ /* - * SPI flash operations + * SPI Flash Core * - * Copyright (C) 2008 Atmel Corporation - * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik + * Copyright (C) 2015 Jagan Teki <jteki@openedev.com> * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. + * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik + * Copyright (C) 2008 Atmel Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -11,14 +12,15 @@ #include <common.h> #include <errno.h> #include <malloc.h> +#include <mapmem.h> #include <spi.h> #include <spi_flash.h> -#include <watchdog.h> -#include <linux/compiler.h> #include <linux/log2.h> #include "sf_internal.h" +DECLARE_GLOBAL_DATA_PTR; + static void spi_flash_addr(u32 addr, u8 *cmd) { /* cmd[0] is actual command */ @@ -27,7 +29,17 @@ static void spi_flash_addr(u32 addr, u8 *cmd) cmd[3] = addr >> 0; } -int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs) +/* Read commands array */ +static u8 spi_read_cmds_array[] = { + CMD_READ_ARRAY_SLOW, + CMD_READ_ARRAY_FAST, + CMD_READ_DUAL_OUTPUT_FAST, + CMD_READ_DUAL_IO_FAST, + CMD_READ_QUAD_OUTPUT_FAST, + CMD_READ_QUAD_IO_FAST, +}; + +static int read_sr(struct spi_flash *flash, u8 *rs) { int ret; u8 cmd; @@ -56,7 +68,7 @@ static int read_fsr(struct spi_flash *flash, u8 *fsr) return 0; } -int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws) +static int write_sr(struct spi_flash *flash, u8 ws) { u8 cmd; int ret; @@ -72,7 +84,7 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws) } #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) -int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc) +static int read_cr(struct spi_flash *flash, u8 *rc) { int ret; u8 cmd; @@ -87,13 +99,13 @@ int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc) return 0; } -int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc) +static int write_cr(struct spi_flash *flash, u8 wc) { u8 data[2]; u8 cmd; int ret; - ret = spi_flash_cmd_read_status(flash, &data[0]); + ret = read_sr(flash, &data[0]); if (ret < 0) return ret; @@ -110,7 +122,7 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc) #endif #ifdef CONFIG_SPI_FLASH_BAR -static int spi_flash_write_bank(struct spi_flash *flash, u32 offset) +static int spi_flash_write_bar(struct spi_flash *flash, u32 offset) { u8 cmd, bank_sel; int ret; @@ -130,10 +142,40 @@ bar_end: flash->bank_curr = bank_sel; return flash->bank_curr; } + +static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) +{ + u8 curr_bank = 0; + int ret; + + if (flash->size <= SPI_FLASH_16MB_BOUN) + goto bank_end; + + switch (idcode0) { + case SPI_FLASH_CFI_MFR_SPANSION: + flash->bank_read_cmd = CMD_BANKADDR_BRRD; + flash->bank_write_cmd = CMD_BANKADDR_BRWR; + break; + default: + flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; + flash->bank_write_cmd = CMD_EXTNADDR_WREAR; + } + + ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1, + &curr_bank, 1); + if (ret) { + debug("SF: fail to read bank addr register\n"); + return ret; + } + +bank_end: + flash->bank_curr = curr_bank; + return 0; +} #endif #ifdef CONFIG_SF_DUAL_FLASH -static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr) +static void spi_flash_dual(struct spi_flash *flash, u32 *addr) { switch (flash->dual_flash) { case SF_DUAL_STACKED_FLASH: @@ -159,7 +201,7 @@ static int spi_flash_sr_ready(struct spi_flash *flash) u8 sr; int ret; - ret = spi_flash_cmd_read_status(flash, &sr); + ret = read_sr(flash, &sr); if (ret < 0) return ret; @@ -196,7 +238,8 @@ static int spi_flash_ready(struct spi_flash *flash) return sr && fsr; } -int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) +static int spi_flash_cmd_wait_ready(struct spi_flash *flash, + unsigned long timeout) { int timebase, ret; @@ -282,10 +325,10 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) #ifdef CONFIG_SF_DUAL_FLASH if (flash->dual_flash > SF_SINGLE_FLASH) - spi_flash_dual_flash(flash, &erase_addr); + spi_flash_dual(flash, &erase_addr); #endif #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_write_bank(flash, erase_addr); + ret = spi_flash_write_bar(flash, erase_addr); if (ret < 0) return ret; #endif @@ -332,10 +375,10 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, #ifdef CONFIG_SF_DUAL_FLASH if (flash->dual_flash > SF_SINGLE_FLASH) - spi_flash_dual_flash(flash, &write_addr); + spi_flash_dual(flash, &write_addr); #endif #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_write_bank(flash, write_addr); + ret = spi_flash_write_bar(flash, write_addr); if (ret < 0) return ret; #endif @@ -427,10 +470,10 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, #ifdef CONFIG_SF_DUAL_FLASH if (flash->dual_flash > SF_SINGLE_FLASH) - spi_flash_dual_flash(flash, &read_addr); + spi_flash_dual(flash, &read_addr); #endif #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_write_bank(flash, read_addr); + ret = spi_flash_write_bar(flash, read_addr); if (ret < 0) return ret; bank_sel = flash->bank_curr; @@ -628,7 +671,7 @@ int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len) int status; u8 sr; - status = spi_flash_cmd_read_status(flash, &sr); + status = read_sr(flash, &sr); if (status < 0) return status; @@ -665,7 +708,7 @@ int stm_lock(struct spi_flash *flash, u32 ofs, size_t len) u8 shift = ffs(mask) - 1, pow, val; int ret; - ret = spi_flash_cmd_read_status(flash, &status_old); + ret = read_sr(flash, &status_old); if (ret < 0) return ret; @@ -702,7 +745,7 @@ int stm_lock(struct spi_flash *flash, u32 ofs, size_t len) if ((status_new & mask) <= (status_old & mask)) return -EINVAL; - spi_flash_cmd_write_status(flash, status_new); + write_sr(flash, status_new); return 0; } @@ -719,7 +762,7 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len) u8 shift = ffs(mask) - 1, pow, val; int ret; - ret = spi_flash_cmd_read_status(flash, &status_old); + ret = read_sr(flash, &status_old); if (ret < 0) return ret; @@ -752,8 +795,321 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len) if ((status_new & mask) >= (status_old & mask)) return -EINVAL; - spi_flash_cmd_write_status(flash, status_new); + write_sr(flash, status_new); return 0; } #endif + + +#ifdef CONFIG_SPI_FLASH_MACRONIX +static int spi_flash_set_qeb_mxic(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = read_sr(flash, &qeb_status); + if (ret < 0) + return ret; + + if (qeb_status & STATUS_QEB_MXIC) { + debug("SF: mxic: QEB is already set\n"); + } else { + ret = write_sr(flash, STATUS_QEB_MXIC); + if (ret < 0) + return ret; + } + + return ret; +} +#endif + +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) +static int spi_flash_set_qeb_winspan(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = read_cr(flash, &qeb_status); + if (ret < 0) + return ret; + + if (qeb_status & STATUS_QEB_WINSPAN) { + debug("SF: winspan: QEB is already set\n"); + } else { + ret = write_cr(flash, STATUS_QEB_WINSPAN); + if (ret < 0) + return ret; + } + + return ret; +} +#endif + +static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0) +{ + switch (idcode0) { +#ifdef CONFIG_SPI_FLASH_MACRONIX + case SPI_FLASH_CFI_MFR_MACRONIX: + return spi_flash_set_qeb_mxic(flash); +#endif +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) + case SPI_FLASH_CFI_MFR_SPANSION: + case SPI_FLASH_CFI_MFR_WINBOND: + return spi_flash_set_qeb_winspan(flash); +#endif +#ifdef CONFIG_SPI_FLASH_STMICRO + case SPI_FLASH_CFI_MFR_STMICRO: + debug("SF: QEB is volatile for %02x flash\n", idcode0); + return 0; +#endif + default: + printf("SF: Need set QEB func for %02x flash\n", idcode0); + return -1; + } +} + +#if CONFIG_IS_ENABLED(OF_CONTROL) +int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) +{ + fdt_addr_t addr; + fdt_size_t size; + int node; + + /* If there is no node, do nothing */ + node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); + if (node < 0) + return 0; + + addr = fdtdec_get_addr_size(blob, node, "memory-map", &size); + if (addr == FDT_ADDR_T_NONE) { + debug("%s: Cannot decode address\n", __func__); + return 0; + } + + if (flash->size != size) { + debug("%s: Memory map must cover entire device\n", __func__); + return -1; + } + flash->memory_map = map_sysmem(addr, size); + + return 0; +} +#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ + +int spi_flash_scan(struct spi_flash *flash) +{ + struct spi_slave *spi = flash->spi; + const struct spi_flash_params *params; + u16 jedec, ext_jedec; + u8 idcode[5]; + u8 cmd; + int ret; + + /* Read the ID codes */ + ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); + if (ret) { + printf("SF: Failed to get idcodes\n"); + return -EINVAL; + } + +#ifdef DEBUG + printf("SF: Got idcodes\n"); + print_buffer(0, idcode, 1, sizeof(idcode), 0); +#endif + + jedec = idcode[1] << 8 | idcode[2]; + ext_jedec = idcode[3] << 8 | idcode[4]; + + /* Validate params from spi_flash_params table */ + params = spi_flash_params_table; + for (; params->name != NULL; params++) { + if ((params->jedec >> 16) == idcode[0]) { + if ((params->jedec & 0xFFFF) == jedec) { + if (params->ext_jedec == 0) + break; + else if (params->ext_jedec == ext_jedec) + break; + } + } + } + + if (!params->name) { + printf("SF: Unsupported flash IDs: "); + printf("manuf %02x, jedec %04x, ext_jedec %04x\n", + idcode[0], jedec, ext_jedec); + return -EPROTONOSUPPORT; + } + + /* Flash powers up read-only, so clear BP# bits */ + if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL || + idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX || + idcode[0] == SPI_FLASH_CFI_MFR_SST) + write_sr(flash, 0); + + /* Assign spi data */ + flash->name = params->name; + flash->memory_map = spi->memory_map; + flash->dual_flash = flash->spi->option; + + /* Assign spi flash flags */ + if (params->flags & SST_WR) + flash->flags |= SNOR_F_SST_WR; + + /* Assign spi_flash ops */ +#ifndef CONFIG_DM_SPI_FLASH + flash->write = spi_flash_cmd_write_ops; +#if defined(CONFIG_SPI_FLASH_SST) + if (flash->flags & SNOR_F_SST_WR) { + if (flash->spi->op_mode_tx & SPI_OPM_TX_BP) + flash->write = sst_write_bp; + else + flash->write = sst_write_wp; + } +#endif + flash->erase = spi_flash_cmd_erase_ops; + flash->read = spi_flash_cmd_read_ops; +#endif + + /* lock hooks are flash specific - assign them based on idcode0 */ + switch (idcode[0]) { +#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) + case SPI_FLASH_CFI_MFR_STMICRO: + case SPI_FLASH_CFI_MFR_SST: + flash->flash_lock = stm_lock; + flash->flash_unlock = stm_unlock; + flash->flash_is_locked = stm_is_locked; +#endif + break; + default: + debug("SF: Lock ops not supported for %02x flash\n", idcode[0]); + } + + /* Compute the flash size */ + flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; + /* + * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the + * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with + * the 0x4d00 Extended JEDEC code have 512b pages. All of the others + * have 256b pages. + */ + if (ext_jedec == 0x4d00) { + if ((jedec == 0x0215) || (jedec == 0x216)) + flash->page_size = 256; + else + flash->page_size = 512; + } else { + flash->page_size = 256; + } + flash->page_size <<= flash->shift; + flash->sector_size = params->sector_size << flash->shift; + flash->size = flash->sector_size * params->nr_sectors << flash->shift; +#ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash & SF_DUAL_STACKED_FLASH) + flash->size <<= 1; +#endif + + /* Compute erase sector and command */ + if (params->flags & SECT_4K) { + flash->erase_cmd = CMD_ERASE_4K; + flash->erase_size = 4096 << flash->shift; + } else if (params->flags & SECT_32K) { + flash->erase_cmd = CMD_ERASE_32K; + flash->erase_size = 32768 << flash->shift; + } else { + flash->erase_cmd = CMD_ERASE_64K; + flash->erase_size = flash->sector_size; + } + + /* Now erase size becomes valid sector size */ + flash->sector_size = flash->erase_size; + + /* Look for the fastest read cmd */ + cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx); + if (cmd) { + cmd = spi_read_cmds_array[cmd - 1]; + flash->read_cmd = cmd; + } else { + /* Go for default supported read cmd */ + flash->read_cmd = CMD_READ_ARRAY_FAST; + } + + /* Not require to look for fastest only two write cmds yet */ + if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP) + flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; + else + /* Go for default supported write cmd */ + flash->write_cmd = CMD_PAGE_PROGRAM; + + /* Set the quad enable bit - only for quad commands */ + if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || + (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || + (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { + ret = spi_flash_set_qeb(flash, idcode[0]); + if (ret) { + debug("SF: Fail to set QEB for %02x\n", idcode[0]); + return -EINVAL; + } + } + + /* Read dummy_byte: dummy byte is determined based on the + * dummy cycles of a particular command. + * Fast commands - dummy_byte = dummy_cycles/8 + * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8 + * For I/O commands except cmd[0] everything goes on no.of lines + * based on particular command but incase of fast commands except + * data all go on single line irrespective of command. + */ + switch (flash->read_cmd) { + case CMD_READ_QUAD_IO_FAST: + flash->dummy_byte = 2; + break; + case CMD_READ_ARRAY_SLOW: + flash->dummy_byte = 0; + break; + default: + flash->dummy_byte = 1; + } + +#ifdef CONFIG_SPI_FLASH_STMICRO + if (params->flags & E_FSR) + flash->flags |= SNOR_F_USE_FSR; +#endif + + /* Configure the BAR - discover bank cmds and read current bank */ +#ifdef CONFIG_SPI_FLASH_BAR + ret = spi_flash_read_bar(flash, idcode[0]); + if (ret < 0) + return ret; +#endif + +#if CONFIG_IS_ENABLED(OF_CONTROL) + ret = spi_flash_decode_fdt(gd->fdt_blob, flash); + if (ret) { + debug("SF: FDT decode error\n"); + return -EINVAL; + } +#endif + +#ifndef CONFIG_SPL_BUILD + printf("SF: Detected %s with page size ", flash->name); + print_size(flash->page_size, ", erase size "); + print_size(flash->erase_size, ", total "); + print_size(flash->size, ""); + if (flash->memory_map) + printf(", mapped at %p", flash->memory_map); + puts("\n"); +#endif + +#ifndef CONFIG_SPI_FLASH_BAR + if (((flash->dual_flash == SF_SINGLE_FLASH) && + (flash->size > SPI_FLASH_16MB_BOUN)) || + ((flash->dual_flash > SF_SINGLE_FLASH) && + (flash->size > SPI_FLASH_16MB_BOUN << 1))) { + puts("SF: Warning - Only lower 16MiB accessible,"); + puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); + } +#endif + + return ret; +} diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index a03a95d..de54ca8 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -88,6 +88,7 @@ config ETH_SANDBOX_RAW config ETH_DESIGNWARE bool "Synopsys Designware Ethernet MAC" + select PHYLIB help This MAC is present in SoCs from various vendors. It supports 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to @@ -101,4 +102,11 @@ config PCH_GBE This MAC is present in Intel Platform Controller Hub EG20T. It supports 10/100/1000 Mbps operation. +config ZYNQ_GEM + depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP) + select PHYLIB + bool "Xilinx Ethernet GEM" + help + This MAC is present in Xilinx Zynq and ZynqMP SoCs. + endif # NETDEVICES diff --git a/drivers/net/designware.c b/drivers/net/designware.c index a6c39c3..04114a1 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -22,10 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if !defined(CONFIG_PHYLIB) -# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB" -#endif - static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { struct eth_mac_regs *mac_p = bus->priv; @@ -107,8 +103,8 @@ static void tx_descs_init(struct dw_eth_dev *priv) #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | - DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ - DESC_TXSTS_TXCHECKINSCTRL | \ + DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | + DESC_TXSTS_TXCHECKINSCTRL | DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; @@ -155,7 +151,7 @@ static void rx_descs_init(struct dw_eth_dev *priv) desc_p->dmamac_next = &desc_table_p[idx + 1]; desc_p->dmamac_cntl = - (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ + (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | DESC_RXCTRL_RXCHAIN; desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; @@ -321,14 +317,14 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; - desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ + desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & DESC_TXCTRL_SIZE1MASK; desc_p->txrx_status &= ~(DESC_TXSTS_MSK); desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; #else - desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ - DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ + desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & + DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | DESC_TXCTRL_TXFIRST; desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; @@ -368,7 +364,7 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) /* Check if the owner is the CPU */ if (!(status & DESC_RXSTS_OWNBYDMA)) { - length = (status & DESC_RXSTS_FRMLENMSK) >> \ + length = (status & DESC_RXSTS_FRMLENMSK) >> DESC_RXSTS_FRMLENSHFT; /* Invalidate received data */ diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 3a1de59..7e312f1 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -242,8 +242,10 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) int off; uint32_t ph; phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset; +#ifndef CONFIG_SYS_FMAN_V3 u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET; +#endif off = fdt_node_offset_by_compat_reg(blob, prop, paddr); if (off == -FDT_ERR_NOTFOUND) @@ -295,8 +297,10 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) /* board code might have caused offset to change */ off = fdt_node_offset_by_compat_reg(blob, prop, paddr); +#ifndef CONFIG_SYS_FMAN_V3 /* Don't disable FM1-DTSEC1 MAC as its used for MDIO */ if (paddr != dtsec1_addr) +#endif fdt_status_disabled(blob, off); /* disable the MAC node */ /* disable the fsl,dpa-ethernet node that points to the MAC */ diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c index cf2cc95..93ba318 100644 --- a/drivers/net/fm/ls1043.c +++ b/drivers/net/fm/ls1043.c @@ -54,11 +54,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port) struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]); - if (is_device_disabled(port)) { - printf("%s:%d: port(%d) is disabled\n", __func__, - __LINE__, port); + if (is_device_disabled(port)) return PHY_INTERFACE_MODE_NONE; - } if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9))) return PHY_INTERFACE_MODE_XGMII; @@ -69,15 +66,11 @@ phy_interface_t fman_port_enet_if(enum fm_port port) if (port == FM1_DTSEC3) if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) == FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) { - printf("%s:%d: port(FM1_DTSEC3) is OK\n", - __func__, __LINE__); return PHY_INTERFACE_MODE_RGMII; } if (port == FM1_DTSEC4) if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) == FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) { - printf("%s:%d: port(FM1_DTSEC4) is OK\n", - __func__, __LINE__); return PHY_INTERFACE_MODE_RGMII; } diff --git a/drivers/net/fsl-mc/Makefile b/drivers/net/fsl-mc/Makefile index 7563a5f..a492388 100644 --- a/drivers/net/fsl-mc/Makefile +++ b/drivers/net/fsl-mc/Makefile @@ -10,5 +10,6 @@ obj-y += mc.o \ dpmng.o \ dprc.o \ dpbp.o \ - dpni.o + dpni.o \ + dpmac.o obj-y += dpio/ diff --git a/drivers/net/fsl-mc/dpbp.c b/drivers/net/fsl-mc/dpbp.c index 1517a70..ba9536d 100644 --- a/drivers/net/fsl-mc/dpbp.c +++ b/drivers/net/fsl-mc/dpbp.c @@ -49,6 +49,47 @@ int dpbp_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } +int dpbp_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpbp_cfg *cfg, + uint16_t *token) +{ + struct mc_command cmd = { 0 }; + int err; + + (void)(cfg); /* unused */ + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE, + cmd_flags, + 0); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + + return 0; +} + +int dpbp_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + int dpbp_enable(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token) diff --git a/drivers/net/fsl-mc/dpio/dpio.c b/drivers/net/fsl-mc/dpio/dpio.c index cd3fd50..b61df52 100644 --- a/drivers/net/fsl-mc/dpio/dpio.c +++ b/drivers/net/fsl-mc/dpio/dpio.c @@ -48,6 +48,46 @@ int dpio_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } +int dpio_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpio_cfg *cfg, + uint16_t *token) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPIO_CMDID_CREATE, + cmd_flags, + 0); + DPIO_CMD_CREATE(cmd, cfg); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + + return 0; +} + +int dpio_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPIO_CMDID_DESTROY, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + int dpio_enable(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token) diff --git a/drivers/net/fsl-mc/dpio/qbman_portal.c b/drivers/net/fsl-mc/dpio/qbman_portal.c index 5fa8d95..449ff8a 100644 --- a/drivers/net/fsl-mc/dpio/qbman_portal.c +++ b/drivers/net/fsl-mc/dpio/qbman_portal.c @@ -117,7 +117,7 @@ void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint32_t cmd_verb) { uint32_t *v = cmd; #ifdef QBMAN_CHECKING - BUG_ON(!p->mc.check != swp_mc_can_submit); + BUG_ON(p->mc.check != swp_mc_can_submit); #endif lwsync(); /* TBD: "|=" is going to hurt performance. Need to move as many fields diff --git a/drivers/net/fsl-mc/dpmac.c b/drivers/net/fsl-mc/dpmac.c new file mode 100644 index 0000000..072a90d --- /dev/null +++ b/drivers/net/fsl-mc/dpmac.c @@ -0,0 +1,222 @@ +/* + * Freescale Layerscape MC I/O wrapper + * + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Author: Prabhakar Kushwaha <prabhakar@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <fsl-mc/fsl_mc_sys.h> +#include <fsl-mc/fsl_mc_cmd.h> +#include <fsl-mc/fsl_dpmac.h> + +int dpmac_open(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + int dpmac_id, + uint16_t *token) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN, + cmd_flags, + 0); + DPMAC_CMD_OPEN(cmd, dpmac_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + + return err; +} + +int dpmac_close(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpmac_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpmac_cfg *cfg, + uint16_t *token) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE, + cmd_flags, + 0); + DPMAC_CMD_CREATE(cmd, cfg); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + + return 0; +} + +int dpmac_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_DESTROY, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpmac_get_attributes(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_attr *attr) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_ATTR, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPMAC_RSP_GET_ATTRIBUTES(cmd, attr); + + return 0; +} + +int dpmac_mdio_read(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_mdio_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_READ, + cmd_flags, + token); + DPMAC_CMD_MDIO_READ(cmd, cfg); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPMAC_RSP_MDIO_READ(cmd, cfg->data); + + return 0; +} + +int dpmac_mdio_write(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_mdio_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_WRITE, + cmd_flags, + token); + DPMAC_CMD_MDIO_WRITE(cmd, cfg); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpmac_get_link_cfg(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_link_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + int err = 0; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_LINK_CFG, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + DPMAC_RSP_GET_LINK_CFG(cmd, cfg); + + return 0; +} + +int dpmac_set_link_state(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_link_state *link_state) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE, + cmd_flags, + token); + DPMAC_CMD_SET_LINK_STATE(cmd, link_state); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpmac_get_counter(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpmac_counter type, + uint64_t *counter) +{ + struct mc_command cmd = { 0 }; + int err = 0; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_COUNTER, + cmd_flags, + token); + DPMAC_CMD_GET_COUNTER(cmd, type); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + DPMAC_RSP_GET_COUNTER(cmd, *counter); + + return 0; +} diff --git a/drivers/net/fsl-mc/dpni.c b/drivers/net/fsl-mc/dpni.c index 9111f35..eacb3c8 100644 --- a/drivers/net/fsl-mc/dpni.c +++ b/drivers/net/fsl-mc/dpni.c @@ -48,6 +48,46 @@ int dpni_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } +int dpni_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpni_cfg *cfg, + uint16_t *token) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_CREATE, + cmd_flags, + 0); + DPNI_CMD_CREATE(cmd, cfg); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + + return 0; +} + +int dpni_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_DESTROY, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + int dpni_set_pools(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, diff --git a/drivers/net/fsl-mc/dprc.c b/drivers/net/fsl-mc/dprc.c index 357aa48..7d34355 100644 --- a/drivers/net/fsl-mc/dprc.c +++ b/drivers/net/fsl-mc/dprc.c @@ -72,6 +72,52 @@ int dprc_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } +int dprc_create_container(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dprc_cfg *cfg, + int *child_container_id, + uint64_t *child_portal_paddr) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + DPRC_CMD_CREATE_CONTAINER(cmd, cfg); + + cmd.header = mc_encode_cmd_header(DPRC_CMDID_CREATE_CONT, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPRC_RSP_CREATE_CONTAINER(cmd, *child_container_id, + *child_portal_paddr); + + return 0; +} + +int dprc_destroy_container(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + int child_container_id) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_DESTROY_CONT, + cmd_flags, + token); + DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + int dprc_reset_container(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index ea987d7..bac4610 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -14,7 +14,9 @@ #include <fsl-mc/fsl_dpmng.h> #include <fsl-mc/fsl_dprc.h> #include <fsl-mc/fsl_dpio.h> +#include <fsl-mc/fsl_dpni.h> #include <fsl-mc/fsl_qbman_portal.h> +#include <fsl-mc/ldpaa_wriop.h> #define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024) #define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1)) @@ -24,12 +26,19 @@ #define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout" DECLARE_GLOBAL_DATA_PTR; -static int mc_boot_status; -struct fsl_mc_io *dflt_mc_io = NULL; +static int mc_boot_status = -1; +static int mc_dpl_applied = -1; +#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +static int mc_aiop_applied = -1; +#endif +struct fsl_mc_io *root_mc_io = NULL; +struct fsl_mc_io *dflt_mc_io = NULL; /* child container */ +uint16_t root_dprc_handle = 0; uint16_t dflt_dprc_handle = 0; +int child_dprc_id; struct fsl_dpbp_obj *dflt_dpbp = NULL; struct fsl_dpio_obj *dflt_dpio = NULL; -uint16_t dflt_dpio_handle = 0; +struct fsl_dpni_obj *dflt_dpni = NULL; #ifdef DEBUG void dump_ram_words(const char *title, void *addr) @@ -93,7 +102,8 @@ static int mc_copy_image(const char *title, * Returns 0 on success and a negative errno on error. * task fail. **/ -int parse_mc_firmware_fit_image(const void **raw_image_addr, +int parse_mc_firmware_fit_image(u64 mc_fw_addr, + const void **raw_image_addr, size_t *raw_image_size) { int format; @@ -103,36 +113,31 @@ int parse_mc_firmware_fit_image(const void **raw_image_addr, size_t size; const char *uname = "firmware"; - /* Check if the image is in NOR flash */ -#ifdef CONFIG_SYS_LS_MC_FW_IN_NOR - fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR; -#else -#error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined" -#endif + fit_hdr = (void *)mc_fw_addr; /* Check if Image is in FIT format */ format = genimg_get_format(fit_hdr); if (format != IMAGE_FORMAT_FIT) { - printf("fsl-mc: ERROR: Bad firmware image (not a FIT image)\n"); + printf("fsl-mc: ERR: Bad firmware image (not a FIT image)\n"); return -EINVAL; } if (!fit_check_format(fit_hdr)) { - printf("fsl-mc: ERROR: Bad firmware image (bad FIT header)\n"); + printf("fsl-mc: ERR: Bad firmware image (bad FIT header)\n"); return -EINVAL; } node_offset = fit_image_get_node(fit_hdr, uname); if (node_offset < 0) { - printf("fsl-mc: ERROR: Bad firmware image (missing subimage)\n"); + printf("fsl-mc: ERR: Bad firmware image (missing subimage)\n"); return -ENOENT; } /* Verify MC firmware image */ if (!(fit_image_verify(fit_hdr, node_offset))) { - printf("fsl-mc: ERROR: Bad firmware image (bad CRC)\n"); + printf("fsl-mc: ERR: Bad firmware image (bad CRC)\n"); return -EINVAL; } @@ -218,7 +223,7 @@ static int mc_fixup_dpc(u64 dpc_addr) return 0; } -static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size) +static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr) { u64 mc_dpc_offset; #ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR @@ -245,11 +250,7 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size) /* * Get address and size of the DPC blob stored in flash: */ -#ifdef CONFIG_SYS_LS_MC_DPC_IN_NOR - dpc_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPC_ADDR; -#else -#error "No CONFIG_SYS_LS_MC_DPC_IN_xxx defined" -#endif + dpc_fdt_hdr = (void *)mc_dpc_addr; error = fdt_check_header(dpc_fdt_hdr); if (error != 0) { @@ -279,7 +280,7 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size) return 0; } -static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size) +static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) { u64 mc_dpl_offset; #ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR @@ -306,11 +307,7 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size) /* * Get address and size of the DPL blob stored in flash: */ -#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR - dpl_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR; -#else -#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined" -#endif + dpl_fdt_hdr = (void *)mc_dpl_addr; error = fdt_check_header(dpl_fdt_hdr); if (error != 0) { @@ -357,23 +354,33 @@ static unsigned long get_mc_boot_timeout_ms(void) return timeout_ms; } -#ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR -static int load_mc_aiop_img(u64 mc_ram_addr, size_t mc_ram_size) +#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +static int load_mc_aiop_img(u64 aiop_fw_addr) { + u64 mc_ram_addr = mc_get_dram_addr(); +#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR void *aiop_img; +#endif /* * Load the MC AIOP image in the MC private DRAM block: */ - aiop_img = (void *)CONFIG_SYS_LS_MC_AIOP_IMG_ADDR; +#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR + printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr + + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); +#else + aiop_img = (void *)aiop_fw_addr; mc_copy_image("MC AIOP image", (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH, mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); +#endif + mc_aiop_applied = 0; return 0; } #endif + static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr) { u32 reg_gsr; @@ -420,12 +427,12 @@ static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr) return 0; } -int mc_init(void) +int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) { int error = 0; int portal_id = 0; struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; - u64 mc_ram_addr; + u64 mc_ram_addr = mc_get_dram_addr(); u32 reg_gsr; u32 reg_mcfbalr; #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR @@ -437,17 +444,6 @@ int mc_init(void) u8 mc_ram_num_256mb_blocks; size_t mc_ram_size = mc_get_dram_block_size(); - /* - * The MC private DRAM block was already carved at the end of DRAM - * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: - */ - if (gd->bd->bi_dram[1].start) { - mc_ram_addr = - gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; - } else { - mc_ram_addr = - gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; - } error = calculate_mc_private_ram_params(mc_ram_addr, mc_ram_size, @@ -474,7 +470,8 @@ int mc_init(void) #ifdef CONFIG_SYS_LS_MC_FW_IN_DDR printf("MC firmware is preloaded to %#llx\n", mc_ram_addr); #else - error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size); + error = parse_mc_firmware_fit_image(mc_fw_addr, &raw_image_addr, + &raw_image_size); if (error != 0) goto out; /* @@ -485,20 +482,10 @@ int mc_init(void) #endif dump_ram_words("firmware", (void *)mc_ram_addr); - error = load_mc_dpc(mc_ram_addr, mc_ram_size); + error = load_mc_dpc(mc_ram_addr, mc_ram_size, mc_dpc_addr); if (error != 0) goto out; - error = load_mc_dpl(mc_ram_addr, mc_ram_size); - if (error != 0) - goto out; - -#ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR - error = load_mc_aiop_img(mc_ram_addr, mc_ram_size); - if (error != 0) - goto out; -#endif - debug("mc_ccsr_regs %p\n", mc_ccsr_regs); dump_mc_ccsr_regs(mc_ccsr_regs); @@ -537,54 +524,57 @@ int mc_init(void) * Initialize the global default MC portal * And check that the MC firmware is responding portal commands: */ - dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io)); - if (!dflt_mc_io) { + root_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io)); + if (!root_mc_io) { printf(" No memory: malloc() failed\n"); return -ENOMEM; } - dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id); + root_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id); debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n", - portal_id, dflt_mc_io->mmio_regs); + portal_id, root_mc_io->mmio_regs); - error = mc_get_version(dflt_mc_io, MC_CMD_NO_FLAGS, &mc_ver_info); + error = mc_get_version(root_mc_io, MC_CMD_NO_FLAGS, &mc_ver_info); if (error != 0) { printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n", error); goto out; } - if (MC_VER_MAJOR != mc_ver_info.major) { - printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n", - mc_ver_info.major, MC_VER_MAJOR); - printf("fsl-mc: Update the Management Complex firmware\n"); - - error = -ENODEV; - goto out; - } - - if (MC_VER_MINOR != mc_ver_info.minor) - printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n", - mc_ver_info.minor, MC_VER_MINOR); - printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n", mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision, reg_gsr & GSR_FS_MASK); +out: + if (error != 0) + mc_boot_status = error; + else + mc_boot_status = 0; + + return error; +} + +int mc_apply_dpl(u64 mc_dpl_addr) +{ + struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; + int error = 0; + u32 reg_gsr; + u64 mc_ram_addr = mc_get_dram_addr(); + size_t mc_ram_size = mc_get_dram_block_size(); + + error = load_mc_dpl(mc_ram_addr, mc_ram_size, mc_dpl_addr); + if (error != 0) + return error; + /* * Tell the MC to deploy the DPL: */ out_le32(&mc_ccsr_regs->reg_gsr, 0x0); printf("fsl-mc: Deploying data path layout ... "); error = wait_for_mc(false, ®_gsr); - if (error != 0) - goto out; -out: - if (error != 0) - mc_boot_status = error; - else - mc_boot_status = 0; + if (!error) + mc_dpl_applied = 0; return error; } @@ -594,6 +584,40 @@ int get_mc_boot_status(void) return mc_boot_status; } +#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +int get_aiop_apply_status(void) +{ + return mc_aiop_applied; +} +#endif + +int get_dpl_apply_status(void) +{ + return mc_dpl_applied; +} + +/** + * Return the MC address of private DRAM block. + */ +u64 mc_get_dram_addr(void) +{ + u64 mc_ram_addr; + + /* + * The MC private DRAM block was already carved at the end of DRAM + * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: + */ + if (gd->bd->bi_dram[1].start) { + mc_ram_addr = + gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; + } else { + mc_ram_addr = + gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; + } + + return mc_ram_addr; +} + /** * Return the actual size of the MC private DRAM block. */ @@ -620,36 +644,57 @@ unsigned long mc_get_dram_block_size(void) return dram_block_size; } -int dpio_init(struct dprc_obj_desc obj_desc) +int fsl_mc_ldpaa_init(bd_t *bis) +{ + int i; + + for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) + if ((wriop_is_enabled_dpmac(i) == 1) && + (wriop_get_phy_address(i) != -1)) + ldpaa_eth_init(i, wriop_get_enet_if(i)); + return 0; +} + +static int dpio_init(void) { struct qbman_swp_desc p_des; struct dpio_attr attr; + struct dpio_cfg dpio_cfg; int err = 0; dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj)); if (!dflt_dpio) { - printf(" No memory: malloc() failed\n"); - return -ENOMEM; + printf("No memory: malloc() failed\n"); + err = -ENOMEM; + goto err_malloc; } - dflt_dpio->dpio_id = obj_desc.id; + dpio_cfg.channel_mode = DPIO_LOCAL_CHANNEL; + dpio_cfg.num_priorities = 8; - err = dpio_open(dflt_mc_io, MC_CMD_NO_FLAGS, obj_desc.id, - &dflt_dpio_handle); - if (err) { - printf("dpio_open() failed\n"); - goto err_open; + err = dpio_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpio_cfg, + &dflt_dpio->dpio_handle); + if (err < 0) { + printf("dpio_create() failed: %d\n", err); + err = -ENODEV; + goto err_create; } + memset(&attr, 0, sizeof(struct dpio_attr)); err = dpio_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS, - dflt_dpio_handle, &attr); - if (err) { - printf("dpio_get_attributes() failed %d\n", err); + dflt_dpio->dpio_handle, &attr); + if (err < 0) { + printf("dpio_get_attributes() failed: %d\n", err); goto err_get_attr; } - err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio_handle); - if (err) { + dflt_dpio->dpio_id = attr.id; +#ifdef DEBUG + printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id); +#endif + + err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); + if (err < 0) { printf("dpio_enable() failed %d\n", err); goto err_get_enable; } @@ -672,176 +717,512 @@ int dpio_init(struct dprc_obj_desc obj_desc) return 0; err_get_swp_init: + dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); err_get_enable: - dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio_handle); -err_get_attr: - dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio_handle); -err_open: free(dflt_dpio); +err_get_attr: + dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); + dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); +err_create: +err_malloc: return err; } -int dpbp_init(struct dprc_obj_desc obj_desc) +static int dpio_exit(void) { - dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj)); - if (!dflt_dpbp) { + int err; + + err = dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); + if (err < 0) { + printf("dpio_disable() failed: %d\n", err); + goto err; + } + + err = dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); + if (err < 0) { + printf("dpio_destroy() failed: %d\n", err); + goto err; + } + +#ifdef DEBUG + printf("Exit: DPIO id=0x%d\n", dflt_dpio->dpio_id); +#endif + + if (dflt_dpio) + free(dflt_dpio); + + return 0; +err: + return err; +} + +static int dprc_init(void) +{ + int err, child_portal_id, container_id; + struct dprc_cfg cfg; + uint64_t mc_portal_offset; + + /* Open root container */ + err = dprc_get_container_id(root_mc_io, MC_CMD_NO_FLAGS, &container_id); + if (err < 0) { + printf("dprc_get_container_id(): Root failed: %d\n", err); + goto err_root_container_id; + } + +#ifdef DEBUG + printf("Root container id = %d\n", container_id); +#endif + err = dprc_open(root_mc_io, MC_CMD_NO_FLAGS, container_id, + &root_dprc_handle); + if (err < 0) { + printf("dprc_open(): Root Container failed: %d\n", err); + goto err_root_open; + } + + if (!root_dprc_handle) { + printf("dprc_open(): Root Container Handle is not valid\n"); + goto err_root_open; + } + + cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED | + DPRC_CFG_OPT_OBJ_CREATE_ALLOWED | + DPRC_CFG_OPT_ALLOC_ALLOWED; + cfg.icid = DPRC_GET_ICID_FROM_POOL; + cfg.portal_id = 250; + err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS, + root_dprc_handle, + &cfg, + &child_dprc_id, + &mc_portal_offset); + if (err < 0) { + printf("dprc_create_container() failed: %d\n", err); + goto err_create; + } + + dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io)); + if (!dflt_mc_io) { + err = -ENOMEM; printf(" No memory: malloc() failed\n"); - return -ENOMEM; + goto err_malloc; + } + + child_portal_id = MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset); + dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(child_portal_id); +#ifdef DEBUG + printf("MC portal of child DPRC container: %d, physical addr %p)\n", + child_dprc_id, dflt_mc_io->mmio_regs); +#endif + + err = dprc_open(dflt_mc_io, MC_CMD_NO_FLAGS, child_dprc_id, + &dflt_dprc_handle); + if (err < 0) { + printf("dprc_open(): Child container failed: %d\n", err); + goto err_child_open; + } + + if (!dflt_dprc_handle) { + printf("dprc_open(): Child container Handle is not valid\n"); + goto err_child_open; } - dflt_dpbp->dpbp_attr.id = obj_desc.id; return 0; +err_child_open: + free(dflt_mc_io); +err_malloc: + dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS, + root_dprc_handle, child_dprc_id); +err_create: + dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle); +err_root_open: +err_root_container_id: + return err; } -int dprc_init_container_obj(struct dprc_obj_desc obj_desc, uint16_t dprc_handle) +static int dprc_exit(void) { - int error = 0, state = 0; - struct dprc_endpoint dpni_endpoint, dpmac_endpoint; - if (!strcmp(obj_desc.type, "dpbp")) { - if (!dflt_dpbp) { - error = dpbp_init(obj_desc); - if (error < 0) - printf("dpbp_init failed\n"); - } - } else if (!strcmp(obj_desc.type, "dpio")) { - if (!dflt_dpio) { - error = dpio_init(obj_desc); - if (error < 0) - printf("dpio_init failed\n"); - } - } else if (!strcmp(obj_desc.type, "dpni")) { - strcpy(dpni_endpoint.type, obj_desc.type); - dpni_endpoint.id = obj_desc.id; - error = dprc_get_connection(dflt_mc_io, MC_CMD_NO_FLAGS, - dprc_handle, &dpni_endpoint, - &dpmac_endpoint, &state); - if (!strcmp(dpmac_endpoint.type, "dpmac")) - error = ldpaa_eth_init(obj_desc); - if (error < 0) - printf("ldpaa_eth_init failed\n"); + int err; + + err = dprc_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dprc_handle); + if (err < 0) { + printf("dprc_close(): Child failed: %d\n", err); + goto err; } - return error; + err = dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS, + root_dprc_handle, child_dprc_id); + if (err < 0) { + printf("dprc_destroy_container() failed: %d\n", err); + goto err; + } + + err = dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle); + if (err < 0) { + printf("dprc_close(): Root failed: %d\n", err); + goto err; + } + + if (dflt_mc_io) + free(dflt_mc_io); + + if (root_mc_io) + free(root_mc_io); + + return 0; + +err: + return err; } -int dprc_scan_container_obj(uint16_t dprc_handle, char *obj_type, int i) +static int dpbp_init(void) { - int error = 0; - struct dprc_obj_desc obj_desc; + int err; + struct dpbp_attr dpbp_attr; + struct dpbp_cfg dpbp_cfg; - memset((void *)&obj_desc, 0x00, sizeof(struct dprc_obj_desc)); + dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj)); + if (!dflt_dpbp) { + printf("No memory: malloc() failed\n"); + err = -ENOMEM; + goto err_malloc; + } - error = dprc_get_obj(dflt_mc_io, MC_CMD_NO_FLAGS, dprc_handle, - i, &obj_desc); - if (error < 0) { - printf("dprc_get_obj(i=%d) failed: %d\n", - i, error); - return error; + dpbp_cfg.options = 512; + + err = dpbp_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpbp_cfg, + &dflt_dpbp->dpbp_handle); + + if (err < 0) { + err = -ENODEV; + printf("dpbp_create() failed: %d\n", err); + goto err_create; } - if (!strcmp(obj_desc.type, obj_type)) { - debug("Discovered object: type %s, id %d, req %s\n", - obj_desc.type, obj_desc.id, obj_type); + memset(&dpbp_attr, 0, sizeof(struct dpbp_attr)); + err = dpbp_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpbp->dpbp_handle, + &dpbp_attr); + if (err < 0) { + printf("dpbp_get_attributes() failed: %d\n", err); + goto err_get_attr; + } - error = dprc_init_container_obj(obj_desc, dprc_handle); - if (error < 0) { - printf("dprc_init_container_obj(i=%d) failed: %d\n", - i, error); - return error; - } + dflt_dpbp->dpbp_attr.id = dpbp_attr.id; +#ifdef DEBUG + printf("Init: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id); +#endif + + err = dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); + if (err < 0) { + printf("dpbp_close() failed: %d\n", err); + goto err_close; } - return error; + return 0; + +err_close: + free(dflt_dpbp); +err_get_attr: + dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); + dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); +err_create: +err_malloc: + return err; } -int fsl_mc_ldpaa_init(bd_t *bis) +static int dpbp_exit(void) { - int i, error = 0; - int dprc_opened = 0, container_id; - int num_child_objects = 0; + int err; - error = mc_init(); - if (error < 0) - goto error; + err = dpbp_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_attr.id, + &dflt_dpbp->dpbp_handle); + if (err < 0) { + printf("dpbp_open() failed: %d\n", err); + goto err; + } - error = dprc_get_container_id(dflt_mc_io, MC_CMD_NO_FLAGS, - &container_id); - if (error < 0) { - printf("dprc_get_container_id() failed: %d\n", error); - goto error; + err = dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpbp->dpbp_handle); + if (err < 0) { + printf("dpbp_destroy() failed: %d\n", err); + goto err; } - debug("fsl-mc: Container id=0x%x\n", container_id); +#ifdef DEBUG + printf("Exit: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id); +#endif + + if (dflt_dpbp) + free(dflt_dpbp); + return 0; + +err: + return err; +} - error = dprc_open(dflt_mc_io, MC_CMD_NO_FLAGS, container_id, - &dflt_dprc_handle); - if (error < 0) { - printf("dprc_open() failed: %d\n", error); - goto error; +static int dpni_init(void) +{ + int err; + struct dpni_attr dpni_attr; + struct dpni_cfg dpni_cfg; + + dflt_dpni = (struct fsl_dpni_obj *)malloc(sizeof(struct fsl_dpni_obj)); + if (!dflt_dpni) { + printf("No memory: malloc() failed\n"); + err = -ENOMEM; + goto err_malloc; } - dprc_opened = true; - error = dprc_get_obj_count(dflt_mc_io, - MC_CMD_NO_FLAGS, dflt_dprc_handle, - &num_child_objects); - if (error < 0) { - printf("dprc_get_obj_count() failed: %d\n", error); - goto error; + memset(&dpni_cfg, 0, sizeof(dpni_cfg)); + dpni_cfg.adv.options = DPNI_OPT_UNICAST_FILTER | + DPNI_OPT_MULTICAST_FILTER; + + err = dpni_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpni_cfg, + &dflt_dpni->dpni_handle); + + if (err < 0) { + err = -ENODEV; + printf("dpni_create() failed: %d\n", err); + goto err_create; } - debug("Total child in container %d = %d\n", container_id, - num_child_objects); - if (num_child_objects != 0) { - /* - * Discover objects currently in the DPRC container in the MC: - */ - for (i = 0; i < num_child_objects; i++) - error = dprc_scan_container_obj(dflt_dprc_handle, - "dpbp", i); + memset(&dpni_attr, 0, sizeof(struct dpni_attr)); + err = dpni_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + &dpni_attr); + if (err < 0) { + printf("dpni_get_attributes() failed: %d\n", err); + goto err_get_attr; + } - for (i = 0; i < num_child_objects; i++) - error = dprc_scan_container_obj(dflt_dprc_handle, - "dpio", i); + dflt_dpni->dpni_id = dpni_attr.id; +#ifdef DEBUG + printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id); +#endif - for (i = 0; i < num_child_objects; i++) - error = dprc_scan_container_obj(dflt_dprc_handle, - "dpni", i); + err = dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); + if (err < 0) { + printf("dpni_close() failed: %d\n", err); + goto err_close; } -error: - if (dprc_opened) - dprc_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dprc_handle); - return error; + return 0; + +err_close: + free(dflt_dpni); +err_get_attr: + dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); + dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); +err_create: +err_malloc: + return err; } -void fsl_mc_ldpaa_exit(bd_t *bis) +static int dpni_exit(void) { int err; - if (get_mc_boot_status() == 0) { - err = dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, - dflt_dpio_handle); - if (err < 0) { - printf("dpio_disable() failed: %d\n", err); - return; - } - err = dpio_reset(dflt_mc_io, MC_CMD_NO_FLAGS, - dflt_dpio_handle); - if (err < 0) { - printf("dpio_reset() failed: %d\n", err); - return; - } - err = dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, - dflt_dpio_handle); - if (err < 0) { - printf("dpio_close() failed: %d\n", err); - return; - } + err = dpni_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_id, + &dflt_dpni->dpni_handle); + if (err < 0) { + printf("dpni_open() failed: %d\n", err); + goto err; + } - free(dflt_dpio); - free(dflt_dpbp); + err = dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle); + if (err < 0) { + printf("dpni_destroy() failed: %d\n", err); + goto err; } - if (dflt_mc_io) - free(dflt_mc_io); +#ifdef DEBUG + printf("Exit: DPNI id=0x%d\n", dflt_dpni->dpni_id); +#endif + + if (dflt_dpni) + free(dflt_dpni); + return 0; + +err: + return err; +} + +static int mc_init_object(void) +{ + int err = 0; + + err = dprc_init(); + if (err < 0) { + printf("dprc_init() failed: %d\n", err); + goto err; + } + + err = dpbp_init(); + if (err < 0) { + printf("dpbp_init() failed: %d\n", err); + goto err; + } + + err = dpio_init(); + if (err < 0) { + printf("dpio_init() failed: %d\n", err); + goto err; + } + + err = dpni_init(); + if (err < 0) { + printf("dpni_init() failed: %d\n", err); + goto err; + } + + return 0; +err: + return err; +} + +int fsl_mc_ldpaa_exit(bd_t *bd) +{ + int err = 0; + + if (bd && get_mc_boot_status() == -1) + return 0; + + if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) { + printf("ERROR: fsl-mc: DPL is not applied\n"); + err = -ENODEV; + return err; + } + + if (bd && !get_mc_boot_status() && !get_dpl_apply_status()) + return err; + + err = dpbp_exit(); + if (err < 0) { + printf("dpni_exit() failed: %d\n", err); + goto err; + } + + err = dpio_exit(); + if (err < 0) { + printf("dpio_exit() failed: %d\n", err); + goto err; + } + + err = dpni_exit(); + if (err < 0) { + printf("dpni_exit() failed: %d\n", err); + goto err; + } + + err = dprc_exit(); + if (err < 0) { + printf("dprc_exit() failed: %d\n", err); + goto err; + } + + return 0; +err: + return err; +} + +static int do_fsl_mc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int err = 0; + if (argc < 3) + goto usage; + + switch (argv[1][0]) { + case 's': { + char sub_cmd; + u64 mc_fw_addr, mc_dpc_addr; +#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET + u64 aiop_fw_addr; +#endif + + sub_cmd = argv[2][0]; + switch (sub_cmd) { + case 'm': + if (argc < 5) + goto usage; + + if (get_mc_boot_status() == 0) { + printf("fsl-mc: MC is already booted"); + printf("\n"); + return err; + } + mc_fw_addr = simple_strtoull(argv[3], NULL, 16); + mc_dpc_addr = simple_strtoull(argv[4], NULL, + 16); + + if (!mc_init(mc_fw_addr, mc_dpc_addr)) + err = mc_init_object(); + break; + +#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET + case 'a': + if (argc < 4) + goto usage; + if (get_aiop_apply_status() == 0) { + printf("fsl-mc: AIOP FW is already"); + printf(" applied\n"); + return err; + } + + aiop_fw_addr = simple_strtoull(argv[3], NULL, + 16); + + err = load_mc_aiop_img(aiop_fw_addr); + if (!err) + printf("fsl-mc: AIOP FW applied\n"); + break; +#endif + default: + printf("Invalid option: %s\n", argv[2]); + goto usage; + + break; + } + } + break; + + case 'a': { + u64 mc_dpl_addr; + + if (argc < 4) + goto usage; + + if (get_dpl_apply_status() == 0) { + printf("fsl-mc: DPL already applied\n"); + return err; + } + + mc_dpl_addr = simple_strtoull(argv[3], NULL, + 16); + + if (get_mc_boot_status() != 0) { + printf("fsl-mc: Deploying data path layout .."); + printf("ERROR (MC is not booted)\n"); + return -ENODEV; + } + + if (!fsl_mc_ldpaa_exit(NULL)) + err = mc_apply_dpl(mc_dpl_addr); + break; + } + default: + printf("Invalid option: %s\n", argv[1]); + goto usage; + break; + } + return err; + usage: + return CMD_RET_USAGE; } + +U_BOOT_CMD( + fsl_mc, CONFIG_SYS_MAXARGS, 1, do_fsl_mc, + "DPAA2 command to manage Management Complex (MC)", + "start mc [FW_addr] [DPC_addr] - Start Management Complex\n" + "fsl_mc apply DPL [DPL_addr] - Apply DPL file\n" + "fsl_mc start aiop [FW_addr] - Start AIOP\n" +); diff --git a/drivers/net/fsl-mc/mc_sys.c b/drivers/net/fsl-mc/mc_sys.c index 2136670..71e1456 100644 --- a/drivers/net/fsl-mc/mc_sys.c +++ b/drivers/net/fsl-mc/mc_sys.c @@ -32,7 +32,7 @@ int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd) { enum mc_cmd_status status; - int timeout = 6000; + int timeout = 12000; mc_write_command(mc_io->mmio_regs, cmd); diff --git a/drivers/net/greth.c b/drivers/net/greth.c index 0624eb8..088cb22 100644 --- a/drivers/net/greth.c +++ b/drivers/net/greth.c @@ -245,7 +245,7 @@ int greth_init_phy(greth_priv * dev, bd_t * bis) debug("GRETH PHY ADDRESS: %d\n", phyaddr); /* X msecs to ticks */ - timeout = usec2ticks(GRETH_PHY_TIMEOUT_MS * 1000); + timeout = GRETH_PHY_TIMEOUT_MS * 1000; /* Get system timer0 current value * Total timeout is 5s diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile index c37633f..74c4916 100644 --- a/drivers/net/ldpaa_eth/Makefile +++ b/drivers/net/ldpaa_eth/Makefile @@ -6,4 +6,5 @@ obj-y += ldpaa_wriop.o obj-y += ldpaa_eth.o -obj-$(CONFIG_LS2085A) += ls2085a.o +obj-$(CONFIG_LS2080A) += ls2080a.o +obj-$(CONFIG_LS2085A) += ls2080a.o diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 99acb7a..69530b1 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -12,6 +12,7 @@ #include <hwconfig.h> #include <phy.h> #include <linux/compat.h> +#include <fsl-mc/fsl_dpmac.h> #include "ldpaa_eth.h" @@ -23,6 +24,84 @@ static int init_phy(struct eth_device *dev) return 0; } +#ifdef DEBUG +static void ldpaa_eth_get_dpni_counter(void) +{ + int err = 0; + u64 value; + + err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + DPNI_CNT_ING_FRAME, + &value); + if (err < 0) { + printf("dpni_get_counter: DPNI_CNT_ING_FRAME failed\n"); + return; + } + printf("DPNI_CNT_ING_FRAME=%lld\n", value); + + err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + DPNI_CNT_ING_BYTE, + &value); + if (err < 0) { + printf("dpni_get_counter: DPNI_CNT_ING_BYTE failed\n"); + return; + } + printf("DPNI_CNT_ING_BYTE=%lld\n", value); + + err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + DPNI_CNT_ING_FRAME_DROP , + &value); + if (err < 0) { + printf("dpni_get_counter: DPNI_CNT_ING_FRAME_DROP failed\n"); + return; + } + printf("DPNI_CNT_ING_FRAME_DROP =%lld\n", value); + + err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + DPNI_CNT_ING_FRAME_DISCARD, + &value); + if (err < 0) { + printf("dpni_get_counter: DPNI_CNT_ING_FRAME_DISCARD failed\n"); + return; + } + printf("DPNI_CNT_ING_FRAME_DISCARD=%lld\n", value); + + err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + DPNI_CNT_EGR_FRAME, + &value); + if (err < 0) { + printf("dpni_get_counter: DPNI_CNT_EGR_FRAME failed\n"); + return; + } + printf("DPNI_CNT_EGR_FRAME=%lld\n", value); + + err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + DPNI_CNT_EGR_BYTE , + &value); + if (err < 0) { + printf("dpni_get_counter: DPNI_CNT_EGR_BYTE failed\n"); + return; + } + printf("DPNI_CNT_EGR_BYTE =%lld\n", value); + + err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + DPNI_CNT_EGR_FRAME_DISCARD , + &value); + if (err < 0) { + printf("dpni_get_counter: DPNI_CNT_EGR_FRAME_DISCARD failed\n"); + return; + } + printf("DPNI_CNT_EGR_FRAME_DISCARD =%lld\n", value); +} +#endif + static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv, const struct dpaa_fd *fd) { @@ -46,7 +125,7 @@ static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv, /* Read the frame annotation status word and check for errors */ fas = (struct ldpaa_fas *) ((uint8_t *)(fd_addr) + - priv->buf_layout.private_data_size); + dflt_dpni->buf_layout.private_data_size); status = le32_to_cpu(fas->status); if (status & LDPAA_ETH_RX_ERR_MASK) { printf("Rx frame error(s): 0x%08x\n", @@ -220,11 +299,34 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) { struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; struct dpni_queue_attr rx_queue_attr; + struct dpmac_link_state dpmac_link_state = { 0 }; +#ifdef DEBUG + struct dpni_link_state link_state; +#endif int err; if (net_dev->state == ETH_STATE_ACTIVE) return 0; + if (get_mc_boot_status() != 0) { + printf("ERROR (MC is not booted)\n"); + return -ENODEV; + } + + if (get_dpl_apply_status() == 0) { + printf("ERROR (DPL is deployed. No device available)\n"); + return -ENODEV; + } + /* DPMAC initialization */ + err = ldpaa_dpmac_setup(priv); + if (err < 0) + goto err_dpmac_setup; + + /* DPMAC binding DPNI */ + err = ldpaa_dpmac_bind(priv); + if (err) + goto err_dpamc_bind; + /* DPNI initialization */ err = ldpaa_dpni_setup(priv); if (err < 0) @@ -237,10 +339,10 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) /* DPNI binding DPBP */ err = ldpaa_dpni_bind(priv); if (err) - goto err_bind; + goto err_dpni_bind; err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpni_handle, net_dev->enetaddr); + dflt_dpni->dpni_handle, net_dev->enetaddr); if (err) { printf("dpni_add_mac_addr() failed\n"); return err; @@ -259,15 +361,38 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) priv->phydev->duplex = DUPLEX_FULL; #endif - err = dpni_enable(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle); + err = dpni_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); if (err < 0) { printf("dpni_enable() failed\n"); return err; } + dpmac_link_state.rate = SPEED_1000; + dpmac_link_state.options = DPMAC_LINK_OPT_AUTONEG; + dpmac_link_state.up = 1; + err = dpmac_set_link_state(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, &dpmac_link_state); + if (err < 0) { + printf("dpmac_set_link_state() failed\n"); + return err; + } + +#ifdef DEBUG + err = dpni_get_link_state(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, &link_state); + if (err < 0) { + printf("dpni_get_link_state() failed\n"); + return err; + } + + printf("link status: %d - ", link_state.up); + link_state.up == 0 ? printf("down\n") : + link_state.up == 1 ? printf("up\n") : printf("error state\n"); +#endif + /* TODO: support multiple Rx flows */ - err = dpni_get_rx_flow(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle, - 0, 0, &rx_queue_attr); + err = dpni_get_rx_flow(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, 0, 0, &rx_queue_attr); if (err) { printf("dpni_get_rx_flow() failed\n"); goto err_rx_flow; @@ -275,7 +400,7 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) priv->rx_dflt_fqid = rx_queue_attr.fqid; - err = dpni_get_qdid(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle, + err = dpni_get_qdid(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, &priv->tx_qdid); if (err) { printf("dpni_get_qdid() failed\n"); @@ -289,12 +414,14 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) err_qdid: err_rx_flow: - dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle); -err_bind: + dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); +err_dpni_bind: ldpaa_dpbp_free(); err_dpbp_setup: - dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle); +err_dpamc_bind: + dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); err_dpni_setup: +err_dpmac_setup: return err; } @@ -306,8 +433,22 @@ static void ldpaa_eth_stop(struct eth_device *net_dev) if ((net_dev->state == ETH_STATE_PASSIVE) || (net_dev->state == ETH_STATE_INIT)) return; + +#ifdef DEBUG + ldpaa_eth_get_dpni_counter(); +#endif + + err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dprc_handle, &dpmac_endpoint); + if (err < 0) + printf("dprc_disconnect() failed dpmac_endpoint\n"); + + err = dpmac_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle); + if (err < 0) + printf("dpmac_destroy() failed\n"); + /* Stop Tx and Rx traffic */ - err = dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle); + err = dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); if (err < 0) printf("dpni_disable() failed\n"); @@ -316,8 +457,8 @@ static void ldpaa_eth_stop(struct eth_device *net_dev) #endif ldpaa_dpbp_free(); - dpni_reset(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle); - dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle); + dpni_reset(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); + dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); } static void ldpaa_dpbp_drain_cnt(int count) @@ -359,7 +500,7 @@ static int ldpaa_bp_add_7(uint16_t bpid) struct qbman_release_desc rd; for (i = 0; i < 7; i++) { - addr = memalign(L1_CACHE_BYTES, LDPAA_ETH_RX_BUFFER_SIZE); + addr = memalign(LDPAA_ETH_BUF_ALIGN, LDPAA_ETH_RX_BUFFER_SIZE); if (!addr) { printf("addr allocation failed\n"); goto err_alloc; @@ -458,54 +599,125 @@ static void ldpaa_dpbp_free(void) dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); } +static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv) +{ + int err = 0; + struct dpmac_cfg dpmac_cfg; + + dpmac_cfg.mac_id = priv->dpmac_id; + err = dpmac_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpmac_cfg, + &priv->dpmac_handle); + if (err) + printf("dpmac_create() failed\n"); + return err; +} + +static int ldpaa_dpmac_bind(struct ldpaa_eth_priv *priv) +{ + int err = 0; + struct dprc_connection_cfg dprc_connection_cfg = { + /* If both rates are zero the connection */ + /* will be configured in "best effort" mode. */ + .committed_rate = 0, + .max_rate = 0 + }; + +#ifdef DEBUG + struct dprc_endpoint dbg_endpoint; + int state = 0; +#endif + + memset(&dpmac_endpoint, 0, sizeof(struct dprc_endpoint)); + sprintf(dpmac_endpoint.type, "dpmac"); + dpmac_endpoint.id = priv->dpmac_id; + + memset(&dpni_endpoint, 0, sizeof(struct dprc_endpoint)); + sprintf(dpni_endpoint.type, "dpni"); + dpni_endpoint.id = dflt_dpni->dpni_id; + + err = dprc_connect(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dprc_handle, + &dpmac_endpoint, + &dpni_endpoint, + &dprc_connection_cfg); + if (err) + printf("dprc_connect() failed\n"); + +#ifdef DEBUG + err = dprc_get_connection(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dprc_handle, &dpni_endpoint, + &dbg_endpoint, &state); + printf("%s, DPMAC Type= %s\n", __func__, dbg_endpoint.type); + printf("%s, DPMAC ID= %d\n", __func__, dbg_endpoint.id); + printf("%s, DPMAC State= %d\n", __func__, state); + + memset(&dbg_endpoint, 0, sizeof(struct dprc_endpoint)); + err = dprc_get_connection(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dprc_handle, &dpmac_endpoint, + &dbg_endpoint, &state); + printf("%s, DPNI Type= %s\n", __func__, dbg_endpoint.type); + printf("%s, DPNI ID= %d\n", __func__, dbg_endpoint.id); + printf("%s, DPNI State= %d\n", __func__, state); +#endif + return err; +} + static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv) { int err; /* and get a handle for the DPNI this interface is associate with */ - err = dpni_open(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_id, - &priv->dpni_handle); + err = dpni_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_id, + &dflt_dpni->dpni_handle); if (err) { printf("dpni_open() failed\n"); goto err_open; } err = dpni_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpni_handle, &priv->dpni_attrs); + dflt_dpni->dpni_handle, + &dflt_dpni->dpni_attrs); if (err) { printf("dpni_get_attributes() failed (err=%d)\n", err); goto err_get_attr; } /* Configure our buffers' layout */ - priv->buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT | + dflt_dpni->buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT | DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | - DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE; - priv->buf_layout.pass_parser_result = true; - priv->buf_layout.pass_frame_status = true; - priv->buf_layout.private_data_size = LDPAA_ETH_SWA_SIZE; + DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE | + DPNI_BUF_LAYOUT_OPT_DATA_ALIGN; + dflt_dpni->buf_layout.pass_parser_result = true; + dflt_dpni->buf_layout.pass_frame_status = true; + dflt_dpni->buf_layout.private_data_size = LDPAA_ETH_SWA_SIZE; + /* HW erratum mandates data alignment in multiples of 256 */ + dflt_dpni->buf_layout.data_align = LDPAA_ETH_BUF_ALIGN; /* ...rx, ... */ err = dpni_set_rx_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpni_handle, &priv->buf_layout); + dflt_dpni->dpni_handle, + &dflt_dpni->buf_layout); if (err) { printf("dpni_set_rx_buffer_layout() failed"); goto err_buf_layout; } /* ... tx, ... */ - priv->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PARSER_RESULT; + /* remove Rx-only options */ + dflt_dpni->buf_layout.options &= ~(DPNI_BUF_LAYOUT_OPT_DATA_ALIGN | + DPNI_BUF_LAYOUT_OPT_PARSER_RESULT); err = dpni_set_tx_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpni_handle, &priv->buf_layout); + dflt_dpni->dpni_handle, + &dflt_dpni->buf_layout); if (err) { printf("dpni_set_tx_buffer_layout() failed"); goto err_buf_layout; } /* ... tx-confirm. */ - priv->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE; + dflt_dpni->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE; err = dpni_set_tx_conf_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpni_handle, - &priv->buf_layout); + dflt_dpni->dpni_handle, + &dflt_dpni->buf_layout); if (err) { printf("dpni_set_tx_conf_buffer_layout() failed"); goto err_buf_layout; @@ -515,7 +727,8 @@ static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv) * required tx data offset. */ err = dpni_get_tx_data_offset(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpni_handle, &priv->tx_data_offset); + dflt_dpni->dpni_handle, + &priv->tx_data_offset); if (err) { printf("dpni_get_tx_data_offset() failed\n"); goto err_data_offset; @@ -533,7 +746,7 @@ static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv) err_data_offset: err_buf_layout: err_get_attr: - dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle); + dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); err_open: return err; } @@ -547,8 +760,8 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) pools_params.num_dpbp = 1; pools_params.pools[0].dpbp_id = (uint16_t)dflt_dpbp->dpbp_attr.id; pools_params.pools[0].buffer_size = LDPAA_ETH_RX_BUFFER_SIZE; - err = dpni_set_pools(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle, - &pools_params); + err = dpni_set_pools(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, &pools_params); if (err) { printf("dpni_set_pools() failed\n"); return err; @@ -560,8 +773,9 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) dflt_tx_flow.options = DPNI_TX_FLOW_OPT_ONLY_TX_ERROR; dflt_tx_flow.conf_err_cfg.use_default_queue = 0; dflt_tx_flow.conf_err_cfg.errors_only = 1; - err = dpni_set_tx_flow(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle, - &priv->tx_flow_id, &dflt_tx_flow); + err = dpni_set_tx_flow(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, &priv->tx_flow_id, + &dflt_tx_flow); if (err) { printf("dpni_set_tx_flow() failed\n"); return err; @@ -570,12 +784,14 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) return 0; } -static int ldpaa_eth_netdev_init(struct eth_device *net_dev) +static int ldpaa_eth_netdev_init(struct eth_device *net_dev, + phy_interface_t enet_if) { int err; struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; - sprintf(net_dev->name, "DPNI%d", priv->dpni_id); + sprintf(net_dev->name, "DPMAC%d@%s", priv->dpmac_id, + phy_interface_strings[enet_if]); net_dev->iobase = 0; net_dev->init = ldpaa_eth_open; @@ -601,7 +817,7 @@ static int ldpaa_eth_netdev_init(struct eth_device *net_dev) return 0; } -int ldpaa_eth_init(struct dprc_obj_desc obj_desc) +int ldpaa_eth_init(int dpmac_id, phy_interface_t enet_if) { struct eth_device *net_dev = NULL; struct ldpaa_eth_priv *priv = NULL; @@ -626,9 +842,10 @@ int ldpaa_eth_init(struct dprc_obj_desc obj_desc) net_dev->priv = (void *)priv; priv->net_dev = (struct eth_device *)net_dev; - priv->dpni_id = obj_desc.id; + priv->dpmac_id = dpmac_id; + debug("%s dpmac_id=%d\n", __func__, dpmac_id); - err = ldpaa_eth_netdev_init(net_dev); + err = ldpaa_eth_netdev_init(net_dev, enet_if); if (err) goto err_netdev_init; diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h index b4ef700..af41b27 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.h +++ b/drivers/net/ldpaa_eth/ldpaa_eth.h @@ -28,10 +28,10 @@ enum ldpaa_eth_type { #define LDPAA_ETH_REFILL_THRESH (LDPAA_ETH_NUM_BUFS/2) #define LDPAA_ETH_RX_BUFFER_SIZE 2048 -/* Hardware requires alignment for ingress/egress buffer addresses - * and ingress buffer lengths. +/* Hardware requires alignment for buffer address and length: 256-byte + * for ingress, 64-byte for egress. Using 256 for both. */ -#define LDPAA_ETH_BUF_ALIGN 64 +#define LDPAA_ETH_BUF_ALIGN 256 /* So far we're only accomodating a skb backpointer in the frame's * software annotation, but the hardware options are either 0 or 64. @@ -117,13 +117,9 @@ struct ldpaa_fas { struct ldpaa_eth_priv { struct eth_device *net_dev; - int dpni_id; - uint16_t dpni_handle; - struct dpni_attr dpni_attrs; - /* Insofar as the MC is concerned, we're using one layout on all 3 types - * of buffers (Rx, Tx, Tx-Conf). - */ - struct dpni_buffer_layout buf_layout; + int dpmac_id; + uint16_t dpmac_handle; + uint16_t tx_data_offset; uint32_t rx_dflt_fqid; @@ -134,9 +130,14 @@ struct ldpaa_eth_priv { struct phy_device *phydev; }; +struct dprc_endpoint dpmac_endpoint; +struct dprc_endpoint dpni_endpoint; + extern struct fsl_mc_io *dflt_mc_io; extern struct fsl_dpbp_obj *dflt_dpbp; extern struct fsl_dpio_obj *dflt_dpio; +extern struct fsl_dpni_obj *dflt_dpni; +extern uint16_t dflt_dprc_handle; static void ldpaa_dpbp_drain_cnt(int count); static void ldpaa_dpbp_drain(void); @@ -145,4 +146,6 @@ static void ldpaa_dpbp_free(void); static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv); static int ldpaa_dpbp_setup(void); static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv); +static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv); +static int ldpaa_dpmac_bind(struct ldpaa_eth_priv *priv); #endif /* __LDPAA_H */ diff --git a/drivers/net/ldpaa_eth/ldpaa_wriop.c b/drivers/net/ldpaa_eth/ldpaa_wriop.c index 926057a..f7f26c2 100644 --- a/drivers/net/ldpaa_eth/ldpaa_wriop.c +++ b/drivers/net/ldpaa_eth/ldpaa_wriop.c @@ -23,17 +23,17 @@ __weak phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtc) void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl) { phy_interface_t enet_if; - int index = dpmac_id + sd * 8; - dpmac_info[index].enabled = 0; - dpmac_info[index].id = 0; - dpmac_info[index].enet_if = PHY_INTERFACE_MODE_NONE; + dpmac_info[dpmac_id].enabled = 0; + dpmac_info[dpmac_id].id = 0; + dpmac_info[dpmac_id].phy_addr = -1; + dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NONE; - enet_if = wriop_dpmac_enet_if(index, lane_prtcl); + enet_if = wriop_dpmac_enet_if(dpmac_id, lane_prtcl); if (enet_if != PHY_INTERFACE_MODE_NONE) { - dpmac_info[index].enabled = 1; - dpmac_info[index].id = index; - dpmac_info[index].enet_if = enet_if; + dpmac_info[dpmac_id].enabled = 1; + dpmac_info[dpmac_id].id = dpmac_id; + dpmac_info[dpmac_id].enet_if = enet_if; } } @@ -72,6 +72,17 @@ void wriop_enable_dpmac(int dpmac_id) wriop_dpmac_enable(dpmac_id); } +u8 wriop_is_enabled_dpmac(int dpmac_id) +{ + int i = wriop_dpmac_to_index(dpmac_id); + + if (i == -1) + return -1; + + return dpmac_info[i].enabled; +} + + void wriop_set_mdio(int dpmac_id, struct mii_dev *bus) { int i = wriop_dpmac_to_index(dpmac_id); diff --git a/drivers/net/ldpaa_eth/ls2085a.c b/drivers/net/ldpaa_eth/ls2080a.c index 93ed4f1..93ed4f1 100644 --- a/drivers/net/ldpaa_eth/ls2085a.c +++ b/drivers/net/ldpaa_eth/ls2080a.c diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index ef4da4e..f90c2ae 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -146,11 +146,26 @@ struct phy_driver aqr105_driver = { .startup = &aquantia_startup, .shutdown = &gen10g_shutdown, }; + +struct phy_driver aqr405_driver = { + .name = "Aquantia AQR405", + .uid = 0x3a1b4b2, + .mask = 0xfffffff0, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| + MDIO_MMD_PHYXS | MDIO_MMD_AN | + MDIO_MMD_VEND1), + .config = &aquantia_config, + .startup = &aquantia_startup, + .shutdown = &gen10g_shutdown, +}; + int phy_aquantia_init(void) { phy_register(&aq1202_driver); phy_register(&aq2104_driver); phy_register(&aqr105_driver); + phy_register(&aqr405_driver); return 0; } diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 5e49666..19b6bc7 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -9,9 +9,14 @@ */ #include <config.h> #include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> #include <micrel.h> #include <phy.h> +DECLARE_GLOBAL_DATA_PTR; + static struct phy_driver KSZ804_driver = { .name = "Micrel KSZ804", .uid = 0x221510, @@ -174,6 +179,73 @@ static int ksz90xx_startup(struct phy_device *phydev) return 0; } +/* Common OF config bits for KSZ9021 and KSZ9031 */ +#if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031) +#ifdef CONFIG_DM_ETH +struct ksz90x1_reg_field { + const char *name; + const u8 size; /* Size of the bitfield, in bits */ + const u8 off; /* Offset from bit 0 */ + const u8 dflt; /* Default value */ +}; + +struct ksz90x1_ofcfg { + const u16 reg; + const u16 devad; + const struct ksz90x1_reg_field *grp; + const u16 grpsz; +}; + +static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = { + { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 }, + { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 } +}; + +static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = { + { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 }, + { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 }, +}; + +static int ksz90x1_of_config_group(struct phy_device *phydev, + struct ksz90x1_ofcfg *ofcfg) +{ + struct udevice *dev = phydev->dev; + struct phy_driver *drv = phydev->drv; + const int ps_to_regval = 200; + int val[4]; + int i, changed = 0, offset, max; + u16 regval = 0; + + if (!drv || !drv->writeext) + return -EOPNOTSUPP; + + for (i = 0; i < ofcfg->grpsz; i++) { + val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + ofcfg->grp[i].name, -1); + offset = ofcfg->grp[i].off; + if (val[i] == -1) { + /* Default register value for KSZ9021 */ + regval |= ofcfg->grp[i].dflt << offset; + } else { + changed = 1; /* Value was changed in OF */ + /* Calculate the register value and fix corner cases */ + if (val[i] > ps_to_regval * 0xf) { + max = (1 << ofcfg->grp[i].size) - 1; + regval |= max << offset; + } else { + regval |= (val[i] / ps_to_regval) << offset; + } + } + } + + if (!changed) + return 0; + + return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval); +} +#endif +#endif + #ifdef CONFIG_PHY_MICREL_KSZ9021 /* * KSZ9021 @@ -188,6 +260,35 @@ static int ksz90xx_startup(struct phy_device *phydev) #define CTRL1000_CONFIG_MASTER (1 << 11) #define CTRL1000_MANUAL_CONFIG (1 << 12) +#ifdef CONFIG_DM_ETH +static const struct ksz90x1_reg_field ksz9021_clk_grp[] = { + { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 }, + { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 }, +}; + +static int ksz9021_of_config(struct phy_device *phydev) +{ + struct ksz90x1_ofcfg ofcfg[] = { + { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 }, + { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 }, + { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 }, + }; + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(ofcfg); i++) + ret = ksz90x1_of_config_group(phydev, &(ofcfg[i])); + if (ret) + return ret; + + return 0; +} +#else +static int ksz9021_of_config(struct phy_device *phydev) +{ + return 0; +} +#endif + int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val) { /* extended registers */ @@ -224,6 +325,11 @@ static int ksz9021_config(struct phy_device *phydev) const unsigned master = CTRL1000_PREFER_MASTER | CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG; unsigned features = phydev->drv->features; + int ret; + + ret = ksz9021_of_config(phydev); + if (ret) + return ret; if (getenv("disable_giga")) features &= ~(SUPPORTED_1000baseT_Half | @@ -260,6 +366,36 @@ static struct phy_driver ksz9021_driver = { #define MII_KSZ9031_MMD_ACCES_CTRL 0x0d #define MII_KSZ9031_MMD_REG_DATA 0x0e +#ifdef CONFIG_DM_ETH +static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = + { { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } }; +static const struct ksz90x1_reg_field ksz9031_clk_grp[] = + { { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } }; + +static int ksz9031_of_config(struct phy_device *phydev) +{ + struct ksz90x1_ofcfg ofcfg[] = { + { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 }, + { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 }, + { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 }, + { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 }, + }; + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(ofcfg); i++) + ret = ksz90x1_of_config_group(phydev, &(ofcfg[i])); + if (ret) + return ret; + + return 0; +} +#else +static int ksz9031_of_config(struct phy_device *phydev) +{ + return 0; +} +#endif + /* Accessors to extended registers*/ int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr, int regnum, u16 mode, u16 val) @@ -304,13 +440,21 @@ static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr, MII_KSZ9031_MOD_DATA_POST_INC_RW, val); }; +static int ksz9031_config(struct phy_device *phydev) +{ + int ret; + ret = ksz9031_of_config(phydev); + if (ret) + return ret; + return genphy_config(phydev); +} static struct phy_driver ksz9031_driver = { .name = "Micrel ksz9031", .uid = 0x221620, .mask = 0xfffff0, .features = PHY_GBIT_FEATURES, - .config = &genphy_config, + .config = &ksz9031_config, .startup = &ksz90xx_startup, .shutdown = &genphy_shutdown, .writeext = &ksz9031_phy_extwrite, diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 858093f..7059c84 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -10,11 +10,11 @@ */ #include <common.h> +#include <dm.h> #include <net.h> #include <netdev.h> #include <config.h> -#include <fdtdec.h> -#include <libfdt.h> +#include <console.h> #include <malloc.h> #include <asm/io.h> #include <phy.h> @@ -25,9 +25,7 @@ #include <asm/arch/sys_proto.h> #include <asm-generic/errno.h> -#if !defined(CONFIG_PHYLIB) -# error XILINX_GEM_ETHERNET requires PHYLIB -#endif +DECLARE_GLOBAL_DATA_PTR; /* Bit/mask specification */ #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ @@ -167,14 +165,14 @@ struct zynq_gem_priv { int phyaddr; u32 emio; int init; + struct zynq_gem_regs *iobase; phy_interface_t interface; struct phy_device *phydev; struct mii_dev *bus; }; -static inline int mdio_wait(struct eth_device *dev) +static inline int mdio_wait(struct zynq_gem_regs *regs) { - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; u32 timeout = 20000; /* Wait till MDIO interface is ready to accept a new transaction. */ @@ -192,13 +190,13 @@ static inline int mdio_wait(struct eth_device *dev) return 0; } -static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, - u32 op, u16 *data) +static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, + u32 op, u16 *data) { u32 mgtcr; - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; + struct zynq_gem_regs *regs = priv->iobase; - if (mdio_wait(dev)) + if (mdio_wait(regs)) return 1; /* Construct mgtcr mask for the operation */ @@ -209,7 +207,7 @@ static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, /* Write mgtcr and wait for completion */ writel(mgtcr, ®s->phymntnc); - if (mdio_wait(dev)) + if (mdio_wait(regs)) return 1; if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) @@ -218,12 +216,13 @@ static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, return 0; } -static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) +static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, + u32 regnum, u16 *val) { u32 ret; - ret = phy_setup_op(dev, phy_addr, regnum, - ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); + ret = phy_setup_op(priv, phy_addr, regnum, + ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); if (!ret) debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, @@ -232,29 +231,30 @@ static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) return ret; } -static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) +static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, + u32 regnum, u16 data) { debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, regnum, data); - return phy_setup_op(dev, phy_addr, regnum, - ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); + return phy_setup_op(priv, phy_addr, regnum, + ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); } -static void phy_detection(struct eth_device *dev) +static int phy_detection(struct udevice *dev) { int i; u16 phyreg; struct zynq_gem_priv *priv = dev->priv; if (priv->phyaddr != -1) { - phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg); + phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); if ((phyreg != 0xFFFF) && ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { /* Found a valid PHY address */ debug("Default phy address %d is valid\n", priv->phyaddr); - return; + return 0; } else { debug("PHY address is not setup correctly %d\n", priv->phyaddr); @@ -266,33 +266,36 @@ static void phy_detection(struct eth_device *dev) if (priv->phyaddr == -1) { /* detect the PHY address */ for (i = 31; i >= 0; i--) { - phyread(dev, i, PHY_DETECT_REG, &phyreg); + phyread(priv, i, PHY_DETECT_REG, &phyreg); if ((phyreg != 0xFFFF) && ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { /* Found a valid PHY address */ priv->phyaddr = i; debug("Found valid phy address, %d\n", i); - return; + return 0; } } } printf("PHY is not detected\n"); + return -1; } -static int zynq_gem_setup_mac(struct eth_device *dev) +static int zynq_gem_setup_mac(struct udevice *dev) { u32 i, macaddrlow, macaddrhigh; - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; + struct eth_pdata *pdata = dev_get_platdata(dev); + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; /* Set the MAC bits [31:0] in BOT */ - macaddrlow = dev->enetaddr[0]; - macaddrlow |= dev->enetaddr[1] << 8; - macaddrlow |= dev->enetaddr[2] << 16; - macaddrlow |= dev->enetaddr[3] << 24; + macaddrlow = pdata->enetaddr[0]; + macaddrlow |= pdata->enetaddr[1] << 8; + macaddrlow |= pdata->enetaddr[2] << 16; + macaddrlow |= pdata->enetaddr[3] << 24; /* Set MAC bits [47:32] in TOP */ - macaddrhigh = dev->enetaddr[4]; - macaddrhigh |= dev->enetaddr[5] << 8; + macaddrhigh = pdata->enetaddr[4]; + macaddrhigh |= pdata->enetaddr[5] << 8; for (i = 0; i < 4; i++) { writel(0, ®s->laddr[i][LADDR_LOW]); @@ -307,15 +310,11 @@ static int zynq_gem_setup_mac(struct eth_device *dev) return 0; } -static int zynq_gem_init(struct eth_device *dev, bd_t * bis) +static int zynq_phy_init(struct udevice *dev) { - u32 i; - unsigned long clk_rate = 0; - struct phy_device *phydev; - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; - struct zynq_gem_priv *priv = dev->priv; - struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; - struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; + int ret; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; const u32 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | @@ -323,6 +322,37 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full; + /* Enable only MDIO bus */ + writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); + + ret = phy_detection(dev); + if (ret) { + printf("GEM PHY init failed\n"); + return ret; + } + + priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, + priv->interface); + if (!priv->phydev) + return -ENODEV; + + priv->phydev->supported = supported | ADVERTISED_Pause | + ADVERTISED_Asym_Pause; + priv->phydev->advertising = priv->phydev->supported; + phy_config(priv->phydev); + + return 0; +} + +static int zynq_gem_init(struct udevice *dev) +{ + u32 i; + unsigned long clk_rate = 0; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; + struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; + struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; + if (!priv->init) { /* Disable all interrupts */ writel(0xFFFFFFFF, ®s->idr); @@ -384,25 +414,14 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) priv->init++; } - phy_detection(dev); - - /* interface - look at tsec */ - phydev = phy_connect(priv->bus, priv->phyaddr, dev, - priv->interface); + phy_startup(priv->phydev); - phydev->supported = supported | ADVERTISED_Pause | - ADVERTISED_Asym_Pause; - phydev->advertising = phydev->supported; - priv->phydev = phydev; - phy_config(phydev); - phy_startup(phydev); - - if (!phydev->link) { - printf("%s: No link.\n", phydev->dev->name); + if (!priv->phydev->link) { + printf("%s: No link.\n", priv->phydev->dev->name); return -1; } - switch (phydev->speed) { + switch (priv->phydev->speed) { case SPEED_1000: writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, ®s->nwcfg); @@ -420,7 +439,7 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) /* Change the rclk and clk only not using EMIO interface */ if (!priv->emio) - zynq_slcr_gem_clk_setup(dev->iobase != + zynq_slcr_gem_clk_setup((ulong)priv->iobase != ZYNQ_GEM_BASEADDR0, clk_rate); setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | @@ -447,6 +466,11 @@ static int wait_for_bit(const char *func, u32 *reg, const u32 mask, if (get_timer(start) > timeout) break; + if (ctrlc()) { + puts("Abort\n"); + return -EINTR; + } + udelay(1); } @@ -456,11 +480,11 @@ static int wait_for_bit(const char *func, u32 *reg, const u32 mask, return -ETIMEDOUT; } -static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) +static int zynq_gem_send(struct udevice *dev, void *ptr, int len) { u32 addr, size; - struct zynq_gem_priv *priv = dev->priv; - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; struct emac_bd *current_bd = &priv->tx_bd[1]; /* Setup Tx BD */ @@ -501,94 +525,95 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) } /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ -static int zynq_gem_recv(struct eth_device *dev) +static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) { int frame_len; - struct zynq_gem_priv *priv = dev->priv; + u32 addr; + struct zynq_gem_priv *priv = dev_get_priv(dev); struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; - struct emac_bd *first_bd; if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) - return 0; + return -1; if (!(current_bd->status & (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { printf("GEM: SOF or EOF not set for last buffer received!\n"); - return 0; + return -1; } frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; - if (frame_len) { - u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; - addr &= ~(ARCH_DMA_MINALIGN - 1); + if (!frame_len) { + printf("%s: Zero size packet?\n", __func__); + return -1; + } - net_process_received_packet((u8 *)(ulong)addr, frame_len); + addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; + addr &= ~(ARCH_DMA_MINALIGN - 1); + *packetp = (uchar *)(uintptr_t)addr; - if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) - priv->rx_first_buf = priv->rxbd_current; - else { - current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; - current_bd->status = 0xF0000000; /* FIXME */ - } + return frame_len; +} - if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { - first_bd = &priv->rx_bd[priv->rx_first_buf]; - first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; - first_bd->status = 0xF0000000; - } +static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; + struct emac_bd *first_bd; - if ((++priv->rxbd_current) >= RX_BUF) - priv->rxbd_current = 0; + if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { + priv->rx_first_buf = priv->rxbd_current; + } else { + current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; + current_bd->status = 0xF0000000; /* FIXME */ } - return frame_len; + if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { + first_bd = &priv->rx_bd[priv->rx_first_buf]; + first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; + first_bd->status = 0xF0000000; + } + + if ((++priv->rxbd_current) >= RX_BUF) + priv->rxbd_current = 0; + + return 0; } -static void zynq_gem_halt(struct eth_device *dev) +static void zynq_gem_halt(struct udevice *dev) { - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); } -static int zynq_gem_miiphyread(const char *devname, uchar addr, - uchar reg, ushort *val) +static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, + int devad, int reg) { - struct eth_device *dev = eth_get_dev(); + struct zynq_gem_priv *priv = bus->priv; int ret; + u16 val; - ret = phyread(dev, addr, reg, val); - debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); - return ret; + ret = phyread(priv, addr, reg, &val); + debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); + return val; } -static int zynq_gem_miiphy_write(const char *devname, uchar addr, - uchar reg, ushort val) +static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) { - struct eth_device *dev = eth_get_dev(); + struct zynq_gem_priv *priv = bus->priv; - debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); - return phywrite(dev, addr, reg, val); + debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); + return phywrite(priv, addr, reg, value); } -int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, - int phy_addr, u32 emio) +static int zynq_gem_probe(struct udevice *dev) { - struct eth_device *dev; - struct zynq_gem_priv *priv; void *bd_space; - - dev = calloc(1, sizeof(*dev)); - if (dev == NULL) - return -1; - - dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); - if (dev->priv == NULL) { - free(dev); - return -1; - } - priv = dev->priv; + struct zynq_gem_priv *priv = dev_get_priv(dev); + int ret; /* Align rxbuffers to ARCH_DMA_MINALIGN */ priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); @@ -603,69 +628,89 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, priv->tx_bd = (struct emac_bd *)bd_space; priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); - priv->phyaddr = phy_addr; - priv->emio = emio; + priv->bus = mdio_alloc(); + priv->bus->read = zynq_gem_miiphy_read; + priv->bus->write = zynq_gem_miiphy_write; + priv->bus->priv = priv; + strcpy(priv->bus->name, "gem"); -#ifndef CONFIG_ZYNQ_GEM_INTERFACE - priv->interface = PHY_INTERFACE_MODE_MII; -#else - priv->interface = CONFIG_ZYNQ_GEM_INTERFACE; -#endif + ret = mdio_register(priv->bus); + if (ret) + return ret; - sprintf(dev->name, "Gem.%lx", base_addr); + zynq_phy_init(dev); - dev->iobase = base_addr; - - dev->init = zynq_gem_init; - dev->halt = zynq_gem_halt; - dev->send = zynq_gem_send; - dev->recv = zynq_gem_recv; - dev->write_hwaddr = zynq_gem_setup_mac; + return 0; +} - eth_register(dev); +static int zynq_gem_remove(struct udevice *dev) +{ + struct zynq_gem_priv *priv = dev_get_priv(dev); - miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); - priv->bus = miiphy_get_dev_by_name(dev->name); + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); - return 1; + return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) -int zynq_gem_of_init(const void *blob) +static const struct eth_ops zynq_gem_ops = { + .start = zynq_gem_init, + .send = zynq_gem_send, + .recv = zynq_gem_recv, + .free_pkt = zynq_gem_free_pkt, + .stop = zynq_gem_halt, + .write_hwaddr = zynq_gem_setup_mac, +}; + +static int zynq_gem_ofdata_to_platdata(struct udevice *dev) { + struct eth_pdata *pdata = dev_get_platdata(dev); + struct zynq_gem_priv *priv = dev_get_priv(dev); int offset = 0; - u32 ret = 0; - u32 reg, phy_reg; - - debug("ZYNQ GEM: Initialization\n"); - - do { - offset = fdt_node_offset_by_compatible(blob, offset, - "xlnx,ps7-ethernet-1.00.a"); - if (offset != -1) { - reg = fdtdec_get_addr(blob, offset, "reg"); - if (reg != FDT_ADDR_T_NONE) { - offset = fdtdec_lookup_phandle(blob, offset, - "phy-handle"); - if (offset != -1) - phy_reg = fdtdec_get_addr(blob, offset, - "reg"); - else - phy_reg = 0; - - debug("ZYNQ GEM: addr %x, phyaddr %x\n", - reg, phy_reg); - - ret |= zynq_gem_initialize(NULL, reg, - phy_reg, 0); - - } else { - debug("ZYNQ GEM: Can't get base address\n"); - return -1; - } - } - } while (offset != -1); + const char *phy_mode; + + pdata->iobase = (phys_addr_t)dev_get_addr(dev); + priv->iobase = (struct zynq_gem_regs *)pdata->iobase; + /* Hardcode for now */ + priv->emio = 0; + priv->phyaddr = -1; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "phy-handle"); + if (offset > 0) + priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); + + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + priv->interface = pdata->phy_interface; - return ret; + printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, + priv->phyaddr, phy_string_for_interface(priv->interface)); + + return 0; } -#endif + +static const struct udevice_id zynq_gem_ids[] = { + { .compatible = "cdns,zynqmp-gem" }, + { .compatible = "cdns,zynq-gem" }, + { .compatible = "cdns,gem" }, + { } +}; + +U_BOOT_DRIVER(zynq_gem) = { + .name = "zynq_gem", + .id = UCLASS_ETH, + .of_match = zynq_gem_ids, + .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, + .probe = zynq_gem_probe, + .remove = zynq_gem_remove, + .ops = &zynq_gem_ops, + .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 167d405..26aa2b0 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -9,6 +9,15 @@ config DM_PCI available PCI devices, allows scanning of PCI buses and provides device configuration support. +config DM_PCI_COMPAT + bool "Enable compatible functions for PCI" + depends on DM_PCI + help + Enable compatibility functions for PCI so that old code can be used + with CONFIG_DM_PCI enabled. This should be used as an interim + measure when porting a board to use driver model for PCI. Once the + board is fully supported, this option should be disabled. + config PCI_SANDBOX bool "Sandbox PCI support" depends on SANDBOX && DM_PCI @@ -19,4 +28,14 @@ config PCI_SANDBOX the device tree but the normal PCI scan technique is used to find then. +config PCI_TEGRA + bool "Tegra PCI support" + depends on TEGRA + help + Enable support for the PCIe controller found on some generations of + Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has + 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports + with a total of 5 lanes. Some boards require this for Ethernet + support to work (e.g. beaver, jetson-tk1). + endmenu diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index bcf8127..6b761b4 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -6,14 +6,15 @@ # ifneq ($(CONFIG_DM_PCI),) -obj-$(CONFIG_PCI) += pci-uclass.o pci_compat.o +obj-$(CONFIG_PCI) += pci-uclass.o +obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o obj-$(CONFIG_X86) += pci_x86.o else obj-$(CONFIG_PCI) += pci.o endif -obj-$(CONFIG_PCI) += pci_common.o pci_auto.o pci_rom.o +obj-$(CONFIG_PCI) += pci_auto_common.o pci_auto_old.o pci_common.o pci_rom.o obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 1d93194..5fe3072 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -53,6 +53,14 @@ struct pci_controller *pci_bus_to_hose(int busnum) return dev_get_uclass_priv(bus); } +struct udevice *pci_get_controller(struct udevice *dev) +{ + while (device_is_on_pci_bus(dev)) + dev = dev->parent; + + return dev; +} + pci_dev_t pci_get_bdf(struct udevice *dev) { struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); @@ -680,8 +688,8 @@ static int decode_regions(struct pci_controller *hose, const void *blob, int parent_node, int node) { int pci_addr_cells, addr_cells, size_cells; + phys_addr_t base = 0, size; int cells_per_record; - phys_addr_t addr; const u32 *prop; int len; int i; @@ -704,6 +712,7 @@ static int decode_regions(struct pci_controller *hose, const void *blob, int space_code; u32 flags; int type; + int pos; if (len < cells_per_record) break; @@ -726,17 +735,26 @@ static int decode_regions(struct pci_controller *hose, const void *blob, } else { continue; } - debug(" - type=%d\n", type); - pci_set_region(hose->regions + hose->region_count++, pci_addr, - addr, size, type); + pos = -1; + for (i = 0; i < hose->region_count; i++) { + if (hose->regions[i].flags == type) + pos = i; + } + if (pos == -1) + pos = hose->region_count++; + debug(" - type=%d, pos=%d\n", type, pos); + pci_set_region(hose->regions + pos, pci_addr, addr, size, type); } /* Add a region for our local memory */ - addr = gd->ram_size; - if (gd->pci_ram_top && gd->pci_ram_top < addr) - addr = gd->pci_ram_top; - pci_set_region(hose->regions + hose->region_count++, 0, 0, addr, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + size = gd->ram_size; +#ifdef CONFIG_SYS_SDRAM_BASE + base = CONFIG_SYS_SDRAM_BASE; +#endif + if (gd->pci_ram_top && gd->pci_ram_top < base + size) + size = gd->pci_ram_top - base; + pci_set_region(hose->regions + hose->region_count++, base, base, + size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); return 0; } @@ -917,6 +935,75 @@ int pci_find_first_device(struct udevice **devp) return skip_to_next_device(bus, devp); } +ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size) +{ + switch (size) { + case PCI_SIZE_8: + return (value >> ((offset & 3) * 8)) & 0xff; + case PCI_SIZE_16: + return (value >> ((offset & 2) * 8)) & 0xffff; + default: + return value; + } +} + +ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, + enum pci_size_t size) +{ + uint off_mask; + uint val_mask, shift; + ulong ldata, mask; + + switch (size) { + case PCI_SIZE_8: + off_mask = 3; + val_mask = 0xff; + break; + case PCI_SIZE_16: + off_mask = 2; + val_mask = 0xffff; + break; + default: + return value; + } + shift = (offset & off_mask) * 8; + ldata = (value & val_mask) << shift; + mask = val_mask << shift; + value = (old & ~mask) | ldata; + + return value; +} + +int pci_get_regions(struct udevice *dev, struct pci_region **iop, + struct pci_region **memp, struct pci_region **prefp) +{ + struct udevice *bus = pci_get_controller(dev); + struct pci_controller *hose = dev_get_uclass_priv(bus); + int i; + + *iop = NULL; + *memp = NULL; + *prefp = NULL; + for (i = 0; i < hose->region_count; i++) { + switch (hose->regions[i].flags) { + case PCI_REGION_IO: + if (!*iop || (*iop)->size < hose->regions[i].size) + *iop = hose->regions + i; + break; + case PCI_REGION_MEM: + if (!*memp || (*memp)->size < hose->regions[i].size) + *memp = hose->regions + i; + break; + case (PCI_REGION_MEM | PCI_REGION_PREFETCH): + if (!*prefp || (*prefp)->size < hose->regions[i].size) + *prefp = hose->regions + i; + break; + } + } + + return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL); +} + UCLASS_DRIVER(pci) = { .id = UCLASS_PCI, .name = "pci", diff --git a/drivers/pci/pci_auto_common.c b/drivers/pci/pci_auto_common.c new file mode 100644 index 0000000..85c419e --- /dev/null +++ b/drivers/pci/pci_auto_common.c @@ -0,0 +1,128 @@ +/* + * PCI auto-configuration library + * + * Author: Matt Porter <mporter@mvista.com> + * + * Copyright 2000 MontaVista Software Inc. + * + * Modifications for driver model: + * Copyright 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <pci.h> + +void pciauto_region_init(struct pci_region *res) +{ + /* + * Avoid allocating PCI resources from address 0 -- this is illegal + * according to PCI 2.1 and moreover, this is known to cause Linux IDE + * drivers to fail. Use a reasonable starting value of 0x1000 instead. + */ + res->bus_lower = res->bus_start ? res->bus_start : 0x1000; +} + +void pciauto_region_align(struct pci_region *res, pci_size_t size) +{ + res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1; +} + +int pciauto_region_allocate(struct pci_region *res, pci_size_t size, + pci_addr_t *bar) +{ + pci_addr_t addr; + + if (!res) { + debug("No resource"); + goto error; + } + + addr = ((res->bus_lower - 1) | (size - 1)) + 1; + + if (addr - res->bus_start + size > res->size) { + debug("No room in resource"); + goto error; + } + + res->bus_lower = addr + size; + + debug("address=0x%llx bus_lower=0x%llx", (unsigned long long)addr, + (unsigned long long)res->bus_lower); + + *bar = addr; + return 0; + + error: + *bar = (pci_addr_t)-1; + return -1; +} + +void pciauto_config_init(struct pci_controller *hose) +{ + int i; + + hose->pci_io = NULL; + hose->pci_mem = NULL; + hose->pci_prefetch = NULL; + + for (i = 0; i < hose->region_count; i++) { + switch (hose->regions[i].flags) { + case PCI_REGION_IO: + if (!hose->pci_io || + hose->pci_io->size < hose->regions[i].size) + hose->pci_io = hose->regions + i; + break; + case PCI_REGION_MEM: + if (!hose->pci_mem || + hose->pci_mem->size < hose->regions[i].size) + hose->pci_mem = hose->regions + i; + break; + case (PCI_REGION_MEM | PCI_REGION_PREFETCH): + if (!hose->pci_prefetch || + hose->pci_prefetch->size < hose->regions[i].size) + hose->pci_prefetch = hose->regions + i; + break; + } + } + + + if (hose->pci_mem) { + pciauto_region_init(hose->pci_mem); + + debug("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n" + "\t\tPhysical Memory [%llx-%llxx]\n", + (u64)hose->pci_mem->bus_start, + (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1), + (u64)hose->pci_mem->phys_start, + (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1)); + } + + if (hose->pci_prefetch) { + pciauto_region_init(hose->pci_prefetch); + + debug("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n" + "\t\tPhysical Memory [%llx-%llx]\n", + (u64)hose->pci_prefetch->bus_start, + (u64)(hose->pci_prefetch->bus_start + + hose->pci_prefetch->size - 1), + (u64)hose->pci_prefetch->phys_start, + (u64)(hose->pci_prefetch->phys_start + + hose->pci_prefetch->size - 1)); + } + + if (hose->pci_io) { + pciauto_region_init(hose->pci_io); + + debug("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n" + "\t\tPhysical Memory: [%llx-%llx]\n", + (u64)hose->pci_io->bus_start, + (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1), + (u64)hose->pci_io->phys_start, + (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1)); + } +} diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto_old.c index 0412bf3..932eab8 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto_old.c @@ -23,55 +23,6 @@ * */ -void pciauto_region_init(struct pci_region *res) -{ - /* - * Avoid allocating PCI resources from address 0 -- this is illegal - * according to PCI 2.1 and moreover, this is known to cause Linux IDE - * drivers to fail. Use a reasonable starting value of 0x1000 instead. - */ - res->bus_lower = res->bus_start ? res->bus_start : 0x1000; -} - -void pciauto_region_align(struct pci_region *res, pci_size_t size) -{ - res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1; -} - -int pciauto_region_allocate(struct pci_region *res, pci_size_t size, - pci_addr_t *bar) -{ - pci_addr_t addr; - - if (!res) { - debug("No resource"); - goto error; - } - - addr = ((res->bus_lower - 1) | (size - 1)) + 1; - - if (addr - res->bus_start + size > res->size) { - debug("No room in resource"); - goto error; - } - - res->bus_lower = addr + size; - - debug("address=0x%llx bus_lower=0x%llx", (unsigned long long)addr, - (unsigned long long)res->bus_lower); - - *bar = addr; - return 0; - - error: - *bar = (pci_addr_t)-1; - return -1; -} - -/* - * - */ - void pciauto_setup_device(struct pci_controller *hose, pci_dev_t dev, int bars_num, struct pci_region *mem, @@ -385,73 +336,6 @@ void pciauto_postscan_setup_bridge(struct pci_controller *hose, } } -/* - * - */ - -void pciauto_config_init(struct pci_controller *hose) -{ - int i; - - hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL; - - for (i = 0; i < hose->region_count; i++) { - switch(hose->regions[i].flags) { - case PCI_REGION_IO: - if (!hose->pci_io || - hose->pci_io->size < hose->regions[i].size) - hose->pci_io = hose->regions + i; - break; - case PCI_REGION_MEM: - if (!hose->pci_mem || - hose->pci_mem->size < hose->regions[i].size) - hose->pci_mem = hose->regions + i; - break; - case (PCI_REGION_MEM | PCI_REGION_PREFETCH): - if (!hose->pci_prefetch || - hose->pci_prefetch->size < hose->regions[i].size) - hose->pci_prefetch = hose->regions + i; - break; - } - } - - - if (hose->pci_mem) { - pciauto_region_init(hose->pci_mem); - - debug("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n" - "\t\tPhysical Memory [%llx-%llxx]\n", - (u64)hose->pci_mem->bus_start, - (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1), - (u64)hose->pci_mem->phys_start, - (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1)); - } - - if (hose->pci_prefetch) { - pciauto_region_init(hose->pci_prefetch); - - debug("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n" - "\t\tPhysical Memory [%llx-%llx]\n", - (u64)hose->pci_prefetch->bus_start, - (u64)(hose->pci_prefetch->bus_start + - hose->pci_prefetch->size - 1), - (u64)hose->pci_prefetch->phys_start, - (u64)(hose->pci_prefetch->phys_start + - hose->pci_prefetch->size - 1)); - } - - if (hose->pci_io) { - pciauto_region_init(hose->pci_io); - - debug("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n" - "\t\tPhysical Memory: [%llx-%llx]\n", - (u64)hose->pci_io->bus_start, - (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1), - (u64)hose->pci_io->phys_start, - (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1)); - - } -} /* * HJF: Changed this to return int. I think this is required diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c index a64792f..2a14902 100644 --- a/drivers/pci/pci_common.c +++ b/drivers/pci/pci_common.c @@ -268,7 +268,7 @@ int __pci_hose_phys_to_bus(struct pci_controller *hose, bus_addr = phys_addr - res->phys_start + res->bus_start; if (bus_addr >= res->bus_start && - bus_addr < res->bus_start + res->size) { + (bus_addr - res->bus_start) < res->size) { *ba = bus_addr; return 0; } diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index d244543..ad1167e 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -33,10 +33,6 @@ #include <video_fb.h> #include <linux/screen_info.h> -#ifdef CONFIG_HAVE_ACPI_RESUME -#include <asm/acpi.h> -#endif - __weak bool board_should_run_oprom(pci_dev_t dev) { return true; @@ -44,10 +40,6 @@ __weak bool board_should_run_oprom(pci_dev_t dev) static bool should_load_oprom(pci_dev_t dev) { -#ifdef CONFIG_HAVE_ACPI_RESUME - if (acpi_get_slp_type() == 3) - return false; -#endif if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) return 1; if (board_should_run_oprom(dev)) diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index 690896f..5a7fefe 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -10,10 +10,10 @@ * SPDX-License-Identifier: GPL-2.0 */ -#define DEBUG #define pr_fmt(fmt) "tegra-pcie: " fmt #include <common.h> +#include <dm.h> #include <errno.h> #include <fdtdec.h> #include <malloc.h> @@ -177,7 +177,12 @@ DECLARE_GLOBAL_DATA_PTR; #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 -struct tegra_pcie; +enum tegra_pci_id { + TEGRA20_PCIE, + TEGRA30_PCIE, + TEGRA124_PCIE, + TEGRA210_PCIE, +}; struct tegra_pcie_port { struct tegra_pcie *pcie; @@ -207,10 +212,6 @@ struct tegra_pcie { struct fdt_resource afi; struct fdt_resource cs; - struct fdt_resource prefetch; - struct fdt_resource mem; - struct fdt_resource io; - struct list_head ports; unsigned long xbar; @@ -218,11 +219,6 @@ struct tegra_pcie { struct tegra_xusb_phy *phy; }; -static inline struct tegra_pcie *to_tegra_pcie(struct pci_controller *hose) -{ - return container_of(hose, struct tegra_pcie, hose); -} - static void afi_writel(struct tegra_pcie *pcie, unsigned long value, unsigned long offset) { @@ -284,46 +280,54 @@ static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, return 0; } - return -1; + return -EFAULT; } -static int tegra_pcie_read_conf(struct pci_controller *hose, pci_dev_t bdf, - int where, u32 *value) +static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) { - struct tegra_pcie *pcie = to_tegra_pcie(hose); - unsigned long address; + struct tegra_pcie *pcie = dev_get_priv(bus); + unsigned long address, value; int err; - err = tegra_pcie_conf_address(pcie, bdf, where, &address); + err = tegra_pcie_conf_address(pcie, bdf, offset, &address); if (err < 0) { - *value = 0xffffffff; - return 1; + value = 0xffffffff; + goto done; } - *value = readl(address); + value = readl(address); /* fixup root port class */ if (PCI_BUS(bdf) == 0) { - if (where == PCI_CLASS_REVISION) { - *value &= ~0x00ff0000; - *value |= PCI_CLASS_BRIDGE_PCI << 16; + if (offset == PCI_CLASS_REVISION) { + value &= ~0x00ff0000; + value |= PCI_CLASS_BRIDGE_PCI << 16; } } +done: + *valuep = pci_conv_32_to_size(value, offset, size); + return 0; } -static int tegra_pcie_write_conf(struct pci_controller *hose, pci_dev_t bdf, - int where, u32 value) +static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) { - struct tegra_pcie *pcie = to_tegra_pcie(hose); + struct tegra_pcie *pcie = dev_get_priv(bus); unsigned long address; + ulong old; int err; - err = tegra_pcie_conf_address(pcie, bdf, where, &address); + err = tegra_pcie_conf_address(pcie, bdf, offset, &address); if (err < 0) - return 1; + return 0; + old = readl(address); + value = pci_conv_size_to_32(old, value, offset, size); writel(value, address); return 0; @@ -348,12 +352,10 @@ static int tegra_pcie_port_parse_dt(const void *fdt, int node, } static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, - unsigned long *xbar) + enum tegra_pci_id id, unsigned long *xbar) { - enum fdt_compat_id id = fdtdec_lookup(fdt, node); - switch (id) { - case COMPAT_NVIDIA_TEGRA20_PCIE: + case TEGRA20_PCIE: switch (lanes) { case 0x00000004: debug("single-mode configuration\n"); @@ -366,8 +368,7 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, return 0; } break; - - case COMPAT_NVIDIA_TEGRA30_PCIE: + case TEGRA30_PCIE: switch (lanes) { case 0x00000204: debug("4x1, 2x1 configuration\n"); @@ -385,9 +386,8 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, return 0; } break; - - case COMPAT_NVIDIA_TEGRA124_PCIE: - case COMPAT_NVIDIA_TEGRA210_PCIE: + case TEGRA124_PCIE: + case TEGRA210_PCIE: switch (lanes) { case 0x0000104: debug("4x1, 1x1 configuration\n"); @@ -400,7 +400,6 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, return 0; } break; - default: break; } @@ -408,84 +407,6 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, return -FDT_ERR_NOTFOUND; } -static int tegra_pcie_parse_dt_ranges(const void *fdt, int node, - struct tegra_pcie *pcie) -{ - int parent, na_parent, na_pcie, ns_pcie; - const u32 *ptr, *end; - int len; - - parent = fdt_parent_offset(fdt, node); - if (parent < 0) { - error("Can't find PCI parent node\n"); - return -FDT_ERR_NOTFOUND; - } - - na_parent = fdt_address_cells(fdt, parent); - if (na_parent < 1) { - error("bad #address-cells for PCIE parent\n"); - return -FDT_ERR_NOTFOUND; - } - - na_pcie = fdt_address_cells(fdt, node); - if (na_pcie < 1) { - error("bad #address-cells for PCIE\n"); - return -FDT_ERR_NOTFOUND; - } - - ns_pcie = fdt_size_cells(fdt, node); - if (ns_pcie < 1) { - error("bad #size-cells for PCIE\n"); - return -FDT_ERR_NOTFOUND; - } - - ptr = fdt_getprop(fdt, node, "ranges", &len); - if (!ptr) { - error("missing \"ranges\" property"); - return -FDT_ERR_NOTFOUND; - } - - end = ptr + len / 4; - - while (ptr < end) { - struct fdt_resource *res = NULL; - u32 space = fdt32_to_cpu(*ptr); - - switch ((space >> 24) & 0x3) { - case 0x01: - res = &pcie->io; - break; - - case 0x02: /* 32 bit */ - case 0x03: /* 64 bit */ - if (space & (1 << 30)) - res = &pcie->prefetch; - else - res = &pcie->mem; - - break; - } - - if (res) { - int start_low = na_pcie + (na_parent - 1); - int size_low = na_pcie + na_parent + (ns_pcie - 1); - res->start = fdt32_to_cpu(ptr[start_low]); - res->end = res->start + fdt32_to_cpu(ptr[size_low]); - } - - ptr += na_pcie + na_parent + ns_pcie; - } - - debug("PCI regions:\n"); - debug(" I/O: %pa-%pa\n", &pcie->io.start, &pcie->io.end); - debug(" non-prefetchable memory: %pa-%pa\n", &pcie->mem.start, - &pcie->mem.end); - debug(" prefetchable memory: %pa-%pa\n", &pcie->prefetch.start, - &pcie->prefetch.end); - - return 0; -} - static int tegra_pcie_parse_port_info(const void *fdt, int node, unsigned int *index, unsigned int *lanes) @@ -512,7 +433,12 @@ static int tegra_pcie_parse_port_info(const void *fdt, int node, return 0; } -static int tegra_pcie_parse_dt(const void *fdt, int node, +int __weak tegra_pcie_board_init(void) +{ + return 0; +} + +static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id, struct tegra_pcie *pcie) { int err, subnode; @@ -539,6 +465,8 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, return err; } + tegra_pcie_board_init(); + pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); if (pcie->phy) { err = tegra_xusb_phy_prepare(pcie->phy); @@ -548,12 +476,6 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, } } - err = tegra_pcie_parse_dt_ranges(fdt, node, pcie); - if (err < 0) { - error("failed to parse \"ranges\" property"); - return err; - } - fdt_for_each_subnode(fdt, subnode, node) { unsigned int index = 0, num_lanes = 0; struct tegra_pcie_port *port; @@ -588,7 +510,7 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, port->pcie = pcie; } - err = tegra_pcie_get_xbar_config(fdt, node, lanes, &pcie->xbar); + err = tegra_pcie_get_xbar_config(fdt, node, lanes, id, &pcie->xbar); if (err < 0) { error("invalid lane configuration"); return err; @@ -597,11 +519,6 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, return 0; } -int __weak tegra_pcie_board_init(void) -{ - return 0; -} - static int tegra_pcie_power_on(struct tegra_pcie *pcie) { const struct tegra_pcie_soc *soc = pcie->soc; @@ -788,9 +705,12 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) return 0; } -static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) +static int tegra_pcie_setup_translations(struct udevice *bus) { + struct tegra_pcie *pcie = dev_get_priv(bus); unsigned long fpci, axi, size; + struct pci_region *io, *mem, *pref; + int count; /* BAR 0: type 1 extended configuration space */ fpci = 0xfe100000; @@ -801,28 +721,32 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); afi_writel(pcie, fpci, AFI_FPCI_BAR0); + count = pci_get_regions(bus, &io, &mem, &pref); + if (count != 3) + return -EINVAL; + /* BAR 1: downstream I/O */ fpci = 0xfdfc0000; - size = fdt_resource_size(&pcie->io); - axi = pcie->io.start; + size = io->size; + axi = io->phys_start; afi_writel(pcie, axi, AFI_AXI_BAR1_START); afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); afi_writel(pcie, fpci, AFI_FPCI_BAR1); /* BAR 2: prefetchable memory */ - fpci = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1; - size = fdt_resource_size(&pcie->prefetch); - axi = pcie->prefetch.start; + fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1; + size = pref->size; + axi = pref->phys_start; afi_writel(pcie, axi, AFI_AXI_BAR2_START); afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); afi_writel(pcie, fpci, AFI_FPCI_BAR2); /* BAR 3: non-prefetchable memory */ - fpci = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1; - size = fdt_resource_size(&pcie->mem); - axi = pcie->mem.start; + fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1; + size = mem->size; + axi = mem->phys_start; afi_writel(pcie, axi, AFI_AXI_BAR3_START); afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); @@ -848,6 +772,8 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) afi_writel(pcie, 0, AFI_MSI_BAR_SZ); afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); afi_writel(pcie, 0, AFI_MSI_BAR_SZ); + + return 0; } static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) @@ -1001,209 +927,116 @@ static int tegra_pcie_enable(struct tegra_pcie *pcie) return 0; } -static const struct tegra_pcie_soc tegra20_pcie_soc = { - .num_ports = 2, - .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, - .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, - .has_pex_clkreq_en = false, - .has_pex_bias_ctrl = false, - .has_cml_clk = false, - .has_gen2 = false, - .force_pca_enable = false, -}; - -static const struct tegra_pcie_soc tegra30_pcie_soc = { - .num_ports = 3, - .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, - .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, - .has_pex_clkreq_en = true, - .has_pex_bias_ctrl = true, - .has_cml_clk = true, - .has_gen2 = false, - .force_pca_enable = false, -}; - -static const struct tegra_pcie_soc tegra124_pcie_soc = { - .num_ports = 2, - .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, - .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, - .has_pex_clkreq_en = true, - .has_pex_bias_ctrl = true, - .has_cml_clk = true, - .has_gen2 = true, - .force_pca_enable = false, -}; - -static const struct tegra_pcie_soc tegra210_pcie_soc = { - .num_ports = 2, - .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, - .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, - .has_pex_clkreq_en = true, - .has_pex_bias_ctrl = true, - .has_cml_clk = true, - .has_gen2 = true, - .force_pca_enable = true, +static const struct tegra_pcie_soc pci_tegra_soc[] = { + [TEGRA20_PCIE] = { + .num_ports = 2, + .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, + .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, + .has_pex_clkreq_en = false, + .has_pex_bias_ctrl = false, + .has_cml_clk = false, + .has_gen2 = false, + }, + [TEGRA30_PCIE] = { + .num_ports = 3, + .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, + .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .has_pex_clkreq_en = true, + .has_pex_bias_ctrl = true, + .has_cml_clk = true, + .has_gen2 = false, + }, + [TEGRA124_PCIE] = { + .num_ports = 2, + .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, + .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .has_pex_clkreq_en = true, + .has_pex_bias_ctrl = true, + .has_cml_clk = true, + .has_gen2 = true, + }, + [TEGRA210_PCIE] = { + .num_ports = 2, + .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, + .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .has_pex_clkreq_en = true, + .has_pex_bias_ctrl = true, + .has_cml_clk = true, + .has_gen2 = true, + .force_pca_enable = true, + } }; -static int process_nodes(const void *fdt, int nodes[], unsigned int count) +static int pci_tegra_ofdata_to_platdata(struct udevice *dev) { - unsigned int i; - uint64_t dram_end; - uint32_t pci_dram_size; - - /* Clip PCI-accessible DRAM to 32-bits */ - dram_end = ((uint64_t)NV_PA_SDRAM_BASE) + gd->ram_size; - if (dram_end > 0x100000000) - dram_end = 0x100000000; - pci_dram_size = dram_end - NV_PA_SDRAM_BASE; - - for (i = 0; i < count; i++) { - const struct tegra_pcie_soc *soc; - struct tegra_pcie *pcie; - enum fdt_compat_id id; - int err; - - if (!fdtdec_get_is_enabled(fdt, nodes[i])) - continue; - - id = fdtdec_lookup(fdt, nodes[i]); - switch (id) { - case COMPAT_NVIDIA_TEGRA20_PCIE: - soc = &tegra20_pcie_soc; - break; - - case COMPAT_NVIDIA_TEGRA30_PCIE: - soc = &tegra30_pcie_soc; - break; - - case COMPAT_NVIDIA_TEGRA124_PCIE: - soc = &tegra124_pcie_soc; - break; - - case COMPAT_NVIDIA_TEGRA210_PCIE: - soc = &tegra210_pcie_soc; - break; - - default: - error("unsupported compatible: %s", - fdtdec_get_compatible(id)); - continue; - } - - pcie = malloc(sizeof(*pcie)); - if (!pcie) { - error("failed to allocate controller"); - continue; - } - - memset(pcie, 0, sizeof(*pcie)); - pcie->soc = soc; - - INIT_LIST_HEAD(&pcie->ports); - - err = tegra_pcie_parse_dt(fdt, nodes[i], pcie); - if (err < 0) { - free(pcie); - continue; - } - - err = tegra_pcie_power_on(pcie); - if (err < 0) { - error("failed to power on"); - continue; - } + struct tegra_pcie *pcie = dev_get_priv(dev); + enum tegra_pci_id id; - err = tegra_pcie_enable_controller(pcie); - if (err < 0) { - error("failed to enable controller"); - continue; - } - - tegra_pcie_setup_translations(pcie); - - err = tegra_pcie_enable(pcie); - if (err < 0) { - error("failed to enable PCIe"); - continue; - } + id = dev_get_driver_data(dev); + pcie->soc = &pci_tegra_soc[id]; - pcie->hose.first_busno = 0; - pcie->hose.current_busno = 0; - pcie->hose.last_busno = 0; + INIT_LIST_HEAD(&pcie->ports); - pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE, - NV_PA_SDRAM_BASE, pci_dram_size, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + if (tegra_pcie_parse_dt(gd->fdt_blob, dev->of_offset, id, pcie)) + return -EINVAL; - pci_set_region(&pcie->hose.regions[1], pcie->io.start, - pcie->io.start, fdt_resource_size(&pcie->io), - PCI_REGION_IO); - - pci_set_region(&pcie->hose.regions[2], pcie->mem.start, - pcie->mem.start, fdt_resource_size(&pcie->mem), - PCI_REGION_MEM); - - pci_set_region(&pcie->hose.regions[3], pcie->prefetch.start, - pcie->prefetch.start, - fdt_resource_size(&pcie->prefetch), - PCI_REGION_MEM | PCI_REGION_PREFETCH); + return 0; +} - pcie->hose.region_count = 4; +static int pci_tegra_probe(struct udevice *dev) +{ + struct tegra_pcie *pcie = dev_get_priv(dev); + int err; - pci_set_ops(&pcie->hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - tegra_pcie_read_conf, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - tegra_pcie_write_conf); + err = tegra_pcie_power_on(pcie); + if (err < 0) { + error("failed to power on"); + return err; + } - pci_register_hose(&pcie->hose); + err = tegra_pcie_enable_controller(pcie); + if (err < 0) { + error("failed to enable controller"); + return err; + } -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Enumerating devices...\n"); - printf("---------------------------------------\n"); - printf(" Device ID Description\n"); - printf(" ------ -- -----------\n"); -#endif + err = tegra_pcie_setup_translations(dev); + if (err < 0) { + error("failed to decode ranges"); + return err; + } - pcie->hose.last_busno = pci_hose_scan(&pcie->hose); + err = tegra_pcie_enable(pcie); + if (err < 0) { + error("failed to enable PCIe"); + return err; } return 0; } -void pci_init_board(void) -{ - const void *fdt = gd->fdt_blob; - int count, nodes[1]; +static const struct dm_pci_ops pci_tegra_ops = { + .read_config = pci_tegra_read_config, + .write_config = pci_tegra_write_config, +}; - tegra_pcie_board_init(); +static const struct udevice_id pci_tegra_ids[] = { + { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE }, + { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE }, + { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE }, + { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE }, + { } +}; - count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", - COMPAT_NVIDIA_TEGRA210_PCIE, - nodes, ARRAY_SIZE(nodes)); - if (process_nodes(fdt, nodes, count)) - return; - - count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", - COMPAT_NVIDIA_TEGRA124_PCIE, - nodes, ARRAY_SIZE(nodes)); - if (process_nodes(fdt, nodes, count)) - return; - - count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", - COMPAT_NVIDIA_TEGRA30_PCIE, - nodes, ARRAY_SIZE(nodes)); - if (process_nodes(fdt, nodes, count)) - return; - - count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", - COMPAT_NVIDIA_TEGRA20_PCIE, - nodes, ARRAY_SIZE(nodes)); - if (process_nodes(fdt, nodes, count)) - return; -} +U_BOOT_DRIVER(pci_tegra) = { + .name = "pci_tegra", + .id = UCLASS_PCI, + .of_match = pci_tegra_ids, + .ops = &pci_tegra_ops, + .ofdata_to_platdata = pci_tegra_ofdata_to_platdata, + .probe = pci_tegra_probe, + .priv_auto_alloc_size = sizeof(struct tegra_pcie), +}; int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) { diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 4cee038..58e88ae 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -11,8 +11,9 @@ #include <asm/io.h> #include <errno.h> #include <malloc.h> -#ifdef CONFIG_FSL_LAYERSCAPE +#ifndef CONFIG_LS102XA #include <asm/arch/fdt.h> +#include <asm/arch/soc.h> #endif #ifndef CONFIG_SYS_PCI_MEMORY_BUS @@ -57,11 +58,6 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C -/* LUT registers */ -#define PCIE_LUT_BASE 0x80000 -#define PCIE_LUT_LCTRL0 0x7F8 -#define PCIE_LUT_DBG 0x7FC - #define PCIE_DBI_RO_WR_EN 0x8bc #define PCIE_LINK_CAP 0x7c @@ -162,7 +158,7 @@ static int ls_pcie_link_state(struct ls_pcie *pcie) { u32 state; - state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) & + state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) & LTSSM_STATE_MASK; if (state < LTSSM_PCIE_L0) { debug("....PCIe link error. LTSSM=0x%02x.\n", state); @@ -466,16 +462,20 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info) for (pf = 0; pf < PCIE_PF_NUM; pf++) { for (vf = 0; vf <= PCIE_VF_NUM; vf++) { +#ifndef CONFIG_LS102XA writel(PCIE_LCTRL0_VAL(pf, vf), pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0); +#endif ls_pcie_ep_setup_bars(pcie->dbi); ls_pcie_ep_setup_atu(pcie, info); } } /* Disable CFG2 */ +#ifndef CONFIG_LS102XA writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0); +#endif } else { ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); ls_pcie_ep_setup_atu(pcie, info); @@ -665,7 +665,7 @@ void ft_pci_setup(void *blob, bd_t *bd) } #endif -#ifdef CONFIG_LS2085A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) void pcie_set_available_streamids(void *blob, const char *pcie_path, u32 *stream_ids, int count) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 3b6e3b7..57e6142 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -114,6 +114,15 @@ config ROCKCHIP_PINCTRL definitions and pin control functions for each available multiplex function. +config ROCKCHIP_3036_PINCTRL + bool "Rockchip rk3036 pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is + controlled by a device tree node which contains both the GPIO + definitions and pin control functions for each available multiplex + function. + config PINCTRL_SANDBOX bool "Sandbox pinctrl driver" depends on SANDBOX diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 251bace..6fa7d00 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -6,3 +6,4 @@ # obj-$(CONFIG_ROCKCHIP_PINCTRL) += pinctrl_rk3288.o +obj-$(CONFIG_ROCKCHIP_3036_PINCTRL) += pinctrl_rk3036.o diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c new file mode 100644 index 0000000..581b096 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c @@ -0,0 +1,276 @@ +/* + * Pinctrl driver for Rockchip 3036 SoCs + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3036.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <dm/pinctrl.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3036_pinctrl_priv { + struct rk3036_grf *grf; +}; + +static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id) +{ + switch (pwm_id) { + case PERIPH_ID_PWM0: + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK << GPIO0D2_SHIFT, + GPIO0D2_PWM0 << GPIO0D2_SHIFT); + break; + case PERIPH_ID_PWM1: + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK << GPIO0A0_SHIFT, + GPIO0A0_PWM1 << GPIO0A0_SHIFT); + break; + case PERIPH_ID_PWM2: + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK << GPIO0A1_SHIFT, + GPIO0A1_PWM2 << GPIO0A1_SHIFT); + break; + case PERIPH_ID_PWM3: + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK << GPIO0D3_SHIFT, + GPIO0D3_PWM3 << GPIO0D3_SHIFT); + break; + default: + debug("pwm id = %d iomux error!\n", pwm_id); + break; + } +} + +static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id) +{ + switch (i2c_id) { + case PERIPH_ID_I2C0: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A1_MASK << GPIO0A1_SHIFT | + GPIO0A0_MASK << GPIO0A0_SHIFT, + GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT | + GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT); + + break; + case PERIPH_ID_I2C1: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A3_MASK << GPIO0A3_SHIFT | + GPIO0A2_MASK << GPIO0A2_SHIFT, + GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT | + GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT); + break; + case PERIPH_ID_I2C2: + rk_clrsetreg(&grf->gpio2c_iomux, + GPIO2C5_MASK << GPIO2C5_SHIFT | + GPIO2C4_MASK << GPIO2C4_SHIFT, + GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT | + GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT); + + break; + } +} + +static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs) +{ + switch (cs) { + case 0: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D6_MASK << GPIO1D6_SHIFT, + GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT); + break; + case 1: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D7_MASK << GPIO1D7_SHIFT, + GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT); + break; + } + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D5_MASK << GPIO1D5_SHIFT | + GPIO1D4_MASK << GPIO1D4_SHIFT, + GPIO1D5_SPI_TXD << GPIO1D5_SHIFT | + GPIO1D4_SPI_RXD << GPIO1D4_SHIFT); + + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A0_MASK << GPIO2A0_SHIFT, + GPIO2A0_SPI_CLK << GPIO2A0_SHIFT); +} + +static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id) +{ + switch (uart_id) { + case PERIPH_ID_UART0: + rk_clrsetreg(&grf->gpio0c_iomux, + GPIO0C3_MASK << GPIO0C3_SHIFT | + GPIO0C2_MASK << GPIO0C2_SHIFT | + GPIO0C1_MASK << GPIO0C1_SHIFT | + GPIO0C0_MASK << GPIO0C0_SHIFT, + GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT | + GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT | + GPIO0C1_UART0_SIN << GPIO0C1_SHIFT | + GPIO0C0_UART0_SOUT << GPIO0C0_SHIFT); + break; + case PERIPH_ID_UART1: + rk_clrsetreg(&grf->gpio2c_iomux, + GPIO2C7_MASK << GPIO2C7_SHIFT | + GPIO2C6_MASK << GPIO2C6_SHIFT, + GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT | + GPIO2C6_UART1_SIN << GPIO2C6_SHIFT); + break; + case PERIPH_ID_UART2: + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C3_MASK << GPIO1C3_SHIFT | + GPIO1C2_MASK << GPIO1C2_SHIFT, + GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | + GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); + break; + } +} + +static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id) +{ + switch (mmc_id) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&grf->gpio1d_iomux, 0xffff, + GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT | + GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT | + GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT | + GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT | + GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT | + GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT | + GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT | + GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A4_MASK << GPIO2A4_SHIFT | + GPIO2A1_MASK << GPIO2A1_SHIFT, + GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT | + GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT); + break; + case PERIPH_ID_SDCARD: + rk_clrsetreg(&grf->gpio1c_iomux, 0xffff, + GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT | + GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT | + GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT | + GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT | + GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT | + GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT); + break; + } +} + +static int rk3036_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rk3036_pinctrl_priv *priv = dev_get_priv(dev); + + debug("%s: func=%x, flags=%x\n", __func__, func, flags); + switch (func) { + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + pinctrl_rk3036_pwm_config(priv->grf, func); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + pinctrl_rk3036_i2c_config(priv->grf, func); + break; + case PERIPH_ID_SPI0: + pinctrl_rk3036_spi_config(priv->grf, flags); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + pinctrl_rk3036_uart_config(priv->grf, func); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + pinctrl_rk3036_sdmmc_config(priv->grf, func); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk3036_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset, + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 14: + return PERIPH_ID_SDCARD; + case 16: + return PERIPH_ID_EMMC; + case 20: + return PERIPH_ID_UART0; + case 21: + return PERIPH_ID_UART1; + case 22: + return PERIPH_ID_UART2; + case 23: + return PERIPH_ID_SPI0; + case 24: + return PERIPH_ID_I2C0; + case 25: + return PERIPH_ID_I2C1; + case 26: + return PERIPH_ID_I2C2; + case 30: + return PERIPH_ID_PWM0; + } + return -ENOENT; +} + +static int rk3036_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rk3036_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + return rk3036_pinctrl_request(dev, func, 0); +} + +static struct pinctrl_ops rk3036_pinctrl_ops = { + .set_state_simple = rk3036_pinctrl_set_state_simple, + .request = rk3036_pinctrl_request, + .get_periph_id = rk3036_pinctrl_get_periph_id, +}; + +static int rk3036_pinctrl_probe(struct udevice *dev) +{ + struct rk3036_pinctrl_priv *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + debug("%s: grf=%p\n", __func__, priv->grf); + return 0; +} + +static const struct udevice_id rk3036_pinctrl_ids[] = { + { .compatible = "rockchip,rk3036-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3036) = { + .name = "pinctrl_rk3036", + .id = UCLASS_PINCTRL, + .of_match = rk3036_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv), + .ops = &rk3036_pinctrl_ops, + .probe = rk3036_pinctrl_probe, +}; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 809f8f1..e86dd72 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -8,7 +8,9 @@ choice prompt "Select Sunxi PMIC Variant" depends on ARCH_SUNXI default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I - default AXP221_POWER if MACH_SUN6I || MACH_SUN8I + default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 + default AXP818_POWER if MACH_SUN8I_A83T + default SUNXI_NO_PMIC if MACH_SUN8I_H3 config SUNXI_NO_PMIC boolean "board without a pmic" @@ -31,27 +33,37 @@ config AXP209_POWER config AXP221_POWER boolean "axp221 / axp223 pmic support" - depends on MACH_SUN6I || MACH_SUN8I + depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 ---help--- Select this to enable support for the axp221/axp223 pmic found on most A23 and A31 boards. +config AXP818_POWER + boolean "axp818 pmic support" + depends on MACH_SUN8I_A83T + ---help--- + Say y here to enable support for the axp818 pmic found on + A83T dev board. + endchoice config AXP_DCDC1_VOLT int "axp pmic dcdc1 voltage" - depends on AXP221_POWER + depends on AXP221_POWER || AXP818_POWER + default 3300 if AXP818_POWER default 3000 if MACH_SUN6I || MACH_SUN8I ---help--- Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for generic 3.3V IO voltage for external devices like the lcd-panal and sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to - safe battery. On A31 devices dcdc1 is also used for VCC-IO. + safe battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T + dcdc1 is used for VCC-IO, nand, usb0, sd , etc. config AXP_DCDC2_VOLT int "axp pmic dcdc2 voltage" - depends on AXP152_POWER || AXP209_POWER || AXP221_POWER + depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER + default 900 if AXP818_POWER default 1400 if AXP152_POWER || AXP209_POWER default 1200 if MACH_SUN6I default 1100 if MACH_SUN8I @@ -61,10 +73,12 @@ config AXP_DCDC2_VOLT On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V. On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V. On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V. + On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V. config AXP_DCDC3_VOLT int "axp pmic dcdc3 voltage" - depends on AXP152_POWER || AXP209_POWER || AXP221_POWER + depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER + default 900 if AXP818_POWER default 1500 if AXP152_POWER default 1250 if AXP209_POWER default 1200 if MACH_SUN6I || MACH_SUN8I @@ -75,10 +89,11 @@ config AXP_DCDC3_VOLT should be 1.25V. On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V. On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V. + On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V. config AXP_DCDC4_VOLT int "axp pmic dcdc4 voltage" - depends on AXP152_POWER || AXP221_POWER + depends on AXP152_POWER || AXP221_POWER || AXP818_POWER default 1250 if AXP152_POWER default 1200 if MACH_SUN6I default 0 if MACH_SUN8I @@ -88,15 +103,18 @@ config AXP_DCDC4_VOLT On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V. On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V. On A23 / A33 boards dcdc4 is unused and should be disabled. + On A83T boards dcdc4 is used for VDD-GPU. config AXP_DCDC5_VOLT int "axp pmic dcdc5 voltage" - depends on AXP221_POWER + depends on AXP221_POWER || AXP818_POWER + default 1800 if AXP818_POWER default 1500 if MACH_SUN6I || MACH_SUN8I ---help--- Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to disable dcdc5. - On A23 / A31 / A33 boards dcdc5 is VCC-DRAM and should be 1.5V. + On A23 / A31 / A33 / A83T boards dcdc5 is VCC-DRAM and should be 1.5V, + 1.8V for A83T. config AXP_ALDO1_VOLT int "axp pmic (a)ldo1 voltage" @@ -111,7 +129,7 @@ config AXP_ALDO1_VOLT config AXP_ALDO2_VOLT int "axp pmic (a)ldo2 voltage" - depends on AXP152_POWER || AXP209_POWER || AXP221_POWER + depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER default 3000 if AXP152_POWER || AXP209_POWER default 0 if MACH_SUN6I default 2500 if MACH_SUN8I @@ -125,14 +143,15 @@ config AXP_ALDO2_VOLT config AXP_ALDO3_VOLT int "axp pmic (a)ldo3 voltage" - depends on AXP209_POWER || AXP221_POWER - default 0 if AXP209_POWER + depends on AXP209_POWER || AXP221_POWER || AXP818_POWER + default 0 if AXP209_POWER || AXP818_POWER default 3000 if MACH_SUN6I || MACH_SUN8I ---help--- Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to disable aldo3. On A10(s) / A13 / A20 boards aldo3 should be 2.8V. On A23 / A31 / A33 boards aldo3 is VCC-PLL and AVCC and should be 3.0V. + On A83T aldo3 is used for LVDS, DSI, MIPI, HDMI, etc. config AXP_ALDO4_VOLT int "axp pmic (a)ldo4 voltage" @@ -171,7 +190,7 @@ config AXP_DLDO3_VOLT config AXP_DLDO4_VOLT int "axp pmic dldo4 voltage" - depends on AXP221_POWER + depends on AXP221_POWER || AXP818_POWER default 0 ---help--- Set the voltage (mV) to program the axp pmic dldo4 at, set to 0 to diff --git a/drivers/power/Makefile b/drivers/power/Makefile index a2d3c04..0fdbca3 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_AS3722_POWER) += as3722.o obj-$(CONFIG_AXP152_POWER) += axp152.o obj-$(CONFIG_AXP209_POWER) += axp209.o obj-$(CONFIG_AXP221_POWER) += axp221.o +obj-$(CONFIG_AXP818_POWER) += axp818.o obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c new file mode 100644 index 0000000..4b21a83 --- /dev/null +++ b/drivers/power/axp818.c @@ -0,0 +1,132 @@ +/* + * AXP818 driver based on AXP221 driver + * + * + * (C) Copyright 2015 Vishnu Patekar <vishnuptekar0510@gmail.com> + * + * Based on axp221.c + * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> + * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pmic_bus.h> +#include <axp_pmic.h> + +static u8 axp818_mvolt_to_cfg(int mvolt, int min, int max, int div) +{ + if (mvolt < min) + mvolt = min; + else if (mvolt > max) + mvolt = max; + + return (mvolt - min) / div; +} + +int axp_set_dcdc1(unsigned int mvolt) +{ + int ret; + u8 cfg = axp818_mvolt_to_cfg(mvolt, 1600, 3400, 100); + + if (mvolt == 0) + return pmic_bus_clrbits(AXP818_OUTPUT_CTRL1, + AXP818_OUTPUT_CTRL1_DCDC1_EN); + + ret = pmic_bus_write(AXP818_DCDC1_CTRL, cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP818_OUTPUT_CTRL1, + AXP818_OUTPUT_CTRL1_DCDC1_EN); +} + +int axp_set_dcdc2(unsigned int mvolt) +{ + int ret; + u8 cfg; + + if (mvolt >= 1220) + cfg = 70 + axp818_mvolt_to_cfg(mvolt, 1220, 1300, 20); + else + cfg = axp818_mvolt_to_cfg(mvolt, 500, 1200, 10); + + if (mvolt == 0) + return pmic_bus_clrbits(AXP818_OUTPUT_CTRL1, + AXP818_OUTPUT_CTRL1_DCDC2_EN); + + ret = pmic_bus_write(AXP818_DCDC2_CTRL, cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP818_OUTPUT_CTRL1, + AXP818_OUTPUT_CTRL1_DCDC2_EN); +} + +int axp_set_dcdc3(unsigned int mvolt) +{ + int ret; + u8 cfg; + + if (mvolt >= 1220) + cfg = 70 + axp818_mvolt_to_cfg(mvolt, 1220, 1300, 20); + else + cfg = axp818_mvolt_to_cfg(mvolt, 500, 1200, 10); + + if (mvolt == 0) + return pmic_bus_clrbits(AXP818_OUTPUT_CTRL1, + AXP818_OUTPUT_CTRL1_DCDC3_EN); + + ret = pmic_bus_write(AXP818_DCDC3_CTRL, cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP818_OUTPUT_CTRL1, + AXP818_OUTPUT_CTRL1_DCDC3_EN); +} + +int axp_set_dcdc5(unsigned int mvolt) +{ + int ret; + u8 cfg; + + if (mvolt >= 1140) + cfg = 32 + axp818_mvolt_to_cfg(mvolt, 1140, 1840, 20); + else + cfg = axp818_mvolt_to_cfg(mvolt, 800, 1120, 10); + + if (mvolt == 0) + return pmic_bus_clrbits(AXP818_OUTPUT_CTRL1, + AXP818_OUTPUT_CTRL1_DCDC5_EN); + + ret = pmic_bus_write(AXP818_DCDC5_CTRL, cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP818_OUTPUT_CTRL1, + AXP818_OUTPUT_CTRL1_DCDC5_EN); +} + +int axp_init(void) +{ + u8 axp_chip_id; + int ret; + + ret = pmic_bus_init(); + if (ret) + return ret; + + ret = pmic_bus_read(AXP818_CHIP_ID, &axp_chip_id); + if (ret) + return ret; + + if (!(axp_chip_id == 0x51)) + return -ENODEV; + else + return ret; + + return 0; +} diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index a421e12..200cf61 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -66,7 +66,7 @@ static int _rproc_name_is_unique(struct udevice *dev, const char *check_name = data; /* devices not yet populated with data - so skip them */ - if (!uc_pdata->name && check_name) + if (!uc_pdata->name || !check_name) return 0; /* Return 0 to search further if we dont match */ diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index eba96f4..1fc287e 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -53,6 +53,7 @@ config DEBUG_UART choice prompt "Select which UART will provide the debug UART" depends on DEBUG_UART + default DEBUG_UART_NS16550 config DEBUG_UART_ALTERA_JTAGUART bool "Altera JTAG UART" @@ -94,7 +95,7 @@ config DEBUG_UART_S5P config DEBUG_UART_ZYNQ bool "Xilinx Zynq" help - Select this to enable a debug UART using the serial_s5p driver. You + Select this to enable a debug UART using the serial_zynq driver. You will need to provide parameters to make this work. The driver will be available until the real driver-model serial is running. @@ -185,14 +186,15 @@ config ALTERA_UART Select this to enable an UART for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. -config ROCKCHIP_SERIAL - bool "Rockchip on-chip UART support" - depends on ARCH_ROCKCHIP && DM_SERIAL +config SYS_NS16550 + bool "NS16550 UART or compatible" help - Select this to enable a debug UART for Rockchip devices. This uses - the ns16550 driver. You will need to #define CONFIG_SYS_NS16550 in - your board config header. The clock input is automatically set to - use the oscillator (24MHz). + Support NS16550 UART or compatible. This can be enabled in the + device tree with the correct input clock frequency. If the input + clock frequency is not defined in the device tree, the macro + CONFIG_SYS_NS16550_CLK defined in a legacy board header file will + be used. It can be a constant or a function to get clock, eg, + get_serial_clock(). config SANDBOX_SERIAL bool "Sandbox UART support" @@ -221,14 +223,4 @@ config UNIPHIER_SERIAL If you have a UniPhier based board and want to use the on-chip serial ports, say Y to this option. If unsure, say N. -config X86_SERIAL - bool "Support for 16550 serial port on x86 machines" - depends on X86 - default y - help - Most x86 machines have a ns16550 UART or compatible. This can be - enabled in the device tree with the correct input clock frequency - provided (default 1843200). Enable this to obtain serial console - output. - endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 1818c7c..dd87147 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -8,7 +8,6 @@ ifdef CONFIG_DM_SERIAL obj-y += serial-uclass.o obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o -obj-$(CONFIG_PPC) += serial_ppc.o else obj-y += serial.o obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o @@ -20,12 +19,10 @@ obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o -obj-$(CONFIG_DW_SERIAL) += serial_dw.o obj-$(CONFIG_EFI_APP) += serial_efi.o obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += mcfuart.o obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o -obj-$(CONFIG_KEYSTONE_SERIAL) += serial_keystone.o obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P) += serial_s5p.o obj-$(CONFIG_IMX_SERIAL) += serial_imx.o @@ -41,12 +38,8 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o obj-$(CONFIG_MXS_AUART) += mxs_auart.o -obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o -obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o -obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o -obj-$(CONFIG_X86_SERIAL) += serial_x86.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o ifndef CONFIG_SPL_BUILD diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 6433844..3fab3f1 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -8,7 +8,6 @@ #include <dm.h> #include <errno.h> #include <fdtdec.h> -#include <mapmem.h> #include <ns16550.h> #include <serial.h> #include <watchdog.h> @@ -57,6 +56,10 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_DM_SERIAL +#ifndef CONFIG_SYS_NS16550_CLK +#define CONFIG_SYS_NS16550_CLK 0 +#endif + static inline void serial_out_shift(void *addr, int shift, int value) { #ifdef CONFIG_SYS_NS16550_PORT_MAPPED @@ -97,7 +100,7 @@ static void ns16550_writeb(NS16550_t port, int offset, int value) unsigned char *addr; offset *= 1 << plat->reg_shift; - addr = map_sysmem(plat->base, 0) + offset; + addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset; /* * As far as we know it doesn't make sense to support selection of * these options at run-time, so use the existing CONFIG options. @@ -111,7 +114,7 @@ static int ns16550_readb(NS16550_t port, int offset) unsigned char *addr; offset *= 1 << plat->reg_shift; - addr = map_sysmem(plat->base, 0) + offset; + addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset; return serial_in_shift(addr, plat->reg_shift); } @@ -400,7 +403,14 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) plat->base = addr; plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset, - "reg-shift", 1); + "reg-shift", 0); + plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", + CONFIG_SYS_NS16550_CLK); + if (!plat->clock) { + debug("ns16550 clock not defined\n"); + return -EINVAL; + } return 0; } @@ -412,4 +422,35 @@ const struct dm_serial_ops ns16550_serial_ops = { .getc = ns16550_serial_getc, .setbrg = ns16550_serial_setbrg, }; + +#if CONFIG_IS_ENABLED(OF_CONTROL) +static const struct udevice_id ns16550_serial_ids[] = { + { .compatible = "ns16550" }, + { .compatible = "ns16550a" }, + { .compatible = "nvidia,tegra20-uart" }, + { .compatible = "rockchip,rk3036-uart" }, + { .compatible = "snps,dw-apb-uart" }, + { .compatible = "ti,omap2-uart" }, + { .compatible = "ti,omap3-uart" }, + { .compatible = "ti,omap4-uart" }, + { .compatible = "ti,am3352-uart" }, + { .compatible = "ti,am4372-uart" }, + { .compatible = "ti,dra742-uart" }, + {} +}; +#endif + +U_BOOT_DRIVER(ns16550_serial) = { + .name = "ns16550_serial", + .id = UCLASS_SERIAL, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .of_match = ns16550_serial_ids, + .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), +#endif + .priv_auto_alloc_size = sizeof(struct NS16550), + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; #endif /* CONFIG_DM_SERIAL */ diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 842f78b..4bf9a5c 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -64,9 +64,9 @@ static void serial_find_console_or_panic(void) } /* - * If the console is not marked to be bound before relocation, - * bind it anyway. - */ + * If the console is not marked to be bound before relocation, + * bind it anyway. + */ if (node > 0 && !lists_bind_fdt(gd->dm_root, blob, node, &dev)) { if (!device_probe(dev)) { @@ -77,13 +77,13 @@ static void serial_find_console_or_panic(void) } if (!SPL_BUILD || !CONFIG_IS_ENABLED(OF_CONTROL) || !blob) { /* - * Try to use CONFIG_CONS_INDEX if available (it is numbered - * from 1!). - * - * Failing that, get the device with sequence number 0, or in - * extremis just the first serial device we can find. But we - * insist on having a console (even if it is silent). - */ + * Try to use CONFIG_CONS_INDEX if available (it is numbered + * from 1!). + * + * Failing that, get the device with sequence number 0, or in + * extremis just the first serial device we can find. But we + * insist on having a console (even if it is silent). + */ #ifdef CONFIG_CONS_INDEX #define INDEX (CONFIG_CONS_INDEX - 1) #else diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 422d3ae..f1bd15b 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -527,7 +527,7 @@ static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE; * * Do a loopback test of the currently selected serial port. This * function is only useful in the context of the POST testing framwork. - * The serial port is firstly configured into loopback mode and then + * The serial port is first configured into loopback mode and then * characters are sent through it. * * Returns 0 on success, value otherwise. diff --git a/drivers/serial/serial_dw.c b/drivers/serial/serial_dw.c deleted file mode 100644 index a348f29..0000000 --- a/drivers/serial/serial_dw.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2014 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <ns16550.h> -#include <serial.h> - -static const struct udevice_id dw_serial_ids[] = { - { .compatible = "snps,dw-apb-uart" }, - { } -}; - -static int dw_serial_ofdata_to_platdata(struct udevice *dev) -{ - struct ns16550_platdata *plat = dev_get_platdata(dev); - int ret; - - ret = ns16550_serial_ofdata_to_platdata(dev); - if (ret) - return ret; - plat->clock = CONFIG_SYS_NS16550_CLK; - - return 0; -} - -U_BOOT_DRIVER(serial_ns16550) = { - .name = "serial_dw", - .id = UCLASS_SERIAL, - .of_match = dw_serial_ids, - .ofdata_to_platdata = dw_serial_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), - .priv_auto_alloc_size = sizeof(struct NS16550), - .probe = ns16550_serial_probe, - .ops = &ns16550_serial_ops, -}; diff --git a/drivers/serial/serial_keystone.c b/drivers/serial/serial_keystone.c deleted file mode 100644 index 7b5ab6c..0000000 --- a/drivers/serial/serial_keystone.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2015 Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <fdtdec.h> -#include <ns16550.h> -#include <serial.h> -#include <asm/arch/clock.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if CONFIG_IS_ENABLED(OF_CONTROL) -static const struct udevice_id keystone_serial_ids[] = { - { .compatible = "ti,keystone-uart" }, - { .compatible = "ns16550a" }, - { } -}; - -static int keystone_serial_ofdata_to_platdata(struct udevice *dev) -{ - struct ns16550_platdata *plat = dev_get_platdata(dev); - int ret; - - ret = ns16550_serial_ofdata_to_platdata(dev); - if (ret) - return ret; - plat->clock = CONFIG_SYS_NS16550_CLK; - return 0; -} -#endif - -U_BOOT_DRIVER(serial_keystone_ns16550) = { - .name = "serial_keystone", - .id = UCLASS_SERIAL, -#if CONFIG_IS_ENABLED(OF_CONTROL) - .of_match = of_match_ptr(keystone_serial_ids), - .ofdata_to_platdata = of_match_ptr(keystone_serial_ofdata_to_platdata), - .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), -#endif - .priv_auto_alloc_size = sizeof(struct NS16550), - .probe = ns16550_serial_probe, - .ops = &ns16550_serial_ops, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c deleted file mode 100644 index 891cd7b..0000000 --- a/drivers/serial/serial_omap.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2014 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <fdtdec.h> -#include <ns16550.h> -#include <serial.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */ - -#if CONFIG_IS_ENABLED(OF_CONTROL) -static const struct udevice_id omap_serial_ids[] = { - { .compatible = "ti,omap2-uart" }, - { .compatible = "ti,omap3-uart" }, - { .compatible = "ti,omap4-uart" }, - { .compatible = "ti,am3352-uart" }, - { .compatible = "ti,am4372-uart" }, - { .compatible = "ti,dra742-uart" }, - { } -}; - -static int omap_serial_ofdata_to_platdata(struct udevice *dev) -{ - struct ns16550_platdata *plat = dev_get_platdata(dev); - int ret; - - ret = ns16550_serial_ofdata_to_platdata(dev); - if (ret) - return ret; - plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, - "clock-frequency", DEFAULT_CLK_SPEED); - plat->reg_shift = 2; - - return 0; -} -#endif - -U_BOOT_DRIVER(serial_omap_ns16550) = { - .name = "serial_omap", - .id = UCLASS_SERIAL, - .of_match = of_match_ptr(omap_serial_ids), - .ofdata_to_platdata = of_match_ptr(omap_serial_ofdata_to_platdata), - .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), - .priv_auto_alloc_size = sizeof(struct NS16550), - .probe = ns16550_serial_probe, - .ops = &ns16550_serial_ops, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/serial/serial_ppc.c b/drivers/serial/serial_ppc.c deleted file mode 100644 index 47141c6..0000000 --- a/drivers/serial/serial_ppc.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2014 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <ns16550.h> -#include <serial.h> - -static const struct udevice_id ppc_serial_ids[] = { - { .compatible = "ns16550" }, - { } -}; - -static int ppc_serial_ofdata_to_platdata(struct udevice *dev) -{ - struct ns16550_platdata *plat = dev_get_platdata(dev); - int ret; - - ret = ns16550_serial_ofdata_to_platdata(dev); - if (ret) - return ret; - plat->clock = get_serial_clock(); - - return 0; -} - -U_BOOT_DRIVER(serial_ns16550) = { - .name = "serial_ppc", - .id = UCLASS_SERIAL, - .of_match = ppc_serial_ids, - .ofdata_to_platdata = ppc_serial_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), - .priv_auto_alloc_size = sizeof(struct NS16550), - .probe = ns16550_serial_probe, - .ops = &ns16550_serial_ops, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c deleted file mode 100644 index 0e7bbfc..0000000 --- a/drivers/serial/serial_rockchip.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <ns16550.h> -#include <serial.h> -#include <asm/arch/clock.h> - -static const struct udevice_id rockchip_serial_ids[] = { - { .compatible = "rockchip,rk3288-uart" }, - { } -}; - -static int rockchip_serial_ofdata_to_platdata(struct udevice *dev) -{ - struct ns16550_platdata *plat = dev_get_platdata(dev); - int ret; - - ret = ns16550_serial_ofdata_to_platdata(dev); - if (ret) - return ret; - - /* Do all Rockchip parts use 24MHz? */ - plat->clock = 24 * 1000000; - - return 0; -} - -U_BOOT_DRIVER(serial_ns16550) = { - .name = "serial_rockchip", - .id = UCLASS_SERIAL, - .of_match = rockchip_serial_ids, - .ofdata_to_platdata = rockchip_serial_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), - .priv_auto_alloc_size = sizeof(struct NS16550), - .probe = ns16550_serial_probe, - .ops = &ns16550_serial_ops, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 8b2830b..91a5dde 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -1,45 +1,18 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> #include <asm/io.h> #include <serial.h> #include <asm/arch/stm32.h> +#include <dm/platform_data/serial_stm32.h> -/* - * Set up the usart port - */ -#if (CONFIG_STM32_USART >= 1) && (CONFIG_STM32_USART <= 6) -#define USART_PORT (CONFIG_STM32_USART - 1) -#else -#define USART_PORT 0 -#endif -/* - * Set up the usart base address - * - * --STM32_USARTD_BASE means default setting - */ -#define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000) -#define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400) -#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800) -#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400) -#define STM32_USARTD_BASE STM32_USART1_BASE -/* - * RCC USART specific definitions - * - * --RCC_ENR_USARTDEN means default setting - */ -#define RCC_ENR_USART1EN (1 << 4) -#define RCC_ENR_USART2EN (1 << 17) -#define RCC_ENR_USART3EN (1 << 18) -#define RCC_ENR_USART6EN (1 << 5) -#define RCC_ENR_USARTDEN RCC_ENR_USART1EN - -struct stm32_serial { +struct stm32_usart { u32 sr; u32 dr; u32 brr; @@ -49,120 +22,136 @@ struct stm32_serial { u32 gtpr; }; -#define USART_CR1_RE (1 << 2) -#define USART_CR1_TE (1 << 3) -#define USART_CR1_UE (1 << 13) +#define USART_CR1_RE (1 << 2) +#define USART_CR1_TE (1 << 3) +#define USART_CR1_UE (1 << 13) #define USART_SR_FLAG_RXNE (1 << 5) -#define USART_SR_FLAG_TXE (1 << 7) +#define USART_SR_FLAG_TXE (1 << 7) -#define USART_BRR_F_MASK 0xF +#define USART_BRR_F_MASK 0xF #define USART_BRR_M_SHIFT 4 #define USART_BRR_M_MASK 0xFFF0 DECLARE_GLOBAL_DATA_PTR; -static const unsigned long usart_base[] = { - STM32_USART1_BASE, - STM32_USART2_BASE, - STM32_USART3_BASE, - STM32_USARTD_BASE, - STM32_USARTD_BASE, - STM32_USART6_BASE -}; +#define MAX_SERIAL_PORTS 4 -static const unsigned long rcc_enr_en[] = { - RCC_ENR_USART1EN, - RCC_ENR_USART2EN, - RCC_ENR_USART3EN, - RCC_ENR_USARTDEN, - RCC_ENR_USARTDEN, - RCC_ENR_USART6EN +/* + * RCC USART specific definitions + */ +#define RCC_ENR_USART1EN (1 << 4) +#define RCC_ENR_USART2EN (1 << 17) +#define RCC_ENR_USART3EN (1 << 18) +#define RCC_ENR_USART6EN (1 << 5) + +/* Array used to figure out which RCC bit needs to be set */ +static const unsigned long usart_port_rcc_pairs[MAX_SERIAL_PORTS][2] = { + { STM32_USART1_BASE, RCC_ENR_USART1EN }, + { STM32_USART2_BASE, RCC_ENR_USART2EN }, + { STM32_USART3_BASE, RCC_ENR_USART3EN }, + { STM32_USART6_BASE, RCC_ENR_USART6EN } }; -static void stm32_serial_setbrg(void) +static int stm32_serial_setbrg(struct udevice *dev, int baudrate) { - serial_init(); -} + struct stm32_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + u32 clock, int_div, frac_div, tmp; -static int stm32_serial_init(void) -{ - struct stm32_serial *usart = - (struct stm32_serial *)usart_base[USART_PORT]; - u32 clock, int_div, frac_div, tmp; - - if ((usart_base[USART_PORT] & STM32_BUS_MASK) == - STM32_APB1PERIPH_BASE) { - setbits_le32(&STM32_RCC->apb1enr, rcc_enr_en[USART_PORT]); + if (((u32)usart & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE) clock = clock_get(CLOCK_APB1); - } else if ((usart_base[USART_PORT] & STM32_BUS_MASK) == - STM32_APB2PERIPH_BASE) { - setbits_le32(&STM32_RCC->apb2enr, rcc_enr_en[USART_PORT]); + else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE) clock = clock_get(CLOCK_APB2); - } else { - return -1; - } + else + return -EINVAL; - int_div = (25 * clock) / (4 * gd->baudrate); + int_div = (25 * clock) / (4 * baudrate); tmp = ((int_div / 100) << USART_BRR_M_SHIFT) & USART_BRR_M_MASK; frac_div = int_div - (100 * (tmp >> USART_BRR_M_SHIFT)); tmp |= (((frac_div * 16) + 50) / 100) & USART_BRR_F_MASK; - writel(tmp, &usart->brr); - setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); return 0; } -static int stm32_serial_getc(void) +static int stm32_serial_getc(struct udevice *dev) { - struct stm32_serial *usart = - (struct stm32_serial *)usart_base[USART_PORT]; - while ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0) - ; + struct stm32_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + + if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0) + return -EAGAIN; + return readl(&usart->dr); } -static void stm32_serial_putc(const char c) +static int stm32_serial_putc(struct udevice *dev, const char c) { - struct stm32_serial *usart = - (struct stm32_serial *)usart_base[USART_PORT]; + struct stm32_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; - if (c == '\n') - stm32_serial_putc('\r'); + if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0) + return -EAGAIN; - while ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0) - ; writel(c, &usart->dr); + + return 0; } -static int stm32_serial_tstc(void) +static int stm32_serial_pending(struct udevice *dev, bool input) { - struct stm32_serial *usart = - (struct stm32_serial *)usart_base[USART_PORT]; - u8 ret; + struct stm32_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; - ret = readl(&usart->sr) & USART_SR_FLAG_RXNE; - return ret; + if (input) + return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0; + else + return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1; } -static struct serial_device stm32_serial_drv = { - .name = "stm32_serial", - .start = stm32_serial_init, - .stop = NULL, - .setbrg = stm32_serial_setbrg, - .putc = stm32_serial_putc, - .puts = default_serial_puts, - .getc = stm32_serial_getc, - .tstc = stm32_serial_tstc, -}; - -void stm32_serial_initialize(void) +static int stm32_serial_probe(struct udevice *dev) { - serial_register(&stm32_serial_drv); -} + struct stm32_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + int usart_port = -1; + int i; + + for (i = 0; i < MAX_SERIAL_PORTS; i++) { + if ((u32)usart == usart_port_rcc_pairs[i][0]) { + usart_port = i; + break; + } + } -__weak struct serial_device *default_serial_console(void) -{ - return &stm32_serial_drv; + if (usart_port == -1) + return -EINVAL; + + if (((u32)usart & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE) + setbits_le32(&STM32_RCC->apb1enr, + usart_port_rcc_pairs[usart_port][1]); + else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE) + setbits_le32(&STM32_RCC->apb2enr, + usart_port_rcc_pairs[usart_port][1]); + else + return -EINVAL; + + setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); + + return 0; } + +static const struct dm_serial_ops stm32_serial_ops = { + .putc = stm32_serial_putc, + .pending = stm32_serial_pending, + .getc = stm32_serial_getc, + .setbrg = stm32_serial_setbrg, +}; + +U_BOOT_DRIVER(serial_stm32) = { + .name = "serial_stm32", + .id = UCLASS_SERIAL, + .ops = &stm32_serial_ops, + .probe = stm32_serial_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/serial_tegra.c b/drivers/serial/serial_tegra.c deleted file mode 100644 index 0c84f0b..0000000 --- a/drivers/serial/serial_tegra.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2014 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <ns16550.h> -#include <serial.h> - -#if CONFIG_IS_ENABLED(OF_CONTROL) -static const struct udevice_id tegra_serial_ids[] = { - { .compatible = "nvidia,tegra20-uart" }, - { } -}; - -static int tegra_serial_ofdata_to_platdata(struct udevice *dev) -{ - struct ns16550_platdata *plat = dev_get_platdata(dev); - int ret; - - ret = ns16550_serial_ofdata_to_platdata(dev); - if (ret) - return ret; - plat->clock = V_NS16550_CLK; - - return 0; -} -#else -struct ns16550_platdata tegra_serial = { - .base = CONFIG_SYS_NS16550_COM1, - .reg_shift = 2, - .clock = V_NS16550_CLK, -}; - -U_BOOT_DEVICE(ns16550_serial) = { - "serial_tegra20", &tegra_serial -}; -#endif - -U_BOOT_DRIVER(serial_ns16550) = { - .name = "serial_tegra20", - .id = UCLASS_SERIAL, -#if CONFIG_IS_ENABLED(OF_CONTROL) - .of_match = tegra_serial_ids, - .ofdata_to_platdata = tegra_serial_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), -#endif - .priv_auto_alloc_size = sizeof(struct NS16550), - .probe = ns16550_serial_probe, - .ops = &ns16550_serial_ops, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/serial/serial_x86.c b/drivers/serial/serial_x86.c deleted file mode 100644 index 4bf6062..0000000 --- a/drivers/serial/serial_x86.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2014 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <fdtdec.h> -#include <ns16550.h> -#include <serial.h> - -DECLARE_GLOBAL_DATA_PTR; - -static const struct udevice_id x86_serial_ids[] = { - { .compatible = "x86-uart" }, - { } -}; - -static int x86_serial_ofdata_to_platdata(struct udevice *dev) -{ - struct ns16550_platdata *plat = dev_get_platdata(dev); - int ret; - - ret = ns16550_serial_ofdata_to_platdata(dev); - if (ret) - return ret; - - plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, - "clock-frequency", 1843200); - - return 0; -} - -U_BOOT_DRIVER(serial_ns16550) = { - .name = "serial_x86", - .id = UCLASS_SERIAL, - .of_match = x86_serial_ids, - .ofdata_to_platdata = x86_serial_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), - .priv_auto_alloc_size = sizeof(struct NS16550), - .probe = ns16550_serial_probe, - .ops = &ns16550_serial_ops, -}; diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 88bebed..b2b98de 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -180,7 +180,7 @@ static const struct udevice_id zynq_serial_ids[] = { { } }; -U_BOOT_DRIVER(serial_s5p) = { +U_BOOT_DRIVER(serial_zynq) = { .name = "serial_zynq", .id = UCLASS_SERIAL, .of_match = zynq_serial_ids, @@ -192,9 +192,6 @@ U_BOOT_DRIVER(serial_s5p) = { }; #ifdef CONFIG_DEBUG_UART_ZYNQ - -#include <debug_uart.h> - void _debug_uart_init(void) { struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a0dbd8b..2cdb110 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -140,7 +140,7 @@ config XILINX_SPI config ZYNQ_SPI bool "Zynq SPI driver" - depends on ARCH_ZYNQ || TARGET_XILINX_ZYNQMP + depends on ARCH_ZYNQ || ARCH_ZYNQMP help Enable the Zynq SPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Zynq diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index ed39114..feec3e8 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -13,6 +13,7 @@ #include <linux/sizes.h> #include <dm.h> #include <errno.h> +#include <watchdog.h> #include "fsl_qspi.h" DECLARE_GLOBAL_DATA_PTR; @@ -527,6 +528,8 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) to_or_from = priv->sf_addr + priv->cur_amba_base; while (len > 0) { + WATCHDOG_RESET(); + qspi_write32(priv->flags, ®s->sfar, to_or_from); size = (len > RX_BUFFER_SIZE) ? @@ -574,6 +577,8 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) status_reg = 0; while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) { + WATCHDOG_RESET(); + qspi_write32(priv->flags, ®s->ipcr, (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 3c7d64a..e0f6b25 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -378,6 +378,8 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, mode |= SPI_CPHA; if (fdtdec_get_bool(blob, node, "spi-cs-high")) mode |= SPI_CS_HIGH; + if (fdtdec_get_bool(blob, node, "spi-3wire")) + mode |= SPI_3WIRE; if (fdtdec_get_bool(blob, node, "spi-half-duplex")) mode |= SPI_PREAMBLE; plat->mode = mode; diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 646dd89..5747ed1 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -293,7 +293,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, qslave->cmd = 0; qslave->cmd |= QSPI_WLEN(8); qslave->cmd |= QSPI_EN_CS(slave->cs); - if (flags & SPI_3WIRE) + if (qslave->mode & SPI_3WIRE) qslave->cmd |= QSPI_3_PIN; qslave->cmd |= 0xfff; diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 0713714..a951a77 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -287,7 +287,8 @@ static const struct dm_spi_ops xilinx_spi_ops = { }; static const struct udevice_id xilinx_spi_ids[] = { - { .compatible = "xlnx,xilinx-spi" }, + { .compatible = "xlnx,xps-spi-2.00.a" }, + { .compatible = "xlnx,xps-spi-2.00.b" }, { } }; diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 5825c6d..b98663c 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -30,6 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ +#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */ /* zynq qspi Transmit Data Register */ #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */ @@ -68,6 +69,9 @@ struct zynq_qspi_regs { u32 txd1r; /* 0x80 */ u32 txd2r; /* 0x84 */ u32 txd3r; /* 0x88 */ + u32 reserved1[5]; + u32 lqspicfg; /* 0xA0 */ + u32 lqspists; /* 0xA4 */ }; /* zynq qspi platform data */ @@ -143,6 +147,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) ZYNQ_QSPI_CR_MSTREN_MASK; writel(confr, ®s->cr); + /* Disable the LQSPI feature */ + confr = readl(®s->lqspicfg); + confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK; + writel(confr, ®s->lqspicfg); + /* Enable SPI */ writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); } diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 6ed2165..09ae1be 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -313,6 +313,7 @@ static const struct dm_spi_ops zynq_spi_ops = { static const struct udevice_id zynq_spi_ids[] = { { .compatible = "xlnx,zynq-spi-r1p6" }, + { .compatible = "cdns,spi-r1p6" }, { } }; diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 601e493..2b10d2b 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -1,26 +1,33 @@ menu "Timer Support" config TIMER - bool "Enable Driver Model for Timer drivers" + bool "Enable driver model for timer drivers" depends on DM help - Enable driver model for Timer access. It uses the same API as - lib/time.c. But now implemented by the uclass. The first timer + Enable driver model for timer access. It uses the same API as + lib/time.c, but now implemented by the uclass. The first timer will be used. The timer is usually a 32 bits free-running up counter. There may be no real tick, and no timer interrupt. config ALTERA_TIMER - bool "Altera Timer support" + bool "Altera timer support" depends on TIMER help - Select this to enable an timer for Altera devices. Please find + Select this to enable a timer for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. config SANDBOX_TIMER - bool "Sandbox Timer support" + bool "Sandbox timer support" depends on SANDBOX && TIMER help Select this to enable an emulated timer for sandbox. It gets time from host os. +config X86_TSC_TIMER + bool "x86 Time-Stamp Counter (TSC) timer support" + depends on TIMER && X86 + default y if X86 + help + Select this to enable Time-Stamp Counter (TSC) timer for x86. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 300946e..fe954ec 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_TIMER) += timer-uclass.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o +obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o diff --git a/drivers/timer/altera_timer.c b/drivers/timer/altera_timer.c index 971ed38..89fe05b 100644 --- a/drivers/timer/altera_timer.c +++ b/drivers/timer/altera_timer.c @@ -32,10 +32,9 @@ struct altera_timer_regs { struct altera_timer_platdata { struct altera_timer_regs *regs; - unsigned long clock_rate; }; -static int altera_timer_get_count(struct udevice *dev, unsigned long *count) +static int altera_timer_get_count(struct udevice *dev, u64 *count) { struct altera_timer_platdata *plat = dev->platdata; struct altera_timer_regs *const regs = plat->regs; @@ -47,19 +46,16 @@ static int altera_timer_get_count(struct udevice *dev, unsigned long *count) /* Read timer value */ val = readl(®s->snapl) & 0xffff; val |= (readl(®s->snaph) & 0xffff) << 16; - *count = ~val; + *count = timer_conv_64(~val); return 0; } static int altera_timer_probe(struct udevice *dev) { - struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct altera_timer_platdata *plat = dev->platdata; struct altera_timer_regs *const regs = plat->regs; - uc_priv->clock_rate = plat->clock_rate; - writel(0, ®s->status); writel(0, ®s->control); writel(ALTERA_TIMER_STOP, ®s->control); @@ -78,8 +74,6 @@ static int altera_timer_ofdata_to_platdata(struct udevice *dev) plat->regs = map_physmem(dev_get_addr(dev), sizeof(struct altera_timer_regs), MAP_NOCACHE); - plat->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset, - "clock-frequency", 0); return 0; } diff --git a/drivers/timer/sandbox_timer.c b/drivers/timer/sandbox_timer.c index 38de763..00a9944 100644 --- a/drivers/timer/sandbox_timer.c +++ b/drivers/timer/sandbox_timer.c @@ -18,7 +18,7 @@ void sandbox_timer_add_offset(unsigned long offset) sandbox_timer_offset += offset; } -static int sandbox_timer_get_count(struct udevice *dev, unsigned long *count) +static int sandbox_timer_get_count(struct udevice *dev, u64 *count) { *count = os_get_nsec() / 1000 + sandbox_timer_offset * 1000; @@ -27,10 +27,6 @@ static int sandbox_timer_get_count(struct udevice *dev, unsigned long *count) static int sandbox_timer_probe(struct udevice *dev) { - struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); - - uc_priv->clock_rate = 1000000; - return 0; } diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index 12aee5b..aca421b 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -9,16 +9,18 @@ #include <errno.h> #include <timer.h> +DECLARE_GLOBAL_DATA_PTR; + /* - * Implement a Timer uclass to work with lib/time.c. The timer is usually - * a 32 bits free-running up counter. The get_rate() method is used to get + * Implement a timer uclass to work with lib/time.c. The timer is usually + * a 32/64 bits free-running up counter. The get_rate() method is used to get * the input clock frequency of the timer. The get_count() method is used - * get the current 32 bits count value. If the hardware is counting down, + * to get the current 64 bits count value. If the hardware is counting down, * the value should be inversed inside the method. There may be no real * tick, and no timer interrupt. */ -int timer_get_count(struct udevice *dev, unsigned long *count) +int timer_get_count(struct udevice *dev, u64 *count) { const struct timer_ops *ops = device_get_ops(dev); @@ -35,8 +37,28 @@ unsigned long timer_get_rate(struct udevice *dev) return uc_priv->clock_rate; } +static int timer_pre_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", 0); + + return 0; +} + +u64 timer_conv_64(u32 count) +{ + /* increment tbh if tbl has rolled over */ + if (count < gd->timebase_l) + gd->timebase_h++; + gd->timebase_l = count; + return ((u64)gd->timebase_h << 32) | gd->timebase_l; +} + UCLASS_DRIVER(timer) = { .id = UCLASS_TIMER, .name = "timer", + .pre_probe = timer_pre_probe, .per_device_auto_alloc_size = sizeof(struct timer_dev_priv), }; diff --git a/arch/x86/lib/tsc_timer.c b/drivers/timer/tsc_timer.c index e02b918..5c4ec00 100644 --- a/arch/x86/lib/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -8,7 +8,9 @@ */ #include <common.h> +#include <dm.h> #include <malloc.h> +#include <timer.h> #include <asm/io.h> #include <asm/i8254.h> #include <asm/ibmpc.h> @@ -278,53 +280,10 @@ success: return delta / 1000; } -void timer_set_base(u64 base) -{ - gd->arch.tsc_base = base; -} - -/* - * Get the number of CPU time counter ticks since it was read first time after - * restart. This yields a free running counter guaranteed to take almost 6 - * years to wrap around even at 100GHz clock rate. - */ -u64 __attribute__((no_instrument_function)) get_ticks(void) -{ - u64 now_tick = rdtsc(); - - /* We assume that 0 means the base hasn't been set yet */ - if (!gd->arch.tsc_base) - panic("No tick base available"); - return now_tick - gd->arch.tsc_base; -} - /* Get the speed of the TSC timer in MHz */ -unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void) +unsigned notrace long get_tbclk_mhz(void) { - unsigned long fast_calibrate; - - if (gd->arch.tsc_mhz) - return gd->arch.tsc_mhz; - -#ifdef CONFIG_TSC_CALIBRATION_BYPASS - fast_calibrate = CONFIG_TSC_FREQ_IN_MHZ; -#else - fast_calibrate = try_msr_calibrate_tsc(); - if (!fast_calibrate) { - - fast_calibrate = quick_pit_calibrate(); - if (!fast_calibrate) - panic("TSC frequency is ZERO"); - } -#endif - - gd->arch.tsc_mhz = fast_calibrate; - return fast_calibrate; -} - -unsigned long get_tbclk(void) -{ - return get_tbclk_mhz() * 1000 * 1000; + return get_tbclk() / 1000000; } static ulong get_ms_timer(void) @@ -337,7 +296,7 @@ ulong get_timer(ulong base) return get_ms_timer() - base; } -ulong __attribute__((no_instrument_function)) timer_get_us(void) +ulong notrace timer_get_us(void) { return get_ticks() / get_tbclk_mhz(); } @@ -366,12 +325,55 @@ void __udelay(unsigned long usec) #endif } -int timer_init(void) +static int tsc_timer_get_count(struct udevice *dev, u64 *count) { -#ifdef CONFIG_I8254_TIMER - /* Set up the i8254 timer if required */ - i8254_init(); -#endif + u64 now_tick = rdtsc(); + + *count = now_tick - gd->arch.tsc_base; + + return 0; +} + +static int tsc_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + gd->arch.tsc_base = rdtsc(); + + /* + * If there is no clock frequency specified in the device tree, + * calibrate it by ourselves. + */ + if (!uc_priv->clock_rate) { + unsigned long fast_calibrate; + + fast_calibrate = try_msr_calibrate_tsc(); + if (!fast_calibrate) { + fast_calibrate = quick_pit_calibrate(); + if (!fast_calibrate) + panic("TSC frequency is ZERO"); + } + + uc_priv->clock_rate = fast_calibrate * 1000000; + } return 0; } + +static const struct timer_ops tsc_timer_ops = { + .get_count = tsc_timer_get_count, +}; + +static const struct udevice_id tsc_timer_ids[] = { + { .compatible = "x86,tsc-timer", }, + { } +}; + +U_BOOT_DRIVER(tsc_timer) = { + .name = "tsc_timer", + .id = UCLASS_TIMER, + .of_match = tsc_timer_ids, + .probe = tsc_timer_probe, + .ops = &tsc_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 0ae3de5..85cc96a 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -613,7 +613,7 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc) int dwc3_uboot_init(struct dwc3_device *dwc3_dev) { struct dwc3 *dwc; - struct device *dev; + struct device *dev = NULL; u8 lpm_nyet_threshold; u8 tx_de_emphasis; u8 hird_threshold; diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c index ac9a856..3dcc2f4 100644 --- a/drivers/usb/dwc3/dwc3-omap.c +++ b/drivers/usb/dwc3/dwc3-omap.c @@ -374,7 +374,7 @@ static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap, int utmi_mode) int dwc3_omap_uboot_init(struct dwc3_omap_device *omap_dev) { u32 reg; - struct device *dev; + struct device *dev = NULL; struct dwc3_omap *omap; omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 6288ecf..c915c79 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -13,8 +13,8 @@ ifdef CONFIG_USB_GADGET obj-$(CONFIG_USB_GADGET_AT91) += at91_udc.o obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o obj-$(CONFIG_USB_GADGET_BCM_UDC_OTG_PHY) += bcm_udc_otg_phy.o -obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o -obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG_PHY) += s3c_udc_otg_phy.o +obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_udc_otg.o +obj-$(CONFIG_USB_GADGET_DWC2_OTG_PHY) += dwc2_udc_otg_phy.o obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o obj-$(CONFIG_CI_UDC) += ci_udc.o obj-$(CONFIG_USB_GADGET_DOWNLOAD) += g_dnl.o diff --git a/drivers/usb/gadget/bcm_udc_otg_phy.c b/drivers/usb/gadget/bcm_udc_otg_phy.c index f8690b0..10b2e13 100644 --- a/drivers/usb/gadget/bcm_udc_otg_phy.c +++ b/drivers/usb/gadget/bcm_udc_otg_phy.c @@ -9,10 +9,10 @@ #include <asm/io.h> #include <asm/arch/sysmap.h> -#include <usb/s3c_udc.h> +#include "dwc2_udc_otg_priv.h" #include "bcm_udc_otg.h" -void otg_phy_init(struct s3c_udc *dev) +void otg_phy_init(struct dwc2_udc *dev) { /* set Phy to driving mode */ wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, @@ -37,7 +37,7 @@ void otg_phy_init(struct s3c_udc *dev) HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK); } -void otg_phy_off(struct s3c_udc *dev) +void otg_phy_off(struct dwc2_udc *dev) { /* Soft Disconnect */ wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET, diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index 7a2d1e7..ffe2952 100644 --- a/drivers/usb/gadget/s3c_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -1,6 +1,6 @@ /* - * drivers/usb/gadget/s3c_udc_otg.c - * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers + * drivers/usb/gadget/dwc2_udc_otg.c + * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers * * Copyright (C) 2008 for Samsung Electronics * @@ -32,7 +32,8 @@ #include <asm/mach-types.h> -#include "regs-otg.h" +#include "dwc2_udc_otg_regs.h" +#include "dwc2_udc_otg_priv.h" #include <usb/lin_gadget_compat.h> /***********************************************************/ @@ -45,7 +46,7 @@ #define DEBUG_OUT_EP 0 #define DEBUG_IN_EP 0 -#include <usb/s3c_udc.h> +#include <usb/dwc2_udc.h> #define EP0_CON 0 #define EP_MASK 0xF @@ -62,12 +63,12 @@ static char *state_names[] = { "WAIT_FOR_NULL_COMPLETE", }; -#define DRIVER_DESC "S3C HS USB OTG Device Driver, (c) Samsung Electronics" +#define DRIVER_DESC "DWC2 HS USB OTG Device Driver, (c) Samsung Electronics" #define DRIVER_VERSION "15 March 2009" -struct s3c_udc *the_controller; +struct dwc2_udc *the_controller; -static const char driver_name[] = "s3c-udc"; +static const char driver_name[] = "dwc2-udc"; static const char driver_desc[] = DRIVER_DESC; static const char ep0name[] = "ep0-control"; @@ -83,32 +84,32 @@ static dma_addr_t usb_ctrl_dma_addr; /* Local declarations. */ -static int s3c_ep_enable(struct usb_ep *ep, +static int dwc2_ep_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *); -static int s3c_ep_disable(struct usb_ep *ep); -static struct usb_request *s3c_alloc_request(struct usb_ep *ep, +static int dwc2_ep_disable(struct usb_ep *ep); +static struct usb_request *dwc2_alloc_request(struct usb_ep *ep, gfp_t gfp_flags); -static void s3c_free_request(struct usb_ep *ep, struct usb_request *); - -static int s3c_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags); -static int s3c_dequeue(struct usb_ep *ep, struct usb_request *); -static int s3c_fifo_status(struct usb_ep *ep); -static void s3c_fifo_flush(struct usb_ep *ep); -static void s3c_ep0_read(struct s3c_udc *dev); -static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep); -static void s3c_handle_ep0(struct s3c_udc *dev); -static int s3c_ep0_write(struct s3c_udc *dev); -static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req); -static void done(struct s3c_ep *ep, struct s3c_request *req, int status); -static void stop_activity(struct s3c_udc *dev, +static void dwc2_free_request(struct usb_ep *ep, struct usb_request *); + +static int dwc2_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags); +static int dwc2_dequeue(struct usb_ep *ep, struct usb_request *); +static int dwc2_fifo_status(struct usb_ep *ep); +static void dwc2_fifo_flush(struct usb_ep *ep); +static void dwc2_ep0_read(struct dwc2_udc *dev); +static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep); +static void dwc2_handle_ep0(struct dwc2_udc *dev); +static int dwc2_ep0_write(struct dwc2_udc *dev); +static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req); +static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status); +static void stop_activity(struct dwc2_udc *dev, struct usb_gadget_driver *driver); -static int udc_enable(struct s3c_udc *dev); -static void udc_set_address(struct s3c_udc *dev, unsigned char address); -static void reconfig_usbd(struct s3c_udc *dev); -static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed); -static void nuke(struct s3c_ep *ep, int status); -static int s3c_udc_set_halt(struct usb_ep *_ep, int value); -static void s3c_udc_set_nak(struct s3c_ep *ep); +static int udc_enable(struct dwc2_udc *dev); +static void udc_set_address(struct dwc2_udc *dev, unsigned char address); +static void reconfig_usbd(struct dwc2_udc *dev); +static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed); +static void nuke(struct dwc2_ep *ep, int status); +static int dwc2_udc_set_halt(struct usb_ep *_ep, int value); +static void dwc2_udc_set_nak(struct dwc2_ep *ep); void set_udc_gadget_private_data(void *p) { @@ -123,19 +124,19 @@ void *get_udc_gadget_private_data(struct usb_gadget *gadget) return gadget->dev.device_data; } -static struct usb_ep_ops s3c_ep_ops = { - .enable = s3c_ep_enable, - .disable = s3c_ep_disable, +static struct usb_ep_ops dwc2_ep_ops = { + .enable = dwc2_ep_enable, + .disable = dwc2_ep_disable, - .alloc_request = s3c_alloc_request, - .free_request = s3c_free_request, + .alloc_request = dwc2_alloc_request, + .free_request = dwc2_free_request, - .queue = s3c_queue, - .dequeue = s3c_dequeue, + .queue = dwc2_queue, + .dequeue = dwc2_dequeue, - .set_halt = s3c_udc_set_halt, - .fifo_status = s3c_fifo_status, - .fifo_flush = s3c_fifo_flush, + .set_halt = dwc2_udc_set_halt, + .fifo_status = dwc2_fifo_status, + .fifo_flush = dwc2_fifo_flush, }; #define create_proc_files() do {} while (0) @@ -144,24 +145,24 @@ static struct usb_ep_ops s3c_ep_ops = { /***********************************************************/ void __iomem *regs_otg; -struct s3c_usbotg_reg *reg; +struct dwc2_usbotg_reg *reg; bool dfu_usb_get_reset(void) { return !!(readl(®->gintsts) & INT_RESET); } -__weak void otg_phy_init(struct s3c_udc *dev) {} -__weak void otg_phy_off(struct s3c_udc *dev) {} +__weak void otg_phy_init(struct dwc2_udc *dev) {} +__weak void otg_phy_off(struct dwc2_udc *dev) {} /***********************************************************/ -#include "s3c_udc_otg_xfer_dma.c" +#include "dwc2_udc_otg_xfer_dma.c" /* * udc_disable - disable USB device controller */ -static void udc_disable(struct s3c_udc *dev) +static void udc_disable(struct dwc2_udc *dev) { debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev); @@ -177,7 +178,7 @@ static void udc_disable(struct s3c_udc *dev) /* * udc_reinit - initialize software state */ -static void udc_reinit(struct s3c_udc *dev) +static void udc_reinit(struct dwc2_udc *dev) { unsigned int i; @@ -189,8 +190,8 @@ static void udc_reinit(struct s3c_udc *dev) dev->ep0state = WAIT_FOR_SETUP; /* basic endpoint records init */ - for (i = 0; i < S3C_MAX_ENDPOINTS; i++) { - struct s3c_ep *ep = &dev->ep[i]; + for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) { + struct dwc2_ep *ep = &dev->ep[i]; if (i != 0) list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); @@ -210,7 +211,7 @@ static void udc_reinit(struct s3c_udc *dev) /* until it's enabled, this UDC should be completely invisible * to any USB host. */ -static int udc_enable(struct s3c_udc *dev) +static int udc_enable(struct dwc2_udc *dev) { debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev); @@ -218,7 +219,7 @@ static int udc_enable(struct s3c_udc *dev) reconfig_usbd(dev); debug_cond(DEBUG_SETUP != 0, - "S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n", + "DWC2 USB 2.0 OTG Controller Core Initialized : 0x%x\n", readl(®->gintmsk)); dev->gadget.speed = USB_SPEED_UNKNOWN; @@ -231,7 +232,7 @@ static int udc_enable(struct s3c_udc *dev) */ int usb_gadget_register_driver(struct usb_gadget_driver *driver) { - struct s3c_udc *dev = the_controller; + struct dwc2_udc *dev = the_controller; int retval = 0; unsigned long flags = 0; @@ -280,7 +281,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) */ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) { - struct s3c_udc *dev = the_controller; + struct dwc2_udc *dev = the_controller; unsigned long flags = 0; if (!dev) @@ -304,7 +305,7 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) /* * done - retire a request; caller blocked irqs */ -static void done(struct s3c_ep *ep, struct s3c_request *req, int status) +static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status) { unsigned int stopped = ep->stopped; @@ -355,20 +356,20 @@ static void done(struct s3c_ep *ep, struct s3c_request *req, int status) /* * nuke - dequeue ALL requests */ -static void nuke(struct s3c_ep *ep, int status) +static void nuke(struct dwc2_ep *ep, int status) { - struct s3c_request *req; + struct dwc2_request *req; debug("%s: %s %p\n", __func__, ep->ep.name, ep); /* called with irqs blocked */ while (!list_empty(&ep->queue)) { - req = list_entry(ep->queue.next, struct s3c_request, queue); + req = list_entry(ep->queue.next, struct dwc2_request, queue); done(ep, req, status); } } -static void stop_activity(struct s3c_udc *dev, +static void stop_activity(struct dwc2_udc *dev, struct usb_gadget_driver *driver) { int i; @@ -379,8 +380,8 @@ static void stop_activity(struct s3c_udc *dev, dev->gadget.speed = USB_SPEED_UNKNOWN; /* prevent new request submissions, kill any outstanding requests */ - for (i = 0; i < S3C_MAX_ENDPOINTS; i++) { - struct s3c_ep *ep = &dev->ep[i]; + for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) { + struct dwc2_ep *ep = &dev->ep[i]; ep->stopped = 1; nuke(ep, -ESHUTDOWN); } @@ -396,7 +397,7 @@ static void stop_activity(struct s3c_udc *dev, udc_reinit(dev); } -static void reconfig_usbd(struct s3c_udc *dev) +static void reconfig_usbd(struct dwc2_udc *dev) { /* 2. Soft-reset OTG Core and then unreset again. */ int i; @@ -447,7 +448,7 @@ static void reconfig_usbd(struct s3c_udc *dev) writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->out_endp[EP0_CON].doepctl); writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->in_endp[EP0_CON].diepctl); - for (i = 1; i < S3C_MAX_ENDPOINTS; i++) { + for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) { writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->out_endp[i].doepctl); writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->in_endp[i].diepctl); } @@ -469,7 +470,7 @@ static void reconfig_usbd(struct s3c_udc *dev) writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0, ®->gnptxfsiz); - for (i = 1; i < S3C_MAX_HW_ENDPOINTS; i++) + for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++) writel((PTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE + NPTX_FIFO_SIZE + PTX_FIFO_SIZE*(i-1)) >> 2) << 0, @@ -478,13 +479,13 @@ static void reconfig_usbd(struct s3c_udc *dev) /* Flush the RX FIFO */ writel(RX_FIFO_FLUSH, ®->grstctl); while (readl(®->grstctl) & RX_FIFO_FLUSH) - debug("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__); + debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__); /* Flush all the Tx FIFO's */ writel(TX_FIFO_FLUSH_ALL, ®->grstctl); writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, ®->grstctl); while (readl(®->grstctl) & TX_FIFO_FLUSH) - debug("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__); + debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__); /* 13. Clear NAK bit of EP0, EP1, EP2*/ /* For Slave mode*/ @@ -496,7 +497,7 @@ static void reconfig_usbd(struct s3c_udc *dev) writel(GAHBCFG_INIT, ®->gahbcfg); } -static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed) +static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed) { unsigned int ep_ctrl; int i; @@ -514,7 +515,7 @@ static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed) } dev->ep[0].ep.maxpacket = ep0_fifo_size; - for (i = 1; i < S3C_MAX_ENDPOINTS; i++) + for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) dev->ep[i].ep.maxpacket = ep_fifo_size; /* EP0 - Control IN (64 bytes)*/ @@ -526,16 +527,16 @@ static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed) writel(ep_ctrl|(0<<0), ®->out_endp[EP0_CON].doepctl); } -static int s3c_ep_enable(struct usb_ep *_ep, +static int dwc2_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc) { - struct s3c_ep *ep; - struct s3c_udc *dev; + struct dwc2_ep *ep; + struct dwc2_udc *dev; unsigned long flags = 0; debug("%s: %p\n", __func__, _ep); - ep = container_of(_ep, struct s3c_ep, ep); + ep = container_of(_ep, struct dwc2_ep, ep); if (!_ep || !desc || ep->desc || _ep->name == ep0name || desc->bDescriptorType != USB_DT_ENDPOINT || ep->bEndpointAddress != desc->bEndpointAddress @@ -577,11 +578,11 @@ static int s3c_ep_enable(struct usb_ep *_ep, ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)); /* Reset halt state */ - s3c_udc_set_nak(ep); - s3c_udc_set_halt(_ep, 0); + dwc2_udc_set_nak(ep); + dwc2_udc_set_halt(_ep, 0); spin_lock_irqsave(&ep->dev->lock, flags); - s3c_udc_ep_activate(ep); + dwc2_udc_ep_activate(ep); spin_unlock_irqrestore(&ep->dev->lock, flags); debug("%s: enabled %s, stopped = %d, maxpacket = %d\n", @@ -592,14 +593,14 @@ static int s3c_ep_enable(struct usb_ep *_ep, /* * Disable EP */ -static int s3c_ep_disable(struct usb_ep *_ep) +static int dwc2_ep_disable(struct usb_ep *_ep) { - struct s3c_ep *ep; + struct dwc2_ep *ep; unsigned long flags = 0; debug("%s: %p\n", __func__, _ep); - ep = container_of(_ep, struct s3c_ep, ep); + ep = container_of(_ep, struct dwc2_ep, ep); if (!_ep || !ep->desc) { debug("%s: %s not enabled\n", __func__, _ep ? ep->ep.name : NULL); @@ -620,10 +621,10 @@ static int s3c_ep_disable(struct usb_ep *_ep) return 0; } -static struct usb_request *s3c_alloc_request(struct usb_ep *ep, +static struct usb_request *dwc2_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) { - struct s3c_request *req; + struct dwc2_request *req; debug("%s: %s %p\n", __func__, ep->name, ep); @@ -637,27 +638,27 @@ static struct usb_request *s3c_alloc_request(struct usb_ep *ep, return &req->req; } -static void s3c_free_request(struct usb_ep *ep, struct usb_request *_req) +static void dwc2_free_request(struct usb_ep *ep, struct usb_request *_req) { - struct s3c_request *req; + struct dwc2_request *req; debug("%s: %p\n", __func__, ep); - req = container_of(_req, struct s3c_request, req); + req = container_of(_req, struct dwc2_request, req); WARN_ON(!list_empty(&req->queue)); kfree(req); } /* dequeue JUST ONE request */ -static int s3c_dequeue(struct usb_ep *_ep, struct usb_request *_req) +static int dwc2_dequeue(struct usb_ep *_ep, struct usb_request *_req) { - struct s3c_ep *ep; - struct s3c_request *req; + struct dwc2_ep *ep; + struct dwc2_request *req; unsigned long flags = 0; debug("%s: %p\n", __func__, _ep); - ep = container_of(_ep, struct s3c_ep, ep); + ep = container_of(_ep, struct dwc2_ep, ep); if (!_ep || ep->ep.name == ep0name) return -EINVAL; @@ -682,12 +683,12 @@ static int s3c_dequeue(struct usb_ep *_ep, struct usb_request *_req) /* * Return bytes in EP FIFO */ -static int s3c_fifo_status(struct usb_ep *_ep) +static int dwc2_fifo_status(struct usb_ep *_ep) { int count = 0; - struct s3c_ep *ep; + struct dwc2_ep *ep; - ep = container_of(_ep, struct s3c_ep, ep); + ep = container_of(_ep, struct dwc2_ep, ep); if (!_ep) { debug("%s: bad ep\n", __func__); return -ENODEV; @@ -705,11 +706,11 @@ static int s3c_fifo_status(struct usb_ep *_ep) /* * Flush EP FIFO */ -static void s3c_fifo_flush(struct usb_ep *_ep) +static void dwc2_fifo_flush(struct usb_ep *_ep) { - struct s3c_ep *ep; + struct dwc2_ep *ep; - ep = container_of(_ep, struct s3c_ep, ep); + ep = container_of(_ep, struct dwc2_ep, ep); if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) { debug("%s: bad ep\n", __func__); return; @@ -718,14 +719,14 @@ static void s3c_fifo_flush(struct usb_ep *_ep) debug("%s: %d\n", __func__, ep_index(ep)); } -static const struct usb_gadget_ops s3c_udc_ops = { +static const struct usb_gadget_ops dwc2_udc_ops = { /* current versions must always be self-powered */ }; -static struct s3c_udc memory = { +static struct dwc2_udc memory = { .usb_address = 0, .gadget = { - .ops = &s3c_udc_ops, + .ops = &dwc2_udc_ops, .ep0 = &memory.ep[0].ep, .name = driver_name, }, @@ -734,7 +735,7 @@ static struct s3c_udc memory = { .ep[0] = { .ep = { .name = ep0name, - .ops = &s3c_ep_ops, + .ops = &dwc2_ep_ops, .maxpacket = EP0_FIFO_SIZE, }, .dev = &memory, @@ -749,7 +750,7 @@ static struct s3c_udc memory = { .ep[1] = { .ep = { .name = "ep1in-bulk", - .ops = &s3c_ep_ops, + .ops = &dwc2_ep_ops, .maxpacket = EP_FIFO_SIZE, }, .dev = &memory, @@ -764,7 +765,7 @@ static struct s3c_udc memory = { .ep[2] = { .ep = { .name = "ep2out-bulk", - .ops = &s3c_ep_ops, + .ops = &dwc2_ep_ops, .maxpacket = EP_FIFO_SIZE, }, .dev = &memory, @@ -779,7 +780,7 @@ static struct s3c_udc memory = { .ep[3] = { .ep = { .name = "ep3in-int", - .ops = &s3c_ep_ops, + .ops = &dwc2_ep_ops, .maxpacket = EP_FIFO_SIZE, }, .dev = &memory, @@ -796,16 +797,16 @@ static struct s3c_udc memory = { * probe - binds to the platform device */ -int s3c_udc_probe(struct s3c_plat_otg_data *pdata) +int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata) { - struct s3c_udc *dev = &memory; + struct dwc2_udc *dev = &memory; int retval = 0; debug("%s: %p\n", __func__, pdata); dev->pdata = pdata; - reg = (struct s3c_usbotg_reg *)pdata->regs_otg; + reg = (struct dwc2_usbotg_reg *)pdata->regs_otg; /* regs_otg = (void *)pdata->regs_otg; */ @@ -839,6 +840,6 @@ int usb_gadget_handle_interrupts(int index) u32 gintmsk = readl(®->gintmsk); if (intr_status & gintmsk) - return s3c_udc_irq(1, (void *)the_controller); + return dwc2_udc_irq(1, (void *)the_controller); return 0; } diff --git a/drivers/usb/gadget/s3c_udc_otg_phy.c b/drivers/usb/gadget/dwc2_udc_otg_phy.c index f13cb89..e0cbbc0 100644 --- a/drivers/usb/gadget/s3c_udc_otg_phy.c +++ b/drivers/usb/gadget/dwc2_udc_otg_phy.c @@ -1,6 +1,6 @@ /* - * drivers/usb/gadget/s3c_udc_otg.c - * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers + * drivers/usb/gadget/dwc2_udc_otg.c + * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers * * Copyright (C) 2008 for Samsung Electronics * @@ -32,16 +32,17 @@ #include <asm/mach-types.h> -#include "regs-otg.h" +#include "dwc2_udc_otg_regs.h" +#include "dwc2_udc_otg_priv.h" #include <usb/lin_gadget_compat.h> -#include <usb/s3c_udc.h> +#include <usb/dwc2_udc.h> -void otg_phy_init(struct s3c_udc *dev) +void otg_phy_init(struct dwc2_udc *dev) { unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl; - struct s3c_usbotg_phy *phy = - (struct s3c_usbotg_phy *)dev->pdata->regs_phy; + struct dwc2_usbotg_phy *phy = + (struct dwc2_usbotg_phy *)dev->pdata->regs_phy; dev->pdata->phy_control(1); @@ -75,11 +76,11 @@ void otg_phy_init(struct s3c_udc *dev) udelay(10); } -void otg_phy_off(struct s3c_udc *dev) +void otg_phy_off(struct dwc2_udc *dev) { unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl; - struct s3c_usbotg_phy *phy = - (struct s3c_usbotg_phy *)dev->pdata->regs_phy; + struct dwc2_usbotg_phy *phy = + (struct dwc2_usbotg_phy *)dev->pdata->regs_phy; /* reset controller just in case */ writel(PHY_SW_RST0, &phy->rstcon); diff --git a/include/usb/s3c_udc.h b/drivers/usb/gadget/dwc2_udc_otg_priv.h index 7f49a4e..b2c1fc4 100644 --- a/include/usb/s3c_udc.h +++ b/drivers/usb/gadget/dwc2_udc_otg_priv.h @@ -1,13 +1,12 @@ /* - * drivers/usb/gadget/s3c_udc.h - * Samsung S3C on-chip full/high speed USB device controllers + * Designware DWC2 on-chip full/high speed USB device controllers * Copyright (C) 2005 for Samsung Electronics * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __S3C_USB_GADGET -#define __S3C_USB_GADGET +#ifndef __DWC2_UDC_OTG_PRIV__ +#define __DWC2_UDC_OTG_PRIV__ #include <asm/errno.h> #include <linux/sizes.h> @@ -15,8 +14,7 @@ #include <linux/usb/gadget.h> #include <linux/list.h> #include <usb/lin_gadget_compat.h> - -#define PHY0_SLEEP (1 << 5) +#include <usb/dwc2_udc.h> /*-------------------------------------------------------------------------*/ /* DMA bounce buffer size, 16K is enough even for mass storage */ @@ -26,8 +24,8 @@ #define EP_FIFO_SIZE 512 #define EP_FIFO_SIZE2 1024 /* ep0-control, ep1in-bulk, ep2out-bulk, ep3in-int */ -#define S3C_MAX_ENDPOINTS 4 -#define S3C_MAX_HW_ENDPOINTS 16 +#define DWC2_MAX_ENDPOINTS 4 +#define DWC2_MAX_HW_ENDPOINTS 16 #define WAIT_FOR_SETUP 0 #define DATA_STATE_XMIT 1 @@ -53,9 +51,9 @@ enum ep_type { ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt }; -struct s3c_ep { +struct dwc2_ep { struct usb_ep ep; - struct s3c_udc *dev; + struct dwc2_udc *dev; const struct usb_endpoint_descriptor *desc; struct list_head queue; @@ -71,43 +69,30 @@ struct s3c_ep { int fifo_num; }; -struct s3c_request { +struct dwc2_request { struct usb_request req; struct list_head queue; }; -struct s3c_udc { +struct dwc2_udc { struct usb_gadget gadget; struct usb_gadget_driver *driver; - struct s3c_plat_otg_data *pdata; + struct dwc2_plat_otg_data *pdata; int ep0state; - struct s3c_ep ep[S3C_MAX_ENDPOINTS]; + struct dwc2_ep ep[DWC2_MAX_ENDPOINTS]; unsigned char usb_address; unsigned req_pending:1, req_std:1; }; -extern struct s3c_udc *the_controller; - #define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN) == USB_DIR_IN) #define ep_index(EP) ((EP)->bEndpointAddress&0xF) #define ep_maxpacket(EP) ((EP)->ep.maxpacket) -extern void otg_phy_init(struct s3c_udc *dev); -extern void otg_phy_off(struct s3c_udc *dev); +void otg_phy_init(struct dwc2_udc *dev); +void otg_phy_off(struct dwc2_udc *dev); -extern void s3c_udc_ep_set_stall(struct s3c_ep *ep); -extern int s3c_udc_probe(struct s3c_plat_otg_data *pdata); - -struct s3c_plat_otg_data { - int (*phy_control)(int on); - unsigned int regs_phy; - unsigned int regs_otg; - unsigned int usb_phy_ctrl; - unsigned int usb_flags; - unsigned int usb_gusbcfg; -}; -#endif +#endif /* __DWC2_UDC_OTG_PRIV__ */ diff --git a/drivers/usb/gadget/regs-otg.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h index ac5d112..78ec90e 100644 --- a/drivers/usb/gadget/regs-otg.h +++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h @@ -12,14 +12,14 @@ #define __ASM_ARCH_REGS_USB_OTG_HS_H /* USB2.0 OTG Controller register */ -struct s3c_usbotg_phy { +struct dwc2_usbotg_phy { u32 phypwr; u32 phyclk; u32 rstcon; }; /* Device Logical IN Endpoint-Specific Registers */ -struct s3c_dev_in_endp { +struct dwc2_dev_in_endp { u32 diepctl; u8 res1[4]; u32 diepint; @@ -31,7 +31,7 @@ struct s3c_dev_in_endp { }; /* Device Logical OUT Endpoint-Specific Registers */ -struct s3c_dev_out_endp { +struct dwc2_dev_out_endp { u32 doepctl; u8 res1[4]; u32 doepint; @@ -48,7 +48,7 @@ struct ep_fifo { }; /* USB2.0 OTG Controller register */ -struct s3c_usbotg_reg { +struct dwc2_usbotg_reg { /* Core Global Registers */ u32 gotgctl; /* OTG Control & Status */ u32 gotgint; /* OTG Interrupt */ @@ -74,8 +74,8 @@ struct s3c_usbotg_reg { u32 daint; /* Device All Endpoints Interrupt */ u32 daintmsk; /* Device All Endpoints Interrupt Mask */ u8 res4[224]; - struct s3c_dev_in_endp in_endp[16]; - struct s3c_dev_out_endp out_endp[16]; + struct dwc2_dev_in_endp in_endp[16]; + struct dwc2_dev_out_endp out_endp[16]; u8 res5[768]; struct ep_fifo ep[16]; }; @@ -83,11 +83,11 @@ struct s3c_usbotg_reg { /*===================================================================== */ /*definitions related to CSR setting */ -/* S3C_UDC_OTG_GOTGCTL */ +/* DWC2_UDC_OTG_GOTGCTL */ #define B_SESSION_VALID (0x1<<19) #define A_SESSION_VALID (0x1<<18) -/* S3C_UDC_OTG_GAHBCFG */ +/* DWC2_UDC_OTG_GAHBCFG */ #define PTXFE_HALF (0<<8) #define PTXFE_ZERO (1<<8) #define NPTXFE_HALF (0<<7) @@ -102,11 +102,11 @@ struct s3c_usbotg_reg { #define GBL_INT_UNMASK (1<<0) #define GBL_INT_MASK (0<<0) -/* S3C_UDC_OTG_GRSTCTL */ +/* DWC2_UDC_OTG_GRSTCTL */ #define AHB_MASTER_IDLE (1u<<31) #define CORE_SOFT_RESET (0x1<<0) -/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */ +/* DWC2_UDC_OTG_GINTSTS/DWC2_UDC_OTG_GINTMSK core interrupt register */ #define INT_RESUME (1u<<31) #define INT_DISCONN (0x1<<29) #define INT_CONN_ID_STS_CNG (0x1<<28) @@ -146,22 +146,22 @@ struct s3c_usbotg_reg { #define USB_LOW_6MHZ (0x2<<1) #define USB_FULL_48MHZ (0x3<<1) -/* S3C_UDC_OTG_GRXSTSP STATUS */ +/* DWC2_UDC_OTG_GRXSTSP STATUS */ #define OUT_PKT_RECEIVED (0x2<<17) #define OUT_TRANSFER_COMPLELTED (0x3<<17) #define SETUP_TRANSACTION_COMPLETED (0x4<<17) #define SETUP_PKT_RECEIVED (0x6<<17) #define GLOBAL_OUT_NAK (0x1<<17) -/* S3C_UDC_OTG_DCTL device control register */ +/* DWC2_UDC_OTG_DCTL device control register */ #define NORMAL_OPERATION (0x1<<0) #define SOFT_DISCONNECT (0x1<<1) -/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */ +/* DWC2_UDC_OTG_DAINT device all endpoint interrupt register */ #define DAINT_OUT_BIT (16) #define DAINT_MASK (0xFFFF) -/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device +/* DWC2_UDC_OTG_DIEPCTL0/DOEPCTL0 device control IN/OUT endpoint 0 control register */ #define DEPCTL_EPENA (0x1<<31) #define DEPCTL_EPDIS (0x1<<30) @@ -191,9 +191,9 @@ struct s3c_usbotg_reg { #define DIEPCTL0_NEXT_EP_BIT (11) -/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint +/* DWC2_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint common interrupt mask register */ -/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */ +/* DWC2_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */ #define BACK2BACK_SETUP_RECEIVED (0x1<<6) #define INTKNEPMIS (0x1<<5) #define INTKN_TXFEMP (0x1<<4) diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c index 7e7a2c2..bce9c30 100644 --- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c @@ -1,6 +1,6 @@ /* - * drivers/usb/gadget/s3c_udc_otg_xfer_dma.c - * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers + * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c + * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers * * Copyright (C) 2009 for Samsung Electronics * @@ -25,7 +25,7 @@ int clear_feature_flag; #define GET_MAX_LUN_REQUEST 0xFE #define BOT_RESET_REQUEST 0xFF -static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev) +static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev) { u32 ep_ctrl; @@ -41,7 +41,7 @@ static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev) dev->ep0state = WAIT_FOR_IN_COMPLETE; } -void s3c_udc_pre_setup(void) +static void dwc2_udc_pre_setup(void) { u32 ep_ctrl; @@ -62,7 +62,7 @@ void s3c_udc_pre_setup(void) } -static inline void s3c_ep0_complete_out(void) +static inline void dwc2_ep0_complete_out(void) { u32 ep_ctrl; @@ -90,7 +90,7 @@ static inline void s3c_ep0_complete_out(void) } -static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req) +static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req) { u32 *buf, ctrl; u32 length, pktcnt; @@ -128,7 +128,7 @@ static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req) } -int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) +static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req) { u32 *buf, ctrl = 0; u32 length, pktcnt; @@ -186,10 +186,10 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) return length; } -static void complete_rx(struct s3c_udc *dev, u8 ep_num) +static void complete_rx(struct dwc2_udc *dev, u8 ep_num) { - struct s3c_ep *ep = &dev->ep[ep_num]; - struct s3c_request *req = NULL; + struct dwc2_ep *ep = &dev->ep[ep_num]; + struct dwc2_request *req = NULL; u32 ep_tsr = 0, xfer_size = 0, is_short = 0; if (list_empty(&ep->queue)) { @@ -200,7 +200,7 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num) } - req = list_entry(ep->queue.next, struct s3c_request, queue); + req = list_entry(ep->queue.next, struct dwc2_request, queue); ep_tsr = readl(®->out_endp[ep_num].doeptsiz); if (ep_num == EP0_CON) @@ -240,7 +240,7 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num) if (is_short || req->req.actual == req->req.length) { if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) { debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n"); - s3c_udc_ep0_zlp(dev); + dwc2_udc_ep0_zlp(dev); /* packet will be completed in complete_tx() */ dev->ep0state = WAIT_FOR_IN_COMPLETE; } else { @@ -248,7 +248,7 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num) if (!list_empty(&ep->queue)) { req = list_entry(ep->queue.next, - struct s3c_request, queue); + struct dwc2_request, queue); debug_cond(DEBUG_OUT_EP != 0, "%s: Next Rx request start...\n", __func__); @@ -259,16 +259,16 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num) setdma_rx(ep, req); } -static void complete_tx(struct s3c_udc *dev, u8 ep_num) +static void complete_tx(struct dwc2_udc *dev, u8 ep_num) { - struct s3c_ep *ep = &dev->ep[ep_num]; - struct s3c_request *req; + struct dwc2_ep *ep = &dev->ep[ep_num]; + struct dwc2_request *req; u32 ep_tsr = 0, xfer_size = 0, is_short = 0; u32 last; if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) { dev->ep0state = WAIT_FOR_OUT_COMPLETE; - s3c_ep0_complete_out(); + dwc2_ep0_complete_out(); return; } @@ -280,7 +280,7 @@ static void complete_tx(struct s3c_udc *dev, u8 ep_num) } - req = list_entry(ep->queue.next, struct s3c_request, queue); + req = list_entry(ep->queue.next, struct dwc2_request, queue); ep_tsr = readl(®->in_endp[ep_num].dieptsiz); @@ -315,7 +315,7 @@ static void complete_tx(struct s3c_udc *dev, u8 ep_num) __func__, ep_num); done(ep, req, 0); dev->ep0state = WAIT_FOR_OUT_COMPLETE; - s3c_ep0_complete_out(); + dwc2_ep0_complete_out(); } else { debug_cond(DEBUG_IN_EP, "%s: ep_num = %d, invalid ep state\n", @@ -328,23 +328,23 @@ static void complete_tx(struct s3c_udc *dev, u8 ep_num) done(ep, req, 0); if (!list_empty(&ep->queue)) { - req = list_entry(ep->queue.next, struct s3c_request, queue); + req = list_entry(ep->queue.next, struct dwc2_request, queue); debug_cond(DEBUG_IN_EP, "%s: Next Tx request start...\n", __func__); setdma_tx(ep, req); } } -static inline void s3c_udc_check_tx_queue(struct s3c_udc *dev, u8 ep_num) +static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num) { - struct s3c_ep *ep = &dev->ep[ep_num]; - struct s3c_request *req; + struct dwc2_ep *ep = &dev->ep[ep_num]; + struct dwc2_request *req; debug_cond(DEBUG_IN_EP, "%s: Check queue, ep_num = %d\n", __func__, ep_num); if (!list_empty(&ep->queue)) { - req = list_entry(ep->queue.next, struct s3c_request, queue); + req = list_entry(ep->queue.next, struct dwc2_request, queue); debug_cond(DEBUG_IN_EP, "%s: Next Tx request(0x%p) start...\n", __func__, req); @@ -362,7 +362,7 @@ static inline void s3c_udc_check_tx_queue(struct s3c_udc *dev, u8 ep_num) } -static void process_ep_in_intr(struct s3c_udc *dev) +static void process_ep_in_intr(struct dwc2_udc *dev) { u32 ep_intr, ep_intr_status; u8 ep_num = 0; @@ -392,12 +392,12 @@ static void process_ep_in_intr(struct s3c_udc *dev) dev->ep0state = WAIT_FOR_SETUP; if (dev->ep0state == WAIT_FOR_SETUP) - s3c_udc_pre_setup(); + dwc2_udc_pre_setup(); /* continue transfer after set_clear_halt for DMA mode */ if (clear_feature_flag == 1) { - s3c_udc_check_tx_queue(dev, + dwc2_udc_check_tx_queue(dev, clear_feature_num); clear_feature_flag = 0; } @@ -409,7 +409,7 @@ static void process_ep_in_intr(struct s3c_udc *dev) } } -static void process_ep_out_intr(struct s3c_udc *dev) +static void process_ep_out_intr(struct dwc2_udc *dev) { u32 ep_intr, ep_intr_status; u8 ep_num = 0; @@ -438,7 +438,7 @@ static void process_ep_out_intr(struct s3c_udc *dev) complete_rx(dev, ep_num); else { dev->ep0state = WAIT_FOR_SETUP; - s3c_udc_pre_setup(); + dwc2_udc_pre_setup(); } } @@ -446,7 +446,7 @@ static void process_ep_out_intr(struct s3c_udc *dev) CTRL_OUT_EP_SETUP_PHASE_DONE) { debug_cond(DEBUG_OUT_EP != 0, "SETUP packet arrived\n"); - s3c_handle_ep0(dev); + dwc2_handle_ep0(dev); } } else { if (ep_intr_status & TRANSFER_DONE) @@ -461,9 +461,9 @@ static void process_ep_out_intr(struct s3c_udc *dev) /* * usb client interrupt handler. */ -static int s3c_udc_irq(int irq, void *_dev) +static int dwc2_udc_irq(int irq, void *_dev) { - struct s3c_udc *dev = _dev; + struct dwc2_udc *dev = _dev; u32 intr_status; u32 usb_status, gintmsk; unsigned long flags = 0; @@ -554,7 +554,7 @@ static int s3c_udc_irq(int irq, void *_dev) reconfig_usbd(dev); dev->ep0state = WAIT_FOR_SETUP; reset_available = 0; - s3c_udc_pre_setup(); + dwc2_udc_pre_setup(); } else reset_available = 1; @@ -579,16 +579,16 @@ static int s3c_udc_irq(int irq, void *_dev) /** Queue one request * Kickstart transfer if needed */ -static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req, +static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) { - struct s3c_request *req; - struct s3c_ep *ep; - struct s3c_udc *dev; + struct dwc2_request *req; + struct dwc2_ep *ep; + struct dwc2_udc *dev; unsigned long flags = 0; u32 ep_num, gintsts; - req = container_of(_req, struct s3c_request, req); + req = container_of(_req, struct dwc2_request, req); if (unlikely(!_req || !_req->complete || !_req->buf || !list_empty(&req->queue))) { @@ -596,7 +596,7 @@ static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req, return -EINVAL; } - ep = container_of(_ep, struct s3c_ep, ep); + ep = container_of(_ep, struct dwc2_ep, ep); if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) { @@ -646,20 +646,20 @@ static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req, if (ep_num == 0) { /* EP0 */ list_add_tail(&req->queue, &ep->queue); - s3c_ep0_kick(dev, ep); + dwc2_ep0_kick(dev, ep); req = 0; } else if (ep_is_in(ep)) { gintsts = readl(®->gintsts); debug_cond(DEBUG_IN_EP, - "%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n", + "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n", __func__, gintsts); setdma_tx(ep, req); } else { gintsts = readl(®->gintsts); debug_cond(DEBUG_OUT_EP != 0, - "%s:ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n", + "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n", __func__, gintsts); setdma_rx(ep, req); @@ -680,7 +680,7 @@ static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req, /****************************************************************/ /* return: 0 = still running, 1 = completed, negative = errno */ -static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req) +static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req) { u32 max; unsigned count; @@ -718,7 +718,7 @@ static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req) return 0; } -int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max) +static int dwc2_fifo_read(struct dwc2_ep *ep, u32 *cp, int max) { invalidate_dcache_range((unsigned long)cp, (unsigned long)cp + ROUND(max, CONFIG_SYS_CACHELINE_SIZE)); @@ -737,12 +737,12 @@ int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max) * Called from control endpoint function * after it decodes a set address setup packet. */ -static void udc_set_address(struct s3c_udc *dev, unsigned char address) +static void udc_set_address(struct dwc2_udc *dev, unsigned char address) { u32 ctrl = readl(®->dcfg); writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg); - s3c_udc_ep0_zlp(dev); + dwc2_udc_ep0_zlp(dev); debug_cond(DEBUG_EP0 != 0, "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n", @@ -751,9 +751,9 @@ static void udc_set_address(struct s3c_udc *dev, unsigned char address) dev->usb_address = address; } -static inline void s3c_udc_ep0_set_stall(struct s3c_ep *ep) +static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep) { - struct s3c_udc *dev; + struct dwc2_udc *dev; u32 ep_ctrl = 0; dev = ep->dev; @@ -776,16 +776,16 @@ static inline void s3c_udc_ep0_set_stall(struct s3c_ep *ep) */ dev->ep0state = WAIT_FOR_SETUP; - s3c_udc_pre_setup(); + dwc2_udc_pre_setup(); } -static void s3c_ep0_read(struct s3c_udc *dev) +static void dwc2_ep0_read(struct dwc2_udc *dev) { - struct s3c_request *req; - struct s3c_ep *ep = &dev->ep[0]; + struct dwc2_request *req; + struct dwc2_ep *ep = &dev->ep[0]; if (!list_empty(&ep->queue)) { - req = list_entry(ep->queue.next, struct s3c_request, queue); + req = list_entry(ep->queue.next, struct dwc2_request, queue); } else { debug("%s: ---> BUG\n", __func__); @@ -802,7 +802,7 @@ static void s3c_ep0_read(struct s3c_udc *dev) * or Bulk-Only mass storge reset */ ep->len = 0; - s3c_udc_ep0_zlp(dev); + dwc2_udc_ep0_zlp(dev); debug_cond(DEBUG_EP0 != 0, "%s: req.length = 0, bRequest = %d\n", @@ -816,16 +816,16 @@ static void s3c_ep0_read(struct s3c_udc *dev) /* * DATA_STATE_XMIT */ -static int s3c_ep0_write(struct s3c_udc *dev) +static int dwc2_ep0_write(struct dwc2_udc *dev) { - struct s3c_request *req; - struct s3c_ep *ep = &dev->ep[0]; + struct dwc2_request *req; + struct dwc2_ep *ep = &dev->ep[0]; int ret, need_zlp = 0; if (list_empty(&ep->queue)) req = 0; else - req = list_entry(ep->queue.next, struct s3c_request, queue); + req = list_entry(ep->queue.next, struct dwc2_request, queue); if (!req) { debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__); @@ -859,7 +859,7 @@ static int s3c_ep0_write(struct s3c_udc *dev) return 1; } -int s3c_udc_get_status(struct s3c_udc *dev, +static int dwc2_udc_get_status(struct dwc2_udc *dev, struct usb_ctrlrequest *crq) { u8 ep_num = crq->wIndex & 0x7F; @@ -920,7 +920,7 @@ int s3c_udc_get_status(struct s3c_udc *dev, return 0; } -static void s3c_udc_set_nak(struct s3c_ep *ep) +static void dwc2_udc_set_nak(struct dwc2_ep *ep) { u8 ep_num; u32 ep_ctrl = 0; @@ -946,7 +946,7 @@ static void s3c_udc_set_nak(struct s3c_ep *ep) } -void s3c_udc_ep_set_stall(struct s3c_ep *ep) +static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep) { u8 ep_num; u32 ep_ctrl = 0; @@ -981,7 +981,7 @@ void s3c_udc_ep_set_stall(struct s3c_ep *ep) return; } -void s3c_udc_ep_clear_stall(struct s3c_ep *ep) +static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep) { u8 ep_num; u32 ep_ctrl = 0; @@ -1029,14 +1029,14 @@ void s3c_udc_ep_clear_stall(struct s3c_ep *ep) return; } -static int s3c_udc_set_halt(struct usb_ep *_ep, int value) +static int dwc2_udc_set_halt(struct usb_ep *_ep, int value) { - struct s3c_ep *ep; - struct s3c_udc *dev; + struct dwc2_ep *ep; + struct dwc2_udc *dev; unsigned long flags = 0; u8 ep_num; - ep = container_of(_ep, struct s3c_ep, ep); + ep = container_of(_ep, struct dwc2_ep, ep); ep_num = ep_index(ep); if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON || @@ -1050,7 +1050,7 @@ static int s3c_udc_set_halt(struct usb_ep *_ep, int value) if (value && ep_is_in(ep) && !list_empty(&ep->queue)) { debug("%s: %s queue not empty, req = %p\n", __func__, ep->ep.name, - list_entry(ep->queue.next, struct s3c_request, queue)); + list_entry(ep->queue.next, struct dwc2_request, queue)); return -EAGAIN; } @@ -1062,13 +1062,13 @@ static int s3c_udc_set_halt(struct usb_ep *_ep, int value) if (value == 0) { ep->stopped = 0; - s3c_udc_ep_clear_stall(ep); + dwc2_udc_ep_clear_stall(ep); } else { if (ep_num == 0) dev->ep0state = WAIT_FOR_SETUP; ep->stopped = 1; - s3c_udc_ep_set_stall(ep); + dwc2_udc_ep_set_stall(ep); } spin_unlock_irqrestore(&dev->lock, flags); @@ -1076,7 +1076,7 @@ static int s3c_udc_set_halt(struct usb_ep *_ep, int value) return 0; } -void s3c_udc_ep_activate(struct s3c_ep *ep) +static void dwc2_udc_ep_activate(struct dwc2_ep *ep) { u8 ep_num; u32 ep_ctrl = 0, daintmsk = 0; @@ -1123,13 +1123,13 @@ void s3c_udc_ep_activate(struct s3c_ep *ep) } -static int s3c_udc_clear_feature(struct usb_ep *_ep) +static int dwc2_udc_clear_feature(struct usb_ep *_ep) { - struct s3c_udc *dev; - struct s3c_ep *ep; + struct dwc2_udc *dev; + struct dwc2_ep *ep; u8 ep_num; - ep = container_of(_ep, struct s3c_ep, ep); + ep = container_of(_ep, struct dwc2_ep, ep); ep_num = ep_index(ep); dev = ep->dev; @@ -1158,7 +1158,7 @@ static int s3c_udc_clear_feature(struct usb_ep *_ep) break; } - s3c_udc_ep0_zlp(dev); + dwc2_udc_ep0_zlp(dev); break; case USB_RECIP_ENDPOINT: @@ -1168,14 +1168,14 @@ static int s3c_udc_clear_feature(struct usb_ep *_ep) if (usb_ctrl->wValue == USB_ENDPOINT_HALT) { if (ep_num == 0) { - s3c_udc_ep0_set_stall(ep); + dwc2_udc_ep0_set_stall(ep); return 0; } - s3c_udc_ep0_zlp(dev); + dwc2_udc_ep0_zlp(dev); - s3c_udc_ep_clear_stall(ep); - s3c_udc_ep_activate(ep); + dwc2_udc_ep_clear_stall(ep); + dwc2_udc_ep_activate(ep); ep->stopped = 0; clear_feature_num = ep_num; @@ -1187,13 +1187,13 @@ static int s3c_udc_clear_feature(struct usb_ep *_ep) return 0; } -static int s3c_udc_set_feature(struct usb_ep *_ep) +static int dwc2_udc_set_feature(struct usb_ep *_ep) { - struct s3c_udc *dev; - struct s3c_ep *ep; + struct dwc2_udc *dev; + struct dwc2_ep *ep; u8 ep_num; - ep = container_of(_ep, struct s3c_ep, ep); + ep = container_of(_ep, struct dwc2_ep, ep); ep_num = ep_index(ep); dev = ep->dev; @@ -1232,7 +1232,7 @@ static int s3c_udc_set_feature(struct usb_ep *_ep) break; } - s3c_udc_ep0_zlp(dev); + dwc2_udc_ep0_zlp(dev); return 0; case USB_RECIP_INTERFACE: @@ -1245,14 +1245,14 @@ static int s3c_udc_set_feature(struct usb_ep *_ep) "\tSET_FEATURE: USB_RECIP_ENDPOINT\n"); if (usb_ctrl->wValue == USB_ENDPOINT_HALT) { if (ep_num == 0) { - s3c_udc_ep0_set_stall(ep); + dwc2_udc_ep0_set_stall(ep); return 0; } ep->stopped = 1; - s3c_udc_ep_set_stall(ep); + dwc2_udc_ep_set_stall(ep); } - s3c_udc_ep0_zlp(dev); + dwc2_udc_ep0_zlp(dev); return 0; } @@ -1262,9 +1262,9 @@ static int s3c_udc_set_feature(struct usb_ep *_ep) /* * WAIT_FOR_SETUP (OUT_PKT_RDY) */ -void s3c_ep0_setup(struct s3c_udc *dev) +static void dwc2_ep0_setup(struct dwc2_udc *dev) { - struct s3c_ep *ep = &dev->ep[0]; + struct dwc2_ep *ep = &dev->ep[0]; int i; u8 ep_num; @@ -1272,7 +1272,7 @@ void s3c_ep0_setup(struct s3c_udc *dev) nuke(ep, -EPROTO); /* read control req from fifo (8 bytes) */ - s3c_fifo_read(ep, (u32 *)usb_ctrl, 8); + dwc2_fifo_read(ep, (u32 *)usb_ctrl, 8); debug_cond(DEBUG_SETUP != 0, "%s: bRequestType = 0x%x(%s), bRequest = 0x%x" @@ -1306,7 +1306,7 @@ void s3c_ep0_setup(struct s3c_udc *dev) "wLength = %d, setup returned\n", usb_ctrl->wLength); - s3c_udc_ep0_set_stall(ep); + dwc2_udc_ep0_set_stall(ep); dev->ep0state = WAIT_FOR_SETUP; return; @@ -1317,7 +1317,7 @@ void s3c_ep0_setup(struct s3c_udc *dev) "%s:BOT Rest:invalid wLength =%d, setup returned\n", __func__, usb_ctrl->wLength); - s3c_udc_ep0_set_stall(ep); + dwc2_udc_ep0_set_stall(ep); dev->ep0state = WAIT_FOR_SETUP; return; @@ -1384,7 +1384,7 @@ void s3c_ep0_setup(struct s3c_udc *dev) break; case USB_REQ_GET_STATUS: - if (!s3c_udc_get_status(dev, usb_ctrl)) + if (!dwc2_udc_get_status(dev, usb_ctrl)) return; break; @@ -1392,7 +1392,7 @@ void s3c_ep0_setup(struct s3c_udc *dev) case USB_REQ_CLEAR_FEATURE: ep_num = usb_ctrl->wIndex & 0x7f; - if (!s3c_udc_clear_feature(&dev->ep[ep_num].ep)) + if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep)) return; break; @@ -1400,7 +1400,7 @@ void s3c_ep0_setup(struct s3c_udc *dev) case USB_REQ_SET_FEATURE: ep_num = usb_ctrl->wIndex & 0x7f; - if (!s3c_udc_set_feature(&dev->ep[ep_num].ep)) + if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep)) return; break; @@ -1427,7 +1427,7 @@ void s3c_ep0_setup(struct s3c_udc *dev) if (i < 0) { /* setup processing failed, force stall */ - s3c_udc_ep0_set_stall(ep); + dwc2_udc_ep0_set_stall(ep); dev->ep0state = WAIT_FOR_SETUP; debug_cond(DEBUG_SETUP != 0, @@ -1451,12 +1451,12 @@ void s3c_ep0_setup(struct s3c_udc *dev) /* * handle ep0 interrupt */ -static void s3c_handle_ep0(struct s3c_udc *dev) +static void dwc2_handle_ep0(struct dwc2_udc *dev) { if (dev->ep0state == WAIT_FOR_SETUP) { debug_cond(DEBUG_OUT_EP != 0, "%s: WAIT_FOR_SETUP\n", __func__); - s3c_ep0_setup(dev); + dwc2_ep0_setup(dev); } else { debug_cond(DEBUG_OUT_EP != 0, @@ -1465,16 +1465,16 @@ static void s3c_handle_ep0(struct s3c_udc *dev) } } -static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep) +static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep) { debug_cond(DEBUG_EP0 != 0, "%s: ep_is_in = %d\n", __func__, ep_is_in(ep)); if (ep_is_in(ep)) { dev->ep0state = DATA_STATE_XMIT; - s3c_ep0_write(dev); + dwc2_ep0_write(dev); } else { dev->ep0state = DATA_STATE_RECV; - s3c_ep0_read(dev); + dwc2_ep0_read(dev); } } diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 2a2bffe..39f7185 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -26,6 +26,14 @@ config USB_XHCI_UNIPHIER endif +config USB_OHCI_GENERIC + bool "Support for generic OHCI USB controller" + depends on OF_CONTROL + depends on DM_USB + default n + ---help--- + Enables support for generic OHCI controller. + config USB_EHCI_HCD bool "EHCI HCD (USB 2.0) support" ---help--- @@ -73,4 +81,12 @@ config USB_EHCI_UNIPHIER ---help--- Enables support for the on-chip EHCI controller on UniPhier SoCs. +config USB_EHCI_GENERIC + bool "Support for generic EHCI USB controller" + depends on OF_CONTROL + depends on DM_USB + default n + ---help--- + Enables support for generic EHCI controller. + endif diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index f70f38c..6183b80 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o +obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o # echi obj-$(CONFIG_USB_EHCI) += ehci-hcd.o @@ -32,6 +33,7 @@ else obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o endif obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o +obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o @@ -54,6 +56,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o +obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 541c0f9..5ef6deb 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -823,12 +823,13 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, (*pid << DWC2_HCTSIZ_PID_OFFSET), &hc_regs->hctsiz); - if (!in) { - memcpy(priv->aligned_buffer, (char *)buffer + done, len); + if (!in && xfer_len) { + memcpy(priv->aligned_buffer, (char *)buffer + done, + xfer_len); flush_dcache_range((unsigned long)priv->aligned_buffer, (unsigned long)((void *)priv->aligned_buffer + - roundup(len, ARCH_DMA_MINALIGN))); + roundup(xfer_len, ARCH_DMA_MINALIGN))); } writel(phys_to_bus((unsigned long)priv->aligned_buffer), diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index 18e9251..bede04b 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -219,14 +219,14 @@ static int ehci_usb_probe(struct udevice *dev) ctx->hcd = (struct ehci_hccr *)plat->hcd_base; ctx->usb = (struct exynos_usb_phy *)plat->phy_base; - hcor = (struct ehci_hcor *)((uint32_t)ctx->hcd + - HC_LENGTH(ehci_readl(&ctx->hcd->cr_capbase))); /* setup the Vbus gpio here */ if (dm_gpio_is_valid(&plat->vbus_gpio)) dm_gpio_set_value(&plat->vbus_gpio, 1); setup_usb_phy(ctx->usb); + hcor = (struct ehci_hcor *)((uint32_t)ctx->hcd + + HC_LENGTH(ehci_readl(&ctx->hcd->cr_capbase))); return ehci_register(dev, ctx->hcd, hcor, NULL, 0, USB_INIT_HOST); } diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c new file mode 100644 index 0000000..1292caa --- /dev/null +++ b/drivers/usb/host/ehci-generic.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2015 Alexey Brodkin <abrodkin@synopsys.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include "ehci.h" + +/* + * Even though here we don't explicitly use "struct ehci_ctrl" + * ehci_register() expects it to be the first thing that resides in + * device's private data. + */ +struct generic_ehci { + struct ehci_ctrl ctrl; +}; + +static int ehci_usb_probe(struct udevice *dev) +{ + struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev); + struct ehci_hcor *hcor; + + hcor = (struct ehci_hcor *)((uintptr_t)hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); +} + +static int ehci_usb_remove(struct udevice *dev) +{ + return ehci_deregister(dev); +} + +static const struct udevice_id ehci_usb_ids[] = { + { .compatible = "generic-ehci" }, + { } +}; + +U_BOOT_DRIVER(ehci_generic) = { + .name = "ehci_generic", + .id = UCLASS_USB, + .of_match = ehci_usb_ids, + .probe = ehci_usb_probe, + .remove = ehci_usb_remove, + .ops = &ehci_usb_ops, + .priv_auto_alloc_size = sizeof(struct generic_ehci), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index c85dbce..c664b16 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -279,56 +279,16 @@ static inline u8 ehci_encode_speed(enum usb_device_speed speed) static void ehci_update_endpt2_dev_n_port(struct usb_device *udev, struct QH *qh) { - struct usb_device *ttdev; - int parent_devnum; + uint8_t portnr = 0; + uint8_t hubaddr = 0; if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL) return; - /* - * For full / low speed devices we need to get the devnum and portnr of - * the tt, so of the first upstream usb-2 hub, there may be usb-1 hubs - * in the tree before that one! - */ -#ifdef CONFIG_DM_USB - /* - * When called from usb-uclass.c: usb_scan_device() udev->dev points - * to the parent udevice, not the actual udevice belonging to the - * udev as the device is not instantiated yet. So when searching - * for the first usb-2 parent start with udev->dev not - * udev->dev->parent . - */ - struct udevice *parent; - struct usb_device *uparent; - - ttdev = udev; - parent = udev->dev; - uparent = dev_get_parent_priv(parent); - - while (uparent->speed != USB_SPEED_HIGH) { - struct udevice *dev = parent; - - if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) { - printf("ehci: Error cannot find high-speed parent of usb-1 device\n"); - return; - } - - ttdev = dev_get_parent_priv(dev); - parent = dev->parent; - uparent = dev_get_parent_priv(parent); - } - parent_devnum = uparent->devnum; -#else - ttdev = udev; - while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH) - ttdev = ttdev->parent; - if (!ttdev->parent) - return; - parent_devnum = ttdev->parent->devnum; -#endif + usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr); - qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(ttdev->portnr) | - QH_ENDPT2_HUBADDR(parent_devnum)); + qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) | + QH_ENDPT2_HUBADDR(hubaddr)); } static int diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index 38d5f92..d494ca1 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -87,7 +87,7 @@ static const struct udevice_id ehci_usb_ids[] = { { } }; -U_BOOT_DRIVER(usb_ehci) = { +U_BOOT_DRIVER(ehci_sunxi) = { .name = "ehci_sunxi", .id = UCLASS_USB, .of_match = ehci_usb_ids, diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c new file mode 100644 index 0000000..f3307f4 --- /dev/null +++ b/drivers/usb/host/ohci-generic.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2015 Alexey Brodkin <abrodkin@synopsys.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include "ohci.h" + +#if !defined(CONFIG_USB_OHCI_NEW) +# error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW" +#endif + +struct generic_ohci { + ohci_t ohci; +}; + +static int ohci_usb_probe(struct udevice *dev) +{ + struct ohci_regs *regs = (struct ohci_regs *)dev_get_addr(dev); + + return ohci_register(dev, regs); +} + +static int ohci_usb_remove(struct udevice *dev) +{ + return ohci_deregister(dev); +} + +static const struct udevice_id ohci_usb_ids[] = { + { .compatible = "generic-ohci" }, + { } +}; + +U_BOOT_DRIVER(ohci_generic) = { + .name = "ohci_generic", + .id = UCLASS_USB, + .of_match = ohci_usb_ids, + .probe = ohci_usb_probe, + .remove = ohci_usb_remove, + .ops = &ohci_usb_ops, + .priv_auto_alloc_size = sizeof(struct generic_ohci), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index c722c50..33961cd 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -44,6 +44,8 @@ void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) /* reset USB3 phy - if required */ dwc3_phy_reset(dwc3_reg); + mdelay(100); + /* After PHYs are stable we can take Core out of reset state */ clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); } diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index 6481e07..05f09d7 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -27,23 +27,6 @@ __weak int __board_usb_init(int index, enum usb_init_type init) return 0; } -void usb_phy_reset(struct dwc3 *dwc3_reg) -{ - /* Assert USB3 PHY reset */ - setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); - - /* Assert USB2 PHY reset */ - setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); - - mdelay(200); - - /* Clear USB3 PHY reset */ - clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); - - /* Clear USB2 PHY reset */ - clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); -} - static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci) { int ret = 0; diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c index 104e7a7..fd19f79 100644 --- a/drivers/usb/host/xhci-omap.c +++ b/drivers/usb/host/xhci-omap.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct omap_xhci omap; -inline int __board_usb_init(int index, enum usb_init_type init) +__weak int __board_usb_init(int index, enum usb_init_type init) { return 0; } diff --git a/drivers/usb/host/xhci-zynqmp.c b/drivers/usb/host/xhci-zynqmp.c new file mode 100644 index 0000000..a735369 --- /dev/null +++ b/drivers/usb/host/xhci-zynqmp.c @@ -0,0 +1,126 @@ +/* + * Copyright 2015 Xilinx, Inc. + * + * Zynq USB HOST xHCI Controller + * + * Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com> + * + * This file was reused from Freescale USB xHCI + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <usb.h> +#include <asm-generic/errno.h> +#include <asm/arch-zynqmp/hardware.h> +#include <linux/compat.h> +#include <linux/usb/dwc3.h> +#include "xhci.h" + +/* Declare global data pointer */ +DECLARE_GLOBAL_DATA_PTR; + +/* Default to the ZYNQMP XHCI defines */ +#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 +#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC +#define USB3_PHY_PARTIAL_RX_POWERON BIT(6) +#define USB3_PHY_RX_POWERON BIT(14) +#define USB3_PHY_TX_POWERON BIT(15) +#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) +#define USB3_PWRCTL_CLK_CMD_SHIFT 14 +#define USB3_PWRCTL_CLK_FREQ_SHIFT 22 + +/* USBOTGSS_WRAPPER definitions */ +#define USBOTGSS_WRAPRESET BIT(17) +#define USBOTGSS_DMADISABLE BIT(16) +#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) +#define USBOTGSS_STANDBYMODE_SMRT BIT(5) +#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) +#define USBOTGSS_IDLEMODE_NOIDLE BIT(2) +#define USBOTGSS_IDLEMODE_SMRT BIT(3) +#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) + +/* USBOTGSS_IRQENABLE_SET_0 bit */ +#define USBOTGSS_COREIRQ_EN BIT(1) + +/* USBOTGSS_IRQENABLE_SET_1 bits */ +#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) +#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) +#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) +#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) + +struct zynqmp_xhci { + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; +}; + +static struct zynqmp_xhci zynqmp_xhci; + +unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST; + +static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci) +{ + int ret = 0; + + ret = dwc3_core_init(zynqmp_xhci->dwc3_reg); + if (ret) { + debug("%s:failed to initialize core\n", __func__); + return ret; + } + + /* We are hard-coding DWC3 core to Host Mode */ + dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); + + return ret; +} + +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) +{ + struct zynqmp_xhci *ctx = &zynqmp_xhci; + int ret = 0; + uint32_t hclen; + + if (index < 0 || index >= ARRAY_SIZE(ctr_addr)) + return -EINVAL; + + ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; + ctx->dwc3_reg = (struct dwc3 *)((void *)ctx->hcd + DWC3_REG_OFFSET); + + ret = board_usb_init(index, USB_INIT_HOST); + if (ret != 0) { + puts("Failed to initialize board for USB\n"); + return ret; + } + + ret = zynqmp_xhci_core_init(ctx); + if (ret < 0) { + puts("Failed to initialize xhci\n"); + return ret; + } + + *hccr = (struct xhci_hccr *)ctx->hcd; + hclen = HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)); + *hcor = (struct xhci_hcor *)((uintptr_t) *hccr + hclen); + + debug("zynqmp-xhci: init hccr %p and hcor %p hc_length %d\n", + *hccr, *hcor, hclen); + + return ret; +} + +void xhci_hcd_stop(int index) +{ + /* + * Currently zynqmp socs do not support PHY shutdown from + * sw. But this support may be added in future socs. + */ + + return; +} diff --git a/drivers/usb/musb-new/musb_host.c b/drivers/usb/musb-new/musb_host.c index 40b9c66..2515447 100644 --- a/drivers/usb/musb-new/musb_host.c +++ b/drivers/usb/musb-new/musb_host.c @@ -2092,9 +2092,13 @@ int musb_urb_enqueue( } #else if (tt_needed(musb, urb->dev)) { - u16 hub_port = find_tt(urb->dev); - qh->h_addr_reg = (u8) (hub_port >> 8); - qh->h_port_reg = (u8) (hub_port & 0xff); + uint8_t portnr = 0; + uint8_t hubaddr = 0; + usb_find_usb2_hub_address_port(urb->dev, + &hubaddr, + &portnr); + qh->h_addr_reg = hubaddr; + qh->h_port_reg = portnr; } #endif } diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index a146c08..5eb8d19 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -166,6 +166,17 @@ static void USBC_ConfigFIFO_Base(void) } /****************************************************************************** + * Needed for the DFU polling magic + ******************************************************************************/ + +static u8 last_int_usb; + +bool dfu_usb_get_reset(void) +{ + return !!(last_int_usb & MUSB_INTR_RESET); +} + +/****************************************************************************** * MUSB Glue code ******************************************************************************/ @@ -176,6 +187,7 @@ static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci) /* read and flush interrupts */ musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); + last_int_usb = musb->int_usb; if (musb->int_usb) musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb); musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); diff --git a/drivers/usb/musb-new/usb-compat.h b/drivers/usb/musb-new/usb-compat.h index 1c41e2a..760bd78 100644 --- a/drivers/usb/musb-new/usb-compat.h +++ b/drivers/usb/musb-new/usb-compat.h @@ -68,38 +68,6 @@ static inline int usb_hcd_unmap_urb_for_dma(struct usb_hcd *hcd, } #ifdef CONFIG_DM_USB -static inline u16 find_tt(struct usb_device *udev) -{ - struct udevice *parent; - struct usb_device *uparent, *ttdev; - - /* - * When called from usb-uclass.c: usb_scan_device() udev->dev points - * to the parent udevice, not the actual udevice belonging to the - * udev as the device is not instantiated yet. So when searching - * for the first usb-2 parent start with udev->dev not - * udev->dev->parent . - */ - ttdev = udev; - parent = udev->dev; - uparent = dev_get_parent_priv(parent); - - while (uparent->speed != USB_SPEED_HIGH) { - struct udevice *dev = parent; - - if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) { - printf("musb: Error cannot find high speed parent of usb-1 device\n"); - return 0; - } - - ttdev = dev_get_parent_priv(dev); - parent = dev->parent; - uparent = dev_get_parent_priv(parent); - } - - return (uparent->devnum << 8) | (ttdev->portnr - 1); -} - static inline struct usb_device *usb_dev_get_parent(struct usb_device *udev) { struct udevice *parent = udev->dev->parent; @@ -129,27 +97,6 @@ static inline struct usb_device *usb_dev_get_parent(struct usb_device *udev) return NULL; } #else -static inline u16 find_tt(struct usb_device *dev) -{ - u8 chid; - u8 hub; - - /* Find out the nearest parent which is high speed */ - while (dev->parent->parent != NULL) - if (dev->parent->speed != USB_SPEED_HIGH) - dev = dev->parent; - else - break; - - /* determine the port address at that hub */ - hub = dev->parent->devnum; - for (chid = 0; chid < USB_MAXCHILDREN; chid++) - if (dev->parent->children[chid] == dev) - break; - - return (hub << 8) | chid; -} - static inline struct usb_device *usb_dev_get_parent(struct usb_device *dev) { return dev->parent; diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c index 7a87478..cbac9f7 100644 --- a/drivers/video/ipu_disp.c +++ b/drivers/video/ipu_disp.c @@ -1117,7 +1117,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, reg &= 0x0000FFFF; __raw_writel(reg, DI_STP_REP(disp, 6)); __raw_writel(0, DI_STP_REP(disp, 7)); - __raw_writel(0, DI_STP_REP(disp, 9)); + __raw_writel(0, DI_STP_REP9(disp)); /* Init template microcode */ if (disp) { diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h index c2c134a..0d3fe06 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/ipu_regs.h @@ -338,6 +338,7 @@ struct ipu_dmfc { #define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1]) #define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1]) #define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2]) +#define DI_STP_REP9(di) (&DI_REG(di)->stp_rep9) #define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as) #define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen]) #define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set]) diff --git a/examples/api/libgenwrap.c b/examples/api/libgenwrap.c index c1afa5b..ba51007 100644 --- a/examples/api/libgenwrap.c +++ b/examples/api/libgenwrap.c @@ -16,46 +16,14 @@ #include "glue.h" -/* - * printf() and vprintf() are stolen from u-boot/common/console.c - */ -int printf (const char *fmt, ...) -{ - va_list args; - uint i; - char printbuffer[256]; - - va_start (args, fmt); - - /* For this to work, printbuffer must be larger than - * anything we ever want to print. - */ - i = vsprintf (printbuffer, fmt, args); - va_end (args); - - /* Print the string */ - ub_puts (printbuffer); - return i; -} - -int vprintf (const char *fmt, va_list args) +void putc(const char c) { - uint i; - char printbuffer[256]; - - /* For this to work, printbuffer must be larger than - * anything we ever want to print. - */ - i = vsprintf (printbuffer, fmt, args); - - /* Print the string */ - ub_puts (printbuffer); - return i; + ub_putc(c); } -void putc (const char c) +void puts(const char *s) { - ub_putc(c); + ub_puts(s); } void __udelay(unsigned long usec) diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index 727a2f7..e73223a 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -1920,6 +1920,11 @@ int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, if (status < 0) return 0; + if (dirent.direntlen == 0) { + printf("Failed to iterate over directory %s\n", name); + return 0; + } + if (dirent.namelen != 0) { char filename[dirent.namelen + 1]; struct ext2fs_node *fdiro; diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 1abdcaa..5d8b043 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -59,6 +59,20 @@ typedef struct global_data { unsigned long relocaddr; /* Start address of U-Boot in RAM */ phys_size_t ram_size; /* RAM size */ +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#define MEM_RESERVE_SECURE_SECURED 0x1 +#define MEM_RESERVE_SECURE_MAINTAINED 0x2 +#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3) + /* + * Secure memory addr + * This variable needs maintenance if the RAM base is not zero, + * or if RAM splits into non-consecutive banks. It also has a + * flag indicating the secure memory is marked as secure by MMU. + * Flags used: 0x1 secured + * 0x2 maintained + */ + phys_addr_t secure_ram; +#endif unsigned long mon_len; /* monitor len */ unsigned long irq_sp; /* irq stack pointer */ unsigned long start_addr_sp; /* start_addr_stackpointer */ diff --git a/include/axp818.h b/include/axp818.h new file mode 100644 index 0000000..1dc6456 --- /dev/null +++ b/include/axp818.h @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> + * + * X-Powers AXP818 Power Management IC driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define AXP818_CHIP_ID 0x03 + +#define AXP818_OUTPUT_CTRL1 0x10 +#define AXP818_OUTPUT_CTRL1_DCDC1_EN (1 << 0) +#define AXP818_OUTPUT_CTRL1_DCDC2_EN (1 << 1) +#define AXP818_OUTPUT_CTRL1_DCDC3_EN (1 << 2) +#define AXP818_OUTPUT_CTRL1_DCDC4_EN (1 << 3) +#define AXP818_OUTPUT_CTRL1_DCDC5_EN (1 << 4) +#define AXP818_OUTPUT_CTRL1_DCDC6_EN (1 << 5) +#define AXP818_OUTPUT_CTRL1_DCDC7_EN (1 << 6) +#define AXP818_OUTPUT_CTRL2 0x12 +#define AXP818_OUTPUT_CTRL2_ELDO1_EN (1 << 0) +#define AXP818_OUTPUT_CTRL2_ELDO2_EN (1 << 1) +#define AXP818_OUTPUT_CTRL2_ELDO3_EN (1 << 2) +#define AXP818_OUTPUT_CTRL2_DLDO1_EN (1 << 3) +#define AXP818_OUTPUT_CTRL2_DLDO2_EN (1 << 4) +#define AXP818_OUTPUT_CTRL2_DLDO3_EN (1 << 5) +#define AXP818_OUTPUT_CTRL2_DLDO4_EN (1 << 6) +#define AXP818_OUTPUT_CTRL3 0x13 +#define AXP818_OUTPUT_CTRL3_FLDO1_EN (1 << 2) +#define AXP818_OUTPUT_CTRL3_FLDO2_EN (1 << 3) +#define AXP818_OUTPUT_CTRL3_FLDO3_EN (1 << 4) +#define AXP818_OUTPUT_CTRL3_ALDO1_EN (1 << 5) +#define AXP818_OUTPUT_CTRL3_ALDO2_EN (1 << 6) +#define AXP818_OUTPUT_CTRL3_ALDO3_EN (1 << 7) + +#define AXP818_DCDC1_CTRL 0x20 +#define AXP818_DCDC2_CTRL 0x21 +#define AXP818_DCDC3_CTRL 0x22 +#define AXP818_DCDC4_CTRL 0x23 +#define AXP818_DCDC5_CTRL 0x24 +#define AXP818_DCDC6_CTRL 0x25 + +#define AXP818_DLDO1_CTRL 0x15 +#define AXP818_DLDO2_CTRL 0x16 +#define AXP818_DLDO3_CTRL 0x17 +#define AXP818_DLDO4_CTRL 0x18 +#define AXP818_ELDO1_CTRL 0x19 +#define AXP818_ELDO2_CTRL 0x1a +#define AXP818_ELDO3_CTRL 0x1b +#define AXP818_ELDO3_CTRL 0x1b +#define AXP818_FLDO1_CTRL 0x1c +#define AXP818_FLDO2_3_CTRL 0x1d +#define AXP818_DCDC1_CTRL 0x20 +#define AXP818_DCDC2_CTRL 0x21 +#define AXP818_DCDC3_CTRL 0x22 +#define AXP818_DCDC4_CTRL 0x23 +#define AXP818_DCDC5_CTRL 0x24 +#define AXP818_DCDC6_CTRL 0x25 +#define AXP818_DCDC7_CTRL 0x26 + +#define AXP818_ALDO1_CTRL 0x28 +#define AXP818_ALDO2_CTRL 0x29 +#define AXP818_ALDO3_CTRL 0x2a + +int axp818_init(void); + +/* For axp_gpio.c */ +#define AXP_POWER_STATUS 0x00 +#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_GPIO0_CTRL 0x90 +#define AXP_GPIO1_CTRL 0x92 +#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ +#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ +#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ +#define AXP_GPIO_STATE 0x94 +#define AXP_GPIO_STATE_OFFSET 0 diff --git a/include/axp_pmic.h b/include/axp_pmic.h index ef339c4..3b01c49 100644 --- a/include/axp_pmic.h +++ b/include/axp_pmic.h @@ -16,6 +16,9 @@ #ifdef CONFIG_AXP221_POWER #include <axp221.h> #endif +#ifdef CONFIG_AXP818_POWER +#include <axp818.h> +#endif int axp_set_dcdc1(unsigned int mvolt); int axp_set_dcdc2(unsigned int mvolt); diff --git a/include/command.h b/include/command.h index 6c04cd9..2ae9b6c 100644 --- a/include/command.h +++ b/include/command.h @@ -142,6 +142,7 @@ enum command_ret_t { int cmd_process(int flag, int argc, char * const argv[], int *repeatable, unsigned long *ticks); +void fixup_cmdtable(cmd_tbl_t *cmdtp, int size); #endif /* __ASSEMBLY__ */ /* @@ -179,8 +180,4 @@ int cmd_process(int flag, int argc, char * const argv[], #define U_BOOT_CMD(_name, _maxargs, _rep, _cmd, _usage, _help) \ U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, NULL) -#if defined(CONFIG_NEEDS_MANUAL_RELOC) -void fixup_cmdtable(cmd_tbl_t *cmdtp, int size); -#endif - #endif /* __COMMAND_H */ diff --git a/include/common.h b/include/common.h index e910730..75c78d5 100644 --- a/include/common.h +++ b/include/common.h @@ -432,7 +432,6 @@ int get_env_id (void); void pci_init (void); void pci_init_board(void); -void pciinfo (int, int); #if defined(CONFIG_PCI) && defined(CONFIG_4xx) int pci_pre_init (struct pci_controller *); @@ -474,10 +473,7 @@ void reset_phy (void); void fdc_hw_init (void); /* $(BOARD)/eeprom.c */ -void eeprom_init (void); -#ifndef CONFIG_SPI -int eeprom_probe (unsigned dev_addr, unsigned offset); -#endif +void eeprom_init (int bus); int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 48d5063..8dfe2a8 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -20,6 +20,7 @@ */ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */ +#define CONFIG_SYS_NS16550_MEM32 /* * Flash @@ -53,19 +54,6 @@ #define CONFIG_LMB /* - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - */ -#define CONFIG_ENV_IS_IN_FLASH - -#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR 0xf4040000 - -/* * MEMORY ORGANIZATION * -Monitor at top of sdram. * -The heap is placed below the monitor @@ -75,13 +63,26 @@ #define CONFIG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */ +#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_SDRAM_SIZE - \ CONFIG_SYS_MONITOR_LEN) #define CONFIG_SYS_MALLOC_LEN 0x20000 /* + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + */ +#define CONFIG_ENV_IS_IN_FLASH + +#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CONFIG_ENV_ADDR (0xf4000000 + CONFIG_SYS_MONITOR_LEN) + +/* * MISC */ #define CONFIG_SYS_LONGHELP /* Provide extended help */ @@ -91,12 +92,15 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + \ 16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_LOAD_ADDR 0xcc000000 /* Half of RAM */ +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \ CONFIG_ENV_SIZE - \ CONFIG_SYS_MALLOC_LEN - \ 0x10000) +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING #endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index 2ecdd5d..2e94b69 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -57,19 +57,6 @@ #define CONFIG_LMB /* - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - */ -#define CONFIG_ENV_IS_IN_FLASH - -#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR 0xe2840000 - -/* * MEMORY ORGANIZATION * -Monitor at top of sdram. * -The heap is placed below the monitor @@ -79,13 +66,26 @@ #define CONFIG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */ +#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_SDRAM_SIZE - \ CONFIG_SYS_MONITOR_LEN) #define CONFIG_SYS_MALLOC_LEN 0x20000 /* + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + */ +#define CONFIG_ENV_IS_IN_FLASH + +#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CONFIG_ENV_ADDR (0xe2800000 + CONFIG_SYS_MONITOR_LEN) + +/* * MISC */ #define CONFIG_SYS_LONGHELP /* Provide extended help */ @@ -95,12 +95,15 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + \ 16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */ +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \ CONFIG_ENV_SIZE - \ CONFIG_SYS_MALLOC_LEN - \ 0x10000) +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING #endif /* __CONFIG_H */ diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index c83e5ce..9fb5cee 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -483,7 +483,6 @@ unsigned long get_board_ddr_clk(void); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -587,8 +586,6 @@ unsigned long get_board_ddr_clk(void); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SST #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 2754016..4b5ad0e 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -227,7 +227,6 @@ extern unsigned long get_sdram_size(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -267,7 +266,6 @@ extern unsigned long get_sdram_size(void); /* I2C EEPROM */ #define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -275,10 +273,8 @@ extern unsigned long get_sdram_size(void); #define CONFIG_CMD_I2C -#define CONFIG_FSL_ESPI /* eSPI - Enhanced SPI */ #ifdef CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 54dcf3b..d0e5a25 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -408,7 +408,6 @@ combinations. this should be removed later /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -463,7 +462,6 @@ combinations. this should be removed later /* enable read and write access to EEPROM */ #define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -480,9 +478,7 @@ combinations. this should be removed later * used for SLIC */ /* eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI /* SPI */ #ifdef CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 94f991b..16920c6 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -377,7 +377,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -420,7 +419,6 @@ /* I2C EEPROM */ /* enable read and write access to EEPROM */ #define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -428,9 +426,6 @@ #define CONFIG_CMD_I2C /* eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_SPI_FLASH_EON #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index e00ab04..c3a7714 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -89,7 +89,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 332a1df..1e5285c 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -113,7 +113,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index ffee225..f2ea9a8 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -131,7 +131,6 @@ #define CONFIG_SYS_SBFHDR_SIZE 0x7 #ifdef CONFIG_CMD_SPI # define CONFIG_SYS_DSPI_CS2 -# define CONFIG_SPI_FLASH_STMICRO # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ DSPI_CTAR_PCSSCK_1CLK | \ diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index 927b7da..05ba13b 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -193,7 +193,6 @@ #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x7 #ifdef CONFIG_CMD_SPI -# define CONFIG_SPI_FLASH_ATMEL # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ DSPI_CTAR_PCSSCK_1CLK | \ diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 61ebb24..c778823 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -141,7 +141,6 @@ #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x7 #ifdef CONFIG_CMD_SPI -# define CONFIG_SPI_FLASH_STMICRO # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ DSPI_CTAR_PCSSCK_1CLK | \ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index f813dab..7941040 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -173,7 +173,6 @@ #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x13 #ifdef CONFIG_CMD_SPI -# define CONFIG_SPI_FLASH_STMICRO # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ DSPI_CTAR_PCSSCK_1CLK | \ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index ba93c18..1a793d7 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -160,7 +160,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 551b72d..955ce62 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -315,7 +315,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -354,7 +353,6 @@ #ifdef CONFIG_MPC8XXX_SPI #define CONFIG_CMD_SPI #define CONFIG_USE_SPIFLASH -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #endif diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 44c3175..fa6dd6f 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -370,7 +370,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index eb50be6..ba952e3 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -292,7 +292,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 59d5e56..a1d45d8 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -212,7 +212,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 5ab7d5f..b3322ae 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -292,7 +292,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 988a900..71dcc6c 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -318,7 +318,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 091ca17..ded73b4 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -353,7 +353,6 @@ boards, we say we have two, but don't display a message if we find only one. */ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 7d1262d..df47888 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -308,7 +308,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index ab68e63..e77848e 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -329,7 +329,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index f582f55..294be3b 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -368,7 +368,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -420,10 +419,8 @@ * eSPI - Enhanced SPI */ #define CONFIG_HARD_SPI -#define CONFIG_FSL_ESPI #if defined(CONFIG_SPI_FLASH) -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 157ca69..921180f 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -221,7 +221,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 68ea5d8..d5805c1 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -244,7 +244,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 6ec072c..0fa5fd3 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -196,7 +196,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 517b449..a84ebfd 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -321,7 +321,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 184f514..84b8174 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -242,7 +242,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index f6e43ce..03ba806 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -227,7 +227,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 6f614b0..f86d10f 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -235,7 +235,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 9b131a2..b34a033 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -364,7 +364,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 4ce04a8..8160b28 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -225,7 +225,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index a5dad2d..a84db51 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -259,7 +259,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 81b0855..f9776c0 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -604,7 +604,6 @@ extern unsigned long get_sdram_size(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -660,7 +659,6 @@ extern unsigned long get_sdram_size(void); #endif /* enable read and write access to EEPROM */ #define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -677,8 +675,6 @@ extern unsigned long get_sdram_size(void); */ #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) /* eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index a9d825b..6235bbb 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -393,7 +393,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -478,10 +477,8 @@ /* * eSPI - Enhanced SPI */ -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_HARD_SPI -#define CONFIG_FSL_ESPI #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 4d87198..bc479f6 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -162,7 +162,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 2c4c8b5..b2e51b5 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -324,7 +324,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -410,8 +409,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index aac5a4d..b5959c8 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -153,7 +153,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index d668a15..4eb5fe1 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -114,7 +114,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 0fdd7e2..ce0c49f 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -88,7 +88,6 @@ #define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */ #define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 0227649..05ad315 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -84,7 +84,6 @@ * Serial Port *----------------------------------------------------------------------*/ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() @@ -159,7 +158,6 @@ #define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 52942ed..951cbc4 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -495,7 +495,6 @@ unsigned long get_board_ddr_clk(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -579,11 +578,7 @@ unsigned long get_board_ddr_clk(void); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_STMICRO #ifndef CONFIG_SPL_BUILD -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_EON #endif #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_BAR diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 39fa5e2..4a0f5b2 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -496,7 +496,6 @@ unsigned long get_board_ddr_clk(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -568,11 +567,8 @@ unsigned long get_board_ddr_clk(void); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI #if defined(CONFIG_T1024RDB) -#define CONFIG_SPI_FLASH_STMICRO #elif defined(CONFIG_T1023RDB) -#define CONFIG_SPI_FLASH_SPANSION #endif #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_BAR diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index fc263df..9e151da 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -398,7 +398,6 @@ unsigned long get_board_ddr_clk(void); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -483,10 +482,6 @@ unsigned long get_board_ddr_clk(void); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_EON #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 840be04..da65f56 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -450,7 +450,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -538,8 +537,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_BAR #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index a81f1e6..a0cecc6 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -445,7 +445,6 @@ unsigned long get_board_ddr_clk(void); * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -551,11 +550,7 @@ unsigned long get_board_ddr_clk(void); * eSPI - Enhanced SPI */ #ifdef CONFIG_SPI_FLASH -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_STMICRO #ifndef CONFIG_SPL_BUILD -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_EON #endif #define CONFIG_CMD_SF diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 8b76234..312b0eb 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -405,7 +405,6 @@ unsigned long get_board_ddr_clk(void); * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -505,8 +504,6 @@ unsigned long get_board_ddr_clk(void); * eSPI - Enhanced SPI */ #ifdef CONFIG_SPI_FLASH -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_BAR #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 4edb3cb..1b94f64 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -401,8 +401,6 @@ unsigned long get_board_ddr_clk(void); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SST #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 2e875d2..73279c8 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -197,7 +197,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -610,8 +609,6 @@ unsigned long get_board_ddr_clk(void); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SST #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 0b046d1..58a17f5 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -158,7 +158,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -183,7 +182,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS /* more than one eeprom */ /* I2C RTC */ #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index ad2f115..2354009 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -329,7 +329,6 @@ */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -380,11 +379,7 @@ * eSPI - Enhanced SPI */ #define CONFIG_HARD_SPI -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SST 1 -#define CONFIG_SPI_FLASH_STMICRO 1 -#define CONFIG_SPI_FLASH_WINBOND 1 #define CONFIG_CMD_SF 1 #define CONFIG_CMD_SPI 1 #define CONFIG_SF_DEFAULT_SPEED 10000000 diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 60f266c..6cbf1b7 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -99,7 +99,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 4dd5720..2f53d73 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -120,7 +120,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index 849b08e..2499b39 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -87,7 +87,6 @@ /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ #define CONFIG_BAUDRATE 38400 #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE #define CONFIG_SYS_NS16550_REG_SIZE -4 diff --git a/include/configs/alt.h b/include/configs/alt.h index 6d2c242..6bd2983 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -42,7 +42,6 @@ /* FLASH */ #define CONFIG_SPI #define CONFIG_SH_QSPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_SPI_FLASH_QUAD #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ed3fd34..c51db8c 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -218,7 +218,6 @@ #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS /* PMIC support */ #define CONFIG_POWER_TPS65217 @@ -469,7 +468,6 @@ /* SPI flash. */ #define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_SPEED 24000000 /* Network. */ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index f655e69..1bdb96e 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -78,7 +78,6 @@ #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS /* PMIC support */ #define CONFIG_POWER_TPS65217 diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 0bf0af7..4ed8e00 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -66,7 +66,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 9aa14f4..23457d6 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -72,7 +72,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 76d4032..aac550a 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -22,13 +22,10 @@ #include <asm/arch/omap.h> /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_CLK 48000000 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_REG_SIZE (-4) -#else -#define CONFIG_OMAP_SERIAL #endif /* I2C Configuration */ @@ -36,7 +33,6 @@ #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS /* Power */ #define CONFIG_POWER @@ -223,8 +219,6 @@ /* SPI */ #undef CONFIG_OMAP3_SPI -#define CONFIG_TI_QSPI -#define CONFIG_SPI_FLASH_MACRONIX #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_TI_SPI_MMAP diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index e87c0cb..78d8044 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -19,7 +19,6 @@ /* * UART */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index fe1ef9d..e1eb700 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -49,10 +49,8 @@ /* PCI host support */ #define CONFIG_PCI -#define CONFIG_PCI_TEGRA #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM /* PCI networking support */ #define CONFIG_E1000_NO_NVM diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index f03297e..0b97ccc 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -43,7 +43,6 @@ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_MTD -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 8606151..828bc60 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -57,7 +57,7 @@ #define ENABLE_JFFS 1 #endif -/* Define which commmands should be available at u-boot command prompt */ +/* Define which commands should be available at u-boot command prompt */ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 8fa5ff5..ba91d1f 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -93,7 +93,6 @@ /* DataFlash */ #ifdef CONFIG_CMD_SF #define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_ENV_SPI_MODE SPI_MODE_3 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 20a5581..45bb861 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -92,7 +92,6 @@ /* DataFlash */ #ifdef CONFIG_CMD_SF #define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SF_DEFAULT_SPEED 30000000 #endif diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index c436fef..11d7d0c 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -100,7 +100,6 @@ #define CONFIG_GENERIC_MMC #define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index 3935811..0dcc192 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -120,7 +120,6 @@ #define CONFIG_GENERIC_MMC #define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/axs101.h b/include/configs/axs101.h index 9a7e0dc..98fff63 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -52,7 +52,6 @@ * UART configuration */ #define CONFIG_DW_SERIAL -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33333333 #define CONFIG_SYS_NS16550_MEM32 @@ -79,7 +78,6 @@ /* * EEPROM configuration */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 @@ -97,14 +95,14 @@ /* * Ethernet PHY configuration */ -#define CONFIG_PHYLIB #define CONFIG_MII #define CONFIG_PHY_GIGE /* - * Ethernet configuration + * USB 1.1 configuration */ -#define CONFIG_DW_AUTONEG +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 /* * Commands still not supported in Kconfig diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 5545cf0..e9b4fe1 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -213,7 +213,6 @@ #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS /* PMIC support */ #define CONFIG_POWER_TPS65910 diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 6ba4aaf..5b8b22f 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -139,7 +139,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index 9917627..e61a098 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -346,7 +346,6 @@ DEFAULT_LINUX_BOOT_ENV \ #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS /* PMIC support */ #define CONFIG_POWER_TPS65217 @@ -580,7 +579,6 @@ DEFAULT_LINUX_BOOT_ENV \ /* SPI flash. */ #define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_SPEED 24000000 /* Network. */ diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h index 7247907..a257084 100644 --- a/include/configs/bcm28155_ap.h +++ b/include/configs/bcm28155_ap.h @@ -79,7 +79,6 @@ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE /* Serial Info */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL /* Post pad 3 bytes after each reg addr */ #define CONFIG_SYS_NS16550_REG_SIZE (-4) @@ -143,7 +142,7 @@ #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 0 -#define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_DWC2_OTG #define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY #define CONFIG_USB_GADGET_DOWNLOAD #define CONFIG_USBID_ADDR 0x34052c46 diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h index c3ebb4d..305864f 100644 --- a/include/configs/bcm_ep_board.h +++ b/include/configs/bcm_ep_board.h @@ -45,7 +45,6 @@ #define CONFIG_ENV_OVERWRITE /* Serial Info */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 1790f60..3bed9a4 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -51,9 +51,7 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* SPI */ -#define CONFIG_TEGRA20_SLINK #define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI @@ -73,10 +71,8 @@ /* PCI host support */ #define CONFIG_PCI -#define CONFIG_PCI_TEGRA #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM /* PCI networking support */ #define CONFIG_RTL8169 diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h index 64db3ac..597f1cd 100644 --- a/include/configs/bf506f-ezkit.h +++ b/include/configs/bf506f-ezkit.h @@ -73,7 +73,6 @@ #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 /* -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_CMD_SF #define CONFIG_CMD_SPI */ diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index b7ceba4..84bb044 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -105,8 +105,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h index fce6fc2..d12963a 100644 --- a/include/configs/bf525-ucr2.h +++ b/include/configs/bf525-ucr2.h @@ -69,7 +69,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_HZ 30000000 -#define CONFIG_SPI_FLASH_EON #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_MAX_HZ 30000000 diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index a8f0979..35a2228 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -103,7 +103,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_SST /* diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h index 1c5fc9e..2f3dec5 100644 --- a/include/configs/bf527-ad7160-eval.h +++ b/include/configs/bf527-ad7160-eval.h @@ -89,7 +89,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index d23602b..aee7761 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -101,7 +101,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h index c57c862..4fbdca7 100644 --- a/include/configs/bf537-minotaur.h +++ b/include/configs/bf537-minotaur.h @@ -101,7 +101,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index e922bd5..2474adb 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -82,7 +82,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h index 90aeeec..89d2604 100644 --- a/include/configs/bf537-srv1.h +++ b/include/configs/bf537-srv1.h @@ -100,7 +100,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index f0f768a..65009c6 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -92,7 +92,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h index b3c6d29..92251fc 100644 --- a/include/configs/bf561-acvilon.h +++ b/include/configs/bf561-acvilon.h @@ -114,7 +114,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 10000000 #define CONFIG_SF_DEFAULT_SPEED 10000000 -#define CONFIG_SPI_FLASH_ATMEL /* diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 0e353b9..b5d4847 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -75,7 +75,6 @@ #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_CMD_MII #define CONFIG_MII -#define CONFIG_PHYLIB /* i2c Settings */ #define CONFIG_SYS_I2C diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 91a84fe..9c537e0 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -278,13 +278,6 @@ * SPI Settings */ #ifdef CONFIG_SPI_FLASH_ALL -# define CONFIG_SPI_FLASH_ATMEL -# define CONFIG_SPI_FLASH_EON -# define CONFIG_SPI_FLASH_MACRONIX -# define CONFIG_SPI_FLASH_SPANSION -# define CONFIG_SPI_FLASH_SST -# define CONFIG_SPI_FLASH_STMICRO -# define CONFIG_SPI_FLASH_WINBOND #endif /* diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h index 9abbc39..05c932f 100644 --- a/include/configs/bg0900.h +++ b/include/configs/bg0900.h @@ -48,7 +48,6 @@ /* SPI FLASH */ #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SF_DEFAULT_BUS 2 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 40000000 diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h index 3b7a47f..60650aa 100644 --- a/include/configs/blackstamp.h +++ b/include/configs/blackstamp.h @@ -216,7 +216,6 @@ /* For the M25P64 SCK Should be Kept < 15Mhz */ #define CONFIG_ENV_SPI_MAX_HZ 15000000 #define CONFIG_SF_DEFAULT_SPEED 15000000 -#define CONFIG_SPI_FLASH_STMICRO /* * FLASH organization and environment definitions diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h index 5b15e0e..16949aa 100644 --- a/include/configs/blackvme.h +++ b/include/configs/blackvme.h @@ -142,7 +142,6 @@ #define CONFIG_ENV_SPI_MAX_HZ 15000000 #define CONFIG_SF_DEFAULT_SPEED 15000000 -#define CONFIG_SPI_FLASH_STMICRO /* * Interactive command settings diff --git a/include/configs/br4.h b/include/configs/br4.h index 959f9a9..7dda472 100644 --- a/include/configs/br4.h +++ b/include/configs/br4.h @@ -82,7 +82,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index c9eb63e..ffc6811 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -46,7 +46,6 @@ #include <asm/arch/omap.h> /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000 diff --git a/include/configs/calimain.h b/include/configs/calimain.h index 7f942dc..e6b2d4d 100644 --- a/include/configs/calimain.h +++ b/include/configs/calimain.h @@ -151,7 +151,6 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index ed790cc..e136824 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -248,7 +248,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index ce6b158..c26a25c 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -54,9 +54,7 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* SPI */ -#define CONFIG_TEGRA20_SLINK #define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI @@ -75,10 +73,8 @@ /* PCI host support */ #define CONFIG_PCI -#define CONFIG_PCI_TEGRA #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM /* PCI networking support */ #define CONFIG_RTL8169 diff --git a/include/configs/chromebook_jerry.h b/include/configs/chromebook_jerry.h index a22b123..058325c 100644 --- a/include/configs/chromebook_jerry.h +++ b/include/configs/chromebook_jerry.h @@ -9,6 +9,7 @@ #include <configs/rk3288_common.h> +#define CONFIG_ENV_IS_NOWHERE #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 5f2f020..2dc745e 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -70,7 +70,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index 1c086fc..0aefec8 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -77,7 +77,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index c4d3b94..d3cd38d 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -18,9 +18,7 @@ #include <asm/arch/omap.h> /* Serial support */ -#define CONFIG_OMAP_SERIAL #define CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_COM1 0x44e09000 @@ -71,14 +69,6 @@ /* SPI Flash support */ #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_ATMEL -#define CONFIG_SPI_FLASH_EON -#define CONFIG_SPI_FLASH_GIGADEVICE -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_TI_SPI_MMAP #define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_SPEED 48000000 diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 9135d6c..708c79a 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -270,7 +270,6 @@ #ifdef CONFIG_OF_CONTROL #define CONFIG_DM_SPI #define CONFIG_CMD_SPI -#define CONFIG_FSL_DSPI #endif #endif /* __CONFIG_H */ diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 600bb83..641aa7c 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -178,7 +178,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -216,9 +215,7 @@ * eSPI - Enhanced SPI */ #define CONFIG_HARD_SPI -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 9210216..aef37dd 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -329,7 +329,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -415,8 +414,6 @@ /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index c052e8a..ffd65d5 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -29,7 +29,6 @@ #define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA} -#define CONFIG_SPI_FLASH_SST #define CONFIG_MMC #define CONFIG_SDHCI diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 5d25fb1..bc7cac4 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -215,7 +215,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -280,7 +279,6 @@ /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI /* * General PCI diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 5aa643a..63abb80 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -133,7 +133,6 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ @@ -142,8 +141,6 @@ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_CMD_SF #define CONFIG_DAVINCI_SPI #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 2251f59..944e82f 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -49,7 +49,6 @@ #define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */ /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 9a0596c..3673e5e 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -60,7 +60,6 @@ /* SPI NOR flash default params, used by sf commands */ #define CONFIG_SF_DEFAULT_SPEED 1000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 -#define CONFIG_SPI_FLASH_STMICRO /* * SDIO/MMC Card Configuration diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index b3b2de9..ab6e5a5 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -56,7 +56,6 @@ /* SPI NOR flash default params, used by sf commands */ #define CONFIG_SF_DEFAULT_SPEED 1000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 -#define CONFIG_SPI_FLASH_STMICRO /* Environment in SPI NOR flash */ #define CONFIG_ENV_IS_IN_SPI_FLASH diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index cb9544b..81070b1 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -135,8 +135,6 @@ /* SPI */ #undef CONFIG_OMAP3_SPI -#define CONFIG_TI_QSPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_TI_SPI_MMAP diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 3f35616..0b7d89b 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -61,7 +61,6 @@ #ifdef CONFIG_CMD_SF #define CONFIG_HARD_SPI 1 #define CONFIG_KIRKWOOD_SPI 1 -#define CONFIG_SPI_FLASH_MACRONIX 1 #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */ diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h index 998a69a..18a63d7 100644 --- a/include/configs/e2220-1170.h +++ b/include/configs/e2220-1170.h @@ -35,7 +35,6 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI diff --git a/include/configs/ea20.h b/include/configs/ea20.h index 53ad302..10b30c1 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -58,7 +58,6 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ @@ -67,7 +66,6 @@ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SPI -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_DAVINCI_SPI #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 7fb1894..1dfa721 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -88,7 +88,6 @@ * NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK diff --git a/include/configs/efi-x86.h b/include/configs/efi-x86.h index 1c955d9..258a83f 100644 --- a/include/configs/efi-x86.h +++ b/include/configs/efi-x86.h @@ -15,7 +15,6 @@ #undef CONFIG_CMD_IMLS -#undef CONFIG_SYS_NS16550 #undef CONFIG_X86_SERIAL #undef CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_IS_NOWHERE diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index f55ba9f..90cd959 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -65,7 +65,6 @@ #define CONFIG_CMD_SF #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_SST #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index d6e0456..23a2935 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -59,7 +59,6 @@ /* 512kB DataFlash at NPCS0 */ #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_HAS_DATAFLASH -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 #define DATAFLASH_TCSS (0x1a << 16) diff --git a/include/configs/evb_rk3036.h b/include/configs/evb_rk3036.h new file mode 100644 index 0000000..aa07889 --- /dev/null +++ b/include/configs/evb_rk3036.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/rk3036_common.h> + +#endif diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index ec1f882..d101a77 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -51,8 +51,8 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_S3C_UDC_OTG -#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY +#define CONFIG_USB_GADGET_DWC2_OTG +#define CONFIG_USB_GADGET_DWC2_OTG_PHY #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 5d2b4f3..9c3ea88 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -129,11 +129,8 @@ /* SPI */ #ifdef CONFIG_SPI_FLASH -#define CONFIG_EXYNOS_SPI #define CONFIG_CMD_SF #define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SPI_FLASH_GIGADEVICE #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 50000000 #endif diff --git a/include/configs/firefly-rk3288.h b/include/configs/firefly-rk3288.h index a82adc8..4c5c4dd 100644 --- a/include/configs/firefly-rk3288.h +++ b/include/configs/firefly-rk3288.h @@ -11,4 +11,12 @@ #define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +/* SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) + #endif diff --git a/include/configs/galileo.h b/include/configs/galileo.h index eb16a5e..14a42b1 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -45,7 +45,6 @@ /* 10/100M Ethernet support */ #define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_PHYLIB /* Environment configuration */ #define CONFIG_ENV_SECT_SIZE 0x1000 diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h index b514278..8d79ea8 100644 --- a/include/configs/gdppc440etx.h +++ b/include/configs/gdppc440etx.h @@ -66,7 +66,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/gose.h b/include/configs/gose.h index c08e73a..4e29825 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -44,7 +44,6 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_SPI #define CONFIG_SH_QSPI -#define CONFIG_SPI_FLASH_SPANSION /* SH Ether */ #define CONFIG_SH_ETHER diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index f2fd2ae..52c67d5 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -91,7 +91,6 @@ /* Flash Support */ #define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_ATMEL /* * mv-common.h should be defined after CMD configs since it used them diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h index 5bbf1aa..c3b1729 100644 --- a/include/configs/gr_cpci_ax2000.h +++ b/include/configs/gr_cpci_ax2000.h @@ -14,6 +14,9 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options * (easy to change) @@ -42,9 +45,6 @@ /* CPU / AMBA BUS configuration */ #define CONFIG_SYS_CLK_FREQ 20000000 /* 20MHz */ -/* Number of SPARC register windows */ -#define CONFIG_SYS_SPARC_NWINDOWS 8 - /* * Serial console configuration */ @@ -344,7 +344,7 @@ #undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1 /* Identification string */ -#define CONFIG_IDENT_STRING "GAISLER LEON3 GR-CPCI-AX2000" +#define CONFIG_IDENT_STRING " Gaisler LEON3 GR-CPCI-AX2000" /* default kernel command line */ #define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0" diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h index b55ca77..45163ed 100644 --- a/include/configs/gr_ep2s60.h +++ b/include/configs/gr_ep2s60.h @@ -15,6 +15,9 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options * (easy to change) @@ -26,9 +29,6 @@ /* CPU / AMBA BUS configuration */ #define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */ -/* Number of SPARC register windows */ -#define CONFIG_SYS_SPARC_NWINDOWS 8 - /* Define this is the GR-2S60-MEZZ mezzanine is available and you * want to use the USB and GRETH functionality of the board */ @@ -314,7 +314,7 @@ #undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1 /* Identification string */ -#define CONFIG_IDENT_STRING "GAISLER LEON3 EP2S60" +#define CONFIG_IDENT_STRING " Gaisler LEON3 EP2S60" /* default kernel command line */ #define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0" diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h index d086b69..f675b75 100644 --- a/include/configs/gr_xc3s_1500.h +++ b/include/configs/gr_xc3s_1500.h @@ -13,6 +13,9 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options * (easy to change) @@ -23,9 +26,6 @@ /* CPU / AMBA BUS configuration */ #define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ -/* Number of SPARC register windows */ -#define CONFIG_SYS_SPARC_NWINDOWS 8 - /* * Serial console configuration */ @@ -276,7 +276,7 @@ #undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1 /* Identification string */ -#define CONFIG_IDENT_STRING "GAISLER LEON3 GR-XC3S-1500" +#define CONFIG_IDENT_STRING " Gaisler LEON3 GR-XC3S-1500" /* default kernel command line */ #define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0" diff --git a/include/configs/grsim.h b/include/configs/grsim.h index e1f7dc3..47c3573 100644 --- a/include/configs/grsim.h +++ b/include/configs/grsim.h @@ -13,6 +13,9 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options * (easy to change) @@ -34,9 +37,6 @@ /* CPU / AMBA BUS configuration */ #define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ -/* Number of SPARC register windows */ -#define CONFIG_SYS_SPARC_NWINDOWS 8 - /* * Serial console configuration */ @@ -295,7 +295,7 @@ /* default kernel command line */ #define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0" -#define CONFIG_IDENT_STRING "Gaisler GRSIM" +#define CONFIG_IDENT_STRING " Gaisler GRSIM" /* TSIM command: * $ ./tsim-leon3 -mmu -cas diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h index 83fd7fa..0a5292e 100644 --- a/include/configs/grsim_leon2.h +++ b/include/configs/grsim_leon2.h @@ -3,8 +3,8 @@ * (C) Copyright 2003-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. + * (C) Copyright 2007, 2015 + * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -12,6 +12,9 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options * (easy to change) @@ -29,9 +32,6 @@ /* CPU / AMBA BUS configuration */ #define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ -/* Number of SPARC register windows */ -#define CONFIG_SYS_SPARC_NWINDOWS 8 - /* * Serial console configuration */ @@ -291,6 +291,6 @@ /* default kernel command line */ #define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0" -#define CONFIG_IDENT_STRING "Gaisler GRSIM LEON2" +#define CONFIG_IDENT_STRING " Gaisler GRSIM LEON2" #endif /* __CONFIG_H */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 48010eb..b7b9c78 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -70,7 +70,6 @@ #define CONFIG_MXC_SPI #define CONFIG_SPI_FLASH_MTD #define CONFIG_SPI_FLASH_BAR - #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 /* GPIO 3-19 (21248) */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 84d0928..801be68 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -304,7 +304,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/icon.h b/include/configs/icon.h index bbe9b59..d9a3671 100644 --- a/include/configs/icon.h +++ b/include/configs/icon.h @@ -107,7 +107,6 @@ #define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index ecb7f10..0a5a9f1 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -323,7 +323,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/intip.h b/include/configs/intip.h index a676a20..60c9e2c 100644 --- a/include/configs/intip.h +++ b/include/configs/intip.h @@ -214,7 +214,6 @@ */ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 385a644..8663c17 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -35,8 +35,6 @@ #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ /* new uImage format support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ #define CONFIG_FIT_DISABLE_SHA256 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ diff --git a/include/configs/ip04.h b/include/configs/ip04.h index dd2a618..0993ffa 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -91,8 +91,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_WINBOND /* diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h index 583f7b3..3c4a70c 100644 --- a/include/configs/ipam390.h +++ b/include/configs/ipam390.h @@ -133,7 +133,6 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index f63957a..23b2e43 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -39,7 +39,6 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI @@ -59,10 +58,8 @@ /* PCI host support */ #define CONFIG_PCI -#define CONFIG_PCI_TEGRA #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM /* PCI networking support */ #define CONFIG_RTL8169 diff --git a/include/configs/katmai.h b/include/configs/katmai.h index fa72eb0..664896b 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -109,7 +109,6 @@ #define IIC0_BOOTPROM_ADDR 0x50 #define IIC0_ALT_BOOTPROM_ADDR 0x54 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0x50) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 3f045f2..eba7479 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -25,7 +25,6 @@ #define CONFIG_KM_COMMON_ETH_INIT /* EEprom support 24C08, 24C16, 24C64 */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index 30cf60c..d86b7fc 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -144,7 +144,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 54aa6fb..d1f0b12 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -99,7 +99,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK @@ -221,7 +220,6 @@ int get_scl(void); #define CONFIG_SYS_I2C_SOFT_SPEED 100000 /* EEprom support 24C128, 24C256 valid for environment eeprom */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 @@ -254,7 +252,6 @@ int get_scl(void); #define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_SPI_FLASH_STMICRO /* SPI bus claim MPP configuration */ #define CONFIG_SYS_KW_SPI_MPP 0x0 diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index e163edb..6860ad2 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -244,7 +244,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -297,10 +296,7 @@ int get_scl(void); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index c905cc2..caeb14d 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -44,7 +44,6 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_SPI #define CONFIG_SH_QSPI -#define CONFIG_SPI_FLASH_SPANSION /* SH Ether */ #define CONFIG_SH_ETHER diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h new file mode 100644 index 0000000..aa07889 --- /dev/null +++ b/include/configs/kylin_rk3036.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/rk3036_common.h> + +#endif diff --git a/include/configs/lager.h b/include/configs/lager.h index 1450e8f..ad8b12f 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -43,7 +43,6 @@ /* SPI */ #define CONFIG_SPI #define CONFIG_SH_QSPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_SYS_NO_FLASH /* SH Ether */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 562e78f..2e8dbc7 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -375,7 +375,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_LPUART_32B_REG #else #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() @@ -414,14 +413,11 @@ unsigned long get_board_ddr_clk(void); /* SPI */ #ifdef CONFIG_QSPI_BOOT /* QSPI */ -#define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_SPI_FLASH_SPANSION /* DSPI */ -#define CONFIG_FSL_DSPI /* DM SPI */ #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) @@ -579,14 +575,14 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ - "fdt_high=0xcfffffff\0" \ - "initrd_high=0xcfffffff\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #else #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ - "fdt_high=0xcfffffff\0" \ - "initrd_high=0xcfffffff\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index fdbbfc1..c12ba3a 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -270,7 +270,6 @@ #define CONFIG_LPUART_32B_REG #else #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() @@ -311,15 +310,11 @@ /* SPI */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) /* QSPI */ -#define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_SPI_FLASH_STMICRO /* DSPI */ -#define CONFIG_FSL_DSPI -#define CONFIG_SPI_FLASH_ATMEL #endif /* DM SPI */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 1f22dd3..677d281 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -44,6 +44,7 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CPU_RELEASE_ADDR secondary_boot_func @@ -55,7 +56,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h new file mode 100644 index 0000000..398f1c3 --- /dev/null +++ b/include/configs/ls1043aqds.h @@ -0,0 +1,404 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1043AQDS_H__ +#define __LS1043AQDS_H__ + +#include "ls1043a_common.h" + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x82000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x60100000 +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_LAYERSCAPE_NS_ACCESS + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_DDR_SPD +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SPD_BUS_NUM 0 + +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#ifndef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ +#endif + +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_SYS_HAS_SERDES + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#define CONFIG_PHYLIB_10G +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +/* PHY address on QSGMII riser card on slot 1 */ +#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 +#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 +#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 +#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 +/* PHY address on QSGMII riser card on slot 2 */ +#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 +#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 +#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA +#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB +#endif + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg +#endif + +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA AHCI_BASE_ADDR + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* + * IFC Definitions + */ +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) + +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) | \ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0xe) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ + CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) +#endif + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define QIXIS_BASE 0x7fb00000 +#define QIXIS_BASE_PHYS QIXIS_BASE +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x44 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* + * QIXIS Timing parameters for IFC GPCM + */ +#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ + FTIM0_GPCM_TEADC(0x20) | \ + FTIM0_GPCM_TEAHC(0x10)) +#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0xf0)) +#define CONFIG_SYS_FPGA_FTIM3 0x0 +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#endif + +/* + * I2C bus multiplexer + */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ +#define I2C_RETIMER_ADDR 0x18 +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_CH7301 0xC +#define I2C_MUX_CH5 0xD +#define I2C_MUX_CH7 0xF + +#define I2C_MUX_CH_VOL_MONITOR 0xa + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_VID +#endif +#define CONFIG_VOL_MONITOR_IR36021_SET +#define CONFIG_VOL_MONITOR_INA220 +/* The lowest and highest voltage allowed for LS1043AQDS */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_MISC_INIT_R +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (30 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET (1024 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x20000 +#endif + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_MII +#define CONFIG_CMDLINE_TAG + +#endif /* __LS1043AQDS_H__ */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 307d947..585114f 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -27,7 +27,7 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SPD_BUS_NUM 0 @@ -222,6 +222,16 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +/* DSPI */ +#define CONFIG_FSL_DSPI +#ifdef CONFIG_FSL_DSPI +#define CONFIG_CMD_SF +#define CONFIG_DM_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_CS 0 +#endif + /* * Environment */ @@ -268,4 +278,27 @@ #define CONFIG_ETHPRIME "FM1@DTSEC3" #endif +/* USB */ +#define CONFIG_HAS_FSL_XHCI_USB +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#define CONFIG_CMD_BLOB +/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ +#define CONFIG_ESBC_ADDR_64BIT +#endif + +#include <asm/fsl_secure_boot.h> + #endif /* __LS1043ARDB_H__ */ diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2080a_common.h index 0011e72..4ae7d11 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2080a_common.h @@ -11,7 +11,6 @@ #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE #define CONFIG_FSL_LSCH3 -#define CONFIG_LS2085A #define CONFIG_MP #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 @@ -20,7 +19,7 @@ #define CONFIG_ARM_ERRATA_828024 #define CONFIG_ARM_ERRATA_826974 -#include <asm/arch/ls2085a_stream_id.h> +#include <asm/arch/ls2080a_stream_id.h> #include <asm/arch/config.h> #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) #define CONFIG_SYS_HAS_SERDES @@ -80,6 +79,7 @@ #define CPU_RELEASE_ADDR secondary_boot_func #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL /* * DDR controller use 0 as the base address for binding. @@ -88,6 +88,7 @@ #define CONFIG_SYS_DP_DDR_BASE_PHY 0 #define CONFIG_DP_DDR_CTRL 2 #define CONFIG_DP_DDR_NUM_CTRLS 1 +#endif /* Generic Timer Definitions */ /* @@ -110,7 +111,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -183,8 +183,10 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#ifdef CONFIG_LS2085A #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 +#endif /* * Carve out a DDR region which will not be used by u-boot/Linux @@ -193,10 +195,9 @@ unsigned long long get_qixis_addr(void); * 512MB aligned, so the min size to hide is 512MB. */ #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) -#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) +#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024) #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) -#define CONFIG_SYS_MEM_TOP_HIDE_MIN (512UL * 1024 * 1024) -#define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide() +#define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) #endif /* PCIe */ @@ -205,7 +206,13 @@ unsigned long long get_qixis_addr(void); #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE4 /* PCIE controler 4 */ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#ifdef CONFIG_LS2080A +#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" +#endif + +#ifdef CONFIG_LS2085A #define FSL_PCIE_COMPAT "fsl,ls2085a-pcie" +#endif #define CONFIG_SYS_PCI_64BIT @@ -245,6 +252,9 @@ unsigned long long get_qixis_addr(void); #define CONFIG_DISPLAY_CPUINFO +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ @@ -260,7 +270,7 @@ unsigned long long get_qixis_addr(void); "console=ttyAMA0,38400n8\0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0500,115200 " \ + "earlycon=uart8250,mmio,0x21c0500" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=16" #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ @@ -279,10 +289,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_MAXARGS 64 /* max command args */ -#ifndef __ASSEMBLY__ -unsigned long get_dram_size_to_hide(void); -#endif - #define CONFIG_PANIC_HANG /* do not reset board on panic */ #define CONFIG_SPL_BSS_START_ADDR 0x80100000 diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2080a_emu.h index 2d68e1b..4a7ba24 100644 --- a/include/configs/ls2085a_emu.h +++ b/include/configs/ls2080a_emu.h @@ -7,10 +7,17 @@ #ifndef __LS2_EMU_H #define __LS2_EMU_H -#include "ls2085a_common.h" +#include "ls2080a_common.h" +#ifdef CONFIG_LS2080A +#define CONFIG_IDENT_STRING " LS2080A-EMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-EMU" +#endif + +#ifdef CONFIG_LS2085A #define CONFIG_IDENT_STRING " LS2085A-EMU" #define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" +#endif #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 @@ -27,7 +34,9 @@ #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#endif #define CONFIG_FSL_DDR_SYNC_REFRESH diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2080a_simu.h index bd15b3d..876ee30 100644 --- a/include/configs/ls2085a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -7,10 +7,17 @@ #ifndef __LS2_SIMU_H #define __LS2_SIMU_H -#include "ls2085a_common.h" +#include "ls2080a_common.h" +#ifdef CONFIG_LS2080A +#define CONFIG_IDENT_STRING " LS2080A-SIMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-SIMU" +#endif + +#ifdef CONFIG_LS2085A #define CONFIG_IDENT_STRING " LS2085A-SIMU" #define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU" +#endif #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 @@ -20,7 +27,9 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#endif /* SMSC 91C111 ethernet configuration */ #define CONFIG_SMC91111 diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2080aqds.h index 406d0e6..ba84248 100644 --- a/include/configs/ls2085aqds.h +++ b/include/configs/ls2080aqds.h @@ -7,7 +7,7 @@ #ifndef __LS2_QDS_H #define __LS2_QDS_H -#include "ls2085a_common.h" +#include "ls2080a_common.h" #define CONFIG_DISPLAY_BOARDINFO @@ -35,9 +35,29 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#endif #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) @@ -250,19 +270,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL -/* MC firmware */ -#define CONFIG_SYS_LS_MC_FW_IN_NOR -#define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL - -#define CONFIG_SYS_LS_MC_DPL_IN_NOR -#define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL - -#define CONFIG_SYS_LS_MC_DPC_IN_NOR -#define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL - #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 -#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR -#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x580900000ULL /* * I2C @@ -277,9 +285,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_FSL_DSPI #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_EON #endif /* diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2080ardb.h index f95d7b2..116dbcd 100644 --- a/include/configs/ls2085ardb.h +++ b/include/configs/ls2080ardb.h @@ -7,7 +7,7 @@ #ifndef __LS2_RDB_H #define __LS2_RDB_H -#include "ls2085a_common.h" +#include "ls2080a_common.h" #undef CONFIG_CONS_INDEX #define CONFIG_CONS_INDEX 2 @@ -37,9 +37,29 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#endif #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) @@ -223,19 +243,7 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL -/* MC firmware */ -#define CONFIG_SYS_LS_MC_FW_IN_NOR -#define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL - -#define CONFIG_SYS_LS_MC_DPL_IN_NOR -#define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL - -#define CONFIG_SYS_LS_MC_DPC_IN_NOR -#define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL - #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 -#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR -#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x580900000ULL /* * I2C @@ -250,7 +258,6 @@ unsigned long get_board_sys_clk(void); #ifdef CONFIG_FSL_DSPI #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_BAR #endif @@ -324,7 +331,7 @@ unsigned long get_board_sys_clk(void); #undef CONFIG_BOOTARGS #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0600,115200 " \ + "earlycon=uart8250,mmio,0x21c0600" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=16" diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 4194a0f..19ee5bc 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -78,8 +78,6 @@ #define CONFIG_SUPPORT_RAW_INITRD /* ST M25P40 */ -#undef CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_STMICRO #undef CONFIG_ENV_SPI_MAX_HZ #define CONFIG_ENV_SPI_MAX_HZ 25000000 #undef CONFIG_SF_DEFAULT_SPEED diff --git a/include/configs/luan.h b/include/configs/luan.h index 15e4a7e..e22d0e8 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -119,7 +119,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 66d9710..69172bb 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -102,7 +102,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 24b5489..8063a1e 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -91,7 +91,6 @@ /* EEPROM */ #ifdef CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #endif @@ -124,7 +123,6 @@ /* SPI FLASH */ #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SF_DEFAULT_BUS 2 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 40000000 diff --git a/include/configs/malta.h b/include/configs/malta.h index 4d3751a..3faac37 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -80,7 +80,6 @@ */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (115200 * 16) diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 3c4beeb..da49243 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -47,8 +47,6 @@ /* SPI NOR flash default params, used by sf commands */ #define CONFIG_SF_DEFAULT_SPEED 1000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SPANSION /* Environment in SPI NOR flash */ #define CONFIG_ENV_IS_IN_SPI_FLASH diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 882f3db..4eea06d 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -78,7 +78,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 6f20a82..f93861d 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -39,7 +39,6 @@ # define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } # define CONSOLE_ARG "console=console=ttyUL0,115200\0" #elif XILINX_UART16550_BASEADDR -# define CONFIG_SYS_NS16550 1 # define CONFIG_SYS_NS16550_SERIAL # if defined(__MICROBLAZEEL__) # define CONFIG_SYS_NS16550_REG_SIZE -4 @@ -69,10 +68,6 @@ # define CONFIG_XILINX_EMACLITE 1 # define CONFIG_SYS_ENET #endif -#if defined(XILINX_LLTEMAC_BASEADDR) -# define CONFIG_XILINX_LL_TEMAC 1 -# define CONFIG_SYS_ENET -#endif #if defined(XILINX_AXIEMAC_BASEADDR) # define CONFIG_XILINX_AXIEMAC 1 # define CONFIG_SYS_ENET @@ -102,8 +97,10 @@ #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ) # define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR # define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ -# define CONFIG_HW_WATCHDOG -# define CONFIG_XILINX_TB_WATCHDOG +# ifndef CONFIG_SPL_BUILD +# define CONFIG_HW_WATCHDOG +# define CONFIG_XILINX_TB_WATCHDOG +# endif #endif #if !defined(CONFIG_OF_CONTROL) || \ @@ -114,15 +111,10 @@ #endif #define CONFIG_SYS_MALLOC_LEN 0xC0000 -#ifndef CONFIG_SPL_BUILD -# define CONFIG_SYS_MALLOC_F_LEN 1024 -#else -# define CONFIG_SYS_MALLOC_SIMPLE -# define CONFIG_SYS_MALLOC_F_LEN 0x150 -#endif /* Stack location before relocation */ -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_F_LEN) /* * CFI flash memory layout - Example @@ -175,9 +167,7 @@ #ifdef SPIFLASH # define CONFIG_SYS_NO_FLASH 1 # define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR -# define CONFIG_XILINX_SPI 1 # define CONFIG_SPI 1 -# define CONFIG_SPI_FLASH_STMICRO 1 # define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 # define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ # define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS @@ -363,7 +353,7 @@ #define CONFIG_FIT 1 #define CONFIG_OF_LIBFDT 1 -#if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC) +#if defined(CONFIG_XILINX_AXIEMAC) # define CONFIG_MII 1 # define CONFIG_CMD_MII 1 # define CONFIG_PHY_GIGE 1 diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 95d356a..1cb135b 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -29,7 +29,6 @@ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT} -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MMC #define CONFIG_SDHCI diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 97c614b..a8cf201 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -285,7 +285,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 1 /* 2 bytes per write cycle */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* 2 EEPROMs (addr:50,52) */ /* * RTC configuration diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 1a627fc..a90083f 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -292,7 +292,6 @@ */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 1ecbd35..d12d725 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -39,11 +39,6 @@ /* * NS16550 Configuration */ -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL) -#define CONFIG_DW_SERIAL -#endif - -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) @@ -128,7 +123,6 @@ * Common SPI Flash configuration */ #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_MACRONIX 1 #endif /* diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 10867a7..a52c8c9 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -129,7 +129,6 @@ #define CONFIG_SF_DEFAULT_BUS 2 #define CONFIG_SF_DEFAULT_CS 0 /* this may vary and depends on the installed chip */ -#define CONFIG_SPI_FLASH_SST #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #endif diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 3e045ef..29d1f91 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -39,7 +39,6 @@ #define CONFIG_CMD_SF #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index ae39503..6937924 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -171,7 +171,6 @@ #define CONFIG_CMD_SF #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index edf7d3f..0aec296 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -182,12 +182,9 @@ #define CONFIG_CMD_TIME -#define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SYS_FSL_QSPI_LE #define CONFIG_SYS_FSL_QSPI_AHB #ifdef CONFIG_MX6SX_SABRESD_REVA diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 5779632..2712b27 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -195,11 +195,9 @@ #define CONFIG_CMD_CACHE #endif -#define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index cc98547..22e515c 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -236,4 +236,19 @@ #define CONFIG_VIDEO_BMP_LOGO #endif +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_QSPI_FLASH_NUM 1 +#define FSL_QSPI_FLASH_SIZE SZ_64M +#define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR +#define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/neo.h b/include/configs/neo.h index a60b3f7..bc01416 100644 --- a/include/configs/neo.h +++ b/include/configs/neo.h @@ -91,7 +91,6 @@ * set Linux BASE_BAUD to 403200. */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 9160971..3416ce3 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -31,7 +31,6 @@ #define CONFIG_CMD_SF #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_SST #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index f071c59..b11e43a 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -85,7 +85,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h new file mode 100644 index 0000000..4510b16 --- /dev/null +++ b/include/configs/nsa310s.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2015 + * Gerald Kerma <dreagle@doukki.net> + * Tony Dinh <mibodhi@gmail.com> + * Luka Perkov <luka.perkov@sartura.hr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_NSA310S_H +#define _CONFIG_NSA310S_H + +/* high level configuration options */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KW88F6192 1 /* SOC Name */ +#define CONFIG_KW88F6702 1 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* add target to build it automatically upon "make" */ +#define CONFIG_BUILD_TARGET "u-boot.kwb" + +/* compression configuration */ +#define CONFIG_BZIP2 +#define CONFIG_LZMA + +/* commands configuration */ +#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MII + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* environment variables configuration */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0xe0000 + +/* default environment variables */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount ubi:rootfs; " \ + "ubifsload 0x800000 ${kernel}; " \ + "ubifsload 0x700000 ${fdt}; " \ + "ubifsumount; " \ + "fdt addr 0x700000; fdt resize; fdt chosen; " \ + "bootz 0x800000 - 0x700000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "0xe0000@0x0(uboot)," \ + "0x20000@0xe0000(uboot_env)," \ + "0x100000@0x100000(second_stage_uboot)," \ + "-@0x200000(root)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS \ + "kernel=/boot/zImage\0" \ + "fdt=/boot/nsa310s.dtb\0" \ + "bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0" + +/* Ethernet driver configuration */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NETCONSOLE +#define CONFIG_NET_MULTI +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 1 +#define CONFIG_PHY_GIGE +#define CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +/* SATA driver configuration */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_DOS_PARTITION +#define CONFIG_MVSATA_IDE_USE_PORT0 +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif /* CONFIG_CMD_IDE */ + +/* RTC driver configuration */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + +#endif /* _CONFIG_NSA310S_H */ diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 4b693e8..9464153 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -51,7 +51,6 @@ #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 7e7f6f2..2004d14 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -72,7 +72,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 4e93705..803f4b8 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -49,7 +49,7 @@ /* * NS16550 Configuration */ -#undef CONFIG_OMAP_SERIAL +#undef CONFIG_SYS_NS16550_CLK #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 80d57f4..4633fec 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -93,7 +93,6 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ @@ -103,8 +102,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_SPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_DAVINCI_SPI #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h index d53e419..c854189 100644 --- a/include/configs/openrisc-generic.h +++ b/include/configs/openrisc-generic.h @@ -31,7 +31,6 @@ /* * SERIAL */ -# define CONFIG_SYS_NS16550 # define CONFIG_SYS_NS16550_SERIAL # define CONFIG_SYS_NS16550_REG_SIZE 1 # define CONFIG_CONS_INDEX 1 diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 426ec72..879ad58 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -23,10 +23,6 @@ /* SF Configs */ #define CONFIG_CMD_SF #define CONFIG_SPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_SST #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 2 #define CONFIG_SF_DEFAULT_CS 0 @@ -115,7 +111,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #endif /* Miscellaneous commands */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 433c409..60bedaa 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -649,7 +649,6 @@ */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -701,7 +700,6 @@ /* enable read and write access to EEPROM */ #define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -710,10 +708,8 @@ * eSPI - Enhanced SPI */ #define CONFIG_HARD_SPI -#define CONFIG_FSL_ESPI #if defined(CONFIG_SPI_FLASH) -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index d83daa0..77ba2d8 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -215,7 +215,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -262,7 +261,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* enable read and write access to EEPROM */ #define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -271,7 +269,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * eSPI - Enhanced SPI */ #define CONFIG_HARD_SPI -#define CONFIG_FSL_ESPI #if defined(CONFIG_PCI) /* diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index f2a713d..fffe5c9 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -35,7 +35,6 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 94f8085..7dbf422 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -35,7 +35,6 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI @@ -55,10 +54,8 @@ /* PCI host support */ #define CONFIG_PCI -#define CONFIG_PCI_TEGRA #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM /* PCI networking support */ #define CONFIG_RTL8169 diff --git a/include/configs/p2571.h b/include/configs/p2571.h index a5de411..f3357d1 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -36,7 +36,6 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 275e952..45c140d 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -97,7 +97,6 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ + (8 * 1024 * 1024)) -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 24000000 @@ -115,7 +114,6 @@ #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 046ddb8..b851bba 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -97,12 +97,10 @@ #define CONFIG_PHY_MICREL /* QSPI Configs*/ -#define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_SYS_FSL_QSPI_LE diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index d68cded..bfc1c1e 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -112,7 +112,6 @@ #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS /* SPL */ #define CONFIG_SPL_POWER_SUPPORT diff --git a/include/configs/porter.h b/include/configs/porter.h index 59b14e9..e34cd05 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -43,7 +43,6 @@ /* FLASH */ #define CONFIG_SPI #define CONFIG_SH_QSPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_SPI_FLASH_QUAD #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/pr1.h b/include/configs/pr1.h index f76e023..2e5ce75 100644 --- a/include/configs/pr1.h +++ b/include/configs/pr1.h @@ -83,7 +83,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 9395bda..5a043d5 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -52,7 +52,6 @@ #define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_NE2000_BASE 0xb4000300 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK 115200 diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index 53ff802..070b5de 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -52,7 +52,6 @@ #define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK 115200 diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index f45789f..2dfea33 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -103,7 +103,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index e3445dd..4258dcb 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -54,7 +54,6 @@ #undef CONFIG_INTEL_ICH6_GPIO /* SPI is not supported */ -#undef CONFIG_ICH_SPI #undef CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_IS_NOWHERE diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h new file mode 100644 index 0000000..f753e68 --- /dev/null +++ b/include/configs/rk3036_common.h @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_RK3036_COMMON_H +#define __CONFIG_RK3036_COMMON_H + +#include <asm/arch/hardware.h> + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 +#define CONFIG_SPL_STACK 0x10081fff +#define CONFIG_SPL_TEXT_BASE 0x10081004 + +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10) +#define CONFIG_ROCKCHIP_CHIP_TAG "RK30" + +#define CONFIG_ROCKCHIP_COMMON + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SDHCI +#define CONFIG_DWMMC +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_TIME + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define SDRAM_BANK_SIZE (512UL << 20UL) + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#define CONFIG_CMD_I2C + +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "pxefile_addr_r=0x60100000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +/* First try to boot from SD (index 0), then eMMC (index 1 */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#include <config_distro_bootcmd.h> + +/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board, + * so limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x7fffffff\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV +#endif + +#endif diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 36408b9..238711a 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_BAUDRATE 115200 @@ -23,26 +22,25 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_COUNTER (TIMER7_BASE + 8) +#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SPL_BOARD_INIT -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - #define CONFIG_SYS_TEXT_BASE 0x00100000 #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff718000 #define CONFIG_SPL_TEXT_BASE 0xff704004 +#define CONFIG_ROCKCHIP_COMMON +#define CONFIG_SPL_ROCKCHIP_COMMON + /* MMC/SD IP block */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC @@ -84,7 +82,6 @@ #define CONFIG_SPI #define CONFIG_CMD_SF #define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_GIGADEVICE #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_CMD_I2C @@ -110,6 +107,7 @@ * limit the fdt reallocation to that */ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x1fffffff\0" \ + "initrd_high=0x1fffffff\0" \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV #endif diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 2877e19..8f65d7e 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -269,8 +269,8 @@ #define CONFIG_SYS_MAX_I2C_BUS 7 #define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_S3C_UDC_OTG -#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY +#define CONFIG_USB_GADGET_DWC2_OTG +#define CONFIG_USB_GADGET_DWC2_OTG_PHY #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_CMD_USB_MASS_STORAGE diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 35fef2b..7bb62ca 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -177,8 +177,8 @@ #define CONFIG_POWER_MAX8998 #define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_S3C_UDC_OTG -#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY +#define CONFIG_USB_GADGET_DWC2_OTG +#define CONFIG_USB_GADGET_DWC2_OTG_PHY #define CONFIG_USB_GADGET_DUALSPEED /* diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h new file mode 100644 index 0000000..ae5ba3d --- /dev/null +++ b/include/configs/sama5d2_xplained.h @@ -0,0 +1,122 @@ +/* + * Configuration file for the SAMA5D2 Xplained Board. + * + * Copyright (C) 2015 Atmel Corporation + * Wenyou Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* No NOR flash, this definition should put before common header */ +#define CONFIG_SYS_NO_FLASH + +#include "at91-sama5_common.h" + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_UART1 +#define CONFIG_USART_ID ATMEL_ID_UART1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#undef CONFIG_AT91_GPIO +#define CONFIG_ATMEL_PIO4 + +/* SerialFlash */ +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI +#define CONFIG_ATMEL_SPI0 +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#endif + +/* NAND flash */ +#undef CONFIG_CMD_NAND + +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SDHCI +#define CONFIG_ATMEL_SDHCI +#define CONFIG_ATMEL_SDHCI0 +#define CONFIG_ATMEL_SDHCI1 +#define CONFIG_SUPPORT_EMMC_BOOT +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE +#endif + +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2 XPlained" + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +/* LCD */ +/* #define CONFIG_LCD */ + +#ifdef CONFIG_LCD +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP 24 +#define CONFIG_LCD_LOGO +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_HLCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#endif + +#ifdef CONFIG_SYS_USE_MMC + +/* bootstrap + u-boot + env in sd card */ +#undef FAT_ENV_DEVICE_AND_PART +#undef CONFIG_BOOTCOMMAND + +#define FAT_ENV_DEVICE_AND_PART "1" +#define CONFIG_BOOTCOMMAND "fatload mmc 1:1 0x21000000 at91-sama5d2_xplained.dtb; " \ + "fatload mmc 1:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait" + +#endif + +#endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 61b4bda..bd5f4ee 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -80,7 +80,6 @@ #ifdef CONFIG_CMD_SF #define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SF_DEFAULT_SPEED 30000000 #endif diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 139031d..52b4584 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -40,7 +40,6 @@ #ifdef CONFIG_CMD_SF #define CONFIG_ATMEL_SPI #define CONFIG_ATMEL_SPI0 -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 30000000 diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index cde549a..ce96a7c 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -40,7 +40,6 @@ #ifdef CONFIG_CMD_SF #define CONFIG_ATMEL_SPI #define CONFIG_ATMEL_SPI0 -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 30000000 diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 1c75c38..d3112e1 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -83,14 +83,6 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_SF_TEST #define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_ATMEL -#define CONFIG_SPI_FLASH_EON -#define CONFIG_SPI_FLASH_GIGADEVICE -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_CMD_I2C #define CONFIG_I2C_EDID diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index c8b14e9..25ec7bc 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -267,7 +267,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 1c309a4..9783804 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -406,7 +406,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 0b22ce0..f88d685 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -247,7 +247,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 1f1beea..f32459b 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -151,7 +151,6 @@ */ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index f1f9ca8..fc9d246 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -97,8 +97,6 @@ /* SPI */ #define CONFIG_SH_SPI 1 #define CONFIG_SH_SPI_BASE 0xfe002000 -#define CONFIG_SPI_FLASH_STMICRO 1 -#define CONFIG_SPI_FLASH_MACRONIX 1 /* MMCIF */ #define CONFIG_MMC 1 diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index d7ed65b..31dd984 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -97,8 +97,6 @@ /* SPI */ #define CONFIG_SH_SPI 1 #define CONFIG_SH_SPI_BASE 0xfe002000 -#define CONFIG_SPI_FLASH_STMICRO 1 -#define CONFIG_SPI_FLASH_MACRONIX 1 /* MMCIF */ #define CONFIG_MMC 1 diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index cf514b6..26d70f4 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -98,7 +98,6 @@ /* SPI */ #define CONFIG_SH_SPI 1 #define CONFIG_SH_SPI_BASE 0xfe002000 -#define CONFIG_SPI_FLASH_STMICRO 1 /* MMCIF */ #define CONFIG_MMC 1 diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 9ab0457..eac7270 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -97,7 +97,6 @@ #define CONFIG_SPI #define CONFIG_OMAP3_SPI #define CONFIG_MTD_DEVICE -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED (75000000) @@ -113,7 +112,6 @@ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) diff --git a/include/configs/silk.h b/include/configs/silk.h index cd839aa..93c3d0d 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -43,7 +43,6 @@ /* FLASH */ #define CONFIG_SPI #define CONFIG_SH_QSPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_SPI_FLASH_QUAD #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 217cfc0..2492f99 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -13,8 +13,8 @@ #undef CONFIG_BOARD_COMMON #undef CONFIG_USB_GADGET -#undef CONFIG_USB_GADGET_S3C_UDC_OTG -#undef CONFIG_USB_GADGET_S3C_UDC_OTG_PHY +#undef CONFIG_USB_GADGET_DWC2_OTG +#undef CONFIG_USB_GADGET_DWC2_OTG_PHY #undef CONFIG_CMD_USB_MASS_STORAGE #undef CONFIG_REVISION_TAG #undef CONFIG_CMD_THOR_DOWNLOAD diff --git a/include/configs/sniper.h b/include/configs/sniper.h index f168e8f..08046b5 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -196,15 +196,12 @@ */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_OMAP_SERIAL -#else +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #endif -#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_CONS_INDEX 3 #define CONFIG_SERIAL3 3 diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index 8364c66..a0161bc 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_SOCFPGA_ARRIA5_H__ #define __CONFIG_SOCFPGA_ARRIA5_H__ -#include <asm/arch/socfpga_base_addrs.h> +#include <asm/arch/base_addr_ac5.h> /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH @@ -47,30 +47,13 @@ /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) - -/* PHY */ #define CONFIG_PHY_MICREL #define CONFIG_PHY_MICREL_KSZ9021 -#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" -#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 -#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" -#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 - #endif #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif -#define CONFIG_G_DNL_MANUFACTURER "Altera" /* Extra Environment */ -#define CONFIG_HOSTNAME socfpga_arria5 - #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ @@ -79,7 +62,6 @@ "bootimage=zImage\0" \ "fdt_addr=100\0" \ "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ "bootm ${loadaddr} - ${fdt_addr}\0" \ "mmcroot=/dev/mmcblk0p2\0" \ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ @@ -88,11 +70,13 @@ "mmcload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ + "qspiload=sf probe && mtdparts default && run ubiload\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" + " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "ubiload=ubi part UBI && ubifsmount ubi0 && " \ + "ubifsload ${loadaddr} /boot/${bootimage} && " \ + "ubifsload ${fdt_addr} /boot/${fdtimage}\0" /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 3374683..a09e906 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ -#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ +#ifndef __CONFIG_SOCFPGA_COMMON_H__ +#define __CONFIG_SOCFPGA_COMMON_H__ /* Virtual target or real hardware */ @@ -69,6 +69,10 @@ #define CONFIG_CMDLINE_EDITING /* Command history etc */ #define CONFIG_SYS_HUSH_PARSER +#ifndef CONFIG_SYS_HOSTNAME +#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD +#endif + /* * Cache */ @@ -88,7 +92,6 @@ #define CONFIG_CMD_SPI #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_BAR /* * The base address is configurable in QSys, each board must specify the @@ -106,7 +109,6 @@ #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_MII #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) -#define CONFIG_PHYLIB #define CONFIG_PHY_GIGE #endif @@ -153,14 +155,25 @@ #define CONFIG_DWMMC #define CONFIG_SOCFPGA_DWMMC #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 -#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 -#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 /* FIXME */ /* using smaller max blk cnt to avoid flooding the limited stack we have */ #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ #endif /* + * NAND Support + */ +#ifdef CONFIG_NAND_DENALI +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_DENALI_ECC_SIZE 512 +#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS +#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) +#endif + +/* * I2C support */ #define CONFIG_SYS_I2C @@ -190,16 +203,13 @@ unsigned int cm_get_l4_sp_clk_hz(void); /* * QSPI support */ -#define CONFIG_CADENCE_QSPI /* Enable multiple SPI NOR flash manufacturers */ -#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ -#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */ #ifndef CONFIG_SPL_BUILD #define CONFIG_SPI_FLASH_MTD #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT "nor0=ff705000.spi" +#define MTDIDS_DEFAULT "nor0=ff705000.spi.0" #endif /* QSPI reference clock */ #ifndef __ASSEMBLY__ @@ -213,13 +223,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * Designware SPI support */ -#define CONFIG_DESIGNWARE_SPI #define CONFIG_CMD_SPI /* * Serial Driver */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS @@ -237,13 +245,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2 #define CONFIG_USB_STORAGE -/* - * NOTE: User must define either of the following to select which - * of the two USB controllers available on SoCFPGA to use. - * The DWC2 driver doesn't support multiple USB controllers. - * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS - * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS - */ #endif /* @@ -251,7 +252,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) #define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_DWC2_OTG #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 @@ -260,7 +261,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_USB_FUNCTION_DFU +#ifdef CONFIG_DM_MMC #define CONFIG_DFU_MMC +#endif #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) #define DFU_DEFAULT_POLL_TIMEOUT 300 @@ -270,7 +273,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM #define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM #ifndef CONFIG_G_DNL_MANUFACTURER -#define CONFIG_G_DNL_MANUFACTURER "Altera" +#define CONFIG_G_DNL_MANUFACTURER CONFIG_SYS_VENDOR #endif #endif @@ -282,6 +285,43 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE #define CONFIG_ENV_SIZE 4096 +/* Environment for SDMMC boot */ +#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ +#endif + +/* + * mtd partitioning for serial NOR flash + * + * device nor0 <ff705000.spi.0>, # parts = 6 + * #: name size offset mask_flags + * 0: u-boot 0x00100000 0x00000000 0 + * 1: env1 0x00040000 0x00100000 0 + * 2: env2 0x00040000 0x00140000 0 + * 3: UBI 0x03e80000 0x00180000 0 + * 4: boot 0x00e80000 0x00180000 0 + * 5: rootfs 0x01000000 0x01000000 0 + * + */ +#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) +#define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ + "1m(u-boot)," \ + "256k(env1)," \ + "256k(env2)," \ + "14848k(boot)," \ + "16m(rootfs)," \ + "-@1536k(UBI)\0" +#endif + +/* UBI and UBIFS support */ +#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#endif + /* * SPL * @@ -305,8 +345,15 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_DM_MMC #define CONFIG_SPL_MMC_SUPPORT +#endif +#ifdef CONFIG_DM_SPI #define CONFIG_SPL_SPI_SUPPORT +#endif +#ifdef CONFIG_SPL_NAND_DENALI +#define CONFIG_SPL_NAND_SUPPORT +#endif /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT @@ -329,9 +376,16 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #endif +/* SPL NAND boot support */ +#ifdef CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#endif + /* * Stack setup */ #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */ +#endif /* __CONFIG_SOCFPGA_COMMON_H__ */ diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 86b53e2..c4c4ecb 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ #define __CONFIG_SOCFPGA_CYCLONE5_H__ -#include <asm/arch/socfpga_base_addrs.h> +#include <asm/arch/base_addr_ac5.h> /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH @@ -47,30 +47,13 @@ /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) - -/* PHY */ #define CONFIG_PHY_MICREL #define CONFIG_PHY_MICREL_KSZ9021 -#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" -#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 -#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" -#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 - #endif #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif -#define CONFIG_G_DNL_MANUFACTURER "Altera" /* Extra Environment */ -#define CONFIG_HOSTNAME socfpga_cyclone5 - #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ @@ -79,7 +62,6 @@ "bootimage=zImage\0" \ "fdt_addr=100\0" \ "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ "bootm ${loadaddr} - ${fdt_addr}\0" \ "mmcroot=/dev/mmcblk0p2\0" \ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ @@ -88,11 +70,13 @@ "mmcload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ + "qspiload=sf probe && mtdparts default && run ubiload\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" + " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "ubiload=ubi part UBI && ubifsmount ubi0 && " \ + "ubifsload ${loadaddr} /boot/${bootimage} && " \ + "ubifsload ${fdt_addr} /boot/${fdtimage}\0" /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index 3ae9b3e..cbc7396 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_TERASIC_DE0_H__ #define __CONFIG_TERASIC_DE0_H__ -#include <asm/arch/socfpga_base_addrs.h> +#include <asm/arch/base_addr_ac5.h> /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH @@ -37,36 +37,19 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_BOOTCOMMAND "run ramboot" -#else #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" -#endif #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) - -/* PHY */ #define CONFIG_PHY_MICREL #define CONFIG_PHY_MICREL_KSZ9031 - #endif #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif -#define CONFIG_G_DNL_MANUFACTURER "Terasic" /* Extra Environment */ -#define CONFIG_HOSTNAME socfpga_de0_nano_soc - #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ @@ -74,7 +57,6 @@ "bootimage=zImage\0" \ "fdt_addr=100\0" \ "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ "bootm ${loadaddr} - ${fdt_addr}\0" \ "mmcroot=/dev/mmcblk0p2\0" \ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index 4b270ce..e7b5675 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_DENX_MCVEVK_H__ #define __CONFIG_DENX_MCVEVK_H__ -#include <asm/arch/socfpga_base_addrs.h> +#include <asm/arch/base_addr_ac5.h> /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH @@ -45,18 +45,8 @@ /* Environment is in MMC */ #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif -#define CONFIG_G_DNL_MANUFACTURER "DENX" /* Extra Environment */ -#define CONFIG_HOSTNAME mcvevk - #define CONFIG_EXTRA_ENV_SETTINGS \ "consdev=ttyS0\0" \ "baudrate=115200\0" \ diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 742c5ae..95e7ba6 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_TERASIC_SOCKIT_H__ #define __CONFIG_TERASIC_SOCKIT_H__ -#include <asm/arch/socfpga_base_addrs.h> +#include <asm/arch/base_addr_ac5.h> /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH @@ -37,40 +37,19 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_BOOTCOMMAND "run ramboot" -#else #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" -#endif #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) - -/* PHY */ #define CONFIG_PHY_MICREL #define CONFIG_PHY_MICREL_KSZ9021 -#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" -#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 -#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" -#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 - #endif #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif -#define CONFIG_G_DNL_MANUFACTURER "Terasic" /* Extra Environment */ -#define CONFIG_HOSTNAME socfpga_sockit - #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ @@ -79,7 +58,6 @@ "bootimage=zImage\0" \ "fdt_addr=100\0" \ "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ "bootm ${loadaddr} - ${fdt_addr}\0" \ "mmcroot=/dev/mmcblk0p2\0" \ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ @@ -88,6 +66,13 @@ "mmcload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiload=sf probe && mtdparts default && run ubiload\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "ubiload=ubi part UBI && ubifsmount ubi0 && " \ + "ubifsload ${loadaddr} /boot/${bootimage} && " \ + "ubifsload ${fdt_addr} /boot/${fdtimage}\0" /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h new file mode 100644 index 0000000..c32a40a --- /dev/null +++ b/include/configs/socfpga_socrates.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_SOCFPGA_SOCRATES_H__ +#define __CONFIG_SOCFPGA_SOCRATES_H__ + +#include <asm/arch/base_addr_ac5.h> + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DFU +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_USB_MASS_STORAGE + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */ + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#endif + +#define CONFIG_ENV_IS_IN_MMC + +/* Extra Environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +#endif /* __CONFIG_SOCFPGA_SOCRATES_H__ */ diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h new file mode 100644 index 0000000..fdf67ca --- /dev/null +++ b/include/configs/socfpga_sr1500.h @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_SOCFPGA_SR1500_H__ +#define __CONFIG_SOCFPGA_SR1500_H__ + +#include <asm/arch/base_addr_ac5.h> + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE + +#define CONFIG_HW_WATCHDOG + +/* U-Boot Commands */ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MEMTEST +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_TIME + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ + +/* Ethernet on SoC (EMAC) */ +#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII +/* The PHY is autodetected, so no MII PHY address is needed here */ +#define CONFIG_PHY_MARVELL +#define PHY_ANEG_TIMEOUT 8000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiload=sf probe && mtdparts default && run ubiload\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "ubiload=ubi part UBI && ubifsmount ubi0 && " \ + "ubifsload ${loadaddr} /boot/${bootimage} && " \ + "ubifsload ${fdt_addr} /boot/${fdtimage}\0" + +/* Environment */ +#define CONFIG_ENV_IS_IN_SPI_FLASH + +/* Enable SPI NOR flash reset, needed for SPI booting */ +#define CONFIG_SPI_N25Q256A_RESET + +/* + * Bootcounter + */ +#define CONFIG_BOOTCOUNT_LIMIT +/* last 2 lwords in OCRAM */ +#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8 +#define CONFIG_SYS_BOOTCOUNT_BE + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +/* U-Boot payload is stored at offset 0x60000 */ +#undef CONFIG_SYS_SPI_U_BOOT_OFFS +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x60000 + +/* Environment setting for SPI flash */ +#undef CONFIG_ENV_SIZE +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_OFFSET 0x00040000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MODE SPI_MODE_3 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED + +#endif /* __CONFIG_SOCFPGA_SR1500_H__ */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 019cf30..f8bddca 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -198,7 +198,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 1d69477..d2630f4 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -17,7 +17,6 @@ /* Ethernet driver configuration */ #define CONFIG_MII -#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 8191fb2..3e80861 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -51,14 +51,6 @@ #define CONFIG_STM32_GPIO #define CONFIG_STM32_SERIAL -/* - * Configuration of the USART - * 1: TX:PA9 RX:PA10 - * 2: TX:PD5 RX:PD6 - * 3: TX:PC10 RX:PC11 - * 6: TX:PG14 RX:PG9 - */ -#define CONFIG_STM32_USART 1 #define CONFIG_STM32_HSE_HZ 8000000 diff --git a/include/configs/stout.h b/include/configs/stout.h index 87ea530..70fedf1 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -48,7 +48,6 @@ /* SPI */ #define CONFIG_SPI #define CONFIG_SH_QSPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_SPI_FLASH_QUAD #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/strider.h b/include/configs/strider.h index fb7b7f9..8771cdc 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -308,7 +308,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 1526d13..f421321 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -53,7 +53,6 @@ /* GMAC related configs */ #define CONFIG_MII -#define CONFIG_PHYLIB #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_PHY_MICREL @@ -78,13 +77,10 @@ + * QSPI support + */ #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ -#define CONFIG_CADENCE_QSPI #define CONFIG_CQSPI_DECODER 0 #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 #define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ -#define CONFIG_SPI_FLASH_WINBOND /* WINBOND */ #define CONFIG_CMD_SF #endif diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index 4fc6365..781ff6e 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -20,14 +20,20 @@ #define CONFIG_SUNXI_USB_PHYS 2 + +#ifndef CONFIG_MACH_SUN8I_A83T #define CONFIG_ARMV7_PSCI 1 #if defined(CONFIG_MACH_SUN8I_A23) #define CONFIG_ARMV7_PSCI_NR_CPUS 2 #elif defined(CONFIG_MACH_SUN8I_A33) #define CONFIG_ARMV7_PSCI_NR_CPUS 4 +#elif defined(CONFIG_MACH_SUN8I_H3) +#define CONFIG_ARMV7_PSCI_NR_CPUS 4 #else #error Unsupported sun8i variant #endif +#endif + #define CONFIG_TIMER_CLK_FREQ 24000000 /* diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index d7d5d25..790e704 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -41,13 +41,10 @@ #endif /* Serial & console */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ #define CONFIG_SYS_NS16550_CLK 24000000 -#ifdef CONFIG_DM_SERIAL -# define CONFIG_DW_SERIAL -#else +#ifndef CONFIG_DM_SERIAL # define CONFIG_SYS_NS16550_REG_SIZE -4 # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE @@ -242,7 +239,8 @@ extern int soft_i2c_gpio_scl; #endif /* PMU */ -#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER +#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ + defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER #define CONFIG_SPL_POWER_SUPPORT #endif @@ -311,11 +309,9 @@ extern int soft_i2c_gpio_scl; #endif #ifdef CONFIG_SUNXI_GMAC -#define CONFIG_DW_AUTONEG #define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ #define CONFIG_PHY_ADDR 1 #define CONFIG_MII /* MII PHY management */ -#define CONFIG_PHYLIB #endif #ifdef CONFIG_USB_EHCI_HCD @@ -335,6 +331,7 @@ extern int soft_i2c_gpio_scl; #define CONFIG_USB_GADGET_VBUS_DRAW 0 #define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_FUNCTION_DFU #define CONFIG_USB_FUNCTION_FASTBOOT #define CONFIG_USB_FUNCTION_MASS_STORAGE #endif @@ -345,6 +342,11 @@ extern int soft_i2c_gpio_scl; #define CONFIG_G_DNL_MANUFACTURER "Allwinner Technology" #endif +#ifdef CONFIG_USB_FUNCTION_DFU +#define CONFIG_CMD_DFU +#define CONFIG_DFU_RAM +#endif + #ifdef CONFIG_USB_FUNCTION_FASTBOOT #define CONFIG_CMD_FASTBOOT #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR @@ -392,18 +394,37 @@ extern int soft_i2c_gpio_scl; * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, * 1M script, 1M pxe and the ramdisk at the end. */ + +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000)) + #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0xa000000\0" \ - "kernel_addr_r=" __stringify(SDRAM_OFFSET(2000000)) "\0" \ - "fdt_addr_r=" __stringify(SDRAM_OFFSET(3000000)) "\0" \ - "scriptaddr=" __stringify(SDRAM_OFFSET(3100000)) "\0" \ - "pxefile_addr_r=" __stringify(SDRAM_OFFSET(3200000)) "\0" \ - "ramdisk_addr_r=" __stringify(SDRAM_OFFSET(3300000)) "\0" + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" \ + "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" + +#define DFU_ALT_INFO_RAM \ + "dfu_alt_info_ram=" \ + "kernel ram " KERNEL_ADDR_R " 0x1000000;" \ + "fdt ram " FDT_ADDR_R " 0x100000;" \ + "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0" #ifdef CONFIG_MMC #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 +#define BOOT_TARGET_DEVICES_MMC_EXTRA(func) func(MMC, mmc, 1) +#else +#define BOOT_TARGET_DEVICES_MMC_EXTRA(func) +#endif #else #define BOOT_TARGET_DEVICES_MMC(func) +#define BOOT_TARGET_DEVICES_MMC_EXTRA(func) #endif #ifdef CONFIG_AHCI @@ -431,6 +452,7 @@ extern int soft_i2c_gpio_scl; #define BOOT_TARGET_DEVICES(func) \ func(FEL, fel, na) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_MMC_EXTRA(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ func(PXE, pxe, na) \ @@ -480,6 +502,7 @@ extern int soft_i2c_gpio_scl; #define CONFIG_EXTRA_ENV_SETTINGS \ CONSOLE_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ + DFU_ALT_INFO_RAM \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "console=ttyS0,115200\0" \ BOOTCMD_SUNXI_COMPAT \ diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 502e795..7942865 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -307,7 +307,6 @@ */ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 5754369..5788a70 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -141,7 +141,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 4cb7902..ec0a812 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -66,7 +66,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 97fe796..c1bd179 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -66,7 +66,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/taurus.h b/include/configs/taurus.h index a5e7090..1d6f9c3 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -159,7 +159,6 @@ #define CONFIG_CMD_SPI #define CONFIG_CMD_SF #define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH_STMICRO #define TAURUS_SPI_MASK (1 << 4) #define TAURUS_SPI_CS_PIN AT91_PIN_PA3 diff --git a/include/configs/tb100.h b/include/configs/tb100.h index e3c41ef..e06484f 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -35,8 +35,6 @@ /* * UART configuration */ -#define CONFIG_DW_SERIAL -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 166666666 #define CONFIG_BAUDRATE 115200 @@ -44,7 +42,6 @@ /* * Ethernet PHY configuration */ -#define CONFIG_PHYLIB #define CONFIG_PHY_GIGE /* diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index 3297424..a9e3e66 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -34,9 +34,7 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* SPI */ -#define CONFIG_TEGRA20_SLINK #define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 5bb9e48..ba819c4 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -39,8 +39,7 @@ /* * NS16550 Configuration */ -#define CONFIG_TEGRA_SERIAL -#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* * Common HW configuration. diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 7fa35a1..e726040 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -145,7 +145,6 @@ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 01d8233..ba652ca 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -108,7 +108,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 9697431..edbd820 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -19,14 +19,9 @@ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC -#ifndef CONFIG_SPL_BUILD -# define CONFIG_OMAP_SERIAL -#endif - #include <asm/arch/omap.h> /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 2b2c060..a7206f4 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -58,13 +58,10 @@ #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO /* UART Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_MEM32 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 -#else -#define CONFIG_KEYSTONE_SERIAL #endif #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE @@ -77,7 +74,6 @@ #endif /* SPI Configuration */ -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_DAVINCI_SPI #define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6) #define CONFIG_SF_DEFAULT_SPEED 30000000 @@ -162,7 +158,6 @@ #define I2C_BUS_MAX 3 /* EEPROM definitions */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 @@ -252,7 +247,7 @@ "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ "get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \ - "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ + "burn_uboot_spi=sf probe; sf erase 0 0x80000; " \ "sf write ${loadaddr} 0 ${filesize}\0" \ "burn_uboot_nand=nand erase 0 0x100000; " \ "nand write ${loadaddr} 0 ${filesize}\0" \ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index e399a87..1c71cb6 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -18,10 +18,6 @@ #include <asm/arch/cpu.h> #include <asm/arch/omap.h> -#ifndef CONFIG_SPL_BUILD -# define CONFIG_OMAP_SERIAL -#endif - /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 @@ -36,11 +32,10 @@ /* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #ifdef CONFIG_SPL_BUILD # define CONFIG_SYS_NS16550_SERIAL # define CONFIG_SYS_NS16550_REG_SIZE (-4) -# define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #endif #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 741f71f..08130eb 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -57,14 +57,11 @@ /* * Hardware drivers */ -#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_CLK 48000000 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_COM3 UART3_BASE -#else -#define CONFIG_OMAP_SERIAL #endif #define CONFIG_CONS_INDEX 3 diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 5acbc92..2d492f8 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -50,13 +50,10 @@ /* * Hardware drivers */ -#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_CLK 48000000 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 -#else -#define CONFIG_OMAP_SERIAL #endif /* diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 295e163..31d7757 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -48,7 +48,6 @@ #define CONFIG_MXC_SPI /* SPI Flash */ -#define CONFIG_SPI_FLASH_STMICRO #define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 0ab69e6..f5f5324 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -86,7 +86,6 @@ #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ @@ -113,7 +112,6 @@ /* EEPROM */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_EEPROM_BUS_NUM 1 diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 2ab5511..8761f8d 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -22,8 +22,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE /* SPI */ -#define CONFIG_TEGRA20_SFLASH -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_CMD_SPI #define CONFIG_CMD_SF @@ -58,10 +56,8 @@ /* PCI host support */ #define CONFIG_PCI -#define CONFIG_PCI_TEGRA #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM /* PCI networking support */ #define CONFIG_RTL8169 diff --git a/include/configs/tseries.h b/include/configs/tseries.h index 4265b8a..93e3454 100644 --- a/include/configs/tseries.h +++ b/include/configs/tseries.h @@ -266,7 +266,6 @@ MMCARGS #define CONFIG_OMAP3_SPI #define CONFIG_CMD_SPI #define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_SPL_SPI_SUPPORT diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 1e71703..463c687 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 #ifdef CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE #define CONFIG_SYS_NS16550_CLK 12288000 #define CONFIG_SYS_NS16550_REG_SIZE -2 @@ -189,14 +188,14 @@ "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ "bootm $fit_addr_r\0" #else -#define CONFIG_BOOTFILE "uImage" +#define CONFIG_CMD_BOOTZ +#define CONFIG_BOOTFILE "zImage" #define LINUXBOOT_ENV_SETTINGS \ "fdt_addr=0x00100000\0" \ "fdt_addr_r=0x84100000\0" \ "fdt_size=0x00008000\0" \ - "fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "kernel_addr=0x00200000\0" \ - "kernel_addr_r=0x84200000\0" \ + "kernel_addr_r=0x80208000\0" \ "kernel_size=0x00800000\0" \ "ramdisk_addr=0x00a00000\0" \ "ramdisk_addr_r=0x84a00000\0" \ @@ -205,15 +204,15 @@ "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \ "setexpr fdt_addr $nor_base + $fdt_addr &&" \ - "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ + "bootz $kernel_addr $ramdisk_addr $fdt_addr\0" \ "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ - "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ + "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ "tftpboot $fdt_addr_r $fdt_file &&" \ - "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" + "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/vct.h b/include/configs/vct.h index 92726c8..872f2f0 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -54,7 +54,6 @@ #endif #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 UART_1_BASE #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index f5df4fb..bc2d441 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -251,7 +251,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/venice2.h b/include/configs/venice2.h index a374cd9..4a0b448 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -36,7 +36,6 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index a99d712..c767f90 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -35,8 +35,6 @@ #elif CONFIG_TARGET_VEXPRESS64_JUNO #define CONFIG_SYS_TEXT_BASE 0xe0000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#else -#error "Unknown board variant" #endif #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ @@ -108,8 +106,6 @@ #elif CONFIG_TARGET_VEXPRESS64_JUNO #define GICD_BASE (0x2C010000) #define GICC_BASE (0x2C02f000) -#else -#error "Unknown board variant" #endif #endif /* !CONFIG_GICV3 */ @@ -165,15 +161,20 @@ #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) /* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ -#define PHYS_SDRAM_2 (0x880000000) /* Top 16MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x01000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE -#define PHYS_SDRAM_2_SIZE 0x180000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_2 (0x880000000) +#define PHYS_SDRAM_2_SIZE 0x180000000 +#else +#define CONFIG_NR_DRAM_BANKS 1 +#endif + /* Enable memtest */ #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 @@ -273,14 +274,8 @@ #define CONFIG_BOOTDELAY 1 -#else -#error "Unknown board variant" #endif -/* Do not preserve environment */ -#define CONFIG_ENV_IS_NOWHERE 1 -#define CONFIG_ENV_SIZE 0x1000 - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ @@ -291,28 +286,35 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_MAXARGS 64 /* max command args */ -/* Flash memory is available on the Juno board only */ -#ifndef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_SYS_NO_FLASH +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_SYS_FLASH_BASE 0x08000000 +/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ +#define CONFIG_SYS_MAX_FLASH_SECT 259 +/* Store environment at top of flash in the same location as blank.img */ +/* in the Juno firmware. */ +#define CONFIG_ENV_ADDR 0x0BFC0000 +#define CONFIG_ENV_SECT_SIZE 0x00010000 #else +#define CONFIG_SYS_FLASH_BASE 0x0C000000 +/* 256 x 256KiB sectors */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 +/* Store environment at top of flash */ +#define CONFIG_ENV_ADDR 0x0FFC0000 +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#endif + #define CONFIG_CMD_ARMFLASH #define CONFIG_SYS_FLASH_CFI 1 #define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT -#define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* Timeout values in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ - -/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ -#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ +#define FLASH_MAX_SECTOR_SIZE 0x00040000 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_IS_IN_FLASH 1 -#endif #endif /* __VEXPRESS_AEMV8A_H */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index a3ea2e0..34df6f0 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -96,11 +96,9 @@ #define CONFIG_PHY_MICREL /* QSPI Configs*/ -#define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_SPANSION #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_SYS_FSL_QSPI_LE diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 7f5f089..714ebee 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -200,7 +200,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/walnut.h b/include/configs/walnut.h index 8b803a2..dd6b519 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -80,7 +80,6 @@ */ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/x600.h b/include/configs/x600.h index 58f1aca..0263c50 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -77,7 +77,6 @@ /* Ethernet config options */ #define CONFIG_MII -#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 9fb1a7a..c575dab 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -14,7 +14,6 @@ #define CONFIG_MISC_INIT_R #define CONFIG_X86_MRC_ADDR 0xfffa0000 -#define CONFIG_CACHE_MRC_SIZE_KB 512 #define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 3a18f69..70ec103 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -59,7 +59,6 @@ /*----------------------------------------------------------------------- * Serial Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \ 9600, 19200, 38400, 115200} @@ -153,8 +152,6 @@ * CPU Features */ -#define CONFIG_SYS_X86_TSC_TIMER - #define CONFIG_SYS_STACK_SIZE (32 * 1024) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MALLOC_LEN 0x200000 @@ -165,10 +162,6 @@ /*----------------------------------------------------------------------- * FLASH configuration */ -#define CONFIG_ICH_SPI -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SPI_FLASH_GIGADEVICE #define CONFIG_SYS_NO_FLASH #define CONFIG_CMD_SF #define CONFIG_CMD_SF_TEST diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h index 1abd0ef..eb400d0 100644 --- a/include/configs/xilinx-ppc.h +++ b/include/configs/xilinx-ppc.h @@ -109,7 +109,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } #else #ifdef XPAR_UARTNS550_0_BASEADDR -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 4 #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index e990512..03f7450 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -84,7 +84,6 @@ /* SPI */ #ifdef CONFIG_ZYNQ_SPI -# define CONFIG_SPI_FLASH_SST # define CONFIG_CMD_SF #endif @@ -108,6 +107,14 @@ #define CONFIG_SYS_LOAD_ADDR 0x8000000 #if defined(CONFIG_ZYNQMP_USB) +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_XHCI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_XHCI_ZYNQMP + #define CONFIG_USB_DWC3 #define CONFIG_USB_DWC3_GADGET @@ -177,13 +184,10 @@ #define CONFIG_SYS_MAXARGS 64 /* Ethernet driver */ -#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) || \ - defined(CONFIG_ZYNQ_GEM2) || defined(CONFIG_ZYNQ_GEM3) +#if defined(CONFIG_ZYNQ_GEM) # define CONFIG_NET_MULTI -# define CONFIG_ZYNQ_GEM # define CONFIG_MII # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_PHYLIB # define CONFIG_PHY_MARVELL # define CONFIG_PHY_TI #endif @@ -217,9 +221,6 @@ #define CONFIG_CMD_SCSI #endif -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ - #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) #define CONFIG_CMD_BOOTI diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index 8bdb5c9..ec39211 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -15,15 +15,14 @@ #ifndef __CONFIG_ZYNQMP_EP_H #define __CONFIG_ZYNQMP_EP_H -#define CONFIG_ZYNQ_GEM0 -#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 - #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 #define CONFIG_ZYNQ_I2C0 #define CONFIG_SYS_I2C_ZYNQ #define CONFIG_ZYNQ_EEPROM #define CONFIG_AHCI +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ + ZYNQMP_USB1_XHCI_BASEADDR} #include <configs/xilinx_zynqmp.h> diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h index 005f149..5bc926f 100644 --- a/include/configs/xpedite1000.h +++ b/include/configs/xpedite1000.h @@ -97,7 +97,6 @@ extern void out32(unsigned int, unsigned long); * Serial Port */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 3e09635..96b357b 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -214,7 +214,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index 39bdb88..b2d6a1e 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -177,7 +177,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index c687555..8b4d4d9 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -213,7 +213,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index f971f8b..c7e25d9 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -204,7 +204,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 8508a80..0cffab8 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -122,7 +122,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index d10f1dd..0ab6083 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -46,28 +46,19 @@ #define CONFIG_ZYNQ_GPIO /* Ethernet driver */ -#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) -# define CONFIG_ZYNQ_GEM +#if defined(CONFIG_ZYNQ_GEM) # define CONFIG_MII # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_PHYLIB # define CONFIG_PHY_MARVELL # define CONFIG_BOOTP_SERVERIP # define CONFIG_BOOTP_BOOTPATH # define CONFIG_BOOTP_GATEWAY # define CONFIG_BOOTP_HOSTNAME # define CONFIG_BOOTP_MAY_FAIL -# if !defined(CONFIG_ZYNQ_GEM_EMIO0) -# define CONFIG_ZYNQ_GEM_EMIO0 0 -# endif -# if !defined(CONFIG_ZYNQ_GEM_EMIO1) -# define CONFIG_ZYNQ_GEM_EMIO1 0 -# endif #endif /* SPI */ #ifdef CONFIG_ZYNQ_SPI -# define CONFIG_SPI_FLASH_SST # define CONFIG_CMD_SF #endif @@ -75,9 +66,6 @@ #ifdef CONFIG_ZYNQ_QSPI # define CONFIG_SF_DEFAULT_SPEED 30000000 # define CONFIG_SPI_FLASH_ISSI -# define CONFIG_SPI_FLASH_SPANSION -# define CONFIG_SPI_FLASH_STMICRO -# define CONFIG_SPI_FLASH_WINBOND # define CONFIG_SPI_FLASH_BAR # define CONFIG_CMD_SF #endif @@ -302,7 +290,6 @@ /* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) -# define CONFIG_API # define CONFIG_SYS_MMC_MAX_DEVICE 1 #endif @@ -380,16 +367,16 @@ /* The highest 64k OCM address */ #define OCM_HIGH_ADDR 0xffff0000 -/* Just define any reasonable size */ -#define CONFIG_SPL_STACK_SIZE 0x1000 - -/* SPL stack position - and stack goes down */ -#define CONFIG_SPL_STACK (OCM_HIGH_ADDR + CONFIG_SPL_STACK_SIZE) - /* On the top of OCM space */ -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_STACK + \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x1000 +#define CONFIG_SYS_SPL_MALLOC_START OCM_HIGH_ADDR +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000 + +/* + * SPL stack position - and stack goes down + * 0xfffffe00 is used for putting wfi loop. + * Set it up as limit for now. + */ +#define CONFIG_SPL_STACK 0xfffffe00 /* BSS setup */ #define CONFIG_SPL_BSS_START_ADDR 0x100000 diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h index b5ffafb..169ee36 100644 --- a/include/configs/zynq_microzed.h +++ b/include/configs/zynq_microzed.h @@ -12,9 +12,6 @@ #define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) -#define CONFIG_ZYNQ_GEM0 -#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 - #define CONFIG_SYS_NO_FLASH #define CONFIG_ZYNQ_SDHCI0 diff --git a/include/configs/zynq_picozed.h b/include/configs/zynq_picozed.h index ffc73bd..47fad66 100644 --- a/include/configs/zynq_picozed.h +++ b/include/configs/zynq_picozed.h @@ -12,9 +12,6 @@ #define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) -#define CONFIG_ZYNQ_GEM0 -#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 - #define CONFIG_SYS_NO_FLASH #define CONFIG_ZYNQ_SDHCI1 diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index 468a6bc..c52a655 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -12,9 +12,6 @@ #define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) -#define CONFIG_ZYNQ_GEM0 -#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 - #define CONFIG_SYS_NO_FLASH #define CONFIG_ZYNQ_SDHCI0 diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h index 63224dd..32ea1f3 100644 --- a/include/configs/zynq_zc770.h +++ b/include/configs/zynq_zc770.h @@ -15,10 +15,7 @@ #define CONFIG_SYS_NO_FLASH #if defined(CONFIG_ZC770_XM010) -# define CONFIG_ZYNQ_GEM0 -# define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 # define CONFIG_ZYNQ_SDHCI0 -# define CONFIG_ZYNQ_SPI #elif defined(CONFIG_ZC770_XM011) @@ -26,8 +23,6 @@ # undef CONFIG_SYS_NO_FLASH #elif defined(CONFIG_ZC770_XM013) -# define CONFIG_ZYNQ_GEM1 -# define CONFIG_ZYNQ_GEM_PHY_ADDR1 7 #endif diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h index 6ec6117..1488bfe 100644 --- a/include/configs/zynq_zed.h +++ b/include/configs/zynq_zed.h @@ -12,9 +12,6 @@ #define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024) -#define CONFIG_ZYNQ_GEM0 -#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 - #define CONFIG_SYS_NO_FLASH #define CONFIG_ZYNQ_USB diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h index e2270cd..c53ba79 100644 --- a/include/configs/zynq_zybo.h +++ b/include/configs/zynq_zybo.h @@ -13,11 +13,9 @@ #define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024) -#define CONFIG_ZYNQ_GEM0 -#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 - #define CONFIG_SYS_NO_FLASH +#define CONFIG_ZYNQ_USB #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_BOOT_FREEBSD diff --git a/include/dm/platform_data/serial_stm32.h b/include/dm/platform_data/serial_stm32.h new file mode 100644 index 0000000..d1cfcbe --- /dev/null +++ b/include/dm/platform_data/serial_stm32.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2015 + * Kamil Lulko, <kamil.lulko@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SERIAL_STM32_H +#define __SERIAL_STM32_H + +/* Information about a serial port */ +struct stm32_serial_platdata { + struct stm32_usart *base; /* address of registers in physical memory */ +}; + +#endif /* __SERIAL_STM32_H */ diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h new file mode 100644 index 0000000..87acf4a --- /dev/null +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_GPLL 3 +#define ARMCLK 4 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI 65 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_NANDC 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_OTGPHY0 93 +#define SCLK_LCDC 100 +#define SCLK_HDMI 109 +#define SCLK_HEVC 111 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_VIDEO 125 +#define SCLK_MAC 151 +#define SCLK_MACREF 152 +#define SCLK_SFC 160 + +#define DCLK_LCDC 190 + +/* aclk gates */ +#define ACLK_DMAC2 194 +#define ACLK_LCDC 197 +#define ACLK_VIO 203 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_SPI 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_HDMI 360 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_WDT 368 + +/* hclk gates */ +#define HCLK_OTG0 449 +#define HCLK_OTG1 450 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_I2S 462 +#define HCLK_LCDC 465 +#define HCLK_ROM 467 +#define HCLK_VIO_BUS 472 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_CORE0_POR 8 +#define SRST_CORE1_POR 9 +#define SRST_L2C 12 +#define SRST_TOPDBG 13 +#define SRST_STRC_SYS_A 14 +#define SRST_PD_CORE_NIU 15 + +#define SRST_TIMER2 16 +#define SRST_CPUSYS_H 17 +#define SRST_AHB2APB_H 19 +#define SRST_TIMER3 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S 24 +#define SRST_DDR_PLL 25 +#define SRST_GPU_DLL 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_CORE_DLL 29 +#define SRST_EFUSE_P 30 +#define SRST_ACODEC_P 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_SFC 47 + +#define SRST_PWM0 48 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_GRF 55 +#define SRST_PERIPHSYS_A 57 +#define SRST_PERIPHSYS_H 58 +#define SRST_PERIPHSYS_P 59 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_MAC 66 +#define SRST_NANDC 68 +#define SRST_USBOTG0 69 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_OTGC1 74 +#define SRST_DDRMSCH 79 + +#define SRST_MMC0 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_WDT 86 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 + +#define SRST_HDMI_P 96 +#define SRST_VIO_BUS_H 99 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_USBPOR 105 + +#define SRST_VCODEC_A 112 +#define SRST_VCODEC_H 113 +#define SRST_VIO1_A 114 +#define SRST_HEVC 115 +#define SRST_VCODEC_NIU_A 116 +#define SRST_LCDC1_A 117 +#define SRST_LCDC1_H 118 +#define SRST_LCDC1_D 119 +#define SRST_GPU 120 +#define SRST_GPU_NIU_A 122 + +#define SRST_DBG_P 131 + +#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index 25cf42c..05b0817 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -105,6 +105,8 @@ /* Status Register */ #define DWMCI_BUSY (1 << 9) +#define DWMCI_FIFO_MASK 0x1ff +#define DWMCI_FIFO_SHIFT 17 /* FIFOTH Register */ #define MSIZE(x) ((x) << 28) @@ -180,6 +182,9 @@ struct dwmci_host { unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq); struct mmc_config cfg; + + /* use fifo mode to read and write data */ + bool fifo_mode; }; struct dwmci_idmac { diff --git a/include/fdtdec.h b/include/fdtdec.h index 79826d7..d82dc35 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -128,10 +128,6 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */ - COMPAT_NVIDIA_TEGRA124_PCIE, /* Tegra 124 PCIe controller */ - COMPAT_NVIDIA_TEGRA210_PCIE, /* Tegra 210 PCIe controller */ - COMPAT_NVIDIA_TEGRA30_PCIE, /* Tegra 30 PCIe controller */ - COMPAT_NVIDIA_TEGRA20_PCIE, /* Tegra 20 PCIe controller */ COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, /* Tegra124 XUSB pad controller */ COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, @@ -171,6 +167,7 @@ enum fdt_compat_id { COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */ COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */ COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ + COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */ COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ diff --git a/include/flash.h b/include/flash.h index 13e0384..f53ace7 100644 --- a/include/flash.h +++ b/include/flash.h @@ -8,7 +8,10 @@ #ifndef _FLASH_H_ #define _FLASH_H_ -#ifndef CONFIG_SYS_NO_FLASH +#ifndef CONFIG_SYS_MAX_FLASH_SECT +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#endif + /*----------------------------------------------------------------------- * FLASH Info: contains chip specific data, per FLASH bank */ @@ -503,6 +506,4 @@ extern flash_info_t *flash_get_info(ulong base); #define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */ #define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */ -#endif /* !CONFIG_SYS_NO_FLASH */ - #endif /* _FLASH_H_ */ diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h index 3cdc94e..92c5437 100644 --- a/include/fsl-mc/fsl_dpbp.h +++ b/include/fsl-mc/fsl_dpbp.h @@ -20,6 +20,8 @@ /* Command IDs */ #define DPBP_CMDID_CLOSE 0x800 #define DPBP_CMDID_OPEN 0x804 +#define DPBP_CMDID_CREATE 0x904 +#define DPBP_CMDID_DESTROY 0x900 #define DPBP_CMDID_ENABLE 0x002 #define DPBP_CMDID_DISABLE 0x003 @@ -83,6 +85,52 @@ int dpbp_close(struct fsl_mc_io *mc_io, uint16_t token); /** + * struct dpbp_cfg - Structure representing DPBP configuration + * @options: place holder + */ +struct dpbp_cfg { + uint32_t options; +}; + +/** + * dpbp_create() - Create the DPBP object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @token: Returned token; use in subsequent API calls + * + * Create the DPBP object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpbp_open function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpbp_cfg *cfg, + uint16_t *token); + +/** + * dpbp_destroy() - Destroy the DPBP object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; error code otherwise. + */ +int dpbp_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** * dpbp_enable() - Enable the DPBP. * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h index 9e83a2e..0bc0b44 100644 --- a/include/fsl-mc/fsl_dpio.h +++ b/include/fsl-mc/fsl_dpio.h @@ -14,6 +14,8 @@ /* Command IDs */ #define DPIO_CMDID_CLOSE 0x800 #define DPIO_CMDID_OPEN 0x803 +#define DPIO_CMDID_CREATE 0x903 +#define DPIO_CMDID_DESTROY 0x900 #define DPIO_CMDID_ENABLE 0x002 #define DPIO_CMDID_DISABLE 0x003 @@ -25,6 +27,14 @@ MC_CMD_OP(cmd, 0, 0, 32, int, dpio_id) /* cmd, param, offset, width, type, arg_name */ +#define DPIO_CMD_CREATE(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 16, 2, enum dpio_channel_mode, \ + cfg->channel_mode);\ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->num_priorities);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ #define DPIO_RSP_GET_ATTR(cmd, attr) \ do { \ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\ @@ -90,6 +100,56 @@ enum dpio_channel_mode { }; /** + * struct dpio_cfg - Structure representing DPIO configuration + * @channel_mode: Notification channel mode + * @num_priorities: Number of priorities for the notification channel (1-8); + * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' + */ +struct dpio_cfg { + enum dpio_channel_mode channel_mode; + uint8_t num_priorities; +}; + +/** + * dpio_create() - Create the DPIO object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @token: Returned token; use in subsequent API calls + * + * Create the DPIO object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpio_open() function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpio_cfg *cfg, + uint16_t *token); + +/** + * dpio_destroy() - Destroy the DPIO object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** * dpio_enable() - Enable the DPIO, allow I/O portal operations. * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h new file mode 100644 index 0000000..24f0b48 --- /dev/null +++ b/include/fsl-mc/fsl_dpmac.h @@ -0,0 +1,468 @@ +/* + * Freescale Layerscape MC I/O wrapper + * + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Author: Prabhakar Kushwaha <prabhakar@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_DPMAC_H +#define __FSL_DPMAC_H + +/* DPMAC Version */ +#define DPMAC_VER_MAJOR 3 +#define DPMAC_VER_MINOR 1 + +/* Command IDs */ +#define DPMAC_CMDID_CLOSE 0x800 +#define DPMAC_CMDID_OPEN 0x80c +#define DPMAC_CMDID_CREATE 0x90c +#define DPMAC_CMDID_DESTROY 0x900 + +#define DPMAC_CMDID_GET_ATTR 0x004 +#define DPMAC_CMDID_RESET 0x005 + +#define DPMAC_CMDID_MDIO_READ 0x0c0 +#define DPMAC_CMDID_MDIO_WRITE 0x0c1 +#define DPMAC_CMDID_GET_LINK_CFG 0x0c2 +#define DPMAC_CMDID_SET_LINK_STATE 0x0c3 +#define DPMAC_CMDID_GET_COUNTER 0x0c4 + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_CREATE(cmd, cfg) \ + MC_CMD_OP(cmd, 0, 0, 32, int, cfg->mac_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_OPEN(cmd, dpmac_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, dpmac_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_RSP_GET_ATTRIBUTES(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 32, int, attr->phy_id);\ + MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\ + MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\ + MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\ + MC_RSP_OP(cmd, 1, 32, 8, enum dpmac_link_type, attr->link_type);\ + MC_RSP_OP(cmd, 1, 40, 8, enum dpmac_eth_if, attr->eth_if);\ + MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->max_rate);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_MDIO_READ(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \ + MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_RSP_MDIO_READ(cmd, data) \ + MC_RSP_OP(cmd, 0, 16, 16, uint16_t, data) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_MDIO_WRITE(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \ + MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \ + MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->data); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_RSP_GET_LINK_CFG(cmd, cfg) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \ + MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_SET_LINK_STATE(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \ + MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \ + MC_CMD_OP(cmd, 2, 0, 1, int, cfg->up); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_GET_COUNTER(cmd, type) \ + MC_CMD_OP(cmd, 0, 0, 8, enum dpmac_counter, type) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_RSP_GET_COUNTER(cmd, counter) \ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter) + +/* Data Path MAC API + * Contains initialization APIs and runtime control APIs for DPMAC + */ + +struct fsl_mc_io; + +/** + * dpmac_open() - Open a control session for the specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpmac_id: DPMAC unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpmac_create function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_open(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + int dpmac_id, + uint16_t *token); + +/** + * dpmac_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_close(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** + * enum dpmac_link_type - DPMAC link type + * @DPMAC_LINK_TYPE_NONE: No link + * @DPMAC_LINK_TYPE_FIXED: Link is fixed type + * @DPMAC_LINK_TYPE_PHY: Link by PHY ID + * @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type + */ +enum dpmac_link_type { + DPMAC_LINK_TYPE_NONE, + DPMAC_LINK_TYPE_FIXED, + DPMAC_LINK_TYPE_PHY, + DPMAC_LINK_TYPE_BACKPLANE +}; + +/** + * enum dpmac_eth_if - DPMAC Ethrnet interface + * @DPMAC_ETH_IF_MII: MII interface + * @DPMAC_ETH_IF_RMII: RMII interface + * @DPMAC_ETH_IF_SMII: SMII interface + * @DPMAC_ETH_IF_GMII: GMII interface + * @DPMAC_ETH_IF_RGMII: RGMII interface + * @DPMAC_ETH_IF_SGMII: SGMII interface + * @DPMAC_ETH_IF_QSGMII: QSGMII interface + * @DPMAC_ETH_IF_XAUI: XAUI interface + * @DPMAC_ETH_IF_XFI: XFI interface + */ +enum dpmac_eth_if { + DPMAC_ETH_IF_MII, + DPMAC_ETH_IF_RMII, + DPMAC_ETH_IF_SMII, + DPMAC_ETH_IF_GMII, + DPMAC_ETH_IF_RGMII, + DPMAC_ETH_IF_SGMII, + DPMAC_ETH_IF_QSGMII, + DPMAC_ETH_IF_XAUI, + DPMAC_ETH_IF_XFI +}; + +/** + * struct dpmac_cfg - Structure representing DPMAC configuration + * @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP, + * the MAC IDs are continuous. + * For example: 2 WRIOPs, 16 MACs in each: + * MAC IDs for the 1st WRIOP: 1-16, + * MAC IDs for the 2nd WRIOP: 17-32. + */ +struct dpmac_cfg { + int mac_id; +}; + +/** + * dpmac_create() - Create the DPMAC object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @token: Returned token; use in subsequent API calls + * + * Create the DPMAC object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpmac_open function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpmac_cfg *cfg, + uint16_t *token); + +/** + * dpmac_destroy() - Destroy the DPMAC object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * + * Return: '0' on Success; error code otherwise. + */ +int dpmac_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/* DPMAC IRQ Index and Events */ + +/* IRQ index */ +#define DPMAC_IRQ_INDEX 0 +/* IRQ event - indicates a change in link state */ +#define DPMAC_IRQ_EVENT_LINK_CFG_REQ 0x00000001 +/* irq event - Indicates that the link state changed */ +#define DPMAC_IRQ_EVENT_LINK_CHANGED 0x00000002 + +/** + * struct dpmac_attr - Structure representing DPMAC attributes + * @id: DPMAC object ID + * @phy_id: PHY ID + * @link_type: link type + * @eth_if: Ethernet interface + * @max_rate: Maximum supported rate - in Mbps + * @version: DPMAC version + */ +struct dpmac_attr { + int id; + int phy_id; + enum dpmac_link_type link_type; + enum dpmac_eth_if eth_if; + uint32_t max_rate; + /** + * struct version - Structure representing DPMAC version + * @major: DPMAC major version + * @minor: DPMAC minor version + */ + struct { + uint16_t major; + uint16_t minor; + } version; +}; + +/** + * dpmac_get_attributes - Retrieve DPMAC attributes. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_get_attributes(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_attr *attr); + +/** + * struct dpmac_mdio_cfg - DPMAC MDIO read/write parameters + * @phy_addr: MDIO device address + * @reg: Address of the register within the Clause 45 PHY device from which data + * is to be read + * @data: Data read/write from/to MDIO + */ +struct dpmac_mdio_cfg { + uint8_t phy_addr; + uint8_t reg; + uint16_t data; +}; + +/** + * dpmac_mdio_read() - Perform MDIO read transaction + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @cfg: Structure with MDIO transaction parameters + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_mdio_read(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_mdio_cfg *cfg); + +/** + * dpmac_mdio_write() - Perform MDIO write transaction + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @cfg: Structure with MDIO transaction parameters + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_mdio_write(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_mdio_cfg *cfg); + +/* DPMAC link configuration/state options */ + +/* Enable auto-negotiation */ +#define DPMAC_LINK_OPT_AUTONEG 0x0000000000000001ULL +/* Enable half-duplex mode */ +#define DPMAC_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL +/* Enable pause frames */ +#define DPMAC_LINK_OPT_PAUSE 0x0000000000000004ULL +/* Enable a-symmetric pause frames */ +#define DPMAC_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL + +/** + * struct dpmac_link_cfg - Structure representing DPMAC link configuration + * @rate: Link's rate - in Mbps + * @options: Enable/Disable DPMAC link cfg features (bitmap) + */ +struct dpmac_link_cfg { + uint32_t rate; + uint64_t options; +}; + +/** + * dpmac_get_link_cfg() - Get Ethernet link configuration + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @cfg: Returned structure with the link configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_get_link_cfg(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_link_cfg *cfg); + +/** + * struct dpmac_link_state - DPMAC link configuration request + * @rate: Rate in Mbps + * @options: Enable/Disable DPMAC link cfg features (bitmap) + * @up: Link state + */ +struct dpmac_link_state { + uint32_t rate; + uint64_t options; + int up; +}; + +/** + * dpmac_set_link_state() - Set the Ethernet link status + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @link_state: Link state configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_set_link_state(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_link_state *link_state); + +/** + * enum dpni_counter - DPNI counter types + * @DPMAC_CNT_ING_FRAME_64: counts 64-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-octet frame and larger + * (up to max frame length specified), + * good or bad. + * @DPMAC_CNT_ING_FRAG: counts packet which is shorter than 64 octets received + * with a wrong CRC + * @DPMAC_CNT_ING_JABBER: counts packet longer than the maximum frame length + * specified, with a bad frame check sequence. + * @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped packet due to internal errors. + * Occurs when a receive FIFO overflows. + * Includes also packets truncated as a result of + * the receive FIFO overflow. + * @DPMAC_CNT_ING_ALIGN_ERR: counts frame with an alignment error + * (optional used for wrong SFD) + * @DPMAC_CNT_EGR_UNDERSIZED: counts packet transmitted that was less than 64 + * octets long with a good CRC. + * @DPMAC_CNT_ING_OVERSIZED: counts packet longer than the maximum frame length + * specified, with a good frame check sequence. + * @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frame (regular and PFC). + * @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frame transmitted + * (regular and PFC). + * @DPMAC_CNT_ING_BYTE: counts octet received except preamble for all valid + * frames and valid pause frames. + * @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frame + * @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frame + * @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad packet received. + * @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frame + * @DPMAC_CNT_ING_ERR_FRAME: counts frame received with an error + * (except for undersized/fragment frame) + * @DPMAC_CNT_EGR_BYTE: counts octet transmitted except preamble for all valid + * frames and valid pause frames transmitted. + * @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frame + * @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frame + * @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frame + * @DPMAC_CNT_EGR_ERR_FRAME: counts frame transmitted with an error + * @DPMAC_CNT_ING_GOOD_FRAME: counts frame received without error, including + * pause frames. + */ +enum dpmac_counter { + DPMAC_CNT_ING_FRAME_64, + DPMAC_CNT_ING_FRAME_127, + DPMAC_CNT_ING_FRAME_255, + DPMAC_CNT_ING_FRAME_511, + DPMAC_CNT_ING_FRAME_1023, + DPMAC_CNT_ING_FRAME_1518, + DPMAC_CNT_ING_FRAME_1519_MAX, + DPMAC_CNT_ING_FRAG, + DPMAC_CNT_ING_JABBER, + DPMAC_CNT_ING_FRAME_DISCARD, + DPMAC_CNT_ING_ALIGN_ERR, + DPMAC_CNT_EGR_UNDERSIZED, + DPMAC_CNT_ING_OVERSIZED, + DPMAC_CNT_ING_VALID_PAUSE_FRAME, + DPMAC_CNT_EGR_VALID_PAUSE_FRAME, + DPMAC_CNT_ING_BYTE, + DPMAC_CNT_ING_MCAST_FRAME, + DPMAC_CNT_ING_BCAST_FRAME, + DPMAC_CNT_ING_ALL_FRAME, + DPMAC_CNT_ING_UCAST_FRAME, + DPMAC_CNT_ING_ERR_FRAME, + DPMAC_CNT_EGR_BYTE, + DPMAC_CNT_EGR_MCAST_FRAME, + DPMAC_CNT_EGR_BCAST_FRAME, + DPMAC_CNT_EGR_UCAST_FRAME, + DPMAC_CNT_EGR_ERR_FRAME, + DPMAC_CNT_ING_GOOD_FRAME +}; + +/** + * dpmac_get_counter() - Read a specific DPMAC counter + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @type: The requested counter + * @counter: Returned counter value + * + * Return: The requested counter; '0' otherwise. + */ +int dpmac_get_counter(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpmac_counter type, + uint64_t *counter); + +#endif /* __FSL_DPMAC_H */ diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h index e9a4712..140a009 100644 --- a/include/fsl-mc/fsl_dpni.h +++ b/include/fsl-mc/fsl_dpni.h @@ -13,6 +13,8 @@ /* Command IDs */ #define DPNI_CMDID_OPEN 0x801 #define DPNI_CMDID_CLOSE 0x800 +#define DPNI_CMDID_CREATE 0x901 +#define DPNI_CMDID_DESTROY 0x900 #define DPNI_CMDID_ENABLE 0x002 #define DPNI_CMDID_DISABLE 0x003 @@ -48,6 +50,46 @@ #define DPNI_CMD_OPEN(cmd, dpni_id) \ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id) +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_CREATE(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->adv.max_tcs); \ + MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->adv.max_senders); \ + MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]); \ + MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]); \ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]); \ + MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]); \ + MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]); \ + MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]); \ + MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->adv.options); \ + MC_CMD_OP(cmd, 2, 0, 8, uint8_t, cfg->adv.max_unicast_filters); \ + MC_CMD_OP(cmd, 2, 8, 8, uint8_t, cfg->adv.max_multicast_filters); \ + MC_CMD_OP(cmd, 2, 16, 8, uint8_t, cfg->adv.max_vlan_filters); \ + MC_CMD_OP(cmd, 2, 24, 8, uint8_t, cfg->adv.max_qos_entries); \ + MC_CMD_OP(cmd, 2, 32, 8, uint8_t, cfg->adv.max_qos_key_size); \ + MC_CMD_OP(cmd, 2, 48, 8, uint8_t, cfg->adv.max_dist_key_size); \ + MC_CMD_OP(cmd, 2, 56, 8, enum net_prot, cfg->adv.start_hdr); \ + MC_CMD_OP(cmd, 3, 0, 8, uint8_t, cfg->adv.max_dist_per_tc[0]); \ + MC_CMD_OP(cmd, 3, 8, 8, uint8_t, cfg->adv.max_dist_per_tc[1]); \ + MC_CMD_OP(cmd, 3, 16, 8, uint8_t, cfg->adv.max_dist_per_tc[2]); \ + MC_CMD_OP(cmd, 3, 24, 8, uint8_t, cfg->adv.max_dist_per_tc[3]); \ + MC_CMD_OP(cmd, 3, 32, 8, uint8_t, cfg->adv.max_dist_per_tc[4]); \ + MC_CMD_OP(cmd, 3, 40, 8, uint8_t, cfg->adv.max_dist_per_tc[5]); \ + MC_CMD_OP(cmd, 3, 48, 8, uint8_t, cfg->adv.max_dist_per_tc[6]); \ + MC_CMD_OP(cmd, 3, 56, 8, uint8_t, cfg->adv.max_dist_per_tc[7]); \ + MC_CMD_OP(cmd, 4, 0, 16, uint16_t, \ + cfg->adv.ipr_cfg.max_reass_frm_size); \ + MC_CMD_OP(cmd, 4, 16, 16, uint16_t, \ + cfg->adv.ipr_cfg.min_frag_size_ipv4); \ + MC_CMD_OP(cmd, 4, 32, 16, uint16_t, \ + cfg->adv.ipr_cfg.min_frag_size_ipv6); \ + MC_CMD_OP(cmd, 4, 48, 8, uint8_t, cfg->adv.max_policers); \ + MC_CMD_OP(cmd, 4, 56, 8, uint8_t, cfg->adv.max_congestion_ctrl); \ + MC_CMD_OP(cmd, 5, 0, 16, uint16_t, \ + cfg->adv.ipr_cfg.max_open_frames_ipv4); \ + MC_CMD_OP(cmd, 5, 16, 16, uint16_t, \ + cfg->adv.ipr_cfg.max_open_frames_ipv6); \ +} while (0) /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_SET_POOLS(cmd, cfg) \ @@ -475,6 +517,53 @@ int dpni_close(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token); +/* DPNI configuration options */ + +/** + * Allow different distribution key profiles for different traffic classes; + * if not set, a single key profile is assumed + */ +#define DPNI_OPT_ALLOW_DIST_KEY_PER_TC 0x00000001 + +/** + * Disable all non-error transmit confirmation; error frames are reported + * back to a common Tx error queue + */ +#define DPNI_OPT_TX_CONF_DISABLED 0x00000002 + +/* Disable per-sender private Tx confirmation/error queue */ +#define DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED 0x00000004 + +/** + * Support distribution based on hashed key; + * allows statistical distribution over receive queues in a traffic class + */ +#define DPNI_OPT_DIST_HASH 0x00000010 + +/** + * Support distribution based on flow steering; + * allows explicit control of distribution over receive queues in a traffic + * class + */ +#define DPNI_OPT_DIST_FS 0x00000020 + +/* Unicast filtering support */ +#define DPNI_OPT_UNICAST_FILTER 0x00000080 +/* Multicast filtering support */ +#define DPNI_OPT_MULTICAST_FILTER 0x00000100 +/* VLAN filtering support */ +#define DPNI_OPT_VLAN_FILTER 0x00000200 +/* Support IP reassembly on received packets */ +#define DPNI_OPT_IPR 0x00000800 +/* Support IP fragmentation on transmitted packets */ +#define DPNI_OPT_IPF 0x00001000 +/* VLAN manipulation support */ +#define DPNI_OPT_VLAN_MANIPULATION 0x00010000 +/* Support masking of QoS lookup keys */ +#define DPNI_OPT_QOS_MASK_SUPPORT 0x00020000 +/* Support masking of Flow Steering lookup keys */ +#define DPNI_OPT_FS_MASK_SUPPORT 0x00040000 + /** * struct dpni_ipr_cfg - Structure representing IP reassembly configuration * @max_reass_frm_size: Maximum size of the reassembled frame @@ -492,6 +581,106 @@ struct dpni_ipr_cfg { }; /** + * struct dpni_cfg - Structure representing DPNI configuration + * @mac_addr: Primary MAC address + * @adv: Advanced parameters; default is all zeros; + * use this structure to change default settings + */ +struct dpni_cfg { + uint8_t mac_addr[6]; + /** + * struct adv - Advanced parameters + * @options: Mask of available options; use 'DPNI_OPT_<X>' values + * @start_hdr: Selects the packet starting header for parsing; + * 'NET_PROT_NONE' is treated as default: 'NET_PROT_ETH' + * @max_senders: Maximum number of different senders; used as the number + * of dedicated Tx flows; Non-power-of-2 values are rounded + * up to the next power-of-2 value as hardware demands it; + * '0' will be treated as '1' + * @max_tcs: Maximum number of traffic classes (for both Tx and Rx); + * '0' will e treated as '1' + * @max_dist_per_tc: Maximum distribution size per Rx traffic class; + * Must be set to the required value minus 1; + * i.e. 0->1, 1->2, ... ,255->256; + * Non-power-of-2 values are rounded up to the next + * power-of-2 value as hardware demands it + * @max_unicast_filters: Maximum number of unicast filters; + * '0' is treated as '16' + * @max_multicast_filters: Maximum number of multicast filters; + * '0' is treated as '64' + * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in + * the QoS table; '0' is treated as '64' + * @max_qos_key_size: Maximum key size for the QoS look-up; + * '0' is treated as '24' which is enough for IPv4 + * 5-tuple + * @max_dist_key_size: Maximum key size for the distribution; + * '0' is treated as '24' which is enough for IPv4 5-tuple + * @max_policers: Maximum number of policers; + * should be between '0' and max_tcs + * @max_congestion_ctrl: Maximum number of congestion control groups + * (CGs); covers early drop and congestion notification + * requirements for traffic classes; + * should be between '0' and max_tcs + * @ipr_cfg: IP reassembly configuration + */ + struct { + uint32_t options; + enum net_prot start_hdr; + uint8_t max_senders; + uint8_t max_tcs; + uint8_t max_dist_per_tc[DPNI_MAX_TC]; + uint8_t max_unicast_filters; + uint8_t max_multicast_filters; + uint8_t max_vlan_filters; + uint8_t max_qos_entries; + uint8_t max_qos_key_size; + uint8_t max_dist_key_size; + uint8_t max_policers; + uint8_t max_congestion_ctrl; + struct dpni_ipr_cfg ipr_cfg; + } adv; +}; + +/** + * dpni_create() - Create the DPNI object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @token: Returned token; use in subsequent API calls + * + * Create the DPNI object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpni_open() function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpni_cfg *cfg, + uint16_t *token); + +/** + * dpni_destroy() - Destroy the DPNI object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * Return: '0' on Success; error code otherwise. + */ +int dpni_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** * struct dpni_pools_cfg - Structure representing buffer pools configuration * @num_dpbp: Number of DPBPs * @pools: Array of buffer pools parameters; The number of valid entries diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h index b2cd2cb..a87179d 100644 --- a/include/fsl-mc/fsl_dprc.h +++ b/include/fsl-mc/fsl_dprc.h @@ -16,10 +16,13 @@ /* Command IDs */ #define DPRC_CMDID_CLOSE 0x800 #define DPRC_CMDID_OPEN 0x805 +#define DPRC_CMDID_CREATE 0x905 #define DPRC_CMDID_GET_ATTR 0x004 #define DPRC_CMDID_RESET_CONT 0x005 +#define DPRC_CMDID_CREATE_CONT 0x151 +#define DPRC_CMDID_DESTROY_CONT 0x152 #define DPRC_CMDID_GET_CONT_ID 0x830 #define DPRC_CMDID_GET_OBJ_COUNT 0x159 #define DPRC_CMDID_GET_OBJ 0x15A @@ -40,6 +43,41 @@ MC_CMD_OP(cmd, 0, 0, 32, int, container_id) /* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_CREATE_CONTAINER(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->icid); \ + MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->options); \ + MC_CMD_OP(cmd, 1, 32, 32, int, cfg->portal_id); \ + MC_CMD_OP(cmd, 2, 0, 8, char, cfg->label[0]);\ + MC_CMD_OP(cmd, 2, 8, 8, char, cfg->label[1]);\ + MC_CMD_OP(cmd, 2, 16, 8, char, cfg->label[2]);\ + MC_CMD_OP(cmd, 2, 24, 8, char, cfg->label[3]);\ + MC_CMD_OP(cmd, 2, 32, 8, char, cfg->label[4]);\ + MC_CMD_OP(cmd, 2, 40, 8, char, cfg->label[5]);\ + MC_CMD_OP(cmd, 2, 48, 8, char, cfg->label[6]);\ + MC_CMD_OP(cmd, 2, 56, 8, char, cfg->label[7]);\ + MC_CMD_OP(cmd, 3, 0, 8, char, cfg->label[8]);\ + MC_CMD_OP(cmd, 3, 8, 8, char, cfg->label[9]);\ + MC_CMD_OP(cmd, 3, 16, 8, char, cfg->label[10]);\ + MC_CMD_OP(cmd, 3, 24, 8, char, cfg->label[11]);\ + MC_CMD_OP(cmd, 3, 32, 8, char, cfg->label[12]);\ + MC_CMD_OP(cmd, 3, 40, 8, char, cfg->label[13]);\ + MC_CMD_OP(cmd, 3, 48, 8, char, cfg->label[14]);\ + MC_CMD_OP(cmd, 3, 56, 8, char, cfg->label[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_CREATE_CONTAINER(cmd, child_container_id, child_portal_offset)\ +do { \ + MC_RSP_OP(cmd, 1, 0, 32, int, child_container_id); \ + MC_RSP_OP(cmd, 2, 0, 64, uint64_t, child_portal_offset);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id) + +/* cmd, param, offset, width, type, arg_name */ #define DPRC_CMD_RESET_CONTAINER(cmd, child_container_id) \ MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id) @@ -467,6 +505,52 @@ struct dprc_cfg { }; /** + * dprc_create_container() - Create child container + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @cfg: Child container configuration + * @child_container_id: Returned child container ID + * @child_portal_offset: Returned child portal offset from MC portal base + * + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_create_container(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dprc_cfg *cfg, + int *child_container_id, + uint64_t *child_portal_offset); + +/** + * dprc_destroy_container() - Destroy child container. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @child_container_id: ID of the container to destroy + * + * This function terminates the child container, so following this call the + * child container ID becomes invalid. + * + * Notes: + * - All resources and objects of the destroyed container are returned to the + * parent container or destroyed if were created be the destroyed container. + * - This function destroy all the child containers of the specified + * container prior to destroying the container itself. + * + * warning: Only the parent container is allowed to destroy a child policy + * Container 0 can't be destroyed + * + * Return: '0' on Success; Error code otherwise. + * + */ +int dprc_destroy_container(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + int child_container_id); + +/** * dprc_reset_container - Reset child container. * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index 9517a4a..ffe6da5 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -29,6 +29,9 @@ ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \ (_portal_id) * SOC_MC_PORTAL_STRIDE)) +#define MC_PORTAL_OFFSET_TO_PORTAL_ID(_portal_offset) \ + ((_portal_offset) / SOC_MC_PORTAL_STRIDE) + struct mc_ccsr_registers { u32 reg_gcr1; u32 reserved1; @@ -50,7 +53,12 @@ struct mc_ccsr_registers { }; int get_mc_boot_status(void); +int get_dpl_apply_status(void); +#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +int get_aiop_apply_status(void); +#endif +u64 mc_get_dram_addr(void); unsigned long mc_get_dram_block_size(void); int fsl_mc_ldpaa_init(bd_t *bis); -void fsl_mc_ldpaa_exit(bd_t *bis); +int fsl_mc_ldpaa_exit(bd_t *bd); #endif diff --git a/include/fsl-mc/fsl_mc_private.h b/include/fsl-mc/fsl_mc_private.h index 9f06978..17e0611 100644 --- a/include/fsl-mc/fsl_mc_private.h +++ b/include/fsl-mc/fsl_mc_private.h @@ -13,18 +13,20 @@ #include <linux/compat.h> #include <linux/types.h> #include <linux/stringify.h> +#include <phy.h> #include <fsl-mc/fsl_mc_sys.h> #include <fsl-mc/fsl_mc_cmd.h> #include <fsl-mc/fsl_dprc.h> #include <fsl-mc/fsl_dpbp.h> +#include <fsl-mc/fsl_dpni.h> extern struct fsl_mc_io *dflt_mc_io; /** * struct dpbp_node - DPBP strucuture * @uint16_t handle: DPBP object handle - * @int dpbp_id: DPBP id + * @struct dpbp_attr: DPBP attribute */ struct fsl_dpbp_obj { uint16_t dpbp_handle; @@ -40,11 +42,29 @@ extern struct fsl_dpbp_obj *dflt_dpbp; */ struct fsl_dpio_obj { int dpio_id; + uint16_t dpio_handle; struct qbman_swp *sw_portal; /** SW portal object */ }; extern struct fsl_dpio_obj *dflt_dpio; -int mc_init(void); -int ldpaa_eth_init(struct dprc_obj_desc obj_desc); +/** + * struct dpni_node - DPNI strucuture + * @int dpni_id: DPNI id + * @uint16_t handle: DPNI object handle + * @struct dpni_attr: DPNI attributes + * @struct dpni_buffer_layout: DPNI buffer layout + */ +struct fsl_dpni_obj { + int dpni_id; + uint16_t dpni_handle; + struct dpni_attr dpni_attrs; + struct dpni_buffer_layout buf_layout; +}; + +extern struct fsl_dpni_obj *dflt_dpni; + +int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr); +int ldpaa_eth_init(int dpmac_id, phy_interface_t enet_if); +int mc_apply_dpl(u64 mc_dpl_addr); #endif /* _FSL_MC_PRIVATE_H_ */ diff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h index ca8e440..6dc159d 100644 --- a/include/fsl-mc/ldpaa_wriop.h +++ b/include/fsl-mc/ldpaa_wriop.h @@ -40,8 +40,8 @@ enum wriop_port { struct wriop_dpmac_info { u8 enabled; u8 id; - u8 phy_addr; u8 board_mux; + int phy_addr; void *phy_regs; phy_interface_t enet_if; struct phy_device *phydev; @@ -56,6 +56,7 @@ extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS]; void wriop_init_dpmac(int, int, int); void wriop_disable_dpmac(int); void wriop_enable_dpmac(int); +u8 wriop_is_enabled_dpmac(int dpmac_id); void wriop_set_mdio(int, struct mii_dev *); struct mii_dev *wriop_get_mdio(int); void wriop_set_phy_address(int, int); diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 1ac092b..9aaf6b3 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -131,6 +131,7 @@ void board_add_ram_info(int use_default); /* processor specific function */ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num, int step); +void remove_unused_controllers(fsl_ddr_info_t *info); /* board specific function */ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index c79fce0..4b022d4 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -33,6 +33,15 @@ #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ +#define DDR4_RTT_OFF 0 +#define DDR4_RTT_60_OHM 1 /* RZQ/4 */ +#define DDR4_RTT_120_OHM 2 /* RZQ/2 */ +#define DDR4_RTT_40_OHM 3 /* RZQ/6 */ +#define DDR4_RTT_240_OHM 4 /* RZQ/1 */ +#define DDR4_RTT_48_OHM 5 /* RZQ/5 */ +#define DDR4_RTT_80_OHM 6 /* RZQ/3 */ +#define DDR4_RTT_34_OHM 7 /* RZQ/7 */ + #define DDR2_RTT_OFF 0 #define DDR2_RTT_75_OHM 1 #define DDR2_RTT_150_OHM 2 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/include/fsl_errata.h index 4861e3bf..8441f91 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/include/fsl_errata.h @@ -1,14 +1,21 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013 - 2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _ASM_FSL_ERRATA_H -#define _ASM_FSL_ERRATA_H +#ifndef _FSL_ERRATA_H +#define _FSL_ERRATA_H #include <common.h> +#if defined(CONFIG_PPC) #include <asm/processor.h> +#elif defined(CONFIG_LS102XA) +#include <asm/arch-ls102xa/immap_ls102xa.h> +#elif defined(CONFIG_FSL_LAYERSCAPE) +#include <asm/arch/soc.h> +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 static inline bool has_erratum_a006379(void) @@ -26,7 +33,6 @@ static inline bool has_erratum_a006379(void) return false; } #endif -#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 static inline bool has_erratum_a007186(void) @@ -51,3 +57,36 @@ static inline bool has_erratum_a007186(void) return false; } #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008378 +static inline bool has_erratum_a008378(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + + switch (soc) { +#ifdef CONFIG_LS102XA + case SOC_VER_LS1020: + case SOC_VER_LS1021: + case SOC_VER_LS1022: + case SOC_VER_SLS1020: + return IS_SVR_REV(svr, 1, 0); +#endif +#ifdef CONFIG_PPC + case SVR_T1023: + case SVR_T1024: + return IS_SVR_REV(svr, 1, 0); + case SVR_T1020: + case SVR_T1022: + case SVR_T1040: + case SVR_T1042: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); +#endif + default: + return false; + } +} +#endif + +#endif /* _FSL_ERRATA_H */ diff --git a/include/fsl_usb.h b/include/fsl_usb.h index 8e3dded..187e384 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -181,6 +181,7 @@ static inline bool has_erratum_a007792(void) switch (soc) { case SVR_T4240: case SVR_T4160: + case SVR_T4080: return IS_SVR_REV(svr, 2, 0); case SVR_T1024: case SVR_T1023: diff --git a/include/fsl_validate.h b/include/fsl_validate.h index 92dd98b..a62dc74 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -83,7 +83,9 @@ struct fsl_secboot_img_hdr { u32 sign_len; /* length of the signature in bytes */ union { u32 psgtable; /* ptr to SG table */ +#ifndef CONFIG_ESBC_ADDR_64BIT u32 pimg; /* ptr to ESBC client image */ +#endif }; union { u32 sg_entries; /* no of entries in SG table */ @@ -97,7 +99,12 @@ struct fsl_secboot_img_hdr { u32 reserved1[2]; u32 fsl_uid_1; u32 oem_uid_1; - u32 reserved2[2]; + union { + u32 reserved2[2]; +#ifdef CONFIG_ESBC_ADDR_64BIT + u64 pimg64; /* 64 bit pointer to ESBC Image */ +#endif + }; u32 ie_flag; u32 ie_key_sel; }; diff --git a/include/i2c.h b/include/i2c.h index 6493931..1f5ae45 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -499,7 +499,8 @@ int i2c_get_chip(struct udevice *bus, uint chip_addr, uint offset_len, struct udevice **devp); /** - * i2c_get_chip() - get a device to use to access a chip on a bus number + * i2c_get_chip_for_busnum() - get a device to use to access a chip on + * a bus number * * This returns the device for the given chip address on a particular bus * number. diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h index dd934a0..6d1e365 100644 --- a/include/linux/usb/dwc3.h +++ b/include/linux/usb/dwc3.h @@ -204,7 +204,6 @@ struct dwc3 { /* offset: 0xC100 */ void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode); void dwc3_core_soft_reset(struct dwc3 *dwc3_reg); int dwc3_core_init(struct dwc3 *dwc3_reg); -void usb_phy_reset(struct dwc3 *dwc3_reg); void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val); #endif #endif /* __DWC3_H_ */ diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 602a413..e922e32 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -54,11 +54,18 @@ struct fsl_xhci { #if defined(CONFIG_LS102XA) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 -#elif defined(CONFIG_LS2085A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR +#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 +#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR +#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 +#elif defined(CONFIG_LS1043A) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR +#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR #endif #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ - CONFIG_SYS_FSL_XHCI_USB2_ADDR} + CONFIG_SYS_FSL_XHCI_USB2_ADDR, \ + CONFIG_SYS_FSL_XHCI_USB3_ADDR} #endif /* _ASM_ARCH_XHCI_FSL_H_ */ diff --git a/include/netdev.h b/include/netdev.h index 28eab46..de74b9a 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -87,9 +87,6 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, int txpp, int rxpp); int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, unsigned long ctrl_addr); -int zynq_gem_of_init(const void *blob); -int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, - int phy_addr, u32 emio); /* * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface * exported by a public hader file, we need a global definition at this point. diff --git a/include/part.h b/include/part.h index 8b5ac12..720a867 100644 --- a/include/part.h +++ b/include/part.h @@ -267,6 +267,41 @@ int is_valid_gpt_buf(block_dev_desc_t *dev_desc, void *buf); * @return - '0' on success, otherwise error */ int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf); + +/** + * gpt_verify_headers() - Function to read and CRC32 check of the GPT's header + * and partition table entries (PTE) + * + * As a side effect if sets gpt_head and gpt_pte so they point to GPT data. + * + * @param dev_desc - block device descriptor + * @param gpt_head - pointer to GPT header data read from medium + * @param gpt_pte - pointer to GPT partition table enties read from medium + * + * @return - '0' on success, otherwise error + */ +int gpt_verify_headers(block_dev_desc_t *dev_desc, gpt_header *gpt_head, + gpt_entry **gpt_pte); + +/** + * gpt_verify_partitions() - Function to check if partitions' name, start and + * size correspond to '$partitions' env variable + * + * This function checks if on medium stored GPT data is in sync with information + * provided in '$partitions' environment variable. Specificially, name, start + * and size of the partition is checked. + * + * @param dev_desc - block device descriptor + * @param partitions - partition data read from '$partitions' env variable + * @param parts - number of partitions read from '$partitions' env variable + * @param gpt_head - pointer to GPT header data read from medium + * @param gpt_pte - pointer to GPT partition table enties read from medium + * + * @return - '0' on success, otherwise error + */ +int gpt_verify_partitions(block_dev_desc_t *dev_desc, + disk_partition_t *partitions, int parts, + gpt_header *gpt_head, gpt_entry **gpt_pte); #endif #endif /* _PART_H */ diff --git a/include/pci.h b/include/pci.h index ed135a5..2adca85 100644 --- a/include/pci.h +++ b/include/pci.h @@ -537,6 +537,8 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev /* * Structure of a PCI controller (host bridge) + * + * With driver model this is dev_get_uclass_priv(bus) */ struct pci_controller { #ifdef CONFIG_DM_PCI @@ -654,6 +656,7 @@ extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) /* For driver model these are defined in macros in pci_compat.c */ +#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) extern int pci_hose_read_config_byte(struct pci_controller *hose, pci_dev_t dev, int where, u8 *val); extern int pci_hose_read_config_word(struct pci_controller *hose, @@ -666,6 +669,7 @@ extern int pci_hose_write_config_word(struct pci_controller *hose, pci_dev_t dev, int where, u16 val); extern int pci_hose_write_config_dword(struct pci_controller *hose, pci_dev_t dev, int where, u32 val); +#endif #ifndef CONFIG_DM_PCI extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); @@ -676,6 +680,13 @@ extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); #endif +void pciauto_region_init(struct pci_region *res); +void pciauto_region_align(struct pci_region *res, pci_size_t size); +void pciauto_config_init(struct pci_controller *hose); +int pciauto_region_allocate(struct pci_region *res, pci_size_t size, + pci_addr_t *bar); + +#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, pci_dev_t dev, int where, u8 *val); extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, @@ -694,9 +705,6 @@ extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); extern int pci_hose_scan(struct pci_controller *hose); extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); -extern void pciauto_region_init(struct pci_region* res); -extern void pciauto_region_align(struct pci_region *res, pci_size_t size); -extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar); extern void pciauto_setup_device(struct pci_controller *hose, pci_dev_t dev, int bars_num, struct pci_region *mem, @@ -706,7 +714,6 @@ extern void pciauto_prescan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus); extern void pciauto_postscan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus); -extern void pciauto_config_init(struct pci_controller *hose); extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); @@ -737,6 +744,7 @@ extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, unsigned short device, unsigned short class); #endif +#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */ const char * pci_class_str(u8 class); int pci_last_busno(void); @@ -745,6 +753,7 @@ int pci_last_busno(void); extern void pci_mpc85xx_init (struct pci_controller *hose); #endif +#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) /** * pci_write_bar32() - Write the address of a BAR including control bits * @@ -781,6 +790,7 @@ u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); */ pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, struct pci_device_id *ids, int *indexp); +#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */ /* Access sizes for PCI reads and writes */ enum pci_size_t { @@ -1039,6 +1049,7 @@ int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); */ int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); +#ifdef CONFIG_DM_PCI_COMPAT /* Compatibility with old naming */ static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, u32 value) @@ -1091,6 +1102,70 @@ static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, return pci_read_config8(pcidev, offset, valuep); } +#endif /* CONFIG_DM_PCI_COMPAT */ + +/** + * dm_pciauto_config_device() - configure a device ready for use + * + * Space is allocated for each PCI base address register (BAR) so that the + * devices are mapped into memory and I/O space ready for use. + * + * @dev: Device to configure + * @return 0 if OK, -ve on error + */ +int dm_pciauto_config_device(struct udevice *dev); + +/** + * pci_conv_32_to_size() - convert a 32-bit read value to the given size + * + * Some PCI buses must always perform 32-bit reads. The data must then be + * shifted and masked to reflect the required access size and offset. This + * function performs this transformation. + * + * @value: Value to transform (32-bit value read from @offset & ~3) + * @offset: Register offset that was read + * @size: Required size of the result + * @return the value that would have been obtained if the read had been + * performed at the given offset with the correct size + */ +ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size); + +/** + * pci_conv_size_to_32() - update a 32-bit value to prepare for a write + * + * Some PCI buses must always perform 32-bit writes. To emulate a smaller + * write the old 32-bit data must be read, updated with the required new data + * and written back as a 32-bit value. This function performs the + * transformation from the old value to the new value. + * + * @value: Value to transform (32-bit value read from @offset & ~3) + * @offset: Register offset that should be written + * @size: Required size of the write + * @return the value that should be written as a 32-bit access to @offset & ~3. + */ +ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, + enum pci_size_t size); + +/** + * pci_get_controller() - obtain the controller to use for a bus + * + * @dev: Device to check + * @return pointer to the controller device for this bus + */ +struct udevice *pci_get_controller(struct udevice *dev); + +/** + * pci_get_regions() - obtain pointers to all the region types + * + * @dev: Device to check + * @iop: Returns a pointer to the I/O region, or NULL if none + * @memp: Returns a pointer to the memory region, or NULL if none + * @prefp: Returns a pointer to the pre-fetch region, or NULL if none + * @return the number of non-NULL regions returned, normally 3 + */ +int pci_get_regions(struct udevice *dev, struct pci_region **iop, + struct pci_region **memp, struct pci_region **prefp); + /** * struct dm_pci_emul_ops - PCI device emulator operations */ diff --git a/include/timer.h b/include/timer.h index cdf385d..7fee17e 100644 --- a/include/timer.h +++ b/include/timer.h @@ -8,36 +8,45 @@ #define _TIMER_H_ /* + * timer_conv_64 - convert 32-bit counter value to 64-bit + * + * @count: 32-bit counter value + * @return: 64-bit counter value + */ +u64 timer_conv_64(u32 count); + +/* * Get the current timer count * - * @dev: The Timer device + * @dev: The timer device * @count: pointer that returns the current timer count * @return: 0 if OK, -ve on error */ -int timer_get_count(struct udevice *dev, unsigned long *count); +int timer_get_count(struct udevice *dev, u64 *count); + /* * Get the timer input clock frequency * - * @dev: The Timer device + * @dev: The timer device * @return: the timer input clock frequency */ unsigned long timer_get_rate(struct udevice *dev); /* - * struct timer_ops - Driver model Timer operations + * struct timer_ops - Driver model timer operations * - * The uclass interface is implemented by all Timer devices which use + * The uclass interface is implemented by all timer devices which use * driver model. */ struct timer_ops { /* * Get the current timer count * - * @dev: The Timer device - * @count: pointer that returns the current timer count + * @dev: The timer device + * @count: pointer that returns the current 64-bit timer count * @return: 0 if OK, -ve on error */ - int (*get_count)(struct udevice *dev, unsigned long *count); + int (*get_count)(struct udevice *dev, u64 *count); }; /* diff --git a/include/usb.h b/include/usb.h index 55b9268..2539364 100644 --- a/include/usb.h +++ b/include/usb.h @@ -266,8 +266,9 @@ int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int interval); int usb_disable_asynch(int disable); int usb_maxpacket(struct usb_device *dev, unsigned long pipe); -int usb_get_configuration_no(struct usb_device *dev, unsigned char *buffer, - int cfgno); +int usb_get_configuration_no(struct usb_device *dev, int cfgno, + unsigned char *buffer, int length); +int usb_get_configuration_len(struct usb_device *dev, int cfgno); int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type, unsigned char id, void *buf, int size); int usb_get_class_descriptor(struct usb_device *dev, int ifnum, @@ -874,6 +875,18 @@ int legacy_hub_port_reset(struct usb_device *dev, int port, int hub_port_reset(struct udevice *dev, int port, unsigned short *portstat); +/* + * usb_find_usb2_hub_address_port() - Get hub address and port for TT setting + * + * Searches for the first HS hub above the given device. If a + * HS hub is found, the hub address and the port the device is + * connected to is return, as required for SPLIT transactions + * + * @param: udev full speed or low speed device + */ +void usb_find_usb2_hub_address_port(struct usb_device *udev, + uint8_t *hub_address, uint8_t *hub_port); + /** * usb_alloc_new_device() - Allocate a new device * diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h new file mode 100644 index 0000000..302e9a3 --- /dev/null +++ b/include/usb/dwc2_udc.h @@ -0,0 +1,25 @@ +/* + * drivers/usb/gadget/dwc2_udc.h + * Designware DWC2 on-chip full/high speed USB device controllers + * Copyright (C) 2005 for Samsung Electronics + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DWC2_USB_GADGET +#define __DWC2_USB_GADGET + +#define PHY0_SLEEP (1 << 5) + +struct dwc2_plat_otg_data { + int (*phy_control)(int on); + unsigned int regs_phy; + unsigned int regs_otg; + unsigned int usb_phy_ctrl; + unsigned int usb_flags; + unsigned int usb_gusbcfg; +}; + +int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata); + +#endif /* __DWC2_USB_GADGET */ diff --git a/lib/Kconfig b/lib/Kconfig index 30e84ed..9d580e4 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -36,6 +36,16 @@ config SYS_VSNPRINTF Thumb-2, about 420 bytes). Enable this option for safety when using sprintf() with data you do not control. +config USE_TINY_PRINTF + bool "Enable tiny printf() version" + help + This option enables a tiny, stripped down printf version. + This should only be used in space limited environments, + like SPL versions with hard memory limits. This version + reduces the code size by about 2.5KiB on armv7. + + The supported format specifiers are %c, %s, %u/%d and %x. + config REGEX bool "Enable regular expression support" default y if NET diff --git a/lib/Makefile b/lib/Makefile index 6c36278..dd36f25 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -80,7 +80,18 @@ obj-y += string.o obj-y += time.o obj-$(CONFIG_TRACE) += trace.o obj-$(CONFIG_LIB_UUID) += uuid.o -obj-y += vsprintf.o obj-$(CONFIG_LIB_RAND) += rand.o +ifdef CONFIG_SPL_BUILD +# SPL U-Boot may use full-printf, tiny-printf or none at all +ifdef CONFIG_USE_TINY_PRINTF +obj-$(CONFIG_SPL_SERIAL_SUPPORT) += tiny-printf.o panic.o strto.o +else +obj-$(CONFIG_SPL_SERIAL_SUPPORT) += vsprintf.o panic.o strto.o +endif +else +# Main U-Boot always uses the full printf support +obj-y += vsprintf.o panic.o strto.o +endif + subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2 diff --git a/lib/fdtdec.c b/lib/fdtdec.c index e0e6bb4..ae0b708 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -34,10 +34,6 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"), COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"), COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"), - COMPAT(NVIDIA_TEGRA124_PCIE, "nvidia,tegra124-pcie"), - COMPAT(NVIDIA_TEGRA210_PCIE, "nvidia,tegra210-pcie"), - COMPAT(NVIDIA_TEGRA30_PCIE, "nvidia,tegra30-pcie"), - COMPAT(NVIDIA_TEGRA20_PCIE, "nvidia,tegra20-pcie"), COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"), COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"), COMPAT(SMSC_LAN9215, "smsc,lan9215"), @@ -75,6 +71,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"), COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"), COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"), + COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), }; diff --git a/lib/panic.c b/lib/panic.c new file mode 100644 index 0000000..e2b8b74 --- /dev/null +++ b/lib/panic.c @@ -0,0 +1,45 @@ +/* + * linux/lib/vsprintf.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */ +/* + * Wirzenius wrote this portably, Torvalds fucked it up :-) + */ + +#include <common.h> +#if !defined(CONFIG_PANIC_HANG) +#include <command.h> +#endif + +static void panic_finish(void) __attribute__ ((noreturn)); + +static void panic_finish(void) +{ + putc('\n'); +#if defined(CONFIG_PANIC_HANG) + hang(); +#else + udelay(100000); /* allow messages to go out */ + do_reset(NULL, 0, 0, NULL); +#endif + while (1) + ; +} + +void panic_str(const char *str) +{ + puts(str); + panic_finish(); +} + +void panic(const char *fmt, ...) +{ + va_list args; + va_start(args, fmt); + vprintf(fmt, args); + va_end(args); + panic_finish(); +} diff --git a/lib/strto.c b/lib/strto.c new file mode 100644 index 0000000..a6c0157 --- /dev/null +++ b/lib/strto.c @@ -0,0 +1,174 @@ +/* + * linux/lib/vsprintf.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */ +/* + * Wirzenius wrote this portably, Torvalds fucked it up :-) + */ + +#include <common.h> +#include <errno.h> +#include <linux/ctype.h> + +unsigned long simple_strtoul(const char *cp, char **endp, + unsigned int base) +{ + unsigned long result = 0; + unsigned long value; + + if (*cp == '0') { + cp++; + if ((*cp == 'x') && isxdigit(cp[1])) { + base = 16; + cp++; + } + + if (!base) + base = 8; + } + + if (!base) + base = 10; + + while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) + ? toupper(*cp) : *cp)-'A'+10) < base) { + result = result*base + value; + cp++; + } + + if (endp) + *endp = (char *)cp; + + return result; +} + +int strict_strtoul(const char *cp, unsigned int base, unsigned long *res) +{ + char *tail; + unsigned long val; + size_t len; + + *res = 0; + len = strlen(cp); + if (len == 0) + return -EINVAL; + + val = simple_strtoul(cp, &tail, base); + if (tail == cp) + return -EINVAL; + + if ((*tail == '\0') || + ((len == (size_t)(tail - cp) + 1) && (*tail == '\n'))) { + *res = val; + return 0; + } + + return -EINVAL; +} + +long simple_strtol(const char *cp, char **endp, unsigned int base) +{ + if (*cp == '-') + return -simple_strtoul(cp + 1, endp, base); + + return simple_strtoul(cp, endp, base); +} + +unsigned long ustrtoul(const char *cp, char **endp, unsigned int base) +{ + unsigned long result = simple_strtoul(cp, endp, base); + switch (**endp) { + case 'G': + result *= 1024; + /* fall through */ + case 'M': + result *= 1024; + /* fall through */ + case 'K': + case 'k': + result *= 1024; + if ((*endp)[1] == 'i') { + if ((*endp)[2] == 'B') + (*endp) += 3; + else + (*endp) += 2; + } + } + return result; +} + +unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base) +{ + unsigned long long result = simple_strtoull(cp, endp, base); + switch (**endp) { + case 'G': + result *= 1024; + /* fall through */ + case 'M': + result *= 1024; + /* fall through */ + case 'K': + case 'k': + result *= 1024; + if ((*endp)[1] == 'i') { + if ((*endp)[2] == 'B') + (*endp) += 3; + else + (*endp) += 2; + } + } + return result; +} + +unsigned long long simple_strtoull(const char *cp, char **endp, + unsigned int base) +{ + unsigned long long result = 0, value; + + if (*cp == '0') { + cp++; + if ((*cp == 'x') && isxdigit(cp[1])) { + base = 16; + cp++; + } + + if (!base) + base = 8; + } + + if (!base) + base = 10; + + while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp - '0' + : (islower(*cp) ? toupper(*cp) : *cp) - 'A' + 10) < base) { + result = result * base + value; + cp++; + } + + if (endp) + *endp = (char *) cp; + + return result; +} + +long trailing_strtoln(const char *str, const char *end) +{ + const char *p; + + if (!end) + end = str + strlen(str); + for (p = end - 1; p > str; p--) { + if (!isdigit(*p)) + return simple_strtoul(p + 1, NULL, 10); + } + + return -1; +} + +long trailing_strtol(const char *str) +{ + return trailing_strtoln(str, NULL); +} @@ -69,9 +69,9 @@ ulong notrace get_tbclk(void) return timer_get_rate(gd->timer); } -unsigned long notrace timer_read_counter(void) +uint64_t notrace get_ticks(void) { - unsigned long count; + u64 count; int ret; ret = dm_timer_init(); @@ -84,7 +84,8 @@ unsigned long notrace timer_read_counter(void) return count; } -#endif /* CONFIG_TIMER */ + +#else /* !CONFIG_TIMER */ uint64_t __weak notrace get_ticks(void) { @@ -97,6 +98,8 @@ uint64_t __weak notrace get_ticks(void) return ((uint64_t)gd->timebase_h << 32) | gd->timebase_l; } +#endif /* CONFIG_TIMER */ + /* Returns time in milliseconds */ static uint64_t notrace tick_to_time(uint64_t tick) { diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c new file mode 100644 index 0000000..403b134 --- /dev/null +++ b/lib/tiny-printf.c @@ -0,0 +1,130 @@ +/* + * Tiny printf version for SPL + * + * Copied from: + * http://www.sparetimelabs.com/printfrevisited/printfrevisited.php + * + * Copyright (C) 2004,2008 Kustaa Nyholm + * + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#include <common.h> +#include <stdarg.h> +#include <serial.h> + +static char *bf; +static char zs; + +static void out(char c) +{ + *bf++ = c; +} + +static void out_dgt(char dgt) +{ + out(dgt + (dgt < 10 ? '0' : 'a' - 10)); + zs = 1; +} + +static void div_out(unsigned int *num, unsigned int div) +{ + unsigned char dgt = 0; + + while (*num >= div) { + *num -= div; + dgt++; + } + + if (zs || dgt > 0) + out_dgt(dgt); +} + +int vprintf(const char *fmt, va_list va) +{ + char ch; + char *p; + unsigned int num; + char buf[12]; + unsigned int div; + + while ((ch = *(fmt++))) { + if (ch != '%') { + putc(ch); + } else { + char lz = 0; + char w = 0; + + ch = *(fmt++); + if (ch == '0') { + ch = *(fmt++); + lz = 1; + } + + if (ch >= '0' && ch <= '9') { + w = 0; + while (ch >= '0' && ch <= '9') { + w = (w * 10) + ch - '0'; + ch = *fmt++; + } + } + bf = buf; + p = bf; + zs = 0; + + switch (ch) { + case 0: + goto abort; + case 'u': + case 'd': + num = va_arg(va, unsigned int); + if (ch == 'd' && (int)num < 0) { + num = -(int)num; + out('-'); + } + for (div = 1000000000; div; div /= 10) + div_out(&num, div); + break; + case 'x': + num = va_arg(va, unsigned int); + for (div = 0x10000000; div; div /= 0x10) + div_out(&num, div); + break; + case 'c': + out((char)(va_arg(va, int))); + break; + case 's': + p = va_arg(va, char*); + break; + case '%': + out('%'); + default: + break; + } + + *bf = 0; + bf = p; + while (*bf++ && w > 0) + w--; + while (w-- > 0) + putc(lz ? '0' : ' '); + while ((ch = *p++)) + putc(ch); + } + } + +abort: + return 0; +} + +int printf(const char *fmt, ...) +{ + va_list va; + int ret; + + va_start(va, fmt); + ret = vprintf(fmt, va); + va_end(va); + + return ret; +} diff --git a/lib/vsprintf.c b/lib/vsprintf.c index 4c82837..24167a1 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -15,176 +15,12 @@ #include <linux/types.h> #include <linux/string.h> #include <linux/ctype.h> -#include <errno.h> #include <common.h> -#if !defined(CONFIG_PANIC_HANG) -#include <command.h> -#endif #include <div64.h> #define noinline __attribute__((noinline)) -unsigned long simple_strtoul(const char *cp, char **endp, - unsigned int base) -{ - unsigned long result = 0; - unsigned long value; - - if (*cp == '0') { - cp++; - if ((*cp == 'x') && isxdigit(cp[1])) { - base = 16; - cp++; - } - - if (!base) - base = 8; - } - - if (!base) - base = 10; - - while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) - ? toupper(*cp) : *cp)-'A'+10) < base) { - result = result*base + value; - cp++; - } - - if (endp) - *endp = (char *)cp; - - return result; -} - -int strict_strtoul(const char *cp, unsigned int base, unsigned long *res) -{ - char *tail; - unsigned long val; - size_t len; - - *res = 0; - len = strlen(cp); - if (len == 0) - return -EINVAL; - - val = simple_strtoul(cp, &tail, base); - if (tail == cp) - return -EINVAL; - - if ((*tail == '\0') || - ((len == (size_t)(tail - cp) + 1) && (*tail == '\n'))) { - *res = val; - return 0; - } - - return -EINVAL; -} - -long simple_strtol(const char *cp, char **endp, unsigned int base) -{ - if (*cp == '-') - return -simple_strtoul(cp + 1, endp, base); - - return simple_strtoul(cp, endp, base); -} - -unsigned long ustrtoul(const char *cp, char **endp, unsigned int base) -{ - unsigned long result = simple_strtoul(cp, endp, base); - switch (**endp) { - case 'G': - result *= 1024; - /* fall through */ - case 'M': - result *= 1024; - /* fall through */ - case 'K': - case 'k': - result *= 1024; - if ((*endp)[1] == 'i') { - if ((*endp)[2] == 'B') - (*endp) += 3; - else - (*endp) += 2; - } - } - return result; -} - -unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base) -{ - unsigned long long result = simple_strtoull(cp, endp, base); - switch (**endp) { - case 'G': - result *= 1024; - /* fall through */ - case 'M': - result *= 1024; - /* fall through */ - case 'K': - case 'k': - result *= 1024; - if ((*endp)[1] == 'i') { - if ((*endp)[2] == 'B') - (*endp) += 3; - else - (*endp) += 2; - } - } - return result; -} - -unsigned long long simple_strtoull(const char *cp, char **endp, - unsigned int base) -{ - unsigned long long result = 0, value; - - if (*cp == '0') { - cp++; - if ((*cp == 'x') && isxdigit(cp[1])) { - base = 16; - cp++; - } - - if (!base) - base = 8; - } - - if (!base) - base = 10; - - while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp - '0' - : (islower(*cp) ? toupper(*cp) : *cp) - 'A' + 10) < base) { - result = result * base + value; - cp++; - } - - if (endp) - *endp = (char *) cp; - - return result; -} - -long trailing_strtoln(const char *str, const char *end) -{ - const char *p; - - if (!end) - end = str + strlen(str); - for (p = end - 1; p > str; p--) { - if (!isdigit(*p)) - return simple_strtoul(p + 1, NULL, 10); - } - - return -1; -} - -long trailing_strtol(const char *str) -{ - return trailing_strtoln(str, NULL); -} - /* we use this so that we can do without the ctype library */ #define is_digit(c) ((c) >= '0' && (c) <= '9') @@ -861,36 +697,43 @@ int sprintf(char *buf, const char *fmt, ...) return i; } -static void panic_finish(void) __attribute__ ((noreturn)); - -static void panic_finish(void) +int printf(const char *fmt, ...) { - putc('\n'); -#if defined(CONFIG_PANIC_HANG) - hang(); -#else - udelay(100000); /* allow messages to go out */ - do_reset(NULL, 0, 0, NULL); -#endif - while (1) - ; -} + va_list args; + uint i; + char printbuffer[CONFIG_SYS_PBSIZE]; -void panic_str(const char *str) -{ - puts(str); - panic_finish(); + va_start(args, fmt); + + /* + * For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args); + va_end(args); + + /* Print the string */ + puts(printbuffer); + return i; } -void panic(const char *fmt, ...) +int vprintf(const char *fmt, va_list args) { - va_list args; - va_start(args, fmt); - vprintf(fmt, args); - va_end(args); - panic_finish(); + uint i; + char printbuffer[CONFIG_SYS_PBSIZE]; + + /* + * For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args); + + /* Print the string */ + puts(printbuffer); + return i; } + void __assert_fail(const char *assertion, const char *file, unsigned line, const char *function) { @@ -541,6 +541,34 @@ static int eth_post_probe(struct udevice *dev) struct eth_pdata *pdata = dev->platdata; unsigned char env_enetaddr[6]; +#if defined(CONFIG_NEEDS_MANUAL_RELOC) + struct eth_ops *ops = eth_get_ops(dev); + static int reloc_done; + + if (!reloc_done) { + if (ops->start) + ops->start += gd->reloc_off; + if (ops->send) + ops->send += gd->reloc_off; + if (ops->recv) + ops->recv += gd->reloc_off; + if (ops->free_pkt) + ops->free_pkt += gd->reloc_off; + if (ops->stop) + ops->stop += gd->reloc_off; +#ifdef CONFIG_MCAST_TFTP + if (ops->mcast) + ops->mcast += gd->reloc_off; +#endif + if (ops->write_hwaddr) + ops->write_hwaddr += gd->reloc_off; + if (ops->read_rom_hwaddr) + ops->read_rom_hwaddr += gd->reloc_off; + + reloc_done++; + } +#endif + priv->state = ETH_STATE_INIT; /* Check if the device has a MAC address in ROM */ diff --git a/post/board/lwmon/Makefile b/post/board/lwmon/Makefile deleted file mode 100644 index 7f6d5a0..0000000 --- a/post/board/lwmon/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += sysmon.o diff --git a/post/board/lwmon/sysmon.c b/post/board/lwmon/sysmon.c deleted file mode 100644 index f521b27..0000000 --- a/post/board/lwmon/sysmon.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <post.h> -#include <common.h> - -/* - * SYSMON test - * - * This test performs the system hardware monitoring. - * The test passes when all the following voltages and temperatures - * are within allowed ranges: - * - * Board temperature - * Front temperature - * +3.3V CPU logic - * +5V logic - * +12V PCMCIA - * +12V CCFL - * +5V standby - * - * CCFL is not enabled if temperature values are not within allowed ranges - * - * See the list off all parameters in the sysmon_table below - */ - -#include <post.h> -#include <watchdog.h> -#include <i2c.h> - -#if CONFIG_POST & CONFIG_SYS_POST_SYSMON - -DECLARE_GLOBAL_DATA_PTR; - -static int sysmon_temp_invalid = 0; - -/* #define DEBUG */ - -typedef struct sysmon_s sysmon_t; -typedef struct sysmon_table_s sysmon_table_t; - -static void sysmon_lm87_init (sysmon_t * this); -static void sysmon_pic_init (sysmon_t * this); -static uint sysmon_i2c_read (sysmon_t * this, uint addr); -static uint sysmon_i2c_read_sgn (sysmon_t * this, uint addr); -static void sysmon_ccfl_disable (sysmon_table_t * this); -static void sysmon_ccfl_enable (sysmon_table_t * this); - -struct sysmon_s -{ - uchar chip; - void (*init)(sysmon_t *); - uint (*read)(sysmon_t *, uint); -}; - -static sysmon_t sysmon_lm87 = - {CONFIG_SYS_I2C_SYSMON_ADDR, sysmon_lm87_init, sysmon_i2c_read}; -static sysmon_t sysmon_lm87_sgn = - {CONFIG_SYS_I2C_SYSMON_ADDR, sysmon_lm87_init, sysmon_i2c_read_sgn}; -static sysmon_t sysmon_pic = - {CONFIG_SYS_I2C_PICIO_ADDR, sysmon_pic_init, sysmon_i2c_read}; - -static sysmon_t * sysmon_list[] = -{ - &sysmon_lm87, - &sysmon_lm87_sgn, - &sysmon_pic, - NULL -}; - -struct sysmon_table_s -{ - char * name; - char * unit_name; - sysmon_t * sysmon; - void (*exec_before)(sysmon_table_t *); - void (*exec_after)(sysmon_table_t *); - - int unit_precision; - int unit_div; - int unit_min; - int unit_max; - uint val_mask; - uint val_min; - uint val_max; - int val_valid; - uint val_min_alt; - uint val_max_alt; - int val_valid_alt; - uint addr; -}; - -static sysmon_table_t sysmon_table[] = -{ - {"Board temperature", " C", &sysmon_lm87_sgn, NULL, sysmon_ccfl_disable, - 1, 1, -128, 127, 0xFF, 0x58, 0xD5, 0, 0x6C, 0xC6, 0, 0x27}, - - {"Front temperature", " C", &sysmon_lm87, NULL, sysmon_ccfl_disable, - 1, 100, -27316, 8984, 0xFF, 0xA4, 0xFC, 0, 0xB2, 0xF1, 0, 0x29}, - - {"+3.3V CPU logic", "V", &sysmon_lm87, NULL, NULL, - 100, 1000, 0, 4386, 0xFF, 0xB6, 0xC9, 0, 0xB6, 0xC9, 0, 0x22}, - - {"+ 5 V logic", "V", &sysmon_lm87, NULL, NULL, - 100, 1000, 0, 6630, 0xFF, 0xB6, 0xCA, 0, 0xB6, 0xCA, 0, 0x23}, - - {"+12 V PCMCIA", "V", &sysmon_lm87, NULL, NULL, - 100, 1000, 0, 15460, 0xFF, 0xBC, 0xD0, 0, 0xBC, 0xD0, 0, 0x21}, - - {"+12 V CCFL", "V", &sysmon_lm87, NULL, sysmon_ccfl_enable, - 100, 1000, 0, 15900, 0xFF, 0xB6, 0xCA, 0, 0xB6, 0xCA, 0, 0x24}, - - {"+ 5 V standby", "V", &sysmon_pic, NULL, NULL, - 100, 1000, 0, 6040, 0xFF, 0xC8, 0xDE, 0, 0xC8, 0xDE, 0, 0x7C}, -}; -static int sysmon_table_size = ARRAY_SIZE(sysmon_table); - -static int conversion_done = 0; - - -int sysmon_init_f (void) -{ - sysmon_t ** l; - ulong reg; - - /* Power on CCFL, PCMCIA */ - reg = pic_read (0x60); - reg |= 0x09; - pic_write (0x60, reg); - - for (l = sysmon_list; *l; l++) { - (*l)->init(*l); - } - - return 0; -} - -void sysmon_reloc (void) -{ - /* Do nothing for now, sysmon_reloc() is required by the sysmon post */ -} - -static char *sysmon_unit_value (sysmon_table_t *s, uint val) -{ - static char buf[32]; - int unit_val = - s->unit_min + (s->unit_max - s->unit_min) * val / s->val_mask; - char *p, sign; - int dec, frac; - - if (val == -1) { - return "I/O ERROR"; - } - - if (unit_val < 0) { - sign = '-'; - unit_val = -unit_val; - } else { - sign = '+'; - } - - p = buf + sprintf(buf, "%c%2d", sign, unit_val / s->unit_div); - - - frac = unit_val % s->unit_div; - - frac /= (s->unit_div / s->unit_precision); - - dec = s->unit_precision; - - if (dec != 1) { - *p++ = '.'; - } - for (dec /= 10; dec != 0; dec /= 10) { - *p++ = '0' + (frac / dec) % 10; - } - strcpy(p, s->unit_name); - - return buf; -} - -static void sysmon_lm87_init (sysmon_t * this) -{ - uchar val; - - /* Detect LM87 chip */ - if (i2c_read(this->chip, 0x40, 1, &val, 1) || (val & 0x80) != 0 || - i2c_read(this->chip, 0x3E, 1, &val, 1) || val != 0x02) { - printf("Error: LM87 not found at 0x%02X\n", this->chip); - return; - } - - /* Configure pins 5,6 as AIN */ - val = 0x03; - if (i2c_write(this->chip, 0x16, 1, &val, 1)) { - printf("Error: can't write LM87 config register\n"); - return; - } - - /* Start monitoring */ - val = 0x01; - if (i2c_write(this->chip, 0x40, 1, &val, 1)) { - printf("Error: can't write LM87 config register\n"); - return; - } -} - -static void sysmon_pic_init (sysmon_t * this) -{ -} - -static uint sysmon_i2c_read (sysmon_t * this, uint addr) -{ - uchar val; - uint res = i2c_read(this->chip, addr, 1, &val, 1); - - return res == 0 ? val : -1; -} - -static uint sysmon_i2c_read_sgn (sysmon_t * this, uint addr) -{ - uchar val; - return i2c_read(this->chip, addr, 1, &val, 1) == 0 ? - 128 + (signed char)val : -1; -} - -static void sysmon_ccfl_disable (sysmon_table_t * this) -{ - if (!this->val_valid_alt) { - sysmon_temp_invalid = 1; - } -} - -static void sysmon_ccfl_enable (sysmon_table_t * this) -{ - ulong reg; - - if (!sysmon_temp_invalid) { - reg = pic_read (0x60); - reg |= 0x06; - pic_write (0x60, reg); - } -} - -int sysmon_post_test (int flags) -{ - int res = 0; - sysmon_table_t * t; - uint val; - - /* - * The A/D conversion on the LM87 sensor takes 300 ms. - */ - if (! conversion_done) { - while (post_time_ms(gd->post_init_f_time) < 300) WATCHDOG_RESET (); - conversion_done = 1; - } - - for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) { - if (t->exec_before) { - t->exec_before(t); - } - - val = t->sysmon->read(t->sysmon, t->addr); - if (val != -1) { - t->val_valid = val >= t->val_min && val <= t->val_max; - t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt; - } else { - t->val_valid = 0; - t->val_valid_alt = 0; - } - - if (t->exec_after) { - t->exec_after(t); - } - - if ((!t->val_valid) || (flags & POST_MANUAL)) { - printf("%-17s = %-10s ", t->name, sysmon_unit_value(t, val)); - printf("allowed range"); - printf(" %-8s ..", sysmon_unit_value(t, t->val_min)); - printf(" %-8s", sysmon_unit_value(t, t->val_max)); - printf(" %s\n", t->val_valid ? "OK" : "FAIL"); - } - - if (!t->val_valid) { - res = -1; - } - } - - return res; -} - -#endif /* CONFIG_POST & CONFIG_SYS_POST_SYSMON */ diff --git a/test/dm/cmd_dm.c b/test/dm/cmd_dm.c index caff49a..a3c5971 100644 --- a/test/dm/cmd_dm.c +++ b/test/dm/cmd_dm.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <command.h> #include <dm.h> #include <malloc.h> #include <mapmem.h> @@ -46,11 +47,25 @@ static cmd_tbl_t test_commands[] = { U_BOOT_CMD_MKENT(devres, 1, 1, do_dm_dump_devres, "", ""), }; +static __maybe_unused void dm_reloc(void) +{ + static int relocated; + + if (!relocated) { + fixup_cmdtable(test_commands, ARRAY_SIZE(test_commands)); + relocated = 1; + } +} + static int do_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { cmd_tbl_t *test_cmd; int ret; +#ifdef CONFIG_NEEDS_MANUAL_RELOC + dm_reloc(); +#endif + if (argc < 2) return CMD_RET_USAGE; test_cmd = find_cmd_tbl(argv[1], test_commands, diff --git a/tools/buildman/README b/tools/buildman/README index 10c7135..66502af 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -156,7 +156,6 @@ aarch64: /opt/linaro/gcc-linaro-aarch64-none-elf-4.8-2013.10_linux [toolchain-alias] x86: i386 blackfin: bfin -sh: sh4 nds32: nds32le openrisc: or32 @@ -341,6 +340,28 @@ Testing - found '/home/sjg/.buildman-toolchains/gcc-4.5.1-nolibc/or32-linux/bin/or32-linux-gcc' Tool chain test: OK +Or download them all from kernel.org and move them to /toolchains directory, + +$ for i in aarch64 arm avr32 i386 m68k microblaze mips or32 powerpc sparc + do + ./tools/buildman/buildman --fetch-arch $i + done +$ sudo mkdir -p /toolchains +$ sudo mv ~/.buildman-toolchains/*/* /toolchains/ + +For those not available from kernel.org, download from the following links. + +arc: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/ + arc_gnu_2015.06_prebuilt_uclibc_le_archs_linux_install.tar.gz +blackfin: http://sourceforge.net/projects/adi-toolchain/files/ + blackfin-toolchain-elf-gcc-4.5-2014R1_45-RC2.x86_64.tar.bz2 +nds32: http://osdk.andestech.com/packages/ + nds32le-linux-glibc-v1.tgz +nios2: http://sourcery.mentor.com/public/gnu_toolchain/nios2-linux-gnu/ + sourceryg++-2015.11-27-nios2-linux-gnu-i686-pc-linux-gnu.tar.bz2 +sh: http://sourcery.mentor.com/public/gnu_toolchain/sh-linux-gnu/ + renesas-4.4-200-sh-linux-gnu-i686-pc-linux-gnu.tar.bz2 + Buildman should now be set up to use your new toolchain. At the time of writing, U-Boot has these architectures: diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index ba11f77..39f7333 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -10,6 +10,7 @@ #define _GNU_SOURCE +#include <compiler.h> #include <errno.h> #include <env_flags.h> #include <fcntl.h> diff --git a/tools/kwbimage.c b/tools/kwbimage.c index 5f6d91c..369aba7 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -232,11 +232,12 @@ static void *image_create_v0(size_t *imagesz, struct image_tool_params *params, main_hdr = image; /* Fill in the main header */ - main_hdr->blocksize = payloadsz + sizeof(uint32_t) - headersz; - main_hdr->srcaddr = headersz; + main_hdr->blocksize = + cpu_to_le32(payloadsz + sizeof(uint32_t) - headersz); + main_hdr->srcaddr = cpu_to_le32(headersz); main_hdr->ext = has_ext; - main_hdr->destaddr = params->addr; - main_hdr->execaddr = params->ep; + main_hdr->destaddr = cpu_to_le32(params->addr); + main_hdr->execaddr = cpu_to_le32(params->ep); e = image_find_option(IMAGE_CFG_BOOT_FROM); if (e) @@ -246,7 +247,7 @@ static void *image_create_v0(size_t *imagesz, struct image_tool_params *params, main_hdr->nandeccmode = e->nandeccmode; e = image_find_option(IMAGE_CFG_NAND_PAGESZ); if (e) - main_hdr->nandpagesize = e->nandpagesz; + main_hdr->nandpagesize = cpu_to_le16(e->nandpagesz); main_hdr->checksum = image_checksum8(image, sizeof(struct main_hdr_v0)); @@ -255,15 +256,17 @@ static void *image_create_v0(size_t *imagesz, struct image_tool_params *params, int cfgi, datai; ext_hdr = image + sizeof(struct main_hdr_v0); - ext_hdr->offset = 0x40; + ext_hdr->offset = cpu_to_le32(0x40); for (cfgi = 0, datai = 0; cfgi < cfgn; cfgi++) { e = &image_cfg[cfgi]; if (e->type != IMAGE_CFG_DATA) continue; - ext_hdr->rcfg[datai].raddr = e->regdata.raddr; - ext_hdr->rcfg[datai].rdata = e->regdata.rdata; + ext_hdr->rcfg[datai].raddr = + cpu_to_le32(e->regdata.raddr); + ext_hdr->rcfg[datai].rdata = + cpu_to_le32(e->regdata.rdata); datai++; } @@ -321,8 +324,9 @@ static size_t image_headersz_v1(struct image_tool_params *params, return 0; } - headersz += s.st_size + - binarye->binary.nargs * sizeof(unsigned int); + headersz += sizeof(struct opt_hdr_v1) + + s.st_size + + (binarye->binary.nargs + 2) * sizeof(uint32_t); if (hasext) *hasext = 1; } @@ -376,12 +380,13 @@ static void *image_create_v1(size_t *imagesz, struct image_tool_params *params, cur += sizeof(struct main_hdr_v1); /* Fill the main header */ - main_hdr->blocksize = payloadsz - headersz + sizeof(uint32_t); - main_hdr->headersz_lsb = headersz & 0xFFFF; + main_hdr->blocksize = + cpu_to_le32(payloadsz - headersz + sizeof(uint32_t)); + main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF); main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16; - main_hdr->destaddr = params->addr; - main_hdr->execaddr = params->ep; - main_hdr->srcaddr = headersz; + main_hdr->destaddr = cpu_to_le32(params->addr); + main_hdr->execaddr = cpu_to_le32(params->ep); + main_hdr->srcaddr = cpu_to_le32(headersz); main_hdr->ext = hasext; main_hdr->version = 1; e = image_find_option(IMAGE_CFG_BOOT_FROM); @@ -397,7 +402,7 @@ static void *image_create_v1(size_t *imagesz, struct image_tool_params *params, binarye = image_find_option(IMAGE_CFG_BINARY); if (binarye) { struct opt_hdr_v1 *hdr = cur; - unsigned int *args; + uint32_t *args; size_t binhdrsz; struct stat s; int argi; @@ -415,7 +420,7 @@ static void *image_create_v1(size_t *imagesz, struct image_tool_params *params, fstat(fileno(bin), &s); binhdrsz = sizeof(struct opt_hdr_v1) + - (binarye->binary.nargs + 1) * sizeof(unsigned int) + + (binarye->binary.nargs + 2) * sizeof(uint32_t) + s.st_size; /* @@ -424,18 +429,18 @@ static void *image_create_v1(size_t *imagesz, struct image_tool_params *params, * next-header byte and 3-byte alignment at the end. */ binhdrsz = ALIGN_SUP(binhdrsz, 4) + 4; - hdr->headersz_lsb = binhdrsz & 0xFFFF; + hdr->headersz_lsb = cpu_to_le16(binhdrsz & 0xFFFF); hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16; cur += sizeof(struct opt_hdr_v1); args = cur; - *args = binarye->binary.nargs; + *args = cpu_to_le32(binarye->binary.nargs); args++; for (argi = 0; argi < binarye->binary.nargs; argi++) - args[argi] = binarye->binary.args[argi]; + args[argi] = cpu_to_le32(binarye->binary.args[argi]); - cur += (binarye->binary.nargs + 1) * sizeof(unsigned int); + cur += (binarye->binary.nargs + 1) * sizeof(uint32_t); ret = fread(cur, s.st_size, 1, bin); if (ret != 1) { @@ -720,7 +725,8 @@ static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd, free(image_cfg); /* Build and add image checksum header */ - checksum = image_checksum32((uint32_t *)ptr, sbuf->st_size); + checksum = + cpu_to_le32(image_checksum32((uint32_t *)ptr, sbuf->st_size)); size = write(ifd, &checksum, sizeof(uint32_t)); if (size != sizeof(uint32_t)) { fprintf(stderr, "Error:%s - Checksum write %d bytes %s\n", @@ -810,7 +816,15 @@ static int kwbimage_generate(struct image_tool_params *params, tparams->header_size = alloc_len; tparams->hdr = hdr; - return 0; + /* + * The resulting image needs to be 4-byte aligned. At least + * the Marvell hdrparser tool complains if its unaligned. + * By returning 1 here in this function, called via + * tparams->vrec_header() in mkimage.c, mkimage will + * automatically pad the the resulting image to a 4-byte + * size if necessary. + */ + return 1; } /* diff --git a/tools/kwbimage.h b/tools/kwbimage.h index 9d2585c..e6e3d1d 100644 --- a/tools/kwbimage.h +++ b/tools/kwbimage.h @@ -9,6 +9,7 @@ #ifndef _KWBIMAGE_H_ #define _KWBIMAGE_H_ +#include <compiler.h> #include <stdint.h> #define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config)) @@ -115,7 +116,7 @@ struct opt_hdr_v1 { #define OPT_HDR_V1_REGISTER_TYPE 0x3 #define KWBHEADER_V1_SIZE(hdr) \ - (((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb) + (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb)) enum kwbimage_cmd { CMD_INVALID, diff --git a/tools/mkimage.c b/tools/mkimage.c index 8af9d50..8f8b6df 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -311,21 +311,25 @@ NXTARG: ; exit (retval); } - dfd = open(params.datafile, O_RDONLY | O_BINARY); - if (dfd < 0) { - fprintf(stderr, "%s: Can't open %s: %s\n", - params.cmdname, params.datafile, strerror(errno)); - exit(EXIT_FAILURE); - } + if ((params.type != IH_TYPE_MULTI) && (params.type != IH_TYPE_SCRIPT)) { + dfd = open(params.datafile, O_RDONLY | O_BINARY); + if (dfd < 0) { + fprintf(stderr, "%s: Can't open %s: %s\n", + params.cmdname, params.datafile, + strerror(errno)); + exit(EXIT_FAILURE); + } - if (fstat(dfd, &sbuf) < 0) { - fprintf(stderr, "%s: Can't stat %s: %s\n", - params.cmdname, params.datafile, strerror(errno)); - exit(EXIT_FAILURE); - } + if (fstat(dfd, &sbuf) < 0) { + fprintf(stderr, "%s: Can't stat %s: %s\n", + params.cmdname, params.datafile, + strerror(errno)); + exit(EXIT_FAILURE); + } - params.file_size = sbuf.st_size + tparams->header_size; - close(dfd); + params.file_size = sbuf.st_size + tparams->header_size; + close(dfd); + } /* * In case there an header with a variable diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 4389622..72621fd 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -25,7 +25,7 @@ enum { * * @signature: Signature (must be RKSD_SIGNATURE) * @disable_rc4: 0 to use rc4 for boot image, 1 to use plain binary - * @code1_offset: Offset in blocks of the SPL code from this header + * @init_offset: Offset in blocks of the SPL code from this header * block. E.g. 4 means 2KB after the start of this header. * Other fields are not used by U-Boot */ @@ -33,38 +33,102 @@ struct header0_info { uint32_t signature; uint8_t reserved[4]; uint32_t disable_rc4; - uint16_t code1_offset; - uint16_t code2_offset; - uint8_t reserved1[490]; - uint16_t usflashdatasize; - uint16_t ucflashbootsize; + uint16_t init_offset; + uint8_t reserved1[492]; + uint16_t init_size; + uint16_t init_boot_size; uint8_t reserved2[2]; }; +/** + * struct spl_info - spl info for each chip + * + * @imagename: Image name(passed by "mkimage -n") + * @spl_hdr: Boot ROM requires a 4-bytes spl header + * @spl_size: Spl size(include extra 4-bytes spl header) + */ +struct spl_info { + const char *imagename; + const char *spl_hdr; + const uint32_t spl_size; +}; + +static struct spl_info spl_infos[] = { + { "rk3036", "RK30", 0x1000 }, + { "rk3288", "RK32", 0x8000 }, +}; + static unsigned char rc4_key[16] = { 124, 78, 3, 4, 85, 5, 9, 7, 45, 44, 123, 56, 23, 13, 23, 17 }; -int rkcommon_set_header(void *buf, uint file_size) +static struct spl_info *rkcommon_get_spl_info(char *imagename) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(spl_infos); i++) + if (!strncmp(imagename, spl_infos[i].imagename, 6)) + return spl_infos + i; + + return NULL; +} + +int rkcommon_check_params(struct image_tool_params *params) +{ + int i; + + if (rkcommon_get_spl_info(params->imagename) != NULL) + return 0; + + fprintf(stderr, "ERROR: imagename (%s) is not supported!\n", + strlen(params->imagename) > 0 ? params->imagename : "NULL"); + + fprintf(stderr, "Available imagename:"); + for (i = 0; i < ARRAY_SIZE(spl_infos); i++) + fprintf(stderr, "\t%s", spl_infos[i].imagename); + fprintf(stderr, "\n"); + + return -1; +} + +const char *rkcommon_get_spl_hdr(struct image_tool_params *params) +{ + struct spl_info *info = rkcommon_get_spl_info(params->imagename); + + /* + * info would not be NULL, because of we checked params before. + */ + return info->spl_hdr; +} + +int rkcommon_get_spl_size(struct image_tool_params *params) +{ + struct spl_info *info = rkcommon_get_spl_info(params->imagename); + + /* + * info would not be NULL, because of we checked params before. + */ + return info->spl_size; +} + +int rkcommon_set_header(void *buf, uint file_size, + struct image_tool_params *params) { struct header0_info *hdr; - if (file_size > RK_MAX_CODE1_SIZE) + if (file_size > rkcommon_get_spl_size(params)) return -ENOSPC; - memset(buf, '\0', RK_CODE1_OFFSET * RK_BLK_SIZE); + memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE); hdr = (struct header0_info *)buf; hdr->signature = RK_SIGNATURE; hdr->disable_rc4 = 1; - hdr->code1_offset = RK_CODE1_OFFSET; - hdr->code2_offset = 8; - - hdr->usflashdatasize = (file_size + RK_BLK_SIZE - 1) / RK_BLK_SIZE; - hdr->usflashdatasize = (hdr->usflashdatasize + 3) & ~3; - hdr->ucflashbootsize = hdr->usflashdatasize; + hdr->init_offset = RK_INIT_OFFSET; - debug("size=%x, %x\n", params->file_size, hdr->usflashdatasize); + hdr->init_size = (file_size + RK_BLK_SIZE - 1) / RK_BLK_SIZE; + hdr->init_size = (hdr->init_size + 3) & ~3; + hdr->init_boot_size = hdr->init_size + RK_MAX_BOOT_SIZE / RK_BLK_SIZE; rc4_encode(buf, RK_BLK_SIZE, rc4_key); diff --git a/tools/rkcommon.h b/tools/rkcommon.h index 57fd726..c69540f 100644 --- a/tools/rkcommon.h +++ b/tools/rkcommon.h @@ -10,11 +10,40 @@ enum { RK_BLK_SIZE = 512, - RK_CODE1_OFFSET = 4, - RK_MAX_CODE1_SIZE = 32 << 10, + RK_INIT_OFFSET = 4, + RK_MAX_BOOT_SIZE = 512 << 10, + RK_SPL_HDR_START = RK_INIT_OFFSET * RK_BLK_SIZE, + RK_SPL_HDR_SIZE = 4, + RK_SPL_START = RK_SPL_HDR_START + RK_SPL_HDR_SIZE, + RK_IMAGE_HEADER_LEN = RK_SPL_START, }; /** + * rkcommon_check_params() - check params + * + * @return 0 if OK, -1 if ERROR. + */ +int rkcommon_check_params(struct image_tool_params *params); + +/** + * rkcommon_get_spl_hdr() - get 4-bytes spl hdr for a Rockchip boot image + * + * Rockchip's bootrom requires the spl loader to start with a 4-bytes + * header. The content of this header depends on the chip type. + */ +const char *rkcommon_get_spl_hdr(struct image_tool_params *params); + +/** + * rkcommon_get_spl_size() - get spl size for a Rockchip boot image + * + * Different chip may have different sram size. And if we want to jump + * back to the bootrom after spl, we may need to reserve some sram space + * for the bootrom. + * The spl loader size should be sram size minus reserved size(if needed) + */ +int rkcommon_get_spl_size(struct image_tool_params *params); + +/** * rkcommon_set_header() - set up the header for a Rockchip boot image * * This sets up a 2KB header which can be interpreted by the Rockchip boot ROM. @@ -23,6 +52,7 @@ enum { * @file_size: Size of the file we want the boot ROM to load, in bytes * @return 0 if OK, -ENOSPC if too large */ -int rkcommon_set_header(void *buf, uint file_size); +int rkcommon_set_header(void *buf, uint file_size, + struct image_tool_params *params); #endif diff --git a/tools/rkimage.c b/tools/rkimage.c index 7b292f4..f9fdcfa 100644 --- a/tools/rkimage.c +++ b/tools/rkimage.c @@ -9,6 +9,7 @@ #include "imagetool.h" #include <image.h> +#include "rkcommon.h" static uint32_t header; @@ -30,7 +31,8 @@ static void rkimage_print_header(const void *buf) static void rkimage_set_header(void *buf, struct stat *sbuf, int ifd, struct image_tool_params *params) { - memcpy(buf, "RK32", 4); + memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params), + RK_SPL_HDR_SIZE); } static int rkimage_extract_subimage(void *buf, struct image_tool_params *params) diff --git a/tools/rksd.c b/tools/rksd.c index a8dbe98..a2baa74 100644 --- a/tools/rksd.c +++ b/tools/rksd.c @@ -13,18 +13,7 @@ #include "mkimage.h" #include "rkcommon.h" -enum { - RKSD_SPL_HDR_START = RK_CODE1_OFFSET * RK_BLK_SIZE, - RKSD_SPL_START = RKSD_SPL_HDR_START + 4, - RKSD_HEADER_LEN = RKSD_SPL_START, -}; - -static char dummy_hdr[RKSD_HEADER_LEN]; - -static int rksd_check_params(struct image_tool_params *params) -{ - return 0; -} +static char dummy_hdr[RK_IMAGE_HEADER_LEN]; static int rksd_verify_header(unsigned char *buf, int size, struct image_tool_params *params) @@ -42,15 +31,16 @@ static void rksd_set_header(void *buf, struct stat *sbuf, int ifd, unsigned int size; int ret; - size = params->file_size - RKSD_SPL_HDR_START; - ret = rkcommon_set_header(buf, size); + size = params->file_size - RK_SPL_HDR_START; + ret = rkcommon_set_header(buf, size, params); if (ret) { /* TODO(sjg@chromium.org): This method should return an error */ printf("Warning: SPL image is too large (size %#x) and will not boot\n", size); } - memcpy(buf + RKSD_SPL_HDR_START, "RK32", 4); + memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params), + RK_SPL_HDR_SIZE); } static int rksd_extract_subimage(void *buf, struct image_tool_params *params) @@ -72,7 +62,7 @@ static int rksd_vrec_header(struct image_tool_params *params, { int pad_size; - pad_size = RKSD_SPL_HDR_START + RK_MAX_CODE1_SIZE; + pad_size = RK_SPL_HDR_START + rkcommon_get_spl_size(params); debug("pad_size %x\n", pad_size); return pad_size - params->file_size; @@ -84,9 +74,9 @@ static int rksd_vrec_header(struct image_tool_params *params, U_BOOT_IMAGE_TYPE( rksd, "Rockchip SD Boot Image support", - RKSD_HEADER_LEN, + RK_IMAGE_HEADER_LEN, dummy_hdr, - rksd_check_params, + rkcommon_check_params, rksd_verify_header, rksd_print_header, rksd_set_header, diff --git a/tools/rkspi.c b/tools/rkspi.c index a3c4c73..800e235 100644 --- a/tools/rkspi.c +++ b/tools/rkspi.c @@ -14,18 +14,10 @@ #include "rkcommon.h" enum { - RKSPI_SPL_HDR_START = RK_CODE1_OFFSET * RK_BLK_SIZE, - RKSPI_SPL_START = RKSPI_SPL_HDR_START + 4, - RKSPI_HEADER_LEN = RKSPI_SPL_START, RKSPI_SECT_LEN = RK_BLK_SIZE * 4, }; -static char dummy_hdr[RKSPI_HEADER_LEN]; - -static int rkspi_check_params(struct image_tool_params *params) -{ - return 0; -} +static char dummy_hdr[RK_IMAGE_HEADER_LEN]; static int rkspi_verify_header(unsigned char *buf, int size, struct image_tool_params *params) @@ -45,7 +37,7 @@ static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd, int ret; size = params->orig_file_size; - ret = rkcommon_set_header(buf, size); + ret = rkcommon_set_header(buf, size, params); debug("size %x\n", size); if (ret) { /* TODO(sjg@chromium.org): This method should return an error */ @@ -53,7 +45,8 @@ static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd, size); } - memcpy(buf + RKSPI_SPL_HDR_START, "RK32", 4); + memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params), + RK_SPL_HDR_SIZE); /* * Spread the image out so we only use the first 2KB of each 4KB @@ -89,12 +82,12 @@ static int rkspi_vrec_header(struct image_tool_params *params, { int pad_size; - pad_size = (RK_MAX_CODE1_SIZE + 0x7ff) / 0x800 * 0x800; + pad_size = (rkcommon_get_spl_size(params) + 0x7ff) / 0x800 * 0x800; params->orig_file_size = pad_size; /* We will double the image size due to the SPI format */ pad_size *= 2; - pad_size += RKSPI_SPL_HDR_START; + pad_size += RK_SPL_HDR_START; debug("pad_size %x\n", pad_size); return pad_size - params->file_size; @@ -106,9 +99,9 @@ static int rkspi_vrec_header(struct image_tool_params *params, U_BOOT_IMAGE_TYPE( rkspi, "Rockchip SPI Boot Image support", - RKSPI_HEADER_LEN, + RK_IMAGE_HEADER_LEN, dummy_hdr, - rkspi_check_params, + rkcommon_check_params, rkspi_verify_header, rkspi_print_header, rkspi_set_header, diff --git a/tools/zynqimage.c b/tools/zynqimage.c index 25f558d..c43bd5d 100644 --- a/tools/zynqimage.c +++ b/tools/zynqimage.c @@ -212,8 +212,7 @@ static int zynqimage_check_params(struct image_tool_params *params) return -1; } - return !((params->lflag || params->dflag) || - (params->dflag && params->eflag)); + return !(params->lflag || params->dflag); } static int zynqimage_check_image_types(uint8_t type) |