diff options
| -rw-r--r-- | arch/x86/cpu/ivybridge/bd82x6x.c | 33 | ||||
| -rw-r--r-- | drivers/pch/pch7.c | 33 | ||||
| -rw-r--r-- | drivers/pch/pch9.c | 33 |
3 files changed, 99 insertions, 0 deletions
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 66a8414..996707b 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -19,6 +19,7 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h> +#define GPIO_BASE 0x48 #define BIOS_CTRL 0xdc static int pch_revision_id = -1; @@ -200,9 +201,41 @@ static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect) return 0; } +static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep) +{ + u32 base; + + /* + * GPIO_BASE moved to its current offset with ICH6, but prior to + * that it was unused (or undocumented). Check that it looks + * okay: not all ones or zeros. + * + * Note we don't need check bit0 here, because the Tunnel Creek + * GPIO base address register bit0 is reserved (read returns 0), + * while on the Ivybridge the bit0 is used to indicate it is an + * I/O space. + */ + dm_pci_read_config32(dev, GPIO_BASE, &base); + if (base == 0x00000000 || base == 0xffffffff) { + debug("%s: unexpected BASE value\n", __func__); + return -ENODEV; + } + + /* + * Okay, I guess we're looking at the right device. The actual + * GPIO registers are in the PCI device's I/O space, starting + * at the offset that we just read. Bit 0 indicates that it's + * an I/O address, not a memory address, so mask that off. + */ + *gbasep = base & 1 ? base & ~3 : base & ~15; + + return 0; +} + static const struct pch_ops bd82x6x_pch_ops = { .get_spi_base = bd82x6x_pch_get_spi_base, .set_spi_protect = bd82x6x_set_spi_protect, + .get_gpio_base = bd82x6x_get_gpio_base, }; static const struct udevice_id bd82x6x_ids[] = { diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c index fe1fb85..302c929 100644 --- a/drivers/pch/pch7.c +++ b/drivers/pch/pch7.c @@ -8,6 +8,7 @@ #include <dm.h> #include <pch.h> +#define GPIO_BASE 0x44 #define BIOS_CTRL 0xd8 static int pch7_get_spi_base(struct udevice *dev, ulong *sbasep) @@ -37,9 +38,41 @@ static int pch7_set_spi_protect(struct udevice *dev, bool protect) return 0; } +static int pch7_get_gpio_base(struct udevice *dev, u32 *gbasep) +{ + u32 base; + + /* + * GPIO_BASE moved to its current offset with ICH6, but prior to + * that it was unused (or undocumented). Check that it looks + * okay: not all ones or zeros. + * + * Note we don't need check bit0 here, because the Tunnel Creek + * GPIO base address register bit0 is reserved (read returns 0), + * while on the Ivybridge the bit0 is used to indicate it is an + * I/O space. + */ + dm_pci_read_config32(dev, GPIO_BASE, &base); + if (base == 0x00000000 || base == 0xffffffff) { + debug("%s: unexpected BASE value\n", __func__); + return -ENODEV; + } + + /* + * Okay, I guess we're looking at the right device. The actual + * GPIO registers are in the PCI device's I/O space, starting + * at the offset that we just read. Bit 0 indicates that it's + * an I/O address, not a memory address, so mask that off. + */ + *gbasep = base & 1 ? base & ~3 : base & ~15; + + return 0; +} + static const struct pch_ops pch7_ops = { .get_spi_base = pch7_get_spi_base, .set_spi_protect = pch7_set_spi_protect, + .get_gpio_base = pch7_get_gpio_base, }; static const struct udevice_id pch7_ids[] = { diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c index 5ac2e8a..2a212ce 100644 --- a/drivers/pch/pch9.c +++ b/drivers/pch/pch9.c @@ -8,6 +8,7 @@ #include <dm.h> #include <pch.h> +#define GPIO_BASE 0x48 #define SBASE_ADDR 0x54 static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep) @@ -20,8 +21,40 @@ static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep) return 0; } +static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep) +{ + u32 base; + + /* + * GPIO_BASE moved to its current offset with ICH6, but prior to + * that it was unused (or undocumented). Check that it looks + * okay: not all ones or zeros. + * + * Note we don't need check bit0 here, because the Tunnel Creek + * GPIO base address register bit0 is reserved (read returns 0), + * while on the Ivybridge the bit0 is used to indicate it is an + * I/O space. + */ + dm_pci_read_config32(dev, GPIO_BASE, &base); + if (base == 0x00000000 || base == 0xffffffff) { + debug("%s: unexpected BASE value\n", __func__); + return -ENODEV; + } + + /* + * Okay, I guess we're looking at the right device. The actual + * GPIO registers are in the PCI device's I/O space, starting + * at the offset that we just read. Bit 0 indicates that it's + * an I/O address, not a memory address, so mask that off. + */ + *gbasep = base & 1 ? base & ~3 : base & ~15; + + return 0; +} + static const struct pch_ops pch9_ops = { .get_spi_base = pch9_get_spi_base, + .get_gpio_base = pch9_get_gpio_base, }; static const struct udevice_id pch9_ids[] = { |